Copyright: Copyright (c) Altera Corporation 1992-1995


Third Party Interfaces Help Contents
Third-Party Interfaces Help Contents

Introduction

EDIF Interface Information

OrCAD Interface Information

Verilog Interface Information

VHDL Interface Information

Xilinx Interface Information


EDIF Interface Information

The following information applies to any third-party CAE tool that can generate an EDIF netlist file and interface with MAX+PLUS II:

Basic Tools

EDIF Input/Output Files (Compiler)

EDIF Command File (.edc)

EDIF Command File Format

EDIF Input File (.edf)

EDIF 2 0 0 Constructs Interpreted by MAX+PLUS II

EDIF 3 0 0 Constructs Interpreted by MAX+PLUS II

Resource Assignments in EDIF Input Files

EDIF Output File (.edo)

Primitives in Simulator Netlist Files & EDIF Output Files

Library Mapping File (.lmf)

Library Mapping File Format

Cadence Concept Library Mapping File (vld_bas.lmf)

Cadence Composer Library Mapping File (vld_bas.lmf)

Mentor Graphics Library Mapping File (mnt8_bas.lmf)

Synopsys Library Mapping File (altsynsm.lmf)

Viewlogic Library Mapping File (vwl_bas.lmf)

Standard Delay Format Output File (.sdo)

VHDL Memory Model Output File (.vmo)

EDIF Modules (Compiler)

EDIF Netlist Reader (See Compiler Netlist Extractor)

EDIF Netlist Writer

Commands

EDIF Netlist Reader Settings (Compiler)

EDIF Netlist Writer (Compiler)

EDIF Netlist Writer Settings (Compiler)

Procedures

Design Entry

Assigning Resources in a Third-Party Design Editor

Preserving Net & Instance Names in EDIF Input Files

Specifying Port Directions in EDIF Input Files

Using MAX+PLUS II Buffer & Expander Primitives in a Third-Party Design Editor

Compilation

Compiling EDIF Input Files

Creating EDIF Output Files

Programming

Configuring a FLEX 8000 Device with the BitBlaster

See also:

Guidelines for Workstation Help Users

Recommended reading:

Cadence & MAX+PLUS II Software Interface Guide

Mentor Graphics & MAX+PLUS II Software Interface Guide

Synopsys & MAX+PLUS II Software Interface Guide

Viewlogic Powerview & MAX+PLUS II Software Interface Guide

AN30 (Viewlogic Workview PLUS & MAX+PLUS II Logic Design)


Verilog Interface Information

The following information applies to any third-party CAE tool that can simulate a Verilog netlist file and interface with MAX+PLUS II:

Basic Tools

Standard Delay Format Output File (.sdo)

Verilog Netlist Writer

Verilog Output File (.vo)

Commands

Verilog Netlist Writer (Compiler)

Verilog Netlist Writer Settings (Compiler)

Procedures

Creating Verilog Output Files

See also:

Guidelines for Workstation Help Users

Recommended reading:

Cadence & MAX+PLUS II Software Interface Guide

AN30 (Viewlogic Workview PLUS & MAX+PLUS II Logic Design)

Mentor Graphics & MAX+PLUS II Software Interface Guide

Synopsys & MAX+PLUS II Software Interface Guide

Viewlogic Powerview & MAX+PLUS II Software Interface Guide


VHDL Interface Information

The following information applies to any third-party CAE tool that can simulate a VHDL netlist file and interface with MAX+PLUS II:

Basic Tools

Standard Delay Format Output File (.sdo)

VHDL Design File (.vhd)

VHDL Netlist Writer

VHDL Output File (.vho)

Commands

VHDL Netlist Writer (Compiler)

VHDL Netlist Writer Settings (Compiler)

Procedures

Compiling VHDL Design Files

Creating VHDL Output Files

See also:

Guidelines for Workstation Help Users

VHDL Help Contents

Recommended reading:

Cadence & MAX+PLUS II Software Interface Guide

Mentor Graphics & MAX+PLUS II Software Interface Guide

Synopsys & MAX+PLUS II Software Interface Guide

Viewlogic Powerview & MAX+PLUS II Software Interface Guide

AN30 (Viewlogic Workview PLUS & MAX+PLUS II Logic Design)


OrCAD Interface Information

The following information applies to compiling OrCAD schematic files with MAX+PLUS II:

Basic Tools

OrCAD Schematic File (.sch)

Guidelines for Working with OrCAD Schematic Files

Restrictions on OrCAD Schematic Files in MAX+PLUS II

OrCAD Library File (.lib)

Library Mapping File (.lmf)

Library Mapping File Format

OrCAD Library Mapping File (orcad.lmf)

Procedures

Compiling OrCAD Schematic Files

See also:

Guidelines for Workstation Help Users


Xilinx Interface Information

The following information applies to compiling XNF Files with MAX+PLUS II:

Basic Tools

Xilinx Netlist Format File (.xnf)

Text Design Export File (.tdx)

Commands

XNF Netlist Reader Settings

Procedures

Compiling XNF Files

See also:

Guidelines for Workstation Help Users


Third-Party Interfaces Introduction
Introduction

The PC- and workstation-based MAX+PLUS II software can interface with almost any industry-standard CAE tool that generates an EDIF 2 0 0 or 3 0 0 netlist file, an OrCAD Schematic File, or an XNF File. You can create a design with a standard CAE tool or with one of the MAX+PLUS II design editors, compile it with the MAX+PLUS II Compiler, and perform timing analysis with the MAX+PLUS II Timing Analyzer. After compilation, you can simulate the design with the MAX+PLUS II Simulator or with a standard simulator, then program the device with Altera programming software and hardware or programming software and hardware from another manufacturer. Show me

How Does the Third-Party Interface Work?

You can create MAX+PLUS II-compatible designs in several ways:

Generate an EDIF netlist file from one of the following types of designs:

-	A schematic design created with an industry-standard CAE tool.

-	A Verilog design created with a standard text editor and processed with a synthesis tool.

-	A VHDL design created with a standard text editor and processed with a synthesis tool.

You must change the EDIF filename extension to .edf so that MAX+PLUS II can read the file as an EDIF Input File.

Generate an OrCAD Schematic File with the OrCAD Draft schematic editor. You can either compile the OrCAD Schematic File directly, or, in the PC-based version of MAX+PLUS II, you can open the OrCAD Schematic File and save it as a GDF that can be compiled with MAX+PLUS II.

Generate an XNF File by running the Xilinx LCA2XNF utility with the -g command-line option.

Create a TDF in AHDL with the MAX+PLUS II Text Editor or any standard text editor.

Create a VHDL Design File with the MAX+PLUS II Text Editor or any standard text editor.

You can then compile the project, which can include one or more EDIF Input Files, XNF Files, OrCAD Schematic Files, VHDL Desiign Files, Graphic Design Files, Waveform Design Files and/or TDFs, with the PC- or workstation-based MAX+PLUS II Compiler. The Compiler’s EDIF Netlist Reader reads EDIF Input Files with the help of Altera-provided or user-defined LMFs that map third-party macrofunctions to MAX+PLUS II macrofunctions. The EDIF Netlist Reader also includes built-in LPM support. The Compiler’s XNF Netlist Reader reads XNF Files automatically. The Compiler reads OrCAD Schematic Files automatically, with the help of the Altera-provided orcad.lmf file that maps OrCAD functions to MAX+PLUS II primitives and macrofunctions.

The Compiler can generate one or more output files for use with other industry-standard design verification tools:

The Compiler’s EDIF Netlist Writer generates an EDIF Output File that contains post-synthesis and -partitioning functional netlist information and optional timing information. The EDIF Netlist Writer can use an optional EDIF Command File to customize the EDIF Output File for a standard EDIF simulator.

The Compiler’s Verilog Netlist Writer generates a Verilog Output File that contains post-synthesis and -partitioning timing information for simulation with a standard Verilog simulator.

The Compiler’s VHDL Netlist Writer generates a VHDL Output File that contains post-synthesis and -partitioning timing information for simulation with a standard VHDL simulator.

The Compiler can also create an optional Standard Delay Format Output File that contains timing delay information for use with VITAL-compatible libraries.

The Compiler also generates a timing SNF for timing analysis with the MAX+PLUS II Timing Analyzer. In addition, it generates one or more programming files that you can use to program devices either with the PC-based MAX+PLUS II Programmer and Altera programming hardware or with programming tools from another manufacturer.

Where to Start

Altera offers a variety of information to help you create designs with industry-standard CAE tools and MAX+PLUS II.

On-Line Help

On-line help provides extensive reference and how-to information on using MAX+PLUS II with industry-standard CAE tools.

Third-Party Interfaces Help Contents provides access to all on-line Third-Party Interfaces Help.

Recommended Reading

Additional publications help you understand the interface between MAX+PLUS II and your third-party CAE tool. The following software interface guides and application notes and briefs are relevant to using a third-party interface:

Cadence & MAX+PLUS II Software Interface Guide

Mentor Graphics & MAX+PLUS II Software Interface Guide

Synopsys & MAX+PLUS II Software Interface Guide

Viewlogic Powerview & MAX+PLUS II Software Interface Guide

AN30 (Viewlogic Workview PLUS & MAX+PLUS II Logic Design)

AB96 (Generating Library Mapping Files)

AB97 (Integrating EDIF Files with AHDL Files in Hierarchical Projects)

AB99 (Design Flow Between Workstations & PCs)

See also:

Compiler Introduction

Guidelines for Workstation Help Users

How to Use MAX+PLUS II Help

Timing Analyzer Introduction


Third-Party/EDIF Interfaces


EDIF Command File--Context-Sensitive Help
EDIF Command File Context-Sensitive Help

Context-sensitive help is available for the following EDIF Command File keywords:

ALIAS

CELL

FILENAME

KEYWORDLEVEL

LOGICVALUE

PROPERTY

See also:

EDIF Command File Format

Getting Context-Sensitive Help


ALIAS Command (EDIF Command File)

The ALIAS command specifies an alias for an EDIF keyword. Aliases may only be used with EDIF keyword level 1, and they cannot be EDIF keywords or previously-defined aliases.

The ALIAS command has the following BNF syntax:

ALIAS <EDIF name> <user name>

See also:

EDIF Command File Format


CELL Command (EDIF Command File)

The CELL command renames a cell in an EDIF Output File to <user name>.

The CELL command has the following BNF syntax:

CELL <MAX+PLUS II name> <user name>

See also:

EDIF Command File Format


FILENAME Command (EDIF Command File)

The FILENAME command specifies an internal filename for EDIF Output File(s) as <user name> . The internal filename, which cannot have an extension, follows the EDIF keyword in EDIF Output Files. The default filename is the project name.

The FILENAME command has the following BNF syntax:

Filename <user name>

See also:

EDIF Command File Format


KEYWORDLEVEL Command (EDIF Command File)

The KEYWORDLEVEL command specifies the EDIF keyword level as 0 or 1. Level 1 allows keyword aliases; with level 0, keywords must be explicitly stated. The default keyword level is 0.

The KEYWORDLEVEL command has the following BNF syntax:

KEYWORDLEVEL <level>

<level>::= 0 | 1

See also:

EDIF Command File Format


LOGICVALUE Command (EDIF Command File)

The LOGICVALUE command renames a logic level in EDIF Output File(s) to <user name>. The following logic levels are available:

Character:	Logic Level:

L	Logic low

H	Logic high

X	Undefined/Don’t Care

Z	High impedance (no input to pin)

The LOGICVALUE command has the following BNF syntax:

LOGICVALUE <MAX+PLUS II name> <user name>

See also:

EDIF Command File Format


PROPERTY Command (EDIF Command File)

The PROPERTY command renames a property construct in EDIF Output File(s) to <user name>. Default property names are assigned to the following EDIF cells in EDIF Output Files:

Property Name & Delay Type:	EDIF Cells:

TPD	general propagation delay	AND, DELAY, NAND, NOT, OR, XOR

TREG	Clock active edge to output	DFF, DFFE, LATCH

TRSU	register setup time, Clock	DFF, LATCH

TRSU	register setup time, Clock & Output Enable	DFFE

TRH 	register hold time, Clock	DFF, LATCH

TRH	register hold time, Clock & Output Enable	DFFE

TRPR	Preset to output	DFF, DFFE

TRCL	Clear to output	DFF, DFFE

TTRI	through tri-state	TRI

TTXZ	disable time, Output Enable to output tri-state	TRI

TTZX	enable time, Output Enable to output high or low	TRI

TPHI	Minimum duration for a high pulse	FILTER

TPLO	Minimum duration for a low pulse	FILTER

TPRISE	Interim delay before rising edge signal appears on the output	RISEFALL

TPFALL	Interim delay before falling edge signal appears on the output	RISEFALL

The PROPERTY command has the following BNF syntax:

PROPERTY <MAX+PLUS II name> <user name>

See also:

EDIF Command File Format


Example: MAX+PLUS II name
<MAX+PLUS II name> is the MAX+PLUS II name for the property name. It is an EDIF identifier, as defined by the EDIF 2 0 0 and 3 0 0 standards.


Example: EDIF Name
<EDIF name> is the EDIF-defined or default name for a particular construct. It is a legal EDIF identifier, as defined by the EDIF 2 0 0 and 3 0 0 standards.


Example: user name
<user name> is the user-specified name for a particular EDIF construct. It must be a legal EDIF identifier, as defined by the EDIF 2 0 0 and 3 0 0 standards.


EDIF 2 0 0 Constructs Interpreted by MAX+PLUS II (Compiler)
EDIF 2 0 0 Constructs Interpreted by MAX+PLUS II

The following EDIF 2 0 0 constructs are interpreted by the MAX+PLUS II Compiler when you compile an EDIF Input File:

cell	keywordLevel

cellRef	keywordMap

cellType	library

contents	libraryRef

design	name

direction	net

edif	numberDefinition

edifLevel	port

edifVersion	portArray

external	portRef

globalPortRef	property

instance	rename

instanceRef	string

integerDisplay	stringDisplay

integerToken	technology

interface	view

joined	viewRef

keywordAlias	viewType

See also:

EDIF 3 0 0 Constructs Interpreted by MAX+PLUS II


EDIF 3 0 0 Constructs Interpreted by MAX+PLUS II (Compiler)
EDIF 3 0 0 Constructs Interpreted by MAX+PLUS II

The following EDIF 3 0 0 constructs are interpreted by the MAX+PLUS II Compiler when you compile an EDIF Input File:

bidirectionalPort	k1KeywordLevel

boolean	k2KeywordLevel

cell	k3KeywordLevel

cellHeader	keywordMap

cellRef	library

cluster	libraryHeader

clusterHeader	libraryNameCaseSensitive

clusterNameCaseSensitive	libraryObjectNameCaseSensitive

clusterRef	libraryRef

connectivityStructure	logicalConnectivity

connectivityUnits	nameCaseSensitivity

connectivityView	nameInformation

connectivityViewHeader	number

design	outputPort

designHeader	physicalDefaults

designNameCaseSensitive	physicalScaling

designUnits	port

edif	portBundle

edifHeader	portInstanceRef

edifLevel	portList

edifVersion	portNameCaseSensitive

external	portRef

false	primaryName

globalPort	property

globalPortBundle	propertyNameCaseSensitive

globalPortDefinitions	signal

globalPortList	signalGroup

globalPortNameCaseSensitive	signalGroupRef

globalPortRef	signalJoined

inputPort	signalList

instance	signalNameCaseSensitive

instanceNameCaseSensitive	string

instanceRef	technology

integer	true

interface	unitDefinitions

interfaceUnits	unitRef

interconnectHeader	unspecifiedDirectionPort

interconnectNameCaseSensitive	untyped

k0KeywordLevel	viewNameCaseSensitive

See also:

EDIF 2 0 0 Constructs Interpreted by MAX+PLUS II


Resource Assignments in EDIF Input Files

You can enter the following types of resource assignments in your source schematic design files before you convert them to EDIF Input Files for the MAX+PLUS II Compiler:

Chips	Cliques

Pins	Logic Options

Logic Cells

Be sure to refer to Guidelines for Working with Assignments for absolutely essential information on using all types of resource and device assignments.

All resource assignments appear in EDIF Input Files as property constructs. Values of the resource assignment appear as string values within the property construct. Example

See also:

Assigning Resources in a Third-Party Design Editor

Example: Resource Assignments in EDIF 2 0 0 Input Files

Example: Resource Assignments in EDIF 3 0 0 Input Files

Recommended reading:

Cadence & MAX+PLUS II Software Interface Guide

Mentor Graphics & MAX+PLUS II Software Interface Guide

Viewlogic Powerview & MAX+PLUS II Software Interface Guide

AN30 (Viewlogic Workview PLUS & MAX+PLUS II Logic Design)


Primitives in Simulator Netlist Files & EDIF Output Files (Compiler)
Primitives in Simulator Netlist Files & EDIF Output Files

Names and descriptions of primitives that are included in functional SNFs, timing SNFs, and linked SNFs are provided below. The primitives that appear in timing SNFs are also used in EDIF Output Files.

Primitive: Note 1	SNF: Note 2	Inputs:	Output:	Description:

ANDn (1<=n<=128)	T,F	&16 ...&(n+1)	&1	Logical AND

NANDn (1<=n<=128)	T,F	&2  ...&(n+1)	&1	Logical NAND

ORn (1<=n<=8)	T,F	&16 ...&(n+1)	&1	Logical OR

NOT	T,F	&2	&1	Logical NOT

XOR2	T,F	&2, &3	&1	Logical XOR

DELAY	T,F	&2	&1	Delay

TRI	T,F	&2, OE	&1	Tri-state

LATCH	T,F	D, CLRN, PRN	Q	Latch

DFF	T,F	D, CLRN, PRN, CLK	Q	D flipflop

DFFE	T,F	D, CLRN, PRN, CLK, ENA	Q	D flipflop with Clock Enable

JKFF	F	J, K, CLRN, PRN, CLK	Q	JK flipflop

JKFFE	F	J, K, CLRN, PRN, CLK, ENA	Q	JK flipflop with Clock Enable

NORn (1<=n<=128)	F	&2 ...&(n+1)	&1	Logical NOR

XNOR2	F	&2, &3	&1	Logical XNOR

FILTER	T	&2	&1	Checks pulse width

RISEFALL	T	&2	&1	Models rise & fall behavior

OPNDRN	T,F	&1	&1	Similar to tri-state

See also:

Creating EDIF Output Files

Library Mapping File Format


Note 1

Primitives in EDIF Output Files may differ from standard MAX+PLUS II primtives, specifically, the available AND, NAND, OR, XOR2, and XNOR2 primitives may be different.


Note 2

T = timing SNF; F = functional SNF

All of these primitives can be included in a linked SNF, since a linked SNF can contain both timing and functional information.


Library Mapping File Syntax

LMFs have the following BNF syntax:

LIBRARY <library name>

{ BEGIN

FUNCTION <MAX+PLUS II function> (<MAX+PLUS II IN1>, <MAX+PLUS II IN2>, ..., <MAX+PLUS II INn>)

RETURNS ( <MAX+PLUS I OUT1>, <MAX+PLUS IIOUT2>, ..., <MAX+II OUTn>)

FUNCTION "<workstation function>" ("<workstation IN1>", "<workstation IN2>", ..., "<workstation INn>")

RETURNS ("<workstation OUT1>", "<workstation OUT2>", ..., "<workstation OUTn>")

END }

See also:

Library Mapping File Format

Mapping Unequal Numbers of Inputs & Outputs

MAX+PLUS II Function Variables

Workstation Function Variables

Recommended reading:

AB96 (Generating Library Mapping Files)


LMF Library Name
<library name> is the user-specified name of the LMF.


LMF MAX+PLUS II function name
<MAX+PLUS II function> is the MAX+PLUS II primitive or macrofunction name.


LMF MAX+PLUS II primitive or macrofunction input port
<MAX+PLUS II IN> is the MAX+PLUS II primitive or macrofunction input pin name. The LMF includes a list of all macrofunction input pin names, enclosed in parentheses.


LMF MAX+PLUS II primitive or macrofunction output port
<MAX+PLUS II OUT> is the MAX+PLUS II primitive or macrofunction output or bidirectional pin name. The LMF includes a list of all macrofunction output pin names, enclosed in parentheses.


LMF third-party function name
<workstation function> is the third-party function name, which must be enclosed in double quotation marks (").


LMF third-party function’s input port name
<workstation IN> is the third-party function’s input port name, which must be enclosed in double quotation marks (").


LMF third-party functions output port name
<workstation OUT> is the third-party function’s output or bidirectional port name, which must be enclosed in double quotation marks (").


Mapping Unequal Numbers of Inputs & Outputs (EDIF)
Mapping Unequal Numbers of Inputs & Outputs

If an EDIF cell generated from a third-party design tool function contains more inputs than a MAX+PLUS II primitive or macrofunction, the Compiler ignores the extra ports and issues a warning message. Also, if an EDIF cell contains more outputs than the equivalent MAX+PLUS II function, and the extra EDIF output signal(s) feeds another function, a warning message is issued.

However, if a MAX+PLUS II function has more or fewer ports than an equivalent third-party function, you can make the following modifications to the appropriate Library Mapping File:

If there are more Altera input pins than EDIF input ports, map the extra Altera input pins to VCC or GND to make them inactive. Be careful to choose intelligent default values. Example

If there are fewer Altera input pins than EDIF input ports, insert an extra comma at the end of the Altera macrofunction input list for each of the EDIF input ports that cannot be mapped to the Altera macrofunction. Example

If there are more Altera output pins than EDIF output ports, the RETURNS section for the EDIF function must contain an extra comma (,) and double quotation marks for each of the unmapped outputs in the Altera macrofunction. Example

If there are fewer Altera output pins than EDIF output ports, the RETURNS section for the Altera macrofunction must contain commas for each of the EDIF ports that do not map to an Altera macrofunction port. Example

See also:

Library Mapping File Format

Library Mapping File Syntax

Recommended reading:

AB96 (Generating Library Mapping Files)


Example: More input pins than EDIF input ports

In this example, the active-low PRN pin of the Altera DFF primitive must be driven by VCC to become inactive. The placeholder is the global-high or global-low signal defined by the CAE tool.

BEGIN

FUNCTION	dff	(CLRN, CLK, D, PRN)

RETURNS	(Q)

FUNCTION	"LS174"	("-CL", "CLOCK", "D<0>", "VCC")

RETURNS	("Q<0>")

END


Example: Fewer input pins than EDIF input ports

In this example, only the A<0> and B<0> ports of the LS21 function are mapped onto the AND2 primitive. The C<0> and D<0> ports must not be driven by signals within the EDIF Input File; if they are, the Compiler reports that the signal driving the unmapped pin is a node without a destination.

BEGIN

FUNCTION	and2	(IN1, IN2, , )

RETURNS	(OUT)

FUNCTION	"LS21"	("A<0>", "B<0>", "C<0>", "D<0>")

RETURNS	("Y<0>")

END


Example: More output pins than EDIF output ports

In this example, the Compiler automatically removes the Q1 and Q2 outputs of the customized BILL macrofunction and all logic within the BILL macrofunction required to generate these outputs.

BEGIN

FUNCTION 	bill 	(CLRN, BOG, V, PRTY)

RETURNS 	(Q0, Q1, Q2)

FUNCTION	"TED"	("-CL", "-BGS", "Z", "-PRTY")

RETURNS 	("Q0", "", "")

END


Example: Fewer output pins than EDIF output ports

In this example, if the -Q<0> port drives a net within the EDIF netlist, the MAX+PLUS II Compiler generates a warning because no source pin is driving the net.

BEGIN

FUNCTION	dff 	(CLRN, CLK, D, PRN)

RETURNS 	( ,Q)

FUNCTION	"LS74"	("-CL", "CLOCK", "D<0>", "-PR")

RETURNS 	("-Q<0>", "Q<0>")

END


MAX+PLUS II Function Variables (Library Mapping File)

MAX+PLUS II functions that are mapped in Library Mapping Files can be either Altera-provided or user-created. A user-created macrofunction can have a filename with up to eight name characters, and its input and output port names must have legal name characters.

Recommended reading:

AB96 (Generating Library Mapping Files)


Workstation Function Variables (Library Mapping File)

Workstation function and port names are the original names given to cells and ports. If a design is converted to an EDIF Input File, these original names can change in one of two ways:

The original name can be changed with the EDIF rename construct in the EDIF netlist file when the design is converted.

For example, you may have a function called foo$, which is an illegal EDIF identifier. This function would be renamed to cell foodollar when the design is converted to EDIF. This cell would appear as follows:

(cell (rename foodollar "foo$")...

In this case, you should use the name "foo$" to map the function in a Library Mapping File. In addition, you must ensure that the workstation EDIF netlist writer generates the rename construct when it renames cells and ports.

The original workstation name might be automatically renamed when the design is converted, rather than being explicitly renamed with the rename construct.

Some EDIF netlist writers may automatically append an ampersand (&) to the beginning of an illegal function name to make the name legal. Remember, however, that you must still use the function’s original name (without the &) when mapping it to an Altera macrofunction in an LMF.

For example, if you have a function called 74185, which is an illegal EDIF identifier, the function might be automatically renamed to EDIF cell &74185 when the design is converted to EDIF. This cell would then appear as follows:

(cell &74185...

The function must appear as "74185" in an LMF.

Recommended reading:

AB96 (Generating Library Mapping Files)

AB97 (Integrating EDIF Files with AHDL Files in Hierarchical Projects)


Example: Resource Assignments in EDIF 2 0 0 Input Files (EDIF)
Example: Resource Assignments in EDIF 2 0 0 Input Files

The following example shows excerpts from an EDIF 2 0 0 EDIF Input File that makes resource assignments. The top-level cell is eseradd.

(edif

  (rename eseraddedif "eseradd.edif")

  (edifVersion 2 0 0)

  (edifLevel 0)

  (keywordMap

    (keywordLevel 0))

  (status

    (written

      (timestamp 1991 9 30 6 14 34)

     (author "Altera")

      (program "edif"

        (version "%37%"))

     (dataorigin "Altera")))

           .

           .

           .

  (library

     (rename eseraddwrk "eseradd.wrk")

    (edifLevel 0)

    (technology

      (numberDefinition))

           .

           .

           .

    (cell FULLADD

      (cellType GENERIC)

      (view netlist

        (viewType NETLIST)

        (interface

           .

           .

           .

          (port SUM

            (direction output))

           .

           .

           .

           )

        (contents

           .

           .

           .

         (instance

            (rename &1 "7P_1.7P")

            (viewRef netlist

              (cellRef HALFADD))

          (comment "Logic cell and chip assignment information will be associated with all cells that make up this instance of halfadd.")

          (comment "The following assignment information will be extracted.")

            (property CHIP_PIN_LC

              (string "chipa@lc1"))

            (property CLIQUE

              (string "fast"))

            (property TURBO

              (string "on"))

            (property LOGIC_OPTION

              (string "parallel_expanders=on,xor_synthesis=default")))

           .

           .

           .

          (net

            (rename SUM "SUM")

            (joined

              (portRef S

                (instanceRef &1))

              (portRef SUM))

          (comment "Pin assignment information will be associated with all cells that make up this instance of sum.")

          (comment "The following assignment information will be ignored, because ESERADD is the top level cell.")

            (property CHIP_PIN_LC

              (string "chipa@20")))

           .

           .

           .

           )))

           .

           .

           .

    (cell ESERADD

      (cellType GENERIC)

      (view netlist

        (viewType NETLIST)

        (interface

           .

           .

           .

          (port SERSUM

            (direction output))

           .

           .

           .

            )

        (contents

           .

           .

           .

          (instance

            (rename &2 "1P_1.1P")

            (viewRef netlist

              (cellRef FULLADD))

          (comment "Assignment information will be associated with all cells that make up this instance of fulladd.")

          (comment "The following assignment information will be extracted.")

            (property CHIP_PIN_LC

              (string "chipa@lc4"))

            (property CLIQUE

              (string "fast"))

            (property LOGIC_OPTION

              (string "turbo=on,parallel_expanders=off,xor_synthesis=off")))

           .

           .

           .

          (net

            (rename SERSUM "SERSUM")

            (joined

              (portRef SUM

                (instanceRef &2)))

          (comment "Pin assignment information will be extracted only from external nets of the top level cell.")

          (comment "The following assignment information will be extracted, because ESERADD is the top level cell.")

            (property CHIP_PIN_LC

              (string "chipa@30")))

           .

           .

           .

            ))))

  (design Top

    (cellRef ESERADD

      (libraryRef eseraddwrk))))

See also:

Assigning Resources in a Third-Party Design Editor

Clique Assignments

Logic Option Assignments

Pin, Logic Cell & Chip Assignments

Resource Assignments in EDIF Input Files

Recommended reading:

Cadence & MAX+PLUS II Software Interface Guide

AN30 (Viewlogic Workview PLUS & MAX+PLUS II Logic Design)

Mentor Graphics & MAX+PLUS II Software Interface Guide

Viewlogic Powerview & MAX+PLUS II Software Interface Guide


Example: Resource Assignments in EDIF 2 9 0 Input Files (EDIF)
Example: Resource Assignments in EDIF 3 0 0 Input Files

The following example shows excerpts from an EDIF 3 0 0 EDIF Input File that makes resource assignments.

(edif eseraddedif

  (edifVersion 3 0 0)

  (edifHeader

    (edifLevel 0)

    (keywordMap

      (k0KeywordLevel))

    (status

      (written

        (timeStamp

          (date 1993 6 27)

          (time 15 15 0))

        (program "edif"

          (version "%37%"))

        (dataOrigin "Altera")))

    (nameInformation

        (primaryName "eseradd.edif")))

           .

           .

           .

  (library eseraddwrk

    (libraryHeader

      (edifLevel 0)

      (nameCaseSensitivity)

      (technology

        (numberDefinition

          (unitDefinitions))))

           .

           .

           .

    (cell FULLADD

      (cellHeader)

      (cluster cluster1

        (interface

          (interfaceUnits)

           .

           .

           .

          (port SUM

            (outputPort))

           .

           .

           .

           )

        (clusterHeader)

        (connectivityView view1

          (connectivityViewHeader

            (connectivityUnits))

          (logicalConnectivity

           .

           .

           .

            (instance &1

              (clusterRef cluster1

                (cellRef HALFADD))

          (comment "Logic cell and chip assignment information will be associated with all cells that make up this instance of halfadd.")

          (comment "The following assignment information will be extracted.")

              (property CHIP_PIN_LC

                (string "chipa@lc1"))

              (property CLIQUE

                (string "fast"))

              (property TURBO

                (string "on"))

              (property LOGIC_OPTION

                (string "parallel_expanders=on,xor_synthesis=default")))

           .

           .

           .

            (signal SUM

              (signalJoined

                (portRef S

                  (instanceRef &1))

                (portRef SUM))

          (comment "Pin assignment information will be associated with all cells that make up this instance of sum.")

          (comment "The following assignment information will be ignored, because ESERADD is the top level cell.")

            (property CHIP_PIN_LC

              (string "chipa@20")))

           .

           .

           .

           )

          (connectivityStructure))))

           .

           .

           .

    (cell ESERADD

      (cellHeader)

      (cluster cluster1

        (interface

          (interfaceUnits)

           .

           .

           .

          (port SERSUM

            (outputPort))

           .

           .

           .

           )

        (clusterHeader)

        (connectivityView view1

          (connectivityViewHeader

            (connectivityUnits))

          (logicalConnectivity

           .

           .

           .

            (instance &2

              (clusterRef cluster1

                (cellRef FULLADD))

          (comment "Assignment information will be associated with all cells that make up this instance of fulladd.")

          (comment "The following assignment information will be extracted.")

              (property CHIP_PIN_LC

                (string "chipa@lc4"))

              (property CLIQUE

                (string "fast"))

              (property LOGIC_OPTION

                (string "turbo=on,parallel_expanders=off,xor_synthesis=off")))

           .

           .

           .

            (signal SERSUM

              (signalJoined

                (portRef SUM

                  (instanceRef &2))

                (portRef SUM))

          (comment "Pin assignment information will be extracted only from external nets of the top level cell.")

          (comment "The following assignment information will be extracted, because ESERADD is the top level cell.")

            (property CHIP_PIN_LC

              (string "chipa@30")))

           .

           .

           .

           )

          (connectivityStructure)))))

  (design Top

    (cellRef ESERADD

      (libraryRef eseraddwrk))

    (designHeader

      (designUnits))))

See also:

Assigning Resources in a Third-Party Design Editor

Chip Assignments

Clique Assignments

Logic Option Assignments

Logic Cell Assignments

Pin Assignments

Resource Assignments in EDIF Input Files

Recommended reading:

Cadence & MAX+PLUS II Software Interface Guide

AN30 (Viewlogic Workview PLUS & MAX+PLUS II Logic Design)

Mentor Graphics & MAX+PLUS II Software Interface Guide

Viewlogic Powerview & MAX+PLUS II Software Interface Guide


Assigning Resources in a Third-Party Design Editor (EDIF)
Assigning Resources in a Third-Party Design Editor

You can specify resource assignments in your source schematic design files before you convert them to EDIF Input Files for the MAX+PLUS II Compiler.

Be sure to refer to Guidelines for Working with Assignments for absolutely essential information on using all types of resource assignments.

You can enter resource assignments as properties or attributes in your schematic design editor. Refer to the documentation for your schematic design editor for information on entering properties or attributes.

Assignments are entered with the following properties or attributes:

Property/Attribute Name:	Action:

CHIP_PIN_LC	Assigns chips, pins, and logic cells in third-party design editors. Use the modified assignment syntax for pin, logic cell, and pin assignments.

CLIQUE	Assigns cliques in third-party design editors.

LOGIC_OPTION	Assigns logic options in third-party design editors. Use the modified assignment syntax for logic option assignments.

All resource assignments appear in the EDIF Input Files as property constructs. Values of the resource assignment appear as string values within the property construct. Example

See also:

Example: Resource Assignments in EDIF 2 0 0 Input Files

Example: Resource Assignments in EDIF 3 0 0 Input Files

Resource Assignments in EDIF Input Files

Recommended reading:

Cadence & MAX+PLUS II Software Interface Guide

AN30 (Viewlogic Workview PLUS & MAX+PLUS II Logic Design)

Mentor Graphics & MAX+PLUS II Software Interface Guide

Viewlogic Powerview & MAX+PLUS II Software Interface Guide


A chip assignment might appear as follows:

(property CHIP_PIN_LC

   (string "chipa@lc10"))


Preserving Net & Instance Names in EDIF Input Files (EDIF)
Preserving Net & Instance Names in EDIF Input Files

In all cases, instance names are preserved through compilation with MAX+PLUS II. In the following cases, net names can be preserved through compilation:

net drives an external output and the net and pin names are the same.

net is driven by an external input and the net and pin names are the same.

net is driven by a hard logic function (in projects compiled with multi-level synthesis, some additional logic functions may be preserved)

You can preserve net and instance names in EDIF Input Files by ensuring that you adhere to the following MAX+PLUS II naming conventions in the source design files:

Do not use more than 32 name characters for a net name or more than 8 name characters for an instance name.

Use only name characters that are supported by MAX+PLUS II.

Nets must use the same name as the port symbols that drive them.

See also:

Pin & Node Names


Specifying Port Directions in EDIF Input Files (EDIF)
Specifying Port Directions in EDIF Input Files

Port directions (INPUT, OUTPUT, or INOUT) must be present and specified for all port definitions in the interface section for each cell in an EDIF Input File. Ports with unspecified directions are assumed to be inputs.

See also:

Preserving Net & Instance Names in EDIF Input Files


Using MAX+PLUS II Buffer & Expander Primitives in a Third-Party Design Editor (EDIF)
Using MAX+PLUS II Buffer & Expander Primitives in a Third-Party Design Editor

Most industry-standard CAE tools have equivalents for only some of the special MAX+PLUS II buffer and expander primitives (which include EXP and the LCELL, GLOBAL, SOFT, CARRY, and CASCADE buffers).

If you want to use one of these primitives, but your CAE tool has no equivalent for it:

1.	Create the function with your CAE tool.

2.	Map it to the corresponding MAX+PLUS II primitive in a Library Mapping File.

See also:

Library Mapping File Format

Recommended reading:

AB96 (Generating Library Mapping Files)


File Structure Requirements for XNF Files

Xilinx Netlist Format Files that are compiled with MAX+PLUS II must be generated by running the Xilinx LCA2XNF utility. (For version 4.0 of XACT software, you must use the -g command-line option; for version 5.0, you must use the command-line options -g -v.)

You do not need to route a Xilinx design file and fit it into a Xilinx device before generating an XNF File to be compiled with MAX+PLUS II.

MAX+PLUS II does not support the following features in XNF Files:

Internal oscillator nets in the XC2000 and XC3000 devices. If the XNF Netlist Reader encounters an internal oscillator net in the XNF File, it routes the oscillator net from a pin and the Compiler issues a warning.

Programmable pull-up or pull-down resistors on input and tri-stated pins. If the XNF Netlist Reader encounters pin pull-ups or pull-downs, the Compiler will give a warning.

RAM or ROM in the XC4000 device family. If the XNF File contains RAM or ROM, the compilation is aborted.

Output slew-rate control. The Compiler ignores this feature.

Programmable register power-on state. If the XNF File contains a flipflop that is set (i.e., to logic 1) or reset during power-on, the Compiler issues a warning.

See also:

Compiling Xilinx Netlist Format Files


Restrictions on OrCAD Schematic Files in MAX+PLUS II

You can save OrCAD Schematic Files as Graphic Design Files and vice versa. When you open or save an OrCAD Schematic File, MAX+PLUS II retains as much information as possible from the original file, but some information is lost.

Refer to Guidelines for Working with OrCAD Schematic Files for important information on working with OrCAD Schematic Files.

How the Graphic Editor Opens & Saves OrCAD Schematic Files

The Graphic Editor changes OrCAD Schematic Files in the following ways:

The Graphic Editor can edit and save OrCAD Schematic Files. You can open and edit both 16-bit or 32-bit OrCAD Schematic Files. By default, the Graphic Editor saves OrCAD files in 16-bit format. If you wish to save files in 32-bit format instead, you must add the following line to the [system] section of your maxplus2.ini File:

GIO_WRITE_32_BIT_ORCAD=ON

All types of power objects are displayed as VCC primitives and are saved as bar power objects with the name VCC.

The pinstub types oc, pas, hiz, and oe on OrCAD parts are displayed and saved as output pinstubs.

MAX+PLUS II pin symbols are saved as OrCAD module ports. Because OrCAD Schematic Files do not support vertical ports, the pins are rotated horizontally with their origins adjusted so the pinstub remains in the same place.

When only short pinstubs are used on one side of a part, all pinstubs appear as short pinstubs. When a combination of short and normal pinstubs are used on one side of a part, all pinstubs appear as normal pinstubs.

Only Input, Output, and Bidirectional module ports are supported. The Unspecified module port is ignored.

OrCAD sheets, OrCAD parts, and MAX+PLUS II symbols are saved as parts. MAXPLUS II uses an OrCAD Library File (.lib) with an acceptable description if it exists. If not, MAX+PLUS II creates a new OrCAD Library File called <filename>.lib. The new OrCAD Library File contains descriptions of all parts that do not exist in other OrCAD Library Files. The OrCAD Library File descriptions generated by MAX+PLUS II consist of block parts, i.e., rectangles with pins, and do not contain graphical information. To minimize the number of times a new OrCAD Library File is generated, MAX+PLUS II checks existing OrCAD Library Files for all parts. If a part is found, MAX+PLUS II compares the pin layout to the part in the Graphic Editor to ensure that connectivity is preserved.

Before you open or compile an OrCAD Schematic File project in MAX+PLUS II, Altera recommends that you create a single OrCAD Library File that contains descriptions of all the symbols in the project. You should copy this file to the project directory or specify the directory that contains the OrCAD Library File as a user library with User Libraries (Options menu).

The MAX+PLUS II Compiler automatically compiles OrCAD Schematic Files. MAX+PLUS II supports most functions in the OrCAD Library Files pldgates.lib and ttl.lib.

Features Not Supported in MAX+PLUS II:

In addition to the changes noted above, MAX+PLUS II does not support and ignores the following OrCAD Schematic File characteristics:

Jump, cursor, and zoom level information

Title block information

Sheet name information

The pin types pwr and Unspecified

MAX+PLUS II ignores the following part information:

-	Reference strings

-	Value strings

-	Part data in fields 1 through 8

-	Sheet path name

-	Instance-specific text location information

-	Converted parts

-	Pin numbers

-	Fill areas

-	Part numbers

You should not enter probe, clique, logic cell, logic options, timing, and device assignments in OrCAD Schematic Files with the Assign menu commands, i.e., Probe, Pin/Location/Chip, Clique, Logic Options, Timing Requirements, and Device. Assignments entered with these commands must be identified by net (symbol) ID numbers, which do not exist in OrCAD Schematic Files. In addition, you can enter pin and chip assignments only on pin primitives with the Pin/Location/Chip command or with the Floorplan Editor. If you save an OrCAD Schematic File as a GDF, you can enter resource and device assignments with Assign menu commands in the GDF. Otherwise, you must enter all types of resource and device assignments only in a separate ACF with the same filename as the top-level OrCAD Schematic File.

You should not use the Edit Ports/Parameters dialog box (Symbol menu) to edit instance-specific parameter settings in OrCAD Schematic Files if you plan to save the file as a GDF later. When you save an OrCAD Schematic File as a GDF, these instance-specific parameter settings are not preserved.

See also:

Compiling OrCAD Schematic Files

Guidelines for Working with Assignments

Saving a File


Guidelines for Working with OrCAD Schematic Files

The following guidelines will help you use OrCAD Schematic Files effectively in MAX+PLUS II:

Altera strongly recommends that you save OrCAD Schematic Files as GDFs and edit the GDFs in MAX+PLUS II. If you do not wish to save your OrCAD Schematic Files as GDFs, you should enter all edits to your files with OrCAD. If you import an OrCAD Schematic File into MAX+PLUS II, you should save the file as a GDF and enter all subsequent edits with the Graphic Editor only. You should only save an OrCAD Schematic File in the Graphic Editor if you have made very minor connectivity-related edits such as moving lines or symbols.

Altera recommends saving OrCAD Schematic Files as GDFs for the following reasons:

-	Some OrCAD-specific information is lost when you save an OrCAD Schematic File in the Graphic Editor. See Restrictions on OrCAD Schematic Files in MAX+PLUS II for details.

-	If you enter MAX+PLUS II symbols in an OrCAD Schematic File from within the Graphic Editor, descriptions of these symbols are saved in an OrCAD Library File called <filename>.lib unless an acceptable description of the symbol already exists in another OrCAD Library File. The <filename>.lib is created in most cases because the description of the MAX+PLUS II symbol is likely to differ from any OrCAD description of the same symbol. However, the <filename>.lib can cause conflicts when you use OrCAD to open other OrCAD Schematic Files in the same directory. These files may use the <filename>.lib description of a symbol instead of the native OrCAD description, which can cause connectivity problems in your files.

-	You should not enter probe, clique, logic cell, logic options, timing, and device assignments in OrCAD Schematic Files with the Assign menu commands, i.e., Probe, Pin/Location/Chip, Clique, Logic Options, Timing Requirements, and Device. Assignments entered with these commands must be identified by net (symbol) ID numbers, which do not exist in OrCAD Schematic Files. In addition, you can enter pin and chip assignments only on pin primitives with the Pin/Location/Chip command or with the Floorplan Editor. If you save an OrCAD Schematic File as a GDF, you can enter resource and device assignments with Assign menu commands in the GDF. Otherwise, you must enter all types of resource and device assignments only in a separate ACF with the same filename as the top-level OrCAD Schematic File.

-	You should not use the Edit Ports/Parameters dialog box (Symbol menu) to edit instance-specific parameter settings in OrCAD Schematic Files if you plan to save the file as a GDF later. When you save an OrCAD Schematic File as a GDF, these instance-specific parameter settings are not preserved.

If you save an OrCAD Schematic File as a GDF, you must specify the new top-level GDF as the project before compiling your project.

Text that touches a node line is treated as a node name. All other text or labels are treated as comments. Therefore, when you open an OrCAD Schematic File in the Graphic Editor, you must check all text and labels to make sure that all node names are associated with node lines and that all comments are not touching node lines.

Edit and update symbols carefully. When you open an OrCAD Schematic File in the Graphic Editor, MAX+PLUS II automatically translates the symbol and pinstub names in the original OrCAD Schematic File into their equivalent MAX+PLUS II symbol and pinstub names, using the mappings provided in the orcad.lmf file. MAX+PLUS II preserves the shape and pinstub locations in the original OrCAD symbol, which are stored in an OrCAD Library File, to maintain connectivity.

However, when you save an OrCAD Schematic File as a GDF, the "converted" OrCAD symbols do not have a corresponding Symbol File on disk. The only Symbol File that is available for you to edit or update is the Altera-provided version of the file, which may have a significantly different appearance. Therefore, you must exercise caution if you wish to edit or update a symbol in a file that is imported from OrCAD because you may lose connectivity in your schematic.

If you save a GDF as an OrCAD Schematic File, MAX+PLUS II creates an OrCAD Library File called <filename>.lib that describes all symbols as block parts, i.e., rectangles with pinstubs. MAX+PLUS II cannot create a graphical part, i.e., a part containing more detailed graphics, when it saves MAX+PLUS II symbol descriptions in an OrCAD Library File. In addition, the <filename>.lib may create conflicts when you use OrCAD to open other OrCAD Schematic Files in the same directory, as described above.

Altera recommends allowing extra space between symbols in OrCAD Schematic Files that will be opened in the MAX+PLUS II Graphic Editor: symbols in MAX+PLUS II can be slightly larger, and MAX+PLUS II will generate warning messages during compilation if symbols overlap.

See also:

Saving a File


OrCAD Schematic File (.sch) Description
OrCAD Schematic File (.sch)

A binary file (with the extension .sch), created with the OrCAD Draft schematic editor, that contains a logic schematic. You can open and edit an OrCAD Schematic File in the Graphic Editor, and save the edited file as either a GDF or an OrCAD Schematic File. You can also compile a project containing OrCAD Schematic Files directly in the MAX+PLUS II Compiler.

An OrCAD Schematic File can contain OrCAD function symbols that are mapped to equivalent MAX+PLUS II primitives and macrofunctions with the LMF orcad.lmf. MAX+PLUS II supports most functions in the OrCAD Library Files pldgates.lib and ttl.lib. All logic functions in the OrCAD Schematic File must be mapped to MAX+PLUS II primitives or macrofunctions in orcad.lmf. If you wish to use a function that is not mapped in orcad.lmf, you must add a mapping to orcad.lmf. You can map OrCAD functions to Altera-provided functions or to any design file created with MAX+PLUS II.

A single OrCAD Schematic File can be used to define all logic in a project, or can be incorporated at any hierarchy level in a hierarchical project. If you save an OrCAD Schematic File as a GDF, MAX+PLUS II treats it as an ordinary GDF and you can more easily incorporate the file’s logic into a higher-level design file in a hierarchical project.

Significant restrictions apply to using OrCAD Schematic Files in MAX+PLUS II. Refer to Restrictions on OrCAD Schematic Files in MAX+PLUS II and Guidelines for Working with OrCAD Schematic Files for detailed information.

The file icon for each OrCAD Schematic File that is part of the current hierarchy tree appears in the Hierarchy Display window.

See also:

Compiling OrCAD Schematic Files

Creating & Using Custom Macrofunctions (AHDL)

Creating a Default Include File

Guidelines for Working with Assignments

Library Mapping File (.lmf)

Saving a File

Specifying a User Library

Updating a Symbol in a Graphic Editor File


OrCAD Library File (.lib) Description
OrCAD Library File (.lib)

A binary file (with the extension .lib) that specifies how OrCAD symbols should be displayed in an OrCAD Schematic File.

The MAX+PLUS II Graphic Editor uses the information in an OrCAD Library File generated by OrCAD Compile Library or Edit Library graphical part editors to display symbols (parts) when you open an OrCAD Schematic File in MAX+PLUS II. MAX+PLUS II supports most functions in the OrCAD Library Files pldgates.lib and ttl.lib.

Before you open an OrCAD Schematic File in MAX+PLUS II, you should use OrCAD tools to create a single OrCAD Library File that contains the descriptions or all the OrCAD symbols used in the schematic. You should copy this OrCAD Library File into the project directory, or specify the directory that contains the file as a user library with User Libraries (Options menu). If the OrCAD Library File that contains a symbol description is not in the project directory or specified as a user library, MAX+PLUS II cannot display or compile the symbol.

When you save an OrCAD Schematic File in MAX+PLUS II, an OrCAD Library File called <filename>.lib is created in the project directory to contain descriptions of symbols (parts) that do not exist in other OrCAD Library Files. To minimize the number of times a new OrCAD Library File is generated, MAX+PLUS II checks existing OrCAD Library Files for all parts. If a part is found, MAX+PLUS II compares the pin layout to the part in the Graphic Editor to ensure that connectivity is preserved.

See also:

Compiling OrCAD Schematic Files

Guidelines for Working with OrCAD Schematic Files

Restrictions on OrCAD Schematic Files in MAX+PLUS II

Specifying a User Library


EDIF Command File (.edc) Description
EDIF Command File (.edc)

An ASCII text file (with the extension .edc) used to customize the format of EDIF Output Files created by the EDIF Netlist Writer module of the Compiler. Altera provides EDIF Command Files for popular industry-standard simulation tools.

Commands in the file are entered in EDIF Command File format. EDIF Command Files are specified as Compiler inputs with the EDIF Netlist Writer command (Interfaces menu) .

The file icon for each EDIF Command File with the same filename as the top-level design file in the current hierarchy tree appears in the Hierarchy Display window.

See also:

Creating EDIF Output Files

Recommended reading:

AN30 (Viewlogic Workview PLUS & MAX+PLUS II Logic Design)

AB99 (Design Flow between Workstations & PCs)

Viewlogic Powerview & MAX+PLUS II Software Interface Guide


EDIF Command File Format

The EDIF Command File is an ASCII text file you use or create to customize EDIF Output Files generated by the Compiler. Altera provides EDIF Command Files for popular industry-standard simulation tools. A sample EDIF Command File is shown below.

% This is a sample EDIF Command File %

FILENAME     example

KEYWORDLEVEL 1

ALIAS        instance   IN

CELL         and        LS04

PROPERTY     TTRI       tri_delay

LOGICVALUE   H          HI

You can use the EDIF Netlist Writer command (Interfaces menu) to specify an EDIF Command File is specified as an input to the Compiler.

The EDIF Command File consists of one command per line, with spaces delimiting command parameters. Comments must be enclosed in percent symbols (%). The EDIF Command File can contain one or more of the following commands:

ALIAS

CELL

FILENAME

KEYWORDLEVEL

LOGICVALUE

PROPERTY

See also:

Creating EDIF Output Files


EDIF Input File (.edf) Description
EDIF Input File (.edf)

An EDIF version 2 0 0 or 3 0 0 netlist file (with the extension .edf) generated by any industry-standard EDIF netlist writer.

Library Mapping Files

Library Mapping Files are used to map cells in an EDIF Input File to corresponding MAX+PLUS II primitives and macrofunctions, as well as user-defined macrofunctions. All logic functions in the EDIF Input File must be mapped to MAX+PLUS II primitives or macrofunctions in an LMF. If you wish to use a function that is not mapped in an Altera-provided LMF, you must create a customized LMF. You can map EDIF cells to Altera-provided functions or to any design file created with MAX+PLUS II.

The Compiler processes EDIF Input Files automatically. However, you can use the EDIF Netlist Reader command (Interfaces menu) to help the Compiler interpret EDIF Input Files by specifying optional LMFs and non-default VCC and GND signal names.

EDIF Constructs

To properly convert an EDIF Input File, EDIF constructs must have the following values:

Construct:	Value:

edifLevel	0

keywordLevel	0

viewType	Netlist

cellType	Generic

Hierarchical Projects

A single EDIF Input File can be used to define all logic in a project, or can be incorporated at any hierarchy level in a hierarchical project. MAX+PLUS II automatically creates a Symbol File that represents a EDIF Input File when you first save the file or when you choose Create Default Symbol (File menu). This symbol and the logic it represents can be incorporated into a GDF. You can also use EDIF Input File logic in an AHDL TDF by including a Function Prototype and inserting an instance of the macrofunction into the TDF.

Resource Assignments in EDIF Input Files

You can import resource assignments into MAX+PLUS II with the following EDIF property constructs. See Example: Resource Assignments in EDIF 2 0 0 Input Files or Example: Resource Assignments in EDIF 3 0 0 Input Files for an example.

chip_pin_lc

clique

logic_option

As an alternative, you can use the Assign menu commands to make device and resource assignments for the logic in the EDIF Input File, and to specify device and logic options.

Other Information

The Compiler Netlist Extractor generates a CNF and an HIF for every cell in an EDIF Input File. A Symbol File is generated for every cell except primitive cells (i.e., cells without Contents constructs) or cells that are mapped to MAX+PLUS II primitives or macrofunctions in an LMF.

The file icon for each EDIF Input File that is part of the current hierarchy tree appears in the Hierarchy Display window.

You can also automatically generate a default Include Filethat contains a Function Prototype for an EDIF Input File with Create Default Include File (File menu).

If you transfer an EDIF Input File from a workstation to a PC running Windows 3.1 for compilation, the filename may be truncated to 8 characters. You must then either rename the file with its previous longer filename from within MAX+PLUS II, or edit the file to change any instances of the filename to the new, truncated name. To rename the file from within MAX+PLUS II, open the file with the truncated name in the Text Editor and save it to its previous longer filename. However, if your file transfer software inserts characters into the truncated name that are not legal MAX+PLUS II name characters, you may need to first rename the file from Windows 3.1 or DOS before you can open it in the Text Editor.

See also:

Assigning Resources in a Third-Party Design Editor

Clique Assignments

Device Assignments

Compiling EDIF Input Files

Creating a Default Include File

Creating the Default Symbol for a File

Creating & Using Custom Macrofunctions (AHDL)

EDIF 2 0 0 Constructs Interpreted by MAX+PLUS II

EDIF 3 0 0 Constructs Interpreted by MAX+PLUS II

Guidelines for Working with Assignments

Logic Option Assignments

Pin, Logic Cell & Chip Assignments

Resource Assignments in EDIF Input Files

Recommended reading:

AN30 (Viewlogic Workview PLUS & MAX+PLUS II Logic Design)

Cadence & MAX+PLUS II Software Interface Guide

Mentor Graphics & MAX+PLUS II Software Interface Guide

Synopsys & MAX+PLUS II Software Interface Guide

Viewlogic Powerview & MAX+PLUS II Software Interface Guide


EDIF Output File (.edo) Description
EDIF Output File (.edo)

An EDIF version 2 0 0 or 3 0 0 netlist file (with the extension .edo) generated by the EDIF Netlist Writer module of the MAX+PLUS II Compiler.

You can create an EDIF Output File by turning on the EDIF Netlist Writer command (Interfaces menu) before compiling the project. You can specify options for the EDIF Output File with the EDIF Netlist Writer Settings command (Interfaces menu). The filenames of the EDIF Output File(s) and optional SDF Output File(s) are the same as the user-defined chip name(s) for the project; if no chip names exist, the Compiler assigns filenames that are based on the project name. For a multi-device project, MAX+PLUS II also generates a top-level EDIF Output File that is uniquely identified by "_t" appended to the the project name. Example

You can import an EDIF Output File into an industry-standard simulator on the workstation or PC for simulation. You can also create an EDIF Command File to customize the EDIF Output File for a particular simulation environment.

You can double-click Button 1 on the EDIF Output File icon in the Compiler window to open a Text Editor window with the EDIF Output File for the current project.

The file icon for an EDIF Output File with the same filename as the top-level design file in the current hierarchy tree appears in the Hierarchy Display window.

See also:

Creating EDIF Output Files

Recommended reading:

Cadence & MAX+PLUS II Software Interface Guide

AN30 (Viewlogic Workview PLUS & MAX+PLUS II Logic Design)

Mentor Graphics & MAX+PLUS II Software Interface Guide

Viewlogic Powerview & MAX+PLUS II Software Interface Guide

AB99 (Design Flow Between Workstations & PCs)


Library Mapping File (.lmf) Description
Library Mapping File (.lmf)

An ASCII text file (with the extension .lmf) that maps cells in EDIF Input Files or function symbols in OrCAD Schematic Files to equivalent MAX+PLUS II primitives and macrofunctions.

LMFs for EDIF Input Files allow the Compiler to substitute MAX+PLUS II primitives and macrofunctions for EDIF cells. They also eliminate the need for the Compiler to extract the information on those cells or symbols from the EDIF Input File. The orcad.lmf file allows the Graphic Editor to display symbols in an OrCAD Schematic File. The macrofunction mappings in Altera-provided LMFs also allow you to take advantage of family-specific macrofunctions.

All cells in EDIF Input Files and all symbols in OrCAD Schematic Files must be mapped to Altera macrofunctions or primitives in an LMF so that the MAX+PLUS II Compiler can interpret them.

LMFs for EDIF Input Files are specified as Compiler input files with the EDIF Netlist Reader command (Interfaces menu). The MAX+PLUS II Graphic Editor and Compiler automatically accept orcad.lmf as an input for OrCAD Schematic Files.

You can use one of the following Altera-provided LMFs for EDIF Input Files or OrCAD Schematic Files generated by industry-standard CAE tools:

Software:	Library Mapping File:

Cadence Design Systems	vld_bas.lmf	(for use with Concept)

cadence.lmf	(for use with Composer)

Mentor Graphics	mnt8_bas.lmf

OrCAD	orcad.lmf

Synopsys	altsyn.lmf

Viewlogic Systems	vwl_bas.lmf

You can also create a new custom LMFs for EDIF Input Files. You can also customize the orcad.lmf file to include additional macrofunction mappings.

See also:

Compiling EDIF Input Files

Compiling OrCAD Schematic Files

Library Mapping File Format

Recommended reading:

Cadence & MAX+PLUS II Software Interface Guide

AN30 (Viewlogic Workview PLUS & MAX+PLUS II Logic Design)

Mentor Graphics & MAX+PLUS II Software Interface Guide

Synopsys & MAX+PLUS II Software Interface Guide

Viewlogic Powerview & MAX+PLUS II Software Interface Guide

AB96 (Generating Library Mapping Files)

AB97 (Integrating EDIF Files with AHDL Files in Hierarchical Projects)

AB99 (Design Flow between Workstations & PCs)


Library Mapping File Format

An LMF is used to map EDIF cells or OrCAD Schematic File symbols to corresponding MAX+PLUS II primitives and macrofunctions. These MAX+PLUS II functions are directly substituted for the EDIF cells or OrCAD symbols when a file is opened or compiled in MAX+PLUS II.

An LMF includes statements that declare the names and input/output ports of MAX+PLUS II primitives or macrofunctions and corresponding EDIF cells or OrCAD symbols.

When compiling EDIF Input Files, you can specify up to two LMFs as inputs to the Compiler with the EDIF Netlist Reader command (Interfaces menu). The MAX+PLUS II Graphic Editor and Compiler automatically accept orcad.lmf as an input for OrCAD Schematic Files.

The following example shows a sample LMF that maps a single function.

LIBRARY	sample

% This LMF includes one entry that maps %

% Mentor Graphics NOR3 to MAX+PLUS II NOR3 %

BEGIN

FUNCTION	nor3 (IN1, IN2, IN3)

RETURNS	(OUT)

FUNCTION	"$nor3" ("I0", "I1", "I2")

RETURNS	("OUT")

END

LMFs have the following characteristics:

The LIBRARY keyword, followed by the library name, occurs once at the beginning of the LMF. The remainder of the file consists of one or more pairs of FUNCTION-RETURNS statements that declare MAX+PLUS II primitives or macrofunctions and EDIF cells or OrCAD symbols. An LMF must contain at least one pair of FUNCTION-RETURNS statements.

Every two pairs of FUNCTION-RETURNS statements, which are enclosed in one BEGIN-END statement, represent a mapping between a MAX+PLUS II primitive or macrofunction and an EDIF cell or OrCAD symbol. The MAX+PLUS II FUNCTION-RETURNS statement must come first. The MAX+PLUS II primitive or macrofunction ports must correspond to the EDIF cell or OrCAD symbol ports in position.

EDIF cells that have more or fewer ports than MAX+PLUS II primitives or macrofunctions can still be mapped, as described in Mapping Unequal Numbers of Inputs & Outputs.

Comments must be enclosed in percent symbols (%).

Several different EDIF cells or OrCAD symbols can be mapped to the same MAX+PLUS II primitive or macrofunction. All the mappings must list the same inputs and outputs. A single EDIF cell or OrCAD symbol cannot be mapped to multiple MAX+PLUS II primitives or macrofunctions.

When creating LMFS for EDIF 3 0 0 files that contain buses, you must create a mapping for each bit of the bus. Example

See also:

Compiling EDIF Input Files

Compiling OrCAD Schematic Files

Library Mapping File Syntax

Recommended reading:

AB96 (Generating Library Mapping Files)


Standard Delay Format Output File (.sdo) Description
Standard Delay Format Output File (.sdo)

An optional VHDL standard netlist file (with the extension .sdo) that is generated by the MAX+PLUS II Compiler. The Standard Delay Format (SDF) is an industry-standard format. The SDF Output File contains timing delay information that allows you to perform back-annotation simulation in VHDL with VITAL-compliant simulation libraries, back-annotation simulation in Verilog, timing analysis, and synthesis.

You can create an SDF Output File when you select the SDF 2.1 or SDF 1.0 options under Delay Formats Written To in the EDIF Netlist Writer Settings, Verilog Netlist Writer Settings, or VHDL Netlist Writer Settings dialog box (Interfaces menu), then turn on the EDIF Netlist Writer, Verilog Netlist Writer, or VHDL Netlist Writer command (Interfaces menu). The filenames of the Standard Delay Output File(s) are the same as the user-defined chip name(s) for the project; if no chip names exist, the Compiler assigns filenames that are based on the project name. For a multi-device project, MAX+PLUS II also generates a top-level SDF Output File that is uniquely identified by "_t" appended to the the project name. Example

Specifying the SDF Output File (.sdo) Ver. 2.1 or SDF Output File (.sdo) Ver. SDF 1.0 option under Delay Formats Written To in any one of the EDIF Netlist Writer Settings, Verilog Netlist Writer Settings, or VHDL Netlist Writer Settings dialog boxes sets the option for all the netlist writers. For example, if you specify SDF Output File (.sdo) Ver. 2.1 under Delay Formats Written To in the EDIF Netlist Writer Settings dialog box, but have turned off the EDIF Netlist Writer command and turned on the VHDL Netlist Writer command, the Compiler will still generate an SDF Output File in SDF version 2.1 format when it generates the VHDL Output File.

The file icon for a SDF Output File with the same filename as the top-level design file in the current hierarchy tree appears in the Hierarchy Display window.

See also:

Creating EDIF Output Files

Creating Verilog Output Files

Creating VHDL Output Files

Recommended reading:

Cadence & MAX+PLUS II Software Interface Guide

Mentor Graphics & MAX+PLUS II Software Interface Guide

Synopsys & MAX+PLUS II Software Interface Guide

Viewlogic Powerview & MAX+PLUS II Software Interface Guide

AN30 (Viewlogic Workview PLUS & MAX+PLUS II Logic Design)


Verilog Output File (.vo) Description
Verilog Output File (.vo)

A Verilog Hardware Description Language (HDL) standard netlist file (with the extension .vo) that is generated by the Verilog Netlist Writer module of the Compiler.

You can create a Verilog Output File by turning on the Verilog Netlist Writer command (Interfaces menu) before compiling the project.  You can specify options for the Verilog Output File with the Verilog Netlist Writer Settings command (Interfaces menu). The filenames of the Verilog Output File(s) and optional SDF Output File(s) are the same as the user-defined chip name(s) for the project; if no chip names exist, the Compiler assigns filenames that are based on the project name. For a multi-device project, MAX+PLUS II also generates a top-level Verilog Output File that is uniquely identified by "_t" appended to the the project name. Example

You can import a Verilog Output File into a third-party workstation or PC environment for simulation.

You can double-click Button 1 on the Verilog Output File icon in the Compiler window to open a Text Editor window with the Verilog Output File for the current project.

The file icon for a Verilog Output File with the same filename as the top-level design file in the current hierarchy tree appears in the Hierarchy Display window.

See also:

Creating Verilog Output Files

Recommended reading:

Cadence & MAX+PLUS II Software Interface Guide

AN30 (Viewlogic Workview PLUS & MAX+PLUS II Logic Design)

Mentor Graphics & MAX+PLUS II Software Interface Guide

Synopsys & MAX+PLUS II Software Interface Guide

Viewlogic Powerview & MAX+PLUS II Software Interface Guide


VHDL Output File (.vho) Description
VHDL Output File (.vho)

A VHDL standard netlist file (with the extension .vho) that is generated by the VHDL Netlist Writer module of the Compiler.

You can create a VHDL Output File by turning on the VHDL Netlist Writer command (Interfaces menu) before compiling the project. You can specify options for the VHDL Output File with the VHDL Netlist Writer Settings command (Interfaces menu). The filenames of the VHDL Output File(s) and optional SDF Output File(s) are the same as the user-defined chip name(s) for the project; if no chip names exist, the Compiler assigns filenames that are based on the project name. For a multi-device project, MAX+PLUS II also generates a top-level VHDL Output File that is uniquely identified by "_t" appended to the the project name. Example

You can import a VHDL Output File into a third-party workstation or PC environment for simulation.

You can double-click Button 1 on the VHDL Output File icon in the Compiler window to open a Text Editor window with the VHDL Output File for the current project.

The file icon for a VHDL Output File with the same filename as the top-level design file in the current hierarchy tree appears in the Hierarchy Display window.

See also:

Creating VHDL Output Files

Recommended reading:

Cadence & MAX+PLUS II Software Interface Guide

AN30 (Viewlogic Workview PLUS & MAX+PLUS II Logic Design)

Mentor Graphics & MAX+PLUS II Software Interface Guide

Synopsys & MAX+PLUS II Software Interface Guide

Viewlogic Powerview & MAX+PLUS II Software Interface Guide


VHDL Memory Model Output File (.vmo) Description
VHDL Memory Model Output File (.vmo)

A Compiler-generated VHDL standard netlist file (with the extension .vmo) that contains VHDL simulation models.

The Compiler's EDIF Netlist Writer module automatically generates a VHDL Memory Model Output File when it generates an EDIF Output File that contains a RAM or ROM segment that is used for a RAM-slice. The filename of the VHDL Memory Model Output File is the same as the project name.

You can import an VHDL Memory Model Output File with the appropriate EDIF Output File(s) into a third-party workstation or PC environment for simulation.

The file icon for a VHDL Memory Model Output File with the same filename as the top-level design file in the current hierarchy tree appears in the Hierarchy Display window.

See also:

Creating EDIF Output Files


Text Design Export File (.tdx) Description
Text Design Export File (.tdx)

An ASCII text file (with the extension .tdx), generated by the MAX+PLUS II Compiler, that contains the AHDL equivalent of a Xilinx Netlist Format File.

The Compiler generates a Text Design Export File when you compile a project that contains XNF Files if you turn on the Generate Text Design Export File (.tdx) option in the XNF Netlist Reader dialog box (Interfaces menu). All information in the Text Design Export File is given in AHDL Text Design File Format.

After the Compiler has created a Text Design Export File, you can save the file as a TDF and use Change File Type (File menu) in the Hierarchy Display to replace the XNF File with the TDF in the hierarchy tree for your project. The Compiler will then use the TDF rather than the XNF File during future compilations, allowing you to take advantage of the easily readable AHDL format and context-sensitive help in your design debugging and error location.

The file icon for a Text Design Export File that is part of the current hierarchy tree appears in the Hierarchy Display window.

See also:

AHDL Help Contents

Changing the File Type

Compiling XNF Files

Getting Context-Sensitive Help

Saving a File


Example:CMP-Assigned Name for the EDIF Output File
If multiple EDIF Output Files or SDF Output Files are generated, they are uniquely identified by a sequence number appended to the project name, e.g., if the project name is myproj, the first EDIF Output File is myproj.edo, the second is myproj1.edo, etc.; the first SDF Output File is myproj.sdo, the second is myproj1.sdo, etc.

In addition, MAX+PLUS II generates a top-level EDIF Output File that is uniquely identified by "_t" appended to the the project name, e.g., if the project name is myproj, the top-level EDIF Output File is myproj_t.edo.

If you’re using MAX+PLUS II on a PC and the project name has more than 8 characters, MAX+PLUS II will truncate the filename if necessary to include the numerical index or "_t" characters and maintain the 8-character filename length. MAX+PLUS II creates a maxplus2.idx file that maps the original filenames to the 8-character filenames. If you use a project name with 8 characters or less, the numerical index or "_t" characters are appended to it.


Example:CMP-Assigned Name for the Verilog Output File
If multiple Verilog Output Files or SDF Output Files are generated, they are uniquely identified by a sequence number appended to the project name, e.g., if the project name is myproj, the first Verilog Output File is myproj.vo, the second is myproj1.vo, etc.; the first SDF Output File is myproj.sdo, the second is myproj1.sdo, etc.

In addition, MAX+PLUS II generates a top-level Verilog Output File that is uniquely identified by "_t" appended to the the project name, e.g., if the project name is myproj, the top-level Verilog Output File is myproj_t.vo.

If you’re using MAX+PLUS II on a PC and the project name has more than 8 characters, MAX+PLUS II will truncate the filename if necessary to include the numerical index or "_t" characters and maintain the 8-character filename length. MAX+PLUS II creates a maxplus2.idx file that maps the original filenames to the 8-character filenames. If you use a project name with 8 characters or less, the numerical index or "_t" characters are appended to it.


Example:CMP-Assigned Name for the VHDL Output File
If multiple VHDL Output Files or SDF Output Files are generated, they are uniquely identified by a sequence number appended to the project name, e.g., if the project name is myproj, the first VHDL Output File is myproj.vho, the second is myproj1.vho, etc.; the first SDF Output File is myproj.sdo, the second is myproj1.sdo, etc.

In addition, MAX+PLUS II generates a top-level VHDL Output File that is uniquely identified by "_t" appended to the the project name, e.g., if the project name is myproj, the top-level VHDL Output File is myproj_t.vho.

If you’re using MAX+PLUS II on a PC and the project name has more than 8 characters, MAX+PLUS II will truncate the filename if necessary to include the numerical index or "_t" characters and maintain the 8-character filename length. MAX+PLUS II creates a maxplus2.idx file that maps the original filenames to the 8-character filenames. If you use a project name with 8 characters or less, the numerical index or "_t" characters are appended to it.


Example:CMP-Assigned Name for the Text Design Output File
If multiple Text Design Output Files and Assignment & Configuration Output Files are generated, they are uniquely identified by a sequence number appended to the project name, e.g., if the project name is myproj, the first TDO File is myproj.tdo, the second is myproj1.tdo, etc., and the first ACO File is myproj.aco, the second is myproj1.aco, etc.

In addition, MAX+PLUS II generates a top-level TDO File that is uniquely identified by "_t" appended to the the project name, e.g., if the project name is myproj, the top-level TDO File is myproj_t.tdo.

If you’re using MAX+PLUS II on a PC and the project name has more than 8 characters, MAX+PLUS II will truncate the filename if necessary to include the numerical index or "_t" characters and maintain the 8-character filename length. MAX+PLUS II creates a maxplus2.idx file that maps the original filenames to the 8-character filenames. If you use a project name with 8 characters or less, the numerical index or "_t" characters are appended to it.


Text Design Output File (.tdo) Description
Text Design Output File (.tdo)

An ASCII text file (with the extension .tdo), generated by the MAX+PLUS II Compiler, that contains the AHDL equivalent of the fully optimized logic for a device in the project.

You can create one or more TDO File(s), as well as one or more Assignment & Configuration Output File(s), if you turn on the Generate AHDL TDO File command (Processing menu). All information in the TDO File is given in AHDL Text Design File Format. The filenames of the TDO File(s) and ACO File(s) are the same as the user-defined chip name(s) for the project; if no chip names exist, the Compiler assigns filenames that are based on the project name. For a multi-device project, MAX+PLUS II also generates a top-level TDO File that is uniquely identified by "_t" appended to the the project name. Example

A TDO File for a single device contains the fully optimized logic for that device. You can save a TDO File as a Text Design File, edit it, specify as it as the project with Project Name (File menu), and recompile the project. (You must also save the ACO File as an Assignment & Configuration File if you wish to preserve the assignments for the device.) TDO Files facilitate back-annotation and preserve the existing logic synthesis in the project. In a multi-device project, TDO Files also allow you to "lock down" the design and pin-out of each device in the project.

The top-level TDO File for a multi-device project can be used for linked multi-project simulation. You must first recompile each lower-level TDO File to create a functional SNF or timing SNF, and then compile the top-level TDO File with the Linked SNF Extractor command (Processing menu) turned on. See File Structure Requirements for Multi-Project Simulation for more information.

The TDO File contains new node names that represent the flattened hierarchy. If the new node names exceed 32 name characters, you must shorten  the node names before you compile the TDO File.

The file icon for a TDO File with the same filename as the top-level design file in the current hierarchy tree appears in the Hierarchy Display window.

See also:

AHDL Help Contents

Changing the File Type

Hierarchical Node & Symbol Names

Saving a File


Xilinx Netlist Format File (.xnf) Description
Xilinx Netlist Format File (.xnf)

A Xilinx Netlist Format (XNF) netlist file (with the extension .xnf) generated by running the Xilinx LCA2XNF utility. (For version 4.0 of XACT software, you must use the -g command-line option; for version 5.0, you must use the command-line options -g -v.)

The Compiler processes XNF Files automatically and accepts designs targeted for any Xilinx devices or families. However, you must follow the guidelines in File Structure Requirements for XNF Files. You can use the XNF Netlist Reader command (Interfaces menu) to help the Compiler interpret XNF Files.

An XNF File can be used to define all logic in a project, or can be used to define a bottom-level file in a hierarchical project. MAX+PLUS II automatically creates a Symbol File that represents an XNF File when you first compile the file or when you choose Create Default Symbol (File menu). This symbol and the logic it represents can be incorporated into a GDF. You can also use XNF File logic in an AHDL TDF by including a Function Prototype and inserting an instance of the macrofunction into the TDF.

The file icon for each XNF File that is part of the current hierarchy tree appears in the Hierarchy Display window.

You can also automatically generate a default Include Filethat contains a Function Prototype for an XNF File with Create Default Include File (File menu).

See also:

Compiling Xilinx Netlist Format Files

Creating a Default Include File

Creating the Default Symbol for a File

Creating & Using Custom Macrofunctions (AHDL)


Guidelines for Workstation Users

MAX+PLUS II software runs on UNIX workstations and PCs.

The following guidelines apply to using MAX+PLUS II Help for workstations:

Pathnames appear in MAX+PLUS II Help with backslash (\) characters, but workstation pathnames use forward slash (/) characters.

The workstation environment is case-sensitive. Filename extensions should be typed in lowercase letters on the workstation. Filenames and directory names should be typed in the appropriate case (usually lowercase letters). Filenames can contain up to 255 characters; extensions may contain up to 3 characters; and the maximum combined length of a pathname, filename, and extension is 1024 characters.

If you transfer a file from a workstation to a PC running Windows 3.1 for compilation, the filename may be truncated to 8 characters. You must then either rename the file with its previous longer filename from within MAX+PLUS II, or edit the file to change any instances of the filename to the new, truncated name. To rename the file from within MAX+PLUS II, open the file with the truncated name in the Text Editor and save it to its previous longer filename. However, if your file transfer software inserts characters into the truncated name that are not legal MAX+PLUS II name characters, you may need to first rename the file from Windows 3.1 or DOS before you can open it in the Text Editor.

You can ignore all references in MAX+PLUS II Help to drive identifiers (e.g., a:, b:, c:), DOS, and Windows.

For information about available command-line options, type maxplus2 -h at the UNIX prompt.

See also:

How to Use Help (workstations only)

Searching for a Help Topic

Third-Party Interfaces Help Contents


Modified Assignment Syntax for Pin, Logic Cell & Chip Assignments

Syntax:	Example:

[<chip name>]@<pin number>	CHIPB@5

[<chip name>]@LC<logic cell number>	CHIPA@LC42, CHIPB@LC1_B14

<chip name>	CHIPC

The default name for a chip is the project name; the chip name is optional for a project that fits into a single device. However, if you have a multi-device project, you must not use the project name for any of the chips. A chip name may contain up to 32 of the following name characters: A to Z, a to z, 0 to 9, slash (/), dash (-), and underscore (_). Multiple assignments are separated by a comma (,). For example:

 CHIPA@42,CHIPB@10

In FLEX 8000 devices, logic cells have "numbers" of the format LC<number>_<LAB name>, where <number> ranges from 1 to 8 and <LAB name> consists of the row letter and column number of the LAB. In Classic, MAX 5000/EPS464, MAX 7000, and MAX 7000E devices, logic cells have numbers of the format LC<number>, where <number> is specified in Devices & Adapters or the device data sheet.


Modified Assignment Syntax for Logic Option Assignments

You can enter a logic synthesis style or logic option setting in either of the following formats:

STYLE=<logic synthesis style name>

<logic option name>=<logic option setting>

You can abbreviate a <logic option name> and/or <logic option setting> to contain as few as the first three characters. For example, MIN=PART specifies Partial as the setting for Minimization. The <logic option setting> is usually ON, OFF, or DEFAULT, with the following exceptions:

Option:	Setting Name:	Option:	Setting Name:

MINIMIZATION	FULL	OPTIMIZE	AREA

MINIMIZATION	PARTIAL	OPTIMIZE	DELAY

MINIMIZATION	NONE

Multiple assignments are separated by a comma (,). Logic synthesis styles are overridden by individual logic options. In the following example, the settings for the Parallel Expanders and Minimization options override settings for these logic options in the Normal style:

STYLE=NORMAL, PARA=ON, MIN=PART


Cadence Concept Library Mapping File (vld_bas.lmf)

The Cadence-compatible Library Mapping File provided by Altera, vld_bas.lmf, is automatically installed in the \maxplus2\lmf directory. This file maps Cadence basic and LSTTL functions to the following MAX+PLUS II primitives and macrofunctions. Function names are shown here in capital letters, but appear with lowercase letters in the LMF.

See also:

Guidelines for Workstation Help Users

Recommended reading:

Cadence & MAX+PLUS II Software Interface Guide

AB96 (Generating Library Mapping Files)

Cadence Function:	MAX+PLUS II Function:

A00	7400

A02	7402

A04	7404

A08	7408

A10	7410

A11	7411

A20	7420

A21	7421

A27	7427

A28	7428

A30	7430

A32	7432

A37	7437

A40	7440

A42	7442

A51	7451

A54	7454

A74	7474

A75	7475

A76	7476

A77	7477

A78	7478

A83	7483

A85	7485

A86	7486

A90	7490

Cadence Function:	MAX+PLUS II Function:

A91	7491

A92	7492

A93	7493

A95	7495

A96	7496

A107	74107

A109	74109

A112	74112

A113	74113

A114	74114

A126	tri

A133	74133

A138	74138

A139	74139m

A147	74147

A148	74148

A151	74151

A153	74153

A154	74154

A155	74155

A156	74156

A157	74157

A158	74158

Cadence Function:	MAX+PLUS II Function:

A160	74160

A161	74161

A162	74162

A163	74163

A164	74164

A165	74165

A166	74166

A168	74168

A169	74169

A173	74173

A174	74174

A175	74175

A181	74181

A183	74183

A190	74190

A191	74191

A192	74192

A193	74193

A194	74194

A195	74195

A196	74196

A197	74197

A240	74240

A241	74241

Cadence Function:	MAX+PLUS II Function:

A244	74244

A251	74251

A253	74253

A257	74257

A258	74258

A259	74259

A260	74260

A261	74261

A266	xnor

A273	74273

A279	74279

A280	74280

A283	74283

A290	74290

A293	74293

A299	74299

A348	74348

A353	74353

A365	74365

A366	74366

A367	74367

A368	74368

A373	74373

A374	74374

Cadence Function:	MAX+PLUS II Function:

A377	74377

A379	74379

A381	74381

A386	74386

A390	74390

A393	74393

DFFE	dffe

DFF	dff

SOFT	soft

MCELL	mcell

LCELL	lcell

SCLK	sclk

GLOBAL	global

CARRY	carry

CASCADE	cascade

EXP	exp

inv	not

A_8COUNT	8count

A_8MCOMP	8mcomp

A_8FADD	8fadd

A_81MUX	81mux

AND#	and#	(# = 2, 3, 4, 6, 8, 12)

NAND#	nand#	(# = 2, 3, 4, 6, 8, 12)

OR#	or#	(# = 2, 3, 4, 6, 8, 12)

NOR#	nor#	(# = 2, 3, 4, 6, 8, 12)

a_tri	tri

tff	tff

latch	latch

a_vcc	soft

a_gnd	soft

inv	not

xor2	xor


Cadence Composer Library Mapping File (cadence.lmf)

The Cadence Composer-compatible Library Mapping File provided by Altera, cadence.lmf, is automatically installed in the \maxplus2\lmf directory. This file maps Cadence Composer basic functions to the following MAX+PLUS II primitives and macrofunctions. Function names are shown here in capital letters, but appear with lowercase letters in the LMF.

See also:

Guidelines for Workstation Help Users

Recommended reading:

Cadence & MAX+PLUS II Software Interface Guide

AB96 (Generating Library Mapping Files)

Cadence Function:	MAX+PLUS II Function:

A00	7400

A02	7402

A04	7404

A08	7408

A10	7410

A11	7411

A20	7420

A21	7421

A27	7427

A28	7428

A030	7430

A032	7432

A037	7437

A040	7440

A142	7442

A151	7451

A254	7454

A274	7474

A275	7475

A276	7476

A77	7477

A78	7478

A83	7483

Cadence Function:	MAX+PLUS II Function:

A085	7485

A086	7486

A090	7490

A091	7491

A192	7492

A193	7493

A295	7495

A296	7496

A2107	74107

A2109	74109

A0112	74112

A0113	74113

A0114	74114

A0126	tri

A1133	74133

A1138	74138

A2139	74139m

A2147	74147

A2148	74148

A2151	74151

A153	74153

A154	74154

A155	74155

A156	74156

A157	74157

Cadence Function:	MAX+PLUS II Function:

A0158	74158

A0160	74160

A0161	74161

A0162	74162

A1163	74163

A1164	74164

A2165	74165

A2166	74166

A2168	74168

A2169	74169

A0173	74173

A0174	74174

A0175	74175

A0181	74181

A1183	74183

A1190	74190

A2191	74191

A2192	74192

A2193	74193

A2194	74194

A195	74195

A196	74196

A197	74197

A240	74240

A241	74241

Cadence Function:	MAX+PLUS II Function:

A0244	74244

A0251	74251

A0253	74253

A0257	74257

A1258	74258

A1259	74259

A2260	74260

A2261	74261

A2266	xnor

A2273	74273

A279	74279

A0280	74280

A0283	74283

A0290	74290

A0293	74293

A1299	74299

A1348	74348

A2353	74353

A2365	74365

A2366	74366

A2367	74367

A368	74368

A373	74373

A374	74374

Cadence Function:	MAX+PLUS II Function:

A377	74377

A379	74379

A381	74381

A386	74386

A390	74390

A393	74393

CARRY	carry

CASCADE	cascade

EXP	exp

GLOBAL	global

LCELL	lcell

MCELL	mcell

SCLK	sclk

SOFT	soft

AND#	and#	(# = 2, 3, 4, 6, 8, 12)

NAND#	nand#	(# = 2, 3, 4, 6, 8, 12)

OR#	or#	(# = 2, 3, 4, 6, 8, 12)

NOR#	nor#	(# = 2, 3, 4, 6, 8, 12)

a_tri	tri

tff	tff

latch	latch

a_vcc	soft

a_gnd	soft

inv	not

xor2	xor


Synopsys Library Mapping File (altsyn.lmf)

The Synopsys-compatible Library Mapping File provided by Altera, altsyn.lmf, is automatically installed in the \maxplus2\lmf directory. This file maps Synopsys functions to the following MAX+PLUS II primitives and macrofunctions. Function names are shown here in capital letters, but appear with lowercase letters in the LMF.

See also:

Guidelines for Workstation Help Users

Recommended reading:

Synopsys & MAX+PLUS II Software Interface Guide

AB96 (Generating Library Mapping Files)

Synopsys Function:	MAX+PLUS II Function:

AND#	and#	(# = 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)

OR#	s_or#	(# = 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)

NAND#	nand#	(# = 2, 3, 4, 6, 8, 12)

NOR#	nor#	(# = 2, 3, 4, 6, 8, 12)

XOR2	xor

XNOR2	xnor

DFF	dff

DFFS	dff

TFF	tff

TFFS	tff

INV	not

TRI	tri

EXP	exp

CARRY	carry

CASCADE	cascade

LATCH	latch

GLOBAL	global

SOFT	soft

LCELL	lcell

MCELL	mcell

TBL_1	tbl_1

TBL_2	tbl_2

TBL_3	tbl_3

TBL_4	tbl_4

TBL_5	tbl_5

Synopsys Function:	MAX+PLUS II Function:

TBL_6	tbl_6

TBL_7	tbl_7

TBL_8	tbl_8

TBL_9	tbl_9

TBL_10	tbl_10

FLEX_ADD	f_add

FLEX_CARRY	f_c

FLEX_SUB	f_sub

FLEX_BORROW	f_borrow

FLEX_GT	f_gt

FLEX_CARRY_GT	f_c_gt

FLEX_LT	f_lt

FLEX_CARRY_LT	f_c_lt

FLEX_GTEQ	f_gteq

FLEX_CARRY_GTEQ	f_c_ge

FLEX_LTEQ	f_lter

FLEX_CARRY_LTEQ	f_c_le

FLEX_INC	f_inc

FLEX_CARRY_INC	f_c_inc

FLEX_DEC	f_dec

FLEX_CARRY_DEC	f_c_dec

FLEX_COUNT	f_cnt

FLEX_CARRY_COUNT	f_c_cnt

A_81MUX	81mux

A_8COUNT	8count

A_8MCOMP	8mcomp

A_8FADD	8fadd


Mentor Graphics Library Mapping File (mnt8_bas.lmf)

The Mentor Graphics-compatible Library Mapping File provided by Altera, mnt8_bas.lmf, is installed in the \maxplus2\lmf directory. This file maps Mentor Graphics basic and LSTTL functions to the following MAX+PLUS II primitives and macrofunctions. Function names are shown here in capital letters, but appear with lowercase letters in the LMF.

See also:

Guidelines for Workstation Help Users

Recommended reading:

Mentor Graphics & MAX+PLUS II Software Interface Guide

AB96 (Generating Library Mapping Files)

Mentor Graphics Function:	MAX+PLUS II Function:

74LS00	7400

74LS02	7402

74LS04	7404

74LS08	7408

74LS10	7410

74LS11	7411

74LS20	7420

74LS21	7421

74LS27	7427

74LS28	7428

74LS30	7430

74LS32	7432

74LS37	7437

74LS40	7440

74LS42	7442

74LS51	7451

74LS54	7454

74LS55	7455

74LS73A	7473a

74LS74A	7474

74LS75	7475

74LS76A	7476a

74LS77	7477

74LS83A	7483

74LS85	7485

Mentor Graphics Function:	MAX+PLUS II Function:

74LS86	7486

74LS90	7490

74LS91	7491

74LS92	7492

74LS93	7493

74LS95B	7495

74LS96	7496

74LS107A	74107a

74LS109A	74109

74LS112A	74112

74LS113A	74113

74LS114A	74114

74LS126A	tri

74LS133	74133

74LS138	74138

74LS139A	74139m

74LS147	74147

74LS148	74148

74LS151	74151

74LS153	74153

74LS154	74154

74LS155A	74155

74LS156	74156

74LS157	74157

74LS158	74158

Mentor Graphics Function:	MAX+PLUS II Function:

74LS160A	74160

74LS161A	74161

74LS162A	74162

74LS163A	74163

74LS164	74164

74LS165	74165

74LS166	74166

74LS168A	74168

74LS169A	74169

74LS173A	74173

74LS174	74174

74LS175	74175

74LS181	74181

74LS183	74183

74LS190	74190

74LS191 	74191

74LS192 	74192

74LS193	74193

74LS194A	74194

74LS195A	74195

74LS196	74196

74LS197	74197

74LS240	74240

74LS241	74241

74LS244	74244

Mentor Graphics Function:	MAX+PLUS II Function:

74LS251	74251

74LS253	74253

74LS257A	74257

74LS258A	74258

74LS260	74260

74LS266	xnor

74LS273	74273

74LS279	74279

74LS280	74280

74LS283	74283

74LS290	74290

74LS293	74293

74LS299	74299

74LS348	74348

74LS353	74353

74LS365A	74365

74LS366A	74366

74LS367A	74367

74LS368A	74368

74LS373	74373

74LS374	74374

74LS377	74377

74LS379	74379

74LS381	74381

74LS390	74390

Mentor Graphics Function:	MAX+PLUS II Function:

74LS393	74393

74LS688	74688

and#	and#	(# = 2, 3, 4, 5, 6)

buf	sclk

carry	carry

cascade	cascade

delay	mcell

dff	dff2

dffe	dffe

exp	exp

global	global

jkff	jkff2

inv	not

lcell	lcell

mcell	mcell

latch	mlatch

nand#	nand#	(# = 2, 3, 4, 5, 6, 8, 9)

nor#	nor#	(# = 2, 3, 4, 6, 8, 16)

or#	or#	(# = 2, 3, 4, 6, 8)

sclk	sclk

soft	soft

tff	tff

tffe	tffe

tri	tri

Mentor Graphics Function:	MAX+PLUS II Function:

buf.350	tri

xnor2	xnor

xor2	xor

A_81MUX	81mux

A_8COUNT	8count

A_8MCOMP	8mcomp

A_8FADD	8fadd

81MUX	81mux

8COUNT	8count

8MCOMP	8mcomp

8FADD	8fadd


OrCAD Library Mapping File (orcad.lmf) Description
OrCAD Library Mapping File (orcad.lmf)

The OrCAD-compatible Library Mapping File provided by Altera, orcad.lmf, is automatically installed in the \maxplus2 directory. This file maps OrCAD functions to the following MAX+PLUS II primitives and macrofunctions. Function names are shown here in capital letters, but appear with lowercase letters in the LMF.

MAX+PLUS II supports all prefixes in the OrCAD Library File ttl.lib automatically, so that only a single mapping is needed in orcad.lmf for all variations of a single function.

See also:

Guidelines for Workstation Help Users

Recommended reading:

AB96 (Generating Library Mapping Files)

OrCAD Function:	MAX+PLUS II Function:

7400	7400

7402	7402

7404	7404

7408	7408

7410	7410

7411	7411

7414	7404

7419	7404

7420	7420

7421	7421

7424	7400

7425	7425o

7426	7400

7427	7427

7428	7402

7430	7430

7432	7432

7437	7400

7440	7440

7442	7442

7443	7443

7444	7444

7445	7445

7449	7449

7450	7450

OrCAD Function:	MAX+PLUS II Function:

7451	7451

7454	7454

7455	7455

7456	7456

7457	7457

7464	7464

7468	7468

7469	7469

7470	7470

7472	7472

7473	7473o

7474	dff2

7475	7475

7476	jkff2

7477	7477

7478	7478

7482	7482

7483	7483

7486	7486

7490	7490

7491	7491

7492	7492

7493	7493

7494	7494

7495	7495

OrCAD Function:	MAX+PLUS II Function:

7496	7496

74107	74107o

74109	74109o

74112	74112o

74113	74113o

74114	74112o

74116	74116o

74128	7402

74132	7400

74133	74133

74134	74134

74135	74135o

74137	74137

74138	74138

74139	74139o

74140	7420

74145	74145

74147	74147

74148	74148

74151	74151

74153	74153

74154	74154

74155	74155

74156	74156

OrCAD Function:	MAX+PLUS II Function:

74157	74157

74158	74158

74160	74160

74161	74161

74162	74162

74163	74163

74164	74164

74165	74165

74166	74166

74168	74168

74169	74169

74171	74171

74172	74172

74173	74173

74174	74174

74175	74175

74176	74176

74177	74177

74178	74178

74179	74179

74180	74180

74181	74181

74182	74182

74183	74183

OrCAD Function:	MAX+PLUS II Function:

74184	74184

74185	74185

74190	74190

74191 	74191

74192	74192

74193	74193

74194	74194

74195	74195

74196	74196

74197	74197

74198	74198

74199	74199

74240	74240o

74241	74241

74244	74244

74251	74251

74253	74253

74257	74257

74258	74258

74259	74259

74260	nor5

74261	74261

74265	74265

74273	74273

74276	74276o

OrCAD Function:	MAX+PLUS II Function:

74278	74278

74279	74279

74280	74280

74283	74283

74284	74284

74285	74285

74290	74290

74292	74292

74293	74293

74294	74294

74295	74295

74297	74297

74298	74298

74299	74299

74348	74348

74350	74350

74352	74352

74353	74353

74354	74354

74356	74356

74365	74365

74366	74366

74367	74367

74368	74368

74373	74373

OrCAD Function:	MAX+PLUS II Function:

74374	74374

74375	74375

74376	74376

74377	74377

74378	74378

74379	74379

74381	74381

74382	74382

74385	74385

74386	xor

74390	74390o

74393	74393m

74393	74393

74393	74393

74396	74396

74398	74398

74399	74399

74445	74445

74447	74247

74465	74465

74466	74466

74467	74467o

74468	74240o

74490	74490o

74518	74518

OrCAD Function:	MAX+PLUS II Function:

74540	74540

74541	74541

74568	74568

74569	74569

74589	74589

74590	74590

74592	74592

74594	74594

74595	74595

74597	74597

74604	74604

74606	74604

74668	74668

74669	74669

74670	74670

74671	74671

74672	74672

74684	74684

74686	74686

74688	74688

74690	74690

74691	74691

74693	74693

74696	74696

74697	74697

OrCAD Function:	MAX+PLUS II Function:

74698	74698

74699	74699

74821	74821

74822	74822

74823	74823

74824	74824

74825	74825

74826	74826

74841	74841

74842	74842

74843	74843

74844	74844

74845	74845

74846	74846

741000	7400

741002	7402

741004	7404

741008	7408

741010	7410

741011	7411

741020	7420

741032	7432

742036	741036

G00	7400

G02	7402

OrCAD Function:	MAX+PLUS II Function:

G04	7404

G08	7408

G10	7410

G11	7411

G20	7420

G21	7421

G27	7427

G28	7402

G30	7430

G32	7432

G37	7400

G40	7420

G42	7442

G43	7443

G44	7444

G48	7448

G51	7451

G54	7454

G55	7455

G73	7473o

G74	dff2

G75	7475

G76	jkff2

G77	7477

G80	7480

OrCAD Function:	MAX+PLUS II Function:

G82	7482

G85	7485

G86	7486

G96	7496

G107	74107o

G109	74109o

G112	74112o

G114	74112o

G133	74133

G134	74134

G138	74138

G139	74139

G145	74145

G147	74147

G148	74148

G151	74151

G153	74153

G154	74154

G155	74155o

G157	74157o

G158	74158o

G160	74160

G161	74161

G162	74162

G163	74163

OrCAD Function:	MAX+PLUS II Function:

G164	74164

G169	74169

G174	74174

G175	74175

G180	74180

G183	74183o

G194	74194

G195	74195

G240	74240o

G241	74241

G244	74244

G251	74251

G253	74253

G257	74257

G258	74258

G260	nor5

G273	74273

G280	74280

G298	74298

G352	74352o

G365	74365

G366	74366

G367	74367

G368	74368

G373	74373

OrCAD Function:	MAX+PLUS II Function:

G374	74374

G375	74375

G445	74445

G465	74465

G466	74466

G467	74467

G468	74468

G540	74540

G541	74541

AND#	AND#	(#=2,3,4,5,6,7,8,9,12)

NAND#	NAND#	(#=2,3,4,5,6,7,8,9,12)

NOR#	NOR#	(#=2,3,4,5,6,8,12)

NOT	NOT

OR#	OR#	(#=2,3,4,5,6,8,12)

TRI	TRI

XOR2	XOR

XNOR2	XNOR


Viewlogic Library Mapping File (vwl_bas.lmf)

The Viewlogic-compatible Library Mapping File provided by Altera, vwl_bas.lmf, is automatically installed in the \maxplus2\lmf directory. This file maps Viewlogic basic and LSTTL functions to the following MAX+PLUS II primitives and macrofunctions. Function names are shown here in capital letters, but appear with lowercase letters in the LMF:

See also:

Guidelines for Workstation Help Users

Recommended reading:

Viewlogic Powerview & MAX+PLUS II Software Interface Guide

AB30 (Viewlogic Workview PLUS & MAX+PLUS II Logic Design)

AB96 (Generating Library Mapping Files)

Viewlogic Function:	MAX+PLUS II Function:

74LS00	7400

74LS02	7402

74LS04	7404

74LS08	7408

74LS10	7410

74LS11	7411

74LS20	7420

74LS21	7421

74LS27	7427

74LS28	7428

74LS30	7430

74LS32	7432

74LS37	7437

74LS40	7440

74LS42	7442

74LS51	7451

74LS54	7454

74LS55	7455

74LS73A	7473a

74LS74A	dff2

74LS75	7475

74LS76A	7476a

74LS77	7477

74LS78A	7478a

74LS83A	7483

Viewlogic Function:	MAX+PLUS II Function:

74LS85	7485

74LS86	7486

74LS90	7490

74LS91	7491

74LS92	7492

74LS93	7493

74LS95B	7495

74LS96	7496

74LS107A	74107a

74LS109A	74109

74LS112A	74112

74LS113A	74113

74LS114A	74114

74LS126A	tri

74LS133	74133

74LS138	74138

74LS139	74139m

74LS147	74147

74LS148	74148

74LS151	74151

74LS153	74153

74LS155A	74155

74LS156	74156

74LS157	74157

74LS158	74158

Viewlogic Function:	MAX+PLUS II Function:

74LS160A	74160

74LS161A	74161

74LS162A	74162

74LS163A	74163

74LS164	74164

74LS165	74165

74LS166	74166

74LS169	74169

74LS173A	74173

74LS174	74174

74LS175	74175

74LS181	74181

74LS183	74183

74LS190	74190

74LS191 	74191

74LS192	74192

74LS193	74193

74LS194A	74194

74LS195A	74195

74LS196	74196

74LS197	74197

74LS240	74240

74LS241	74241

74LS244	74244

74LS251	74251

Viewlogic Function:	MAX+PLUS II Function:

74LS253	74253

74LS257	74257

74LS258	74258

74LS259	74259

74LS260	74260

74LS266	xnor

74LS273	74273

74LS279	74279

74LS280	74280

74LS283	74283

74LS290	74290

74LS293	74293

74LS299	74299

74LS348	74348

74LS353	74353

74LS365A	74365

74LS366A	74366

74LS367A	74367

74LS368A	74368

74LS373	74373

74LS374	74374

74LS377	74377

74LS379	74379

74LS381	74381

74LS390	74390

Viewlogic Function:	MAX+PLUS II Function:

74LS393	74393

AL_DFF	dff

AL_LATCH	latch

AL_LATRS	mlatch

AL_NOT	not

AL_TRI	tri

AND#	and#	(# = 2, 3, 4, 8)

ANDNOR22	2a2nor2

BUF	soft

CARRY	carry

CASCADE	cascade

DAND#	dand#	(# = 2, 3, 4, 8)

DELAY	lcell

DFFE	dffe

DOR#	dor#	(# = 2, 3, 4, 8)

DXOR#	dxor#	(# = 2, 3, 4, 8)

AL_AND#	and#	(# = 2, 3, 4, 5, 6, 8, 12)

AL_NAND#	nand#	(# = 2, 3, 4, 5, 6, 8, 12)

AL_OR#	or#	(# = 2, 3, 4, 5, 6, 8, 12)

AL_NOR#	nor#	(# = 2, 3, 4, 5, 6, 8, 12)

AL_XOR2	xor

AL_XNOR2	xnor

AL_NAN12	nand12

EXP	exp

GLOBAL	global

JKFFRE	jkffre

LCELL	lcell

MCELL	mcell

MUX41	mux41

NAND#	nand#	(# = 2, 3, 4, 8)

NOR#	nor#	(# = 2, 3, 4, 8)

NOT	not

Viewlogic Function:	MAX+PLUS II Function:

OR#	or#	(# = 2, 3, 4, 8)

SCLK	sclk

SOFT	soft

TRIAND#	tand#	(# = 2, 3, 4, 8)

TRIBUF	tribuf

TRINAND#	tnand#	(# = 2, 3, 4, 8)

TRINOR#	tnor#	(# = 2, 3, 4, 8)

TRINOT	trinot

TRIOR#	tor#	(# = 2, 3, 4, 8)

UBDEC38	dec38

UDFDL	udfdl

UJKFF	ujkff

XNOR#	xnor#	(# = 3, 4, 8)

XNOR2	xnor

XOR#	xor#	(# = 3, 4, 8)

XOR2	xor

A_81MUX	81mux

A_8COUNT	8count

A_8MCOMP	8mcomp

A_8FADD	8fadd

81MUX	81mux

8COUNT	8count

8MCOMP	8mcomp

8FADD	8fadd


-----BEGINNING OF NON-TRANSLATED TEXT-----

Messages in x2cmsgs.msg that are documented elsewhere (not in this file):

ex2c_syntax_error	comess.mac

wx2c_nodename_truncated	ntinmess.mac

-----END OF NON-TRANSLATED TEXT-----


Externally connect pins to emulate internal tri-state bus

CAUSE:	An XNF File contains internal tri-state buses, which have been emulated using the device pins.

ACTION:	After programming the device(s) for the project, connect the specified pins. Refer to the Report File for the device pin-outs.

See also:

File Structure Requirements for XNF Files

MAX+PLUS II Messages

Message Format


File <name> was not generated by the LCA2XNF utility [or has no outputs or inputs
File <name> was not generated by the LCA2XNF utility [or has no outputs or inputs]

CAUSE:	The specified XNF File was not generated by the LCA2XNF utility, or contains no input or output signals. XNF Files can be processed by the MAX+PLUS II Compiler only if they are the output of this utility and contain design logic.

ACTION:	Re-create the XNF File by running LCA2XNF with the -g option before recompiling the project.

See also:

Compiling XNF Files

File Structure Requirements for XNF Files

MAX+PLUS II Messages

Message Format


I/O pin <name> has no source or destination

CAUSE:	The XNF File contains an external I/O pin that is unconnected.

ACTION:	If you intended to use the pin, connect it to a source or destination.

See also:

Compiling XNF Files

File Structure Requirements for XNF Files

MAX+PLUS II Messages

Message Format


Ignored power-on preset for flipflop <name>

CAUSE:	An XNF File contains a flipflop that is set to power up to a Preset state, which is not supported in Altera devices. Therefore, the Compiler has ignored the preset.

ACTION:	No action is required.

See also:

File Structure Requirements for XNF Files

MAX+PLUS II Messages

Message Format


Logic contains an internal <text>: connect external <text> to pin <name>

CAUSE:	The XNF File contains an internal oscillator, pull-up resistor, or pull-down resistor, features that are not available in Altera devices. Therefore, the Compiler has implemented the desired functionality by connecting the node that was driven by the internal oscillator, pull-up resistor, or pull-down resistor to a pin, which can be connected to an external oscillator, pull-up resistor, or pull-down resistor.

ACTION:	After programming the device(s) for the project, connect the specified pin to an external oscillator, pull-up resistor, or pull-down resistor. Refer to the Report File for the device pin-outs.

See also:

Compiling XNF Files

File Structure Requirements for XNF Files

Report File Format

MAX+PLUS II Messages

Message Format


-----BEGINNING OF NON-TRANSLATED TEXT-----

The following message should get reworded to start with "Your current project" instead of with "This project" and then change it in messlist

-----END OF NON-TRANSLATED TEXT-----


This project was originally created for a Xilinx device. etc.
This project was originally created for a Xilinx device. To achieve the best device performance and utilization, Altera recommends switching to an Altera design entry method.

CAUSE:	Your project contains one or more XNF File. Since these files are created without the specific advantages of Altera-provided design entry methods and macrofunctions, compiling them with MAX+PLUS II may not yield the best possible results.

ACTION:	Altera recommends re-creating your design with an Altera design entry method. If you chose to generate an AHDL Text Design Export File, you may wish to modify this file as a starting point.

See also:

AHDL Help Contents

MAX+PLUS II Messages

Message Format


Too many nodes in file

CAUSE:	The current Xilinx Netlist Format File contains too many node names. The XNF Netlist Reader can process up to 512,000 bytes of node name information.

ACTION:	Try flattening the original design hierarchy so that no single file has over 512,000 bytes of name information.

See also:

MAX+PLUS II Messages

Message Format


XNF symbol <name> (named <name>) is not supported by Altera devices

CAUSE:	An XNF File contains the specified symbol, which is not supported by Altera devices.

ACTION:	Remove the specified symbols from the XNF File.

See also:

File Structure Requirements for XNF Files

MAX+PLUS II Messages

Message Format


Ignored symbol <name>

CAUSE:	An XNF File contains the specified symbol, which is not supported by MAX+PLUS II. Therefore, MAX+PLUS II has ignored the symbol.

ACTION:	No action is required. To avoid this message, remove the specified symbol from the XNF File.

See also:

File Structure Requirements for XNF Files

MAX+PLUS II Messages

Message Format


Waveform Editor Basic Tools
Basic Tools

Cursors & Buttons

Cursor Movement Buttons

Reference Cursor

Waveform Selection Buttons

Display Controls

Grid

Input & Output Files

Assignment & Configuration File (.acf)

ACF Format

Include File (.inc)

Simulator Channel File (.scf)

Simulator Netlist File (.snf)

Symbol File (.sym)

Table File (.tbl)

Vector File (.vec)

Vector File Format

Waveform Design File (.wdf)

MAX+PLUS II Initialization & System Files

maxplus2.idx File

maxplus2.ini File

Mouse Behavior

Nodes & Groups

Input Nodes

Output Nodes

Buried Nodes

Groups

Node/Group Information Area

Name Field

Node/Group Handle

Type Field

Value Field

Comments

Probe, Resource & Device Assignments

Clique Assignments

Connected Pin Assignments

Device Assignments

Guidelines for Timing Assignments

Logic Option Assignments

Pin, Location & Chip Assignments

Probe Assignments

Timing Assignments

Status Bar, Toolbar & Tool Palette

Status Bar

Toolbar

Tool Palette

Selection Tool

Text Tool

Waveform Editing Tool

Time Information

Time Field

Reference (Ref) Field

Interval Field

Start Field

End Field

Time Scale

Waveforms

Group (Bus)

High (1)

High-Impedance (Z)

Low (0)

State Machine

Undefined/Don’t Care (X)

Waveform Separator


Cursor Movement Buttons (Waveform Editor)
Cursor Movement Buttons

Move the Reference cursor right or left to the next or previous logic level transition. Show me

The Waveform Editor provides a pair of cursor movement buttons to the right of the Reference (Ref) field. These buttons are active only if no waveform interval is selected in the waveform drawing area, so that the Time field and Reference field are visible, rather than the Start field and End field.

You can click Button 1 on a cursor movement button to move the cursor to the next transition on a selected node or group. If more than one node or group is selected, the cursor moves to the next transition found on any of the selected items. If no nodes or groups are selected, the cursor moves to the next transition found on any node or group in the file.

When an interval on one or more waveforms is selected and the Time and Reference fields have changed into the Start and End fields, the cursor movement buttons change into waveform selection buttons.

See also:

Finding a Transition

Moving the Reference Cursor

Selecting a Node or Group


Reference Cursor (Waveform Editor)
Reference Cursor

The Reference cursor is a solid vertical cursor line that appears in the waveform drawing area. Show me

The time at the top of the cursor and the Reference (Ref) field show the current location of the Reference cursor; the Value field shows all node and group logic levels or state names at this location.

The Reference cursor also shows the current insertion point for waveform editing as a short horizontal line. The cursor and insertion point move whenever you click Button 1 in the waveform drawing area. You can also move the cursor with the cursor movement buttons, the square cursor handle that appears above its junction with the Time scale, or the Find Next Transition, Find Previous Transition, and Go To commands on the Utilities menu.

See also:

Finding a Transition

Moving the Reference Cursor


Waveform Selection Buttons (Waveform Editor)
Waveform Selection Buttons

Extend or shorten the current waveform selection left or right to the next logic level transition. Show me

The Waveform Editor provides a pair of waveform selection buttons, which appear between the Start field and End field. The Start and End fields, as well as the waveform selection buttons, are active and appear only when you have already selected a waveform interval on one or more nodes and/or groups.

Clicking Button 1 on the left or right waveform selection buttons increases or decreases the size of the selected interval based on the next logic level transition.

When no waveform interval is selected, the Start and End fields change into the Time field and Reference (Ref) field, and the waveform selection buttons change into cursor movement buttons.

See also:

Selecting a Waveform


Grid (Waveform Editor)
Grid

A series of dotted vertical lines that provide a visual time reference for selecting and editing waveforms. Show me

You can turn the grid on or off by choosing Snap to Grid (Options menu). When Snap to Grid is on, selections and transitions that you enter, edit, or move are "magnetically" pulled to the nearest grid line. You can turn Snap to Grid on and off in an SCF; it is always turned on in a WDF to help you align transitions.

The grid line spacing also determines the display scale for Normal Size (View menu).

Grid Size (Options menu) allows you to specify any grid size; Show Grid (Options menu) displays the grid. As you zoom out and the view of the file is reduced, grid lines may no longer be visible.

See also:

Aligning Transitions to the Grid

Changing the Grid Size

Showing the Grid

Snapping to the Grid

Zooming In & Out


Simulator Channel File (.scf) Description
Simulator Channel File (.scf)

A binary file (with the extension .scf) that describes simulation or functional testing input vectors and simulation outputs as graphical waveforms.

The SCF can be viewed and edited in the Waveform Editor. This file is both an input and output file of the Simulator. During functional testing in either the Simulator or Programmer, it is an input file only. An SCF with the same filename as the project is loaded automatically in either application; you can use Inputs/Outputs (File menu) to specify files with other names.

You can create an SCF for simulation or functional testing with the MAX+PLUS II Waveform Editor. The Enter Nodes from SNF and Insert Node commands (Node menu) allow you to generate an SCF directly from the node and group names in the SNF for the project. The default SCF contains any user-specified combination of nodes, state machines, and groups (buses) in the compiled project, which can then be edited to provide the vector inputs.

In the Waveform Editor, you can create an SCF by importing a Vector File with the Import Vector File command (File menu). The Simulator creates an SCF automatically when you use a Vector File as the source of input vectors. The Simulator creates and/or overwrites any existing SCF with the same filename as the Vector File before simulation or functional testing begins. In the Programmer, the vectors in the Vector File or programming file are converted into a temporary data buffer with the same format as an SCF before functional testing begins.

The SCF specifies input logic levels that drive the input pins and determine the internal logic levels throughout the project. Inputs without vectors are automatically assigned X (undefined) logic levels during simulation or 0 (low) logic levels during functional testing.

The SCF also includes the names of any combination of output nodes in the project, including buried nodes. When you use an SCF for simulation or functional testing, the logic levels that are appropriate to include for output nodes may vary (less likely uses are shown in parentheses):

SCF Outputs:	Appropriate Function:

undefined (X)	Simulation

user-defined outputs	Simulation with output monitoring (functional testing)

simulation outputs	Functional testing or simulation with output monitoring

actual device outputs	Functional testing (simulation with output monitoring)

During simulation or functional testing, input waveforms remain unchanged. The output and buried logic levels in the file are updated or are preserved and compared to other outputs according to SCF output overwriting rules. You may switch from one SCF to another during a simulation session, although only one file can be used at any given time.

When you perform simulation, you can watch the simulated outputs as they are written to the SCF if the Waveform Editor is displaying the file. However, you cannot edit the SCF during simulation. Displaying the SCF as it is being updated also increases the time it takes to simulate the project.

An SCF is always used for simulation or functional testing; however, you can save it as a WDF and edit it to create a design file (or vice versa). When you save an SCF as a WDF, the nodes in the file are assigned default node types: input nodes have pin input node types, and output and buried nodes have combinatorial node types.

The following information will help you create and interpret SCFs effectively:

Functional Testing with the SCF, Vector File, or Programming File

Output Monitoring Requirements for the SCF or Vector File

Propagation of Undefined Logic Levels

Simulating Bidirectional Pins

The icon for an SCF with the same filename as the top-level design file in the current hierarchy tree appears in the Hierarchy Display window.

See also:

Checking Simulation Outputs vs. User-Specified Outputs

Creating a Default Channel File

Importing a Vector File

Saving Actual Device Outputs

Specifying the Source of Input Vectors (Programmer)

Specifying the Source of Input Vectors (Simulator)

Testing Device Outputs vs. Simulation Outputs


Waveform Design File (.wdf) Description
Waveform Design File (.wdf)

A binary file (with the extension .wdf) containing design logic that is defined by a combination of waveforms.

The WDF is a design file that creates logic by specifying various combinations of input signals and desired output signals. It contains nodes that represent input pins, output pins, and buried logic. The type of logic that a node represents is further categorized as fed by pin input, combinatorial, registered, or state machine logic.

A WDF represents logic with high (1), low (0), undefined (X), and high-impedance (Z) waveforms. For a node that represents a state machine, the waveform contains the names of states.

In the WDF, you create as many different combinations of input logic levels as possible, and specify the outputs that you wish to obtain. You can include intermediate buried logic nodes to further define the operation of the circuit design, and specify which nodes are to be used as the Clock, Reset, and Preset inputs to state machine or registered nodes.

A WDF can be used to define all logic in a project, or can be used to define a bottom-level file in a hierarchical project. MAX+PLUS II automatically creates a Symbol File that represents a WDF when you choose Create Default Symbol (File menu). This symbol and the logic it represents can be incorporated into a GDF.

You can use WDF logic in an AHDL TDF by including a Function Prototype and inserting an instance of the macrofunction into the TDF. You can also automatically generate a default Include File that contains a Function Prototype for a WDF with Create Default Include File (File menu).

A WDF is always a design file; however, you can save it as a Simulator Channel File and edit it to provide the inputs for simulation. When you save a WDF as an SCF, information on the node type is no longer meaningful and is not displayed in the Waveform Editor window.

The file icon for each WDF that is part of the current hierarchy tree appears in the Hierarchy Display window.

See also:

Creating & Using Custom Macrofunctions (AHDL)

Creating a Default Include File

Creating a Waveform Design File

Creating the Default Symbol for a File


Mouse Behavior (Waveform Editor)
Mouse Behavior

Use a two- or three-button mouse for the Waveform Editor.

Button 1 corresponds to the left mouse button. Button 2 corresponds to the right button on a two-button mouse or the middle and right buttons on a three-button mouse.

You can use Button 1 to:

Choose a command, dialog box options, and buttons.

Choose toolbar and tool palette buttons.

Select, edit, move, and/or copy nodes and groups.

Select, edit, move, and/or copy whole waveforms or waveform intervals.

Select and edit text in a dialog box.

Define an insertion point for a node, group, waveform, waveform separator or comment.

Change the width of the Name, Type, and Value fields.

Move the Reference cursor.

You can use Button 2 to pop-up a context-sensitive menu containing commands that will operate on the current selection. If no other item is selected and you click Button 2 on a node handle, group handle, node name, group name, node type, or a value in the Value field, it also selects the item before popping up the context-sensitive menu.

Refer to Waveform Editor Procedures for step-by-step instructions that describe how to manipulate nodes, groups, and other items in the Waveform Editor.


Input Nodes (Waveform Editor)
Input Nodes

Nodes representing input logic driven by a pin or a state machine.

An input node consists of a node handle that shows its I/O type, a node name, and a waveform. In a WDF, the node type also appears in the Type field. Show me

In an SCF, an input node is an input vector that is used for simulation or functional testing. It can represent an input pin or the portion of a bidirectional pin that drives in.

In a WDF, an input node represents logic driven by an input pin or a state machine. Input nodes in a WDF are created and edited according to the following rules:

General Guidelines

State Machine Node Rules

The waveforms of input nodes (other than machine-type nodes) can have low (0), high (1), undefined (X), and high-impedance (Z) logic levels. The waveform of a node with a node type of machine contains the names of states and represents the different states of a state machine. An input state machine node represents a state machine that is defined in (i.e., imported from) another design file of the project. A state machine waveform is not a group, and cannot be ungrouped. However, state machine bits created in a project’s design files are combined into a group by the Compiler and appear as a group in a default SCF. Therefore, a state machine node in a WDF can "become" a group in the SCF after the project has been compiled. However, this type of group is not a state machine and cannot be changed into a state machine node.

You can create a new node with Insert Node or change the node name, default value, or I/O type of an existing node with Edit Node (Node menu). You can also add a node from a project’s SNF to an SCF with Enter Nodes from SNF or Insert Node (Node menu). In addition, you can combine multiple input nodes to create a group.

See also:

Changing the Node Type, I/O Type, Secondary Inputs, or Default Value

Creating a Group

Creating a Node

Creating a Waveform Design File

Renaming a Node or Group

Recommended reading:

AN28 (Waveform Design Entry)

AB92 (Simulating Internal Nodes with MAX+PLUS II Software)


Output Nodes (Waveform Editor)
Output Nodes

Nodes representing output logic that feeds an output pin or a state machine.

An output node consists of a node handle that shows its I/O type, a node name, and a waveform. In a WDF, the node type also appears in the Type field. Show me

In an SCF, output node waveforms can represent user-defined expected outputs, outputs generated by simulation, or outputs read from a programmed device. An output node can be a pin that generates a signal on a device or the portion of a bidirectional pin that drives out.

In a WDF, an output node represents logic that feeds an output pin. Output nodes can be further defined as driven by combinatorial, registered, or state machine logic. For registered output and machine nodes, a required Clock signal and optional Preset and Reset signals are specified as secondary inputs. Output nodes in a WDF are created and edited according to the following rules:

General Guidelines

Combinatorial Node Rules

Registered Node Rules

State Machine Node Rules

The waveforms of output nodes (other than machine-type nodes) can have low (0), high (1), undefined (X), and high-impedance (Z) logic levels. The waveform of a node with a node type of machine contains the names of states and represents the different states of a state machine. An output state machine node is a state machine in the current WDF that can be exported to other design files. A state machine waveform is not a group, and cannot be ungrouped. However, state machine bits created in a project’s design files are combined into a group by the Compiler and appear as a group in a default SCF. Therefore, a state machine node in a WDF can "become" a group in the SCF after the project has been compiled. However, this type of group is not a state machine and cannot be changed into a state machine node.

You can create a new node or change the node name, default value, or I/O type of an existing node with Insert Node (Node menu). You can also add a node from a project’s SNF to an SCF with Enter Nodes from SNF or Insert Node (Node menu). In addition, you can combine multiple output nodes to create a group.

See also:

Changing the Node Type, I/O Type, Secondary Inputs, or Default Value

Creating a Group

Creating a Node

Creating a Waveform Design File

Renaming a Node or Group

Recommended reading:

AN28 (Waveform Design Entry)

AB92 (Simulating Internal Nodes with MAX+PLUS II Software)


Buried Nodes (Waveform Editor)
Buried Nodes

Nodes representing logic that does not drive out to a pin.

A buried node consists of a node handle that shows its I/O type, a node name, and a waveform. In a WDF, the node type also appears in the Type field. Show me

In an SCF, buried node waveforms can represent user-defined expected buried outputs or outputs generated by simulation.

In a WDF, buried logic--consisting of combinatorial, registered, or state machine logic--is optional. It is used only to indicate the type of logic that may exist between the inputs and outputs. For registered and machine nodes, a required Clock signal and optional Preset and Reset signals are specified as secondary inputs. Buried nodes in a WDF are created and edited according to the following rules:

general guidelines

combinatorial node rules

registered node rules

state machine node rules

The waveforms of buried nodes (other than machine-type nodes) can have low (0), high (1), and undefined (X) logic levels. The waveform of a node with a node type of machine contains the names of states and represents the different states of a state machine. A buried-type state machine can be used to define additional logic that exists between inputs and outputs. A state machine waveform is not a group, and cannot be ungrouped. However, state machine bits created in a project’s design files are combined into a group by the Compiler and appear as a group in a default SCF. Therefore, a state machine node in a WDF can "become" a group in the SCF after the project has been compiled. However, this type of group is not a state machine and cannot be changed into a state machine node.

For registered buried nodes, a Clock signal and optional Preset and Reset signals can be specified as secondary inputs. Since registered-type nodes are clocked, changes on inputs that affect these nodes require a non-zero time-slice to provide the setup time; the minimum setup time is 0.1 ns.

You can create a new node or change the node name, default value, or I/O type of an existing node with Insert Node. You can also add a node from a project’s SNF to an SCF with Enter Nodes from SNF or Insert Node (Node menu). In addition, you can combine multiple buried nodes to create a group.

See also:

Changing the Node Type, I/O Type, Secondary Inputs, or Default Value

Creating a Group

Creating a Node

Creating a Waveform Design File

Renaming a Node or Group

Recommended reading:

AN28 (Waveform Design Entry)

AB92 (Simulating Internal Nodes with MAX+PLUS II Software)


Groups (Waveform Editor)
Groups

A combination of up to 256 nodes that are displayed and treated as a unit.

A group can be included in another group, but each member of the group is counted towards the 256-node maximum.

A group consists of a group handle that shows its I/O type, a name in arbitrary group name or single-range group name format, and a waveform. In a WDF, the node type also appears in the Type field. Show me

A group has no special meaning in a WDF or an SCF. It is simply a convenience for representing multiple nodes. A group always consists of nodes with the same I/O type. In a WDF, nodes must also have the same node type and secondary inputs. However, in a WDF, machine-type nodes cannot be grouped.

A group waveform shows the combined logic levels of its member nodes. A group that consists of the bits of a state machine created in the project’s design files can appear in the default SCF. In this type of group, the group value shown within the waveform can be represented as either a logic level or as an equivalent state name. The radix used to display the group value is shown in the Value field.

You can use Enter Group (Node menu) to create a new group or to change the group name or radix. You can use Insert Node (Node menu) to create a new single-range group, and Edit Node to change the default value, I/O type, or node type of an existing group. You can also add a group from a project’s SNF to an SCF with Enter Nodes from SNF or Insert Node (Node menu).

See also:

Changing the Group Radix

Changing the Node Type, I/O Type, Secondary Inputs, or Default Value

Creating a Group

Creating a Waveform Design File

Recommended reading:

AN28 (Waveform Design Entry)


Name Field (Waveform Editor)
Name Field

Shows the names of each node and group (bus), including state machine nodes, in the current file, and allows you to select a whole node or group rather than a waveform interval. Show me

In a default SCF, probes that are assigned in design files for the project also appear as nodes in the Name field.

The Name field also includes a square resizing handle on its top right corner that you can drag right or left to increase or decrease the width of the field.

Double-clicking Button 1 in a blank space in the Name field allows you to insert a new node with Insert Node (Node menu). Double-clicking Button 1 on an existing name allows you to change characteristics of the node or group with Edit Node or Enter Group (Node menu). Dragging Button 1 through the Name field selects multiple adjacent whole nodes, comment lines, and/or blank lines.

You can control the colors used to display node and group names in the Name field with Color Palette (Options menu).

See also:

Changing the Width of the Name, Type & Value Fields

Copying, Cutting & Pasting Nodes and Groups

Creating a Group

Creating a Node

Deleting a Node or Group

Renaming a Node or Group

Selecting a Node or Group


Node/Group Handle (Waveform Editor)
Node/Group Handle

Shows the I/O type of the node or group, and allows you to select and move, copy, or delete the whole node or group.

Handle:	Type:

Input Node

Output Node

Buried Node

Input Group

Output Group

Buried Group

Text

The node/group handle appears on the far left side of the window, next to the node or group name. It shows whether the node or group represents input pins, output pins, buried logic, or a block of text. Show me

The I/O type of a node is initially defined when you create it with Insert Node (Node menu); it can be modified with Edit Node (Node menu). A group always consists of members of the same I/O type.

Double-clicking Button 1 on the handle allows you to change an existing node or group with Edit Node or Enter Group (Node menu). Dragging the handle with Button 1 allows you to move a node or group.

See also:

Changing the Node Type, I/O Type, Secondary Inputs, or Default Value

Copying, Cutting & Pasting Nodes and Groups

Creating a Group

Creating a Node

Deleting a Node or Group

Moving Nodes & Groups

Selecting a Node or Group

Type Field

Ungrouping a Group


Type Field (Waveform Editor)
Type Field

Shows the type of logic that drives the node or group in a WDF, and allows you to select a whole node or group (rather than a waveform interval). Show me

The Type field displays the node type. It is relevant only to a WDF and does not appear in an SCF. However, if you save an SCF as a WDF, the Type field appears.

The node type is initially defined when you create a node with Insert Node (Node menu); it can be modified with Edit Node (Node menu). A group always consists of members of the same node type and I/O type.

The Type field also includes a square resizing handle on its top right corner that you can drag right or left to increase or decrease the width of the field.

Double-clicking Button 1 in a blank space in the Type field allows you to insert a new node with Insert Node (Node menu). Double-clicking Button 1 on an existing type allows you to change characteristics of the node or group with Edit Node or Enter Group (Node menu). Dragging Button 1 through the Type field selects multiple adjacent whole nodes, comment lines, and/or blank lines.

See also:

Changing the Node Type, I/O Type, Secondary Inputs, or Default Value

Changing the Width of the Name, Type & Value Fields

Creating a Node

Deleting a Node or Group

Selecting a Node or Group


Value Field (Waveform Editor)
Value Field

Shows the logic level (value) or state name of each node, or the radix and logic level of each group, and allows you to select an entire waveform rather than the whole node or group. Show me

The value displayed is the node or group value at the current active Reference cursor location.

The group radix is shown as a letter that precedes the group value:

Letter:	Radix:

B	Binary

D	Decimal

H	Hexadecimal

O	Octal

If the group value is displayed as Gray code, the letter G precedes the radix.

The initial default value or state name of a node is defined when you create it with Insert Node (Node menu). A group’s value is always a combination of its members’ values; you set its radix when you create the group with Enter Group (Node menu).

When you compare a WDF, SCF, or simulation outputs to the current file, the value of the compared node or group appears in parentheses next to the current value in the Value field.

The Value field also includes a square resizing handle on its top right corner that you can drag right or left to increase or decrease the field width.

Double-clicking Button 1 in a blank space in the Value field allows you to insert a new node with Insert Node (Node menu). Double-clicking Button 1 on an existing value allows you to change characteristics of the node or group with Edit Node or Enter Group (Node menu). Dragging Button 1 through the Value field selects multiple adjacent whole waveforms.

See also:

Changing the Group Radix

Changing the Node Type, I/O Type, Secondary Inputs, or Default Value

Changing the Width of the Name, Type & Value Fields

Creating a Node

Deleting a Node or Group

Selecting a Node or Group

Selecting a Waveform


Time Field (Waveform Editor)
Time Field

Shows the time at the current mouse pointer location. Show me

The time in the Time field changes whenever you move the mouse.

The Time field changes into the Start field and End field whenever you select an interval on one or more waveforms with Button 1.

See also:

Moving the Reference Cursor


Reference (Ref) Field (Waveform Editor)
Reference (Ref) Field

Shows the time at the current Reference cursor location. Show me

The time in the Reference field changes whenever you drag the Reference cursor by its handle, or whenever you move the cursor by clicking Button 1 in the waveform drawing area or on its cursor movement buttons.

The Reference field changes into the End field whenever you select or edit an interval on one or more waveforms.

Double-clicking Button 1 in the Reference field opens the Go To dialog box (Utilities menu), which allows you to move the Reference cursor to a specific time.

See also:

Moving the Reference Cursors


Interval Field (Waveform Editor)
Interval Field

The Interval field shows the length of time between the Reference cursor and the mouse pointer when no waveform interval is selected. If an interval is selected, the Interval field shows the length of time between the start and end of the selection. Show me

The Interval field therefore shows the time difference between the values in the Time field and Reference (Ref) field or between the Start field and End field.

The interval is positive (+) if the mouse pointer (or start of the selection) is on the left of the Reference cursor (or end of the selection), and negative (-) if it is on the right.

When no waveform interval is selected, the time in the Interval field changes whenever you move the mouse pointer. When you are selecting or editing a waveform interval, the time in the field changes as you drag Button 1.

See also:

Moving the Reference Cursor

Selecting a Waveform


Start Field (Waveform Editor)
Start Field

Shows the time at the beginning of the currently selected waveform interval. Show me

The Start field appears whenever you drag Button 1 to select or edit a time interval on one or more waveforms. The time in the field changes as you change the size of the selection by dragging Button 1, or by clicking Button 1 on the waveform selection buttons. The Start field changes into the Reference (Ref) field when no interval is selected.

The Interval field shows the length of time between the Start field and the End field.

See also:

Selecting a Waveform


End Field (Waveform Editor)
End Field

Shows the time at the end of the currently selected waveform interval. Show me

The End field appears whenever you drag Button 1 to select a time interval on one or more waveforms. The time in the field changes as you change the size of the selection by dragging Button 1, or by clicking Button 1 on the waveform selection buttons. The End field changes into the Time Field when no interval is selected.

The Interval field shows the length of time between the Start field and the End field.

See also:

Selecting a Waveform


Comments (Waveform Editor)
Comments

The Waveform Editor allows you to enter text in the waveform drawing area. For example, you can use these comments to help describe the function of sections of your design or keep track of critical notes.

Comments are identified in a design file with a special node handle ( [image]).

See also:

Text Tool

Selecting a Waveform


Time Scale (Waveform Editor)
Time Scale

Shows the portion of time represented by the waveforms in the current window. Show me

Time is expressed with time units. The time scale displays at least two reference points, which may not necessarily correspond to grid lines. The currently displayed time scale is controlled with the following View menu commands and buttons:

Command/Button:	Action:

Fit in Window command	Shows the entire waveform of each node or group displayed on the screen. Shortcuts

Zoom In command	Zooms in to a more detailed view of the waveforms. Shortcuts

Zoom Out command	Zooms out to a less detailed view of the waveforms. Shortcuts

Normal Size command	Displays waveforms at a scale that is dependent on the current grid size. Shortcuts

Maximum Size command	Displays detail down to 0.1 ns. Shortcuts

The portion of time displayed in the window is controlled by the zooming commands, scrolling, and/or the following commands:

Command:	Action:

Go To (Utilities menu)	Scrolls to and displays a specified point in time. Shortcuts

Time Range (View menu)	Displays a specified time period. Shortcuts

See also:

Changing the Grid Size

Fitting a File into the Window

Going to a Specific Time

Going to a Time Range

Zooming In & Out


Group (Bus) Waveform (Waveform Editor)
Group (Bus) Waveform

Shows the logic level (value) and transition times of a group. Show me

A group waveform shows the combined logic levels of its member nodes. The value of the group is shown within the waveform; its radix and value at the current Reference cursor location are shown in the Value field. In a group that represents a state machine in an SCF, the group value shown within the waveform can be represented as either a logic level or as an equivalent state name that was defined in the project’s design files.

The members of a bus, group, or array created in a design file can appear as a group in the default SCF for a project. The bits of a state machine that is created in a project’s design files are combined into a group by the Compiler and can also appear as a group waveform in a default SCF. Therefore, a node with the machine (MACH) node type in a WDF can "become" a group waveform in the SCF after the project has been compiled. However, a group of state machine bits in an SCF is not a state machine and cannot be changed into a state machine-type node.

A group waveform has no special meaning in a WDF or an SCF. It is simply a convenience for representing multiple signals.

You can use Color Palette (Options menu) to assign a particular color to group waveforms to distinguish them from node and state machine waveforms.

See also:

Changing the Group Radix

Copying, Cutting & Pasting Waveforms

Creating a Group

Inserting a Count Value on a Waveform

Inserting a Group Value on a Waveform

Overwriting a Count Value on a Waveform

Overwriting a Group Value on a Waveform

Selecting a Waveform

Ungrouping a Group

Recommended reading:

AN28 (Waveform Design Entry)

AB92 (Simulating Internal Nodes with MAX+PLUS II Software)


Low, High, Undefined & High-Impedance (0, 1, X, Z) Waveforms (Waveform Editor)
Low (0), High (1), Undefined/Don’t Care (X) & High-Impedance (Z) Waveforms

The 0, 1, X, and Z waveforms show the logic levels of individual input, output, and buried nodes (other than state machine-type nodes). Show me

You can use Color Palette (Options menu) to assign a particular color to node waveforms to distinguish them from group and state machine waveforms.

See also:

Copying, Cutting & Pasting Waveforms

Creating a Node

Deleting a Waveform

Inserting a Count Value on a Waveform

Inserting a Node Waveform with a Low, High, Undefined, or High Impedance Logic Level

Moving a Transition

Overwriting a Count Value on a Waveform

Overwriting a Node Waveform with a Low, High, Undefined, or High Impedance Logic Level

Selecting a Waveform

Recommended reading:

AN28 (Waveform Design Entry)

AB92 (Simulating Internal Nodes with MAX+PLUS II Software)


State Machine Waveform (Waveform Editor)
State Machine Waveform

Shows the state names of a state machine, on a node of the type MACH (machine) in a WDF. Show me

The name of the current state is shown within the waveform; the state name at the current Reference cursor location is shown in the Value Field.

A state machine-type node can appear only in a WDF, not in an SCF.

A state machine waveform represents the different states of a state machine. In a WDF, it is not a group, and cannot be ungrouped. However, state machine bits created in a project’s design files are combined into a group by the Compiler and appear as a group waveform in a default SCF. Therefore, a state machine waveform in a WDF can "become" a group waveform in the SCF after the project has been compiled. In a group that represents a state machine, the group value shown within the waveform can be represented as either a logic level or as an equivalent state name that was defined in the project’s design files. However, this type of group is not a state machine and cannot be changed into a state machine waveform.

You can use Color Palette (Options menu) to assign a particular color to state machine waveforms to distinguish them from other node and group waveforms.

See also:

Copying, Cutting & Pasting Waveforms

Creating a Node

Deleting a Waveform

Inserting a State Name on a Waveform

Moving a Transition

Overwriting a State Name on a Waveform

Recovering from Illegal States

Selecting a Waveform

Recommended reading:

AN28 (Waveform Design Entry)

AB92 (Simulating Internal Nodes with MAX+PLUS II Software)


Waveform Separator (Waveform Editor)
Waveform Separator

A thin vertical line that indicates that the logic levels before the line have no logical relationship to those after the line. Show me

A waveform separator is meaningful only in a WDF, not in an SCF. You can use multiple separators in a single file. The waveform separator marks the beginning of a new and independent sequence of waveforms. It affects nodes with a node type of REG or MACH only.

The waveform separator has a square handle at its junction with the time scale. You can use this handle to select and delete the waveform separator.

You can use the Enter Separator command (Node menu) to create or change a waveform separator.

You can also use Color Palette (Options menu) to assign a particular color to the waveform separator, to distinguish it from the Reference cursor.

See also:

Creating & Deleting a Waveform Separator

Recommended reading:

AN28 (Waveform Design Entry)


Tool Palette (Waveform Editor)
Tool Palette

Displays buttons that allow you to execute commands quickly

The tool palette is displayed on the left side of the MAX+PLUS II window. You can use the tool palette to choose a button as a shortcut to entering a command and to select a working palette tool for design entry and edit.

Click Button 1 on any item in this tool palette for information on that item:

If you point to an item on the tool palette and the status bar is turned on, the status bar displays a brief description of that item.


Selection Tool (Waveform Editor)
Selection Tool

Allows you to perform manipulatory functions on nodes, groups, waveforms, and/or waveform intervals in the Waveform Editor.

With the Selection tool, you can:

Select, edit, move, and/or copy nodes and groups.

Select, edit, move, and/or copy whole waveforms or waveform intervals.

Define an insertion point for a node, group, waveform, waveform separator or comment.

Change the width of the Name, Type, and Value fields.

Move the Reference cursor.

See also:

Tool Palette

Text tool

Waveform Editing tool


Text Tool (Waveform Editor)
Text Tool

Allows you to enter and edit text in the Waveform Editor.

You can use the Text tool to edit node or group names by pressing Button 1 and dragging the mouse over the text you wish to edit.

You can also use the Text tool to enter comments in the waveform drawing area. For example, you can use comments to help describe the function of sections of your design or keep track of critical notes.

Comments are identified in a design file with a special node handle ( [image]).

When you enter a comment at a specific time point, it remains tied to that point, regardless of how far you zoom in or out.

See also:

Tool Palette

Selection tool

Waveform Editing tool

Comments


Waveform Editing Tool (Waveform Editor)
Waveform Editing Tool

Allows you to edit waveforms, waveform intervals, and waveform transitions in the Waveform Editor.

With the Waveform Editing tool, you can:

Select, edit, move, and/or copy nodes and groups.

Select, edit, move, and/or copy whole waveforms or waveform intervals.

See also:

Tool Palette

Selection tool

Text tool


Waveform Editor--Context-Sensitive Help
Waveform Editor Context-Sensitive Help

Context-sensitive help is available for all Waveform Editor commands, dialog boxes and messages, and the following basic tools:

Comments

Cursors & Buttons

Cursor Movement Buttons

Reference Cursor

Waveform Selection Buttons

Display Controls

Grid Lines

Nodes & Groups

Name Field

Node/Group Handle

Type Field

Value Field

Status Bar, Toolbar & Tool Palette

Status Bar

Toolbar

Tool Palette

Selection Tool

Text Tool

Waveform Editing Tool

Time Information

Time Field

Reference (Ref) Field

Interval Field

Start Field

End Field

Time Scale

Waveforms

Group (Bus)

High (1)

High-Impedance (Z)

Low (0)

State Machine

Undefined/Don’t Care (X)

Waveform Separator

For information on other basic tools, see Waveform Editor Basic Tools.

See also:

Getting Context-Sensitive Help


Waveform Editor Help Contents

Introduction

Basic Tools

Commands

Procedures

Golden Rules

Shortcuts

Messages

Glossary


Waveform Editor Introduction
Introduction

The Waveform Editor is a versatile application that serves two roles: as a design entry tool and as a tool for entering simulation vectors and viewing simulation results. Show me

Within this single application, you can create WDFs that contain design logic for a project, or SCFs that contain input vectors for simulation. You can also use SCFs for functional testing with the MAX+PLUS II Simulator or Programmer.

How Does the Waveform Editor Work?

You can initially use the Waveform Editor to enter your design or create input vectors, and then--after running the MAX+PLUS II Simulator--view the results of simulation.

For design entry

Waveform design entry offers an alternative to graphic and text design entry methods. You can create a WDF by specifying combinations of input logic levels and desired outputs as graphical waveforms. WDFs can contain both logical and state machine inputs, and combinatorial, registered, and state machine outputs. MAX+PLUS II also allows you to combine WDFs with other types of design files in a hierarchical project. You can create a default symbol that represents the current WDF; this symbol can then be used in a GDF.

Waveform design entry is best suited for circuits with well-defined sequential inputs and outputs, such as state machines, counters, and registers. WDFs are also ideal for combinatorial functions decoded from counters, and for other repeating functions.

Once your WDF is completely defined, the MAX+PLUS II Compiler synthesizes logic as efficiently as possible to implement the specified outputs. The Compiler automatically generates state bits for any WDF that includes state machines. The Message Processor can automatically locate and highlight errors in the Waveform Editor window.

In addition, all MAX+PLUS II design editors allow you to enter device and resource assignments, and tag timing source and destination nodes for timing analysis. You can also traverse the hierarchy of a project, allowing MAX+PLUS II to automatically open the appropriate editor for each design file.

For design verification

The Waveform Editor allows you to create input vectors for simulation in waveform format. In a few simple steps, you can use the Waveform Editor to create a default SCF from the projects SNF and edit it to provide vector inputs for simulation.

Together with the MAX+PLUS II Simulator, the Waveform Editor allows you to view the results of simulation or functional testing. You can save user-defined, Simulator-generated, or actual device outputs in an SCF. Simulation outputs can be compared to user-defined outputs in the current SCF, or to actual device outputs that show functional testing results.

Whether your purpose is design entry or verification, you can take advantage of the Waveform Editors many features. You can easily modify whole waveforms or waveform intervals and create and edit nodes and groups. With a few simple commands, you can create a Table File or import a Vector File to create an SCF or WDF. You can also save a WDF as an SCF and modify it for simulation purposes or convert an SCF to a WDF for use as a design file.

Where to Start

Altera offers a wide range of information to help you create and edit designs and simulation inputs with MAX+PLUS II and the Waveform Editor.

On-Line Help

On-line help supplies complete reference and how-to information on using the Waveform Editor.

Waveform Editor Help Contents provides access to all on-line Waveform Editor Help.

Waveform Editor Golden Rules summarizes essential rules and guidelines for using the Waveform Editor.

Recommended Reading

Additional Altera publications help you understand MAX+PLUS II and the Waveform Editor. The following application notes and briefs are relevant to using the Waveform Editor:

AN26 (EPLD/MPLD Design Guidelines)

AN28 (Waveform Design Entry)

AB60 (Estimating a Design Fit)

AB92 (Simulating Internal Nodes with MAX+PLUS II Software)

Specific design applications that include design entry or simulation with the Waveform Editor are also available:

AB86 (Designing & Simulating Bidirectional Buses with MAX+PLUS II Software)

AB93 (Partitioning a Project with MAX+PLUS II Software)

See also:

How to Use MAX+PLUS II Help

Simulator Introduction


Waveform Editor Golden Rules
Golden Rules

The following guidelines will help you use the Waveform Editor effectively:

To quickly create a Clock waveform at the current grid size, select the whole Clock waveform by clicking Button 1 on the Value field, choose Overwrite Count Value, and choose OK to accept the default value.

SCF Golden Rules

Create a default SCF with the Enter Nodes from SNF command or enter individual nodes (Enter Node command) from the projects SNF instead of manually creating an SCF from scratch, especially if your project contains state machine logic. The projects SNF automatically includes state bits generated by the Compiler.

When you wish to simulate a state machine, create a default SCF. After compilation, the state bits in the SNF are automatically combined into a group with the same name as the state machine, regardless of whether you named the state bits in the original design files. The default SCF automatically contains the state machine group and bits from the SNF.

Turn on the Preserve Existing Nodes option in the Enter Nodes from SNF command to add nodes from a new SNF to an existing SCF after you recompile a project. This option also ensures that the information in the existing SCF is not overwritten.

The Waveform Editor automatically enters Compare mode if certain Simulator options are turned on. If the Check Outputs option is turned on, the Waveform Editor compares simulation outputs to the outputs in the current SCF. If both the Check Outputs and Use Device options are turned on, the Waveform Editor shows the results of functional testing by comparing actual device inputs to current SCF outputs.

When you turn on the Check Outputs option to check SCF outputs against simulation outputs, ensure that the SCF or Vector File follows the guidelines in Output Monitoring Requirements for the SCF or Vector File.

Ensure that the SCF or Vector File used in functional testing conforms to the rules in Functional Testing with the SCF, Vector File, or Programming File.

When simulating a project that includes bidirectional pins, ensure that the SCF or Vector File conforms to the rules in Simulating Bidirectional Pins.

WDF Golden Rules

Use a WDF to define all logic for a non-hierarchical project, or to define a bottom-level file in a hierarchical project. You cannot use WDFs at intermediate levels of a hierarchy.

Use the following guidelines to create specific types of logic:

-	General Guidelines

-	Combinatorial Node Rules

-	Registered Node Rules

-	State Machine Node Rules

Specify a Clock input as a secondary input for each registered and state machine node. You can specify Clock, Reset, and Preset signals as secondary inputs when you create or edit the node with Enter Node.

For clarity, Altera recommends that you draw inputs that affect registers only on falling Clock edges. Since there is no delay between inputs and combinatorial outputs that are not register-dependent, you should also draw transitions on combinatorial outputs at the same time as the transitions on the inputs, i.e., on falling Clock edges.

Use any grid size or time-slice length you like--the time scale is arbitrary and indicates only a sequential order of operation, not a specific response time.

When creating sequential logic, draw inputs and output transitions in the order in which they will occur during normal operation of the circuit.

When creating non-sequential logic (e.g., purely combinatorial functions), use a waveform separator to specify the beginning of a new waveform sequence that does not depend on the preceding sequence.

If a function is cyclical, show the last set of conditions looping back to the first by repeating the first time-slice at the end of the cycle.

You can import and export signals and state machines to other design files. An imported state machine does not require the setup time and Clock input that are needed for buried and output state machines created in the WDF.

General Design Entry Golden Rules

Be sure to refer to Guidelines for Working with Assignments for absolutely essential information on using all types of resource, probe, and device assignments.

When you start work on a new design file, specify the target device family with Device right away so that you can take advantage of family-specific macrofunctions. If you dont specify a device family, the family for the current project is assumed.

Use the Design Doctor to check the reliability of your project logic during compilation. Follow Project Reliability Guidelines to create reliable projects.

The Altera-provided default logic synthesis styles have different settings for different device families to ensure that each architecture is used most efficiently. When you use an Altera-provided style, the settings for that style will change when you change the device family. After changing the device family, check the new style settings to ensure that they conform to your needs.

General MAX+PLUS II Golden Rules

When you start work on a new design file, name it as the current project with Project Name right away so that you can compile it easily. You can always change the name later.

Use the built-in hierarchy traversal features in MAX+PLUS II to move between design files for the current hierarchy. To open a lower-level file in a hierarchy, open the top-level file and then use the Hierarchy Display window or Hierarchy Down to open the lower-level files. If you choose Open or Retrieve to open a lower-level file, it is considered to be the top of a different hierarchy tree, and resource, device, and probe assignments that you enter are saved only for that hierarchy, not for the project.

When you create an ancillary file for a project, the icon for the file will appear in the Hierarchy Display if you use the same filename as the project.

Dont edit any MAX+PLUS II system files, including HIFs, or the maxplus2.ini or <project name>.ini files.

Use the Save As command if you wish to rename a design file or an ancillary file. Dont rename design files from outside of MAX+PLUS II system (e.g., from DOS or with the Windows File Manager).

When you have completed a project, use Project Archive to ensure that you save a complete backup copy of all project files that will not be affected by future edits or deletions.


Waveform Editor Shortcuts
Shortcuts

The following list provides shortcuts for Waveform Editor commands:

Command:	Shortcut:

Context-Sensitive Help	Shift+F1 or

Align to Grid	Ctrl+Y or

Cascade	Shift+F4

Close	Ctrl+F4 or double-click Button 1 on the Document Control Menu box

Compiler

Copy	Ctrl+C or Ctrl+Insert, or [image] or Press Ctrl+Button 1, drag, and release with the Selection pointer

Cut	Ctrl+X or Shift+Del or

Delete	Del

Enter Group	Double-click Button 1 on an existing group in the group information area to edit a group

Enter Node	Double-click Button 1 in blank space or on an existing node in the node information area to create or edit a node

Exit MAX+PLUS II	Alt+F4 or double-click Button 1 on the Application Control Menu box

Find Next	Ctrl+N

Find Next Transition	Right Arrow

Find Node in Design File	Ctrl+B or

Find Node in Floorplan

Find Previous Transition	Left Arrow

Find Previous	Ctrl+Shift+N

Find Text	Ctrl+F or

Fit in Window	Ctrl+W or

Floorplan Editor

Go To	Ctrl+G or double-click Button 1 on the Time or Reference (Ref) field

Hierarchy Display

Hierarchy Project Top	Ctrl+T or

Hierarchy Up	Ctrl+U

Info	Ctrl+I

Maximum Size	Ctrl+2

New

Next	Ctrl+F6

Normal Size	Ctrl+1

Open	Ctrl+O or

Overwrite Clock

Overwrite Count Value

Overwrite Group Value

Overwrite High (1)

Overwrite High Impedance (Z)

Overwrite Invert

Overwrite Low (0)

Overwrite State Name

Overwrite Undefined (X)

Paste	Ctrl+V or Shift+Ins or

Print	Ctrl+P or choose [image] to print the current file with the settings last specified with the Print dialog box.

Programmer

Project Name	Ctrl+J or

Project Save & Check	Ctrl+K or

Project Save & Compile	Ctrl+L or

Project Save & Simulate	Ctrl+Shift+L or

Project Set Project to Current File	Ctrl+Shift+J or

Save	Ctrl+S or

Search & Replace	Ctrl+R or

Show Grid	Ctrl+Shift+G

Simulator

Snap to Grid

Switch To	Ctrl+Esc

Tile	Shift+F4

Time Range

Timing Analyzer

Timing Cutoff	Ctrl+Alt+C

Timing Destination	Ctrl+Alt+D

Timing Source	Ctrl+Alt+S

Undo	Ctrl-Z or

Zoom In	Ctrl+Space or

Zoom Out	Ctrl+Shift+Space or

You can also press the Space key to refresh the Waveform Editor window.

See also:

Selecting Text


Waveform Editor Procedures
Procedures

Assignments & Compiler Configuration Settings

Assigning a Clique

Assigning a Device

Assigning a Pin, Location, or Chip

Assigning a Probe

Assigning an Individual Logic Option or Synthesis Style

Assigning Connected Pins

Assigning Individual Timing Requirements

Bank-Annotating Assignments for a Project

Clearing Assignments for a Project

Converting an Obsolete Assignment Format

Copying a Resource Assignment

Defining a Logic Synthesis Style

Deleting an Assignment

Guidelines for Achieving Maximum Speed Performance

Guidelines for First-Time Project Fitting

Guidelines for Timing Assignments

Guidelines for Working with Assignments

Ignoring Project Assignments during Compilation

Logic Synthesis Style & Logic Option Rules

Searching the Node Database

Specifying Devices for Automatic Device Selection

Specifying Global Project FLEX 8000 Device & Pin Options

Specifying Global Project Logic Synthesis Settings

Specifying Global Project Security Bit & Reserved Resource Settings

Specifying Global Project Timing Requirements

Specifying Individual Device Security & Turbo Bit Options

Specifying Individual FLEX 8000 Device & Pin Options

File Management

Changing the File Size

Closing a File

Comparing Files or Simulation Outputs

Creating a Default Channel File

Creating a Default Include File

Creating a New File

Creating a Table File

Getting Information on a File

Importing a Vector File

Opening a File

Printing a File

Retrieving a File

Saving a File

Grid

Aligning Transitions to the Grid

Changing the Grid Size

Showing the Grid

Snapping to the Grid

Hierarchy

Navigating the Hierarchy

Updating the Hierarchy

MAX+PLUS II Management

Changing Colors in MAX+PLUS II

Closing a MAX+PLUS II Application

Creating & Using a Local Copy of the maxplus2.ini File

Entering an Authorization Code

Exiting from MAX+PLUS II

Specifying a User Library

Starting MAX+PLUS II Applications

Switching Between MAX+PLUS II Applications

Messages

Getting Help on a Message

Locating the Source of a Message

Nodes & Groups

Changing the Group Radix

Changing the Node Type, I/O Type, Secondary Inputs, or Default Value

Clearing Timing Analysis Tags

Copying, Cutting & Pasting Nodes and Groups

Creating a Group

Creating a Node

Deleting a Node or Group

Finding Nodes & Symbols in a Design File

Moving Nodes & Groups

Renaming a Node or Group

Selecting a Node or Group

Sorting Node & Group Names

Tagging Timing Analysis Cutoff Nodes

Tagging Timing Analysis Source & Destination Nodes

Ungrouping a Group

Project Management

Archiving a Project

Changing the Project Name

Combining Multiple Projects for Simulation

Compiling a Project

Ensuring Project Reliability

Project Reliability Guidelines

Partitioning a Project

Automatic Partitioning

Guiding the Partitioner

Viewing the Results of Partitioning

Renaming a Macrofunction in the Current Project

Status Bar & Toolbar

Showing the Status Bar

Showing the Toolbar

Symbols

Creating the Default Symbol for a File

Editing the Symbol for a File

Finding Nodes & Pins in the Floorplan Editor

Finding Nodes & Symbols in Design Files

Text

Copying, Cutting & Pasting Text

Entering & Deleting Text

Finding Text

Finding & Replacing Text

Selecting Text

Time & Window Display

Changing the Width of the Name, Type & Value Fields

Moving the Reference Cursor

Timing Analysis

Running a Timing Analysis

Undoing Edits

Viewing a File

Fitting a File into the Window

Going to a Specific Time

Going to a Time Range

Zooming In & Out

Waveform Design Entry

Creating a Waveform Design File

Waveforms & Transitions

Copying, Cutting & Pasting Waveforms

Creating & Deleting a Waveform Separator

Deleting a Waveform

Finding a Transition

Growing or Shrinking a Waveform

Inserting a Clock Value on a Waveform

Inserting a Count Value on a Waveform

Inserting a Group Value on a Waveform

Inserting a Node Waveform with a Low, High, Undefined, or High Impedance Logic Level

Inserting a State Name on a Waveform

Inverting a Node or Group Waveform

Moving a Transition

Overwriting a Clock Value on a Waveform

Overwriting a Count Value on a Waveform

Overwriting a Group Value on a Waveform

Overwriting a Node Waveform with a Low, High, Undefined, or High Impedance Logic Level

Overwriting a State Name on a Waveform

Repeating a Waveform

Selecting a Waveform


Changing the File Size (Waveform Editor)
Changing the File Size

To change the size of the current file:

1.	Choose End Time (File menu). The End Time dialog box is displayed.

2.	Type a time value followed immediately (i.e., with no space in between) by a time unit; the default is ns. The default file size of a new file is 1.0 us.

3.	Choose OK.

If you increase the size of the file, the additional waveform intervals in the new portion of the file have the same logic level values that originally appeared at the end.


Creating a Default Channel File (Waveform Editor)
Creating a Default Channel File

When you generate an SCF for simulation, you can either create an empty file and add each node and group (bus) to be simulated in the project, or create a default SCF that contains any combination of nodes (including probes) and groups in the project. You can create a default SCF from the SNF for the project. Only those nodes and groups that have "survived" logic synthesis can appear in the default SCF generated from a timing SNF.

You should always create a default SCF rather than create an SCF "from scratch" when the project contains state machine logic. For each state machine in the project’s design files, the Waveform Editor automatically creates a group of the same name. This group consists of all state bits (which may have been named by the Compiler) in the state machine.

To create a default SCF:

1.	Generate a functional, timing, or linked SNF when you compile the project.

2.	Choose New (File menu), select Waveform Editor file, select the .scf extension, and choose OK to open a new, untitled SCF.

or:

Choose Open (File menu), select the name of an existing SCF, and choose OK to open the file.

3.	Open the Enter Nodes from SNF dialog box by choosing Enter Nodes from SNF (Node menu) or using a shortcut.

4.	The * wildcard character in the Node/Group box and the current Type options represent all nodes and groups that can be placed in the SCF. If you wish to include all nodes and groups, choose List and skip to step 9.

5.	Type the name of a node or group, or a text string that contains wildcard characters for pattern matching in the Node/Group box.

6.	Turn on one or more Type options to specify the type of nodes and/or groups.

7.	If you wish to list all possible hierarchical node names, turn on the Show All Node Name Synonyms option.

8.	Choose List to list all nodes and groups that match the Type options and the name or text string in the Node/Group box in the Available Nodes & Groups box. Node name synonyms are preceded by -> in the list.

9.	Select one or more names in the Available Nodes & Groups box.

10.	Choose the right direction button (=>) to move the selected nodes to the Selected Nodes & Groups box. You can also double-click Button 1 on a single name to move it into the Selected Nodes & Groups box.

11.	If you wish, select one or more nodes in the Selected Nodes & Groups box and choose the left direction button (<=) to move them back into the Available Nodes & Groups box.

12.	Repeat steps 5 through 10 as necessary to select or deselect additional nodes and groups.

13.	If you opened an existing SCF in step 2, turn on Preserve Existing Nodes to add nodes and groups in the Selected Nodes & Groups box without affecting existing nodes and groups in the file. If this option is turned on, nodes and groups that already exist in the current SCF are left unchanged, and only new nodes and groups are added. If it is turned off, all information in the existing file is overwritten.

14.	Choose OK. The Waveform Editor uses the SNF for the project to create a default SCF with the selected nodes and groups in the file.

15.	Choose Save As (File menu) to save the file. You can give the file any name, but Altera recommends that you use the same filename as the project.

See also:

Combining Multiple Projects for Simulation

Creating a Functional Simulator Netlist File

Creating a Timing Simulator Netlist File

Creating a New File

Hierarchical Node & Symbol Names

Saving a File

Recommended reading:

AN28 (Waveform Design Entry)

AB92 (Simulating Internal Nodes with MAX+PLUS II Software)


Creating a Table File (Waveform Editor)
Creating a Table File

The Waveform Editor allows you to create an ASCII-format Table File that records all logic level transitions for nodes and groups in the current WDF or SCF.

You can create a Table File at any time.

To create a Table File:

1.	Choose Create Table File (File menu). The Create Table File dialog box is displayed.

2.	If necessary, select a different drive and/or directory.

3.	Select an existing filename in the Files box, or type a filename in the File Name box. The filename may contain up to 32 name characters. If you select the name of an existing file, it will be overwritten. If you type the name of a directory that does not exist, MAX+PLUS II will offer to create it for you.

4.	Type an extension, or type a period (.) after the filename to create a file without any extension. Otherwise, the extension .tbl is automatically appended to the filename.

5.	Choose OK.

Recommended reading:

AN28 (Waveform Design Entry)

AB92 (Simulating Internal Nodes with MAX+PLUS II Software)


Importing a Vector File (Waveform Editor)
Importing a Vector File

You can create waveforms for waveform design entry or for use with the Simulator by importing an ASCII-format Vector File (.vec) and saving the file as a Waveform Design File or Simulator Channel File.

To import a Vector File:

1.	Choose New (File menu), select Waveform Editor file, select the .scf or .wdf extension, and choose OK to open a new, untitled Waveform Editor file.

2.	Choose Import Vector File (File menu). The Import Vector File dialog box is displayed.

3.	If necessary, select a different drive and/or directory.

4.	Select an existing filename in the Files box, or type a filename in the File Name box.

5.	Type an extension, or type a period (.) after the filename to specify a file without any extension. Otherwise, the extension .vec is automatically appended to the filename. The Waveform Editor converts the specified file into a Waveform Editor file.

6.	Choose Save As (File menu) to save the file as a WDF or SCF.

Recommended reading:

AN28 (Waveform Design Entry)

AB92 (Simulating Internal Nodes with MAX+PLUS II Software)


Printing a File (Waveform Editor)
Printing a File

To print the current file:

1.	Open the Print dialog box by choosing Print (File menu) or using a shortcut.

2.	Turn on one or more of the following options:

Option:	Action:

Copies	Specifies the number of copies to print. Multiple copies are collated.

Time Range

All	Prints the entire file.

From and To	Specify a time period to print. Type a start time and end time, followed immediately (i.e., with no space in between) by a time unit; the default is ns.

Fit Into

Page(s) Horizontally	Specifies how many pages should be used to print the names of the nodes and groups in the file, i.e., controls how many node and group names to print on each page.

Page(s) Vertically	Specifies how many pages should be used to print each waveform in the file, i.e., controls the scale of the waveforms to be printed.

Print

Page Headers	Prints the MAX+PLUS II version number, filename, date, and page number.

Node Information 	Prints the node and group names on each page.

On All Pages

3.	Choose OK.

To change the printer and printer options:

1.	Choose Print Setup (File menu). The Print Setup dialog box is displayed.

2.	Select the desired printer, paper orientation, and paper and source.

3.	If necessary, choose Options to change the printer options that are available with your printer. Choose OK when you are done to close the Options dialog box.

4.	Choose OK in the Print Setup dialog box.


Aligning Transitions to the Grid (Waveform Editor)
Aligning Transitions to the Grid

To align existing transitions to the grid:

1.	With the Selection pointer ( [image] ), select one or more waveform intervals or whole waveforms.

2.	Choose Align to Grid (Edit menu) or use a shortcut.

To align transitions that are created or moved in subsequent drawing:

Choose Snap to Grid (Options menu) or use a shortcut.

Align to Grid and Snap to Grid work regardless of whether the grid is displayed.

See also:

Changing the Grid Size

Guidelines for Working with Copies of Nodes & Groups

Moving a Transition

Selecting a Waveform

Showing the Grid


Changing the Grid Size (Waveform Editor)
Changing the Grid Size

The grid provides a visual reference to aid waveform editing. It also controls the magnification level that is displayed when you choose Normal Size (View menu), which zooms in or out to display 6 to 8 grid units in the current window.

The grid size can be changed regardless of whether the grid is displayed.

To change the grid size:

1.	Choose Grid Size (Options menu). The Grid Size dialog box is displayed.

2.	Type a time value and an optional time unit in the Grid Size box. The optional time unit must immediately follow the time value (i.e., with no space in between); the default is ns.

3.	Choose OK.

In a WDF, the grid size is arbitrary. You can select any grid size that is convenient for drawing your waveform.

See also:

Showing the Grid

Snapping to the Grid


Showing the Grid (Waveform Editor)
Showing the Grid

The grid provides a visual reference to aid waveform editing. Showing the grid has no effect on whether Snap to Grid (Options menu) is turned on or off.

To show or hide the grid:

Choose Show Grid (Options menu) or use a shortcut.

See also:

Aligning Transitions to the Grid

Changing the Grid Size

Snapping to the Grid


Snapping to the Grid (Waveform Editor)
Snapping to the Grid

The grid provides a visual reference to aid waveform editing. When the Snap to Grid command (Options menu) is turned on, grid lines become "magnetic" and insertion points, area selections, and new transitions snap to them. Showing the grid has no effect on whether Snap to Grid is turned on or off.

To turn the snap to grid feature on or off:

Choose Snap to Grid (Options menu) or use a shortcut.

The Snap to Grid command is always turned on in a WDF.

See also:

Changing the Grid Size

Showing the Grid


Changing the Group Radix (Waveform Editor)
Changing the Group Radix

The group radix controls how the group value is displayed, and how group waveform edits are interpreted by the Insert Group Value and Overwrite Group Value commands (Edit menu). The radix of each group in the current file is shown in the Value field for the group.

The group radix is initially set when you create the group in a WDF, another design file, a Vector File, or an SCF. The default is the last group radix entered.

To change the radix of a group:

1.	With the Selection pointer ( [image] ), select a group and open the Enter Group dialog box by choosing Enter Group (Node menu) or using a shortcut.

2.	If you wish, turn on Display Gray Code Count As Binary Count. This option stores the group value as Gray code (represented with the letter G in the Value field) and displays the equivalent binary count.

3.	Select a new Radix option of BIN (binary), DEC (decimal), HEX (hexadecimal), or OCT (octal) for the group. The radix is represented with the letter B, D, H, or O in the Value field.

4.	Choose OK. The new radix is applied to all copies of the group.

See also:

Creating a Group

Renaming a Node or Group

Selecting a Node or Group


Changing the Node Type, I/O Type, Secondary Inputs, or Default Value (Waveform Editor)
Changing the Node Type, I/O Type, Secondary Inputs, or Default Value

When you create a node in an SCF or WDF, it has a name, an I/O type, and an initial default logic level (value) or state name. In a WDF, all nodes also have a node type, and registered and state machine nodes have other nodes in the file specified as their secondary inputs.

The Edit Node command (Node menu) allows you to change the node name, node type, I/O type, secondary inputs, and default value of one or more nodes in a file. You can also use this command to change the same characteristics (except the name) of one or more groups.

To change the node type, I/O type, secondary inputs, or default value:

1.	With the Selection pointer ( [image] ), select a node or group and open the Edit Node dialog box for WDFs or the Edit Node dialog box for SCFs by choosing Edit Node or using a shortcut.

2.	Change the node or group with one or more of the following steps:

Select a new I/O Type option.

(WDFs only) Select a new Node Type option. The following combinations of node and I/O types are permitted:

I/O Type:	Node Types:

Input	Pin Input, Machine

Output	Registered, Combinatorial, Machine

Buried	Registered, Combinatorial, Machine

(WDFs only) Under Secondary Inputs, select an existing node name from the drop-down list boxes, or type a node name to change the Clock, Reset, or Preset inputs to registered- or machine-type nodes.

(Available for a single node only) Type a new name for a single node in the Node Name box. The name may contain up to 32 name characters. You can also paste a name copied from another file or MAX+PLUS II application with Shift+Ins.

(SCFs only; available for a single node only) List nodes from the SNF for the project in the Nodes & Groups from SNF box and select a name to copy a different name to the Node Name box.

Select or type a new default value in the Default Value box to change the logic level or state name of the entire waveform of the node or group. A state name may contain up to 32 name characters.

3.	Choose OK to save the changes.

See also:

Creating a Node

Guidelines for Working with Copies of Nodes & Groups

Renaming a Node or Group

Selecting a Node or Group

Recommended reading:

AN28 (Waveform Design Entry)

AB92 (Simulating Internal Nodes with MAX+PLUS II Software)


Copying, Cutting & Pasting Nodes and Groups (Waveform Editor)
Copying, Cutting & Pasting Nodes and Groups

In the Waveform Editor, a node or group consists of a combination of the node/group handle, and its name and waveform. You can copy, cut, and paste entire nodes and groups, as well as sections of their waveforms and their names.

To copy and paste nodes and groups:

1.	With the Selection pointer ( [image] ), select one or more nodes and/or groups to copy. You can use area  or object-by-object selection.

2.	Choose Copy (Edit menu) or use a shortcut.

3.	Click Button 1 in a blank space in the node/group information area to define an insertion point, or select one or more nodes and groups to replace. You can use area selection only when you select nodes and/or groups to be replaced. You cannot paste a node with a node type of machine into a group.

4.	Choose Paste (Edit menu) or use a shortcut.

or:

1.	Select one or more nodes and/or groups to copy. You can use area or object-by-object selection.

2.	Press Ctrl and point to one of the selected node or group.

3.	Press Button 1 and drag the item(s) to a new location. A horizontal line appears as you drag the mouse to show where the item(s) will be placed. A copy of the item(s) is created, but not placed on the clipboard.

4.	Release Button 1 and the Ctrl key.

You can also press Ctrl after you have started dragging a selection to change a move operation into a copy operation.

To cut and paste nodes and groups:

1.	Select one or more nodes and/or groups to cut. You may use area or object-by-object selection.

2.	Choose Cut (Edit menu) or use a shortcut. The item(s) are placed on the clipboard.

3.	Select an empty Name field as the insertion point, or select one or more nodes and groups to be replaced by the paste. You may use area selection only when you select nodes and/or groups to be replaced. You cannot paste a machine-type node into a group.

4.	Choose Paste.

Text can be copied or cut and pasted into other text, graphic and waveform files. Waveform Editor graphics (nodes, groups, and their waveforms) can only be pasted into other Waveform Editor files.

See also:

Copying, Cutting & Pasting Waveforms

Guidelines for Working with Copies of Nodes & Groups

Selecting a Node or Group


Creating a Group (Waveform Editor)
Creating a Group

You can combine up to 256 nodes into a group (bus) to suit your vector entry needs. You can select a group to be included in another group, but each member of the group is counted towards the 256-node maximum. To create a group, you can combine existing nodes displayed in the window, add a group from the project’s SNF, or use a single-range group name to create a group without first creating individual nodes. A group has no logical meaning in a WDF; nodes with a node type of machine cannot be grouped.

To create a group from existing nodes:

1.	Arrange the nodes so that the MSB is at the top of the nodes you wish to include in the new group, the LSB is at the bottom, and the other nodes are ordered as desired between the MSB and LSB.

2.	With the Selection pointer ( [image] ), select between 2 and 256 nodes and/or groups with the same I/O type, node type, and secondary inputs. (Machine-type nodes cannot be grouped.) You may use area or object-by-object selection. Each member of a group is counted towards the 256-node maximum.

3.	Open the Enter Group dialog box by choosing Enter Group (Node menu) or using a shortcut.

4.	Type a name in the Group Name box. The group name may contain up to 32 name characters. You can also paste a name copied from another file or MAX+PLUS II application with Shift+Ins. A single-range group name appears automatically if it matches the names and numerical range of numbers of the original nodes.

5.	If you wish, turn on Display Gray Code Count As Binary Count. This option stores the group value as Gray code (represented with the letter G in the Value field) and displays the equivalent binary count.

6.	If you wish to set the group radix, select the Radix option of BIN (binary), DEC (decimal), HEX (hexadecimal), or OCT (octal) that will be used to display the group’s logic level and to interpret edits made to the group waveform. The default is the last group radix entered.

7.	Choose OK. The new group occupies the space formerly held by the MSB.

To add a group from the SNF for the project (SCFs only):

1.	If you wish, select a single blank line to create a new group on that line. Otherwise, the new group appears in the first blank space at the bottom of the window.

2.	Open the Insert Node dialog box for SCFs by choosing Insert Node (Node menu) or using a shortcut.

3.	Go to the bottom half of the dialog box and turn on the Group option under Type to list the available groups. Turn off all other options in the Type box.

4.	Choose List to list the group names.

5.	Select a name in the Nodes & Groups from SNF box to copy its name and I/O type to the top portion of the dialog box.

6.	Type a default logic level or select a logic level from the drop-down list in the Default Value box. For a group of state machine bits, you can substitute a default state name.

7.	Choose OK.

The radix used to display the new group is determined by the last group radix entered with Enter Group.

To create a single-range group:

1.	If you wish, select a single blank line to create a new group on that line. Otherwise, the new group appears in the first blank space at the bottom of the window.

2.	Open the Insert Node dialog box for WDFs or the Insert Node dialog box for SCFs by choosing Insert Node or using a shortcut.

3.	Type a single-range group name in the Node Name box. You can also paste a name copied from another file or MAX+PLUS II application with Ctrl+V.

4.	Type a default logic level or select a logic level from the drop-down list in the Default Value box. The initial default logic level is 0.

5.	Select an I/O Type.

6.	(WDFs only) Specify additional node information required for waveform design entry:

a.	Select a Node Type.

b.	If the Node Type is Registered or Machine, type the name of an existing node in the file or select a name from the drop-down list for the following Secondary Inputs:

(Required) Clock

(Optional) Reset (specifies the Clear input for registered nodes)

(Optional) Preset (not applicable to machine nodes)

7.	Choose OK.

The radix used to display the new group is determined by the last group radix entered with Enter Group.

See also:

Changing the Group Radix

Changing the Node Type, I/O Type, Secondary Inputs, or Default Value

Group (Bus) Waveform

Moving Nodes & Groups

Renaming a Node or Group

Selecting a Node or Group

Ungrouping a Group

Recommended reading:

AN28 (Waveform Design Entry)

AB92 (Simulating Internal Nodes with MAX+PLUS II Software)


Creating a Node (Waveform Editor)
Creating a Node

Nodes are the building blocks of both WDFs and SCFs.

A node has a name, an I/O type, an initial default logic level (value) or state name, and a waveform. In a WDF, all nodes also have a node type, and registered and state machine nodes have other nodes in the file specified as their secondary inputs. You must explicitly create or save a file with the extension .wdf to enter node type and secondary input information, as well as to take advantage of other waveform design entry features.

This procedure describes how to create a single node or add a single node from the project’s SNF with Insert Node (Node menu). You can also enter multiple nodes from the project’s SNF with Enter Nodes from SNF (Node menu), as described in Creating a Default Channel File.

To create a node:

1.	Open the Insert Node dialog box for SCFs or the Insert Node dialog box for WDFs by choosing Insert Node or using a shortcut.

2.	Type a name in the Node Name box. The node name can contain up to 32 name characters. A hierarchical node name can contain up to 128 characters. You can also paste a name copied from another file or MAX+PLUS II application with Ctrl+V.

or:

Go to the bottom half of the dialog box to select a node or group from the SNF for the project:

a.	If you wish, type a node name, group name, or a text string that contains wildcard characters for pattern matching in the Node/Group box.

b.	Turn on one or more Type options to specify the groups and/or types of nodes you wish to list.

c.	If you wish to list all possible hierarchical node names, turn on the Show All Node Name Synonyms option.

d.	Choose List to list all node and group names that match the Node/Group name and Type options in the Nodes & Groups from SNF box. Node name synonyms are preceded by the -> in the list.

e.	Select a name in the Nodes & Groups from SNF box to copy its name and I/O type to the top portion of the dialog box.

4.	Type a default logic level or select a logic level from the drop-down list in the Default Value box. For state machine nodes, the initial default state name is X; for other node types, the default logic level is 0. If the current file is a WDF, you can substitute a default state name with up to 32 name characters.

5.	If you did not select a node from the project’s SNF, select an I/O Type.

6.	(WDFs only) Specify additional node information required for waveform design entry:

a.	Select a Node Type.

b.	If the Node Type is Registered or Machine, type the name of an existing node in the file or select a name from the drop-down list for the following Secondary Inputs:

(Required) Clock

(Optional) Reset (specifies the Clear input for registered nodes)

(Optional) Preset (not applicable to machine nodes)

7.	Choose OK.

See also:

Changing the Node Type, I/O Type, Secondary Inputs, or Default Value

Low (0), High (1), Undefined/Don’t Care (X), and High-Impedance (Z) Waveforms

State Machine Waveform

Recommended reading:

AN28 (Waveform Design Entry)

AB92 (Simulating Internal Nodes with MAX+PLUS II Software)


Deleting a Node or Group (Waveform Editor)
Deleting a Node or Group

To delete a node or group:

1.	With the Selection pointer ( [image] ), select one or more nodes or groups to delete.

2.	Choose Delete (Edit menu) or use a shortcut.

Delete removes the selected items from the file without replacing the contents of the Clipboard. To remove a selection from the file and store it on the Clipboard, choose Cut (Edit menu) instead of Delete.

See also:

Selecting a Node or Group

Guidelines for Working with Copies of Nodes & Groups


Moving Nodes & Groups (Waveform Editor)
Moving Nodes & Groups

To move a node or group:

1.	With the Selection pointer ( [image] ), select one or more nodes and/or groups. You may use area or object-by-object selection.

2.	Point to the node or group handle of one of the selected nodes or groups.

3.	Press Button 1 and drag the mouse up or down. As you drag the mouse, a horizontal line shows where the item(s) will be placed.

4.	Release Button 1 at the point where you wish to insert the selected item(s).

The selected items appear at the location indicated by the horizontal line.

See also:

Copying, Cutting & Pasting Nodes and Groups

Selecting a Node or Group


Renaming a Node or Group (Waveform Editor)
Renaming a Node or Group

You may need to rename a node or group to correct an error, or to change a linked copy of a node or group into a separate, unlinked node or group.

A node or group in an SCF that is used for simulation must have the same name as a node or group in the SNF for the project, including a hierarchy path (if necessary). You can use Insert Node (Node menu) to add individual nodes from the SNF to the current file. You can also create a default SCF that lists all names in the SNF, including hierarchy paths, with Enter Nodes from SNF (Node menu). You can copy a name from the default SCF to another file, or edit the default SCF to provide inputs for simulation.

When you copy a node or group, its waveform is linked to all other nodes and groups with the same name. Renaming a node or group removes the link between it and other nodes and groups with the same name.

To rename a node:

1.	With the Selection pointer ( [image] ), select a node and open the Edit Node dialog box for WDFs or Edit Node dialog box for SCFs by choosing Edit Node (Node menu) or using a shortcut.

2.	Type a new name in the Node Name box. A node name can contain up to 32 name characters; a hierarchical node name can contain up to 128 characters. You can also paste a name copied from another file or MAX+PLUS II application with Ctrl+V.

3.	Choose OK to save the changes.

To rename a group:

1.	With the Selection pointer, select a group and open the Enter Group dialog box by choosing Enter Group (Node menu) or using a shortcut.

2.	Type a new name in the Group Name box. A group name can contain up to 32 name characters; a hierarchical node name can contain up to 128 characters. You can also paste a name copied from another file or MAX+PLUS II application with Ctrl+V.

3.	Choose OK to save the changes.

You can also change node and group names with Search & Replace (Utilities menu), as described in Finding & Replacing Text.

See also:

Changing the Group Radix

Changing the Node Type, I/O Type, Secondary Inputs, or Default Value

Guidelines for Working with Copies of Nodes & Groups

Finding & Replacing Text


Selecting a Node or Group (Waveform Editor)
Selecting a Node or Group

Nodes and groups can be selected as a whole, including their waveforms, with Button 1.

To select a single node or group:

With the Selection pointer ( [image] ), click Button 1 on the node or group handle, Name field, or in the Type field.

You can use area or object-by-object selection to select multiple nodes and/or groups.

To select multiple nodes or groups with area selection, point to the Name field or Type field with the selection pointer ( [image] ) and use one of the following Button 1/keyboard combinations:

Mouse/Key:	Action:

Press, Drag, Release	Selects all nodes and groups from the point where Button 1 is pressed to the point where it is released.

Click, Move, Shift+Click	Selects all objects between the first click and the Shift+Click.

To select multiple discontiguous nodes or groups using object-by-object selection:

1.	Press Shift and click Button 1 on a node or group handle to add it to the previous selection.

You can mix area and object-by-object selection. Example

See also:

Selecting a Waveform


Example: Mixing Area and Object Selection
To select the 1st, 2nd, 3rd, 5th, and 7th nodes in the sequence NODE1 through NODE7:

1.	With the Selection pointer ( [image] ), press Button 1 on the node name or in the Type field for NODE1, drag, release on NODE3.

or:

With the Selection pointer, click Button 1 on NODE1, point to the node name or Type field of NODE3, and click Button 1.

2.	Shift+Click Button 1 on the handle for NODE5.

3.	Repeat Step 2 for NODE7.


Sorting Node & Group Names (Waveform Editor)
Sorting Node & Group Names

The Waveform Editor allows you to sort node and group names alphabetically in ascending or descending order. Numbers are sorted in a "smart" numerical order, in which 0 precedes 1. By selecting the Descending option, you can sort nodes with the MSB before the LSB to facilitate grouping.

To sort node and group names:

1.	If you wish, select one or more node and/or group names with the Selection pointer ( [image] ). You may use area or object-by-object selection. Otherwise, all node and/or group names are sorted.

2.	Choose Sort Names (Node menu). The Sort Names dialog box is displayed.

3.	Select the Ascending or Descending option.

4.	Choose OK.

The nodes and/or groups are sorted and are rearranged to appear together in a single block.

See also:

Creating a Group

Selecting a Node or Group


Ungrouping a Group (Waveform Editor)
Ungrouping a Group

To break a group down into its original member nodes:

1.	With the Selection pointer ( [image] ), select one or more group names. You may use area or object-by-object selection.

2.	Choose Ungroup (Node menu) or use a shortcut.

For each group that is ungrouped, the original member nodes replace the space that was formerly held by the group. The MSB appears above all other nodes; the LSB appears below.

See also:

Guidelines for Working with Copies of Nodes & Groups


Finding & Replacing Text (Waveform Editor)
Finding & Replacing Text

To find and replace text:

1.	Move the insertion point to define where the search will begin.

2.	Open the Search & Replace dialog box by choosing Search & Replace (Utilities menu) or using a shortcut.

3.	Type up to 256 characters of search text, including optional wildcard characters, in the Search For box.

4.	Type up to 256 characters of new text in the Replace With box.

5.	If you wish, turn on one or more of the following options:

Option:	Action:

Whole Word	Finds occurrences of the search text that are whole words only.

Confirm Each Change	Specifies whether the Waveform Editor asks before replacing each occurrence of the search text.

Pause At End	Pauses the search when the Waveform Editor reaches the end of the file.

6.	Select the Up or Down option to search up or down within the file.

7.	Turn on one or more Types of Text to Find options.

8.	Choose OK to begin the search.

9.	You can find the next or previous occurrence of the search text after the first occurrence has been found by choosing one of the following Utilities menu commands:

Find Text or a shortcut*ke_short_findtext

Find Next or a shortcut*ke_short_findnext

Find Previous or a shortcut*ke_short_findprev

If the Waveform Editor finds the search text when the Confirm Each Change option is turned on, you are asked whether you wish to replace the selection. Choose one of the following options:

Button/Option:	Action:

Confirm Each Change	Specifies whether the Waveform Editor asks before replacing each occurrence of the search text. If you turn this option off, the Waveform Editor replaces all occurrences.

Yes	Replaces the currently selected search text, then continues the search.

No	Does not replace the currently selected search text, but continues the search.

Cancel	Ends the search.

See also:

Finding Text


Finding Text (Waveform Editor)
Finding Text

To find a specific string of text:

1.	Move the insertion point to define where the search will begin.

2.	Open the Find Text dialog box by choosing Find Text or using a shortcut.

3.	Type up to 256 characters of search text, including optional wildcard characters, in the Search For box.

4.	If you wish, turn on one or more of the following options:

Option:	Action:

Whole Word	Finds occurrences of the search text that are whole words only.

Pause at End	Pauses the search when the Waveform Editor reaches the end of the file.

5.	Select Up or Down to search up or down within the file.

6.	Turn on one or more Types of Text to Find options.

7.	Choose OK to begin the search.

8.	You can find the next or previous occurrence of the search text after the first occurrence has been found by choosing one of the following Utilities menu commands:

Find Text or a shortcut*ke_short_findtext

Find Next or a shortcut*ke_short_findnext

Find Previous or a shortcut*ke_short_findprev

See also:

Finding & Replacing Text

Selecting Text


Entering & Deleting Text (Waveform Editor)
Entering & Deleting Text

To enter text in the Waveform Editor window:

1.	With the Text tool, click Button 1 anywhere in the waveform drawing area to define an insertion point. A text handle appears in the node information area.

2.	Type the text block or comment. You can enter up to 1,024 characters of text.

To delete text in the Waveform Editor window:

1.	With the Selection pointer, click Button 1 on the text to select the entire block.

or:

With the Text tool, double-click Button 1 on the text to select the entire block or press Button 1 on the text, drag, and release to select a portion of the block.

2.	Choose Delete (Edit menu) or use a shortcut.

or:

Type Backspace. The selected text is erased from the Waveform Editor window.

Even if an entire block of text is deleted from the Waveform Editor window, the text handle remains as a marker for you to reuse.

To delete an unused text marker:

With the Text tool, click Button 1 anywhere else in the Waveform Editor window to deactivate the text insertion point.

or:

Type Esc to automatically activate the Selection tool.

or:

Click Button 1 on one of the palette tools to initialize a new entry.

Choosing Cut (Edit menu) or using a shortcut will erase the text from the Waveform Editor window and place it on the clipboard.

See also:

Finding & Replacing Text

Selecting Text


Changing the Width of the Name, Type & Value Fields (Waveform Editor)
Changing the Width of the Name, Type & Value Fields

You can change the width of the Name, Type, and Value fields to display information in the most convenient form.

To change the width of a field:

1.	Point to one of the square field resizing handles that appear at the junction of each field’s boundary with the time scale.

2.	Press Button 1 and drag the handle left or right to expand or shrink the field.

3.	Release Button 1.


Moving the Reference Cursor (Waveform Editor)
Moving the Reference Cursor

The Reference (Ref) cursor can be moved anywhere within a Waveform Editor file as a "bookmark" or to help with waveform selection, editing, and finding logic level transitions.

The Reference cursor moves automatically when you click Button 1 in the waveform drawing area to define an insertion point. You move the cursor manually with the following procedures.

To move the Reference cursor to any position in the file:

1.	Point to the square cursor handle and press Button 1.

2.	Drag the handle right or left to a new location.

3.	Release Button 1.

or:

1.	Open the Go To dialog box by choosing Go To (Utilities menu) or using a shortcut.

2.	Type a time value and an optional time unit in the Time box. The optional time unit must immediately follow the time value (i.e., with no space in between); the default is ns.

3.	Choose OK.

To move the Reference cursor to the next transition to the left or right, respectively:

1.	With the Selection pointer ( [image] ), select the set of nodes and/or groups within which to find a transition. The transition will be found only on selected nodes and/or groups. You must select only whole nodes and groups, not a waveform interval. When all nodes and groups are unselected, it is as if all are selected.

2.	Click Button 1 on the left or right cursor movement button. A pair of these buttons appears next to the Ref field.

or:

Choose one of the following Utilities menu commands:

Find Previous Transition or a shortcut

Find Next Transition or a shortcut

Find Previous or a shortcut

Find Next or a shortcut


Fitting a File into the Window (Waveform Editor)
Fitting a File into the Window

To view the entire file:

Choose Fit in Window (View menu) or use a shortcut.

Fit in Window changes the display scale to fit the entire waveform of each currently displayed node or group into the current window. The number of nodes and groups in the window cannot be scaled.

See also:

Zooming In & Out


Going to a Specific Time (Waveform Editor)
Going to a Specific Time

To display a specific time in the window:

1.	Open the Go To dialog box by choosing Go To (Utilities menu) or using a shortcut.

2.	Type a time value and an optional time unit in the Time box. The optional time unit must immediately follow the time value (i.e., with no space in between); the default is ns.

3.	Choose OK.

The Waveform Editor automatically scrolls the window, and moves the Reference cursor to the specified time.

See also:

Going to a Time Range

Moving the Reference Cursors


Going to a Time Range (Waveform Editor)
Going to a Time Range

To display a specific time range in the window:

1.	Open the Time Range dialog box by choosing Time Range (View menu) or using a shortcut.

2.	Type a time value and an optional time unit in the From and To boxes. The optional time unit must immediately follow the time value (i.e., with no space in between); the default is ns.

3.	Choose OK.

The Reference cursor moves to the time specified in the From box, and the Waveform Editor zooms in or out so that the specified time range completely fills the window.

See also:

Going to a Specific Time


Zooming In & Out (Waveform Editor)
Zooming In & Out

To change the view of the file, select one of the following View menu commands:

Command:	Action:

Fit in Window command	Zooms out to fit the full length of each waveform into the window. Shortcuts

Time Range command	Scrolls and zooms in or out within the file so that a specified time range fills the current window. Shortcuts

Zoom In command	Increases the scale of the waveforms displayed, showing a smaller portion of the file. Shortcuts

Zoom Out command	Reduces the scale of the waveforms displayed, showing a greater portion of the file. Shortcuts

Normal Size command	Zooms in or out to display waveforms at a resolution determined by the current grid size, so that approximately six to eight grid lines are displayed. Shortcuts

Maximum Size command	Zooms in to display waveforms at maximum resolution. Shortcuts

If an interval is selected, the Waveform Editor zooms in and out on the interval. Otherwise, the Waveform Editor zooms in and out on the current insertion point.

When you use the keyboard shortcuts for the Fit in Window, Zoom In, Zoom Out, Normal Size and Maximum Size commands, you can zoom as you are selecting or overwriting a waveform.

See also:

Changing the Grid Size

Fitting a File into the Window

Going to a Time Range


Copying, Cutting & Pasting Waveforms (Waveform Editor)
Copying, Cutting & Pasting Waveforms

The Waveform Editor allows you to edit a whole node or group or a specific interval within a waveform.

To copy or cut and paste a waveform interval:

1.	With the Selection pointer ( [image] ), select one or more intervals or whole waveforms to copy or cut. You may use area selection only.

2.	Choose Copy (Edit menu) or use a shortcut.

or:

Choose Cut (Edit menu) or use a shortcut. If you cut an interval, the end of the file contains an undefined (X) interval of equal length; if you cut a whole waveform, it is replaced with an X waveform.

3.	Click Button 1 to define an insertion point or select one or more whole waveforms or waveform intervals to replace. The following rules apply:

You can replace a whole waveform with an interval or vice versa. If you paste a waveform with a shorter interval, the end of the waveform is "padded" with an X waveform. If you paste an interval with a longer waveform, the waveform is truncated at the end of the file.

You can insert or overwrite a cut or copied group waveform in multiple node waveforms or vice versa. A warning is issued if the paste will only partially edit a group, i.e., if only some member nodes within the group are edited.

You may use area selection when you select the waveform(s) or waveform interval(s) to be overwritten.

4.	Choose Paste (Edit menu) or use a shortcut. If you selected an insertion point rather than one or more waveforms to replace, it defines the top left corner of the pasted waveform(s). In other words, copied or cut waveforms are pasted to the right and below the insertion point.

Text can be copied or cut and pasted into different MAX+PLUS II files and into different types of text fields. For example, a pin name from a WDF can be pasted into a TDF. Waveform Editor graphics (nodes, groups, and their waveforms) can only be pasted into other Waveform Editor files.

See also:

Copying, Cutting & Pasting Nodes and Groups

Guidelines for Working with Copies of Nodes & Groups

Repeating a Waveform

Selecting a Waveform


Creating & Deleting a Waveform Separator (Waveform Editor)
Creating & Deleting a Waveform Separator

You can create a waveform separator to indicate that the logic levels and/or state names in the waveforms before the separator are unrelated to those after it. A waveform separator is available only in a WDF.

To create a waveform separator:

1.	If you wish, with the Selection pointer ( [image] ), click Button 1 to define an insertion point.

2.	Choose Enter Separator (Node menu). The Enter Separator dialog box is displayed.

3.	If you defined an insertion point in step 1, its time is displayed in the Separator Time box. If not, type a time value and an optional time unit. The optional time unit must immediately follow the time value (i.e., with no space in between); the default is ns.

4.	Choose OK. The waveform separator appears as a thin vertical line.

To delete a waveform separator:

1.	Select the separator by clicking Button 1 on the square cursor handle that appears at its junction with the time scale.

2.	Choose Delete (Edit menu) or use a shortcut.

Recommended reading:

AN28 (Waveform Design Entry)


Deleting a Waveform (Waveform Editor)
Deleting a Waveform

To delete a waveform:

1.	With the Selection pointer ( [image] ), select one or more waveform intervals or whole waveforms to delete.

2.	Choose Delete (Edit menu) or use a shortcut.

The selected waveforms are deleted. If you delete an interval, the end of the file then contains an undefined (X) interval of equal length; if you delete a whole waveform, it is replaced with an undefined waveform.

Delete removes the selected waveforms from the file without replacing the contents of the Clipboard. To remove a selection from the file and store it on the Clipboard, choose Cut (Edit menu) instead of Delete.

See also:

Copying, Cutting & Pasting Waveforms

Guidelines for Working with Copies of Nodes & Groups

Selecting a Waveform


Finding a Transition (Waveform Editor)
Finding a Transition

You can find logic level or state name transitions in the Waveform Editor with the Reference cursor.

To find a transition with the Reference cursor:

1.	With the Selection pointer ( [image] ), select the set of nodes and/or groups that you wish to search for a transition. The Reference cursor finds transitions only on selected nodes and/or groups. You must select only whole nodes and groups, not a waveform interval. If none of the nodes or groups in the file are selected, the Reference cursor operates as if all nodes and groups are selected.

2.	Move the Reference cursor to the next transition to the left or right, respectively:

Type the Right Arrow or Left Arrow key.

Click Button 1 on the Reference cursor’s left or right cursor movement button. These buttons appear to the right of the Reference field.

Choose one of the following Utilities menu commands:

Find Previous Transition or a shortcut

Find Next Transition or a shortcut

Find Previous or a shortcut

Find Next or a shortcut

See also:

Aligning Transitions to the Grid

Moving a Transition

Moving the Reference Cursor

Selecting a Node


Growing or Shrinking a Waveform (Waveform Editor)
Growing or Shrinking a Waveform

The Waveform Editor allows you to stretch or compress a waveform that has a desired pattern of logic levels and transitions into a different time period.

To grow or shrink a waveform:

1.	With the Selection pointer ( [image] ), select one or more whole waveforms or waveform intervals that you wish to grow or shrink. You may use area selection only.

2.	Open the Grow or Shrink dialog box by choosing Grow or Shrink (Edit menu) or using a shortcut.

3.	Type a new start and/or end time, including an optional time unit, for the selected interval. The optional time unit must immediately follow the time you enter; the default is ns.

4.	Choose OK.

If you shrink (compress) a waveform, the end of the waveform is "padded" with an X waveform. If you grow (stretch) a waveform, the waveform is truncated at the end of the file.

See also:

Guidelines for Working with Copies of Nodes & Groups

Selecting a Waveform


Inserting a Count Value on a Waveform (Waveform Editor)
Inserting a Count Value on a Waveform

You can edit a single group waveform to include a new interval with a specific binary or Gray code count sequence.

To insert a new count value on a node or group waveform:

1.	With the Selection pointer ( [image] ), click Button 1 to define an insertion point or select an interval on a single node or group that is equal in length to the interval you wish to insert.

2.	Open the Insert Count Value dialog box by choosing Insert Count Value (Edit menu) or using a shortcut.

3.	Select a Count Type of Binary or Gray Code.

4.	Type a logic level in the Starting Value box. The default is the current group or node value at the start of the selected interval. The logic level for a group is interpreted according to the group’s radix.

5.	Type the number by which you wish to increment the count in the Increment By box. You can type a whole number between -32000 and 32000.

6.	If you defined an insertion point in step 1, type a logic level in the Ending Value box. Otherwise, the box is dimmed and the logic level is calculated on the basis of the other fields in the dialog box.

7.	Type the time interval at which the count should be incremented with a combination of the Count Every time interval and the Multiplied By multiplier. The multiplier can be any whole number between -32000 and 32000. The default Count Every time interval is the current grid spacing; the default multiplier is 1. The Count Every box is dimmed and not available if Snap to Grid (Options menu) is turned on.

8.	As you enter the logic level, time, multiplier, and count increment values in the dialog box, other fields are dynamically updated to show how the new interval will appear. When you have specified all conditions, choose OK.

The new interval is inserted to the left of the interval or insertion point selected in step 1, and the new logic levels are displayed on the waveform. The waveforms of all individual nodes within an edited group are changed to create the new value.

When you insert a count value interval, another interval of equal length is deleted from the end of the file, i.e. inserting an interval does not change the file size.

See also:

Changing the File Size

Changing the Grid Size

Changing the Group Radix

Guidelines for Working with Copies of Nodes & Groups

Overwriting a Count Value on a Waveform

Selecting a Waveform


Inserting a Clock Value on a Waveform (Waveform Editor)
Inserting a Clock Value on a Waveform

You can edit a single node waveform to include a new interval with a Clock sequence.

To insert a new Clock value on a node waveform:

1.	With the Selection pointer ( [image] ), select an interval on a single node that is equal in length to the interval you wish to insert.

2.	Open the Insert Clock dialog box by choosing Insert Clock (Edit menu) or using a shortcut.

3.	Type a logic level in the Starting Value box. The default is the current group or node value at the start of the selected interval. The logic level for a group is interpreted according to the group’s radix.

4.	Type the time interval at which the count should be incremented with a combination of the Clock Period time interval and the Multiplied By multiplier. The multiplier can be any whole number between -32000 and 32000. The default Clock Period time interval is the current grid spacing; the default multiplier is 1. The Clock Period box is dimmed and not available if Snap to Grid (Options menu) is turned on.

5.	Choose OK.

The new interval is inserted to the left of the interval or insertion point selected in step 1, and the new logic levels are displayed on the waveform.

When you insert a Clock value interval, another interval of equal length is deleted from the end of the file, i.e. inserting an interval does not change the file size.

See also:

Changing the File Size

Changing the Grid Size

Changing the Group Radix

Guidelines for Working with Copies of Nodes & Groups

Overwriting a Clock Value on a Waveform

Selecting a Waveform


Inserting a Group Value on a Waveform (Waveform Editor)
Inserting a Group Value on a Waveform

You can edit a group waveform to include a new interval with a different value (logic level) or state name.

To insert a new interval on a group waveform:

1.	With the Selection pointer ( [image] ), select an interval on a single group waveform that is equal in length to the interval you wish to insert.

2.	Open the Insert Group Value dialog box by choosing Insert Group Value (Edit menu) or using a shortcut.

3.	Type a new logic level in the Group Value box. The logic level is interpreted according to the group’s radix. In a group that represents a state machine in an SCF, you can enter the group value as either a logic level or as an equivalent state name that was defined in the project’s design files.

4.	Choose OK.

The new interval is inserted to the left of the interval selected in step 1. The logic level or state name you entered is displayed within the group waveform, and the waveforms of all individual nodes within the group are edited to create the new value. When you insert a group value interval, another interval of equal length is deleted from the end of the file, i.e., inserting an interval does not change the file size.

If you entered a logic level that is equivalent to a state name for a group that represents a state machine in an SCF, the state name is shown instead of the numerical value you entered. If you enter a logic level that is not equivalent to a state name, the logic level is displayed.

See also:

Changing the File Size

Changing the Group Radix

Guidelines for Working with Copies of Nodes & Groups

Overwriting a Group Value on a Waveform

Selecting a Waveform


Inserting a Node Waveform with a Low, High, Undefined, or High Impedance Logic Level (Waveform Editor)
Inserting a Node Waveform with a Low (0), High (1), Undefined (X), or High Impedance (Z) Logic Level

You can edit one or more node waveforms, other than state machine waveforms, to include a new interval with a low (0), high (1), undefined (X), or high-impedance (Z) logic level.

To insert a new interval on a node:

1.	With the Selection pointer ( [image] ), select an interval on one or more nodes that is equal in length to the interval you wish to insert. You may use area selection only.

2.	Choose one of the following commands from the Edit menu:

Insert Low (0) or a Shortcut

Insert High (1) or a Shortcut

Insert Undefined (X) or a Shortcut

Insert High Impedance (Z) or a Shortcut

The new interval is inserted to the left of the interval selected in step 1. When you insert an interval, another interval of equal length is deleted from the end of the file, i.e., inserting an interval does not change the file size.

See also:

Changing the File Size

Guidelines for Working with Copies of Nodes & Groups

Inverting a Node or Group Waveform

Inserting a Count Value on a Waveform

Inserting a Group Value on a Waveform

Inserting a State Name on a Waveform

Overwriting a Node Waveform with a Low, High, Undefined, or High Impedance Logic Level

Selecting a Waveform


Inserting a State Name on a Waveform (Waveform Editor)
Inserting a State Name on a Waveform

You can edit a state machine waveform to include a new interval with a different state name.

To insert a new interval on a state machine waveform in a WDF:

1.	With the Selection pointer ( [image] ), select an interval on one or more state machine waveforms that is equal in length to the interval you wish to insert. You may use area selection only.

2.	Open the Insert State Name dialog box by choosing Insert State Name or using a shortcut.

3.	Type a new name in the State Name box. The state name can contain up to 32 name characters.

4.	Choose OK.

The new interval is inserted to the left of the interval selected in step 1.

When you insert a state name interval, another interval of equal length is deleted from the end of the file, i.e., inserting an interval does not change the file size.

See also:

Changing the File Size

Changing the Group Radix

Guidelines for Working with Copies of Nodes & Groups

Overwriting a State Name on a Waveform

Selecting a Waveform


Inverting a Node or Group Waveform (Waveform Editor)
Inverting a Node or Group Waveform

You can invert a waveform interval on one or more node or group waveforms (except state machine waveforms).

Overwrite Invert (Edit menu) inverts all waveforms in the selected interval from low (0) to high (1) and high to low logic levels. Undefined (X) and high impedance (Z) logic levels remain unchanged.

To invert an interval on a node or group waveform:

1.	With the Selection pointer ( [image] ), select an interval on one or more nodes or groups.

2.	Choose Overwrite Invert or use a shortcut.

The complement of the current logic level appears on the selected interval. The waveforms of all individual nodes within an edited group are changed to create the new value.

You can also "invert" individual low or high waveforms with the Weveform Editing tool by overwriting them with their logic level compliments.

See also:

Guidelines for Working with Copies of Nodes & Groups

Overwriting a Node Waveform with a Low, High, Undefined, or High Impedance Logic Level

Overwriting a Clock Value on a Waveform

Overwriting a Count Value on a Waveform

Overwriting a Group Value on a Waveform

Selecting a Waveform


Moving a Transition (Waveform Editor)
Moving a Transition

You can manually move a logic level or state name transition on a node or group waveform. You can also automatically move a transition to a grid line.

To move a transition manually:

1.	Point to a transition on a node or group waveform with the Waveform Editing tool ( [image] ).

2.	Press Button 1.

3.	Drag the transition left or right.

4	Release Button 1.

To move a transition to a grid line:

1.	Choose Snap to Grid (Options menu) or use a shortcut.

2.	Repeat steps 1 through 4 above.

or:

1.	With the Selection pointer ( [image] ), select one or more waveform intervals or whole waveforms.

2.	Choose Align to Grid (Edit menu) or use a shortcut.

See also:

Aligning Transitions to the Grid

Guidelines for Working with Copies of Nodes & Groups

Selecting a Waveform

Snapping to the Grid


Overwriting a Count Value on a Waveform (Waveform Editor)
Overwriting a Count Value on a Waveform

You can overwrite a waveform interval on a single node or group waveform with a specific binary or Gray code count sequence.

To overwrite an interval with a count value on a node or group waveform:

1.	With the Selection pointer ( [image] ), select an interval on a single node or group and open the Overwrite Count Value dialog box by choosing Overwrite Count Value (Edit menu) or using a shortcut.

2.	Select a Count Type of Binary or Gray Code.

3.	Type a logic level in the Starting Value box. The default is the current group or node value at the start of the selected interval.

4.	Type the number by which you wish to increment the count in the Increment By box. You can type a whole number between -32000 and 32000.

5.	Type the time interval at which the count should be incremented with a combination of the Count Every time interval and the Multiplied By multiplier. The multiplier can be any whole number between -32000 and 32000. The default Count Every time interval is the current grid spacing; the default multiplier is 1. The Count Every box is dimmed and not available if Snap to Grid (Options menu) is turned on.

6.	As you enter the logic level, time, multiplier, and count increment values in the dialog box, other fields are dynamically updated to show how the overwritten interval will appear. For this reason, you cannot edit the Ending Value and it is always dimmed. When you have specified all conditions, choose OK.

The waveforms of all individual nodes within an edited group are changed to create the new value.

See also:

Changing the Grid Size

Changing the Group Radix

Guidelines for Working with Copies of Nodes & Groups

Inserting a Count Value on a Waveform

Selecting a Waveform


Overwriting a Clock Value on a Waveform (Waveform Editor)
Overwriting a Clock Value on a Waveform

You can overwrite a waveform interval on a single node waveform with a Clock sequence.

To overwrite an interval with a clock on a node or group waveform:

1.	With the Selection pointer ( [image] ), select an interval on a single node.

2.	Open the Overwrite Clock dialog box by choosing Overwrite Clock (Edit menu) or using a shortcut.

3.	Enter a logic level in the Starting Value box by typing the entry or selecting from the drop-down list box. The default is the current node value at the start of the selected interval.

4.	Type the time interval at which the count should be incremented with a combination of the Clock Period time interval and the Multiplied By multiplier. The multiplier can be any whole number between -32000 and 32000. The default Clock Period time interval is the current grid spacing; the default multiplier is 1. The Clock Period box is dimmed and not available if Snap to Grid (Options menu) is turned on.

5.	Choose OK.

The waveforms of all individual nodes within an edited group are changed to create the new value.

See also:

Changing the Grid Size

Changing the Group Radix

Guidelines for Working with Copies of Nodes & Groups

Inserting a Count Value on a Waveform

Selecting a Waveform


Overwriting a Group Value on a Waveform (Waveform Editor)
Overwriting a Group Value on a Waveform

You can overwrite a waveform interval on a single group with a different value (logic level) or state name.

To overwrite an interval on a group waveform:

1.	With the Selection pointer ( [image] ), select an interval on a single group.

or:

With the Waveform Editing pointer ( [image] ), select an interval on a single group.

2.	Choose Overwrite Group Value (Edit menu) or use a shortcut.The Overwrite Group Value dialog box opens, displaying the current logic level of the group.

3.	Type a new logic level in the Group Value box. The logic level is interpreted according to the group’s radix. In a group that represents a state machine in an SCF, you can enter the group value as either a logic level or as an equivalent state name that was defined in the project’s design files.

3.	Choose OK.

The logic level or state name you entered is displayed within the group waveform. The waveforms of all individual nodes within a group that is overwritten are edited to create the new value.

If you entered a logic level that is equivalent to a state name for a group that represents a state machine in an SCF, the state name is shown instead of the numerical value you entered. If you entered a logic level that is not equivalent to a state name, the logic level is displayed.

See also:

Changing the Group Radix

Guidelines for Working with Copies of Nodes & Groups

Inserting a Group Value on a Waveform

Moving a Transition

Selecting a Waveform


Overwriting a Node Waveform with a Low, High, Undefined, or High Impedance Logic Level (Waveform Editor)
Overwriting a Node Waveform with a Low (0), High (1), Undefined (X), or High Impedance (Z) Logic Level

You can overwrite a waveform interval on one or more individual node waveforms, other than state machine waveforms, with a low (0), high (1), undefined (X), or high-impedance (Z) logic level.

You can use both the Weveform Editing Tool and Edit menu commands to overwrite waveform intervals.

To overwrite an interval on a single node with the Waveform Editing tool:

With the Waveform Editing pointer ( [image] ), drag Button 1 over the interval you wish to overwrite

High and low logic levels are overwritten with their logic level compliment. Undefined and high-impedance logic levels are overwritten with low logic levels.

To overwrite an interval on one or more nodes with menu commands:

1.	With the Selection pointer ( [image] ), select an interval on one or more nodes.

2.	Choose one of the following commands from the Edit menu:

Overwrite Low (0) or a Shortcut

Overwrite High (1) or a Shortcut

Overwrite Undefined (X) or a Shortcut

Overwrite High Impedance (Z) or a Shortcut

See also:

Inverting a Node or Group Waveform

Inserting a Node Waveform with a Low, High, Undefined, or High Impedance Logic Level

Overwriting a Clock Value on a Waveform

Overwriting a Count Value on a Waveform

Overwriting a Group Value on a Waveform

Overwriting a State Name on a Waveform

Selecting a Waveform


Overwriting a State Name on a Waveform (Waveform Editor)
Overwriting a State Name on a Waveform

You can overwrite an interval on a one or more state machine waveforms with a different state name.

1.	With the Selection pointer ( [image] ), select an interval on one or more state machine waveforms and open the Overwrite State Name dialog box by choosing Overwrite State Name (Edit menu) or using a shortcut.

or:

With the Waveform Editing pointer ( [image] ), select an interval on a single State machine waveform.

2.	Type a new name in the State Name box. The state name can contain up to 32 name characters.

3.	Choose OK.

See also:

Changing the Group Radix

Guidelines for Working with Copies of Nodes & Groups

Inserting a State Name on a Waveform

Moving a Transition

Selecting a Waveform


Repeating a Waveform (Waveform Editor)
Repeating a Waveform

The Waveform Editor allows you to copy or cut and repeat an interval on a node or group up to 10,000 times.

To repeat a waveform:

1.	With the Selection pointer ( [image] ), select an interval on one or more node or group waveforms. You may use area selection only.

2.	Choose Copy (Edit menu) or use a shortcut.

or:

Choose Cut (Edit menu) or use a shortcut.

3.	Click Button 1 to define an insertion point or select one or more whole waveforms or waveform intervals to replace. The following rules apply:

You can paste a group waveform onto multiple node waveforms or vice versa.

You may use area selection only.

4.	Choose Repeat (Edit menu) or use a shortcut. The Repeat dialog box is displayed. A warning is issued if the paste will only partially edit a group, i.e., if only some member nodes within the group will be edited.

5.	Type a number between 1 and 10000 in the Number of Copies box.

6.	Choose OK to paste in the specified number of copies.

If you selected an insertion point rather than one or more waveforms to replace, the insertion point defines the top left corner of the pasted waveform(s). In other words, the repeated waveforms are pasted to the right and below the insertion point. When you insert a repeated interval, another interval of equal length is deleted from the end of the file, i.e., inserting an interval does not change the file size.

See also:

Changing the File Size

Copying, Cutting & Pasting Waveforms

Guidelines for Working with Copies of Nodes & Groups

Snapping to the Grid


Selecting a Waveform (Waveform Editor)
Selecting a Waveform

You can select one or more whole waveforms or waveform intervals with the Selection pointer ( [image] ).

Waveform intervals are selected differently from whole waveforms. Waveform intervals are selected in the waveform drawing area or with Select (Utilities menu); whole waveforms are selected in the Value Field:

Waveform Type:	Selected In:	Selection Type:

Interval	Waveform drawing area	Area

Interval	Select dialog box	Area

Whole waveform	Value field	Area

Area selection is performed with Button 1 either in the Value field or in the waveform drawing area, except as noted:

Mouse/Key/Command:	Action:

Press, Drag, Release	Selects all waveforms from where Button 1 is pressed to where it is released.

Click, Move, Shift+Click	Selects all waveforms between the first click and the Shift+Click.

Double-Click	Selects a waveform interval between two transitions on a single waveform. (Waveform drawing area only)

Shift+Right Arrow	Selects a single waveform from the insertion point to the next logic level transition on the right, or extends a selection on multiple nodes to the next logic level transition on the right.

Shift+Left Arrow	Selects a single waveform from the insertion point to the next logic level transition on the left, or extends a selection on multiple nodes to the next logic level transition on the left.

Select	Selects a specified interval on one or more selected nodes and groups. If all nodes or groups are unselected, it is as if all are selected and Select operates on all nodes and groups in the file.

See also:

Selecting a Node or Group

Snapping to the Grid


Creating a Waveform Design File (Waveform Editor)
Creating a Waveform Design File

Waveform design entry provides an easy way to define certain types of logic, particularly state machines. It is best suited for circuits with well-defined sequential inputs and outputs, combinatorial functions decoded from counters, and other repeating functions.

A Waveform Design File contains design logic that is defined by a combination of waveforms that represent inputs, outputs, and optional buried nodes. Logic is specified by drawing a set of input waveforms and the desired outputs. You can provide a buried node as an optional "hint" at the type of node that may exist between an input and an output. Individual design entry rules exist for each type of node: input, output, and buried.

The following procedure describes how to create WDFs for various types of logic, including combinatorial, registered, and state machine logic.

To create a WDF:

1.	Choose New (File menu) or use a shortcut, select Waveform Editor file, select the .wdf extension from the drop-down list box, and choose OK to open a new, untitled WDF.

2.	Create nodes with default logic levels for inputs and outputs.

3.	If you wish, create nodes with default logic levels for buried nodes.

4.	Edit the node waveforms to provide the desired logic, according to the following rules:

General Guidelines

Combinatorial Node Rules

Registered Node Rules

State Machine Node Rules

5.	(For registered or state machine nodes only) Specify a node to be used as the Clock input.

6.	(For registered or state machine nodes only) If you wish to designate secondary inputs, specify the nodes to be used as the Reset and Preset inputs. Reset specifies the Clear for registered nodes.

7.	If you wish to create a new, independent set of waveforms, include one or more waveform separators. Waveform separators are especially useful for combinatorial logic; they are also needed in other types of logic. Outputs after a waveform separator do not depend on any previous inputs or outputs.

8.	If you wish, enter probe, chip, logic cell, pin, clique, logic option, and/or timing assignments.

9.	Choose Save As (File menu) to save the file.

10.	If the WDF will be incorporated into a hierarchy of design files, choose Create Default Symbol (File menu) to create a symbol that can be used to incorporate the WDF’s logic into a GDF or OrCAD Schematic File.

or:

Create a TDF that contains a Function Prototype Statement listing all inputs and outputs of the WDF. You can also use Create Default Include File (File menu) to create an Include File that contains a Function Prototype Statement.

See also:

Assigning a Clique

Assigning a Device

Assigning an Individual Logic Option or Synthesis Style

Assigning a Pin, Location, or Chip

Assigning a Probe

Assigning Individual Timing Requirements

Creating & Deleting a Waveform Separator

Creating a Default Include File

Creating a New File

Creating a Node

Creating the Default Symbol for a File

Guidelines for Working with Assignments

Recovering from Illegal States

Saving a File

Specifying Global Project Logic Synthesis Settings

Specifying Global Project Timing Requirements

Recommended reading:

AN28 (Waveform Design Entry)

AB92 (Simulating Internal Nodes with MAX+PLUS II Software)


General Guidelines (Waveform Editor)
General Guidelines

The following guidelines apply to creating and editing nodes in a WDF:

Include all possible combinations of input values in the WDF.

-	Output values are only valid for the set of inputs you specify in the WDF; inputs can change at any time.

-	Since the same set of logic levels cannot create two different outputs, only one output is allowed for a given set of inputs.

-	You must specify all input combinations and the exact outputs that you want, since the Compiler generates only the minimum logic necessary to implement the logic specified in the file.

-	The Compiler creates "don’t care" (X) output values for all unspecified combinations of inputs.

The Snap to Grid (Options menu) command is turned on permanently in a WDF to help you align transitions. Avoid changing the grid size after creating nodes. Otherwise, the transitions of all existing nodes may not be aligned to the grid.

The grid size in a WDF is arbitrary. Select any grid size that is convenient for drawing your waveforms.

Align all logic level and state name transitions. Otherwise, the Compiler may create unintended logic.


Combinatorial Node Rules (Waveform Editor)
Combinatorial Node Rules

The following rules apply to combinatorial nodes in a WDF:

A combinatorial node must change at the same time that inputs change.

Assume a 0 ns propagation delay for all combinatorial logic.

Combinatorial nodes depend on the current values of every input, buried, and output node in the WDF.

Limit inputs for purely combinatorial functions. As the number of inputs increases, the possible combinations of these inputs expand exponentially.


Registered Node Rules (Waveform Editor)
Registered Node Rules

The following rules apply to registered nodes in a WDF:

A registered node can have a logic level transition only on a rising Clock edge.

The inputs that change the register value must change at least 0.1 ns before the rising Clock edge. In other words, assume a setup time of at least 0.1 ns and a hold time of 0.

Assume a 0 ns propagation delay for all registered logic.

The value of each registered node is a function of the previous values of some or all of the other input, buried, or output nodes in the WDF.


State Machine Node Rules (Waveform Editor)
State Machine Node Rules

The following rules apply to state machine nodes in a WDF:

Plan to create a top-level GDF or TDF for the project. Machine inputs and outputs cannot feed device pins, so a WDF that contains a state machine cannot be the only design file in a project.

Transitions, i.e., state name changes, must occur on Clock edges.

The inputs that change the state name must change at least 0.1 ns before the rising Clock edge. In other words, assume a setup time of at least 0.1 ns and a hold time of 0.

The current state of each state machine node is a function of the previous state and the previous values of some or all of the other input, buried, or output nodes in the WDF.


Guidelines for Working with Copies of Nodes & Groups (Waveform Editor)
Guidelines for Working with Copies of Nodes & Groups

When you copy a node or group in the Waveform Editor, its waveform is linked to all other nodes and groups with the same name.

The links between copies have the following effects when you edit nodes and groups:

If you edit the waveform of one copy of a node, the edits are reflected in all copies in the file, including those copies that are part of a group.

If you edit a group, all copies of all nodes in that group are also edited.

If you paste a node from another file that has the same name as a node in the current file, its waveform overwrites the waveform of the node in the current file. In other words, pasting the node is the same as overwriting a copy of the node, even if you pasted the new item in a blank space.

If you paste a group from another file that contains a node with the same name as a node in the current file, its waveform overwrites the waveform of the node in the current file.

If you paste a group from another file that has the same name as a group in the current file, its waveform overwrites the waveform of the group in the current file.

If you delete an entire node or group, you do not delete other copies.

Ungrouping a group does not ungroup all copies of the group.

Renaming a node or group removes the link between it and other nodes or groups with the same name.

These features are important to remember when you use procedures that edit node and group waveforms, node types, I/O types, secondary inputs, and group radixes.

See also:

Renaming a Node or Group


---------------------BEGINNING OF NON-TRANSLATED TEXT---------------------------------

Messages from wedmsgs.msg that are documented elsewhere (not in this file):

SWED_SCF_LOCKED	simess.mac

SWED_SNF_LOCKED	simess.mac

SWED_STATE_IGNORED	simess.mac

HWED_TABLE_FILE_CREATED	simess.mac

SWED_NO_PATTERN_FOUND	edmess.mac

SWED_REPLACE_DONE	edmess.mac

YWED_CONT_SEARCH_AT_TOP	edmess.mac

YWED_CONT_SEARCH_AT_BEGINNING	edmess.mac

**Update wedmsgs.msg file to show that these 2 msg. are documented**

CWED_OK_TO_OVERWRITE	glmess.mac

SWED_OUT_OF_MEMORY	glmess.mac

SWPR_CANT_START_PRINT	glmess.mac

SWPR_CANT_READ_PRINTER	glmess.mac

SWPR_OUT_OF_MEMORY	glmess.mac

SWPR_IP_COPIES_ERROR	tamess.mac

Messages from other applications/files that are documented here:

STAN_TOO_MANY_NODES	tanmsgs.msg

STAN_TOO_MANY_NODES_ABORTED	tanmsgs.msg

------------------------------END OF NON-TRANSLATED TEXT------------------------------------


Cant change an existing node into multiple nodes
 Cant change an existing node into a group

CAUSE:	You tried to replace an existing node name with a decimal group name in the Enter Node dialog box. A node name can consist of up to 32 name characters.

ACTION:	To create a group, double-click Button 1 on a blank line in the node information area to open the Enter Node dialog box and type a decimal group name, or select two or more nodes and choose Enter Group (Node menu).

See also:

Creating a Group

Creating a Node

MAX+PLUS II Messages

Message Format

Renaming a Node or Group


 Cant compare file

CAUSE:	You chose Compare (File menu), but the file you specified to compare cant be opened or read. This message may indicate that the file has the wrong format or extension, your disk is full, or you have a disk error.

ACTION:	Ensure that the file you wish to compare is either a WDF or SCF. If your disk is nearly full, delete files to create more space. Run the DOS CHKDSK/F program to check for disk errors.

See also:

Comparing Files or Simulation Outputs

MAX+PLUS II Messages

Message Format


 Cant include a machine node in a group

CAUSE:	You selected one or more nodes with a node type of machine and chose Enter Group (Node menu) to create a group. However, machine nodes cannot be grouped: their waveforms represent state names, not logic levels.

ACTION:	Use only non-machine nodes or groups to create a group.

See also:

Creating a Group

Creating a Node

MAX+PLUS II Messages

Message Format

Recommended reading:

AN28 (Waveform Design Entry)


 Cant paste a machine node from a WDF into an SCF

CAUSE:	You copied a node with a node type of machine from a WDF and tried to paste it into an SCF. You cannot copy a machine node into an SCF.

ACTION:	Copy a different node and try again.

See also:

Buried Nodes

Copying, Cutting & Pasting Nodes and Groups

Copying, Cutting & Pasting Waveforms

Input Nodes

MAX+PLUS II Messages

Message Format

Output Nodes

Simulator Channel File (.scf)

Waveform Design File (.wdf)

Recommended reading:

AN28 (Waveform Design Entry)

AB92 (Simulating Internal Nodes with MAX+PLUS II Software)


Cant paste selection
 Cant paste

CAUSE:	You copied or cut one or more items and chose Paste (Edit menu), but the Clipboard contains information that is not compatible with the current file.

ACTION:	Try copying or cutting and pasting again. Objects other than text can be pasted only if they are compatible with the format of the file. Text can be copied and pasted into different MAX+PLUS II files.

See also:

Copying, Cutting & Pasting Nodes and Groups

Copying, Cutting & Pasting Text

Copying, Cutting & Pasting Waveforms

MAX+PLUS II Messages

Message Format


 Cant replace node that is part of a group with a machine node

CAUSE:	You copied one or more nodes with a node type of machine, and tried to paste it into a file that contains a non-machine node with the same name that is also a member of a group. A machine node cannot be a member of a group.

ACTION:	Copy non-machine nodes and try again.

See also:

Buried Nodes

Copying, Cutting & Pasting Nodes and Groups

Copying, Cutting & Pasting Waveforms

Groups

Input Nodes

MAX+PLUS II Messages

Message Format

Output Nodes

Simulator Channel File (.scf)


Can't save file to <name> -- filename is reserved for Clipboard operations
 Cant save file to <name> -- filename is reserved for Clipboard operations

CAUSE:	You have attempted to save a file to the name wedclp.scf, which is the reserved filename for Clipboard information.

ACTION:	Enter another legal filename with up to eight name characters to save the file.

See also:

MAX+PLUS II Messages

Message Format

Saving a File


File <name> will be overwritten by the default channel or Vector File information. OK to overwrite the file?
 File <name> will be overwritten by the new information. OK to overwrite the file?

CAUSE:	You chose Enter Nodes from SNF (Node menu) or Import Vector File (File menu). These commands overwrite the information in the current file with information from the projects SNF or a Vector File, respectively.

ACTION:	If you do not want to overwrite the current file, choose Cancel to cancel the command. You can then either create a new file with New (File menu) or save your edits to another file with Save As (File menu), and then choose Enter Nodes from SNF or Import Vector File again. Otherwise, choose OK.

See also:

Creating a Default Channel File

Importing a Vector File

MAX+PLUS II Messages

Message Format

Saving a File


 Group <name> already exists

CAUSE:	You chose  Enter Group or Enter Node (Node menu) and have typed a name that is already assigned to another group in the file.

ACTION:	Type a different group name with up to 32 name characters. You can also use a decimal group name. To rename an existing group, select the group before choosing Enter Group or Enter Node.

See also:

Creating a Group

Guidelines for Working with Copies of Nodes & Groups

MAX+PLUS II Messages

Message Format

Renaming a Node or Group


 Illegal bus/group name: <text>

CAUSE:	You chose Enter Group (Node menu) and typed a group name that is too long, contains an illegal character, or already exists with the same I/O type.

ACTION:	Type another name with up to 32 name characters, or a decimal group name or sequential group name.

XXXX - need to update cause/action to incluse bus info (the .msg file says user tried to make an assignment to an illegal bus name)

See also:

Creating a Group

Creating a Node

Groups

MAX+PLUS II Messages

Message Format

Renaming a Node or Group


 Illegal count <text> (min. = -32000, max. = 32000)

CAUSE:	You chose Insert Count Value or Overwrite Count Value (Edit menu), and typed a value that is not a whole number.

ACTION:	Type a whole number between -32000 and 32000.

See also:

Inserting a Count Value on a Waveform

MAX+PLUS II Messages

Message Format

Overwriting a Count Value on a Waveform


 Illegal group value: <text>

CAUSE:	You chose Insert Group Value or Overwrite Group Value (Edit menu), and typed a group value (logic level) that is too long or contains an illegal character.

ACTION:	Type a different group value with a logic level that is legal for the current group radix.

See also:

Changing the Group Radix

Changing the Node Type, I/O Type, Secondary Inputs, or Default Value

Inserting a Group Value on a Waveform

MAX+PLUS II Messages

Message Format

Overwriting a Group Value on a Waveform


 Illegal horizontal page scale (min. = <number>, max. = <number>)

CAUSE:	You chose Print (File menu), and typed an incorrect value in the Page(s) Horizontally option.

ACTION:	Type a different value within the specified range in the Page(s) Horizontally option.

See also:

MAX+PLUS II Messages

Message Format

Printing a File


 Illegal node name: <text>

CAUSE:	You chose Insert Node (Node menu), and typed a name that is too long or contains an illegal character.

ACTION:	Type another name with up to 32 name characters. If you wish to create a group, you may also use a decimal group name. A hierarchical node name can contain up to 128 characters.

See also:

Creating a Group

Creating a Node

Hierarchical Node & Symbol Names

MAX+PLUS II Messages

Message Format

Renaming a Node or Group

Recommended reading:

AN28 (Waveform Design Entry)

AB92 (Simulating Internal Nodes with MAX+PLUS II Software)


 Illegal node value: <text>

CAUSE:	You created a node or edited its default value (logic level) with Insert Node (Node menu) and typed a value that is too long or contains an illegal character.

ACTION:	Type a legal logic level or select one of the logic levels in the drop-down list box.

See also:

Changing the Node Type, I/O Type, Secondary Inputs, or Default Value

Creating a Node

MAX+PLUS II Messages

Message Format


 Illegal repeat value (min. = 1, max. = 10000)

CAUSE:	You chose Repeat (Edit menu) and typed an invalid value for the number of times to repeat the selected waveform interval.

ACTION:	Type a whole number between 1 and 10000.

See also:

Buried Nodes

Changing the Node Type, I/O Type, Secondary Inputs, or Default Value

Creating a Node

Groups

Input Nodes

MAX+PLUS II Messages

Message Format

Output Nodes


Illegal start and/or end times. Start time = <number>, end time = <number>
 Illegal start and/or end times:

Start time = <number>, end time = <number>

CAUSE:	You chose Print (File menu), and typed an incorrect start and/or end time value in the From and/or To boxes that specify the time range to be printed.

ACTION:	Type in a legal start and/or end time value and optional time unit. Each time value must be a number between 0 and 28147.4976710655 seconds. The end of the time range must be later than the start. Make sure that there is no space between the time value and the time unit.

See also:

MAX+PLUS II Messages

Message Format

Printing a File


 Illegal state name: <text>

CAUSE:	You chose Insert Node (Node menu), Insert State Name, or Overwrite State Name (Edit menu) and typed a state name that is too long or contains an illegal character.

ACTION:	Enter another state name with up to 32 name characters.

See also:

Creating a Node

Inserting a State Name on a Waveform

MAX+PLUS II Messages

Message Format

Overwriting a State Name on a Waveform


 New group must have a radix

CAUSE:	You selected two or more groups with different radixes and chose Enter Group (Node menu) to create a new group, but did not select a radix for the new group.

ACTION:	Select a group radix.

See also:

Changing the Group Radix

Creating a Group

MAX+PLUS II Messages

Message Format


New selected interval must include part of original interval
 New interval must include part of original interval

CAUSE:	You chose Grow or Shrink (Edit menu) and entered values for a new interval that did not include part of the original waveform interval.

ACTION:	Enter a new start and/or end time that includes part of the original interval.

See also:

Growing or Shrinking a Waveform

MAX+PLUS II Messages

Message Format


No SNF <filename> exists for the project -- can't create default SCF
 No SNF <filename> exists for the project -- cant create default SCF

CAUSE:	You chose Enter Nodes from SNF (Node menu), but no SNF has been created for the project.

ACTION:	Recompile the current project with the Compilers Timing SNF Extractor or Functional SNF Extractor command (Processing menu) turned on to create a timing SNF or functional SNF for simulation.

See also:

Creating a Default Channel File

Creating a Functional Simulator Netlist File

Creating a Timing Simulator Netlist File

MAX+PLUS II Messages

Message Format

Simulator Channel File (.scf)

Simulator Netlist File (.snf)

Recommended reading:

AB92 (Simulating Internal Nodes with MAX+PLUS II Software)


 Node <name> already exists

CAUSE:	You chose Insert Node (Node menu) and have typed a name that is already assigned to another node in the file.

ACTION:	Type a different node name with up to 32 name characters. If you wish to create multiple nodes, you can also use a decimal group name. To rename an existing node, select the node before choosing Enter Node.

See also:

Creating a Node

Guidelines for Working with Copies of Nodes & Groups

MAX+PLUS II Messages

Message Format

Renaming a Node or Group


Node characteristics in current file will be overwritten with information in Clipboard. OK to paste?
 Node characteristics in current file will be replaced with information in Clipboard. OK to paste?

CAUSE:	You copied one or more nodes, then chose Paste (Edit menu) in another file that contains node(s) with the same name. If you paste the nodes, the node characteristics (i.e., waveforms, I/O types, and node types) of the node(s) in the Clipboard will overwrite the existing characteristics of the node(s) in the target file.

ACTION:	If you do not want to overwrite the nodes, choose Cancel to cancel the paste. Otherwise, choose OK.

See also:

Guidelines for Working with Copies of Nodes & Groups

MAX+PLUS II Messages

Message Format


 Node or group must have a name

CAUSE:	You chose Insert Node or Enter Group (Node menu), but did not specify a name.

ACTION: 	If the message occurs for a node, type a name with up to 32 name characters. If you wish to create multiple nodes, you can also use a decimal group name. If the message occurs for a group, type a name with up to 32 name characters, or a decimal group name or sequential group name.

See also:

Changing the Node Type, I/O Type, Secondary Inputs, or Default Value

Creating a Group

Creating a Node

MAX+PLUS II Messages

Message Format

Renaming a Node or Group


Number of waveforms to be pasted is different from the number in the selected area. OK to paste?
 Number of waveforms to be pasted differs from the number in the selected area. OK to paste?

CAUSE:	The number of waveform intervals that you have copied into the Clipboard is not the same as the number of waveform intervals that you selected before choosing Paste (Edit menu). This warning indicates that the number of waveforms that you have copied differs from the number you selected to be overwritten by the paste (i.e., the block of waveforms that you have copied is taller or shorter than the area you selected to be overwritten).

ACTION:	If you do not want to overwrite the waveforms in the file, choose Cancel to cancel the paste. Otherwise, choose OK to paste in all information from the Clipboard.

See also:

Copying, Cutting & Pasting Nodes and Groups

Copying, Cutting & Pasting Waveforms

MAX+PLUS II Messages

Message Format

Selecting a Waveform


OK to create default channel with no nodes or groups?
 OK to create a default channel with no nodes or groups?

CAUSE:	You chose Enter Nodes from SNF (Node menu) but did not copy any nodes or groups to the Selected Nodes & Groups box in the dialog box.

ACTION:	Choose OK to create an empty default SCF. If you want to add nodes and groups to the file, choose Cancel to return to the Enter Nodes from SNF dialog box.

See also:

Creating a Default Channel File

MAX+PLUS II Messages

Message Format

Simulator Channel File (.scf)

Recommended reading:

AB92 (Simulating Internal Nodes with MAX+PLUS II Software)


 OK to overwrite old version of file format?

CAUSE:	You opened a file from MAX+PLUS (DOS) and chose Save (File menu). MAX+PLUS II is asking for permission to save the file in the most up-to-date file format.

ACTION:	Choose OK to overwrite the MAX+PLUS (DOS) version of the file. Choose Cancel if you intend to use the file again with MAX+PLUS (DOS), so that the file is not saved in the new format. If you want to save the changes to the file without overwriting the MAX+PLUS (DOS) version, choose Cancel and then choose Save As and save the edits to another filename.

See also:

MAX+PLUS II Messages

Message Format

Saving a File


 Pasting will edit only part of the group. OK to paste?

CAUSE:	After copying one or more nodes, you selected a group that contains fewer members than the copied nodes, then chose Paste (Edit menu) in another file that contains node(s) with the same name. If you paste the nodes, some but not all of the members of the group will be changed.

ACTION:	If you do not want to partially overwrite the group, choose Cancel to cancel the paste. You can select a different set of nodes or waveforms to overwrite and choose Paste again. Otherwise, choose OK.

See also:

Copying, Cutting & Pasting Nodes and Groups

Copying, Cutting & Pasting Waveforms

Guidelines for Working with Copies of Nodes & Groups

MAX+PLUS II Messages

Message Format

Selecting a Node or Group

Selecting a Waveform


 State <name> already exists

CAUSE:	You chose Search & Replace (Edit menu) and typed a state name that already exists as the replacement text. You cannot rename a state with a name that is already used in the file.

ACTION:	Enter new replacement text and try again.

See also:

Finding & Replacing Text

MAX+PLUS II Messages

Message Format

State Machine


Too many nodes/groups: out of memory
 Too many nodes/groups to list: out of memory

CAUSE:	You have insufficient memory to list all of the nodes and/or groups that match the current node name string and Type options in the dialog box for the Enter Nodes from SNF or Insert Node command (Node menu) in the Waveform Editor, or the Timing Analysis Source, Timing Analysis Destination, or Timing Analysis Cutoff commands (Node menu) in the Timing Analyzer. This message occurs if there are more than 4,096 nodes/groups to be displayed in the Available Nodes or Selected Nodes list in the dialog box, or if your computer has run out of memory.

ACTION:	Increase the memory available to MAX+PLUS II, either by quitting other programs or by installing more memory in your computer. You can also reduce the number of nodes/groups to be listed in the dialog box by changing the node/group name string and the Type options. If this message occurred when you tried to copy nodes from the Available Nodes to the Selected Nodes list, you must ensure that the number of selected nodes is less than 4,096.

See also:

Creating a Default Channel File

Creating a Node

MAX+PLUS II Messages

Message Format

Tagging Timing Cutoff Nodes

Tagging Timing Source & Destination Nodes

Recommended reading:

AB92 (Simulating Internal Nodes with MAX+PLUS II Software)


 Value <number> is not a <text> time value

CAUSE:	You chose Time Range (View menu), but typed an illegal time value or an invalid end time value. An illegal time value is too long or contains an illegal character or an incorrect time unit. An invalid end time value is an end time that is less than the start time.

ACTION:	Type in a legal time value and optional time unit. The time value must be a number between 0 and 28147.4976710655 seconds. The end of the time range must be later than the start. Make sure that there is no space between the time value and the time unit.

See also:

Going to a Time Range

MAX+PLUS II Messages

Message Format


 Vertical page scale must be an integer between <number> and <number>

CAUSE:	You chose Print (File menu), and typed an incorrect value in the Page(s) Vertically box.

ACTION:	Type an integer within the specified range in the Page(s) Vertically box.

See also:

MAX+PLUS II Messages

Message Format

Printing a File


Waveform Editor Commands
Commands

For Help, choose a command name or dialog box name from the following list. Menu names are not included on the list.

About MAX+PLUS II	Maximum Size

Advanced Options	Megafunctions/LPM

AHDL	Message Processor

Align to Grid	Messages

Analyze Timing	Minimize

Archive	More Windows

Arrange Icons	Move

Authorization Code	Name

Auto Device Selection	New

Back-Annotate Project	New Features in This Release

Basic Tools	New Window

Cascade	Next

Classic & MAX Global Project Device Options	Normal Size

Classic & MAX Individual Device Options	Old-Style Macrofunctions

Clear All Timing Tags	Open

Clear Project Assignments	Overwrite Clock

Clique	Overwrite Count Value

Close (File menu)	Overwrite Group Value

Close ( [image] and [image] menus)	Overwrite High (1)

Color Palette	Overwrite High Impedance (Z)

Commands	Overwrite Invert

Compare	Overwrite Low (0)

Compiler	Overwrite State Name

Connected Pins	Overwrite Undefined (X)

Convert Obsolete Assignment Format	Paste

Copy	Pin/Location/Chip

Create Default Include File	Preferences

Create Default Symbol	Primitives

Create Table File	Print

Cut	Print Setup

Define Synthesis Style	Probe

Delete	Procedures

Delete File	Programmer

Device	Project 1, 2, 3, 4...

Devices & Adapters	Project Archive

Edit Node	Project Name

Edit Symbol	Project Save & Check

End Time	Project Save & Compile

Enter Group	Project Save & Simulate

Enter Nodes from SNF	Project Save, Compile & Simulate

Enter Separator	Project Set Project to Current File

ES Site License Authorization Request	READ.ME

Exit MAX+PLUS II	Rename Chip

Find Last Edit	Repeat

Find Next	Restore

Find Next Transition	Retrieve

Find Node in Design File	Save

Find Node in Floorplan	Save & Check

Find Previous	Save & Compile

Find Previous Transition	Save & Simulate

Find Text	Save As

Fit in Window	Save Style As

FLEX 10K Global Project Device Options	Save, Compile & Simulate

FLEX 10K Individual Device Options	Search & Replace

FLEX 8000 Global Project Device Options	Search for Help on

FLEX 8000 Individual Device Options	Search Node Database

Floorplan Editor	Select

Global Project Device Options	Set Project to Current File

Global Project Logic Synthesis 	Shortcuts

Global Project Timing Requirements	Show Grid

Glossary	Show Status Bar

Go To	Show Toolbar

Golden Rules	Simulator

Graphic Editor	Size ( [image] and [image] menus)

Grid Size	Snap to Grid

Grow or Shrink	Sort Names

Hierarchy Display	Switch To

Hierarchy Down	Symbol Editor

Hierarchy Project Top	Table of Contents

Hierarchy Top	Text Editor

Hierarchy Up	Tile Horizontally

How to Use Help	Tile Vertically

How to Use MAX+PLUS II Help	Time Range

Ignore Project Assignments	Timing Analyzer

Import Vector File	Timing Cutoff

Individual Logic Options	Timing Destination

Info	Timing Requirements

Insert Clock	Timing Source

Insert Count Value	Undo

Insert Group Value	Ungroup

Insert High (1)	User Libraries

Insert High Impedance (Z)	VHDL

Insert Low (0)	Waveform Editor

Insert Node	Waveform Editor Help Basic Tools

Insert State Name	Waveform Editor Help Commands

Insert Undefined (X)	Waveform Editor Help Golden Rules

Introduction	Waveform Editor Help Introduction

Logic Options	Waveform Editor Help Procedures

MAX 7000S Global Project Device Options	Waveform Editor Help Shortcuts

MAX 7000S Individual Device Options	Waveform Editor Help Table of Contents

MAX+PLUS II Registration	Zoom In

MAX+PLUS II Table of Contents	Zoom Out

Maximize


Save As Command (Waveform Editor)
Save As Command (File Menu)

Saves a new version of the current file under a different name, in a different directory, or on a different drive. Save As also saves a new file for the first time.

Click Button 1 on any item in this dialog box for information on that item:

You can save an SCF as a WDF and vice versa.

See also:

Saving a File


End Time Command (Waveform Editor)
End Time Command (File Menu)

Specifies a new end time for the current file.

Click Button 1 on any item in this dialog box for information on that item:

When you increase the length of a file, the logic levels on node and group waveforms that originally appeared at the end of the file are extended through the new portion of the file.

See also:

Changing the File Size


End Time dialog box (Waveform Editor)
End Time dialog box

Click Button 1 on any item in this dialog box for information on that item:


End Time

Specifies the end time for the file. The current end time is displayed as the default.

Type a new time, followed immediately (i.e., with no space in between) by a time unit; the default is ns.


Compare Command (Waveform Editor)
Compare Command (File Menu)

Selects a Waveform Editor file to compare with the current file or ends the current comparison. Both WDFs and SCFs can be compared.

If the Waveform Editor is not already in its compare mode, Compare opens the Compare dialog box. If the Waveform Editor is in compare mode, the comparison ends when you choose Compare.

Click Button 1 on any item in this dialog box for information on that item:

After you choose a file to compare, the Waveform Editor superimposes the two files to highlight the differences between them. The original file remains unchanged on screen. Example

The Simulator executes Compare automatically when its Check Outputs option is turned on. In this case, the outputs of simulation are not saved to an SCF, but are stored in a temporary data buffer. This temporary output data is then superimposed on the outputs in the current SCF, and the title bar of the Waveform Editor window includes the words Check Outputs. If the Simulator’s Use Device option is also turned on, actual device outputs, rather than simulation outputs, are compared to the outputs in the current SCF.

Only the waveforms of the compared file are displayed (node and group names are not). The Waveform Editor finds and superimposes nodes of the same name, regardless of whether they are in the same order in the compared file. If a node does not exist in the compared file, no compared waveform appears for the node.

While you are comparing files or simulation outputs, any editing commands you enter are applied only to the "original" file.

See also:

Changing Colors in MAX+PLUS II

Comparing Files or Simulation Outputs


Compare dialog box (Waveform Editor)
Compare dialog box

Click Button 1 on any item in this dialog box for information on that item:


Example of compared waveforms


Import Vector File Command (Waveform Editor)
Import Vector File Command (File Menu)

Converts an ASCII-format Vector File into a Waveform Editor file that can be saved as a WDF or SCF.

Click Button 1 on any item in this dialog box for information on that item:

Because Import Vector File overwrites all information in the current file with Vector File information, MAX+PLUS II warns you before it converts the file. If you do not wish to overwrite the current file, create a new file with New (File menu) before choosing Import Vector File.

See also:

Creating a New File

Importing a Vector File

Vector File Format

Recommended reading:

AB92 (Simulating Internal Nodes with MAX+PLUS II Software)


Import Vector File dialog box (Waveform Editor)
Import Vector File dialog box

Click Button 1 on any item in this dialog box for information on that item:


Create Table File Command (Waveform Editor)
Create Table File Command (File Menu)

Creates an ASCII-format Table File that records all logic level transitions for nodes and groups in the current SCF or WDF.

The Table File format is identical to Vector File format.

Click Button 1 on any item in this dialog box for information on that item:

See also:

Creating a Table File

Recommended reading:

AB92 (Simulating Internal Nodes with MAX+PLUS II Software)


---------------------BEGINNING OF NON-TRANSLATED TEXT---------------------------------

Create Table File dialog box is stored in sicom (max_bmp_cretable).

------------------------------END OF NON-TRANSLATED TEXT------------------------------------


Print Command (Waveform Editor)
Print Command (File Menu)

Shortcuts

Prints all or part of the current file.

Click Button 1 on any item in this dialog box for information on that item:

MAX+PLUS II prints the file according to the settings for the current printer, which are specified with Print Setup (File menu).

See also:

Printing a File


Print dialog box (Waveform Editor)
Print dialog box

Click Button 1 on any item in this dialog box for information on that item:


Time Range

All	Prints the entire file.

From ? To ?	Specify a time period to print. Type a start time and end time, followed immediately (i.e., with no space in between) by a time unit; the default is ns.


Pages

Fit Into

Page(s) Horizontally	Specifies how many pages should be used to print the names of the nodes and groups in the file. This option controls the number of node and group names that are printed on each page.

Page(s) Vertically	Specifies how many pages should be used to print each waveform in the file. This option controls the scale used to print the waveforms.


Print

Page Headers	Prints the filename, date, page count, and project name at the top of each page.

Node Information 	Prints the node and group names on each page.

On All Pages


Cut Command (Waveform Editor)
Cut Command (Edit Menu)

Shortcuts

Deletes selected text, or one or more selected nodes, groups, or waveforms from your file and places them on the Clipboard. The previous contents of the Clipboard are erased.

Use Paste (Edit menu) to insert cut text, nodes, or waveforms at a different location. The contents of the Clipboard can be pasted multiple times. Use Repeat (Edit menu) to paste a single cut waveform interval a precise number of times.

Cut text can be pasted into different MAX+PLUS II files and into different types of text fields. For example, a pin name from a WDF can be pasted into a TDF. Waveform Editor graphics (nodes, groups, and their waveforms) can only be pasted into other Waveform Editor files.

Use Delete (Edit menu) instead of Cut to remove objects from your file without affecting the contents of the Clipboard.

A copied node or group is linked to the original node or group, and all waveform edits that affect one copy are repeated in the other copies. Renaming a copy removes the link to the original.

See also:

Copying, Cutting & Pasting Nodes and Groups

Copying, Cutting & Pasting Text

Copying, Cutting & Pasting Waveforms

Deleting Text

Guidelines for Working with Copies of Nodes & Groups

Repeating a Waveform

Selecting a Node or Group

Selecting Text

Selecting a Waveform


Copy Command (Waveform Editor)
Copy Command (Edit Menu)

Shortcuts

Copies selected text, or one or more nodes, groups, or waveforms from your file and places them on the Clipboard. The previous contents of the Clipboard are erased.

Use Paste (Edit menu) to place the copied text, nodes, or waveforms at another location. The contents of the Clipboard can be pasted multiple times. Use Repeat (Edit menu) to paste a single copied waveform interval a precise number of times.

After you select Copy, the selected objects remain selected.

Copied text can be pasted into different MAX+PLUS II files and into different types of text fields. For example, a pin name from a WDF can be pasted into a TDF. Waveform Editor graphics (nodes, groups, and their waveforms) can only be pasted into other Waveform Editor files.

A copied node or group is linked to the original node or group, and all waveform edits that affect one copy are repeated in the other copies. Renaming a copy removes the link to the original.

See also:

Copying, Cutting & Pasting Nodes and Groups

Copying, Cutting & Pasting Text

Copying, Cutting & Pasting Waveforms

Guidelines for Working with Copies of Nodes & Groups

Repeating a Waveform

Selecting a Node or Group

Selecting Text

Selecting a Waveform


Paste Command (Waveform Editor)
Paste Command (Edit Menu)

Shortcuts

Places a copy of the Clipboard’s contents at the selected insertion point. The Clipboard contains a selection defined with the last Cut or Copy  command (Edit menu).

If a text insertion point has been defined, Paste inserts the contents of the Clipboard to the left of the insertion point. If a graphical insertion point has been defined, Paste inserts the waveform(s) in the Clipboard so that their top left corner is at the insertion point. If one or more nodes or groups, text characters, or a waveform interval is selected, Paste overwrites the selected items.

The contents of the Clipboard can be pasted multiple times. Use Repeat (Edit menu) to paste a single copied or cut waveform interval a precise number of times.

Copied or cut text can be pasted into different MAX+PLUS II files and into different types of text fields. For example, a pin name from a WDF can be pasted into a TDF. Waveform Editor graphics (nodes, groups, and their waveforms) can only be pasted into other Waveform Editor files.

A copied node or group is linked to the original node or group, and all waveform edits that affect one copy are repeated in the other copies. Renaming a copy removes the link to the original.

See also:

Copying, Cutting & Pasting Nodes and Groups

Copying, Cutting & Pasting Text

Copying, Cutting & Pasting Waveforms

Guidelines for Working with Copies of Nodes & Groups

Repeating a Waveform

Selecting a Node or Group

Selecting Text

Selecting a Waveform


Overwrite Low (0), High (1), Undefined (X) & High Impedance (Z) Commands (Waveform Editor)
Overwrite Low (0), High (1), Undefined (X) & High Impedance (Z) Commands (Edit Menu)

Shortcuts

Overwrite a selected whole waveform or waveform interval on one or more individual nodes with a low (0), high (1), undefined (X), or high-impedance (Z) logic level.

These commands overwrite the selected interval on all copies of the node that exist in the current file, including copies that are included in a group. These commands operate on individual node waveforms only, not on group (bus) or state machine waveforms.

See also:

Guidelines for Working with Copies of Nodes & Groups

Inverting a Node or Group Waveform

Overwriting a Clock Value on a Waveform

Overwriting a Count Value on a Waveform

Overwriting a Group Value on a Waveform

Overwriting a Node Waveform with a Low, High, Undefined, or High Impedance Logic Level

Overwriting a State Name on a Waveform

Selecting a Waveform


Overwrite Invert Command (Waveform Editor)
Overwrite Invert Command (Edit Menu)

Shortcuts

Inverts a selected whole waveform or waveform interval on one or more nodes or groups.

Overwrite Invert inverts the selected interval from low (0) to high (1) and high to low logic levels. Undefined (X) and high impedance (Z) logic levels remain unchanged.

Overwrite Invert overwrites the selected interval on all copies of the node that exist in the current file, including copies that are included in a group. This command is not available for state machine waveforms.

You can also invert waveforms with the Waveform Editing tool.

See also:

Guidelines for Working with Copies of Nodes & Groups

Inverting a Node or Group Waveform

Overwriting a Clock Value on a Waveform

Overwriting a Count Value on a Waveform

Overwriting a Group Value on a Waveform

Overwriting a Node Waveform with a Low, High, Undefined, or High Impedance Logic Level

Overwriting a State Name on a Waveform

Selecting a Waveform


Overwrite Clock Command (Waveform Editor)
Overwrite Clock Command (Edit Menu)

Shortcuts

Overwrites a selected whole waveform or waveform interval on one or more individual nodes with a clock sequence.

Click Button 1 on any item in this dialog box for information on that item:

Overwrite Clock overwrites the selected interval on all copies of the node that exist in the current file, including copies that are included in a group. This command operates on individual node waveforms only, not on group (bus) or state machine waveforms.

See also:

Guidelines for Working with Copies of Nodes & Groups

Inverting a Node or Group Waveform

Overwriting a Clock Value on a Waveform

Overwriting a Count Value on a Waveform

Overwriting a Group Value on a Waveform

Overwriting a Node Waveform with a Low, High, Undefined, or High Impedance Logic Level

Overwriting a State Name on a Waveform

Selecting a Waveform


Overwrite Clock dialog box (Waveform Editor)
Overwrite Clock dialog box

Click Button 1 on any item in this dialog box for information on that item:


Overwrite Count Value Command (Waveform Editor)
Overwrite Count Value Command (Edit Menu)

Shortcuts

Overwrites a selected whole waveform or waveform interval on a single group waveform with a specified count sequence.

Click Button 1 on any item in this dialog box for information on that item:

Overwrite Count Value overwrites the selected interval on all copies of the group and member nodes that exist in the current file, including copies of the group that are included in a group. This command is not available for individual node or state machine waveforms.

See also:

Guidelines for Working with Copies of Nodes & Groups

Inverting a Node or Group Waveform

Overwriting a Clock Value on a Waveform

Overwriting a Count Value on a Waveform

Overwriting a Group Value on a Waveform

Overwriting a Node Waveform with a Low, High, Undefined, or High Impedance Logic Level

Overwriting a State Name on a Waveform

Selecting a Waveform


Overwrite Count Value dialog box (Waveform Editor)
Overwrite Count Value dialog box

Click Button 1 on any item in this dialog box for information on that item:


Interval: ? To: ?

Shows the length of the selected waveform interval.


Clock Period: ? Multiplied By: ?

Specify the time interval at which the clock will be incremented.

Clock Period	Specifies a time interval. The default is two times the current grid size. You can enter a new time followed immediately (i.e., with no space in between) by a time unit; the default is ns. This option is not available and is dimmed if Snap to Grid (Options menu) is turned on.

Multiplied By	Specifies a number by which to multiply the time interval shown in the Clock Period box. The default is 1. You can enter any whole number between -32000 and 32000.


Starting Value

Specifies the logic level at the beginning of the count sequence. The default is the current value of the selected group.

If a group waveform is selected, the logic level entered in Starting Value is interpreted according to the group’s radix, which is shown in the dialog box.


Ending Value

Shows the last value of the count sequence on the selected waveform interval, which the Waveform Editor dynamically calculates and updates on the basis of the options you enter in the Starting Value, Increment By, and Multiplied By boxes.

This field is always dimmed.


Count Type

Selects the Gray Code or Binary count sequence.


Increment By

Specifies the number used to increment the count. You can enter any whole number between -32000 and 32000.


Count Every: ? Multiplied By: ?

Specify the time interval at which the count will be incremented.

Count Every	Specifies a time interval. The default is the current grid size. You can enter a new time followed immediately (i.e., with no space in between) by a time unit; the default is ns. This option is not available and is dimmed if Snap to Grid (Options menu) is turned on.

Multiplied By	Specifies a number by which to multiply the time interval shown in the Count Every box. The default is 1. You can enter any whole number between -32000 and 32000.


Overwrite Group Value Command (Waveform Editor)
Overwrite Group Value Command (Edit Menu)

Shortcuts

Overwrites a selected whole waveform or waveform interval on a single group waveforms with a different logic level.

Click Button 1 on any item in this dialog box for information on that item:

Overwrite Group Value overwrites the selected interval on all copies of the group and member nodes that exist in the current file, including copies of the group that are included in other groups. This command is not available for individual node or state machine waveforms.

See also:

Changing the Group Radix

Guidelines for Working with Copies of Nodes & Groups

Inverting a Node or Group Waveform

Overwriting a Clock Value on a Waveform

Overwriting a Count Value on a Waveform

Overwriting a Group Value on a Waveform

Overwriting a Node Waveform with a Low, High, Undefined, or High Impedance Logic Level

Overwriting a State Name on a Waveform

Selecting a Waveform


Overwrite Group Value dialog box (Waveform Editor)
Overwrite Group Value dialog box

Click Button 1 on any item in this dialog box for information on that item:


Group Value

Specifies the value for the selected waveform interval. The current logic level is displayed as the default.

Type a new logic level for the group. The value is interpreted according to the group’s radix, which is shown in the dialog box. In a group that represents a state machine in an SCF, you can enter the group value as either a logic level or as an equivalent state name that was defined in the project’s design files.


Overwrite State Name Command (Waveform Editor)
Overwrite State Name Command (Edit Menu)

Shortcuts

Overwrites a selected whole waveform or waveform interval on one or more state machine waveforms with a new state name.

Click Button 1 on any item in this dialog box for information on that item:

Overwrite State Name overwrites the selected interval on all copies of the node that exist in the current file. This command is not available for individual non-state machine node or group waveforms.

See also:

Guidelines for Working with Copies of Nodes & Groups

Overwriting a Group Value on a Waveform

Overwriting a Node Waveform with a Low, High, Undefined, or High Impedance Logic Level

Overwriting a State Name on a Waveform

Selecting a Waveform


Overwrite State Name dialog box (Waveform Editor)
Overwrite State Name dialog box

Click Button 1 on any item in this dialog box for information on that item:


State Name

Specifies the state name for the selected waveform interval. The current state name is displayed as the default.

You can type a new name with up to 32 name characters.


Insert Low (0), High (1), Undefined (X) & High Impedance (Z) Commands
Insert Low (0), High (1), Undefined (X) & High Impedance (Z) Commands (Edit Menu)

Shortcuts

Inserts a new waveform interval with a low (0), high (1), undefined (X), or high-impedance (Z) logic level on one or more individual nodes.

The length of the inserted interval is the same as the time interval selected on the node waveform(s) before the command is entered. These commands insert the new interval on all copies of the node that exist in the current file, including copies that are included in a group.

The new waveform interval is inserted to the left of the selected interval. The length of the inserted interval is the same as the time interval selected on the node waveform before the command is entered.

These commands do not operate on group (bus) waveforms or state machine waveforms.

See also:

Guidelines for Working with Copies of Nodes & Groups

Inserting a Clock Value on a Waveform

Inserting a Group Value on a Waveform

Inserting a Node Waveform with a Low, High, Undefined, or High Impedance Logic Level

Inserting a State Name on a Waveform

Selecting a Waveform


Insert Clock Command (Waveform Editor)
Insert Clock Command (Edit Menu)

Shortcuts

Inserts a new waveform interval with a clock sequence on a single node.

Click Button 1 on any item in this dialog box for information on that item:

The new waveform interval is inserted to the left of the selected interval. The length of the inserted interval is the same as the time interval selected on the node waveform before the command is entered.

Insert Clock inserts the new interval on all copies of the node that exist in the current file, including copies that are included in a group. This command is not available for group waveforms or state machine waveforms.

See also:

Guidelines for Working with Copies of Nodes & Groups

Inserting a Count Value on a Waveform

Inserting a Clock Value on a Waveform

Inserting a Group Value on a Waveform

Inserting a Node Waveform with a Low, High, Undefined, or High Impedance Logic Level

Inserting a State Name on a Waveform

Selecting a Waveform


Insert Count Value Command (Waveform Editor)
Insert Count Value Command (Edit Menu)

Shortcuts

Inserts a new waveform interval with a specified count sequence on a single group waveform.

Click Button 1 on any item in this dialog box for information on that item:

The new waveform interval is inserted to the left of the selected interval or insertion point. The length of the inserted interval is the same as the time interval selected on the node waveform before the command is entered.

Insert Count Value inserts the new interval on all copies of the group and member nodes that exist in the current file, including copies of the group that are included in a group. This command is not available for individual nodes or state machine waveforms.

See also:

Guidelines for Working with Copies of Nodes & Groups

Inserting a Clock Value on a Waveform

Inserting a Count Value on a Waveform

Inserting a Group Value on a Waveform

Inserting a Node Waveform with a Low, High, Undefined, or High Impedance Logic Level

Inserting a State Name on a Waveform

Selecting a Waveform


Insert Count Value dialog box (Waveform Editor)
Insert Count Value dialog box

Click Button 1 on any item in this dialog box for information on that item:


Insert Clock dialog box (Waveform Editor)
Insert Clock dialog box

Click Button 1 on any item in this dialog box for information on that item:


Interval: ? To: ?

Shows the length of the waveform interval that will be inserted. If you selected an interval before choosing Insert Count Value, it defines the length of the inserted interval. If you defined an insertion point by clicking Button 1 instead, the end of the interval is dynamically calculated and updated on the basis of the options you enter in the Starting Value, Increment By, and Multiplied By boxes.


Ending Value

If you defined an insertion point before choosing Insert Count Value, this option specifies the logic level at the end of the count sequence. If you selected an interval, this field shows the last value of the interval to be inserted and cannot be edited.


Insert Group Value Command (Waveform Editor)
Insert Group Value Command (Edit Menu)

Shortcuts

Inserts a new waveform interval with any group value on a single group waveform.

Click Button 1 on any item in this dialog box for information on that item:

An interval with the new group value is inserted to the left of the selected interval. The length of the inserted interval is the same as the time interval selected on the group waveform before the command was entered.

Insert Group Value inserts a new interval on all copies of the group and member nodes that exist in the current file, including copies of the group that are included in other groups. This command is not available for individual node or state machine waveforms.

See also:

Changing the Group Radix

Guidelines for Working with Copies of Nodes & Groups

Inserting a Clock Value on a Waveform

Inserting a Count Value on a Waveform

Inserting a Group Value on a Waveform

Inserting a Node Waveform with a Low, High, Undefined, or High Impedance Logic Level

Inserting a State Name on a Waveform

Selecting a Waveform


Insert Group Value dialog box (Waveform Editor)
Insert Group Value dialog box

Click Button 1 on any item in this dialog box for information on that item:


Group Value

Specifies the value for the waveform interval to be inserted. The current logic level is displayed as the default.

Type a logic level for the group. The value is interpreted according to the group’s radix, which is shown in the dialog box. In a group that represents a state machine in an SCF, you can enter the group value as either a logic level or as an equivalent state name that was defined in the project’s design files.


Insert State Name Command (Waveform Editor)
Insert State Name Command (Edit Menu)

Shortcuts

Inserts a new waveform interval with any state name into a single state machine waveform.

Click Button 1 on any item in this dialog box for information on that item:

A new waveform interval with the new state name is inserted to the left of the selected interval. The length of the inserted interval is the same as the time interval selected on the waveform before the command was entered.

Insert State Name inserts a new interval on all copies of the node that exist in the current file. This command is not available for non-state machine node or group waveforms.

See also:

Guidelines for Working with Copies of Nodes & Groups

Inserting a Group Value on a Waveform

Inserting a State Name on a Waveform

Selecting a Waveform


Insert State Name dialog box (Waveform Editor)
Insert State Name dialog box

Click Button 1 on any item in this dialog box for information on that item:


State Name

Specifies the state name for the waveform interval to be inserted. The current state name is displayed as the default.

You can type a state name with up to 32 name characters.


Align to Grid Command (Waveform Editor)
Align to Grid Command (Edit Menu)

Shortcuts

Makes transitions on one or more selected whole node or group waveforms or waveform intervals align to the current grid. The current grid is defined with Grid Size and is displayed with Show Grid (Options menu).

Align to Grid moves existing logic level transitions so that they occur only on grid lines. For example, if the grid is set to 100 ns, all logic level transitions are moved to lie at multiples of 100 ns. Transitions are aligned forward or backward to the nearest grid line.

Align to Grid moves transitions on existing waveforms. In contrast, Snap to Grid (Options menu) forces transitions to grid lines only when a new transition is added or an existing transition is moved with Snap to Grid turned on.

Align to Grid aligns transitions on all copies of the node or group that exist in the current file, including copies that are included in a group.

See also:

Aligning Transitions to the Grid

Guidelines for Working with Copies of Nodes & Groups

Selecting a Waveform

Showing the Grid

Snapping to the Grid


Repeat Command (Waveform Editor)
Repeat Command (Edit Menu)

Shortcuts

Inserts multiple copies of the Clipboard’s contents (i.e., an interval from one or more node or group waveforms) at the selected insertion point or overwrites a selected interval. The Clipboard contains a selection defined with the last Cut or Copy command (Edit menu).

Click Button 1 on any item in this dialog box for information on that item:

If you click Button 1 to define an insertion point, Repeat inserts the specified number of copies to the left of the insertion point. Or, if you select a waveform interval, Repeat overwrites the interval and replaces it with the specified number of copies.

Repeat inserts the copies only up to the end time of the file. Additional repetitions that would go beyond the end of the file are ignored. If necessary, you can change the end time of the file with End Time (File menu) before choosing Repeat.

Repeat edits all copies of the node or group that exist in the current file, including copies that are included in a group.

See also:

Copying, Cutting & Pasting Waveforms

Guidelines for Working with Copies of Nodes & Groups

Selecting a Waveform

Repeating a Waveform


Repeat dialog box (Waveform Editor)
Repeat dialog box

Click Button 1 on any item in this dialog box for information on that item:


Number of Copies

Specifies the number of times you wish to repeat the cut or copied waveform. Enter a whole number between 1 and 10000.


Grow or Shrink Command (Waveform Editor)
Grow or Shrink Command (Edit Menu)

Shortcuts

Stretches (grows) or compresses (shrinks) a selected interval on one or more node or group waveforms to fit into a different time span.

Click Button 1 on any item in this dialog box for information on that item:

Grow or Shrink edits all copies of the node or group that exist in the current file, including copies that are included in a group.

See also:

Growing or Shrinking a Waveform

Guidelines for Working with Copies of Nodes & Groups

Selecting a Waveform


Grow or Shrink dialog box (Waveform Editor)
Grow or Shrink dialog box

Click Button 1 on any item in this dialog box for information on that item:


Selected Interval: ? To: ?

Shows the current start and end times of the selected waveform interval.


Fit Selection Into: ? To: ?

Specifies the new start and/or end times for the selected waveform interval. The current start and end times are displayed as the default. The selected interval will be stretched or compressed to fit the specified times.

The times you enter must be followed immediately (i.e., with no space in between) by a time unit; the default is ns.


Fit in Window Command (Waveform Editor)
Fit in Window Command (View Menu)

Shortcuts

Changes the display scale to fit the full length of each waveform into the window.

Fit in Window zooms out to fit the entire file in the current window. When you choose Fit in Window or Zoom Out (View menu), some logic level transitions may disappear or become unreadable if the file is too long or complex to display them on screen. All logic level transitions are visible at Maximum Size (View menu).

When you use the keyboard shortcuts for the Fit in Window, Zoom In, Zoom Out, Normal Size and Maximum Size commands, you can zoom as you are selecting or overwriting a waveform.

See also:

Fitting a File into the Window


Time Range Command (Waveform Editor)
Time Range Command (View Menu)

Shortcuts

Scrolls and zooms within the file to display a specified time range in the current window.

Click Button 1 on any item in this dialog box for information on that item:

See also:

Going to a Time Range


Time Range dialog box (Waveform Editor)
Time Range dialog box

Click Button 1 on any item in this dialog box for information on that item:


Show Time Range in Window

From	Specifies the start of the time range you wish to view.

To	Specifies the end of the time range you wish to view.

The times you enter must be followed immediately (i.e., with no space in between) by a time unit; the default is ns.


Zoom In & Zoom Out Commands (Waveform Editor)
Zoom In & Zoom Out Commands (View Menu)

Shortcuts

Increase or decrease the horizontal scale of the waveforms displayed in the current window.

Zoom In makes the waveforms visible in the window become larger (i.e., wider); Zoom Out makes them smaller. The time period that is displayed becomes correspondingly lesser or greater.

When you choose Zoom Out or Fit in Window (View menu), some logic level transitions or grid lines may disappear or become unreadable if the file is too long or complex to display them in the window. All logic level transitions are visible at Maximum Size (View menu).

Zoom In reduces the display scale incrementally, eventually reaching the size provided by Maximum Size; Zoom Out increases the display scale incrementally to reach the size provided by Fit in Window.

When you use the keyboard shortcuts for the Fit in Window, Zoom In, Zoom Out, Normal Size and Maximum Size commands, you can zoom as you are selecting or overwriting a waveform.

See also:

Zooming In & Out


Normal Size Command (Waveform Editor)
Normal Size Command (View Menu)

Shortcuts

Zooms in or out to display waveforms at a resolution determined by the current grid size.

Normal Size displays waveforms so that approximately six to eight grid units fill the window.

As you Zoom Out (View menu), some logic level transitions may disappear or become unreadable if the file is too long or complex to display them in the window. All logic level transitions are visible at Maximum Size (View menu).

When you use the keyboard shortcuts for the Fit in Window, Zoom In, Zoom Out, Normal Size and Maximum Size commands, you can zoom as you are selecting or overwriting a waveform.

See also:

Changing the Grid Size

Zooming In & Out


Maximum Size Command (Waveform Editor)
Maximum Size Command (View Menu)

Shortcuts

Zooms in to display waveforms at maximum resolution.

Maximum Size displays waveforms at the largest size possible, so that logic level transitions are visible at 0.1 ns resolution. All logic level transitions and grid lines are visible at maximum size.

As you Zoom Out (View menu), some logic level transitions or grid lines may disappear or become unreadable if the file is too long or complex to display them in the window.

When you use the keyboard shortcuts for the Fit in Window, Zoom In, Zoom Out, Normal Size and Maximum Size commands, you can zoom as you are selecting or overwriting a waveform.

See also:

Zooming In & Out


Insert Node Command (Waveform Editor)
Insert Node Command (Node Menu)

Shortcuts

Creates a new node or single-range group in a WDF or an SCF, including its default value, I/O type, node type, and secondary inputs.

Insert Node creates one or more new node or group names and waveforms that are inserted at the top of the file, above all existing nodes, on a blank line that you have selected between existing nodes, or just above any selected nodes.

Insert Node functions differently depending on whether the current file is an SCF or a WDF.

In an SCF, you can optionally enter a node or a group from the SNF for the project.

Click Button 1 on any item in this dialog box for information on that item:

In a WDF, you can use Insert Node to specify node characteristics that are required for waveform design entry.

Click Button 1 on any item in this dialog box for information on that item:

After you create a node, the I/O type is shown in the node handle; the node type (in WDFs only) is shown in the Type field.

You can edit the characteristics of one or more nodes or groups by selecting them and choosing Edit Node (Node menu). In addition, you can edit node and group waveforms with Edit menu commands.

See also:

Creating a Node

Hierarchical Node & Symbol Names

Recommended reading:

AN28 (Waveform Design Entry)

AB92 (Simulating Internal Nodes with MAX+PLUS II Software)


Edit Node Command (Waveform Editor)
Edit Node Command (Node Menu)

Shortcuts

Edits one or more existing nodes or groups in a WDF or an SCF. You can modify the default value, I/O type, node type, and secondary inputs of one or more nodes or groups by selecting them and choosing Edit Node.

Edit Node functions differently depending on whether the current file is an SCF or a WDF.

In an SCF, you can change an existing node or group into a different node or group from the SNF for the project.

Click Button 1 on any item in this dialog box for information on that item:

In a WDF, you can use Edit Node to change the node characteristics that are required for design entry.

Click Button 1 on any item in this dialog box for information on that item:

After you edit a node, the I/O type is shown in the node handle; the node type (in WDFs only) is shown in the Type field.

You can enter one or more new nodes by choosing Insert Node (Node menu). In addition, you can edit node and group waveforms with the Edit menu commands.

See also:

Changing the Node Type, I/O Type, Secondary Inputs, or Default Value

Creating a Node

Hierarchical Node & Symbol Names

Renaming a Node or Group

Recommended reading:

AN28 (Waveform Design Entry)

AB92 (Simulating Internal Nodes with MAX+PLUS II Software)


Insert Node dialog box (WDF) (Waveform Editor)
Insert Node dialog box (WDF)

Click Button 1 on any item in this dialog box for information on that item:


Insert Node dialog box (SCF) (Waveform Editor)
Insert Node dialog box (SCF)

Click Button 1 on any item in this dialog box for information on that item:


Edit Node dialog box (SCF) (Waveform Editor)
Edit Node dialog box (SCF)

Click Button 1 on any item in this dialog box for information on that item:


Edit Node dialog box (WDF) (Waveform Editor)
Edit Node dialog box (WDF)

Click Button 1 on any item in this dialog box for information on that item:


Node Name

Specifies the name of the node.

To create a new node, you can type a node name with up to 32 name characters or a hierarchical node name with up to 128 characters in the Node Name box. To create a group, you can type a single-range group name. In an SCF, you can also select a name in the Nodes & Groups from SNF box to copy it to the Node Name box.

If you selected a single node or group before choosing Edit Node, the name of that node or group appears in the Node Name box. If you selected multiple nodes and/or groups, the Node Name box is dimmed.


Node Name

Specifies the name of the node.

To create a new node, you can type a node name with up to 32 name characters or a hierarchical node name with up to 128 characters in the Node Name box. To create a group, you can type a single-range group name. In an SCF, you can also select a name in the Nodes & Groups from SNF box to copy it to the Node Name box.


Default Value

Specifies the initial logic level or state name for the node name shown in the Node Name box.

You can type a logic level or select one from the drop-down list box. For state machine nodes, the initial default state name for a new node is X; for input, output, buried registered, and buried combinatorial nodes, the default logic level is 0. You can also type a state name with up to 32 name characters for a state machine node.

If you selected one or more nodes and/or groups before choosing Edit Node, the value you specify in the Default Value box changes the logic level(s) of the waveform(s) for all of the selected items.


Default Value

Specifies the initial logic level or state name for the node name shown in the Node Name box.

You can type a logic level or select one from the drop-down list box. For state machine nodes, the initial default state name for a new node is X; for input, output, buried registered, and buried combinatorial nodes, the default logic level is 0. You can also type a state name with up to 32 name characters for a state machine node.


I/O Type

Specifies whether the node name shown in the Node Name box represents an Input Pin, Output Pin, or Buried Node.

If you selected one or more nodes and/or groups before choosing Edit Node, the I/O type you specify changes the I/O types for all of the selected items.


I/O Type

Specifies whether the node name shown in the Node Name box represents an Input Pin, Output Pin, or Buried Node.

If you selected one or more nodes and/or groups before choosing Edit Node, the I/O type you specify changes the I/O types for all of the selected items.


Type

Determines which types of nodes and/or groups are displayed in the Nodes & Groups from SNF box. When you choose the List button, all nodes and/or groups matching the selected types are displayed.

You can turn on one or more options or select all types to be listed. If multiple options are turned on, the nodes and/or groups are listed in the following order: input nodes, output nodes, buried combinatorial nodes, buried registered nodes, groups, memory words, and memory bits.

Inputs	Lists all input nodes in the Nodes & Groups from SNF box.

Outputs	Lists all output nodes in the Nodes & Groups from SNF box.

Group	Lists all input, output, and buried groups in the Nodes & Groups from SNF box.

All	Turns on all type options, i.e., lists all types of nodes and groups in the Nodes & Groups from SNF box. Turning this option off deselects all other Type options.

Registered	Lists all buried registered nodes in the Nodes & Groups from SNF box.

Combinatorial	Lists all buried combinatorial nodes in the Nodes & Groups from SNF box.

Memory Bit	Lists all nodes and groups assigned to a specific memory bit address in the Nodes & Groups from SNF box.

Memory Word	Lists all nodes and groups assigned to a specific memory word location in the Nodes & Groups from SNF box.


List

Lists the nodes and/or groups that match the text string in the Node/Group box and the selected Type options in the Nodes & Groups from SNF box.

If Show All Node Name Synonyms is turned on, the Nodes & Groups from SNF box also lists all possible hierarchical node names for each node or group that matches the text string in the Node/Group box. Synonyms are preceded by -> in the list.


Nodes & Groups from SNF

Displays the nodes and/or groups, including probes and groups that represent state machines, that match the text string in the Node/Group box and the selected Type options. Names are shown in hierarchical node name format.

You must choose List to display the node and group names. If Show All Node Name Synonyms is turned on, the Nodes & Groups from SNF box also lists all possible hierarchical node names for each node or group that matches the text string in the Node/Group box. Synonyms are preceded by -> in the list.

Selecting a name in this box automatically copies the node or group name to the Node Name box and selects its I/O type under I/O Type.


Show All Node Name Synonyms

Shows all possible hierarchical node names for each node or group in the Nodes & Groups from SNF box that matches the text string in the Node/Group box. Synonyms are preceded by -> in the list.


Node Type

Specifies the type of logic that drives the node or group.

Pin Input	Specifies that the node or group is driven by an input pin.

Registered	Specifies that the node or group is fed by a register (implemented with a logic cell on the device).

Combinatorial	Specifies that the node or group is fed by combinatorial logic, e.g., an AND gate.

Machine	Specifies that the node is fed by a state machine.


Secondary Inputs

Specifies the name of another node in the current file that will provide the required Clock and optional Reset and Preset inputs to the node.

You can type a node name or select the name of an existing node from the drop-down list box. The Reset option specifies the Clear input for registered nodes.

This option is available for Registered and Machine nodes only.


Enter Nodes from SNF Command (Waveform Editor)
Enter Nodes from SNF Command (Node Menu)

Shortcuts

Adds any combination of nodes (including probes) and groups from the project’s Simulator Netlist File to a Simulator Channel File.

Enter Nodes from SNF can add new nodes or groups to the current SCF with the user-specified nodes and groups (i.e., buses, groups, and state machines) created in the project’s design files. In addition, if they are already present in the SCF, Enter Nodes for SNF can update (i.e., overwrite) existing nodes or groups in the file with nodes from the SNF. This command allows you to create a default SCF containing nodes from the functional, timing, or linked SNF for the project.

Click Button 1 on any item in this dialog box for information on that item:

Enter Nodes from SNF allows you to enter any combination of input, output, and buried nodes; probes; and groups that were created in the project. All input node waveforms have low (0) logic levels; all output and buried node waveforms have undefined (X) logic levels. Nodes are listed in reverse alphabetical order with inputs displayed at the top of the file, followed by all outputs, buried nodes, and groups.

Because Enter Nodes from SNFcan overwrites all information in the current file with new information if the Preserve Existing Nodes option is turned off, MAX+PLUS II warns you before it creates the file. If you do not wish to overwrite the current file, create a new file with New (File menu).

Enter Nodes from SNF is available only if you have compiled the project to create an SNF.

See also:

Combining Multiple Projects for Simulation

Creating a Default Channel File

Creating a Functional Simulator Netlist File

Creating a New File

Creating a Timing Simulator Netlist File

Hierarchical Node & Symbol Names

Saving a File

Recommended reading:

AN28 (Waveform Design Entry)

AB92 (Simulating Internal Nodes with MAX+PLUS II Software)


Enter Nodes from SNF dialog box (Waveform Editor)
Enter Nodes from SNF dialog box

Click Button 1 on any item in this dialog box for information on that item:


Node/Group

Specifies a text string containing wildcard characters or a node, group, or probe name.


Type

Determines which types of nodes and/or groups are displayed in the Available Nodes & Groups list box. When you choose the List button, all nodes and/or groups matching the selected types are displayed.

You can select one or more options or select all types to be listed. If multiple options are selected, the nodes and/or groups are listed in the following order: input nodes, output nodes, buried combinatorial nodes, buried registered nodes, groups, memory words, and memory bits.

Inputs	Lists all input nodes in the Available Nodes & Groups box.

Outputs	Lists all output nodes in the Available Nodes & Groups box.

Group	Lists all input, output, and buried groups in the Available Nodes & Groups box.

All	Turns on all type options, i.e., lists all types of nodes and groups in the Available Nodes & Groups box. Turning this option off deselects all other Type options.

Registered	Lists all buried registered nodes in the Available Nodes & Groups box.

Combinatorial	Lists all buried combinatorial nodes in the Available Nodes & Groups box.

Memory Bit	Lists all nodes and groups assigned to a specific memory bit address in the Available Nodes & Groups box.

Memory Word	Lists all nodes and groups assigned to a specific memory word location in the Available Nodes & Groups box.


List

Lists the nodes and/or groups that match the text string in the Node/Group box and the selected Type options in the Available Nodes & Groups box.

If Show All Node Name Synonyms is turned on, the Available Nodes & Groups box also lists all possible hierarchical node names for each node or group that matches the text string in the Node/Group box. Synonyms are preceded by -> in the list.


Available Nodes & Groups

Displays the nodes and/or groups in the current SNF that match the text string in the Node/Group box and the selected Type options.

You must choose List to display the node and group names. You can choose => to move selected node and /or group names to the Selected Nodes & Groups box.

If Show All Node Name Synonyms is turned on, the Available Nodes & Groups box also lists all possible hierarchical node names for each node or group that matches the text string in the Node/Group box. Synonyms are preceded by -> in the list.


Selected Nodes & Groups

Shows all nodes and groups that will be included added to the current SCF.

You can choose => and <= to move selected node and/or group names between the Available Nodes & Groups box and Selected Nodes & Groups box.


=>

Moves selected nodes and groups from the Available Nodes & Groups box to the Selected Nodes & Groups box. Node and group names in the Selected Nodes & Groups box are added to the current SCF when you choose OK.


<=

Moves selected nodes and groups from the Selected Nodes & Groups box to the Available Nodes & Groups box.


Preserve Existing Nodes

Adds all nodes and groups in the Selected Nodes & Groups box to the current SCF without affecting existing nodes and groups in the file.

If this option is turned on, nodes and groups that already exist in the current SCF are left unchanged, and only new nodes and groups are added. If it is turned off, all nodes and groups in the existing file are overwritten.


Show All Node Name Synonyms

Shows all possible hierarchical node names for each node or group in the Available Nodes & Groups box that matches the text string in the Node/Group box. Synonyms are preceded by -> in the list.


Clear

Moves all nodes out of the Selected Nodes & Groups box and into the Available Nodes & Groups box.


Enter Group Command (Waveform Editor)
Enter Group Command (Node Menu)

Shortcuts

Creates a new group by combining selected nodes and/or groups, or changes the name or radix of an existing group.

Enter Group combines from 2 to 256 selected nodes into a group that is displayed as a single waveform in the file. You can only create a new group if all members have the same I/O type; in WDFs, group members must also have the same node type and secondary inputs. (Nodes with a node type of machine cannot be grouped.) You can also select a group to be included in another group, but each member of the selected group is counted towards the 256-node maximum.

Click Button 1 on any item in this dialog box for information on that item:

When you select nodes to be grouped, the selected node nearest the top of the file window is the MSB of the group value, the node nearest the bottom is the LSB.

After you create a group, the node/group handle changes to represent a group. You can edit a group name or radix by selecting it and choosing Enter Group again. When you delete a group, its "member" nodes are also deleted.

Enter Group is available only if two or more nodes are selected.

See also:

Changing the Group Radix

Creating a Group

Renaming a Node or Group

Selecting a Node or Group

Sorting Node & Group Names

Ungrouping a Group

Recommended reading:

AN28 (Waveform Design Entry)


Enter Group dialog box (Waveform Editor)
Enter Group dialog box

Click Button 1 on any item in this dialog box for information on that item:


Group Name

Specifies the name of the group.

To create a new group, you can type a group name with up to 32 name characters or a hierarchical group name with up to 128 characters. You can also use a single-range group name if it matches the names and numerical range of the original nodes.

If you selected a single group before choosing Enter Group, the name of that group appears in the Group Name box. If you selected multiple groups with the same I/O type, the Group Name box is blank. In this case, you can enter a group name to create a new group, or edit the Radix for the selected groups without changing their names.

If you select multiple groups with different I/O types, this box is dimmed.


Display Gray Code Count As Binary Count

Stores the group logic level as Gray code and displays the equivalent binary count in the Waveform Editor window.


Radix

Specifies the radix used to interpret and display the logic level of the group as BIN (binary), DEC (decimal), HEX (hexadecimal), or OCT (octal).


Ungroup Command (Waveform Editor)
Ungroup Command (Node Menu)

Shortcuts

Dissolves one or more selected groups and returns the original "member" nodes of each group to the window.

Ungroup deletes the names of one or more selected groups from the file without deleting the original "member" nodes. The original members of the group reappear as selected nodes.

When a group is dissolved, the selected node at the top is the MSB of the group value, the node at the bottom is the LSB.

Ungroup is available only if at least one group is selected.

See also:

Creating a Group

Selecting a Node or Group

Ungrouping a Group


Sort Names Command (Waveform Editor)
Sort Names Command (Node Menu)

Sorts selected nodes and groups by name in ascending or descending alphanumerical order.

Sort Names rearranges the order of nodes and groups in the file into a "smart" alphanumerical order, in which 0 precedes 1. Sort Names works on all nodes and groups that were selected (i.e., the nodes and groups "selected" as a whole by clicking Button 1 on the node/group handle, Name field, or Type field) before Sort Names was entered. If none of the nodes or groups in the file are selected, Sort Names operates as if all nodes and groups are selected.

Click Button 1 on any item in this dialog box for information on that item:

See also:

Moving Nodes & Groups

Sorting Node & Group Names


Sort Names dialog box (Waveform Editor)
Sort Names dialog box

Click Button 1 on any item in this dialog box for information on that item:


Order

Specifies an Ascending or Descending sorting order.


Enter Separator Command (Waveform Editor)
Enter Separator Command (Node Menu)

Creates a waveform separator at the selected insertion point that indicates that the waveforms (i.e., logic levels and/or state names) before the separator are unrelated to those after it.

Click Button 1 on any item in this dialog box for information on that item:

The waveform separator appears as a thin vertical line. It marks the beginning of a new, independent sequence of waveforms, which essentially affects only nodes with a node type of registered and machine. You can create as many waveform separators as you wish.

Enter Separator is available only for a WDF.

See also:

Creating & Deleting a Waveform Separator

Recommended reading:

AN28 (Waveform Design Entry)


Enter Separator dialog box (Waveform Editor)
Enter Separator dialog box

Click Button 1 on any item in this dialog box for information on that item:


Separator Time

Specifies the time for the separator. The time you enter must be followed immediately (i.e., with no space in between) by a time unit; the default time unit is ns.


Go To Command (Waveform Editor)
Go To Command (Utilities Menu)

Shortcuts

Moves the Reference cursor to the specified time within the file.

Click Button 1 on any item in this dialog box for information on that item:

The Waveform Editor places the cursor at the specified time and scrolls to display it in the window.

See also:

Going to a Specific Time


Go To dialog box (Waveform Editor)
Go To dialog box

Click Button 1 on any item in this dialog box for information on that item:


Time

Specifies the time. The time you enter must be followed immediately (i.e., with no space in between) by a time unit; the default time unit is ns.


Select Command (Waveform Editor)
Select Command (Utilities Menu)

Selects a specified time interval on the waveform of one or more nodes and/or groups.

Click Button 1 on any item in this dialog box for information on that item:

Select works on all nodes and groups that were selected (i.e., the nodes and groups "selected" as a whole by clicking Button 1 on the node/group handle, Name field, or Type field) before Select was entered. If none of the nodes or groups in the file are selected, Select operates as if all nodes and groups are selected.

See also:

Going to a Time Range

Selecting a Node or Group

Selecting a Waveform


Select dialog box (Waveform Editor)
Select dialog box

Click Button 1 on any item in this dialog box for information on that item:


Time Range

From	Specifies the start of the time range you wish to select.

To	Specifies the end of the time range you wish to select.

The times you enter must be followed immediately (i.e., with no space in between) by a time unit; the default is ns.

When Snap to Grid (Options menu) is turned on, the time at both ends of the selected range automatically snaps to the nearest gridline.


Find Text Command (Waveform Editor)
Find Text Command (Utilities Menu)

Shortcuts

Searches the current file for the first occurrence of the specified text.

Click Button 1 on any item in this dialog box for information on that item:

After the first occurrence of the search text is found, you can choose Find Next or Find Previous (Utilities menu) to continue the search.

See also:

Finding Text

Finding & Replacing Text

Search & Replace Command

Selecting a Node or Group


Find Text dialog box (Waveform Editor)
Find Text dialog box

Click Button 1 on any item in this dialog box for information on that item:


Types of Text to Find

Node and Group Names	Finds the text that occurs in node and group names.

Node Types	Finds the text that occurs in the node type displayed in the Type field.

State Names	Finds the text that occurs in state machine waveforms.

All	Finds all occurrences of the specified search text.


Find Next Transition Command (Waveform Editor)
Find Next Transition Command (Utilities Menu)

Shortcuts

Moves the Reference cursor to the next logic level transition on any of the currently selected nodes or groups.

Find Next Transition moves the Reference cursor to the right until it reaches the next logic level transition on all nodes that are currently selected. If none of the nodes or groups in the file are selected, Find Next Transition operates as if all nodes and groups are selected, and finds the next transition on any node or group in the file.

See also:

Finding a Transition

Selecting a Node or Group


Find Previous Transition Command (Waveform Editor)
Find Previous Transition Command (Utilities Menu)

Shortcuts

Moves the Reference cursor to the previous logic level transition on any of the currently selected nodes or groups.

Find Previous Transition moves the Reference cursor to the left until it reaches the previous logic level transition on all nodes that are currently selected. If none of the nodes or groups in the file are selected, Find Previous Transition operates as if all nodes and groups are selected, and finds the previous transition on any node or group in the file.

See also:

Finding a Transition


Find Next Command (Waveform Editor)
Find Next Command (Utilities Menu)

Shortcuts

Finds the next occurrence of the search text specified with Find Text or Search & Replace, (Utilities menu), or the next logic level transition.

If the previous command was Find Next Transition (Utilities menu), Find Next repeats the command. If the previous command was Find Text or Search & Replace, Find Next searches in the direction specified in the command. If you specified Down, it searches down the file; if you specified Up, it searches up.

See also:

Finding a Transition

Finding Text

Finding & Replacing Text


Find Previous Command (Waveform Editor)
Find Previous Command (Utilities Menu)

Shortcuts

Finds the previous occurrence of the search text specified with Find Text or Search & Replace (Utilities menu), or the previous logic level transition.

If the previous command was Find Previous Transition (Utilities menu), Find Previous repeats the command. If the previous command was Find Text or Search & Replace, Find Previous searches opposite to the direction specified in Find Text or Search & Replace. If you specified Down, it searches up the file; if you specified Up, it searches down.

See also:

Finding a Transition

Finding Text

Finding & Replacing Text


Search & Replace Command (Waveform Editor)
Search & Replace Command (Utilities Menu)

Shortcuts

Searches from the insertion point for specified text in the current file and replaces it.

Click Button 1 on any item in this dialog box for information on that item:

If the Waveform Editor finds the search text when the Confirm Each Change option is turned on, a dialog box appears. Click Button 1 on any item in this dialog box for information on that item:

After you finish using the Search & Replace command, you can choose Find Text, Find Next, or Find Previous (Utilities menu) to locate the search text again.

See also:

Finding Text

Finding & Replacing Text


Search & Replace dialog box (Waveform Editor)
Search & Replace dialog box

Click Button 1 on any item in this dialog box for information on that item:


Types of Text to Find

Node and Group Names	Finds the text that occurs in node and group names.

State Names	Finds the text that occurs in state machine waveforms.

All	Finds all occurrences of the specified search text.


Snap to Grid Command (Waveform Editor)
Snap to Grid Command (Options Menu)

Shortcuts

Enables or disables the "magnetic" grid that pulls all new or moved logic level transitions to the nearest grid line.

Snap to Grid is always on in a WDF; it is optional only in an SCF. When Snap to Grid is on, all transitions that are moved (dragged) or placed in the file snap to the nearest grid line. Transitions on existing waveforms are not affected. Snap to Grid works regardless of whether Show Grid (Options menu) is turned on or off.

Snap to Grid affects new or moved transitions, but not existing transitions. In contrast, Align to Grid (Edit menu) aligns transitions on existing waveforms to the grid.

See also:

Aligning Transitions to the Grid

Changing the Grid Size

Showing the Grid

Snapping to the Grid


Show Grid Command (Waveform Editor)
Show Grid Command (Options Menu)

Shortcuts

Displays or hides the drawing grid.

Show Grid turns the grid lines on and off. The size (spacing) of the grid lines is set with Grid Size (Options menu).

Show Grid has no effect on the Snap to Grid function (Options menu).

See also:

Changing the Grid Size

Showing the Grid


Grid Size Command (Waveform Editor)
Grid Size Command (Options Menu)

Determines the size (spacing) of the drawing grid.

Click Button 1 on any item in this dialog box for information on that item:

The grid is displayed with Show Grid (Options menu).

The grid size in a WDF is arbitrary. Select any grid size that is convenient for drawing your waveform.

See also:

Changing the Grid Size

Showing the Grid


Grid Size dialog box (Waveform Editor)
Grid Size dialog box

Click Button 1 on any item in this dialog box for information on that item:


Grid Size

Specifies the time interval between grid lines. Enter a time value, followed immediately (i.e., with no space in between) by a time unit. The default unit is ns.


---------------------BEGINNING OF NON-TRANSLATED TEXT---------------------------------

The three WED window bitmaps contain call-outs for the following items:

wed_bt1.bmp:	Cursor Movement Buttons;Reference Cursor; Waveform Separator; Time Field, Reference Field, Interval Field, Name Field, Type Field, Value Field; Node/Group Handles; Field Resizing Handles

wed_bt3.bmp:	Start Field, End Field; Waveform Selection Buttons; Time Scale

wed_bt4.bmp:	Group Waveform; High, Low, High-Impedance, Undefined Waveforms; State Machine Waveform; Input, Output, Buried Nodes and Groups; Grid

------------------------------END OF NON-TRANSLATED TEXT------------------------------------


Waveform Editor Window


Waveform Editor Window


Waveform Editor Window


Waveform Editor Window


---------------------BEGINNING OF NON-TRANSLATED TEXT---------------------------------

Messages from wfpmsgs.msg that are documented elsewhere (not in this file):

EWFP_DUPLICATE_NODE_NAME	COMESS.MAC

EWFP_DUPLICATE_STATE_NAME	COMESS.MAC

FWFP_OUT_OF_MEMORY	GLMESS.MAC

FWFP_TOO_MANY_NODES	GLMESS.MAC

FWFP_TOO_MANY_STATES	GLMESS.MAC

FWFP_CANT_READ_SCF	GLMESS.MAC

------------------------------END OF NON-TRANSLATED TEXT------------------------------------


Cant create file <filename>

CAUSE:	Your disk is full, you have a disk error, or the existing HIF, CNF, or Symbol File on your disk is read-only.

ACTION:	If your disk is nearly full, delete files to make space available. Run the DOS CHKDSK/F program to check your disk for errors. Delete the existing HIF or CNF. You can delete the existing Symbol File unless is it a symbol provided with MAX+PLUS II, which you should never delete.

See also:

MAX+PLUS II Messages

Message Format


Node <name> has same set of inputs but different values at <time> and <time>

CAUSE:	The same combination of input nodes exists at the two specified times in the file, but the specified registered or combinatorial output node has a different value at the two times. (The values are compared at the next Clock transition after each of the specified times.) This condition is illegal because the same set of logic levels cannot create two different outputs. This problem may arise if the waveform transitions are not properly aligned to each another.

ACTION:	Use the Message Processor to locate errors. Edit one or more of the input waveforms so that they are different at the two different times, or make the outputs identical. If necessary, you can create a buried machine node that gives the vectors different state names. Ensure that waveform transitions are properly aligned with Align to Grid.

See also:

Aligning Transitions to the Grid

Creating a Waveform Design File

Locating the Source of a Message

MAX+PLUS II Messages

Message Format

Overwriting a Node Waveform with a Low, High, Undefined, or High Impedance Logic Level


Node <name> has no Clock input

CAUSE:	The specified machine or registered node does not have a Clock input, which is required.

ACTION:	Use the Message Processor to locate errors. Assign a Clock input to the node with the Enter Node dialog box.

See also:

Changing the Node Type, I/O Type, Secondary Inputs, or Default Value

Creating a Waveform Design File

Locating the Source of a Message

MAX+PLUS II Messages

Message Format


Node <name> is not clocked at <time>
Node <name> is not clocked by the Clock input <node name> at <time>

CAUSE:	A registered node has changed its value at a time when its Clock input has not made a low-to-high transition.

ACTION:	Use the Message Processor to locate errors. Edit the waveform so that each registered node only changes its value on the rising edge of its Clock input. It may be helpful to use Align to Grid to ensure that all waveform edges are properly aligned to each other.

See also:

Aligning Transitions to the Grid

Changing the Node Type, I/O Type, Secondary Inputs, or Default Value

Creating a Waveform Design File

Locating the Source of a Message

MAX+PLUS II Messages

Message Format

Overwriting a Node Waveform with a Low, High, Undefined, or High Impedance Logic Level


Node <name> is not preset by the Preset input <node name> at <time>

CAUSE:	The waveform of the specified registered node is not set to high when the node that is defined as its Preset input is active.

ACTION:	Use the Message Processor to locate errors. Edit the waveform so that it is high whenever its Preset input is active.

See also:

Changing the Node Type, I/O Type, Secondary Inputs, or Default Value

Creating a Waveform Design File

Locating the Source of a Message

MAX+PLUS II Messages

Message Format

Overwriting a Node Waveform with a Low, High, Undefined, or High Impedance Logic Level


Node <name> is not reset by the Reset input <node name> at <time>

CAUSE:	The waveform of the specified registered node is set to high when the node that is defined as its Reset input is active.

ACTION:	Use the Message Processor to locate errors. Edit the the waveform so that it is low whenever its Reset input is active.

See also:

Changing the Node Type, I/O Type, Secondary Inputs, or Default Value

Creating a Waveform Design File

Locating the Source of a Message

MAX+PLUS II Messages

Message Format

Overwriting a Node Waveform with a Low, High, Undefined, or High Impedance Logic Level


Non-existent node <name> specified as secondary input of node <name>

CAUSE:	The specified name was entered as a secondary input (i.e., Clock, Reset, or Preset) of another node, but the name does not correspond to any node name in the current WDF.

ACTION:	Always enter the name of an existing node when you specify the secondary input. You can either change the name of the secondary input or create a new node with the existing name. You can also omit a secondary input if no connection is required.

See also:

Changing the Node Type, I/O Type, Secondary Inputs, or Default Value

Creating a Node

Creating a Waveform Design File

MAX+PLUS II Messages

Message Format


Output(s) change at <time>, but no input transitions cause the change

CAUSE:	One or more output or buried nodes have changed value at the specified time, but no input node has changed its value. Since all output node transitions have a 0-ns propagation delay, and results from an input node transition. It is illegal for an output or buried node to change without a change on an input node.

ACTION:	Use the Message Processor to locate errors. Edit the waveforms so that each output node transition is aligned to at least one input node transition.

See also:

Aligning Transitions to the Grid

Creating a Waveform Design File

Locating the Source of a Message

MAX+PLUS II Messages

Message Format

Overwriting a Node Waveform with a Low, High, Undefined, or High Impedance Logic Level


WDF <filename> is being used by another application and is locked

CAUSE:	Another application is is working with the specified WDF while the Compiler is trying to use it.

ACTION:	Stop the current compilation or wait for it to finish to free up the file.

See also:

MAX+PLUS II Messages

Message Format

Starting & Stopping the Compiler


VHDL Help Contents

The Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) is a high-level text entry language that is integrated into MAX+PLUS II. VHDL is described in the following sections:

Introduction	Introduces basic VHDL features.

How to Use MAX+PLUS II VHDL	Provides MAX+PLUS II-specific information for designing with VHDL. Altera recommends that you read the topics in this section sequentially.

MAX+PLUS II VHDL Support	Describes the VHDL constructs supported by the MAX+PLUS II Compiler.

Syntax	Describes the BNF syntax for all VHDL statements and sections.

Style Guide	Provides guidelines for formatting VHDL Design Files and TDFs to improve readability and avoid errors.

Golden Rules	Summarizes essential rules and guidelines that will help you use VHDL effectively.

See also:

Compiling VHDL Design Files

Old-Style Macrofunctions

Megafunctions/LPM

Primitives

VHDL Interface Information


VHDL Introduction
Introduction

The Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) is a high-level, modular language that is completely integrated into the MAX+PLUS II system. You can use the MAX+PLUS II Text Editor or another text editor to create VHDL Design Files (with the .vhd extension). You can then compile and simulate the VHDL Design Files and use them to program Altera devices.

VHDL Design Files can contain any combination of MAX+PLUS II-supported constructs. They can also contain Altera-provided logic functions, including primitives, megafunctions, and macrofunctions, and user-defined logic functions.

How Does MAX+PLUS II VHDL Support Work?

VHDL constructs are powerful and versatile. You can create entire hierarchical projects with VHDL, or mix VHDL Design Files with other types of design files in a hierarchical project.

Although you can use any ASCII text editor to create VHDL designs, the MAX+PLUS II Text Editor allows you to take advantage of features available only in MAX+PLUS II while you enter, compile, and debug a VHDL design, including VHDL templates, syntax coloring, error location, and resource and device assignments.

VHDL designs are easily incorporated into a design hierarchy. In the Text Editor, you can automatically create a symbol that represents a VHDL Design File and incorporate it into a GDF. Similarly, you can incorporate custom functions, as well as Altera-provided macrofunctions, megafunctions, and primitives, into any VHDL Design File.

The Compiler allows you to check VHDL syntax quickly or perform a full compilation to debug and process your project. You can use the MAX+PLUS II Message Processor to locate errors automatically and highlight them in the Text Editor window. After the project has compiled successfully, you can perform optional simulation and timing analysis with MAX+PLUS II, and then program one or more Altera devices. You can also create VHDL Output Files or Standard Delay Format (SDF) Output Files  for use with third-party simulation tools.

You can specify resource and device assignments for a VHDL Design File to guide logic synthesis and fitting for your project. You can choose to have the Compiler automatically fit your project into the best combination of devices from a target device family and assign the resources within them. You can also enter specific assignments with the Assign menu commands, the Floorplan Editor, or in the Assignment & Configuration File (.acf) for a project.

Parameterized functions are not supported in MAX_PLUS II VHDL.

MAX+PLUS II supports a subset of the constructs defined by the IEEE Std 1076-1987, i.e., it supports only those constructs that are relevant to logic synthesis. For details about the level of MAX+PLUS II support for each construct, see MAX+PLUS II VHDL Support.

Where to Start

Altera offers a variety of information to help you create designs with VHDL.

On-Line Help

On-line help supplies complete reference and how-to information on using VHDL to create designs.

VHDL Help Contents provides access to all on-line VHDL Help.

VHDL Golden Rules summarizes essential rules and guidelines for designing with VHDL.

Recommended Reading

For more detailed information on VHDL, refer to the following documents, which are provided with your MAX+PLUS II VHDL support:

Perry’s VHDL

IEEE Standard VHDL Language Reference Manual

See also:

Compiling VHDL Design Files

How to Use MAX+PLUS II Help

Inserting a VHDL Template

Text Editor Introduction

Using Syntax Coloring in Text Files


VHDL Golden Rules
Golden Rules

The following golden rules will help you use VHDL effectively:

Use the Text Editor's Syntax Coloring command (Options menu) to help you identify typographical errors and different sections of VHDL code.

Follow the formatting and naming guidelines described in the AHDL & VHDL Style Guide to improve readability and avoid errors.

Although VHDL is not case-sensitive, Altera recommends that you follow the capitalization rules in the AHDL & VHDL Style Guide to improve readability.

Do not use nested If Statements when a Case Statement can be used instead.

Do not use Conditional Signal Assignment when a Selected Signal Assignment can be used instead.

If you use a Wait Statement in a process, it must be listed at the beginning of the Process Statement.

When you use the MAX+PLUS II Text Editor to create a VHDL Design File, each line can be up to 255 characters long. However, the ideal line length is the number of characters your screen can accommodate. You can press Enter to end a line.

You can start new lines wherever white space (i.e., blank lines, tabs, and spaces) is allowed, without any effect on meaning. White space is allowed between major VHDL constructs.

Keywords, names, and numbers must be separated by the appropriate symbols or operators, and one or more spaces.

Comments must begin with two dashes (--) and continue to the End-of-Line.

When connecting a primitive to another primitive, you must use only "legal" interconnections; not all primitives may connect to all other primitives. For a list of legal interconnections for primitives, see Primitive/Port Interconnections.

Do not create your own cross-coupled structures; use only the EXPDFF, EXPLATCH, INPLTCH, NANDLTCH, and NORLTCH macrofunctions provided with MAX+PLUS II. (These macrofunctions are not optimized for FLEX 8000 and FLEX 10K architectures.) Avoid tying multiple instances of EXPDFF, EXPLATCH, INPLTCH, NANDLTCH, and NORLTCH macrofunctions together. Multiple instances of these macrofunctions should always be separated by LCELL primitives.

General Design Entry Golden Rules

Be sure to refer to Guidelines for Working with Assignments for essential information on using all types of resource, probe, and device assignments.

If you wish to load a register on a specific rising edge of the global Clock, Altera recommends that you use the Clock Enable input of one of the DFFE, TFFE, JKFFE, or SRFFE Enable-type flipflops to control when the register is loaded.

When you start a new design file, specify the target device family with Device (Assign menu) right away, so that you can take advantage of family-specific macrofunctions. If you do not specify a device family, the family for the current project is assumed.

Use the Design Doctor to check the reliability of your project logic during compilation. Follow Project Reliability Guidelines to create reliable projects.

General MAX+PLUS II Golden Rules

When you start work on a new design file, name it as the current project with Project Set Project to Current File or Project Name (File menu) right away so that you can compile it easily. You can always change the project name later.

Use the built-in hierarchy traversal features in MAX+PLUS II to move between design files for the current hierarchy tree. To open a lower-level file in a hierarchy, open the top-level file and then use the Hierarchy Display window or Hierarchy Down (File menu) to open the lower-level files. If you choose Open or Retrieve (File menu) to open a lower-level file, that file is considered to be the top of a different hierarchy tree, and resource, device, and probe assignments that you enter are saved only for that hierarchy, not for the project.

When you create an ancillary file for a project, the icon for the file will appear in the Hierarchy Display if you use the same filename as the project.

Don’t edit any MAX+PLUS II system files, including HIFs, Token Files (.tok), maxplus2.idx files, or the maxplus2.ini file.

Use the Save As (File menu) command if you wish to rename a design file or an ancillary file. Do not rename design files from outside of the MAX+PLUS II system (e.g., from DOS or with the Windows File Manager).

When you have completed a project, use Project Archive (File menu) to save a complete backup copy of all project files that will not be affected by future edits or deletions.


VHDL Design File (.vhd) Description
VHDL Design File (.vhd)

An ASCII text file (with the extension .vhd) created with the MAX+PLUS II Text Editor or another standard text editor. The VHDL Design File contains design logic that is defined with VHDL.

A VHDL Design File can contain any combination of the constructs supported by MAX+PLUS II. For more information, see MAX+PLUS II VHDL Support.

You can easily incorporate primitives, and both Altera-provided and user-defined macrofunctions and megafunctions into a VHDL Design File. You can use a logic function by creating a component in the file or in a referenced package, then use a Component Instantiation Statement to insert an instance of the logic function. You can also use this method to incorporate VHDL logic in another VHDL Design File. Some Altera-provided primitives can also be expressed as logical operators in Boolean expressions.

A single VHDL Design File can be used to define all logic in a project, or can be incorporated at any hierarchy level in a hierarchical project. In the Text Editor, you can create a Symbol File or AHDL Include File (.inc) that represents a VHDL Design File with Create Default Symbol and Create Default Include File commands (File menu). This symbol and the logic it represents can be incorporated into a GDF or TDF, respectively.

You can create a super-project VHDL Design File containing instances of multiple individual sub-projects. In this type of VHDL Design File, the instances represent the SNFs for each individual sub-project, not the actual design file. You can compile the super-project to create a linked SNF that combines the timing and functional SNF information for each sub-project. This SNF allows you to perform a board-level-type simulation. For more information on super-project VHDL Design Files, refer to the guidelines in File Structure Requirements for Multi-Project Simulation.

The MAX+PLUS II Compiler can also create VHDL Output Files and VHDL Memory Model Files for use with third-party simulation tools.

The file icon for each VHDL Design File that is part of the current hierarchy tree appears in the Hierarchy Display window.

See also:

Compiling VHDL Design Files

Creating the Default Symbol for a File

Creating VHDL Output Files

VHDL Help Contents

Recommended Reading:

IEEE Standard VHDL Language Reference Manual

Perry’s VHDL


MAX+PLUS II VHDL Support

MAX+PLUS II support for VHDL is described for the following categories of VHDL constructs. These sections match those in the IEEE Standard VHDL Language Reference Manual.

Design Entities & Configurations

Subprograms & Packages

Types

Declarations

Specifications

Names

Expressions

Sequential Statements

Concurrent Statements

Scope & Visibility

Design Units & Their Analysis

Elaboration & Execution

Lexical Elements

Predefined Language Environment


Design Entities & Configurations (VHDL)
Design Entities & Configurations

MAX+PLUS II support for Design Entities and configurations is described below. Section numbers match those in the IEEE Standard VHDL Language Reference Manual.

Support for each VHDL construct is described with one of the following terms:

Section	VHDL Construct	MAX+PLUS II Support (1)

1.1	Entity Declarations	Supported.

1.1.1	Entity Header	Supported.

1.1.1.1	Generics	Not supported.

1.1.1.2	Ports	Supported.

1.1.2	Entity Declarative Part	Supported.

1.1.3	Entity Statement Part	Supported. These statements are passive.

1.2	Architecture Bodies	Supported.

1.2.1	Architecture Declarative Part	Supported.

1.2.2	Architecture Statement Part	Supported.

1.3	Configuration Declarations	Supported.

1.3.1	Block Configuration	Supported.

1.3.2	Component Configuration	Supported.


Note:  VHDL Support
Note (1)

Support for each VHDL construct is described with one of the following terms:

Term:	Description:

Supported	MAX+PLUS II offers full support for the construct.

Not supported	The construct cannot be used in a VHDL Design File. If used, the construct causes an error when MAX+PLUS II compiles the file.

Ignored	The construct can be included in a VHDL Design File, but it is ignored by the MAX+PLUS II Compiler.


Subprograms & Packages (VHDL)
Subprograms & Packages

MAX+PLUS II support for subprograms and packages is described below. Section numbers match those in the IEEE Standard VHDL Language Reference Manual.

Section	VHDL Construct	MAX+PLUS II Support (1)

2.1	Subprogram Declarations	Supported as defined in subsections 2.1.1 through 2.1.1.2.

2.1.1	Formal Parameters	Supported.

2.1.1.1	Constant & Variable Parameters	Supported.

2.1.1.2	Signal Parameters	Not supported.

2.2	Subprogram Bodies	Supported.

2.3	Subprogram Overloading	Supported.

2.3.1	Operator Overloading	Supported.

2.4	Resolution Functions	Not supported.

2.5	Package Declarations	Supported. Global signals cannot be declared.

2.6	Package Bodies	Supported.

2.7	Conformance Rules	Supported.


Types (VHDL)
Types

MAX+PLUS II support for types is described below. Section numbers match those in the IEEE Standard VHDL Language Reference Manual.

Section	VHDL Construct	MAX+PLUS II Support (1)

3.1	Scalar Types	Supported as defined in subsections 3.1.1 through 3.1.2.1.

3.1.1	Enumeration Types	Supported. Types with character literals that are exclusively

from the set '0', '1', 'D', 'H', 'L', 'U', 'W', 'X', 'Z',

'd', 'h', 'l', 'u', 'w', 'x', 'z', and '-' are treated as

logic types. Variables and signals are represented in logic

types with single bits and in other enumeration types

with arrays of bits.

3.1.1.1	Predefined Enumeration Types	Supported.

3.1.2	Integer Types	Supported.

3.1.2.1	Predefined Integer Types	Supported.

3.1.3	Physical Types	Not supported. The predefined Physical Type TIME is not

supported; user-defined Physical Types have no meaning in

VHDL synthesis. You can make timing assignments with the Timing Requirements

and Global Project Timing Requirements commands in MAX+PLUS II.

3.1.3.1	Predefined Physical Types	Not supported. See above.

3.1.4	Floating Point Types	Not supported. Synthesized logic that supports floating-point

operations is too inefficient for programmable logic.

3.1.4.1	Predefined Floating Point Types	Not supported. See above.

3.2	Composite Types	Supported.

3.2.1	Array Types	Supported.

3.2.1.1	Index Constraints & Discrete Ranges	Supported.

3.2.1.2	Predefined Array Types	Supported.

3.2.2	Record Types	Supported.

3.3	Access Types	Not supported. Synthesized logic that supports dynamic

allocation of objects is too inefficient for programmable logic.

3.3.1	Incomplete Type Declarations	Not supported. See above.

3.3.2	Allocation & Deallocation of Objects	Not supported. See above.

3.4	File Types	Not supported. File I/O cannot be synthesized.

3.4.1	File Operations	Not supported. See above.


Declarations (VHDL)
Declarations

MAX+PLUS II support for declarations is described below. Section numbers match those in the IEEE Standard VHDL Language Reference Manual.

Section	VHDL Construct	MAX+PLUS II Support (1)

4.1	Type Declarations	Supported.

4.2	Subtype Declarations	Supported.

4.3	Objects	Supported as defined in the subsections 4.3.1 through 4.3.4.

4.3.1	Object Declarations	Supported.

4.3.1.1	Constant Declarations	Supported. The Constant Declaration must be of type integer, enumeration,

BIT_VECTOR, STD_LOGIC_VECTOR, or STRING.

4.3.1.2	Signal Declarations	Supported. Array elements must be 1-dimensional arrays or single bits. Default expressions

of signals are ignored.

4.3.1.3	Variable Declarations	Supported. Array elements must be 1-dimensional arrays or single bits. Initial values of variables

are ignored.

4.3.2	File Declarations	Not supported. File I/O cannot be synthesized.

4.3.3	Interface Declarations	Supported.

4.3.3.1	Interface Lists	Supported except for ports with mode LINKAGE.

4.3.3.2	Association Lists	Supported. Type Conversion functions may not be used.

4.3.4	Alias Declarations	Supported.

4.4	Attribute Declarations	Supported.

4.5	Component Declarations	Supported except for Generic Clauses.


Specifications (VHDL)
Specifications

MAX+PLUS II support for specifications is described below. Section numbers match those in the IEEE Standard VHDL Language Reference Manual.

Section	VHDL Construct	MAX+PLUS II Support (1)

5.1	Attribute Specification	Supported.

5.2	Configuration Specification	Supported as defined in the subsections 5.2.1 through 5.2.2.

5.2.1	Binding Indication	Supported.

5.2.1.1	Entity Aspect	Supported, but an Entity Aspect cannot be OPEN and must

have an architecture name.

5.2.1.2	Generic Map & Port Map Aspects	Port Map Aspects are supported. Generic Map Aspects are

not supported.

5.2.2	Default Binding Indication	Supported.

5.3	Disconnection Specification	Ignored. You can make timing assignments with the Timing Requirements

command in the MAX+PLUS II Text Editor.


Names (VHDL)
Names

MAX+PLUS II support for names is described below. Section numbers match those in the IEEE Standard VHDL Language Reference Manual.

Section	VHDL Construct	MAX+PLUS II Support (1)

6.1	Names	Supported.

6.2	Simple Names	Supported.

6.3	Selected Names	Supported.

6.4	Indexed Names	Supported. The prefix of an Indexed Name

must be another Indexed Name or a Simple Name.

6.5	Slice Names	Supported. The prefix of a Slice Name must be a

Simple Name. The Slice Name must be locally static,

and the direction and discrete range of a target Slice

Name must be known.

6.6	Attribute Names	Supported.


Expressions (VHDL)
Expressions

MAX+PLUS II support for expressions is described below. Section numbers match those in the IEEE Standard VHDL Language Reference Manual.

Section	VHDL Construct	MAX+PLUS II Support (1)

7.1	Expressions	Supported.

7.2	Operators	Supported as defined in the subsections 7.2.1 through 7.2.5.

7.2.1	Logical Operators	Supported.

7.2.2	Relational Operators	Supported.

7.2.3	Adding Operators	Supported.

7.2.4	Multiplying Operators	The multiplication (*) and division (/) operators are supported, but the

right-hand operand must be a power of two. The mod and rem

operators are not supported.

7.2.5	Miscellaneous Operators	Not supported. A future enhancement will support exponentiation (**)

when the operand on its left is a power of two.

7.3	Operands	Supported as defined in the subsections 7.3.1 through 7.3.6.

7.3.1	Literals	Supported.

7.3.2	Aggregates	Not supported except for one- and two-dimensional arrays of

scalar elements.

7.3.2.1	Record Aggregates	Not supported. This feature will be supported in a future release

of MAX+PLUS II.

7.3.2.2	Array Aggregates	Supported for one- and two-dimensional arrays of scalar elements only.

7.3.3	Function Calls	Supported for Process Statements. Function Calls will be supported

for Concurrent Signal Assignments in a future release of MAX+PLUS II.

7.3.4	Qualified Expressions	Supported.

7.3.5	Type Conversions	Supported.

7.3.6	Allocators	Not supported. Synthesized logic that supports dynamic allocation

of objects is too inefficient for programmable logic.

7.4	Static Expressions	Supported.

7.5	Universal Expressions	Supported.


Sequential Statements (VHDL)
Sequential Statements

MAX+PLUS II support for sequential statements is described below. Section numbers match those in the IEEE Standard VHDL Language Reference Manual.

Section	VHDL Construct	MAX+PLUS II Support (1)

8.1	Wait Statement	Supported. A Wait Statement must be the first statement

in a process, and it can only contain a condition clause.

8.2	Assertion Statement	Supported. Assertion Statements are passive.

8.3	Signal Assignment Statement	Supported. Signal Assignment Statements can

only have single-element waveforms, and cannot contain

After Clauses or Transport Delays.

8.3.1	Updating a Projected Output Waveform	Supported.

8.4	Variable Assignment Statement	Supported.

8.4.1	Array Variable Assignments	Supported. Only one- and two-dimensional arrays of scalar elements are supported.

8.5	Procedure Call Statement	Supported.

8.6	If Statement	Supported.

8.7	Case Statement	Supported.

8.8	Loop Statement	Supported. Loops must have locally static bounds.

8.9	Next Statement	Supported. Next Statements can only be included in

innermost unconditional loops.

8.10	Exit Statement	Not supported.

8.11	Return Statement	Supported. Return Statements are not allowed

within Procedure Bodies or Loop Statements.

8.12	Null Statement	Supported.


Concurrent Statements (VHDL)
Concurrent Statements

MAX+PLUS II support for concurrent statements is described below. Section numbers match those in the IEEE Standard VHDL Language Reference Manual.

Section	VHDL Construct	MAX+PLUS II Support (1)

9.1	Block Statement	Supported.

9.2	Process Statement	Supported.

9.2.1	Drivers	Supported.

9.3	Concurrent Procedure Call	Not supported. This feature will be supported in a

future release of MAX+PLUS II.

9.4	Concurrent Assertion Statement	Supported. Concurrent Assertion Statements are passive.

9.5	Concurrent Signal Assignment Statements	Supported.

9.5.1	Conditional Signal Assignment	Supported.

9.5.2	Selected Signal Assignment	Supported.

9.6	Component Instantiation Statement	Supported.

9.6.1	Instantiation of a Component	Supported.

9.7	Generate Statement	Supported. "For" Generate Statements must

have locally static bounds, and "If" Generate

Statements must have locally static conditions.


Scope & Visibility (VHDL)
Scope & Visibility

MAX+PLUS II support for the scope and visibility of VHDL constructs is described below. Section numbers match those in the IEEE Standard VHDL Language Reference Manual.

Section	VHDL Construct	MAX+PLUS II Support (1)

10.1	Declarative Regions	Supported.

10.2	Scope of Declarations	Supported.

10.3	Visibility	Supported.

10.4	Use Clauses	Supported.

10.5	The Context of Overload Resolution	Supported.


Design Units & Their Analysis (VHDL)
Design Units & Their Analysis

MAX+PLUS II support for design units and their analysis is described below. Section numbers match those in the IEEE Standard VHDL Language Reference Manual.

Section	VHDL Construct	MAX+PLUS II Support (1)

11.1	Design Units	Supported.

11.2	Design Libraries	Supported.

11.3	Context Clauses	Supported.

11.4	Order of Analysis	Supported.


Elaboration & Execution (VHDL)
Elaboration & Execution

MAX+PLUS II support for elaboration and execution of VHDL designs is described below. Section numbers match those in the IEEE Standard VHDL Language Reference Manual.

Section	VHDL Construct	MAX+PLUS II Support (1)

12.1	Elaboration of a Design Hierarchy	Supported.

12.2	Elaboration of a Block Header	Supported except the Generic Clause and Generic Map Clause.

12.2.1	The Generic Clause	Not supported.

12.2.2	The Generic Map Clause	Not supported.

12.2.3	The Port Clause	Supported as described in Design Entities & Configurations.

12.2.4	The Port Map Clause	Supported.

12.3	Elaboration of a Declarative Part	Supported.

12.3.1	Elaboration of a Declaration	Supported.

12.3.1.1	Subprogram Declarations & Bodies	Supported as described in Subprograms & Packages.

12.3.1.2	Type Declarations	Supported as described in Types and Declarations.

12.3.1.3	Subtype Declarations	Supported as described in Declarations.

12.3.1.4	Object Declarations	Supported as described in Declarations.

12.3.1.5	Alias Declarations	Supported as described in Declarations.

12.3.1.6	Attribute Declarations	Supported as described in Declarations.

12.3.1.7	Component Declarations	Supported except for Generic Clauses.

12.3.2	Elaboration of a Specification	Supported as described in Specifications.

12.3.2.1	Attribute Specification	Supported as described in Specifications.

12.3.2.2	Configuration Specification	Supported as described in Specifications.

12.3.2.3	Disconnection Specification	Ignored, as described in Specifications.

12.4	Elaboration of a Statement Part	Supported.

12.4.1	Block Statements	Supported as described in Concurrent Statements.

12.4.2	Generate Statements	Supported as described in Concurrent Statements.

12.4.3	Component Instantiation Statements	Supported as described in Concurrent Statements.

12.4.4	Other Concurrent Statements	Supported as described in Concurrent Statements.

12.5	Dynamic Elaboration	Not supported.

12.6	Execution of a Model	Not supported.

12.6.1	Propagation of Signal Values	Not supported.

12.6.2	Updating Implicit Signals	Not supported.

12.6.3	The Simulation Cycle	Not supported.


Lexical Elements (VHDL)
Lexical Elements

MAX+PLUS II support for lexical elements is described below. Section numbers match those in the IEEE Standard VHDL Language Reference Manual.

Section	VHDL Construct	MAX+PLUS II Support (1)

13.1	Character Set	Supported, but only 7-bit ASCII characters are

allowed. The full 8-bit VHDL character set will be

supported in a future release of MAX+PLUS II.

13.2	Lexical Elements, Separators & Delimiters	Supported.

13.3	Identifiers	Supported.

13.4	Abstract Literals	Supported.

13.4.1	Decimal Literals	Supported.

13.4.2	Based Literals	Supported.

13.5	Character Literals	Supported.

13.6	String Literals	Supported.

13.7	Bit String Literals	Supported.

13.8	Comments	Supported.

13.9	Reserved Words	Supported.

13.10	Allowable Replacements of Characters	Supported.


Predefined Language Environment (VHDL)
Predefined Language Environment

MAX+PLUS II support for a predefined language environment and file I/O is described below. Section numbers match those in the IEEE Standard VHDL Language Reference Manual.

Section	VHDL Construct	MAX+PLUS II Support (1)

14.1	Predefined Attributes	Supported except for 'ACTIVE, 'DELAYED, 'LAST_ACTIVE,

'LAST_EVENT, 'LAST_VALUE, 'QUIET, and 'TRANSACTION.

14.2	Package STANDARD	Supported.

14.3	Package TEXTIO	Supported. File I/O cannot be synthesized; therefore, calls

to TEXTIO functions are ignored.


VHDL Syntax
Syntax

Context Clauses

Library Clause

Use Clause

Library Units

Architecture Body

Configuration Declaration

Entity Declaration

Package Body

Package Declaration

Concurrent Statements

Block Statement

Component Instantiation Statement

Concurrent Procedure Call

Concurrent Signal Assignment Statement

Generate Statement

Process Statement

Sequential Statements

Case Statement

Exit Statement

Loop Statement

If Statement

Next Statement

Null Statement

Procedure Call Statement

Return Statement

Signal Assignment Statement

Variable Assignment Statement

Wait Statement


Abstract Literal BNF Syntax (VHDL)
Abstract Literal

<Abstract Literal>  ::=  Decimal Literal  |  Based Literal

See also:

<Numeric Literal>

<Physical Literal>


Access Type Definition BNF Syntax (VHDL)
Access Type Definition

<Access Type Definition>  ::=  ACCESS  <Subtype Indication>

See also:

<Type Definition>


Actual Designator BNF Syntax (VHDL)
Actual Designator

<Actual Designator>  ::=

<Expression>

|  <Signal    Name>

|  <Variable    Name>

|  OPEN

See also:

<Actual Part>


Actual Parameter Part BNF Syntax (VHDL)
Actual Parameter Part

<Actual Parameter Part>  ::=  <Parameter    Association List>

See also:

<Function Call>

<Procedure Call Statement>


Actual Part BNF Syntax (VHDL)
Actual Part

<Actual Part>  ::=

<Actual Designator>

|  <Function    Name>   (  <Actual Designator>   )

See also:

<Association Element>


Adding Operator BNF Syntax (VHDL)
Adding Operator

<Adding Operator>  ::=  +  |  -  |  &

See also:

<Simple Expression>


Aggregate BNF Syntax (VHDL)
Aggregate

<Aggregate>  ::=

(  <Element Association>   {  ,  <Element Association>   }  )

See also:

<Primary>

<Qualified Expression>

<Target>


Alias Declaration BNF Syntax (VHDL)
Alias Declaration

<Alias Declaration>  ::=

ALIAS  Identifier  :  <Subtype Indication>   IS  <Name>   ;

See also:

<Block Declarative Item>

<Entity Declarative Item>

<Package Body Declarative Item>

<Package Declarative Item>

<Process Declarative Item>

<Subprogram Declarative Item>


Allocator BNF Syntax (VHDL)
Allocator

<Allocator>  ::=

NEW  <Subtype Indication>

|  NEW  <Qualified Expression>

See also:

<Primary>


Architecture Body BNF Syntax (VHDL)
Architecture Body

<Architecture Body>  ::=

ARCHITECTURE  Identifier  OF  <Entity    Name>   IS

<Architecture Declarative Part>

BEGIN

<Architecture Statement Part>

END  [  <Architecture    Simple Name>   ]  ;

See also:

<Secondary Unit>


Architecture Declarative Part BNF Syntax (VHDL)
Architecture Declarative Part

<Architecture Declarative Part>  ::=

{  <Block Declarative Item>   }

See also:

<Architecture Body>


Architecture Statement Part BNF Syntax (VHDL)
Architecture Statement Part

<Architecture Statement Part>  ::=

{  <Concurrent Statement>   }

See also:

<Architecture Body>


Array Type Definition BNF Syntax (VHDL)
Array Type Definition

<Array Type Definition>  ::=

<Unconstrained Array Definition>   |  <Constrained Array Definition>

See also:

<Composite Type Definition>


Assertion Statement BNF Syntax (VHDL)
Assertion Statement

<Assertion Statement>  ::=

ASSERT  <Condition>

[  REPORT  <Expression>   ]

[  SEVERITY  <Expression>   ]  ;

See also:

<Concurrent Assertion Statement>

<Sequential Statement>


Association Element BNF Syntax (VHDL)
Association Element

<Association Element>  ::=

[  <Formal Part>   =>  ]  <Actual Part>

See also:

<Association List>


Association List BNF Syntax (VHDL)
Association List

<Association List>  ::=

<Association Element>   {  ,  <Association Element>   }

See also:

<Actual Parameter Part>

<Generic Map Aspect>

<Port Map Aspect>


Attribute Declaration BNF Syntax (VHDL)
Attribute Declaration

<Attribute Declaration>  ::=

ATTRIBUTE  Identifier  :  <Type Mark>   ;

See also:

<Block Declarative Item>

<Entity Declarative Item>

<Package Declarative Item>

<Process Declarative Item>

<Subprogram Declarative Item>


Attribute Designator BNF Syntax (VHDL)
Attribute Designator

<Attribute Designator>  ::=  <Attribute    Simple Name>

See also:

<Attribute Name>

<Attribute Specification>


Attribute Name BNF Syntax (VHDL)
Attribute Name

<Attribute Name>  ::=

<Prefix>   '  <Attribute Designator>   [  (  <Static    Expression>   )  ]

See also:

<Name>

<Range>


Attribute Specification BNF Syntax (VHDL)
Attribute Specification

<Attribute Specification>  ::=

ATTRIBUTE  <Attribute Designator>   OF  <Entity Specification>   IS  <Expression>   ;

See also:

<Block Declarative Item>

<Configuration Declarative Item>

<Entity Declarative Item>

<Package Declarative Item>

<Process Declarative Item>

<Subprogram Declarative Item>


Base Unit Declaration BNF Syntax (VHDL)
Base Unit Declaration

<Base Unit Declaration>  ::=  Identifier  ;

See also:

<Physical Type Definition>


Binding Indication BNF Syntax (VHDL)
Binding Indication

<Binding Indication>  ::=

<Entity Aspect>

[  <Generic Map Aspect>   ]

[  <Port Map Aspect>   ]

See also:

<Component Configuration>

<Configuration Specification>


Block Configuration BNF Syntax (VHDL)
Block Configuration

<Block Configuration>  ::=

FOR  <Block Specification>

{  <Use Clause>   }

{  <Configuration Item>   }

END  FOR  ;

See also:

<Component Configuration>

<Configuration Declaration>

<Configuration Item>


Block Declarative Item BNF Syntax (VHDL)
Block Declarative Item

<Block Declarative Item>  ::=

<Subprogram Declaration>

|  <Subprogram Body>

|  <Type Declaration>

|  <Subtype Declaration>

|  <Constant Declaration>

|  <Signal Declaration>

|  <File Declaration>

|  <Alias Declaration>

|  <Component Declaration>

|  <Attribute Declaration>

|  <Attribute Specification>

|  <Configuration Specification>

|  <Disconnection Specification>

|  <Use Clause>

See also:

<Architecture Declarative Part>

<Block Declarative Part>


Block Declarative Part BNF Syntax (VHDL)
Block Declarative Part

<Block Declarative Part>  ::=

{  <Block Declarative Item>   }

See also:

<Block Statement>


Block Header BNF Syntax (VHDL)
Block Header

<Block Header>  ::=

[  <Generic Clause>

[  <Generic Map Aspect>   ;  ]  ]

[  <Port Clause>

[  <Port Map Aspect>   ;  ]  ]

See also:

<Block Statement>


Block Specification BNF Syntax (VHDL)
Block Specification

<Block Specification>  ::=

<Architecture    Name>

|  <Block Statement    Label>

|  <Generate Statement    Label>   [  (  <Index Specification>   )  ]

See also:

<Block Configuration>


Block Statement BNF Syntax (VHDL)
Block Statement

<Block Statement>  ::=

<Block    Label>   :

BLOCK  [  (  <Guard    Expression>   )  ]

<Block Header>

<Block Declarative Part>

BEGIN

<Block Statement Part>

END  BLOCK  [  <Block    Label>   ]  ;

See also:

<Concurrent Statement>


Block Statement Part BNF Syntax (VHDL)
Block Statement Part

<Block Statement Part>  ::=

{  <Concurrent Statement>   }

See also:

<Block Statement>


Case Statement BNF Syntax (VHDL)
Case Statement

<Case Statement>  ::=

CASE  <Expression>   IS

<Case Statement Alternative>

{  <Case Statement Alternative>   }

END  CASE  ;

See also:

<Sequential Statement>


Case Statement Alternative BNF Syntax (VHDL)
Case Statement Alternative

<Case Statement Alternative>  ::=

WHEN  <Choices>   =>

<Sequence Of Statements>

See also:

<Case Statement>


Choice BNF Syntax (VHDL)
Choice

<Choice>  ::=

<Simple Expression>

|  <Discrete Range>

|  <Element    Simple Name>

|  OTHERS

See also:

<Choices>


Choices BNF Syntax (VHDL)
Choices

<Choices>  ::=  <Choice>   {  |  <Choice>   }

See also:

<Case Statement Alternative>

<Element Association>

<Selected Waveforms>


Component Configuration BNF Syntax (VHDL)
Component Configuration

<Component Configuration>  ::=

FOR  <Component Specification>

[  USE  <Binding Indication>   ;  ]

[  <Block Configuration>   ]

END  FOR  ;

See also:

<Configuration Item>


Component Declaration BNF Syntax (VHDL)
Component Declaration

<Component Declaration>  ::=

COMPONENT  Identifier

[  <Local    Generic Clause>   ]

[  <Local    Port Clause>   ]

END  COMPONENT  ;

See also:

<Block Declarative Item>

<Package Declarative Item>


Component Instantiation Statement BNF Syntax (VHDL)
Component Instantiation Statement

<Component Instantiation Statement>  ::=

<Instantiation    Label>   :

<Component    Name>

[  <Generic Map Aspect>   ]

[  <Port Map Aspect>   ]  ;

See also:

<Concurrent Statement>


Component Specification BNF Syntax (VHDL)
Component Specification

<Component Specification>  ::=

<Instantiation List>   :  <Component    Name>

See also:

<Component Configuration>

<Configuration Specification>


Composite Type Definition BNF Syntax (VHDL)
Composite Type Definition

<Composite Type Definition>  ::=

<Array Type Definition>

|  <Record Type Definition>

See also:

<Type Definition>


Concurrent Assertion Statement BNF Syntax (VHDL)
Concurrent Assertion Statement

<Concurrent Assertion Statement>  ::=

[  <Label>   :  ]  <Assertion Statement>

See also:

<Concurrent Statement>

<Entity Statement>


Concurrent Procedure Call BNF Syntax (VHDL)
Concurrent Procedure Call

<Concurrent Procedure Call>  ::=

[  <Label>   :  ]  <Procedure Call Statement>

See also:

<Concurrent Statement>

<Entity Statement>


Concurrent Signal Assignment Statement BNF Syntax (VHDL)
Concurrent Signal Assignment Statement

<Concurrent Signal Assignment Statement>  ::=

[  <Label>   :  ]  <Conditional Signal Assignment>

|  [  <Label>   :  ]  <Selected Signal Assignment>

See also:

<Concurrent Statement>


Concurrent Statement BNF Syntax (VHDL)
Concurrent Statement

<Concurrent Statement>  ::=

<Block Statement>

|  <Process Statement>

|  <Concurrent Procedure Call>

|  <Concurrent Assertion Statement>

|  <Concurrent Signal Assignment Statement>

|  <Component Instantiation Statement>

|  <Generate Statement>

See also:

<Architecture Statement Part>

<Block Statement Part>

<Generate Statement>


Condition BNF Syntax (VHDL)
Condition

<Condition>  ::=  <Boolean    Expression>

See also:

<Assertion Statement>

<Condition Clause>

<Conditional Waveforms>

<Exit Statement>

<Generation Scheme>

<If Statement>

<Iteration Scheme>

<Next Statement>


Condition Clause BNF Syntax (VHDL)
Condition Clause

<Condition Clause>  ::=  UNTIL  <Condition>

See also:

<Wait Statement>


Conditional Signal Assignment BNF Syntax (VHDL)
Conditional Signal Assignment

<Conditional Signal Assignment>  ::=

<Target>   <=  <Options>   <Conditional Waveforms>   ;

See also:

<Concurrent Signal Assignment Statement>


Conditional Waveforms BNF Syntax (VHDL)
Conditional Waveforms

<Conditional Waveforms>  ::=

{  <Waveform>   WHEN  <Condition>   ELSE  }

<Waveform>

See also:

<Conditional Signal Assignment>


Configuration Declaration BNF Syntax (VHDL)
Configuration Declaration

<Configuration Declaration>  ::=

CONFIGURATION  Identifier  OF  <Entity    Name>   IS

<Configuration Declarative Part>

<Block Configuration>

END  [  <Configuration    Simple Name>   ]  ;

See also:

<Primary Unit>


Configuration Declarative Item BNF Syntax (VHDL)
Configuration Declarative Item

<Configuration Declarative Item>  ::=

<Use Clause>

|  <Attribute Specification>

See also:

<Configuration Declarative Part>


Configuration Declarative Part BNF Syntax (VHDL)
Configuration Declarative Part

<Configuration Declarative Part>  ::=

{  <Configuration Declarative Item>   }

See also:

<Configuration Declaration>


Configuration Item BNF Syntax (VHDL)
Configuration Item

<Configuration Item>  ::=

<Block Configuration>

|  <Component Configuration>

See also:

<Block Configuration>


Configuration Specification BNF Syntax (VHDL)
Configuration Specification

<Configuration Specification>  ::=

FOR  <Component Specification>   USE  <Binding Indication>   ;

See also:

<Block Declarative Item>


Constant Declaration BNF Syntax (VHDL)
Constant Declaration

<Constant Declaration>  ::=

CONSTANT  <Identifier List>   :  <Subtype Indication>   [  :=  <Expression>   ]  ;

See also:

<Block Declarative Item>

<Entity Declarative Item>

<Package Body Declarative Item>

<Package Declarative Item>

<Process Declarative Item>

<Subprogram Declarative Item>


Constrained Array Definition BNF Syntax (VHDL)
Constrained Array Definition

<Constrained Array Definition>  ::=

ARRAY  <Index Constraint>   OF  <Element    Subtype Indication>

See also:

<Array Type Definition>


Constraint BNF Syntax (VHDL)
Constraint

<Constraint>  ::=

<Range Constraint>

|  <Index Constraint>

See also:

<Subtype Indication>


Context Clause BNF Syntax (VHDL)
Context Clause

<Context Clause>  ::=  {  <Context Item>   }

See also:

<Design Unit>


Context Item BNF Syntax (VHDL)
Context  Item

<Context Item>  ::=

<Library Clause>

|  <Use Clause>

See also:

<Context Clause>


Design File BNF Syntax (VHDL)
Design File

<Design File>  ::=  <Design Unit>   {  <Design Unit>   }


Design Unit BNF Syntax (VHDL)
Design Unit

<Design Unit>  ::=  <Context Clause>   <Library Unit>

See also:

<Design File>


Designator BNF Syntax (VHDL)
Designator

<Designator>  ::=  Identifier  |  <Operator Symbol>

See also:

<Subprogram Body>

<Subprogram Specification>


Direction BNF Syntax (VHDL)
Direction

<Direction>  ::=  TO  |  DOWNTO

See also:

<Range>


Disconnection Specification BNF Syntax (VHDL)
Disconnection Specification

<Disconnection Specification>  ::=

DISCONNECT  <Guarded Signal Specification>   AFTER  <Time    Expression>   ;

See also:

<Block Declarative Item>

<Entity Declarative Item>

<Package Declarative Item>


Discrete Range BNF Syntax (VHDL)
Discrete Range

<Discrete Range>  ::=  <Discrete    Subtype Indication>   |  <Range>

See also:

<Choice>

<Index Constraint>

<Index Specification>

<Parameter Specification>

<Slice Name>


Element Association BNF Syntax (VHDL)
Element Association

<Element Association>  ::=

[  <Choices>   =>  ]  <Expression>

See also:

<Aggregate>


Element Declaration BNF Syntax (VHDL)
Element Declaration

<Element Declaration>  ::=

<Identifier List>   :  <Element Subtype Definition>   ;

See also:

<Record Type Definition>


Element Subtype Definition BNF Syntax (VHDL)
Element Subtype Definition

<Element Subtype Definition>  ::=  <Subtype Indication>

See also:

<Element Declaration>


Entity Aspect BNF Syntax (VHDL)
Entity Aspect

<Entity Aspect>  ::=

ENTITY  <Entity    Name>   [  (  <Architecture    Identifier  )  ]

|  CONFIGURATION  <Configuration    Name>

|  OPEN

See also:

<Binding Indication>


Entity Class BNF Syntax (VHDL)
Entity Class

<Entity Class>  ::=

ENTITY  	|  ARCHITECTURE  	|  CONFIGURATION

|  PROCEDURE  	|  FUNCTION  	|  PACKAGE

|  TYPE  	|  SUBTYPE  	|  CONSTANT

|  SIGNAL  	|  VARIABLE  	|  COMPONENT

|  LABEL

See also:

<Entity Specification>


Entity Declaration BNF Syntax (VHDL)
Entity Declaration

<Entity Declaration>  ::=

ENTITY  Identifier  IS

<Entity Header>

<Entity Declarative Part>

[  BEGIN

<Entity Statement Part>   ]

END  [  <Entity    Simple Name>   ]  ;

See also:

<Primary Unit>


Entity Declarative Item BNF Syntax (VHDL)
Entity Declarative Item

<Entity Declarative Item>  ::=

<Subprogram Declaration>

|  <Subprogram Body>

|  <Type Declaration>

|  <Subtype Declaration>

|  <Constant Declaration>

|  <Signal Declaration>

|  <File Declaration>

|  <Alias Declaration>

|  <Attribute Declaration>

|  <Attribute Specification>

|  <Disconnection Specification>

|  <Use Clause>

See also:

<Entity Declarative Part>


Entity Declarative Part BNF Syntax (VHDL)
Entity Declarative Part

<Entity Declarative Part>  ::=

{  <Entity Declarative Item>   }

See also:

<Entity Declaration>


Entity Designator BNF Syntax (VHDL)
Entity Designator

<Entity Designator>  ::=  <Simple Name>   |  <Operator Symbol>

See also:

<Entity Name List>


Entity Header BNF Syntax (VHDL)
Entity Header

<Entity Header>  ::=

[  <Formal    Generic Clause>   ]

[  <Formal    Port Clause>   ]

See also:

<Entity Declaration>


Entity Name List BNF Syntax (VHDL)
Entity Name List

<Entity Name List>  ::=

<Entity Designator>   {  ,  <Entity Designator>   }

|  OTHERS

|  ALL

See also:

<Entity Specification>


Entity Specification BNF Syntax (VHDL)
Entity Specification

<Entity Specification>  ::=

<Entity Name List>   :  <Entity Class>

See also:

<Attribute Specification>


Entity Statement BNF Syntax (VHDL)
Entity Statement

<Entity Statement>  ::=

<Concurrent Assertion Statement>

|  <Passive    Concurrent Procedure Call>

|  <Passive    Process Statement>

See also:

<Entity Statement Part>


Entity Statement Part BNF Syntax (VHDL)
Entity Statement Part

<Entity Statement Part>  ::=

{  <Entity Statement>   }

See also:

<Entity Declaration>


Enumeration Literal BNF Syntax (VHDL)
Enumeration Literal

<Enumeration Literal>  ::=  Identifier  |  Character Literal

See also:

<Enumeration Type Definition>

<Literal>


Enumeration Type Definition BNF Syntax (VHDL)
Enumeration Type Definition

<Enumeration Type Definition>  ::=

(  <Enumeration Literal>   {  ,  <Enumeration Literal>   }  )

See also:

<Scalar Type Definition>


Exit Statement BNF Syntax (VHDL)
Exit Statement

<Exit Statement>  ::=

EXIT  [  <Loop    Label>   ]  [  WHEN  <Condition>   ]  ;

See also:

<Sequential Statement>


Expression BNF Syntax (VHDL)
Expression

<Expression>  ::=

<Relation>   {  AND  <Relation>   }

|  <Relation>   {  OR  <Relation>   }

|  <Relation>   {  XOR  <Relation>   }

|  <Relation>   [  NAND  <Relation>   ]

|  <Relation>   [  NOR  <Relation>   ]

See also:

<Actual Designator>

<Assertion Statement>

<Attribute Name>

<Attribute Specification>

<Block Statement>

<Case Statement>

<Condition>

<Constant Declaration>

<Disconnection Specification>

<Element Association>

<File Logical Name>

<Index Specification>

<Indexed Name>

<Interface Constant Declaration>

<Interface Signal Declaration>

<Interface Variable Declaration>

<Primary>

<Qualified Expression>

<Return Statement>

<Selected Signal Assignment>

<Signal Declaration>

<Timeout Clause>

<Type Conversion>

<Variable Assignment Statement>

<Variable Declaration>

<Waveform Element>


Factor BNF Syntax (VHDL)
Factor

<Factor>  ::=

<Primary>   [  **  <Primary>   ]

|  ABS  <Primary>

|  NOT  <Primary>

See also:

<Term>


File Declaration BNF Syntax (VHDL)
File Declaration

<File Declaration>  ::=

FILE  Identifier  :  <Subtype Indication>   IS  [  <Mode>   ]  <File Logical Name>   ;

See also:

<Block Declarative Item>

<Entity Declarative Item>

<Package Body Declarative Item>

<Package Declarative Item>

<Process Declarative Item>

<Subprogram Declarative Item>


File Logical Name BNF Syntax (VHDL)
File Logical Name

<File Logical Name>  ::=  <String    Expression>

See also:

<File Declaration>


File Type Definition BNF Syntax (VHDL)
File Type Definition

<File Type Definition>  ::=

FILE  OF  <Type Mark>

See also:

<Type Definition>


Floating Type Definition BNF Syntax (VHDL)
Floating Type Definition

<Floating Type Definition>  ::=  <Range Constraint>

See also:

<Scalar Type Definition>


Formal Designator BNF Syntax (VHDL)
Formal Designator

<Formal Designator>  ::=

<Generic    Name>

|  <Port    Name>

|  <Parameter    Name>

See also:

<Formal Part>


Formal Parameter List BNF Syntax (VHDL)
Formal Parameter List

<Formal Parameter List>  ::=  <Parameter    Interface List>

See also:

<Subprogram Specification>


Formal Part BNF Syntax (VHDL)
Formal Part

<Formal Part>  ::=

<Formal Designator>

|  <Function    Name>   (  <Formal Designator>   )

See also:

<Association Element>


Full Type Declaration BNF Syntax (VHDL)
Full Type Declaration

<Full Type Declaration>  ::=

TYPE  Identifier  IS  <Type Definition>   ;

See also:

<Type Declaration>


Function Call BNF Syntax (VHDL)
Function Call

<Function Call>  ::=

<Function    Name>   [  (  <Actual Parameter Part>   )  ]

See also:

<Prefix>

<Primary>


Generate Statement BNF Syntax (VHDL)
Generate Statement

<Generate Statement>  ::=

<Generate    Label>   :

<Generation Scheme>   GENERATE

{  <Concurrent Statement>   }

END  GENERATE  [  <Generate    Label>   ]  ;

See also:

<Concurrent Statement>


Generation Scheme BNF Syntax (VHDL)
Generation Scheme

<Generation Scheme>  ::=

FOR  <Generate    Parameter Specification>

|  IF  <Condition>

See also:

<Generate Statement>


Generic Clause BNF Syntax (VHDL)
Generic Clause

<Generic Clause>  ::=

GENERIC  (  <Generic List>   )  ;

See also:

<Block Header>

<Component Declaration>

<Entity Header>


Generic List BNF Syntax (VHDL)
Generic List

<Generic List>  ::=  <Generic    Interface List>

See also:

<Generic Clause>


Generic Map Aspect BNF Syntax (VHDL)
Generic Map Aspect

<Generic Map Aspect>  ::=

GENERIC  MAP  (  <Generic    Association List>   )

See also:

<Binding Indication>

<Block Header>

<Component Instantiation Statement>


Guarded Signal Specification BNF Syntax (VHDL)
Guarded Signal Specification

<Guarded Signal Specification>  ::=

<Guarded    Signal List>   :  <Type Mark>

See also:

<Disconnection Specification>


Identifier List BNF Syntax (VHDL)
Identifier List

<Identifier List>  ::=  Identifier  {  ,  Identifier  }

See also:

<Constant Declaration>

<Element Declaration>

<Interface Constant Declaration>

<Interface Signal Declaration>

<Interface Variable Declaration>

<Signal Declaration>

<Variable Declaration>


If Statement BNF Syntax (VHDL)
If Statement

<If Statement>  ::=

IF  <Condition>   THEN

<Sequence Of Statements>

{  ELSIF  <Condition>   THEN

<Sequence Of Statements>   }

[  ELSE

<Sequence Of Statements>   ]

END  IF  ;

See also:

<Sequential Statement>


Incomplete Type Declaration BNF Syntax (VHDL)
Incomplete Type Declaration

<Incomplete Type Declaration>  ::=  TYPE  Identifier  ;

See also:

<Type Declaration>


Index Constraint BNF Syntax (VHDL)
Index Constraint

<Index Constraint>  ::=  (  <Discrete Range>   {  ,  <Discrete Range>   }  )

See also:

<Constrained Array Definition>

<Constraint>


Index Specification BNF Syntax (VHDL)
Index Specification

<Index Specification>  ::=

<Discrete Range>

|  <Static    Expression>

See also:

<Block Specification>


Index Subtype Definition BNF Syntax (VHDL)
Index Subtype Definition

<Index Subtype Definition>  ::=  <Type Mark>   RANGE  <>

See also:

<Unconstrained Array Definition>


Indexed Name BNF Syntax (VHDL)
Indexed Name

<Indexed Name>  ::=  <Prefix>   (  <Expression>   {  ,  <Expression>   }  )

See also:

<Name>


Instantiation List BNF Syntax (VHDL)
Instantiation List

<Instantiation List>  ::=

<Instantiation    Label>   {  ,  <Instantiation    Label>   }

|  OTHERS

|  ALL

See also:

<Component Specification>


Integer Type Definition BNF Syntax (VHDL)
Integer Type Definition

<Integer Type Definition>  ::=  <Range Constraint>

See also:

<Scalar Type Definition>


Interface Constant Declaration BNF Syntax (VHDL)
Interface Constant Declaration

<Interface Constant Declaration>  ::=

[  CONSTANT  ]  <Identifier List>   :  [  IN  ]  <Subtype Indication>   [  :=  <Static    Expression>   ]

See also:

<Interface Declaration>


Interface Declaration BNF Syntax (VHDL)
Interface Declaration

<Interface Declaration>  ::=

<Interface Constant Declaration>

|  <Interface Signal Declaration>

|  <Interface Variable Declaration>

See also:

<Interface Element>


Interface Element BNF Syntax (VHDL)
Interface Element

<Interface Element>  ::=  <Interface Declaration>

See also:

<Interface List>


Interface List BNF Syntax (VHDL)
Interface List

<Interface List>  ::=

<Interface Element>   {  ;  <Interface Element>   }

See also:

<Formal Parameter List>

<Generic List>

<Port List>


Interface Signal Declaration BNF Syntax (VHDL)
Interface Signal Declaration

<Interface Signal Declaration>  ::=

[  SIGNAL  ]  <Identifier List>   :  [  <Mode>   ]  <Subtype Indication>   [  BUS  ]  [  :=  <Static    Expression>   ]

See also:

<Interface Declaration>


Interface Variable Declaration BNF Syntax (VHDL)
Interface Variable Declaration

<Interface Variable Declaration>  ::=

[  VARIABLE  ]  <Identifier List>   :  [  <Mode>   ]  <Subtype Indication>   [  :=  <Static    Expression>   ]

See also:

<Interface Declaration>


Iteration Scheme BNF Syntax (VHDL)
Iteration Scheme

<Iteration Scheme>  ::=

WHILE  <Condition>

|  FOR  <Loop    Parameter Specification>

See also:

<Loop Statement>


Label BNF Syntax (VHDL)
Label

<Label>  ::=  Identifier

See also:

<Block Specification>

<Block Statement>

<Component Instantiation Statement>

<Concurrent Assertion Statement>

<Concurrent Procedure Call>

<Concurrent Signal Assignment Statement>

<Exit Statement>

<Generate Statement>

<Instantiation List>

<Loop Statement>

<Next Statement>

<Process Statement>


Library Clause BNF Syntax (VHDL)
Library Clause

<Library Clause>  ::=  LIBRARY  <Logical Name List>   ;

See also:

<Context Item>


Library Unit BNF Syntax (VHDL)
Library Unit

<Library Unit>  ::=

<Primary Unit>

|  <Secondary Unit>

See also:

<Design Unit>


Literal BNF Syntax (VHDL)
Literal

<Literal>  ::=

<Numeric Literal>

|  <Enumeration Literal>

|  String Literal

|  Bit String Literal

|  NULL

See also:

<Primary>


Logical Name BNF Syntax (VHDL)
Logical Name

<Logical Name>  ::=  Identifier

See also:

<Logical Name List>


Logical Name List BNF Syntax (VHDL)
Logical Name List

<Logical Name List>  ::=  <Logical Name>   {  ,  <Logical Name>   }

See also:

<Library Clause>


Loop Statement BNF Syntax (VHDL)
Loop Statement

<Loop Statement>  ::=

[  <Loop    Label>   :  ]

[  <Iteration Scheme>   ]  LOOP

<Sequence Of Statements>

END  LOOP  [  <Loop    Label>   ]  ;

See also:

<Sequential Statement>


Mode BNF Syntax (VHDL)
Mode

<Mode>  ::=  IN  |  OUT  |  INOUT  |  BUFFER  |  LINKAGE

See also:

<File Declaration>

<Interface Signal Declaration>

<Interface Variable Declaration>


Multiplying Operator BNF Syntax (VHDL)
Multiplying Operator

<Multiplying Operator>  ::=  *  |  /  |  MOD  |  REM

See also:

<Term>


Name BNF Syntax (VHDL)
Name

<Name>  ::=

<Simple Name>

|  <Operator Symbol>

|  <Selected Name>

|  <Indexed Name>

|  <Slice Name>

|  <Attribute Name>

See also:

<Actual Designator>

<Actual Part>

<Alias Declaration>

<Architecture Body>

<Block Specification>

<Component Instantiation Statement>

<Component Specification>

<Configuration Declaration>

<Entity Aspect>

<Formal Designator>

<Formal Part>

<Function Call>

<Physical Literal>

<Prefix>

<Primary>

<Procedure Call Statement>

<Sensitivity List>

<Signal List>

<Subtype Indication>

<Target>

<Type Mark>


Next Statement BNF Syntax (VHDL)
Next Statement

<Next Statement>  ::=

NEXT  [  <Loop    Label>   ]  [  WHEN  <Condition>   ]  ;

See also:

<Sequential Statement>


Null Statement BNF Syntax (VHDL)
Null Statement

<Null Statement>  ::=  NULL  ;

See also:

<Sequential Statement>


Numeric Literal BNF Syntax (VHDL)
Numeric Literal

<Numeric Literal>  ::=

<Abstract Literal>

|  <Physical Literal>

See also:

<Literal>


Operator Symbol BNF Syntax (VHDL)
Operator Symbol

<Operator Symbol>  ::=  String Literal

See also:

<Designator>

<Entity Designator>

<Name>

<Suffix>


Options BNF Syntax (VHDL)
Options

<Options>  ::=  [  GUARDED  ]  [  TRANSPORT  ]

See also:

<Conditional Signal Assignment>

<Selected Signal Assignment>


Package Body BNF Syntax (VHDL)
Package Body

<Package Body>  ::=

PACKAGE  BODY  <Package    Simple Name>   IS

<Package Body Declarative Part>

END  [  <Package    Simple Name>   ]  ;

See also:

<Secondary Unit>


Package Body Declarative Item BNF Syntax (VHDL)
Package Body Declarative Item

<Package Body Declarative Item>  ::=

<Subprogram Declaration>

|  <Subprogram Body>

|  <Type Declaration>

|  <Subtype Declaration>

|  <Constant Declaration>

|  <File Declaration>

|  <Alias Declaration>

|  <Use Clause>

See also:

<Package Body Declarative Part>


Package Body Declarative Part BNF Syntax (VHDL)
Package Body Declarative Part

<Package Body Declarative Part>  ::=

{  <Package Body Declarative Item>   }

See also:

<Package Body>


Package Declaration BNF Syntax (VHDL)
Package Declaration

<Package Declaration>  ::=

PACKAGE  Identifier  IS

<Package Declarative Part>

END  [  <Package    Simple Name>   ]  ;

See also:

<Primary Unit>


Package Declarative Item BNF Syntax (VHDL)
Package Declarative Item

<Package Declarative Item>  ::=

<Subprogram Declaration>

|  <Type Declaration>

|  <Subtype Declaration>

|  <Constant Declaration>

|  <Signal Declaration>

|  <File Declaration>

|  <Alias Declaration>

|  <Component Declaration>

|  <Attribute Declaration>

|  <Attribute Specification>

|  <Disconnection Specification>

|  <Use Clause>

See also:

<Package Declarative Part>


Package Declarative Part BNF Syntax (VHDL)
Package Declarative Part

<Package Declarative Part>  ::=

{  <Package Declarative Item>   }

See also:

<Package Declaration>


Parameter Specification BNF Syntax (VHDL)
Parameter Specification

<Parameter Specification>  ::=

Identifier  IN  <Discrete Range>

See also:

<Generation Scheme>

<Iteration Scheme>


Physical Literal BNF Syntax (VHDL)
Physical Literal

<Physical Literal>  ::=  [  <Abstract Literal>   ]  <Unit    Name>

See also:

<Numeric Literal>

<Secondary Unit Declaration>


Physical Type Definition BNF Syntax (VHDL)
Physical Type Definition

<Physical Type Definition>  ::=

<Range Constraint>

UNITS

<Base Unit Declaration>

{  <Secondary Unit Declaration>   }

END  UNITS

See also:

<Scalar Type Definition>


Port Clause BNF Syntax (VHDL)
Port Clause

<Port Clause>  ::=

PORT  (  <Port List>   )  ;

See also:

<Block Header>

<Component Declaration>

<Entity Header>


Port List BNF Syntax (VHDL)
Port List

<Port List>  ::=  <Port    Interface List>

See also:

<Port Clause>


Port Map Aspect BNF Syntax (VHDL)
Port Map Aspect

<Port Map Aspect>  ::=

PORT  MAP  (  <Port    Association List>   )

See also:

<Binding Indication>

<Block Header>

<Component Instantiation Statement>


Prefix BNF Syntax (VHDL)
Prefix

<Prefix>  ::=

<Name>

|  <Function Call>

See also:

<Attribute Name>

<Indexed Name>

<Selected Name>

<Slice Name>


Primary BNF Syntax (VHDL)
Primary

<Primary>  ::=

<Name>

|  <Literal>

|  <Aggregate>

|  <Function Call>

|  <Qualified Expression>

|  <Type Conversion>

|  <Allocator>

|  (  <Expression>   )

See also:

<Factor>


Primary Unit BNF Syntax (VHDL)
Primary Unit

<Primary Unit>  ::=

<Entity Declaration>

|  <Configuration Declaration>

|  <Package Declaration>

See also:

<Library Unit>


Procedure Call Statement BNF Syntax (VHDL)
Procedure Call Statement

<Procedure Call Statement>  ::=

<Procedure    Name>   [  (  <Actual Parameter Part>   )  ]  ;

See also:

<Concurrent Procedure Call>

<Sequential Statement>


Process Declarative Item BNF Syntax (VHDL)
Process Declarative Item

<Process Declarative Item>  ::=

<Subprogram Declaration>

|  <Subprogram Body>

|  <Type Declaration>

|  <Subtype Declaration>

|  <Constant Declaration>

|  <Variable Declaration>

|  <File Declaration>

|  <Alias Declaration>

|  <Attribute Declaration>

|  <Attribute Specification>

|  <Use Clause>

See also:

<Process Declarative Part>


Process Declarative Part BNF Syntax (VHDL)
Process Declarative Part

<Process Declarative Part>  ::=

{  <Process Declarative Item>   }

See also:

<Process Statement>


Process Statement BNF Syntax (VHDL)
Process Statement

<Process Statement>  ::=

[  <Process    Label>   :  ]

PROCESS  [  (  <Sensitivity List>   )  ]

<Process Declarative Part>

BEGIN

<Process Statement Part>

END  PROCESS  [  <Process    Label>   ]  ;

See also:

<Concurrent Statement>

<Entity Statement>


Process Statement Part BNF Syntax (VHDL)
Process Statement Part

<Process Statement Part>  ::=

{  <Sequential Statement>   }

See also:

<Process Statement>


Qualified Expression BNF Syntax (VHDL)
Qualified Expression

<Qualified Expression>  ::=

<Type Mark>   '  (  <Expression>   )

|  <Type Mark>   '  <Aggregate>

See also:

<Allocator>

<Primary>


Range BNF Syntax (VHDL)
Range

<Range>  ::=

<Range    Attribute Name>

|  <Simple Expression>   <Direction>   <Simple Expression>

See also:

<Discrete Range>

<Range Constraint>


Range Constraint BNF Syntax (VHDL)
Range Constraint

<Range Constraint>  ::=  RANGE  <Range>

See also:

<Constraint>

<Floating Type Definition>

<Integer Type Definition>

<Physical Type Definition>


Record Type Definition BNF Syntax (VHDL)
Record Type Definition

<Record Type Definition>  ::=

RECORD

<Element Declaration>

{  <Element Declaration>   }

END  RECORD

See also:

<Composite Type Definition>


Relation BNF Syntax (VHDL)
Relation

<Relation>  ::=

<Simple Expression>   [  <Relational Operator>   <Simple Expression>   ]

See also:

<Expression>


Relational Operator BNF Syntax (VHDL)
Relational Operator

<Relational Operator>  ::=  =  |  /=  |  <  |  <=  |  >  |  >=

See also:

<Relation>


Return Statement BNF Syntax (VHDL)
Return Statement

<Return Statement>  ::=

RETURN  [  <Expression>   ]  ;

See also:

<Sequential Statement>


Scalar Type Definition BNF Syntax (VHDL)
Scalar Type Definition

<Scalar Type Definition>  ::=

<Enumeration Type Definition>   	|  <Integer Type Definition>

|  <Floating Type Definition>   	|  <Physical Type Definition>

See also:

<Type Definition>


Secondary Unit BNF Syntax (VHDL)
Secondary Unit

<Secondary Unit>  ::=

<Architecture Body>

|  <Package Body>

See also:

<Library Unit>


Secondary Unit Declaration BNF Syntax (VHDL)
Secondary Unit Declaration

<Secondary Unit Declaration>  ::=  Identifier  =  <Physical Literal>   ;

See also:

<Physical Type Definition>


Selected Name BNF Syntax (VHDL)
Selected Name

<Selected Name>  ::=  <Prefix>   .  <Suffix>

See also:

<Name>

<Use Clause>


Selected Signal Assignment BNF Syntax (VHDL)
Selected Signal Assignment

<Selected Signal Assignment>  ::=

WITH  <Expression>   SELECT

<Target>   <=  <Options>   <Selected Waveforms>   ;

See also:

<Concurrent Signal Assignment Statement>


Selected Waveforms BNF Syntax (VHDL)
Selected Waveforms

<Selected Waveforms>  ::=

{  <Waveform>   WHEN  <Choices>   ,  }

<Waveform>   WHEN  <Choices>

See also:

<Selected Signal Assignment>


Sensitivity Clause BNF Syntax (VHDL)
Sensitivity Clause

<Sensitivity Clause>  ::=  ON  <Sensitivity List>

See also:

<Wait Statement>


Sensitivity List BNF Syntax (VHDL)
Sensitivity List

<Sensitivity List>  ::=  <Signal    Name>   {  ,  <Signal    Name>   }

See also:

<Process Statement>

<Sensitivity Clause>


Sequence Of Statements BNF Syntax (VHDL)
Sequence Of Statements

<Sequence Of Statements>  ::=

{  <Sequential Statement>   }

See also:

<Case Statement Alternative>

<If Statement>

<Loop Statement>


Sequential Statement BNF Syntax (VHDL)
Sequential Statement

<Sequential Statement>  ::=

<Wait Statement>

|  <Assertion Statement>

|  <Signal Assignment Statement>

|  <Variable Assignment Statement>

|  <Procedure Call Statement>

|  <If Statement>

|  <Case Statement>

|  <Loop Statement>

|  <Next Statement>

|  <Exit Statement>

|  <Return Statement>

|  <Null Statement>

See also:

<Process Statement Part>

<Sequence Of Statements>

<Subprogram Statement Part>


Sign BNF Syntax (VHDL)
Sign

<Sign>  ::=  +  |  -

See also:

<Simple Expression>


Signal Assignment Statement BNF Syntax (VHDL)
Signal Assignment Statement

<Signal Assignment Statement>  ::=

<Target>   <=  [  TRANSPORT  ]  <Waveform>   ;

See also:

<Sequential Statement>


Signal Declaration BNF Syntax (VHDL)
Signal Declaration

<Signal Declaration>  ::=

SIGNAL  <Identifier List>   :  <Subtype Indication>   [  <Signal Kind>   ]  [  :=  <Expression>   ]  ;

See also:

<Block Declarative Item>

<Entity Declarative Item>

<Package Declarative Item>


Signal Kind BNF Syntax (VHDL)
Signal Kind

<Signal Kind>  ::=  REGISTER  |  BUS

See also:

<Signal Declaration>


Signal List BNF Syntax (VHDL)
Signal List

<Signal List>  ::=

<Signal    Name>   {  ,  <Signal    Name>   }

|  OTHERS

|  ALL

See also:

<Guarded Signal Specification>


Simple Expression BNF Syntax (VHDL)
Simple Expression

<Simple Expression>  ::=

[  <Sign>   ]  <Term>   {  <Adding Operator>   <Term>   }

See also:

<Choice>

<Range>

<Relation>


Simple Name BNF Syntax (VHDL)
Simple Name

<Simple Name>  ::=  Identifier

See also:

<Architecture Body>

<Attribute Designator>

<Choice>

<Configuration Declaration>

<Entity Declaration>

<Entity Designator>

<Name>

<Package Body>

<Package Declaration>

<Suffix>


Slice Name BNF Syntax (VHDL)
Slice Name

<Slice Name>  ::=  <Prefix>   (  <Discrete Range>   )

See also:

<Name>


Subprogram Body BNF Syntax (VHDL)
Subprogram Body

<Subprogram Body>  ::=

<Subprogram Specification>   IS

<Subprogram Declarative Part>

BEGIN

<Subprogram Statement Part>

END  [  <Designator>   ]  ;

See also:

<Block Declarative Item>

<Entity Declarative Item>

<Package Body Declarative Item>

<Process Declarative Item>

<Subprogram Declarative Item>


Subprogram Declaration BNF Syntax (VHDL)
Subprogram Declaration

<Subprogram Declaration>  ::=

<Subprogram Specification>   ;

See also:

<Block Declarative Item>

<Entity Declarative Item>

<Package Body Declarative Item>

<Package Declarative Item>

<Process Declarative Item>

<Subprogram Declarative Item>


Subprogram Declarative Item BNF Syntax (VHDL)
Subprogram Declarative Item

<Subprogram Declarative Item>  ::=

<Subprogram Declaration>

|  <Subprogram Body>

|  <Type Declaration>

|  <Subtype Declaration>

|  <Constant Declaration>

|  <Variable Declaration>

|  <File Declaration>

|  <Alias Declaration>

|  <Attribute Declaration>

|  <Attribute Specification>

|  <Use Clause>

See also:

<Subprogram Declarative Part>


Subprogram Declarative Part BNF Syntax (VHDL)
Subprogram Declarative Part

<Subprogram Declarative Part>  ::=

{  <Subprogram Declarative Item>   }

See also:

<Subprogram Body>


Subprogram Specification BNF Syntax (VHDL)
Subprogram Specification

<Subprogram Specification>  ::=

PROCEDURE  <Designator>   [  (  <Formal Parameter List>   )  ]

|  FUNCTION <Designator>   [  (  <Formal Parameter List>   )  ]  RETURN  <Type Mark>

See also:

<Subprogram Body>

<Subprogram Declaration>


Subprogram Statement Part BNF Syntax (VHDL)
Subprogram Statement Part

<Subprogram Statement Part>  ::=

{  <Sequential Statement>   }

See also:

<Subprogram Body>


Subtype Declaration BNF Syntax (VHDL)
Subtype Declaration

<Subtype Declaration>  ::=

SUBTYPE  Identifier  IS  <Subtype Indication>   ;

See also:

<Block Declarative Item>

<Entity Declarative Item>

<Package Body Declarative Item>

<Package Declarative Item>

<Process Declarative Item>

<Subprogram Declarative Item>


Subtype Indication BNF Syntax (VHDL)
Subtype Indication

<Subtype Indication>  ::=

[  <Resolution Function    Name>   ]  <Type Mark>   [  <Constraint>   ]

See also:

<Access Type Definition>

<Alias Declaration>

<Allocator>

<Constant Declaration>

<Constrained Array Definition>

<Discrete Range>

<Element Subtype Definition>

<File Declaration>

<Interface Constant Declaration>

<Interface Signal Declaration>

<Interface Variable Declaration>

<Signal Declaration>

<Subtype Declaration>

<Unconstrained Array Definition>

<Variable Declaration>


Suffix BNF Syntax (VHDL)
Suffix

<Suffix>  ::=

<Simple Name>

|  Character Literal

|  <Operator Symbol>

|  ALL

See also:

<Selected Name>


Target BNF Syntax (VHDL)
Target

<Target>  ::=

<Name>

|  <Aggregate>

See also:

<Conditional Signal Assignment>

<Selected Signal Assignment>

<Signal Assignment Statement>

<Variable Assignment Statement>


Term BNF Syntax (VHDL)
Term

<Term>  ::=

<Factor>   {  <Multiplying Operator>   <Factor>   }

See also:

<Simple Expression>


Timeout Clause BNF Syntax (VHDL)
Timeout

<Timeout Clause>  ::=  FOR  <Time    Expression>

See also:

<Wait Statement>


Type Conversion BNF Syntax (VHDL)
Type Conversion

<Type Conversion>  ::=  <Type Mark>   (  <Expression>   )

See also:

<Primary>


Type Declaration BNF Syntax (VHDL)
Type Declaration

<Type Declaration>  ::=

<Full Type Declaration>

|  <Incomplete Type Declaration>

See also:

<Block Declarative Item>

<Entity Declarative Item>

<Package Body Declarative Item>

<Package Declarative Item>

<Process Declarative Item>

<Subprogram Declarative Item>


Type Definition BNF Syntax (VHDL)
Type Definition

<Type Definition>  ::=

<Scalar Type Definition>

|  <Composite Type Definition>

|  <Access Type Definition>

|  <File Type Definition>

See also:

<Full Type Declaration>


Type Mark BNF Syntax (VHDL)
Type Mark

<Type Mark>  ::=

<Type    Name>

|  <Subtype    Name>

See also:

<Attribute Declaration>

<File Type Definition>

<Guarded Signal Specification>

<Index Subtype Definition>

<Qualified Expression>

<Subprogram Specification>

<Subtype Indication>

<Type Conversion>


Unconstrained Array Definition BNF Syntax (VHDL)
Unconstrained Array Definition

<Unconstrained Array Definition>  ::=

ARRAY  (  <Index Subtype Definition>   {  ,  <Index Subtype Definition>   }  )

OF  <Element    Subtype Indication>

See also:

<Array Type Definition>


Use Clause BNF Syntax (VHDL)
Use Clause

<Use Clause>  ::=

USE  <Selected Name>   {  ,  <Selected Name>   }  ;

See also:

<Block Configuration>

<Block Declarative Item>

<Configuration Declarative Item>

<Context Item>

<Entity Declarative Item>

<Package Body Declarative Item>

<Package Declarative Item>

<Process Declarative Item>

<Subprogram Declarative Item>


Variable Assignment Statement BNF Syntax (VHDL)
Variable Assignment Statement

<Variable Assignment Statement>  ::=

<Target>   :=  <Expression>   ;

See also:

<Sequential Statement>


Variable Declaration BNF Syntax (VHDL)
Variable Declaration

<Variable Declaration>  ::=

VARIABLE  <Identifier List>   :  <Subtype Indication>   [  :=  <Expression>   ]  ;

See also:

<Process Declarative Item>

<Subprogram Declarative Item>


Wait Statement BNF Syntax (VHDL)
Wait Statement

<Wait Statement>  ::=

WAIT  [  <Sensitivity Clause>   ]  [  <Condition Clause>   ]  [  <Timeout Clause>   ]  ;

See also:

<Sequential Statement>


Waveform BNF Syntax (VHDL)
Waveform

<Waveform>  ::=

<Waveform Element>   {  ,  <Waveform Element>   }

See also:

<Conditional Waveforms>

<Selected Waveforms>

<Signal Assignment Statement>


Waveform Element BNF Syntax (VHDL)
Waveform Element

<Waveform Element>  ::=

<Value    Expression>   [  AFTER  <Time    Expression>   ]

|  NULL  [  AFTER  <Time    Expression>   ]

See also:

Waveform


How to Use MAX+PLUS II VHDL

Copying Examples from Help

Inserting a VHDL Template

Compiling VHDL Design Files

Creating VHDL Output Files

MAX+PLUS II Packages

Arithmetic Operations & Types

Signed & Unsigned Types

Conversion Functions

Arithmetic & Comparison Operators

Combinatorial Logic

Concurrent Signal Assignment Statements

Simple Signal Assignments

Conditional Signal Assignments

Selected Signal Assignments

Process Statements

Sequential Logic

Implementing Registers

Implementing Counters

Implementing Latches

Implementing State Machines

Automatic State Assignments

Manual State Assignments

Hierarchical Projects

Primitives

Old-Style Macrofunctions

Using a MAX+PLUS II Logic Function

Implementing a User-Defined Megafunction or Macrofunction

See also:

Clique Assignments

Connected Pin Assignments

Device Assignments

Logic Option Assignments

Pin, Location & Chip Assignments

Probe Assignments

Timing Assignments


MAX+PLUS II Packages (VHDL)
MAX+PLUS II Packages

Altera provides several packages for use with MAX+PLUS II. All packages are located in subdirectories of the \maxplus2\max2vhdl directory (a subdirectory of the /usr directory on a UNIX workstation), which are created automatically during MAX+PLUS II installation. See the following table:

File:	Package:	Library:	Contents:

maxplus2.vhd	maxplus2	altera	MAX+PLUS II logic functions supported by VHDL.

std1164.vhd	std_logic_1164	ieee	Standard for describing interconnection data types for VHDL

std1164b.vhd	modeling, and the STD_LOGIC and STD_LOGIC_VECTOR types.

arith.vhd	std_logic_arith	ieee	SIGNED and UNSIGNED types, arithmetic and comparison

arithb.vhd	functions for use with SIGNED and UNSIGNED types, and the conversion

functions CONV_INTEGER, CONV_SIGNED, and CONV_UNSIGNED.

signed.vhd	std_logic_signed	ieee	Functions that allow MAX+PLUS II to use STD_LOGIC_VECTOR types as if they are

signedb.vhd	SIGNED types.

unsigned.vhd	std_logic_unsigned	ieee	Functions that allow MAX+PLUS II to use STD_LOGIC_VECTOR

unsignedb.vhd	types as if they are UNSIGNED types.

If you use more than one of these packages in a single VHDL Design File, you must use them in the order in which they are listed in this table.

In addition, Altera provides the std library with the standard and textio packages that are defined in the IEEE Standard VHDL Language Reference Manual. This library is located in the \maxplus2\max2vhdl\std directory (a subdirectory of the /usr directory on a UNIX workstation).

You can use custom design libraries in VHDL Design Files. See Compiling VHDL Design Files for more information.

See also:

Arithmetic Operations & Types

Hierarchical Projects


Arithmetic Operations & Types (VHDL)
Arithmetic Operations & Types

In VHDL, constants, signals, variables, functions, and parameters can be declared with a type that defines and restricts their characteristics. Each object can hold or return values of these types. Each type has a set of values and a set of operations. When objects are assigned to a type, they are restricted to the values and operations for that type.

Altera recommends using the following types:

STD_LOGIC and STD_LOGIC_VECTOR types. These types are defined in IEEE Std 1164-1993. A copy of the STD_LOGIC_1164 package, which includes these types, is provided in the ieee library in the \maxplus2\max2vhdl\ieee directory.

BIT and BIT_VECTOR types. These types are defined in IEEE Std 1076-1987. A copy of the standard package, which includes these types, is provided in the std library in the \maxplus2\max2vhdl\std directory.

SIGNED and UNSIGNED types. These types are provided in the std_logic_arith package in the ieee library in the \maxplus2\max2vhdl\ieee directory.

On UNIX workstations, the /maxplus2 directory is a subdirectory of the /usr directory.

See also:

Appendix A: Standard Language Package in Perry’s VHDL

Arithmetic & Comparison Operators

Chapter 4: Data Types in Perry’s VHDL

Conversion Functions

Section 3: Types in the IEEE Standard VHDL Language Reference Manual

Signed & Unsigned Types


SIGNED & UNSIGNED Types (VHDL)
SIGNED & UNSIGNED Types

SIGNED and UNSIGNED types are provided in the std_logic_arith package in the ieee library.

UNSIGNED types represent unsigned numerical values, which can be positive or zero only. The MAX+PLUS II Compiler interprets each UNSIGNED type as a binary number, with the digit on the left as the MSB. Example

SIGNED types represent signed numerical values, which can be positive, zero, or negative. The MAX+PLUS II Compiler interprets each SIGNED type as a two’s complement binary representation; the leftmost bit indicates whether the value is positive or negative. Example

See also:

Arithmetic & Comparison Operators

Conversion Functions

MAX+PLUS II Packages


Example: UNSIGNED type
UNSIGNED'("0110") represents +6

UNSIGNED'("1010") represents +10


Example: SIGNED type
SIGNED'("0110") represents +6

SIGNED'("1010") represents ­6


Conversion Functions (VHDL)
Conversion Functions

The std_logic_arith package in the ieee library includes three sets of functions to convert values between SIGNED and UNSIGNED types and the predefined type INTEGER.

Four versions of each function are available; the correct version for each function call is determined through operator overloading.

CONV_INTEGER--Converts a parameter of type INTEGER, UNSIGNED, SIGNED, or STD_ULOGIC to an INTEGER value. The size of operands in CONV_INTEGER functions are limited to the range ­2147483647 to 2147483647, i.e., to a 31-bit UNSIGNED value or a 32-bit SIGNED value.

CONV_UNSIGNED--Converts a parameter of type INTEGER, UNSIGNED, SIGNED, or STD_ULOGIC to an UNSIGNED value with SIZE bits.

CONV_SIGNED--Converts a parameter of type INTEGER, UNSIGNED, SIGNED, or STD_ULOGIC to a SIGNED value with SIZE bits.

Two operands are required for the CONV_UNSIGNED and CONV_SIGNED functions: the value to be converted and an integer that specifies the size of the converted value. If the value to be converted is smaller than the expected size, the value is extended as necessary.

The MAX+PLUS II Compiler adds zeros to the MSBs for UNSIGNED values and uses sign-extension for SIGNED values. The following example shows an 8-bit adder with UNSIGNED-type inputs and an INTEGER-type output.

LIBRARY ieee;

USE ieee.std_logic_1164.all;

USE ieee.std_logic_arith.all;

ENTITY adder IS

PORT (op1, op2	: IN UNSIGNED(7 downto 0);

   result	: OUT INTEGER);

END adder;

ARCHITECTURE maxpld OF adder IS

BEGIN

result <= CONV_INTEGER(op1 + op2);

END maxpld;

In this example, the ieee library is declared, and the std_logic_1164 and std_logic_arith packages are specified. The inputs are declared with type UNSIGNED, and the output is declared with type INTEGER.

In the architecture, op1 and op2, which are both of type UNSIGNED, are added together, converted to type INTEGER with the CONV_INTEGER conversion function, and assigned to result. If this assignment was made without using the CONV_INTEGER conversion function, the MAX+PLUS II Compiler would generate an error during processing.

See also:

Arithmetic & Comparison Operators

MAX+PLUS II Packages

SIGNED & UNSIGNED Types


Arithmetic & Comparison Operators (VHDL)
Arithmetic & Comparison Operators

The std_logic_arith package in the ieee library includes a number of arithmetic and comparison operators for use with SIGNED and UNSIGNED types. These operators are shown below:

Type:	Operator:	Examples:

Arithmetic	+	a + b, +a

-	a - b, -a

*	a * b

Comparison	<	a < b

<=	a <= b

>	a > b

>=	a >= b

=	a = b

/=	a /= b

Operands in arithmetic and comparison operations cannot have a greater width than the result. In arithmetic operations, one of the operands must have the same width as the result; the other is sign- or zero-extended. In comparison operations, the result has a single bit.

See also:

Conversion Functions

MAX+PLUS II Packages

SIGNED & UNSIGNED Types


Combinatorial Logic (VHDL)
Combinatorial Logic

Logic is combinatorial if outputs at a specified time are a function only of the inputs at that time. Examples of combinatorial logic functions are decoders, multiplexers, and adders.

Combinatorial logic is implemented in VHDL with Concurrent Signal Assignment Statements or with Process Statements that describe purely combinatorial behavior, i.e., behavior that does not depend on Clock edges.

Both Concurrent Signal Assignment and Process Statements should be placed in an Architecture Body, as shown below.

ARCHITECTURE a OF and_gate IS

BEGIN

<concurrent signal assignments>

<process statements>

<other concurrent statements>

END a;

This section includes the following topics:

Concurrent Signal Assignment Statements

-	Conditional Signal Assignments

-	Selected Signal Assignment Statements

-	Simple Signal Assignments

Process Statements


Concurrent Signal Assignment Statements (VHDL)
Concurrent Signal Assignment Statements

Concurrent Signal Assignment Statements assign values to signals, directing the MAX+PLUS II Compiler to create simple gates and logical connections. The following types of Concurrent Signal Assignment Statements are available:

Simple Signal Assignments

Conditional Signal Assignments

Selected Signal Assignments

See also:

Section 9.5: Concurrent Signal Assignment Statements in the IEEE Standard VHDL Language Reference Manual

Chapter 2: Behavior Modeling in Perry’s VHDL


Simple Signal Assignments (VHDL)
Simple Signal Assignments

The simple Signal Assignment Statements shown in the following example create an AND gate and connect two nodes, respectively. These statements are executed concurrently.

ENTITY simpsig IS

PORT

(

a, b, e	: IN BIT;

c, d	: OUT BIT

);

END simpsig;

ARCHITECTURE maxpld OF simpsig IS

BEGIN

c <= a AND b;	-- creates an AND gate

d <= e;	   -- connects two nodes

END maxpld;

In this example, the signal c receives the value of a AND b, and the signal d receives the value of e.

See also:

Concurrent Signal Assignment Statements

Conditional Signal Assignments

Selected Signal Assignments

Section 9.5: Concurrent Signal Assignment Statements in the IEEE Standard VHDL Language Reference Manual

Chapter 2: Behavior Modeling in Perry’s VHDL


Conditional Signal Assignments (VHDL)
Conditional Signal Assignments

Conditional Signal Assignment Statements list a series of expressions that are assigned to a target signal after the positive evaluation of one or more Boolean expressions. The following example shows a basic 2-to-1 multiplexer in which the value input0 is assigned to output when sel equals '0'; otherwise, the value input1 is assigned to output.

ENTITY condsig IS

PORT

(

input0, input1, sel	: IN BIT;

output	: OUT BIT

);

END condsig;

ARCHITECTURE maxpld OF condsig IS

BEGIN

output <= input0 WHEN sel = '0' ELSE input1;

END maxpld;

When a Conditional Signal Assignment Statement is executed, each Boolean expression is tested in the order in which it is written. The value of the expression preceding a WHEN keyword is assigned to the target signal for the first Boolean expression that is evaluated as true. If none of the Boolean expressions are true, the expression following the last ELSE keyword is assigned to the target. The following Conditional Signal Assignment Statement has multiple alternatives.

ENTITY condsigm IS

PORT

(

high, mid, low	: IN BIT;

q	: OUT INTEGER

);

END condsigm;

ARCHITECTURE maxpld OF condsigm IS

BEGIN

q <=	3 WHEN high = '1' ELSE	-- when high

2 WHEN mid  = '1' ELSE	-- when mid but not high

1 WHEN low  = '1' ELSE	-- when low but not mid or high

0;	-- when not low, mid, or high

END maxpld;

In this example:

3 is assigned to q when high is '1'

2 is assigned to q when mid is '1' but high is not '1'

1 is assigned to q when low is '1' but high and mid are not '1'

0 is assigned to q when high, mid, or low do not equal '1'

See also:

Concurrent Signal Assignment Statements

Selected Signal Assignments

Simple Signal Assignments

Section 9.5: Concurrent Signal Section 9.5: Concurrent Signal Assignment Statements in the IEEE Standard VHDL Language Reference Manual

Chapter 2: Behavior Modeling in Perry’s VHDL


Selected Signal Assignments (VHDL)
Selected Signal Assignments

Selected Signal Assignment Statements list alternatives that are available for each value of an expression, then select a course of action based on the value of the expression.

You can use Selected Signal Assignments to create multiplexers, as shown below.

ENTITY selsig IS

PORT

(

d0, d1, d2, d3	: IN BIT;

s	: IN INTEGER RANGE 0 TO 3;

output	: OUT BIT

);

END selsig;

ARCHITECTURE maxpld OF selsig IS

BEGIN

WITH s SELECT	-- creates a 4-to-1 multiplexer

output <=	d0 WHEN 0,

d1 WHEN 1,

d2 WHEN 2,

d3 WHEN 3;

END maxpld;

The select expression, which is located between the WITH and SELECT keywords, selects the signal that is to be assigned to the target signal. In this example, when the value of the s multiplexer select expression is 0, the multiplexer output d0 is assigned to the target signal output. When the value of s is 1, the output is d1; when s is 2, the output is d2; when s is 3, the output is d3.

The select signal can also be declared as an Enumeration Type, as shown below:

PACKAGE meals_pkg IS

TYPE MEAL IS (BREAKFAST, LUNCH, DINNER, MIDNIGHT_SNACK);

END meals_pkg;

USE work.meals_pkg.all;

ENTITY selsigen IS

PORT

(

previous_meal	: IN MEAL;

next_meal	: OUT MEAL

);

END selsigen;

ARCHITECTURE maxpld OF selsigen IS

BEGIN

WITH previous_meal	SELECT

next_meal <=	BREAKFAST 	WHEN DINNER | MIDNIGHT_SNACK,

LUNCH	 	WHEN BREAKFAST,

DINNER 	WHEN LUNCH;

END maxpld;

When the value of the previous_meal multiplexer select signal is equal to the constant DINNER or MIDNIGHT_SNACK, the multiplexer output is BREAKFAST. When previous_meal is BREAKFAST, the output is LUNCH. When previous_meal is LUNCH, the output is DINNER.

See also:

Concurrent Signal Assignment Statements

Conditional Signal Assignments

Simple Signal Assignments

9.5: Concurrent Signal Assignment Statements in the IEEE Standard VHDL Language Reference Manual

Chapter 2: Behavior Modeling in Perry’s VHDL


Process Statements (VHDL)
Process Statements

Process Statements include a set of sequential statements that assign values to signals. These statements allow you to perform step-by-step computations. Process Statements that describe purely combinatorial behavior can also be used to create combinatorial logic. To ensure that a process is combinatorial, its sensitivity list must contain all signals that are read in the process. A sensitivity list contains the signals that cause the Process Statements to execute if their values change.

You can use process Statements to create sequential logic. See Sequential Logic for more information.

The following example shows a Process Statement that counts the number of bits in signal d. Signal d is the only signal contained in the sensitivity list that follows the PROCESS keyword, i.e., the only signal to which the process is sensitive.

ENTITY proc IS

PORT

(

d	: IN BIT_VECTOR (2 DOWNTO 0);

q	: OUT INTEGER RANGE 0 TO 3

);

END proc;

ARCHITECTURE maxpld OF proc IS

BEGIN

PROCESS (d)   -- count the number of set bits with the value 1 in word d

    VARIABLE num_bits : INTEGER;

BEGIN

    num_bits := 0;

    FOR i IN d'RANGE LOOP

        IF d(i) = '1' THEN

            num_bits := num_bits + 1;

        END IF;

    END LOOP;

    q <= num_bits;

END PROCESS;

END maxpld;

In this example, d is declared as an array in the Entity Declaration. Every time through the FOR loop, i is set to the next value, and d(i) accesses information from the d array. If d(i) equals 1, the If Statement increments num_bits. The num_bits variable is then assigned to the signal q, which is also declared in the Entity Declaration.

See also:

Section 8.6: If Statement in the IEEE Standard VHDL Language Reference Manual

Section 8.8: Loop Statement in the IEEE Standard VHDL Language Reference Manual

Section 9.2: Process Statements in the IEEE Standard VHDL Language Reference Manual

"Process Statement" in Chapter 3: Sequential Processing in Perry’s VHDL


Sequential Logic (VHDL)
Sequential Logic

Logic is sequential if outputs at a specified time are a function of the inputs at that time and at all preceding times. All sequential circuits must include one or more registers. State machines are especially useful for implementing sequential logic. Other examples of sequential logic are counters, shift registers, and controllers.

Sequential logic is implemented in VHDL with Process Statements. These statements direct the MAX+PLUS II Compiler to create logic circuitry that is controlled by the Process Statement’s Clock signal.

This section includes the following topics:

Implementing Registers

Implementing Latches

Implementing State Machines

-	Automatic State Assignments

-	Manual State Assignments


Implementing Registers (VHDL)
Implementing Registers

A register is implemented implicitly with a Register Inference. Register Inferences in MAX+PLUS II VHDL support any combination of Clear, Preset, Clock Enable, and asynchronous Load signals. MAX+PLUS II can infer memory elements from the following VHDL statements, all of which are used within a Process Statement:

If Statements can be used to imply registers for signals and variables in the clauses of the If Statement.

Wait Statements can be used to imply registers in a synthesized circuit. The MAX+PLUS II Compiler creates flipflops for all signals and some variables that are assigned values in any process with a Wait Statement. If you use a Wait Statement, it must be listed at the beginning of the Process Statement.

During logic synthesis, the MAX+PLUS II Compiler automatically inserts an instance of the register and connects it as specified in the If and/or Wait Statement(s).

You can also implement registers explicitly with Component Instantiation Statements. For more information on Component Instantiations, see Hierarchical Projects.

Unlike Component Instantiations, Register Inferences are technology-independent. When registers are inferred, MAX+PLUS II can select them from the library you are currently using.

The following example shows four methods to infer registers that are controlled by a Clock and asynchronous Clear, Preset, and Load signals.

ENTITY reginf IS

PORT

(

d, clk, clr, pre, load, data	: IN BIT;

q1, q2, q3, q4, q5, q6, q7	: OUT BIT

);

END reginf;

ARCHITECTURE maxpld OF reginf IS

BEGIN

-- Register with active-high Clock

PROCESS

BEGIN

    WAIT UNTIL clk = '1';

    q1 <= d;

END PROCESS;

-- Register with active-low Clock

PROCESS

BEGIN

    WAIT UNTIL clk = '0';

    q2 <= d;

END PROCESS;

-- Register with active-high Clock & asynchronous Clear

PROCESS (clk, clr)

BEGIN

    IF clr = '1' THEN

        q3 <= '0';

    ELSIF clk'EVENT AND clk = '1' THEN

        q3 <= d;

    END IF;

END PROCESS;

-- Register with active-low Clock & asynchronous Clear

PROCESS (clk, clr)

BEGIN

    IF clr = '0' THEN

        q4 <= '0';

    ELSIF clk'EVENT AND clk = '0' THEN

        q4 <= d;

    END IF;

END PROCESS;

-- Register with active-high Clock & asynchronous Preset

PROCESS (clk, pre)

BEGIN

    IF pre = '1' THEN

        q5 <= '1';

    ELSIF clk'EVENT AND clk = '1' THEN

        q5 <= d;

    END IF;

END PROCESS;

-- Register with active-high Clock & asynchronous load

PROCESS (clk, load, data)

BEGIN

    IF load = '1' THEN

        q6 <= data;

    ELSIF clk'EVENT AND clk = '1' THEN

        q6 <= d;

    END IF;

END PROCESS;

-- Register with active-high Clock & asynchronous Clear &  Preset

PROCESS (clk, clr, pre)

BEGIN

    IF clr = '1' THEN

        q7 <= '0';

ELSIF pre = '1' THEN

q7 <= '1';

    ELSIF clk'EVENT AND clk = '1' THEN

        q7 <= d;

    END IF;

END PROCESS;

END maxpld;

In this example, all seven processes are sensitive only to changes on the control signals--i.e., clk, clr, pre, and load--and to changes on the data signal data.

The first two Process Statements use Wait Statements to detect changes on the clk signal. The first process waits for a rising edge on the clk signal (i.e., until clk = '1') and assigns the value d to the signal q1. The second process waits for a falling clk edge and assigns the value d to q2.

The rest of the Process Statements use an If Statement to give the asynchronous controls priority over the clk signal. This prioritization ensures that the asynchronous control signal is implemented as an asynchronous control of the D flipflop, rather than as logic connected to the D input of the flipflop.

The third and fourth Process Statements have sensitivity lists that detect changes in the clk and clr control signals and give the clr signal the higher priority. The circuit waits for an event on clk or clr, then sets q3 and q4 to '0' if clr is '1' or '0'. Otherwise, clk'EVENT and clk are evaluated to determine whether clk is rising or falling. When clk rises, the value of d is assigned to q3; when clk falls, the value of d is assigned to q4.

The fifth Process Statement is sensitive to clk and pre. The circuit waits for an event on clk or pre, then sets q5 to '1' if pre is '1'. Otherwise, clk'EVENT and clk are evaluated to determine whether clk is rising. When clk rises, the value of d is assigned to q5.

The sixth Process Statement is sensitive to clk , load, and data. The circuit waits for an event on any of these signals, then sets q6 to data if load is '1'. Otherwise, clk'EVENT and clk are evaluated to determine whether clk is rising. When clk rises, the value of d is assigned to q6.

The seventh Process Statement is sensitive to clk, clr, and pre. The circuit waits for an event on any of these signals, then sets q7 to '0' if clr is '1' and to '1' if pre is '1'. Otherwise, clk'EVENT and clk are evaluated to determine whether clk is rising. When clk rises, the value of d is assigned to q7.

See also:

Implementing Counters

Implementing Latches

Implementing State Machines

Process Statement

"Register Transfer-Level Description" in Chapter 9: Synthesis in Perry’s VHDL

Section 8.1: Wait Statement in the IEEE Standard VHDL Language Reference Manual

Section 8.6: If Statement in the IEEE Standard VHDL Language Reference Manual

Section 9.2: Process Statement in the IEEE Standard VHDL Language Reference Manual


Implementing Counters (VHDL)
Implementing Counters

Counters use sequential logic to count Clock pulses. A counter can be implemented implicitly with a Register Inference. MAX+PLUS II can infer a counter from an If Statement that specifies a Clock edge together with logic that adds or subtracts a value from the signal or variable. The If Statement and additional logic should be inside a Process Statement.

The following example shows a VHDL Design File that includes a variety of 8-bit counters, controlled by the clk, clear, ld, d, enable, and up_down signals, that are implemented with If Statements.

ENTITY counters IS

PORT

(

d	: IN 	INTEGER RANGE 0 TO 255;

clk	: IN  BIT;

clear	: IN  BIT;

ld	: IN  BIT;

enable	: IN  BIT;

up_down	: IN  BIT;

qa	: OUT INTEGER RANGE 0 TO 255;

qb	: OUT INTEGER RANGE 0 TO 255;

qc	: OUT INTEGER RANGE 0 TO 255;

qd	: OUT INTEGER RANGE 0 TO 255;

qe	: OUT INTEGER RANGE 0 TO 255;

qf	: OUT INTEGER RANGE 0 TO 255;

qg	: OUT INTEGER RANGE 0 TO 255;

qh	: OUT INTEGER RANGE 0 TO 255;

qi	: OUT INTEGER RANGE 0 TO 255;

qj	: OUT INTEGER RANGE 0 TO 255;

qk	: OUT INTEGER RANGE 0 TO 255;

ql	: OUT INTEGER RANGE 0 TO 255;

qm	: OUT INTEGER RANGE 0 TO 255;

qn	: OUT INTEGER RANGE 0 TO 255

);

END counters;

ARCHITECTURE a OF counters IS

BEGIN

-- An enable counter

PROCESS (clk)

VARIABLE	cnt	: INTEGER RANGE 0 TO 255;

BEGIN

IF (clk'EVENT AND clk = '1') THEN

IF enable = '1' THEN

cnt := cnt + 1;

END IF;

END IF;

qa	<= cnt;

END PROCESS;

-- A synchronous load counter

PROCESS (clk)

VARIABLE	cnt	: INTEGER RANGE 0 TO 255;

BEGIN

IF (clk'EVENT AND clk = '1') THEN

IF ld = '0' THEN

cnt := d;

ELSE

cnt := cnt + 1;

END IF;

END IF;

qb	<=	cnt;

END PROCESS;

-- A synchronous clear counter

PROCESS (clk)

VARIABLE	cnt	: INTEGER RANGE 0 TO 255;

BEGIN

IF (clk'EVENT AND clk = '1') THEN

IF clear = '0' THEN

cnt := 0;

ELSE

cnt := cnt + 1;

END IF;

END IF;

qc	<=	cnt;

END PROCESS;

-- An up/down counter

PROCESS (clk)

VARIABLE	cnt	: INTEGER RANGE 0 TO 255;

VARIABLE	direction 	: INTEGER;

BEGIN

IF (up_down = '1') THEN

direction := 1;

ELSE

direction := -1;

END IF;

IF (clk'EVENT AND clk = '1') THEN

cnt := cnt + direction;

END IF;

qd	<=	cnt;

END PROCESS;

-- A synchronous load enable counter

PROCESS (clk)

VARIABLE	cnt	: INTEGER RANGE 0 TO 255;

BEGIN

IF (clk'EVENT AND clk = '1') THEN

IF ld = '0' THEN

cnt := d;

ELSE

IF enable = '1' THEN

cnt := cnt + 1;

END IF;

END IF;

END IF;

qe	<=	cnt;

END PROCESS;

-- An enable up/down counter

PROCESS (clk)

VARIABLE	cnt	: INTEGER RANGE 0 TO 255;

VARIABLE	direction 	: INTEGER;

BEGIN

IF (up_down = '1') THEN

direction := 1;

ELSE

direction := -1;

END IF;

IF (clk'EVENT AND clk = '1') THEN

IF enable = '1' THEN

cnt := cnt + direction;

END IF;

END IF;

qf	<=	cnt;

END PROCESS;

-- A synchronous clear enable counter

PROCESS (clk)

VARIABLE	cnt	: INTEGER RANGE 0 TO 255;

BEGIN

IF (clk'EVENT AND clk = '1') THEN

IF clear = '0' THEN

cnt := 0;

ELSE

IF enable = '1' THEN

cnt := cnt + 1;

END IF;

END IF;

END IF;

qg	<=	cnt;

END PROCESS;

-- A synchronous load clear counter

PROCESS (clk)

VARIABLE	cnt	: INTEGER RANGE 0 TO 255;

BEGIN

IF (clk'EVENT AND clk = '1') THEN

IF clear = '0' THEN

cnt := 0;

ELSE

IF ld = '0' THEN

cnt := d;

ELSE

cnt := cnt + 1;

END IF;

END IF;

END IF;

qh	<=	cnt;

END PROCESS;

-- A synchronous load up/down counter

PROCESS (clk)

VARIABLE	cnt	: INTEGER RANGE 0 TO 255;

VARIABLE	direction 	: INTEGER;

BEGIN

IF (up_down = '1') THEN

direction := 1;

ELSE

direction := -1;

END IF;

IF (clk'EVENT AND clk = '1') THEN

IF ld = '0' THEN

cnt := d;

ELSE

cnt := cnt + direction;

END IF;

END IF;

qi	<=	cnt;

END PROCESS;

-- A synchronous load enable up/down counter

PROCESS (clk)

VARIABLE	cnt	: INTEGER RANGE 0 TO 255;

VARIABLE	direction 	: INTEGER;

BEGIN

IF (up_down = '1') THEN

direction := 1;

ELSE

direction := -1;

END IF;

IF (clk'EVENT AND clk = '1') THEN

IF ld = '0' THEN

cnt := d;

ELSE

IF enable = '1' THEN

cnt := cnt + direction;

END IF;

END IF;

END IF;

qj	<=	cnt;

END PROCESS;

-- A synchronous clear load enable counter

PROCESS (clk)

VARIABLE	cnt	: INTEGER RANGE 0 TO 255;

BEGIN

IF (clk'EVENT AND clk = '1') THEN

IF clear = '0' THEN

cnt := 0;

ELSE

IF ld = '0' THEN

cnt := d;

ELSE

IF enable = '1' THEN

cnt := cnt + 1;

END IF;

END IF;

END IF;

END IF;

qk	<=	cnt;

END PROCESS;

-- A synchronous clear up/down counter

PROCESS (clk)

VARIABLE	cnt	: INTEGER RANGE 0 TO 255;

VARIABLE	direction 	: INTEGER;

BEGIN

IF (up_down = '1') THEN

direction := 1;

ELSE

direction := -1;

END IF;

IF (clk'EVENT AND clk = '1') THEN

IF clear = '0' THEN

cnt := 0;

ELSE

cnt := cnt + direction;

END IF;

END IF;

ql	<=	cnt;

END PROCESS;

-- A synchronous clear enable up/down counter

PROCESS (clk)

VARIABLE	cnt	: INTEGER RANGE 0 TO 255;

VARIABLE	direction 	: INTEGER;

BEGIN

IF (up_down = '1') THEN

direction := 1;

ELSE

direction := -1;

END IF;

IF (clk'EVENT AND clk = '1') THEN

IF clear = '0' THEN

cnt := 0;

ELSE

IF enable = '1' THEN

cnt := cnt + direction;

END IF;

END IF;

END IF;

qm	<=	cnt;

END PROCESS;

-- A modulus 200 up counter

PROCESS (clk)

VARIABLE	cnt	: INTEGER RANGE 0 TO 255;

CONSTANT modulus	: INTEGER := 200;

BEGIN

IF (clk'EVENT AND clk = '1') THEN

IF cnt = modulus THEN;

cnt := 0;

ELSE

cnt := cnt + 1;

END IF;

END IF;

qn	<=	cnt;

END PROCESS;

END a;

In this example, all 14 processes are sensitive only to changes on the clk signal. All other control signals are synchronous.

The first Process Statement describes an enabled counter. An If Statement describes the Clock edge, and an additional embedded If Statement uses the enable signal to control counter operation. At each rising Clock edge, the cnt variable is incremented by 1 and assigned to itself if the enable signal is '1'.

Go to Implementing Registers for information on how to infer registers by specifying Clock edges with If Statements.

The next 12 counters are described in the same manner. An If Statement describes the Clock edge, and one or more embedded If Statement(s) use the enable, ld, d, clear, and up_down signals to control counter operation. The last counter uses the constant modulus declared in the process to control when the counter is reset to zero. At each Clock edge, the counter variable is cleared; loaded with the value d; or incremented or decremented by 1 then assigned to itself based on the value of the control signal(s).

See also:

Implementing Latches

Implementing Registers

Implementing State Machines

Process Statement

Section 8.6: If Statement in the IEEE Standard VHDL Language Reference Manual

Section 9.2: Process Statement in the IEEE Standard VHDL Language Reference Manual


Implementing Latches (VHDL)
Implementing Latches

A latch can be implemented implicitly with a Register Inference. MAX+PLUS II can infer a latch from If Statements that have not been completely specified. The If Statement should be inside a Process Statement.

The following example shows a VHDL Design File that includes a Process Statement with an If Statement that has not been completely specified.

ENTITY latchinf IS

PORT

(

enable, data	: IN BIT;

q	: OUT BIT

);

END latchinf;

ARCHITECTURE maxpld OF latchinf IS

BEGIN

latch :	PROCESS (enable, data)

BEGIN

IF (enable = '1') THEN

q <= data;

END IF;

END PROCESS latch;

END maxpld;

In this example, the circuit analyzes the value of the enable signal. If enable equals '1', the value data is assigned to q. If enable = '0', the circuit maintains its previous state, creating a latch.

See also:

Implementing Counters

Implementing Registers

Implementing State Machines

Process Statement

Section 8.6: If Statement in the IEEE Standard VHDL Language Reference Manual

Section 9.2: Process Statement in the IEEE Standard VHDL Language Reference Manual


Implementing State Machines (VHDL)
Implementing State Machines

A state machine is a sequential circuit that advances through a number of states. To describe a state machine in MAX+PLUS II VHDL, you can declare an Enumeration Type for the states, and use a Process Statement for the state register and the next-state logic.

The VHDL example shown below implements a 2-state state machine.

ENTITY state_machine IS

PORT(

clk	: IN	BIT;

input	: IN	BIT;

output	: OUT	BIT);

END state_machine;

ARCHITECTURE a OF state_machine IS

TYPE STATE_TYPE IS (s0, s1);

SIGNAL state	: STATE_TYPE;

BEGIN

PROCESS

BEGIN

WAIT UNTIL clk = '1';

CASE state IS

WHEN s0=>

state <= s1;

WHEN s1=>

IF input = '1' THEN

state <= s0;

ELSE

state <= s1;

END IF;

END CASE;

END PROCESS;

output <= '1' WHEN state = s1 ELSE '0';

END a;

This state machine includes a Process Statement that is activated on every positive edge of the clk control signal.

The signal state stores the current state of the state machine. The declaration of the type STATE_TYPE defines the states s0 and s1 for state_machine.

At start-up, the state machine is initialized to the first state in the Type Declaration. Otherwise, the Case Statement defines the transitions between the states, i.e., determines which state to enter on the next rising edge of clk.

The MAX+PLUS II Compiler’s VHDL Netlist Reader recognizes state machines and reports them as such in the State Machine Assignments Section of the Report File (.rpt) only if all of the following conditions are met:

The Process Statement that describes the state machine must be clocked, and contain a Wait Statement that is either explicit or implied by a sensitivity list.

The state machine behavior, i.e., the next-state logic, is defined with Case Statements at the top level.

All assignments to the signal or variable that represents the state machine are within the process.

No If Statement that is a function of the state variable can assign to the state variable. Case Statements should be used instead. Example

VHDL state machines that do not meet these conditions are converted into logic gates and registers that are not listed as state machines in the Report File (.rpt).

See also:

Automatic State Assignments

Implementing Counters

Implementing Latches

Implementing Registers

Manual State Assignments

Section 8.1: Wait Statement in the IEEE Standard VHDL Language Reference Manual

Section 8.6: If Statement in the IEEE Standard VHDL Language Reference Manual

Section 8.7: Case Statement in the IEEE Standard VHDL Language Reference Manual

Section 9.2: Process Statement in the IEEE Standard VHDL Language Reference Manual


Example: recognized and unrecognized state machines
Not recognized as a state machine:

IF state_machine = s0 THEN

state_machine <= s1;

ELSE

state_machine <= s2;

END IF;

Recognized as a state machine:

CASE state_machine IS

WHEN s0=>

state_machine <= s1;

WHEN OTHERS =>

state_machine <= s2;

END CASE;


Automatic State Assignments (VHDL)
Automatic State Assignments

You can declare an Enumeration Type for the states of a state machine. Enumeration Types--i.e., types whose values are all user-defined--are ordered by enumeration value. In general, the MAX+PLUS II Compiler automatically assigns the value 0 to the first state, the value 1 to the second state, the value 2 to the third state, and so on. In the example shown in Implementing State Machines, for example, the Compiler assigns the value 0 to s0 and the value 1 to s1.

See also:

Implementing Registers

Manual State Assignments

Section 3.1.1: Enumeration Types in IEEE Standard VHDL Language Reference Manual

"Enumerated Types" in Chapter 4: Data Types in Perry’s VHDL


Manual State Assignments (VHDL)
Manual State Assignments

You can override the MAX+PLUS II Compiler’s automatic state assignments and specify your own state assignments with the ENUM_ENCODING attribute. The ENUM_ENCODING attribute must follow the associated Type Declaration.

The ENUM_ENCODING attribute is MAX+PLUS II-specific, and may not be available with other VHDL tools.

In the following example, the ENUM_ENCODING attribute is defined and declared:

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY enumsmch IS

PORT

(

updown 	: IN STD_LOGIC;

clock 	: IN STD_LOGIC;

lsb 	: OUT STD_LOGIC;

msb 	: OUT STD_LOGIC

);

END enumsmch;

ARCHITECTURE firstenumsmch OF enumsmch IS

TYPE count_state is (zero, one, two, three);

ATTRIBUTE ENUM_ENCODING 	  	 	: STRING;

ATTRIBUTE ENUM_ENCODING OF count_state : TYPE IS "11 01 10 00";

SIGNAL present_state, next_state 	: count_state;

BEGIN

PROCESS (present_state, updown)

BEGIN

CASE present_state IS

WHEN zero =>

IF (updown = '0') THEN

next_state <= one;

lsb <= '0';

msb <= '0';

ELSE

next_state <= three;

lsb <= '1';

msb <= '1';

END IF;

WHEN one =>

IF (updown = '0') THEN

next_state <= two;

lsb <= '1';

msb <= '0';

ELSE

next_state <= zero;

lsb <= '0';

msb <= '0';

END IF;

WHEN two =>

IF (updown = '0') THEN

next_state <= three;

lsb <= '0';

msb <= '1';

ELSE

next_state <= one;

lsb <= '1';

msb <= '0';

END IF;

WHEN three =>

IF (updown = '0') THEN

next_state <= zero;

lsb <= '1';

msb <= '1';

ELSE

next_state <= two;

lsb <= '0';

msb <= '1';

END IF;

END CASE;

END PROCESS;

PROCESS

BEGIN

WAIT UNTIL clock'EVENT and clock = '1';

present_state <= next_state;

END PROCESS;

END firstenumsmch;

The ENUM_ENCODING attribute must be a STRING literal that contains a series of state assignments. These state assignments are the constant values that correspond to the state names in the Enumerated Type Declaration. In this example, the states are encoded with the following values:

zero 	= "11"

one	= "01"

two 	= "10"

three	= "00"

See also:

Automatic State Assignments

Implementing Registers

Implementing State Machines


Hierarchical Projects (VHDL)
Hierarchical Projects

VHDL Design Files can be combined with other VHDL Design Files, TDFs, GDFs, EDIF Input Files, and OrCAD Schematic Files into a hierarchical project at any level of the project hierarchy. In contrast, WDFs, ADFs, SMFs, and XNF Files can be used only at the lowest level of a project hierarchy, unless the entire project consists of a single WDF, ADF, SMF, or XNF File. Lower-level files in a project hierarchy can be Altera-provided or user-defined macrofunctions or megafunctions.

MAX+PLUS II provides primitives and bus and architecture-optimized macrofunctions and megafunctions. You can use Component Instantiation Statements to insert instances of any supported logic function. You can also use Register Inferences to implement registers.

1.	VHDL does not support parameterized logic functions.

2.	VHDL does not directly support logic functions or ports with names that are VHDL keywords or that begin with a number, e.g., 74-series macrofunctions. To use these functions, you must prefix the name with a_. For example, to use the 7480 macrofunction, you must specify a_7480 in your Component Instantiation Statement. MAX+PLUS II automatically removes the a_ prefix of any logic function or port name during processing. The a_ prefix is also omitted from the Report File (.rpt) generated during compilation.

In addition, to use any name that begins with a_, you must prefix the name with an additional a_ to preserve the original characters. For example, to use the name a_bcde, you must specify a_a_bcde.

See also:

Implementing a User-Defined Megafunction or Macrofunction

Megafunctions/LPM

Old-Style Macrofunctions

Primitives

Using a MAX+PLUS II Logic Function


Using a MAX+PLUS II Logic Function (VHDL)
Using a MAX+PLUS II Logic Function

In VHDL, you can use a Component Instantiation Statement to insert an instance of a MAX+PLUS II logic function. The Component Instantiation Statement also connects logic function ports to signals or interface ports of the associated entity/architecture pair. The ports of logic functions are defined with Component Declarations elsewhere in the file or in referenced packages.

Registers can also be implemented with Register Inferences. See Implementing Registers for more information.

In the following example, two Component Instantiation Statements are used to create an instance of a DFF primitive and a 74151b macrofunction.

LIBRARY altera;

USE altera.maxplus2.ALL;

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY compinst IS

PORT

(

data, clock, clearn, presetn	: IN STD_LOGIC;

q_out	: OUT STD_LOGIC;

a, b, c, gn	: IN STD_LOGIC;

d	 	: IN STD_LOGIC_VECTOR(7 DOWNTO 0);

y, wn	: OUT STD_LOGIC

);

END compinst;

ARCHITECTURE a OF compinst IS

BEGIN

dff1 : DFF PORT MAP (d =>data, q => q_out, clk => clock, clrn => clearn, prn => presetn);

mux	: a_74151b PORT MAP (c, b, a, d, gn, y, wn);

END a;

In this example, the library altera is declared as the resource library. The Use Clause specifies the maxplus2 package contained in the altera library.

A single instance of the DFF primitive is created with a Component Instantiation Statement. The values described in the Port Map Clause for each instance are mapped to the corresponding ports in the Component Instantiation Statement for the DFF primitive in the maxplus2 package. The ports of the dff1 primitive instance are connected by name, i.e., ports are mapped directly to signals regardless of the order in which they are listed. The d port of dff1 is mapped to data, q to q_out, clk to clock, clrn to clearn, and prn to presetn.

A Component Instantiation Statement is also used to create a single instance of the 74151b macrofunction. The ports in 74151b are associated by position, i.e., the first port in 74151b is mapped to c, the second port to b, etc.

See also:

"Component Instantiation" in Chapter 1: Introduction to VHDL in Perry’s VHDL

Hierarchical Projects

Implementing a User-Defined Megafunction or Macrofunction

Megafunctions/LPM

Old-Style Macrofunctions

Primitives

Section 9.6: Component Instantiation Statement in the IEEE Standard VHDL Language Reference Manual


Implementing a User-Defined Megafunction or Macrofunction (VHDL)
Implementing a User-Defined Megafunction or Macrofunction

You can implement a user-defined megafunction or macrofunction in VHDL with one of the following methods:

Declare a package for each project that contains Component Declarations for all lower-level entities--in the top-level design file. This method is described here.

Declare a component in the architecture in which it is instantiated. This method is described in "Schematics vs. Architectures" in Chapter 1: Introduction to VHDL in Perry’s VHDL.

The following example shows reg12.vhd, a 12-bit register that will be instantiated in a VHDL Design File that is higher in the project hierarchy. This register has an Entity Declaration and an Architecture Body for the user-defined macrofunction reg12.

ENTITY reg12 IS

PORT(

d	: IN  BIT_VECTOR(11 DOWNTO 0);

clk	: IN  BIT;

q	: OUT BIT_VECTOR(11 DOWNTO 0));

END reg12;

ARCHITECTURE a OF reg12 IS

BEGIN

PROCESS

BEGIN

WAIT UNTIL clk = '1';

q <= d;

END PROCESS;

END a;

The following example shows reg24.vhd, a VHDL Design File that declares reg24_package, identifies it with a Use Clause, then uses the reg12 component without requiring an additional Component Declaration.

PACKAGE reg24_package IS

COMPONENT reg12

PORT(

d	: IN	BIT_VECTOR(11 DOWNTO 0);

clk	: IN	BIT;

q	: OUT	BIT_VECTOR(11 DOWNTO 0));

END COMPONENT;

END reg24_package;

LIBRARY work;

USE work.reg24_package.ALL;

ENTITY reg24 IS

PORT(

d	: IN  BIT_VECTOR(23 DOWNTO 0);

clk	: IN  BIT;

q	: OUT BIT_VECTOR(23 DOWNTO 0));

END reg24;

ARCHITECTURE a OF reg24 IS

BEGIN

reg12a	: reg12 PORT MAP (d => d(11 DOWNTO 0), clk => clk,

  q => q(11 DOWNTO 0));

reg12b	: reg12 PORT MAP (d => d(23 DOWNTO 12), clk => clk,

  q => q(23 DOWNTO 12));

END a;

When instantiating user-defined megafunctions or macrofunctions, you must specify the ports of the function with a Component Declaration. In contrast, Component Declarations for MAX+PLUS II logic functions are provided in the maxplus2 package in the altera library.

 In this example, the ports for reg12 are listed in a Component Declaration in the reg24_package at the beginning of the file. The work library is declared with a Library Clause, and reg24_package in the work library is specified with a Use Clause. The Architecture Body for reg24 contains two instances of reg12.

1.	All VHDL design libraries must be compiled. In MAX+PLUS II, you can compile a library with the Project Save & Compile command (File menu) in any MAX+PLUS II application, or with the Start button in the MAX+PLUS II Compiler window. In addition, you can specify custom design libraries for the current project with VHDL Netlist Reader Settings (Interfaces menu), as described in Compiling VHDL Design Files.

2.	Although a Library Clause is not necessary for a library named work, Altera recommends that your VHDL Design File contain one Library Clause for each Use Clause.

See also:

"Component Instantiation" in Chapter 1: Introduction to VHDL in Perry’s VHDL

Hierarchical Projects

Megafunctions/LPM

Old-Style Macrofunctions

Primitives

Section 9.6: Component Instantiation Statement in the IEEE Standard VHDL Language Reference Manual

Using a MAX+PLUS II Logic Function


********************** BEGINNING OF NON-TRANSLATED TEXT *********************************

The following messages are documented elsewhere:

Handle:	File:

fvhd_cant_create_symbol	glmess

evhd_node_missing_source	comess

evhd_syntax_error	glmess

evhd_vce_cantopenfile	glmess

fvhd_az_fe_cantsave	glmess

fvhd_az_na_cantopenstandard	glmess

fvhd_az_na_outofmemory	glmess

*****************************  END OF NON-TRANSLATED TEXT *********************************


Error: <text>

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	Refer to the IEEE Standard VHDL Language Reference Manual and Perry’s VHDL book for information on creating designs with VHDL.

If you receive this message, please call Altera Applications.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Warning: <text>

CAUSE:	Your VHDL Design File contains a potential problem. The text of the message describes the source of the warning.

ACTION:	Refer to the IEEE Standard VHDL Language Reference Manual and Perry’s VHDL book for information on creating designs with VHDL.

If you receive this message, please call Altera Applications.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Info: <text>

CAUSE:	The MAX+PLUS II Compiler has performed a task during project compilation.

ACTION:	No action is required. Refer to the IEEE Standard VHDL Language Reference Manual and Perry’s VHDL book for information on creating designs with VHDL.

If you receive this message, please call Altera Applications.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Compiling package <name>

CAUSE:	MAX+PLUS II is compiling a VHDL Design File that contains a package.

ACTION:	No action is required.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Duplicate pin name <text>

CAUSE:	The specified pin name is assigned to more than one pin in your VHDL Design File.

ACTION:	Edit your VHDL Design File to correct the errors and recompile the design. Refer to the IEEE Standard VHDL Language Reference Manual and Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Duplicate state name <name>

CAUSE:	The specified state name is assigned to more than one state in your VHDL Design File. This error can occur if the design contains multiple state machines of the same enumeration type, or if multiple state machines of different enumeration types have common enumeration type names.

ACTION:	Edit your VHDL Design File to correct the errors and recompile the design. Refer to Section(s) 3.1, 3.1.1, and 3.1.1.1 of the IEEE Standard VHDL Language Reference Manual for information on enumeration types. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


ELSE clause following Clock edge must contain hold the state of signal <name>
ELSE clause following Clock edge must hold the state of signal <name>

CAUSE:	Your VHDL Design File contains an ELSE clause in an If Statement that implements a Clock edge, but the specified signal does not maintain a stable state. The ELSE clause must hold the signal at the same value when there is no Clock edge.

ACTION:	Edit your VHDL Design File to correct the errors and recompile the design. Refer to the IEEE Standard VHDL Language Reference Manual and Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Entity <name> does not have an Architecture Body

CAUSE:	Your VHDL Design File contains an Entity Declaration, but no corresponding Architecture Body. MAX+PLUS II requires the Entity Declaration and the Architecture Body to be in the same file.

ACTION:	Edit your VHDL Design File to correct the errors and recompile the design. Refer to the IEEE Standard VHDL Language Reference Manual and Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Errors in <name> prevent further processing

CAUSE:	Your VHDL Design File contains errors that prevent MAX+PLUS II from continuing the current compilation.

ACTION:	Edit your VHDL Design File to correct the errors and recompile the design. Refer to the IEEE Standard VHDL Language Reference Manual and Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


File <name> does not contain an Architecture Body. Stopping Compilation.

CAUSE:	Your VHDL Design File does not contain an Architecture Body. All VHDL Design Files must contain an Architecture Body, unless it contains only packages.

ACTION:	If you are compiling a file that contains only packages, no action is required. Otherwise, edit your VHDL Design File to correct the errors and recompile the design. Refer to the IEEE Standard VHDL Language Reference Manual and Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


File <name> does not contain an Architecture Body. No <text> created.

CAUSE:	You tried to create a symbol with the Create Default Symbol command or to create an Include File with the Create Default Include File command in the Text Editor, but your VHDL Design File does not contain an Architecture Body.

ACTION:	Make sure your VHDL Design File contains one or more Architecture Bodies and try again. Refer to the IEEE Standard VHDL Language Reference Manual and Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Flipflops must be implemented with If Statements

CAUSE:	Your VHDL Design File generates a Clock edge with a statement that is not an If Statement. You can only implement flipflops with If Statements.

ACTION:	Edit your VHDL Design File to correct the errors and recompile the design. Refer to the IEEE Standard VHDL Language Reference Manual and Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Found multiple assignments to the same signal or signal bit <name> in a Process Statement etc.
Found multiple assignments to the same signal or signal bit <name> in a Process Statement -- only the last assignment will take effect

CAUSE:	Multiple assignments exist for a signal in a Process Statement in a VHDL Design File. Only the last assignment will be used; all others will be ignored.

ACTION:	Edit your VHDL Design File to remove the unused assignments or change the logic of the Process Statement so that values are assigned correctly in all cases. Refer to the IEEE Standard VHDL Language Reference Manual and Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


High-impedence (Z) value(s) of constant (text> can’t be processed as tri-state buffer(s)
High-impedance (Z) value(s) of constant <text> can't be processed as tri-state buffer(s)

CAUSE:	Your VHDL Design File contains a signal or variable assignment with a high-impedance (Z) value that cannot be interpreted by MAX+PLUS II. You may have If or Case Statements that are too complex, or you may have made a high-impedance assignment based on a Clock edge.

ACTION:	Simplify your VHDL Design File to separate the high-impedance assignment from other complex logic and recompile the design. Refer to the IEEE Standard VHDL Language Reference Manual and Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Ignored attribute <text>

CAUSE:	The ENUM_ENCODING attribute definition in your VHDL Design File has been ignored. This attribute can only be applied to Type Definitions.

ACTION:	Refer to Manual State Assignments for more information on the ENUM_ENCODING attribute. Refer to Section(s) 3.1of the IEEE Standard VHDL Language Reference Manual for information on types. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


More than one If and/or Case Statements in a process assign values to signal <name>

CAUSE:	More than one If and/or Case Statement in a single process assigns value to a signal. This feature is not yet supported in MAX+PLUS II VHDL Design Files.

ACTION:	Edit your VHDL Design File so that it uses nested If Statements to implement the signal assignment and recompile the design. Refer to the IEEE Standard VHDL Language Reference Manual and Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Only one <text> signal can be defined for a flipflop

CAUSE:	Your VHDL Design File contains two or more Clear, Preset, Clock Enable, or asynchronous load signals for a single flipflop.

ACTION:	Edit your VHDL Design File to correct the errors and recompile the design. Refer to the IEEE Standard VHDL Language Reference Manual and Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Port <name> declared as an <text> when it should be an <text>

CAUSE:	You redefined a MAX+PLUS II primitive in a VHDL Design File, but declared an output port of the primitive as an input in the Component Declaration.

ACTION:	Although you may redefine the order of signals in primitives, you must declare the outputs as outputs and the inputs as inputs. Make the necessary changes in the Component Declaration for the primitive.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format

Using a MAX+PLUS II Logic Function


Port <name> is not of the correct width for <text> primitive

CAUSE:	Your VHDL Design File contains an error. You used a Component Instantiation Statement to implement a MAX+PLUS II primitive, but you specified a port with a different width.

ACTION:	Ensure that the width you specify in the Component Instantiation matches the width of the primitive signals. See the IEEE Standard VHDL Language Reference Manual and Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format

Using a MAX+PLUS II Logic Function


Process clocking is too complex.

CAUSE:	Your Process Statement is too complex. If your Process Statement has a Reset signal, it must have an If Statement only. If your Process Statement includes a Wait Statement, it must be the first statement in the process. You cannot have more than one Wait Statement in a process.

ACTION:	Edit your VHDL Design File to correct the errors and recompile the design.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Relational expression with meta-logic is evaluated to FALSE

CAUSE:	Your VHDL Design File contains a comparison to meta-logic values (e.g., to X, H, L, Z, -, W, or U). Since only values of 0 or 1 are considered during synthesis, the expression has been evaluated to False.

ACTION:	If necessary, edit your VHDL Design File to correct the logic and recompile the design. Refer to Section(s) 7.2.2 of the IEEE Standard VHDL Language Reference Manual for information on relational operators. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Right operand of <name> operator must be a power of 2

CAUSE:	You used a multiply (*), divide (/), remainder (REM), or Modulus (MOD) operator with a right operand that is not a integral power of 2.

ACTION:	Change the operand so that it is an integral power of 2. The MAX+PLUS II implementation of VHDL supports these operations only when they reduce to bit-wise shift operations.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Signal <name> has multiple sources

CAUSE:	Your VHDL Design File includes two sources attached to one signal. MAX+PLUS II only allows a single source for each signal.

ACTION:	Edit the file so that each signal is driven by a single source.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Signal <name> was <text> extended

CAUSE:	Your VHDL Design File contains a signal that was extended to match the expected size. The MAX+PLUS II Compiler adds zeros to the MSBs for UNSIGNED values and uses sign-extension for SIGNED values.

ACTION:	Verify that the Compiler interpreted your design as intended.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Signal is driven by illegal value -- Asynchronous Control for DFF is initializing etc.
Signal is driven by illegal value -- Asynchronous Control for DFF is initializing the DFF to a value other than logic '0' or logic '1'

CAUSE:	The specified value is illegal for the signal in your VHDL Design File.

ACTION:	Edit your VHDL Design File to use a legal signal value and recompile the design. Refer to the IEEE Standard VHDL Language Reference Manual and Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Suggested correction: <text>

CAUSE:	The MAX+PLUS II Compiler has found a syntax error and is attempting to continue processing as if you have entered the correction into your VHDL Design File.

ACTION:	If the suggested correction is appropriate, enter it into your VHDL Design File. If it is not appropriate, check the surrounding syntax, look for other errors, and enter any necessary corrections.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Symbolic name <name> is not a port of <name>

CAUSE:	You used a symbolic name in a VHDL Design File as a port of a primitive, macrofunction, megafunction, or state machine, but the port does not exist. You may have used an incorrect pinstub name.

ACTION:	Change the name of the port.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format

Using a MAX+PLUS II Logic Function


Unsupported feature: Combinatorial feedback exists inside a Process Statement. Signal(s)/variable(s): <name(s)>

CAUSE:	A Process Statement infers a latch or other combinatorial feedback. The signals and/or variables listed in the message are being fed back.

ACTION:	If you are inferring a latch, use the following Conditional Signal Assignment Statement instead of using a Process Statement:

q <= d WHEN ena = '1' ELSE q;

Alternatively, place the output of the latch in the sensitivity list of the Process Statement and use an Else Clause in the If Statement to assign the output under all input conditions.

IF ena = '1' THEN

q <= d;

ELSE

q <= q;

END IF;

If you are trying to create combinatorial feedback, you can use either of these methods.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Unknown problem in file <name> <text>

CAUSE:	Your VHDL Design File contains syntax or semantic errors that cannot be identified by MAX+PLUS II.

ACTION:	Quit and restart MAX+PLUS II and recompile the file. If this error appears again, delete the .dls files in the current project directory and recompile. You can also isolate the problem by commenting out or removing portions of the VHDL Design File until it compiles successfully.

Call Altera Applications for further assistance. Refer to the IEEE Standard VHDL Language Reference Manual and Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


VHDL Design File <name> must contain entity of the same name

CAUSE:	Your VHDL Design File contains an error. It must contain an entity name that has the same name as the filename.

ACTION:	Change the name of the entity. See the IEEE Standard VHDL Language Reference Manual and Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Width of asynchronous control signals must be a single bit
Width of flipflop control signals must be a single bit

CAUSE:	Your VHDL Design File contains an flipflop control signal that is wider than one bit.

ACTION:	Edit your VHDL Design File to correct the errors and recompile the design. Refer to the IEEE Standard VHDL Language Reference Manual and Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Width of [logical] operand <name> <text> width of result

CAUSE:	Your VHDL Design File contains an error. The width of an operand is greater than the width of the result in an arithmetic operation, or the width of one or more of the inputs in a logical operation differs from the width of its output.

ACTION:	In an arithmetic operation, you must ensure that the size of the result is equal to or greater than the size of the operand. In a logical operation, you must ensure that the widths of all inputs are equal to the width of the output. See the IEEE Standard VHDL Language Reference Manual and Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Undefined (X) values of constant <value> are interpreted as 0

CAUSE:	You have an undefined (X) value in your VHDL Design File. Undefined values are allowed for simulation purposes, but are not supported by MAX+PLUS II. During compilation, all undefined values are changed to 0.

ACTION:	No action is required. If you don’t want undefined values converted to 0, define all values.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Unsupported feature: <text>

CAUSE:	Your VHDL Design File contains an error. Furthermore, the error occurs in a portion of the file that uses a VHDL statement or section that is not supported by MAX+PLUS II. The text of the message describes the source of the error.

ACTION:	Refer to MAX+PLUS II VHDL Support for information on the VHDL statements and sections that are supported by MAX+PLUS II. For information on how to use VHDL, refer to the IEEE Standard VHDL Language Reference Manual and Perry’s VHDL book.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


********************** BEGINNING OF NON-TRANSLATED TEXT *********************************

The remaining messages in this file are CLSI messages.

The next set of messages (up to to the next comment page) have different wordings for each CAUSE and ACTION paragraph.

***************************** END OF NON-TRANSLATED TEXT *********************************


Analysis order error: Primary unit <name> in library <name> is out of date and must be reanalyzed

CAUSE:	Your VHDL Design File contains an error. You used an entity or package that has not been compiled.

ACTION:	Compile the entity or package, then recompile the VHDL Design File. Refer to Section(s) 11.2 and 11.1 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Any previous unit in this file that depends on this unit is now out of date

CAUSE:	Your VHDL Design File contains a potential problem. A package in this file has been defined twice.

ACTION:	Remove one of the package definitions and recompile the design. You can also refer to Section(s) 11.1 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Attribute <name> must <text>

CAUSE:	The ENUM_ENCODING attribute definition in your VHDL Design File has not been properly used. This attribute can only be applied to Type Definitions.

ACTION:	Refer to Manual State Assignments for more information on the ENUM_ENCODING attribute. Refer to Section(s) 3.1of the IEEE Standard VHDL Language Reference Manual for information on types. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Bad encoding string <text>

CAUSE:	The ENUM_ENCODING attribute definition in your VHDL Design File contains an error.

ACTION:	Refer to Manual State Assignments for more information on the ENUM_ENCODING attribute.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Can't continue -- one or more library logical names have no translation

CAUSE:	Your VHDL Design File specifies a package that does not exist, or specifies a library other than std, ieee, altera, or work. You cannot use a library other than std, ieee, altera, or work. This message usually appears in conjunction with other messages that describe the problem and/or its effects.

ACTION:	Make sure the Library Clause only refers to the std, ieee, altera, or work libraries and that the package you specify exists. If your Library Statement refers to one or more of these libraries, reinstall MAX+PLUS II VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Can't find STANDARD package

CAUSE:	MAX+PLUS II could not find the standard package in the std library. This library is automatically copied to the \maxplus2\max2vhdl\std directory during installation. MAX+PLUS II needs the standard package to compile any VHDL Design File.

ACTION:	Reinstall MAX+PLUS II VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Can't find STD library

CAUSE:	MAX+PLUS II could not find the the std library. This library is automatically created in the the \maxplus2\max2vhdl directory during installation.

ACTION:	Reinstall MAX+PLUS II VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Ignored construct: <text>

CAUSE:	An Assertion Statement or a file operation that you specified in the VHDL Design File has been ignored. These constructs cannot be synthesized by the MAX+PLUS II Compiler.

ACTION:	No action is required.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Interpreting as <text>

CAUSE:	Your VHDL Design File contains a construct that is being interpreted for logic synthesis. For example, your VHDL Design File contains a port of mode BUFFER that is being interpreted as an OUT port. Or, it contains an enumeration type that is interpreted as a single bit rather than a multi-value enumeration type.

ACTION:	If this interpretation is correct, no action is required. If this interpretation is not correct, edit the VHDL Design File.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format

Types (VHDL)


Name <name> is <text>

CAUSE:	Your VHDL Design File contains an error. You have tried to apply the ENUM_ENCODING attribute to a construct that is not a Type Declaration.

ACTION:	Fix the error. ENUM_ENCODING attributes can only be applied to Type Declarations. Refer to Manual State Assignments for more information on the ENUM_ENCODING attribute.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Output file name is too long and will be truncated

CAUSE:	Your VHDL Design File contains a potential problem. An output filename has more than 226 characters.

ACTION:	Make sure the names of all entities and architectures contain less that 226 characters.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


********************** BEGINNING OF NON-TRANSLATED TEXT *********************************

The remaining messages in this file are CLSI messages. All cause and action text was automatically generated with variables substituted in for the IEEE section numbers.

The next set of messages (up to to the next comment page) have an ACTION wording that startes with "Refer to MAX+PLUS II VHDL Support for information..."

***************************** END OF NON-TRANSLATED TEXT *********************************


Array error: Variable index range greater than the range specified by the corresponding array index subtype

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error. The array is being addressed by a variable index whose range is greater than the range of the array.

ACTION:	Change the index range to be equal to the array range. For example, if the array range is 14 and the index range is 25, change this index range to 14. As a starting point, refer to Section(s) 3 and 3.2.1.1 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Configuration Specification error: Generic map or port map in binding indication does not imply a design entity

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error, which may occur for a VHDL feature that is not fully supported in MAX+PLUS II.

ACTION:	Refer to MAX+PLUS II VHDL Support for information on which VHDL features are supported in MAX+PLUS II. You may then wish to refer to Section(s) 5.2.1.2 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Configuration Specification error: "Open" can only be used as the actual of a port or a generic map

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error, which may occur for a VHDL feature that is not fully supported in MAX+PLUS II.

ACTION:	Refer to MAX+PLUS II VHDL Support for information on which VHDL features are supported in MAX+PLUS II. You may then wish to refer to Section(s) 5.2.1.2 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Generic declarations must be constants (generics are supported only in scalar type and subtype declarations in MAX+PLUS II)

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error, which may occur for a VHDL feature that is not fully supported in MAX+PLUS II.

ACTION:	Refer to MAX+PLUS II VHDL Support for information on which VHDL features are supported in MAX+PLUS II. You may then wish to refer to Section(s) 1.1.1, 1.1.1.1, 4.3.1.1, and 4.3.3.1 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Range error: Index constraints applied to array type that is not an array type or to an unsupported access type
Range error: Index constraints are applied to an array type whose designated type is not an array type or to an unsupported access type

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error, which may occur for a VHDL feature that is not fully supported in MAX+PLUS II.

ACTION:	Refer to MAX+PLUS II VHDL Support for information on which VHDL features are supported in MAX+PLUS II. You may then wish to refer to Section(s) 3.2.1 and 3.3 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Range error: Only one range bound is of integer type or range bound has an unsupported floating point type

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error, which may occur for a VHDL feature that is not fully supported in MAX+PLUS II.

ACTION:	Refer to MAX+PLUS II VHDL Support for information on which VHDL features are supported in MAX+PLUS II. You may then wish to refer to Section(s) 3.1 and 3.1.4 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Range error: Range bounds defining this type must be locally static

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error, which may occur for a VHDL feature that is not fully supported in MAX+PLUS II.

ACTION:	Refer to MAX+PLUS II VHDL Support for information on which VHDL features are supported in MAX+PLUS II. You may then wish to refer to Section(s) 3.1.2 and 3.2.1.1 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Range error: Type bounds are not all of an integer type or type bounds have an unsupported floating-point type

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error, which may occur for a VHDL feature that is not fully supported in MAX+PLUS II.

ACTION:	Refer to MAX+PLUS II VHDL Support for information on which VHDL features are supported in MAX+PLUS II. You may then wish to refer to Section(s) 3.1 and 3.1.4 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Resolution Function error: Can't constrain the parameter of a Resolution Function
Resolution Function error: Can't constrain the parameter of a Resolution Function (Resolution Functions can only describe wired-OR, wired-AND, or tri-state behavior in MAX+PLUS II)

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error, which may occur for a VHDL feature that is not fully supported in MAX+PLUS II.

ACTION:	Refer to MAX+PLUS II VHDL Support for information on which VHDL features are supported in MAX+PLUS II. You may then wish to refer to Section(s) 2 and 3.2.1 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


********************** BEGINNING OF NON-TRANSLATED TEXT *********************************

The remaining messages in this file are CLSI messages. All cause and action text was automatically generated with variables substituted in for the IEEE section numbers.

The next set of messages (up to to the next comment page) have an ACTION wording that startes with "Edit your project to remove..."

***************************** END OF NON-TRANSLATED TEXT *********************************


Aggregate error: A non-locally static OTHERS must be the only formal in the aggregate

CAUSE:	Your VHDL Design File contains a construct that not is supported in MAX+PLUS II. This construct may also contain an error that is described in the text of the message.

ACTION:	Edit your project to remove the source of the error. Refer to MAX+PLUS II VHDL Support for information on which VHDL features are supported in MAX+PLUS II. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Aggregate error: Choice OTHERS can’t appear in an aggregate of Unconstrained Array type
Aggregate error: Choice OTHERS can't appear in an aggregate of Unconstrained Array type

CAUSE:	Your VHDL Design File contains a construct that not is supported in MAX+PLUS II. This construct may also contain an error that is described in the text of the message.

ACTION:	Edit your project to remove the source of the error. Refer to MAX+PLUS II VHDL Support for information on which VHDL features are supported in MAX+PLUS II. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Aggregate error: Element associations in Array aggregates must be all named or all positional

CAUSE:	Your VHDL Design File contains a construct that not is supported in MAX+PLUS II. This construct may also contain an error that is described in the text of the message.

ACTION:	Edit your project to remove the source of the error. Refer to MAX+PLUS II VHDL Support for information on which VHDL features are supported in MAX+PLUS II. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Aggregate error: Elements associated by an OTHERS association in a Record aggregate must all have the same type

CAUSE:	Your VHDL Design File contains a construct that not is supported in MAX+PLUS II. This construct may also contain an error that is described in the text of the message.

ACTION:	Edit your project to remove the source of the error. Refer to MAX+PLUS II VHDL Support for information on which VHDL features are supported in MAX+PLUS II. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Aggregate error: No associations may follow an OTHERS association

CAUSE:	Your VHDL Design File contains a construct that not is supported in MAX+PLUS II. This construct may also contain an error that is described in the text of the message.

ACTION:	Edit your project to remove the source of the error. Refer to MAX+PLUS II VHDL Support for information on which VHDL features are supported in MAX+PLUS II. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Aggregate error: Null range or non-locally static choice must be the only choice in the aggregate

CAUSE:	Your VHDL Design File contains a construct that not is supported in MAX+PLUS II. This construct may also contain an error that is described in the text of the message.

ACTION:	Edit your project to remove the source of the error. Refer to MAX+PLUS II VHDL Support for information on which VHDL features are supported in MAX+PLUS II. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Aggregate error: Only one OTHERS association is allowed per aggregate

CAUSE:	Your VHDL Design File contains a construct that not is supported in MAX+PLUS II. This construct may also contain an error that is described in the text of the message.

ACTION:	Edit your project to remove the source of the error. Refer to MAX+PLUS II VHDL Support for information on which VHDL features are supported in MAX+PLUS II. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Aggregate error: OTHERS associations in Record aggregates must associate at least one element

CAUSE:	Your VHDL Design File contains a construct that not is supported in MAX+PLUS II. This construct may also contain an error that is described in the text of the message.

ACTION:	Edit your project to remove the source of the error. Refer to MAX+PLUS II VHDL Support for information on which VHDL features are supported in MAX+PLUS II. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Aggregate error: Type of this aggregate must be Array or Record

CAUSE:	Your VHDL Design File contains a construct that not is supported in MAX+PLUS II. This construct may also contain an error that is described in the text of the message.

ACTION:	Edit your project to remove the source of the error. Refer to MAX+PLUS II VHDL Support for information on which VHDL features are supported in MAX+PLUS II. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Allocator requires either a subtype indication or a Qualified Expression

CAUSE:	Your VHDL Design File contains a construct that not is supported in MAX+PLUS II. This construct may also contain an error that is described in the text of the message.

ACTION:	Edit your project to remove the source of the error. Refer to MAX+PLUS II VHDL Support for information on which VHDL features are supported in MAX+PLUS II. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Block Statement error: Implicit signal GUARD must not have a source

CAUSE:	Your VHDL Design File contains a construct that not is supported in MAX+PLUS II. This construct may also contain an error that is described in the text of the message.

ACTION:	Edit your project to remove the source of the error. Refer to MAX+PLUS II VHDL Support for information on which VHDL features are supported in MAX+PLUS II. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Block Statement error: No signal called "GUARD" exists

CAUSE:	Your VHDL Design File contains a construct that not is supported in MAX+PLUS II. This construct may also contain an error that is described in the text of the message.

ACTION:	Edit your project to remove the source of the error. Refer to MAX+PLUS II VHDL Support for information on which VHDL features are supported in MAX+PLUS II. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Can't apply a range constraint to an access type

CAUSE:	Your VHDL Design File contains a construct that not is supported in MAX+PLUS II. This construct may also contain an error that is described in the text of the message.

ACTION:	Edit your project to remove the source of the error. Refer to MAX+PLUS II VHDL Support for information on which VHDL features are supported in MAX+PLUS II. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Concurrent signal assignment error: Target of this signal assignment is guarded, but assignment is not
Concurrent signal assignment error: Target of this signal assignment is guarded, but assignment is not a guarded signal assignment

CAUSE:	Your VHDL Design File contains a construct that not is supported in MAX+PLUS II. This construct may also contain an error that is described in the text of the message.

ACTION:	Edit your project to remove the source of the error. Refer to MAX+PLUS II VHDL Support for information on which VHDL features are supported in MAX+PLUS II. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Configuration Specification error: Local generic "<name>" cannot be bound to any formal

CAUSE:	Your VHDL Design File contains a construct that not is supported in MAX+PLUS II. This construct may also contain an error that is described in the text of the message.

ACTION:	Edit your project to remove the source of the error. Refer to MAX+PLUS II VHDL Support for information on which VHDL features are supported in MAX+PLUS II. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


File declaration subtype must denote a file type

CAUSE:	Your VHDL Design File contains a construct that not is supported in MAX+PLUS II. This construct may also contain an error that is described in the text of the message.

ACTION:	Edit your project to remove the source of the error. Refer to MAX+PLUS II VHDL Support for information on which VHDL features are supported in MAX+PLUS II. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Illegal Concurrent Procedure Call Statement

CAUSE:	Your VHDL Design File contains a construct that not is supported in MAX+PLUS II. This construct may also contain an error that is described in the text of the message.

ACTION:	Edit your project to remove the source of the error. Refer to MAX+PLUS II VHDL Support for information on which VHDL features are supported in MAX+PLUS II. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Illegal guarded signal declaration of type <name> following disconnection specification

CAUSE:	Your VHDL Design File contains a construct that not is supported in MAX+PLUS II. This construct may also contain an error that is described in the text of the message.

ACTION:	Edit your project to remove the source of the error. Refer to MAX+PLUS II VHDL Support for information on which VHDL features are supported in MAX+PLUS II. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Illegal reference to an incomplete type

CAUSE:	Your VHDL Design File contains a construct that not is supported in MAX+PLUS II. This construct may also contain an error that is described in the text of the message.

ACTION:	Edit your project to remove the source of the error. Refer to MAX+PLUS II VHDL Support for information on which VHDL features are supported in MAX+PLUS II. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


No guarded signal called "<name>" exists in the current declarative region

CAUSE:	Your VHDL Design File contains a construct that not is supported in MAX+PLUS II. This construct may also contain an error that is described in the text of the message.

ACTION:	Edit your project to remove the source of the error. Refer to MAX+PLUS II VHDL Support for information on which VHDL features are supported in MAX+PLUS II. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Signal <name> is not a guarded signal

CAUSE:	Your VHDL Design File contains a construct that not is supported in MAX+PLUS II. This construct may also contain an error that is described in the text of the message.

ACTION:	Edit your project to remove the source of the error. Refer to MAX+PLUS II VHDL Support for information on which VHDL features are supported in MAX+PLUS II. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Signal assignment error: Null waveform elements can only be assigned to guarded signals

CAUSE:	Your VHDL Design File contains a construct that not is supported in MAX+PLUS II. This construct may also contain an error that is described in the text of the message.

ACTION:	Edit your project to remove the source of the error. Refer to MAX+PLUS II VHDL Support for information on which VHDL features are supported in MAX+PLUS II. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Signal Declaration error: Can't declare implicit signal "GUARD"

CAUSE:	Your VHDL Design File contains a construct that not is supported in MAX+PLUS II. This construct may also contain an error that is described in the text of the message.

ACTION:	Edit your project to remove the source of the error. Refer to MAX+PLUS II VHDL Support for information on which VHDL features are supported in MAX+PLUS II. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Signal Declaration error: Guarded signal "<name>" must also be resolved

CAUSE:	Your VHDL Design File contains a construct that not is supported in MAX+PLUS II. This construct may also contain an error that is described in the text of the message.

ACTION:	Edit your project to remove the source of the error. Refer to MAX+PLUS II VHDL Support for information on which VHDL features are supported in MAX+PLUS II. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Subtype indication in an allocator must either denote a constrained subtype or include an explicit constraint

CAUSE:	Your VHDL Design File contains a construct that not is supported in MAX+PLUS II. This construct may also contain an error that is described in the text of the message.

ACTION:	Edit your project to remove the source of the error. Refer to MAX+PLUS II VHDL Support for information on which VHDL features are supported in MAX+PLUS II. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Type error: Bounds defining a physical type must be of some integer type

CAUSE:	Your VHDL Design File contains a construct that not is supported in MAX+PLUS II. This construct may also contain an error that is described in the text of the message.

ACTION:	Edit your project to remove the source of the error. Refer to MAX+PLUS II VHDL Support for information on which VHDL features are supported in MAX+PLUS II. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Type error: Expression must denote a physical type

CAUSE:	Your VHDL Design File contains a construct that not is supported in MAX+PLUS II. This construct may also contain an error that is described in the text of the message.

ACTION:	Edit your project to remove the source of the error. Refer to MAX+PLUS II VHDL Support for information on which VHDL features are supported in MAX+PLUS II. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Type error: Must be a physical unit

CAUSE:	Your VHDL Design File contains a construct that not is supported in MAX+PLUS II. This construct may also contain an error that is described in the text of the message.

ACTION:	Edit your project to remove the source of the error. Refer to MAX+PLUS II VHDL Support for information on which VHDL features are supported in MAX+PLUS II. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Type error: Must be an integer physical literal of the current type

CAUSE:	Your VHDL Design File contains a construct that not is supported in MAX+PLUS II. This construct may also contain an error that is described in the text of the message.

ACTION:	Edit your project to remove the source of the error. Refer to MAX+PLUS II VHDL Support for information on which VHDL features are supported in MAX+PLUS II. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


********************** BEGINNING OF NON-TRANSLATED TEXT *********************************

The remaining messages in this file are CLSI messages. All cause and action text was automatically generated with variables substituted in for the IEEE section numbers.

The next set of messages (up to to the next comment page) have an ACTION wording that startes with "As a starting point, refer to..."

***************************** END OF NON-TRANSLATED TEXT *********************************


 "<name>" does not denote a label

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 8.8, 8.9, 8.10, 9.1, 9.2, 9.3, 9.4, 9.5, 9.6, and 9.7 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


 "<name>" may not be <text>

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 1.1.1.2, 2.1.1, and 4.3.3 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


<name> Statements are allowed only within a loop

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 8.8, 8.9, and 8.10 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


<name> Statements must be labelled

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 9.1, 9.6, and 9.7 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


<name> denotes the configuration being defined

CAUSE:	Your VHDL Design File contains a potential problem. The text of the message describes the source of the warning.

ACTION:	As a starting point, refer to Section(s) 1.3 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Absolute value of universal expression is too large for implementation

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 7.5 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Actual error: Literals can’t be written or passed as actuals to formals of mode out
Actual error: Literals can't be written or passed as actuals to formals of mode out

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 5.2.1.2 and 4.3.3.2 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Actual signal must have a static signal name

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 1.1.1.2 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Alias Declaration error: Can't use name with a multi-dimensional array type

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 4.3.4 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Alias Declaration error: Name must denote an object

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 4.3.4 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


ALL has no meaning with this prefix

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 6.3 and 10.4.11.2 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


All subelements of resolved signal <name> have not been <text>

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 4.3.1.2 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Analysis order error: Architecture <name> of entity <name> in library <name> is out of date and must be reanalyzed

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 11.2 and 1.2 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Analysis order warning: Primary unit <name> in library <name> depends on a modified unit

CAUSE:	Your VHDL Design File contains a potential problem. The text of the message describes the source of the warning.

ACTION:	As a starting point, refer to Section(s) 11.1 and 11.2 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Architecture <name> of entity <name> in library <name> depends on a modified unit

CAUSE:	Your VHDL Design File contains a potential problem. The text of the message describes the source of the warning.

ACTION:	As a starting point, refer to Section(s) 1.1, 1.2, and 11.2 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Array error: Array contains the wrong number of elements

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 3.2.1 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Array error: Array value index constraint is incompatible with the specified type

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 3 and 3.2.1.1 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Array error: Constraints on the "<name>" return type must match those on the "<name>" parameter type

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 2.1-2.1.1 and 3.2.1.1 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Array error: Discrete range direction does not match the prefix direction

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 3 and 3.2.1.1 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Array error: Index expression range does not intersect the range specified by the corresponding array index subtype

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 3.2.1 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Array error: Index value is not within the range specified by the corresponding array index subtype

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 3.2.1 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Array error: Number of constraints supplied does not equal the number of indices

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 3.2 and 3.2.1.1 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Array error: Number of elements in array value is not equal
Array error: Number of elements in array value is not equal to the number of elements specified by the type

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 3.2.1 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Array error: Prefix of the <name> attribute must be constrained

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 3.2.1.1, 4.4, and 6.6 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Array error: Range specified in slice is incompatible with the corresponding array index constraint

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 3.2.1.1 and 6.5 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Assignment error: <name> must be a locally static name

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 8.3, 6.1, and 7.4 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Assignment error: A <text> appears more than once in the target of this assignment

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 8.3 and 8.4 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Assignment error: Can’t determine the type of the <text> of this assignment
Assignment error: Can't determine the type of the <text> of this assignment

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 8.3 and 8.4 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Assignment error: Number of elements in this expression does not equal number of elements in the target of this assignment

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 8.3 and 8.4 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Assignment error: Range of expression does not intersect the range specified by the type of the target of this assignment

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 8.3 and 8.4 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Assignment error: Source-target type mismatch

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 8.3, 8.4, and 9.5 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Assignment error: Target of this assignment is not <text>

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 8.3 and 8.4 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Assignment error: Value does not lie within the range specified by the type of the target of this assignment

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 8.3 and 8.4 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Association list error: Actual does not correspond to any formal

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 4.3.3.2 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Association list error: Actual is associated with a previously associated formal

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 4.3.3.2 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Association list error: Association element subtype is incompatible
Association list error: Association element subtype is incompatible with the associated element subtype

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 4.3.3 and 4.2 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Association list error: Association element type is incompatible
Association list error: Association element type is incompatible with the associated element type

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 4.3.3 and 4.1 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Association list error: Can't determine the formal designator's type

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 4.3.3.2 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Association list error: Can't use positional association after named association

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 4.3.3.2 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Association list error: Can't use positional association after named association

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 4.3.3.2 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Association list error: Formal part of association is in the form of a type conversion, but is invalid

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 4.3.3.2 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Association list error: Formal part of association is not a name or a type converted name

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 4.3.3.2 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Association list error: Formal "<name>" must be associated with an actual <text>

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 4.3.3.2, 8.3, and 8.4 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Association list error: Illegal formal part in named association

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 4.3.3.2 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Association list error: Illegal formal type

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 4.3.3.2 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Association list error: Independent formal subelement association is not allowed on formals of type <type name>

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 4.3.3.2 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Association list error: Invalid formal in association element

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 4.3.3.2 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Association list error: Non-defaultable formal "<name>" is not associated

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 4.3.3.2 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Association list error: Subelement of <name> is not associated

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 4.3.3.2 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Attribute error: <name> attribute is applicable only to <name>

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 4.4 and 5.1 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Attribute error: Attribute <name> does not yield a value

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 4.4 and 5.1 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Attribute error: Attribute <name> is already specified for entity <name>

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 4.4 and 5.1 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Attribute error: Attribute "<name>" is not a user-defined attribute

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 4.4 and 5.1 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Attribute error: Can't read attribute <name> of signal within a subprogram

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 4.4 and 4.3.1.2 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Attribute error: Illegal reference to predefined attribute <name>

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 4.4 and 5.1 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Attribute error: "<name>" does not denote an attribute

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 4.4 and 5.1 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Attribute Specification error: Attribute Specification for design unit is for wrong class of design unit
Attribute Specification error: Attribute Specification for design unit is for wrong class of design unit or not in the design unit's declarative part

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 5.1 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Attribute Specification error: Can't associate entity with <name> -- it is not an attribute

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 4.4 and 1.1.2 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Attribute Specification error: Entity does not have an attribute named "<name>"

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 5.1 and 1.1 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Attribute Specification error: Illegal declaration of <name> following Attribute Specification that applies to it

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 5.1 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Attribute Specification warning: OTHERS used without previous Attribute Specification of same class

CAUSE:	Your VHDL Design File contains a potential problem. The text of the message describes the source of the warning.

ACTION:	As a starting point, refer to Section(s) 5.1 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Bad form for attribute <text> value; expecting string literal

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 7.3.1, 4.4, and 5.1 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Bad meaning for attribute <text>

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 4.4 and 5.1 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Bad meaning for name <text>

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 6.1 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Based Literal error: Base of numbers must be between 2 and 16

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 13.4.2 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Based Literal error: Illegal digit

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 13.4.2 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Bit String Literal error: Binary digits are limited to '0' and '1'

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 13.7 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Bit String Literal error: Bit String Literal can only represent arrays of element type BIT

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 13.7 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Bit String Literal error: Octal digits are limited to '0' through '7'

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 13.7 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Block configuration error: Block configuration in a component configuration requires an implied entity

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 1.3 and 1.3.2 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Block configuration error: index specification must be either an expression or a range
Block configuration error: Block configuration index specification must be either an expression or a range

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 1.3.1 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Block configuration error: Block Specification may contain only one name

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 1.3.1 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Block configuration error: Block specification must be an architecture name, a block statement label...
Block configuration error: Block specification must be an architecture name, a block statement label, or a generate statement label

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 1.3.1 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Block configuration error: Index specification can be applied only to a label denoting a "FOR GENERATE" statement

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 1.3.1 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Can't associate port "<name>" with OPEN

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 1.1.1.2, 4.3.3.2, and 5.2.2 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Can't determine association type

CAUSE:	Your VHDL Design File contains a potential problem. The text of the message describes the source of the warning.

ACTION:	As a starting point, refer to Section(s) 4.3.3.2 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Can't find the corresponding <text> declaration for this <text>

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 4.3.1.1 and 2.2 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Can't process this configuration -- no corresponding entity exists in the working library

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 1.3, 1.1, and 11.2 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Cannot attribute from within a secondary unit any entity declared in the corresponding primary unit

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 5.1 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Case Statement error: One or more case alternatives are missing

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 8.7 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Case Statement error: OTHERS choice is required in this Case Statement

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 8.7 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Case Statement or Selected Signal Assignment error: Alternative does not belong to the selector's type or subtype

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 8.7 and 9.5.2 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Case Statement or Selected Signal Assignment error: Alternative is not locally static

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 8.7 and 9.5.2 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Case Statement or Selected Signal Assignment error: Alternative repeats a previous choice

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 8.7 and 9.5.2 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Case Statement or Selected Signal Assignment error: OTHERS choice must be the last alternative

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 8.7 and 9.5.2 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Case Statement warning: Case Statement has too many possibilities for coverage and overlap checking

CAUSE:	Your VHDL Design File contains a potential problem. The text of the message describes the source of the warning.

ACTION:	As a starting point, refer to Section(s) 8.7 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Component <name> does not have a <text> clause

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 5.2.1.2 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Component does not exist

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 4.5 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Component Instantiation error: <name> is not an instance of component <name>

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 9.6 and 4.5 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Component Instantiation error: Illegal Component Instantiation Statement

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 9.6 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Concurrent signal assignment error: Null waveform element can’t appear in a concurrent signal assignment
Concurrent signal assignment error: Null waveform element can't appear in a concurrent signal assignment

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 9.5 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Concurrent Signal Assignment Statement error: Concurrent signal assignment target is neither guarded nor unguarded

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 9 and 4.3.1.2 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Configuration Specification error: Component has not been bound

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 5.2.1 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Configuration Specification error: Component is bound more than once

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 5.2.1 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Configuration Specification error: Components must be fully bound to <name> (<name>)

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 5.2.1 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Configuration Specification error: Local port "<name>" cannot be bound to any formal

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 5.2.1.2 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Configuration Specification error: More than one configuration affects instance of component <name>

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 5.2 and 1.3.2 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Configuration warning: OTHERS used without previous configuration of same component

CAUSE:	Your VHDL Design File contains a potential problem. The text of the message describes the source of the warning.

ACTION:	As a starting point, refer to Section(s) 5.2 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Constant Declaration error: Deferred constant can be completed only in a package body

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 4.3.1.1 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Constant Declaration error: Deferred constant can be declared only within a package declaration

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 4.3.1.1 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Constant Declaration error: Deferred constant "<name>" must be completed before it is referenced here

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 4.3.1.1 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Constant Declaration error: Found duplicate full declaration of constant "<name>"

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 4.3.1.1 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Constants cannot be written

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 4.3.1.1 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Design library error: Can’t locate the working library
Design library error: Can't locate the working library

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 11.2 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Design library error: Library <name> (translation: "<name>") referenced in <name> cannot be opened

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 11.2 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Design library error: Library name <name> has multiple definitions; none are used

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 11.2 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Design library error: Library unit is inaccessible

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 11.2 and 11.1 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Design library error: No library <name> exists (translation: <name>) or it cannot be read

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 11.2 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Design library error: Primary unit <name> in library <name> can't be opened

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 11.2 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Detected unresolved overloaded name

CAUSE:	Your VHDL Design File contains a potential problem. The text of the message describes the source of the warning.

ACTION:	As a starting point, refer to Section(s) 10.5 and 2.3 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Disconnection Specification error: <text> expression in a <text> must be static

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 5.3 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Disconnection Specification error: Disconnection Specification of type <name> is illegal following ALL or OTHERS
Disconnection Specification error: Disconnection Specification of type <name> is illegal following Disconnection Specification for ALL or OTHERS

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 5.3 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Disconnection Specification error: More than one Disconnection Specification affects signal of type <type name>
Disconnection Specification error: More than one Disconnection Specification affects signal of type <name>

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 5.3 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Disconnection Specification warning: OTHERS used without previous
Disconnection Specification warning: OTHERS used without previous Disconnection Specification of same type

CAUSE:	Your VHDL Design File contains a potential problem. The text of the message describes the source of the warning.

ACTION:	As a starting point, refer to Section(s) 5.3 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Each scalar subelement of signal <name> has not been <text>

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 4.3.1.2 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Element "<name>" is unassociated in the aggregate

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 7.3.2 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Entity Declaration error: <text> is not passive

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 1.1.3 and 9.2 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Entity error: No corresponding entity exists in the working library

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 1.1 and 11.2 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Entity error: No matching entity of this class exists in the current declarative part

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 1.1 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Exponentiation error: Negative exponent is allowed only for a left operand of a Floating Point type

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 7.2.5 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Expression must be of type STD.STANDARD.Time

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 14.2 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Expression type error: Expression is not of type <name>

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 7.1 and 3 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Expression type error: Type of this expression cannot be determined

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 7.1 and 3 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Expression type error: Type of this expression is not unique

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 7.1 and 3 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Expression type error: Value of expression is not within the bounds of the type of the expression

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 7.1 and 3 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Expression value is not within the range specified by the type

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 7 and 3 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Formal parameter error: Constant parameters must be of mode IN

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 2.1.1, 4.3.3, and 3.1.1 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Formal parameter error: Formal function parameters must be of mode IN

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 2.1 and 2.2 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Formal parameter error: Formal function parameters must have an object class of CONSTANT or SIGNAL

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 2.1.1 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Found duplicate body of subprogram "<name>"

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 2.2 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Found extraneous attribute parameter

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 4.4 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Found multiple sources for signal <name>, which is associated with a BUFFER port

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 1.1.1.2, 4.3.1.2, and 4.3.3 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Found multiple sources for unresolved <text>

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 4.3.1.2 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Generic declarations must be of mode IN

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 1.1.1.1 and 4.3.3 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Ignored Resolution Function in <text>

CAUSE:	Your VHDL Design File contains a potential problem. The text of the message describes the source of the warning.

ACTION:	As a starting point, refer to Section(s) 2.4 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Illegal use of keyword ALL

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 5.1, 5.2, 5.3, 6.3, and 10.4.11.2 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Implementation limit: <text>

CAUSE:	Your VHDL Design File contains a construct that is too large or too complex. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Incorrect number of elements for conversion to type "<name>"

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 7.3.5 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Index value <number> is out of bounds for VHDL Object <text>

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 8.8 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Interface Declaration error: BUS keyword is not allowed in a non-signal declaration

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 4.3 and 4.3.1.2 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Interface Declaration error: Ports of mode LINKAGE cannot have a default expression

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 4.3.3, 4.3.1.2, and 3.2.1.1 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Interface files cannot have a default expression

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 4.3.1.2 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Invalid attribute prefix

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 4.4 and 6.1 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Last association in list must be OTHERS

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 5.2, 7.3.2, 7.3.2.2, and 4.3.3.2 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Library logical name <name> has changed since <name> was analyzed

CAUSE:	Your VHDL Design File contains a potential problem. The text of the message describes the source of the warning.

ACTION:	As a starting point, refer to Section(s) 11.2 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Library name "<name>" does not translate to a logical name

CAUSE:	Your VHDL Design File contains a potential problem. The text of the message describes the source of the warning.

ACTION:	As a starting point, refer to Section(s) 11.2 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Literal error: Exponent of integers must not be negative

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 13.4.1 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Literal error: Literals can’t be passed as actuals to <text>
Literal error: Literals can't be passed as actuals to <text>

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 7.3.1 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Literal error: Literals can’t serve as type marks
Literal error: Literals can't serve as type marks

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 7.3.1 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Literal error: String contains the wrong number of characters

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 13.6 and 7.3.1 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Local <text> is not associated as a whole with a formal <text>

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 5.2.1.2 and 4.3.3.2 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Loop error: Labeled <text> Statements are allowed only within the named loop

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 8.8, 8.9, and 8.10 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Loop Statement error: Range in a "FOR" iteration scheme is not of a discrete type

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 8 and 3.2.1.1 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Math overflow while processing <number>

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 7.5 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Name error: <text> must be a static name

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 6.1 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Name error: Ending name does not match beginning name

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 6 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Name error: Last part of name has no meaning with prefix

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 6.1 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Name error: Library name is not valid in this context

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 11.2 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Name error: Name must a package in library <name>

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 11.2 and 2.5 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Name error: Name must be a package in the working library

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 11.2 and 2.5 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Name error: Name must be a primary unit in the working library

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 11.2 and 6.3 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Name error: Name must be a simple or selected name

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 6.2 and 6.3 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Name error: Name must be the name of a library

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 11.2 and 11.3 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Name error: Name "<name>" is already declared

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 6 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Name error: Name "<name>" is ambiguous

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 6.1 and 10.3 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Name error: Name "<name>" is undefined

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 6.1 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Name error: Prefix of attribute name is ambiguous

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 6.6 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Name error: Prefix of name is ambiguous

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 6.1 and 10.3 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Name error: Prefix of name is invalid

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 6.1 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Name error: Prefix of slice name must denote a one-dimensional array type

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 6.5 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Name error: Prefix of this name must be the working library

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 11.2 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Name error: Suffix of name must be a selector

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 6.3 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Name error: Suffix of name must be an identifier

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 6.3 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Named association is not allowed in this context

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 4.3.3.2 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Need to update <text>

CAUSE:	Your VHDL Design File contains a potential problem. The text of the message describes the source of the warning.

ACTION:	As a starting point, refer to Section(s) 2.5 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


No corresponding package exists in the working library

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 2.5 and 11.2 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Nonportable extension: Choice OTHERS in an aggregate of unconstrained array type is not supported by IEEE Std 1076-1987

CAUSE:	Your VHDL Design File contains a potential problem. The text of the message describes the source of the warning.

ACTION:	As a starting point, refer to Section(s) 7.3.2 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Only one formal is allowed in this context

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 14.1 and 2.3.1 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Only signals may be passed to ports of mode LINKAGE

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 4.3.1.2 and 4.3.3 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Operation arguments must have the same length

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 7.2 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


OTHERS choice can’t appear in a list of choices
OTHERS choice can't appear in a list of choices

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 7.3.2, 5.1, 5.2, 5.3, and 8.7 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


OUT and INOUT procedure call arguments not declared within processes must be formals of procedure or one of its parents
OUT and INOUT procedure call arguments in procedures not declared within processes must be formals of the procedure or one of its parents

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 2.2, 8.5, and 2.1.1 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Overloading error: Illegal designator on overloaded operator

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 2.3 and 7.2 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Overloading error: Operator "<name>" must have <text>

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 2.3.1 and 7.2 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Package body does not provide a completion for the deferred constant <name>

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 2 and 4.3.1.1 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Package STD.STANDARD has an obsolete format, processing continuing

CAUSE:	Your VHDL Design File contains a potential problem. The text of the message describes the source of the warning.

ACTION:	As a starting point, refer to Section(s) 14.2 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Parameter is required for <name> attribute

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 4.4 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Parameter to the <name> attribute does not refer to one of the bounds of the array type <type name>
Parameter to the <name> attribute does not refer to one of the bounds of the array type <name>

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 4.4 and 3.2.1 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Parameter to the <name> attribute must be of <type name> type
Parameter to the <name> attribute must be of <name> type

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 4.4 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Parameter to the <name> attribute must not be negative

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 4.4 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Physical literal value overflowed implementation limit

CAUSE:	Your VHDL Design File contains a potential problem. The text of the message describes the source of the warning.

ACTION:	As a starting point, refer to Section(s) 7.3.1 and 3.1.3 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Port error: Found multiple sources for a BUFFER port

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 1.1.1 and 4.3.1.2 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Port error: Port declarations must be signals

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 1.1.1.2 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Predefined attribute error: BASE attribute is allowed only as the prefix of another attribute

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 14.1 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Predefined attribute error: Parameter to the <name> attribute must be a static expression

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 14.1 and 7.4 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Predefined attribute error: Predefined attributes have at most one parameter

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 14.1 and 4.4 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Predefined attribute error: Prefix of <name> attribute must be a static name

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 14.1 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Predefined attribute error: "<name>" already has a predefined attribute named "<name>"

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 14.1 and 4.4 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Process Statement warning: Process may run forever

CAUSE:	Your VHDL Design File contains a potential problem. The text of the message describes the source of the warning.

ACTION:	As a starting point, refer to Section(s) 9.2 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Qualified Expression error: Operand of this Qualified Expression contains the wrong number of elements

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 7.3.4 and 7.3 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Qualified Expression error: Prefix of a Qualified Expression must be a type mark

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 7.3.4 and 4.2 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Qualified expression error: Qualifier of this expression must be a type mark

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 7.3.4 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Qualified Expression error: Type mark of this Qualified Expression can’t uniquely type the operand
Qualified Expression error: Type mark of this Qualified Expression can't uniquely type the operand

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 7.3.4 and 4.2 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Qualified Expression error: Type mark of this Qualified Expression permits no valid interpretations of the operand

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 7.3.4 and 4.2 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Range error: Expression range does not intersect the range specified by the type

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 3.2.1 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Range error: Illegal discrete range

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 3 and 3.2.1.1 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Range error: Range does not yield a value

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 3.2.1 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Resolution Function error: Can't use SIGNAL as the object class of the parameter to a resolution function

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 2.4 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Resolution Function error: No resolution function exists with this name

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 2.4 and 4.3.1.2 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Return Statement error: Base type of Return Expression must be base type of return type mark given in the Function Specification
Return Statement error: Base type of the Return Expression must be the base type of the return type mark given in the Function Specification

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 8.11 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Return Statement error: Return Statements appearing within functions must return a value

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 8.11 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Return Statement error: Return Statements appearing within procedures must not return a value

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 8.11 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Return Statement error: Return Statements can only appear in subprogram bodies

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 8.11 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Selector expression must be of a discrete type or of a one-dimensional character array type

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 3.2.1 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Selector expressions of one-dimensional array type must <text>

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 3.2.1 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Semicolon is extraneous

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 13.2 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Sensitivity list error: Name in this sensitivity list does not denote a signal

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 8.1 and 9.2 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Signal assignment error: Time expression in a waveform element can’t be negative
Signal assignment error: Time expression in a waveform element can't be negative

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 8.3 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Signal assignment error: Times in this waveform are not in ascending order

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 8.3 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Signal assignment targets in procedures not declared within processes must be formals of the procedure or one of its parents

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 2.2 and 8.3 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Signal Declaration error: Signal <name> is not of type <name>

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 4.3.1.2 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Signal name may not appear as a primary in this context

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 7.1, 7.3, 7.4, and 8.3 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Space required between abstract literal and unit name

CAUSE:	Your VHDL Design File contains a potential problem. The text of the message describes the source of the warning.

ACTION:	As a starting point, refer to Section(s) 13.2 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Static expression error: Expression must be globally static

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 7.4 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Static Expression error: Expression must be locally static

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 7.4 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Static expression error: Found arithmetic overflow when evaluating this locally static expression

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 7.4 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Subprogram Body error: Function does not contain a Return Statement

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 8.11 and 2.2 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Subprogram error: <text> has a declaration but no body

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 2.2 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Subprogram error: <text> declared outside this function may not be referenced within the function

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 2.2 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Subprogram error: Constraints can’t be specified in a Function Declaration
Subprogram error: Constraints can't be specified in a Function Declaration

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 2.1 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Subprogram invocation error: Can’t find a function named "<name>" with these parameters
Subprogram invocation error: Can't find a function named "<name>" with these parameters

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 2.3 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Subprogram invocation error: Name must be a procedure

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 2.3 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Subprogram invocation error: Procedure <name> is ambiguous

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 2.3 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Subprogram invocation error: Procedure call is inconsistent with all visible procedures having this name

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 2.3 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Symbol has a homograph with non-conforming declaration

CAUSE:	Your VHDL Design File contains a potential problem. The text of the message describes the source of the warning.

ACTION:	As a starting point, refer to Section(s) 10.3 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Type conversion error: <text> of this Type Conversion Function must be constrained

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 7.3.5 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Type conversion error: Invalid use of a Type Conversion Function

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 7.3.5 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Type conversion error: On formals of mode <text>, if formal or actual is type converted, both must be

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 7.3.5 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Type conversion error: Operand of a Type Conversion Function cannot be <text>

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 7.3.5 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Type conversion error: Parameter to Type Conversion Function "<name>" does not have the correct number of elements

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 7.3.5 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Type conversion error: Result type of type conversion is not closely related to the type of its operand

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 7.3.5 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Type conversion error: Type Conversion Function does not return the correct number of elements

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 7.3.5 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Type conversion error: Type Conversion Function does not return type <name>

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 7.3.5 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Type conversion error: Type Conversion Functions are not allowed on actuals for formals of mode <text>

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 7.3.5 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Type conversion error: Type Conversion Functions are not allowed on formals of mode IN

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 7.3.5 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Type conversion error: Type Conversion Functions can’t include File types
Type conversion error: Type Conversion Functions can't include File types

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 7.3.5 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Type conversion error: Type Conversion Functions must be declared with a single argument

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 7.3.5 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Type conversion error: Type conversion is not allowed on signal parameters

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 7.3.5 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Type conversion error: Type of operand in type conversion cannot be determined independent of its context

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 7.3.5 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Type conversion functions are not allowed on actuals for formals of mode BUFFER

CAUSE:	Your VHDL Design File contains a potential problem. The text of the message describes the source of the warning.

ACTION:	As a starting point, refer to Section(s) 1.1.1.2 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Type Declaration error: Incomplete type declaration must be completed

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 4 and 3.3.1 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Type error: <text> must be of a constrained array subtype

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 3.2 and 3.2.1.1 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Type error: <text> range bound type is incompatible with the range type

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 3 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Type error: Can't determine the parameter type

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 3 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Type error: Can't uniquely determine the range type

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 3.2.1.1 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Type error: Can't use type mark as a constraint

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 3.2.1.1 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Type error: Cannot further constrain a constrained array type

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 3.2 and 3.2.1.1 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Type error: Constraint is inconsistent with the range type

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 3 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Type error: Constraint specified on subtype indication is incompatible with the constraint on the specified type or subtype

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 3.2 and 3.2.1.1 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Type error: Formal is not an element of the record type

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 3.2.2 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Type error: Index constraint is not of a discrete type

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 3.2 and 3.2.1.1 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Type error: Index constraint type mark does not denote a discrete type

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 3.2 and 3.2.1.1 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Type error: Invalid constraint in subtype indication

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 3 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Type error: Range bound is not of a discrete type

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 3.1 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Type error: Range bound types are incompatible with the range type

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 3 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Type error: Range bounds have incompatible types

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 3 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Type error: Range values must belong to a scalar type

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 3.1 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Type error: Record type <type name> does not have an element numbered <element number>
Type error: Record type <name> does not have an element numbered <number>

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 3.2.2 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Type error: Return type mark index ranges and the returned expression type must have the same direction

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 3.1, 3.2.1, 3.2.1.1, and 2.1 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Type error: Subtype of the selector expression must be constrained

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 3.2.1.1 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Type error: "<name>" does not denote a type or subtype

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 3 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Type is an access to itself

CAUSE:	Your VHDL Design File contains a potential problem. The text of the message describes the source of the warning.

ACTION:	As a starting point, refer to Section(s) 3.3 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Unit <name> is not a VHDL design unit; ignoring it

CAUSE:	Your VHDL Design File contains a potential problem. The text of the message describes the source of the warning.

ACTION:	As a starting point, refer to Section(s) 11.1 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Unlabeled statement can't have ending label

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 8.8 and 9.2 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Unsupported arithmetic operation encountered <text>

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 7.2 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Variable Declaration error: Procedure parameters must be of mode IN, OUT, or INOUT

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 4.3.1.3 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


VHDL Netlist Reader limitation: <text> during static expression evaluation

CAUSE:	Your VHDL Design File contains a potential problem. The text of the message describes the source of the warning.

ACTION:	As a starting point, refer to Section(s) 7.4 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


VHDL Netlist Reader limitation: <text>

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 2.3 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


VHDL Netlist Reader limitation: <text>

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 6.4 and 6.5 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


VHDL Netlist Reader limitation: Can't determine validity of string literal's characters

CAUSE:	Your VHDL Design File contains a potential problem. The text of the message describes the source of the warning.

ACTION:	As a starting point, refer to Section(s) 13.6 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


VHDL syntax error: Expected a block, but this is not a block

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 1, 1.1, and 9.1 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


VHDL syntax error: Expected a component, but this is not a component

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 4.5 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


VHDL syntax error: Expected a configuration, but this is not a configuration

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 1.3 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


VHDL syntax error: Expected a package name

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 2.5 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


VHDL syntax error: Expected an architecture, but this is not an architecture

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 1.2 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


VHDL syntax error: Expected an entity, but this is not an entity

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 1.1 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


VHDL syntax error: Expected a type or subtype name, but this is neither

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 4.4, 4.5, 4.6, and 4.7 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


VHDL syntax error: Expected Component Instantiation, but this is not a Component Instantiation

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 9.6 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


VHDL syntax error: OTHERS is not allowed in this context

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 7.3.2, 5.1, 5.2, 5.3, and 8.7 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Wait Statement error: Value of timeout expression cannot be negative

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 8.1 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Wait Statement error: Wait Statements cannot appear in <text> or in procedures called from <text>

CAUSE:	Your VHDL Design File contains an error. The text of the message describes the source of the error.

ACTION:	As a starting point, refer to Section(s) 8.1 of the IEEE Standard VHDL Language Reference Manual for information on how to use this feature. Refer also to Perry’s VHDL book for information on creating designs with VHDL.

See also:

How to Use MAX+PLUS II VHDL

MAX+PLUS II Messages

Message Format


Macrofunctions [by function] (all editor applications)
Old-Style Macrofunctions (by Function)

Over 300 74-series, bus, architecture-optimized, and application-specific macrofunctions are available in the MAX+PLUS II Macrofunction Library.

Macrofunctions are listed here by function. You can also refer to a list of Macrofunctions (by number).

Bus macrofunction names end with the letter B. A bus macrofunction is functionally identical to the corresponding non-bus macrofunction, but has grouped input and/or output pins.

1.	To view the schematic or AHDL file that contains the logic for a macrofunction, select the macrofunction symbol in the Graphic Editor or macrofunction name in the Text Editor and choose Hierarchy Down.

2.	VHDL does not support macrofunctions, primitives, or ports with names that are VHDL keywords or that begin with a number, e.g., 74-series macrofunctions. To use these functions in a VHDL Design File, see Using a MAX+PLUS II Macrofunction or Primitive.

Macrofunction Categories:

Adders	Latches

Arithmetic Logic Units	Multipliers

Buffers	Multiplexers

Comparators	Parity Generators/Checkers

Converters	Rate Multipliers

Counters	Registers

Decoders	Shift Registers

Digital Filters	Storage Registers

EDAC	SSI Functions

Encoders	True/Complement I/O Elements

Frequency Dividers

See also:

Printing a File (Graphic Editor)

Renaming a Macrofunction in the Current Project

Unused Inputs to Primitives & Macrofunctions


Adder Macrofunctions

Macrofunction:	Description:

8FADD	Note	8-Bit Full Adder

8FADDB	8-Bit Full Adder

7480	Gated Full Adder

7482	2-Bit Binary Full Adder

7483	4-Bit Binary Full Adder with Fast Carry

74183	Dual Carry-Save Full Adder

74283	Note	4-Bit Full Adder with Fast Carry

74385	4-Bit Adder/Subtractor with Clear


Arithmetic Logic Unit Macrofunction
Arithmetic Logic Unit Macrofunctions

Macrofunction:	Description:

74181	Arithmetic Logic Unit

74182	Look-Ahead Carry Generator

74381	Arithmetic Logic Unit/Function Generator

74382	Arithmetic Logic Unit/Function Generator


Buffer Macrofunctions

Macrofunction:	Description:

BTRI	Active-Low Tri-State Buffer

74240	Octal Inverting Tri-State Buffer

74240B	Octal Inverting Tri-State Buffer with 2 Sections

74241	Octal Tri-State Buffer

74241B	Octal Tri-State Buffer with 2 Sections

74244	Octal Tri-State Buffer

74244B	Octal Tri-State Buffer with 2 Sections

74365	Hex Tri-State Buffer

74366	Hex Inverting Tri-State Buffer

74367	Hex Tri-State Buffer

74368	Hex Inverting Tri-State Buffer

74465	Octal Tri-State Buffer

74466	Octal Inverting Tri-State Buffer

74467	Octal Tri-State Buffer

74468	Octal Inverting Tri-State Buffer

74540	Octal Inverting Tri-State Buffer

74541	Octal Tri-State Buffer


Comparator Macrofunctions

Macrofunction:	Description:

8MCOMP	Note	8-Bit Magnitude Comparator

8MCOMPB	8-Bit Magnitude Comparator

7485	Note	4-Bit Magnitude Comparator

74518	Note	8-Bit Identity Comparator

74518B	8-Bit Identity Comparator

74684	8-Bit Magnitude/Identity Comparator

74686	8-Bit Magnitude/Identity Comparator

74688	8-Bit Identity Comparator


 Converter Macrofunctions

Macrofunction:	Description:

74184	BCD-to-Binary Converter

74185	Binary-to-BCD Converter


 Counter Macrofunctions

Macrofunction:	Description:

GRAY4	Note	Gray Code Counter

UNICNT	Universal 4-Bit Up/Down Counter Left/Right Shift Register with Asynchronous Set and Load, Clear, and Cascade

16CUDSLR	16-Bit Binary Up/Down Counter Left/Right Shift Register with Asynchronous Set

16CUDSRB	16-Bit Binary Up/Down Counter with Left/Right Shift Register, Asynchronous Clear, and Asynchronous Set

4COUNT	4-Bit Binary Up/Down Counter with Synchronous Load (LDN), Asynchronous Clear, and Asynchronous Load (SETN)

8COUNT	Note	8-Bit Binary Up/Down Counter with Synchronous Load (LDN), Asynchronous Clear, and Asynchronous Load (SETN)

7468	Dual Decade Counter

7469	Dual Binary Counter

7490	Decade or Binary Counter with Clear and Set-to-9

7492	Divide-by-12 Counter

7493	4-Bit Binary Counter

74143	4-Bit Counter/Latch, 7-Segment Driver

74160	4-Bit Decade Counter with Synchronous Load and Asynchronous Clear

74161	Note	4-Bit Binary Up Counter with Synchronous Load and Asynchronous Clear

74162	4-Bit Decade Up Counter with Synchronous Load and Synchronous Clear

74163	Note	4-Bit Binary Up Counter with Synchronous Load and Synchronous Clear

74168	Synchronous 4-Bit Decade Up/Down Counter

74169	Synchronous 4-Bit Binary Up/Down Counter

74176	Presettable Decade Counter

74177	Presettable Binary Counter

74190	4-Bit Decade Up/Down Counter with Asynchronous Load

74191	Note	4-Bit Binary Up/Down Counter with Asynchronous Load

74192	4-Bit Decade Up/Down Counter with Asynchronous Clear

74193	4-Bit Binary Up/Down Counter with Asynchronous Clear

74196	Presettable Decade Counter

74197	Presettable Binary Counter

74290	Decade Counter with Clear

74292	Programmable Frequency Divider/Digital Timer

74293	Binary Counter with Clear

74294	Programmable Frequency Divider/Digital Timer

74390	Dual Decade Counter

74393	Dual 4-Bit Up Counter with Asynchronous Clear

74490	Dual 4-Bit Decade Counter

74568	Decade Up/Down Counter with Synchronous Load and Clear and Asynchronous Clear

74569	Binary Up/Down Counter with Synchronous Load and Clear and Asynchronous Clear

74590	8-Bit Binary Counter with Tri-State Output Registers

74592	8-Bit Binary Counter with Input Registers

74668	Synchronous Decade Up/Down Counter

74669	Synchronous 4-Bit Binary Up/Down Counter

74690	Synchronous Decade Counter with Output Registers, Multiplexed Tri-State Outputs, and Asynchronous Clear

74691	Synchronous Binary Counter with Output Registers, Multiplexed Tri-State Outputs, and Asynchronous Clear

74693	Synchronous Binary Counter with Output Registers, Multiplexed Tri-State Outputs, and Synchronous Clear

74696	Synchronous Decade Up/Down Counter with Output Registers, Multiplexed Tri-State Outputs, and Asynchronous Clear

74697	Synchronous Binary Up/Down Counter with Output Registers, Multiplexed Tri-State Outputs, and Asynchronous Clear

74698	Synchronous Decade Up/Down Counter with Output Registers, Multiplexed Tri-State Outputs, and Synchronous Clear

74699	Synchronous Binary Up/Down Counter with Output Registers, Multiplexed Tri-State Outputs, and Synchronous Clear


 Decoder Macrofunctions

Macrofunction:	Description:

16DMUX	4-Bit Binary-to-16-Line Decoder

16NDMUX	4-Bit Binary-to-16-Line Decoder

7442	1-Line-to-10-Line BCD-to-Decimal Decoder

7443	Excess-3-to-Decimal Decoder

7444	Excess-3-Gray-to-Decimal Decoder

7445	BCD-to-Decimal Decoder

7446	BCD-to-7-Segment Decoder

7447	BCD-to-7-Segment Decoder

7448	BCD-to-7-Segment Decoder

7449	BCD-to-7-Segment Decoder

74137	3-Line-to-8-Line Decoder with Address Latches

74138	3-Line-to-8-Line Decoder

74139	Dual 2-Line-to-4-Line Decoder

74145	BCD-to-Decimal Decoder

74154	4-Line-to-16-Line Line Decoder

74155	Dual 2-Line-to-4-Line Decoder/Demultiplexer

74156	Dual 2-Line-to-4-Line Decoder/Demultiplexer

74246	BCD-to-7-Segment Decoder

74247	BCD-to-7-Segment Decoder

74248	BCD-to-7-Segment Decoder

74445	BCD-to-Decimal Decoder


Digital Filter Macrofunctions
 Digital Filter Macrofunction

Macrofunction:	Description:

74297	Digital Phase-Locked Loop Filter


 EDAC Macrofunctions

Macrofunction:	Description:

74630	16-Bit Parallel Error Detection and Correction Circuit

74636	8-Bit Parallel Error Detection and Correction Circuit


 Encoder Macrofunctions

Macrofunction:	Description:

74147	10-Line-to-4-Line BCD Encoder

74148	8-Line-to-3-Line Octal Encoder

74348	8-Line-to-3-Line Priority Encoder with Tri-State Outputs


 Frequency Divider Macrofunctions

Macrofunction:	Description:

FREQDIV	Frequency Divider

7456	Frequency Divider

7457	Frequency Divider


 Latch Macrofunctions

Macrofunction:	Description:

EXPLATCH 	Latch Implemented with Expanders

INPLTCH 	Input Latch Implemented with Expanders

NANDLTCH 	/SR NAND Latch with Expanders

NORLTCH	SR NOR Latch with Expanders

7475	4-Bit Bistable Latch

7477	4-Bit Bistable Latch

74116	Dual 4-Bit Latch with Clear

74259	8-Bit Addressable Latch with Clear

74279	Quad /SR Latch

74373	Octal Transparent D-Type Latch with Tri-State Outputs

74373B	Octal Transparent D-Type Latch with Tri-State Outputs

74375	4-Bit Bistable Latch

74549	8-Bit 2-Stage Pipelined Latch

74604	Octal 2-Input Multiplexed Latch with Tri-State Outputs

74841	10-Bit D-Type Latch with Tri-State Outputs

74841B	10-Bit D-Type Latch with Tri-State Outputs

74842	10-Bit D-Type Latch with Tri-State Outputs

74842B	10-Bit D-Type Inverting Latch with Tri-State Outputs

74843	9-Bit Bus Interface D-Type Latch with Tri-State Outputs

74844	9-Bit Bus Interface D-Type Inverting Latch with Tri-State Outputs

74845	8-Bit Bus Interface D-Type Latch with Tri-State Outputs

74846	8-Bit Bus Interface D-Type Inverting Latch with Tri-State Outputs

74990	8-Bit Transparent Read-Back Latch


  Multiplier Macrofunctions

Macrofunction:	Description:

MULT2	2-Bit Sign Magnitude Multiplier

MULT24	2-Bit-by-4-Bit Parallel Binary Multiplier

MULT4	4-Bit Parallel Binary Multiplier

MULT4B	4-Bit Parallel Binary Multiplier

TMULT4	4-Bit-by-4-Bit Parallel Binary Multiplier

7497	Synchronous 6-Bit Rate Multiplier

74261	2-Bit Parallel Binary Multiplier

74284	4-Bit-by-4-Bit Parallel Binary Multiplier (Upper 4 Bits of Result)

74285	4-Bit-by-4-Bit Parallel Binary Multiplier (Lower 4 Bits of Result)


 Multiplexer Macrofunctions

Macrofunction:	Description:

21MUX 	2-Line-to-1-Line Multiplexer

161MUX	16-Line-to-1-Line Multiplexer

2X8MUX 	2-Line-to-1-Line Multiplexer for 8-Bit Buses

81MUX	Note	8-Line-to-1-Line Multiplexer

74151	Note	8-Line-to-1-Line Multiplexer

74151B 	8-Line-to-1-Line Multiplexer

74153	Dual 4-Line-to-1-Line Multiplexer

74157 	Quad 2-Line-to-1-Line Multiplexer

74158 	Quad 2-Line-to-1-Line Multiplexer with Inverting Outputs

74251 	8-Line-to-1-Line Data Selector with Tri-State Outputs

74253 	Dual 4-Line-to-1-Line Data Selectors with Tri-State Outputs

74257 	Quad 2-Line-to-1-Line Multiplexers with Tri-State Outputs

74258 	Quad 2-Line-to-1-Line Multiplexers with Inverting Tri-State Outputs

74298 	Quad 2-Input Multiplexer with Storage

74352 	Dual 4-Line-to-1-Line Data Selector/Multiplexer with Inverting Outputs

74353 	Dual 4-Line-to-1-Line Data Selector/Multiplexer with Tri-State Inverting Outputs

74354 	8-Line-to-1-Line Data Selector/Multiplexer/Register with Tri-State Outputs

74356 	8-Line-to-1-Line Data Selector/Multiplexer/Register with Tri-State Outputs

74398 	Quad 2-Input Multiplexer with Storage

74399	Quad 2-Input Multiplexer with Storage


 Parity Generator/Checker Macrofunctions

Macrofunction:	Description:

74180	9-Bit Odd/Even Parity Generator/Checker

74180B	9-Bit Odd/Even Parity Generator/Checker

74280	9-Bit Odd/Even Parity Generator/Checker

74280B	9-Bit Odd/Even Parity Generator/Checker


Rate Multiplexer Macrofunctions
 Rate Multiplier Macrofunctions

Macrofunction:	Description:

74167	Synchronous Decade Rate Multiplier


 Register Macrofunctions

Macrofunction:	Description:

ENADFF	Enabled D-Type Flipflop

EXPDFF	Note	D-Type Flipflop Implemented with Expanders (or with DFF Primitive for FLEX 8000 Projects)

7470	AND-Gated JK Flipflop with Preset and Clear

7471	JK Flipflop with Preset

7472	AND-Gated JK Flipflop with Preset and Clear

7473	Dual JK Flipflop with Clear

7474	Dual D-Type Flipflop with Asynchronous Preset and Asynchronous Clear

7476	Dual JK Flipflop with Asynchronous Preset and Asynchronous Clear

7478	Dual JK Flipflop with Asynchronous Preset, Common Clear, and Common Clock

74107	Dual JK Flipflop with Clear

74109	Dual JK Flipflop with Preset and Clear

74112	Dual JK Negative-Edge-Triggered Flipflop with Preset and Clear

74113	Dual JK Negative-Edge-Triggered Flipflop with Preset

74114	Dual JK Negative-Edge-Triggered Flipflop with Preset, Common Clear, and Common Clock

74171	Quad D-Type Flipflops with Clear

74172	Multi-Port Register File with Tri-State Outputs

74173	4-Bit D-Type Register

74174	Hex D-Type Flipflop with Common Clear

74174B	Hex D-Type Flipflop with Common Clear

74175	Quad D-Type Flipflop with Common Clock and Clear

74273	Octal D-Type Flipflop with Asynchronous Clear

74273B	Octal D-Type Flipflop with Asynchronous Clear

74276	Quad J/K Flipflop Register with Common Preset and Clear

74374	Octal D-Type Flipflop with Tri-State Outputs and Output Enable

74374B	Octal D-Type Flipflop with Tri-State Outputs and Output Enable

74376	Quad JK Flipflop with Common Clock and Common Clear

74377	Octal D-Type Flipflop with Enable

74377B	Octal D-Type Flipflop with Enable

74378	Hex D-Type Flipflop with Enable

74379	Quad D-Type Flipflop with Enable

74396	Octal Storage Register

74548	8-Bit 2-Stage Pipelined Register with Tri-State Outputs

74670	4-Bit by 4-Bit Register File with Tri-State Outputs

74821	10-Bit Bus Interface Flipflop with Tri-State Outputs

74821B	10-Bit D-Type Flipflop with Tri-State Outputs

74822	10-Bit Bus Interface Flipflop with Tri-State Inverting Outputs

74822B	10-Bit D-Type Inverting Flipflop with Tri-State Inverting Outputs

74823	9-Bit Bus Interface Flipflop with Tri-State Outputs

74823B	9-Bit D-Type Flipflop with Tri-State Outputs

74824	9-Bit Bus Interface Flipflop with Tri-State Inverting Outputs

74824B	9-Bit D-Type Inverting Flipflop with Tri-State Inverting Outputs

74825	8-Bit Bus Interface Flipflop with Tri-State Ouputs

74825B	Octal D-Type Flipflop with Tri-State Outputs

74826	9-Bit Bus Interface Flipflop with Tri-State Inverting Outputs

74826B	Octal D-Type Inverting Flipflop with Tri-State Inverting Outputs


 Shift Register Macrofunctions

Macrofunction:	Description:

BARRELST 	8-Bit Barrel Shifter

BARRLSTB	8-Bit Barrel Shifter

7491	Serial-In Serial-Out Shift Register

7494	4-Bit Shift Register with Asynchronous Preset and Aynchronous Clear

7495	4-Bit Parallel-Access Shift Register

7496	5-Bit Shift Register

7499	4-Bit Shift Register with /JK Serial Inputs and Parallel Outputs

74164	Serial-In Parallel-Out Shift Register

74164B	Serial-In Parallel-Out Shift Register

74165	Parallel Load 8-Bit Shift Register

74165B	Parallel Load 8-Bit Shift Register

74166	8-Bit Shift Register with Clock Inhibit

74178	4-Bit Shift Register

74179	4-Bit Shift Register with Clear

74194	4-Bit Bidirectional Shift Register with Parallel Load

74195	4-Bit Parallel-Access Shift Register

74198	8-Bit Bidirectional Shift Register

74199	8-Bit Parallel-Access Shift Register

74295	4-Bit Right-Shift Left-Shift Register with Tri-State Outputs

74299	8-Bit Universal Shift/Storage Register

74350	4-Bit Shift Register with Tri-State Outputs

74395	4-Bit Cascadable Shift Register with Tri-State Outputs

74589	8-Bit Shift Register with Input Latches and Tri-State Output

74594	8-Bit Shift Register with Output Latches

74595	8-Bit Shift Register with Output Latches and Tri-State Outputs

74597	8-Bit Shift Register with Input Register

74671	4-Bit Universal Shift Register/Latch with Direct-Overriding Clear and Tri-State Outputs

74672	4-Bit Universal Shift Register/Latch with Synchronous Clear and Tri-State Outputs

74673	16-Bit Shift Register

74674	16-Bit Shift Register


 Storage Register Macrofunctions

Macrofunction:	Description:

7498	4-Bit Data Selector/Storage Register

74278	4-Bit Cascadable Priority Register


 SSI Functions

Macrofunction:	Description:

CBUF	Complementary Buffer

INHB	Inhibit Gate

7400	NAND2 Gate

7402	NOR2 Gate

7404	NOT Gate

7408	AND2 Gate

7410	NAND3 Gate

7411	AND3 Gate

7420	NAND4 Gate

7421	AND4 Gate

7423	Dual 4-Input NOR Gate with Strobe

7425	Dual 4-Input NOR Gate With Strobe

7427	NOR3 Gate

7428	Quad 2-Input Positive NOR Buffer

7430	NAND8 Gate

7432	OR2 Gate

7437	Quad 2-Input Positive NAND Buffer

7440	Dual 4-Input Positive NAND Buffer

7450	Dual 2-Wide 2-Input AND-OR-INVERT Gate

7451	Dual AND-OR-INVERT Gate

7452	AND-OR Gate

7453	Expandable 4-Wide AND-OR-INVERT Gate

7454	4-Wide AND-OR-INVERT Gate

7455	2-Wide, 4-Input AND-OR-INVERT Gate

7464	4-2-3-2 Input AND-OR-INVERT Gate

7486	XOR Gate

74133	13-Input NAND Gate

74134	12-Input NAND Gate with Tri-State Output

74135	Quad XOR/XNOR Gates

74260	Dual 5-Input Positive NOR Gates

74386	Quad XOR Gate


 True/Complement I/O Element Macrofunctions

Macrofunction:	Description:

7487	4-Bit True/Complement I/O Element

74265	Quad Complementary Output Elements


Macrofunctions [by number] (all editor applications)
Macrofunctions (by Number)

Over 300 74-series, bus, and architecture-optimized macrofunctions are available in the MAX+PLUS II Macrofunction Library.

Macrofunctions are listed here by number. You can also refer to a list of Macrofunctions (by function).

Bus macrofunction names end with the letter B. A bus macrofunction is functionally identical to the corresponding non-bus macrofunction, but has grouped input and/or output pins.

1.	To view the schematic or AHDL file that contains the logic for a macrofunction, select the macrofunction symbol in the Graphic Editor or macrofunction name in the Text Editor and choose Hierarchy Down.

2.	VHDL does not support macrofunctions, primitives, or ports with names that are VHDL keywords or that begin with a number, e.g., 74-series macrofunctions. To use these functions in a VHDL Design File, see Using a MAX+PLUS II Macrofunction or Primitive.

Macrofunction:	Bus Macrofunction:

BARRELST	BARRLSTB

BTRI

CBUF

ENADFF

EXPDFF Note

EXPLATCH

FREQDIV

GRAY4 Note

INHB

INPLTCH

MULT2

MULT4	MULT4B

MULT24

NANDLTCH

NORLTCH

TMULT4

UNICNT

4COUNT

81MUX Note

8COUNT Note

8FADD Note	8FADDB

8MCOMP Note	8MCOMPB

2X8MUX

16CUDSLR	16CUDSRB

16DMUX

16NDMUX

21MUX

161MUX

7400

7402

7404

7408

7410

7411

7420

7421

7423

7425

7427

7428

7430

7432

7437

7440

7442

7443

7444

7445

7446

7447

7448

7449

7450

7451

7452

7453

7454

7455

7456

7457

7464

7468

7469

7470

7471

7472

7473

7474

7475

7476

7477

7478

7480

7482

7483

7485 Note

7486

7487

7490

7491

7492

7493

7494

7495

7496

7497

7498

7499

74107

74109

74112

74113

74114

74116

74133

74134

74135

74137

74138

74139

74143

74145

74147

74148

74151 Note	74151B

74153

74154

74155

74156

74157

74158

74160

74161 Note

74162

74163 Note

74164	74164B

74165	74165B

74166

74167

74168

74169

74171

74172

74173

74174	74174B

74175

74176

74177

74178

74179

74180	74180B

74181

74182

74183

74184

74185

74190

74191 Note

74192

74193

74194

74195

74196

74197

74198

74199

74240	74240B

74241	74241B

74244	74244B

74246

74247

74248

74251

74253

74257

74258

74259

74260

74261

74265

74273	74273B

74276

74278

74279

74280	74280B

74283 Note

74284

74285

74290

74292

74293

74294

74295

74297

74298

74299

74348

74350

74352

74353

74354

74356

74365

74366

74367

74368

74373	74373B

74374	74374B

74375

74376

74377	74377B

74378

74379

74381

74382

74385

74386

74390

74393

74395

74396

74398

74399

74445

74465

74466

74467

74468

74490

74518 Note	74518B

74540

74541

74548

74549

74568

74569

74589

74590

74592

74594

74595

74597

74604

74630

74636

74668

74669

74670

74671

74672

74673

74674

74684

74686

74688

74690

74691

74693

74696

74697

74698

74699

74821	74821B

74822	74822B

74823	74823B

74824	74824B

74825	74825B

74826	74826B

74841	74841B

74842	74842B

74843

74844

74845

74846

74990

See also:

Printing a File (Graphic Editor)

Renaming a Macrofunction in the Current Project

Unused Inputs to Primitives & Macrofunctions


Megafunctions/LPM

A variety of megafunctions, including LPM parameterized functions, are provided with MAX+PLUS II. Megafunctions are listed here by function.

Gates

LPM_AND	LPM_INV

LPM_BUSTRI	LPM_MUX

LPM_CLSHIFT	LPM_OR

LPM_CONSTANT	LPM_XOR

LPM_DECODE	MUX

BUSMUX

Arithmetic Components

LPM_ABS	LPM_COUNTER

LPM_ADD_SUB	LPM_MULT

LPM_COMPARE

Storage Components

LPM_DFF	LPM_ROM

LPM_TFF	RAM

LPM_RAM_IO	ROM

LPM_LATCH	CSFIFO

LPM_RAM_DQ	CSDPRAM

LPM_SYNC_RAM_DQ	LPM_SYNC_RAM_IO

LPM_SYNC_ROM

Other Functions

PLL                NTSC

See also:


LPM_ABS (Parameterized Absolute Value)
LPM_ABS (Absolute Value)

Parameterized Absolute Value Module

Altera recommends that you use the LPM_COUNTER function to replace all other types of absolute value functions, including old-style macrofunctions.

Function Prototype:	FUNCTION LPM_ABS (data[LPM_WIDTH-1..0])

WITH (LPM_WIDTH, ADDERTYPE)

RETURNS (result[LPM_WIDTH-1..0], overflow);

Ports:

INPUTS

Port Name	Required	Description	Comments

DATAn	Yes	Signed Number	Input port n bits wide

where 0 <= n <= LPM_WIDTH-1

OUTPUTS

Port Name	Required	Description	Comments

RESULTn	Yes	[Number]	Output port n bits wide

OVERFLOW 	No	True if DATA = -2^(N-1)

where 0 <= n <= LPM_WIDTH-1

Parameters:

Parameter	Type	Required	Description

LPM_WIDTH	Integer	Yes	Width of the DATA and RESULT ports.

Function:

Inputs	|	Outputs

DATA[LPM_WIDTH-1 .. 0]	|	RESULT[LPM_WIDTH-1 .. 0]	OVERFLOW

>= 0	|	DATA[LPM_WIDTH-1 .. 0]	0

< 0	|	DATA[LPM_WIDTH-1 .. 0]	0

100...	|	100...	1

Resource Usage:

The following table summarizes the resource usage results that occur for an LPM_ABS function used to implement a 16-bit absolute value converter with an up/down control with an overflow output.

Design Goals	|	Design Results

|

Device Family	Optimization	|	Width	Logic Cells	Speed (ns)	Note

FLEX 8000, FLEX 10K	Routability	|	16	23	31.6 ns	Note (1)

Speed	|	16	17	19.4 ns	Note (1)

|

MAX 5000, MAX 7000, and MAX 9000	Routability	|	16	17 (0)	12.5 ns	Note (1), Note (2)

See also:

Megafunctions/LPM


Note (1)

Speed is worst case pin-to-pin.


Note (2)

Shared expander(s) required.


LPM_ADD_SUB (Parameterized Adder/Subtractor)
LPM_ADD_SUB (Adder/Subtractor)

Parameterized Adder/Subtractor Module

Altera recommends that you use the LPM_ADD_SUB function to replace all other types of adder/subtractor functions, including old-style macrofunctions.

Function Prototype:	FUNCTION LPM_ADD_SUB (cin, dataa[LPM_WIDTH-1..0], datab[LPM_WIDTH-1..0], add_sub)

WITH (LPM_WIDTH, LPM_REPRESENTATION, LPM_DIRECTION)

RETURNS (result[LPM_WIDTH-1..0], cout, overflow);

Ports:

INPUTS

Port Name	Required	Description	Comments

DATAAn	Yes	Augend/Minuend	Input port n bits wide

DATABn	Yes	Addend/Subtrahend	Input port n bits wide

CIN	No	Carry in to the low order bit.	Default = 0

If OP = ADD, Low = 0 and

High = +1. If OP = SUB, Low = -1

and High = 0

ADD_SUB	No	If the operation to be performed is	Default = ADD

High, OP = DATAAn + DATABn. If the

operation to be performed is Low,

OP = DATAAn - DATABn.

where 0 <= n <= LPM_WIDTH-1

OUTPUTS

Port Name	Required	Description	Comments

RESULT	Yes	DATAAn OP DATABn OP CIN 	Output port n bits wide

mod2^N

COUT 	No	(DATAAn OP DATABn OP CIN) > 	If COUT is used, OVERFLOW cannot be

2^N -1 | (DATAAn OP DATABn OP	used.

CIN) <  -2^N

OVERFLOW	No	Unsigned 	If OVERFLOW is used, COUT cannot be

(DATAAn OP DATABn OP CIN)  > 	used.

2^N -1 | (DATAAn OP DATABn

OP CIN) < 0 |

Signed

(DATAAn OP DATABn OP CIN)  >

2^(N -1)- 1 | (DATAAn OP DATABn

OP CIN) <  -2^(N-1)

where 0 <= n <= LPM_WIDTH-1

Parameters:

Parameter	Type	Required	Description

LPM_DIRECTION	String	No	Values are ADD and SUB. The LPM_DIRECTION parameter and ADD_SUB

pin are mutually exclusive.

LPM_WIDTH	Integer	Yes	Width of the DATAA, DATAB, and SUM ports.

LPM_REPRESENTATION	String	No	Type of addition performed: SIGNED or UNSIGNED. If omitted, the default is

UNSIGNED.

ADDERTYPE	String	No	Values are RIPPLE_CARRY, CARRY_LOOKAHEAD, and DEFAULT. Altera

recommends selecting the DEFAULT option as a good implementation style

for the device family and logic options. For FLEX 8000 and FLEX 10K devices,

setting the ADDERTYPE parameter to RIPPLE_CARRY causes fast carry chains,

even if the Fast logic synthesis style is selected.

ONE_INPUT_IS_CONSTANT	String	No	Values are YES or NO. The default is NO. Allows better optimization if an input is

constant.

Function:

UNSIGNED

Inputs	|	Outputs

ADD_SUB	DATAA[LPM_WIDTH-1 .. 0]	DATAB[LPM_WIDTH-1 .. 0]	|	COUT, RESULT[LPM_WIDTH-1 .. 0]	|	OVERFLOW

1	a	b	|	a + b + CIN	|	COUT

0	a	b	|	a - b - CIN	|	!COUT

SIGNED

Inputs	|	Outputs

ADD_SUB	DATAA[LPM_WIDTH-1 .. 0]	DATAB[LPM_WIDTH-1 .. 0]	|	COUT, SUM[LPM_WIDTH-1 .. 0]	|	OVERFLOW

1	a	b	|	a + b + CIN	|	a >= 0 and b >= 0 and SUM < 0

|	|	or a < 0 and b < 0 and SUM >= 0

|	|

0	a	b	|	a - b - CIN	|	a >= 0 and b < 0 and SUM < 0

|	|	or a < 0 and b >= 0 and SUM >= 0

Typical Implementation:

Resource Usage:

The following table summarizes the resource usage results that occur for an LPM_ADD_SUB function used to implement a 16-bit unsigned adder with a carry-in input and a carry-out output. Logic cell usage estimates scale linearly in proportion to adder width.

Design Goals	|	Design Results

|

Device Family	Optimization	|	Width	Logic Cells	Speed (ns)	Note

FLEX 8000, FLEX 10K	Routability	|	16	45	53 ns	Note (1)

Speed	|	16	18	17 ns	Note (1)

|

MAX 5000, MAX 7000, and MAX 9000	Routability	|	16	28 (+22)	23 ns	Note (1), Note (2), Note (3)

See also:

Adder Macrofunctions

Megafunctions/LPM


Note (1)

Speed estimates are for an EPF8282A-2 device.


Note (2)

Speed estimates are for an EPM7128E-7 device.


Note (3)

Shared expander(s) required.


LPM_AND (AND Gate)

Parameterized AND Gate

Altera recommends that you use the AND primitives rather than LPM_AND for easier implementation and to improve compilation time. However, LPM_AND may be useful if parameterized input size is needed.

Function Prototype:	FUNCTION LPM_AND (data[lpm_size-1..0][lpm_width-1..0])

WITH (LPM_WIDTH, LPM_SIZE)

RETURNS (result[lpm_width-1..0])

Ports:

INPUTS

Port Name	Required	Description	Comments

DATAmn	Yes	Data input to the AND	Input port with n elements each m bits

wide

where 0 <= n <= LPM_WIDTH-1 and 0 <= m <= LPM_SIZE-1

OUTPUTS

Port Name	Required	Description	Comments

RESULTn	Yes	Each RESULT bit is the AND of m bits	Output port n bits wide

where 0 <= n <= LPM_WIDTH-1 and 0 <= m <= LPM_SIZE-1

Parameters:

Parameter	Type	Required	Description

LPM_WIDTH	Integer	Yes	Width of the DATA and RESULT ports.

LPM_SIZE	Integer	Yes	Number of inputs to each AND gate.

Each LPM_AND module defines LPM_WIDTH AND gates. Each AND gate has the following function:

Function:

Inputs	|	Output

DATA[LPM_SIZEe-1 .. 0]xn	|	RESULTn

0XXX...	|	0

X0XX...	|	0

XX0X...	|	0

...	|	...

1111...	|	1

Resource Usage:

Single LPM_AND gates will tape about one logic cell per gate.

See also:

AND Primitives

7408 Macrofunction

7411 Macrofunction

7421 Macrofunction


LPM_BUSTRI (Buffer)

Parameterized Tri-State Buffer

Altera recommends that you use the TRI primitives rather than LPM_BUSTRI for easier implementation and to improve compilation time. However, the LPM_BUSTRI function may be useful for controlling bidirectional I/O buses.

Function Prototype:	FUNCTION LPM_BUSTRI (tridata[LPM_WIDTH-1..0], data[LPM_WIDTH-1..0], enabletr, enabledt)

WITH (LPM_WIDTH)

RETURNS (tridata[LPM_WIDTH-1..0], result[LPM_WIDTH-1..0]);

Ports:

INPUTS

Port Name	Required	Description	Comments

DATAn	No	Data input to the TRIDATAn	Input port n bits wide. Either DATA or

RESULT must be used.

ENABLETR 	No	If high, enables TRIDATA onto RESULT	Required if RESULT is present  (default = 0)

ENABLEDT 	No	If high, enables DATA onto TRIDATA	Required if DATA is present (default = 0)

where 0 <= n <= LPM_WIDTH-1

OUTPUTS

Port Name	Required	Description	Comments

RESULTn	No	Output of the TRI buffer TRIDATAn	Output port n bits wide. Either DATA or

RESULT must be used.

where 0 <= n <= LPM_WIDTH-1

BIDIRS

Port Name	Required	Description	Comments

TRIDATAn	Yes	Bidirectional bus signal	Bidirectional port n bits wide

where 0 <= n <= LPM_WIDTH-1

Parameters:

Parameter	Type	Required	Description

LPM_WIDTH	Integer	Yes	Width of the DATA, RESULT, and TRIDATA ports.

Function:

Some of the input and output ports of an LPM_BUSTRI are optional. The following three configurations are valid:

1.	Only the input ports DATA[LPM_WIDTH-1 .. 0] and ENABLEDT are present, and only the output ports TRIDATA[LPM_WIDTH-1 .. 0] are present. The LPM_BUSTRI has the following function:

Input	|	Output

ENABLEDT	|	TRIDATA[LPM_WIDTH-1 .. 0]

0	|	Z

1	|	DATA[LPM_WIDTH-1 .. 0]

2.	Only the input ports TRIDATA[LPM_WIDTH-1 .. 0] and ENABLETR are present, and only the output ports RESULT[LPM_WIDTH-1 .. 0] are present. The  LPM_BUSTRI has the following function:

Input	|	Output

ENABLETR	|	RESULT[LPM_WIDTH-1 .. 0]

0	|	Z

1	|	TRIDATA[LPM_WIDTH-1 .. 0]

3.	All ports are present: input ports DATA[LPM_WIDTH-1 .. 0], ENABLEDT, and ENABLETR; output ports RESULT[LPM_WIDTH-1 .. 0]; and bidirectional ports TRIDATA[LPM_WIDTH-1 .. 0]. The LPM_BUSTRI has the following function:

Inputs	|	Bidirectional	|	Output

ENABLEDT	ENABLETR	|	TRIDATA[LPM_WIDTH-1 .. 0].	|	RESULT[LPM_WIDTH-1 .. 0]

0	0	|	Z (input)	|	Z

0	1	|	Z (input)	|	TRIDATA[LPM_WIDTH-1 .. 0]

1	0	|	DATA[LPM_WIDTH-1 .. 0]	|	Z

1	1	|	DATA[LPM_WIDTH-1 .. 0]	|	DATA[LPM_WIDTH-1 .. 0]

Resource Usage:

Uses 1 I/O cell register or one logic cell per bit.

See also:

Buffer Macrofunctions

TRI Primitive


LPM_CLSHIFT (Shifter)

Parameterized Combinatorial Shifter Module

Altera recommends that you use the LPM_CLSHIFT function instead of any other type of shifter, including old-style macrofunctions.

Function Prototype:	FUNCTION LPM_CLSHIFT (data[LPM_WIDTH-1..0], distance[LPM_WIDTH-1..0], direction)

WITH (LPM_WIDTH, LPM_WIDTHDIST, LPM_SHIFTTYPE)

RETURNS (result[LPM_WIDTH-1..0], underflow, overflow);

Ports:

INPUTS

Port Name	Required	Description	Comments

DATAn	Yes	Data to be shifted	Input port n bits wide

DISTANCEm	Yes	Number of positions to shift in the	Input port m bits wide

direction specified by the DIRECTION

port

DIRECTION	No	Low = Left, High = Right	Default = Left

where 0 <= n <= LPM_WIDTH-1 and 0 <= m <= LPM_WIDTHDIST-1

OUTPUTS

Port Name	Required	Description	Comments

RESULTn	Yes	Shifted DATA	Output port n bits wide

OVERFLOW 	No	Arithmetic or value overflow	Not available if ROTATE is specified  for the

LPM_SHIFTTYPE parameter.

UNDERFLOW	No	Arithmetic or value underflow	Not available if ROTATE is specified for the

LPM_SHIFTTYPE parameter.

where 0 <= n <= LPM_WIDTH-1 and 0 <= m <= LPM_WIDTHDIST-1

Parameters:

Parameter	Type	Required	Description

LPM_WIDTH	Integer	Yes	Width of the DATA and RESULT ports. Any positive integer that is > 1.

LPM_WIDTHDIST	Integer	Yes	Width of the DISTANCE input port.

LPM_WIDTHDIST <= ceil(log-base-2(LPM_WIDTH)).

LPM_SHIFTTYPE	String	Yes	Type of shifter: LOGICAL, ROTATE, or ARITHMETIC. You must enter a value

for LPM_SHIFTTYPE; there is no default setting.

Function:

Operation of the LOGICAL shifter is illustrated in the following example, in which LPM_WIDTH = 4:

Inputs	|	Outputs

DIRECTION	DISTANCE[1 .. 0]	DATA[3 .. 0]	|	OVERFLOW	|	RESULT[3 .. 0]	|	UNDERFLOW

X	0	dcba	|	0	|	dcba	|	0

0	1	dcba	|	d	|	cba0	|	0

0	2	dcba	|	d # c	|	ba00	|	0

0	3	dcba	|	d # c # b	|	a000	|	0

1	1	dcba	|	0	|	0dcb	|	!d & !c & !b & a

1	2	dcba	|	0	|	00dc	|	!d & !c & (b # a)

1	3	dcba	|	0	|	000d	|	!d & (c # b # a)

Operation of the ARITHMETIC shifter is illustrated in the following example, in which LPM_WIDTH= 4:

Inputs	|	Outputs

DIRECTION	DISTANCE[1 .. 0]	DATA[3 .. 0]	|	OVERFLOW	|	RESULT[3 .. 0]	|	UNDERFLOW

X	0	dcba	|	0	|	dcba	|	0

0	1	0cba	|	c	|	cba0	|	0

0	1	1cba	|	!c	|	cba0	|	0

0	2	0cba	|	c # b	|	ba00	|	0

0	2	1cba	|	c! # b!	|	ba00	|	0

0	3	0cba	|	c # b # a	|	a000	|	0

0	3	1cba	|	!c # !b # !a	|	a000	|	0

1	1	0cba	|	0	|	00cb	|	!c & !b & a

1	1	1cba	|	0	|	11cb	|	c & b & !a

1	2	0cba	|	0	|	000c	|	!c & (b # a)

1	2	1cba	|	0	|	111c	|	c & (!b # !a)

1	3	0cba	|	0	|	0000	|	(c # b # a)

1	3	1cba	|	0	|	1111	|	(!c # !b # !a)

Operation of the ROTATE shifter is illustrated in the following example, in which LPM_WIDTH= 4:

Inputs	|	Outputs

DIRECTION	DISTANCE[1 .. 0]	DATA[3 .. 0]	|	RESULT[3 .. 0]

X	0	dcba	|	dcba

0	1	dcba	|	cbad

0	2	dcba	|	badc

0	3	dcba	|	adcb

1	1	dcba	|	adcb

1	2	dcba	|	badc

1	3	dcba	|	cbad

Resource Usage:

The following table summarizes the resource usage results that occur for an LPM_CLSHIFT function used to implement a 16-bit bidirectional arithmetic shifter. Logic cell usage estimates scale slightly faster than linearly in proportion to shifter width.

Design Goals	|	Design Results

|

Device Family	Optimization	|	Width	Logic Cells	Speed (ns)	Note

FLEX 8000, FLEX 10K	Routability	|	16	142	51 ns	Note (1)

Speed	|	16	141	45 ns	Note (1)

|

MAX 5000, MAX 7000, and MAX 9000	Routability	|	16	76 (+18)	28 ns	Note (2), Note (3)

Speed	|	16	85 (+10)	22 ns	Note (2), Note (3)

See also:

Megafunctions/LPM


Note (1)

Speed estimates are for an EPF8282A-2 device.


Note (2)

Speed estimates are for an EPM7128E-7 device.


Note (3)

Shared expander(s) required.


LPM_COMPARE (Comparator)

Parameterized Comparator Module

Altera recommends that you use the LPM_COMPARE function instead of any other type of comparator, including old-style macrofunctions.

Function Prototype:	FUNCTION LPM_COMPARE (dataa[LPM_WIDTH-1..0], datab[LPM_WIDTH-1..0])

                        WITH (LPM_WIDTH, LPM_REPRESENTATION)

                        RETURNS (alb, aeb, agb, ageb, aneb, aleb);

Ports:

INPUTS

Port Name	Required	Description	Comments

DATAAn	Yes	DATABn is compared to this value	Input port n bits wide

DATABn	Yes	Value to be compared to DATAAn	Input port n bits wide

where 0 <= n <= LPM_WIDTH-1

OUTPUTS

Port Name	Required	Description	Comments

ALB 	No	Default = 1 if DATAAn < DATABn	Either ALB, AEB, AGB, AGEB, ALEB, or

ANEB must be present.

AEB 	No	Default = 1 if DATAAn = DATABn	Either ALB, AEB, AGB, AGEB, ALEB, or

ANEB must be present.

AGB 	No	Default = 1 if DATAAn > DATABn	Either ALB, AEB, AGB, AGEB, ALEB, or

ANEB must be present.

AGEB	No	Default = 1 if DATAAn >= DATABn	Either ALB, AEB, AGB, AGEB, ALEB, or

ANEB must be present.

ALEB	No	Default = 1 if DATAAn <= DATABn	Either ALB, AEB, AGB, AGEB, ALEB, or

ANEB must be present.

ANEB	No	Default = 1 if DATAAn <> DATABn	Either ALB, AEB, AGB, AGEB, ALEB, or

ANEB must be present.

where 0 <= n <= LPM_WIDTH-1

Parameters:

Parameter	Type	Required	Description

LPM_WIDTH	Integer	Yes	Width of the input ports.

LPM_REPRESENTATION	String	No	Type of multiplication performed: SIGNED or UNSIGNED. If omitted, the

default is UNSIGNED.

Function:

Inputs	|	Outputs

DATAA[LPM_WIDTH-1 .. 0]	DATAB[LPM_WIDTH-1 .. 0]	|	ALB	AEB	AGB	AGEB	ALEB	ANEB

a	b	|	a < b	a = b	a > b	a >= b	a <= b	a <>  b

Resource Usage:

The following table summarizes the resource usage results that occur for an LPM_COMPARE function used to implement a 16-bit unsigned comparator. Logic cell usage estimates scale linearly in proportion to shifter width.

Design Goals	|	Design Results

|

Device Family	Optimization	|	Width	Logic Cells	Speed (ns)	Note

FLEX 8000, FLEX 10K	Routability	|	16	25	45 ns	Note (1)

Speed	|	16	17	23 ns	Note (1)

|

MAX 5000, MAX 7000, and MAX 9000	Routability	|	16	16 (19)	50 ns	Note (2), Note (3)

See also:

Comparator Macrofunctions

Megafunctions/LPM


Note (1)

Speed estimates are for an EPF8282A-2 device.


Note (2)

Speed estimates are for an EPM7128E-7 device.


Note (3)

Shared expander(s) required.


LPM_CONSTANT (Constant Generator)

Parameterized Constant Generator Module

The LPM_CONSTANT function is useful for buses that require a constant value.

Function Prototype:	FUNCTION LPM_CONSTANT (dummy)

                        WITH (LPM_WIDTH, LPM_CVALUE)

                        RETURNS (result[LPM_WIDTH-1..0]);

Ports:

OUTPUTS

Port Name	Required	Description	Comments

RESULTn	Yes	Output port n bits wide. 	Value specified by the argument to

LPM_CVALUE. If the value specified cannot

be represented in a port n bits wide, the

RESULT port contains the n least significant

bits of the value’s two’s-complement

representation.

where 0 <= n <= LPM_WIDTH-1

Parameters:

Parameter	Type	Required	Description

LPM_WIDTH	Integer	Yes	Width of the RESULT port.

LPM_CVALUE	Integer	Yes	Constant value to be driven out on the RESULT port. If LPM_CVALUE cannot

be represented in LPM_WIDTH bits, the RESULT port drives the value

LPM_CVALUE mod 2^LPM_WIDTH.

Function:

Inputs	|	Outputs

(none)	|	RESULT[LPM_WIDTH-1 .. 0]

|	LPM_CVALUE

Resource Usage:

Expect no resource usage (i.e., 0 logic cells). The constant outputs will be absorbed by other logic.

See also:

Megafunctions/LPM


LPM_COUNTER (Counter)

Parameterized Counter Module

A parameterizable megafunction from the industry-standard Library of Parameterized Modules (LPM). You can specify the appropriate size, functionality, and physical implementation for your needs by setting the appropriate parameters.

Altera recommends that you use the LPM_COUNTER function instead of any other type of binary counter, including old-style macrofunctions.

Function Prototype:	FUNCTION LPM_COUNTER (data[LPM_WIDTH-1..0], clock, clk_en, cnt_en,

                                                up/down, sclr, sset, sconst, sload, aclr,

                                                aset, aconst, aload)

WITH (LPM_WIDTH, LPM_REPRESENTATION, LPM_MODULUS, LPM_AVALUE,

                                    LPM_SVALUE)

RETURNS Q[LPM_WIDTH-1..0], eq[15..0]);

Ports:

INPUTS

Port Name	Required	Description	Comments

DATAn 	No	Parallel data input to the counter.	Input port n bits wide.

CLOCK	Yes	Clock, positive-edge triggered.

CLK_EN	No	Clock Enable input.	Default = 1. Default Enable pin is CNT_EN.

CNT_EN	No	Count Enable input.	Default = 1. Default Enable pin is CNT_EN.

UPDOWN	No	Up/Down control input.	Default = Up. The LPM_DIRECTION

parameter and the UPDOWN pin are

mutually exclusive.

ASET	No	Asynchonous set input.	Default = 0. If ASET is used, ACONST

cannot be used. If both ASET and ACLR

are used and both are asserted, ACLR is

dominant.

ACLR	No	Asynchronous Clear input.	Default = 0. If ACLR is used, ACONST

cannot be used. If both ASET and ACLR

are used and both are asserted, ACLR is

dominant.

ALOAD	No	Asynchronous load input.	Default = 0. If ALOAD is used, DATAn

Asynchronously loads the counter 	must be used.

with the value on the DATA input.

ACONST	No	Asynchronous set/clear input. Sets 	Default = 0. If ACONST is used, neither

the counter to the value described 	ASET nor ACLR may be used, and the

by the LPM_AVALUE.	LPM_AVALUE parameter must be specified

SSET	No	Synchronous set input. Sets the 	Default = 0. If SSET is used, SCONST

counter on the next active Clock edge	cannot be used. If both SSET and SCLR

are used and both are asserted, SCLR is

dominant.

SCLR	No	Synchronous clear input. Clears the 	Default = 0. If SCLR is used,

counter on the next active Clock 	SCONSTcannot be used. If both SSET

edge.	and SCLR are used and both are

asserted, SCLR is dominant.

SLOAD	No	Synchronous load input. Loads the 	Default = 0.If SLOAD is used, DATA

with the value on the counter with 	must be used.

the value on the DATAn input on

the next active Clock edge

SCONST	No	Synchronous set/clear input. Sets 	Default = 0. If SCONST is used, neither

the counter to the value described	SSET nor SCLR may be used, and the

on the next active Clock	LPM_SVALUE parameter must be

edge.	specified.

where 0 <= n <= LPM_WIDTH-1 and 0 <= p <= 15-1

OUTPUTS

Port Name	Required	Description	Comments

EQp	No	Counter decode output. Active-high 	Either Qn or at least one of the EQ0:15 must

when counter reaches the specified 	be used. Up to  p EQ ports can be

count value.	used (p is less than or equal to 15). EQp is

equivalent to the carry-out from Qp-1

Qn	No	Data output from the counter.	Either Qn or at least one of the EQp must be

used. Output port n bits wide.

where 0 <= n <= LPM_WIDTH-1 and 0 <= p <= LPM_MODULUS-1

Parameters:

Parameter	Type	Required	Description

LPM_WIDTH	Integer	Yes	Width of the DATA and Q ports.

LPM_REPRESENTATION	String	No	Type of counter: UNSIGNED binary or GRAY. If omitted, the default is

UNSIGNED binary.

LPM_DIRECTION	String	No	Values are UP and DOWN.The LPM_DIRECTION parameter and the UPDOWN

pin are mutually exclusive.

LPM_MODULUS	Integer	No	Number of unique states in the counter’s cycle. If omitted, the default is

2^LPM_WIDTH. LPM_MODULUS is required if LPM_WIDTH is not specified. If

the load value is larger than the LPM_MODULUS parameter, the behavior of

the counter is not specified.

LPM_AVALUE	Integer	No	Must be used if ACONST is used. Constant value that is loaded when ACONST

is high.

LPM_SVALUE	Integer	No	Must be used if SCONST is used. Constant value that is loaded on the rising

edge of CLOCK when SCONST is high.

LPM_PVALUE	Integer	No	Constant value that is loaded at power-up.

Function:

Inputs	|	Outputs	|	Function

|	|

ACLR	ACONST	CLR_EN	SCLR	SCONST	CNT_EN	|	|

ASET	ALOAD	CLOCK	SSET	SLOAD	UPDOWN	|	Q[LPM_WIDTH-1 .. 0]	|

1	X	X	X	X	X	X	X	X	X	X	X	|	000...	|

0	1	X	X	X	X	X	X	X	X	X	X	|	111...	|

X	X	1	X	X	X	X	X	X	X	X	X	|	LPM_AVALUE	|	Asynchronous set to value

|	|	specified for LPM_VALUE

0	0	0	1	X	X	X	X	X	X	X	X	|	DATA[LPM_WIDTH-1 .. 0]	|	Asynchronous load from

|	|	DATA input

0	0	0	0	0	X	X	X	X	X	X	X	|	Q[LPM_WIDTH-1 .. 0]	|	Hold current count value

0	0	0	0	1	1	X	X	X	X	X	|	000...	|	Synchronous clear

0	0	0	0	1	0	1	X	X	X	X	|	111...	|	Synchronous set

0	0	0	0	1	X	X	1	X	X	X	|	LPM_SVALUE	|	Synchronous set to value

|	|	specified for LPM_VALUE

0	0	0	0	1	0	0	0	0	0	0	|	Q[LPM_WIDTH-1 .. 0]	|	Hold current count value

0	0	0	0	1	0	0	0	1	X	X	|	DATA[LPM_WIDTH-1 .. 0]	|	Synchronous load from

|	|	DATA input

0	0	0	0	1	0	0	0	0	1	1	|	Q[LPM_WIDTH-1 .. 0]+1	|	Count up

0	0	0	0	1	0	0	0	0	1	0	|	Q[LPM_WIDTH-1 .. 0]-1	|	Count down

Typical Implementation:

The LPM_COUNTER offers four different modes that allow you to force the count value to a specific number. You can use each of the modes either synchronously (pin name prefixed with an "S") or asynchronously (pin name prefixed with an "A").

Mode	Description

Setting (forcing to all ones)	Asserting the SSET or ASET pin forces the count value to all ones.

Clearing (setting to all zeroes)	Asserting the SCLR or ACLR pin forces the count value to all zeroes.

Loading (from data bus)	Asserting the ALOAD or SLOAD pin loads the count value from the data input.

Loading (to a predetermined value)	Asserting the SCONST or ACONST pin loads the count value to the number specified by

the SVALUE or AVALUE parameter.

The Loading (to a predetermined value) mode cannot be used with either the Clearing or Setting modes.

Resource Usage:

The following table summarizes the resource usage results that occur for an LPM_COUNTER function used to implement a 16-bit counter with an up/down control, a count enable input, a synchronous load input, and an asynchronous Clear input. Logic cell usage estimates scale linearly in proportion to counter width.

Design Goals	|	Design Results

|

Device Family	Optimization	|	Width	Logic Cells	Speed (MHz)	Note

FLEX 8000, FLEX 10K	Routability	|	16	45	29 MHz	Note (1)

Speed	|	16	17	112 MHz	Note (1)

|

MAX 5000, MAX 7000, and MAX 9000	Routability	|	16	16	125 MHz	Note (2)

See also:

Megafunctions/LPM


Note (1)

Speed estimates are for the EPF8282A-2 device.


Note (2)

Speed estimates are for the EPM7128E-7 device.


LPM_DECODE (Decoder)

Parameterized Decoder Module

Altera recommends that you use the LPM_DECODE function instead of any other type of decoder, including old-style macrofunctions.

Function Prototype:	FUNCTION LPM_DECODE (data[LPM_WIDTH-1..0], enable)

                  WITH (LPM_WIDTH, LPM_DECODES)

                  RETURNS (eq[LPM_DECODES-1..0]);

Ports:

INPUTS

Port Name	Required	Description	Comments

DATAn	Yes	Unsigned binary encoded number	Input port n bits wide

ENABLE 	Input	No	Enable	Default = 1 if absent

where 0 <= n <= LPM_WIDTH-1 and 0 <= p <= LPM_DECODE-1

OUTPUTS

Port Name	Required	Description	Comments

EQs 	Yes	EQs s high if DATA = s, s >= 0 ,	Low if DATA /= s

where 0 <= n <= LPM_WIDTH-1 and 0 <= p <= LPM_DECODE-1

Parameters:

Parameter	Type	Required	Description

LPM_WIDTH	Integer	Yes	Width of the input value to be decoded.

LPM_DECODES	Integer	Yes	Number of decoder outputs. LPM_DECODES <= 2^LPM_WIDTH.

Function:

Inputs	|	Outputs

ENABLE	DATA[LPM_WIDTH-1 .. 0]	|	EQ[0 .. LPM_DECODES-1]

0	X	|	0000...

1	0	|	1000...

1	1	|	0100...

1	2	|	0010...

...	...	|	...

1	LPM_DECODES-1	|	0000...1

The ENABLE input port and EQp output ports are optional. When ENABLE is omitted, the decoder is permanently enabled.

Resource Usage:

Expect one logic cell per output for up to 16 outputs, and 2 logic cells per output for more than 16 outputs.

See also:

Decoder Macrofunctions

Megafunctions/LPM


LPM_DFF (Shift Register)

Parameterized D-Type Flipflop and Shift Register Module

The LPM_DFF function is useful if features are needed that are not available in the DFF or DFFE primitives. Also useful as a shift register.

Function Prototype:	FUNCTION LPM_DFF (data[LPM_WIDTH-1..0], clock, enable, shiftin,

                                          shiften, sclr, sset, sconst, aclr, aset, aconst)

                        WITH (LPM_WIDTH, LPM_AVALUE, LPM_SVALUE)

                        RETURNS (Q[LPM_WIDTH-1..0], shiftout);

Ports:

INPUTS

Port Name	Required	Description	Comments

DATAn 	No	Data input to the D-type flipflops	Input port n bits wide

CLOCK	Yes	Clock, positive edge triggered

ENABLE	No	Clock enable input	Default = 1

SHIFTIN	No	Serial shift data input	The shift options also use the Enable

input for the Clock enable.

SHIFTEN	No	Shift enable input	Default = 0. When asserted, shifting

operation is performed. Otherwise,

parallel load is done.

ASET	No	Asynchronous set input	If ASET is used, ACONST cannot be used. If

both ASET and ACLR are used and both

are asserted, ACLR is dominant.

ACLR	No	Asynchronous clear input	If ACLR is used, ACONST cannot be used.

If both ASET and ACLR are used and both

are asserted, ACLR is dominant.

ACONST	No	Asynchronous set/clear input. Sets 	If ACONST is used, neither ASET nor

the flipflops to the value specified 	ACLR may be used, and the

by the LPM_AVALUE parameter	LPM_AVALUE parameter must be specified.

SSET	No	Synchronous set input	If SSET is used, SCONST cannot be used. If

both SSET and SCLR are used and both

are asserted, SCLR is dominant.

SCLR	No	Synchronous clear input	If SCLR is used, SCONST cannot be used. If

both SSET and SCLR are used and both

are asserted, SCLR is dominant.

SCONST	No	Synchronous set/clear input	If SCONSTis used, neither SSET nor

Sets the flipflops to the value	SCLR may be used, and the

parameter.	LPM_SVALUE parameter must be specified

where 0 <= n <= LPM_WIDTH-1

OUTPUTS

Port Name	Required	Description	Comments

Qn	No	Data output from D-flipflops	Output port n bits wide. Either Q or

SHIFTOUT must be used.

SHIFTOUT	No	Serial Shift Data output	Output port n bits wide. Either Q or

SHIFTOUT must be used.

where 0 <= n <= LPM_WIDTH-1

Parameters:

Parameter	Type	Required	Description

LPM_WIDTH	Integer	Yes	Width of the DATA and Q ports.

LPM_AVALUE	Integer	No	Constant value that is loaded when ACONST is high. Must be used If

ACONST is used

LPM_SVALUE	Integer	No	Constant value that is loaded on the rising edge of CLOCK when SCONST

is high. Must be used if SCONST is used.

Function:

Inputs	|	Outputs

|

ACLR	ACONST	CLOCK	SSET	SHIFTEN	|

ASET	ENABLE	SCLR	SCONST	|	Q[LPM_WIDTH-1 .. 0]

1	X	X	X	X	X	X	X	X	|	000...

0	1	X	X	X	X	X	X	X	|	111...

X	X	1	X	X	X	X	X	X	|	AValue

0	0	0	0	X	X	X	X	X	|	Q[LPM_WIDTH-1 .. 0]

0	0	0	1	1	X	X	X	|	000...

0	0	0	1	0	1	X	X	|	111...

0	0	0	1	X	X	1	X	|	SValue

0	0	0	1	0	0	0	1	|	Q[LPM_WIDTH-2 .. 1], SHIFTIN

0	0	0	1	0	0	0	0	|	DATA[LPM_WIDTH-1 .. 0]

Resource Usage:

Expect one logic cell per bit.

See also:

DFF Primitive

Megafunctions/LPM

Register Macrofunctions

Shift Register Macrofunctions


LPM_INV (NOT Gate)

Parameterized Inverter Module

Altera recommends that you use the NOT primitives rather than LPM_INV. The LPM_INV function is useful only when compiling files from other industry-standard design tools.

Function Prototype:     FUNCTION LPM_INV (data[LPM_WIDTH-1..0])

                        WITH (LPM_WIDTH)

                        RETURNS (result[LPM_WIDTH-1..0]);

Ports:

INPUT

Port Name	Required	Description	Comments

DATAn	Yes	Data input to the INV	Input port n bits wide

where 0 <= n <= LPM_WIDTH-1

OUTPUT

Port Name	Required	Description	Comments

RESULTn	Yes	Inverted DATA	Output port n bits wide

where 0 <= n <= LPM_WIDTH-1

Parameters:

Parameter	Type	Required	Description

LPM_WIDTH	Integer	Yes	Width of the DATA and RESULT ports.

Function:

Input	|	Output

DATAn	|	RESULTn

0	|	1

1	|	0

Resource Usage:

Expect zero resource usage.

See also:

Megafunctions/LPM

NOT Primitive

7404 Macrofunction


LPM_LATCH (Latch)

Parameterized Latch Module

Altera recommends that you use the LPM_LATCH function only if using the ACONST port; otherwise Altera recommends that you use LATCH primitive rather than LPM_LATCH for easier implementation and to improve compilation time.

Function Prototype:     FUNCTION LPM_LATCH (data[LPM_WIDTH-1..0], gate, aclr, aset, aconst)

                        WITH (LPM_WIDTH, LPMAVALUE)

                        RETURNS (q[LPM_WIDTH-1..0]);

Ports:

INPUTS

Port Name	Required	Description	Comments

DATAn 	No	Data input to the D-type latches	Input port n bits wide

GATE	Yes	Latch enable input.

High = flow-through, Low = latch

ASET	No	Asynchonous set input	Default = 0. If ASET is used, ACONST

                                                                     cannot be used. If both ASET and ACLR

are used and both are asserted, ACLR is

dominant.

ACLR	No	Asynchronous clear input	Default = 0. If ACLR is used, ACONST

cannot be used. If both ASET and ACLR

are used and both are asserted, ACLR is

dominant.

ACONST	No	Asynchronous set/clear input. Sets 	Default = 0. If ACONST is used, neither

the latches to the value described 	ASET nor ACLR may be used, and the

by the LPM_AVALUE parameter.	LPM_AVALUE parameter must be

specified.

where 0 <= n <= LPM_WIDTH-1

OUTPUTS

Port Name	Required	Description	Comments

Qn	Yes	Data output from D-type latches	Output port n bits wide

where 0 <= n <= LPM_WIDTH-1

Parameters:

Parameter	Type	Required	Description

LPM_WIDTH	Integer	Yes	Width of the DATA, Q, and TESTOUT ports.

LPM_AVALUE	Integer	No	Constant value that is loaded when ACONST is high. Must be used if

ACONST is used

Function:

Inputs	|	Outputs

ACLR	ASET	ACONST	GATE	|	Q[LPM_WIDTH-1 .. 0]

1	X	X	X	|	000...

0	1	X	X	|	111...

X	X	1	X	|	LPM_AVALUE

0	0	0	1	|	DATA[LPM_WIDTH-1 .. 0]

0	0	0	0	|	Q[LPM_WIDTH-1 .. 0]

Resource Usage:

Expect a single logic cell per bit.

See also:

Latch Macrofunctions

LATCH Primitive

Megafunctions/LPM


LPM_MULT (Multiplier)

Multiplier Module

Altera recommends that you use LPM_MULT to replace all other types of multiplier functions.

Function Prototype:     FUNCTION LPM_MULT

                  (

                        dataa[(LPM_WIDTHA-1)..0]

                        datab[(LPM_WIDTHB-1)..0]

                        sum[(LPM_WIDTHS-1)..0]

                        aclr,

                        clock

                  )

                  WITH

                  (

                        LPM_WIDTHA,

                        LPM_WIDTHB,

                        LPM_WIDTHR,

                        LPM_WIDTHS,

                        LPM_REPRESENTATION,

                        LATENCY,

                        OPTIMIZE

                  )

                  RETURNS

                  (

                        result[LPM_WIDTHR-1..0]

                  );

Ports:

INPUTS

Port Name	Required	Description	Comments

DATAAn	Yes	Multiplicand	Input port n bits wide

DATABm	Yes	Multiplier	Input port m bits wide

SUMs	No	Partial Sum	Input port s bits wide

CLOCK	No	Clock	Only required if the LATENCY parameter

is greater than zero.

ACLR	No	Asynchronous Clear of registers when

the LATENCY parameter is greater

than zero.

where 0 <= n <= LPM_WIDTHA, 0 <= m <= LPM_WIDTHB, and  0 <= s <= LPM_WIDTHS

OUTPUTS

Port Name	Required	Description	Comments

RESULTp	Yes	RESULT = DATAA x DATAB + SUM The 	Output port p bits wide If p <

product LSB is aligned with the sum 	max (m+n,s), only the p most

LSB	significant bits are present.

where 0 <= n <= LPM_WIDTHA, 0 <= m <= LPM_WIDTHB, 0 <= s <= LPM_WIDTHS, and 0 <= p <= LPM_WIDTHP

Parameters:

Parameter	Type	Required	Description

LPM_WIDTHA	Integer	Yes	Width of the DATAA port.

LPM_WIDTHB	Integer	Yes	Width of the DATAB port.

LPM_WIDTHS	Integer	Yes 	Width of the SUM port. If SUM is not used, set to any value between 1 and

LPM_WIDTHP, inclusive.

LPM_WIDTHP	Integer	Yes	Width of the RESULT port.

LPM_REPRESENTATION	String	No	Type of multiplication performed: SIGNED or UNSIGNED. If omitted, the

default is UNSIGNED.

LATENCY                 Integer	No	Specifies the number of clock cycles of latency associated with the RESULT

output. The default value of zero (0) indicates that no latency exists, and that

a purely combinatorial function will be instantiated.

OPTIMIZE                String	No	Setting OPTIMIZE to AREA will optimize the size, all other values will

optimize for speed.

Function:

Inputs	|	Outputs

DATAA[LPM_WIDTHA-1 .. 0]	DATAB[LPM_WIDTHB-1 .. 0]	SUM[LPM_WIDTHS-1 .. 0]	|	PRODUCT[LPM_WIDTHP-1..0]

a	b	s	|	LPM_WIDTHPmost significant bits

|	of a * b + s

Resource Usage:

The following table summarizes the resource usage results that occur for an LPM_MULT function used to implement 4-bit and 8-bit multipliers with LATENCY = 0 and without the optional SUM input. Logic cell usage estimates scale linearly in proportion to the square of the input width.

Design Goals	|	Design Results

|

Device Family	Optimization	|	Width	Logic Cells	Speed (ns)	Note

FLEX 8000, FLEX 10K	Routability	|	8	121	80 ns	Note (1)

Speed	|	8	163	52 ns	Note (1)

Routability	|	4	29	34 ns	Note (1)

Speed	|	4	41	27 ns	Note (1)

|

MAX 5000, MAX 7000, and MAX 9000	Routability	|	4	26 (11)	23 ns	Note (2)

Speed	|	4	27 (4)	19 ns	Note (2)

Shared expanders are shown in parentheses ( ).

In the FLEX 10K device family, the 4-bit by 4-bit multiplier example shown above can be implemented in a single EAB.

See also:

Megafunctions/LPM

Multiplier Macrofunctions


Note (1)

Speed estimates are for the EPF8282A-2 device.


Note (2)

Speed estimates are for the EPM7128E-7 device.


LPM_MUX (Multiplexer)
LPM_MUX, MUX, BUSMUX (Multiplexers)

Parameterized Multiplexer Module

Altera recommends that you use the LPM_MUX function to replace all other multiplexer functions. The MUX and BUSMUX macrofunctions are derived from LPM_MUX, and are intended to simplify the use of LPM_MUX in GDFs.

Function Prototype:     FUNCTION LPM_MUX (data[LPM_SIZE-1..0] [LPM_WIDTH-1..0], sel[LPM_WIDTHS-1..0]

                        WITH (LPM_WIDTH, LPM_SIZE, LPM_WIDTHS, CASCADE_CHAIN)

RETURNS (result[LPM_WIDTH-1..0];

Ports:

INPUTS

Port Name	Required	Description	Comments

DATAmn	Yes	Data input to the MUX	Input port with n elements each

m bits wide

SELs	Yes	Selects one of the ports	Input port with s elements

Where 0 <= n <= LPM_WIDTH-1 and 0 <= m <= LPM_SIZE-1

OUTPUTS

Port Name	Required	Description	Comments

RESULTn	Yes	RESULT is the input port selected	Input port n bits wide

Where 0 <= n <= LPM_WIDTH-1 and 0 <= m <= LPM_SIZE-1

Parameters:

Parameter	Type	Required	Description

LPM_WIDTH	Integer	Yes	Width of the DATA and RESULT ports.

LPM_SIZE	Integer	Yes	Number of inputs to each multiplexer LPM_SIZE <= 2^LPM_WIDTHS

LPM_WIDTHS	Integer	Yes	Width of the SEL input port.

Function:

Each LPM_MUX module defines LPM_WIDTHS multiplexers. Each multiplexer has the following function:

Inputs	|	Output

SEL[LPM_WIDTH1 .. 0]	|	RESULTn

0	|	DATAn_0

1	|	DATAn_1

2	|	DATAn_2

...	|	...

m	|	DATAn_m

DATAm_n ports are optional. When DATAm_n is omitted from LPM_MUX, the output of RESULTn is undefined when SELECT[LPM_SELECTIONS-1 .. 0] == m.

See also:

Megafunctions/LPM

Multiplexer Macrofunctions


LPM_OR  (OR Gate)

Parameterized OR Gate

Altera recommends that you use the OR primitives rather than LPM_OR for easier implementation and to improve compilation time. However, LPM_OR may be useful if parameterized input size is needed.

Function Prototype:

Function Prototype:     FUNCTION LPM_OR (data[LPM_SIZE-1..0] [LPM_WIDTH-1..0]

                        WITH (LPM_WIDTH, LPM_SIZE)

RETURNS (result[LPM_WIDTH-1..0];

Ports:

INPUTS

Port Name	Required	Description	Comments

DATAmn	Yes	Data input to the OR	Input port with n elements each m

bits wide

where 0 <= n <= LPM_WIDTH-1 and 0 <= m <= LPM_SIZE-1

OUTPUTS

Port Name	Required	Description	Comments

RESULTn	Yes	Each RESULT bit is the OR of m bits	Output port n bits wide

where 0 <= n <= LPM_WIDTH-1 and 0 <= m <= LPM_SIZE-1

Parameters:

Parameter	Type	Required	Description

LPM_WIDTH	Integer	Yes	Width of the DATA and RESULT ports.

LPM_SIZE	Integer	Yes	Number of inputs to each OR gate.

Function:

Each LPM_OR module defines LPM_WIDTH OR gates. Each OR gate has the following function:

Inputs	|	Output

DATA[LPM_SIZE-1 .. 0]xn	|	RESULTn

1XXX...	|	1

X1XX...	|	1

XX1X...	|	1

...	|	...

0000...	|	0

Resource Usage:

Expect 1 logic cell per output.

See also:

Megafunctions/LPM

OR Primitives

7432 Macrofunction


LPM_ram_dq
LPM_RAM_DQ ( )

Memory with separate input and output ports.

Altera recommends that you use LPM_RAM_DQ when an asynchronous RAM is needed. The LPM_RAM_DQ functions uses EABs in FLEX 10K devices, or latch arrays in other device families. If you are using a FLEX 10K device, Altera strongly recommends that you use synchronous RAM functions rather than asynchronous RAM functions, because asynchronous Write Enable timing can be difficult to generate.

Function Prototype:     FUNCTION lpm_ram_dq(data[LPM_WIDTH-1..0], address[LPM_WIDTHAD-1..0],

                                      we, inclock, outclock)

                        WITH {LPM_WIDTH, LPM_WIDTHAD, LPM_NUMWORDS, LPM_FILE, LPM_INDATA,

                              LPM_ADDRESS_CONTROL, LPMOUTDATA)

                        RETURNS (q[LPM_WIDTH-1..0]);

Ports:

INPUTS

Port Name	Required	Description	Comments

DATA	Yes	Data input to the memory	Input port n bits wide

ADDRESS	Yes	Address input to the memory	Input port n bits wide

CLOCK	No	Clock, positive edge triggered	If CLOCK is used, memories are loaded

on the rising edge of the clock. If CLOCK

is not used, WE must be used.

INCLOCK	No	Synchonous load of memory	If the INCLOCK port is used, the WE port

acts as an enable for write operations

synchronized to the positive rising edge

of the signal on the INCLOCK port. If the

INCLOCK port is not used, the WE port

acts as enable for write operations

asynchronously.

OUTCLOCK	No	Synchronous Q outputs from memory	The address memory content to Q

response is synchronous when the

OUTCLOCK port is connected, and

asynchronous when it is not connected.

WE	No	Write enable input. Enables write 	Required if INCLOCK is not present.

operations to the memory when high.	Default value is enabled if WE is not

present.

OUTPUTS

Port Name	Required	Description	Comments

Q	Yes	Data output from the memory	Input port n bits wide

Parameters:

Parameter	Type	Required	Description

LPM_FILE	String	No	Name of the file containing the contents.

LPM_WIDTH	Integer	Yes	Width of DATA and Q ports.

LPM_WIDTHAD	Integer	Yes	Width of the ADDRESS port.

LPM_NUMWORDS	Integer	No	If LPM_NUMWORDS is present, the number of data words stored in the

memory. The symbol value must be < or = 2^m. If LPM_NUMWORDS is

absent, the number of words is 2^m.

LPM_INDATA              String	No	Indicates whether the DATA port is registerd. The default setting is

REGISTERED.

LPM_ADDRESS_CONTROL	String	No	Indicates whether the ADDRESS and WE ports are registered. Default

setting is REGISTERED.

LPM_OUTDATA	String	No	Indicates whether the Q and EQ ports are registered. Default setting is

REGISTERED.

Function:

Write Enable	Function

H	Clock present

Clock not present

L	Contents of memory location is output on DATA.

Resource Usage:

Expect 1 logic cellper bit for Classic, MAX 5000, MAX 7000, MAX 9000, and FLEX 8000 devices. For FLEX 10K devices, expect 1 logic cell per

See also:

Megafunctions/LPM


LPM_ram_io
LPM_RAM_IO ( )

Memory with a single I/O port.

Altera recommends that you use LPM_RAM_IO when an asynchronous RAM is needed. The LPM_RAM_IO functions uses EABs in FLEX 10K devices, or latch arrays in other device families. If you are using a FLEX 10K device, Altera strongly recommends that you use synchronous RAM functionss are strongly rather than asynchronous RAM functions, because asynchronous Write Enable timing can be difficult to generate.

Function Prototype:     FUNCTION lpm_ram_io(address[LPM_WIDTHAD-1..0], we, inclock, outclock,

                                      outenab, memenab)

                        WITH {LPM_WIDTH, LPM_WIDTHAD, LPM_NUMWORDS, LPM_FILE, LPM_INDATA,

                              LPM_ADDRESS_CONTROL, LPMOUTDATA)

                        RETURNS (data[LPM_WIDTH-1..0]);

Ports:

INPUTS

Port Name	Required	Description	Comments

ADDRESS	Yes	Address input to the memory.	Input port n bits wide. If MEMENAB is

used, then MEMENEAB should be

inactive when ADDRESS is changing.

WE	Yes	Write Enable control. Enables writing	Either WE or OUTENAB should be used;

to the memory when high (1).	not both. If no Clock ports are used, when

WE is high (1) the data on the ADDRESS

port should not change.

INCLOCK	No	Synchronous load of memory.	If the INCLOCK port is used, the WE

port acts as an enable for write operations

synchronized to the positive going edge

of the signal on the INCLOCK port. If

the INCLOCK port is not used, the WE

port acts as an enable for write

operations asynchronously.

OUTCLOCK	No	Synchronous Q outputs	The addressed memory content to Q

response is synchronous when the

OUTCLOCK port is connected, and

asynchronous when it is not connected.

MEMENAB	No	Memory enable input.	Either MEMENAB or OUTENAB must be

present. Enable signal for memories.

Default value is enabled if MEMENAB is not

present. If MEMENAB is present, it should

be inactive when ADDRESS is changing.

OUTENAB	No	Output enable input	Either MEMENAB or OUTENAB must be

present. Enable signal for memories.

Default value is enabled if OUTENAB is

not present.

WE	No	Write enable input. Enables	Required if CLOCK is not present. If WE

operations to the memory when 	is absent, the default value is enabled.

high.

BIDIR

Port Name	Required	Description	Comments

DATA	Yes	Bidirectional data port for the memory	Input port n bits wide

Parameters:

Parameter	Type	Required	Description

LPM_FILE	String	No	Name of the file containing the contents.

LPM_WIDTH	Integer	Yes	Width of DATA and Q ports.

LPM_WIDTHAD 	Integer	Yes	Width of the ADDRESS port.

LPM_NUMWORDS	Integer	No	If LPM_NUMWORDS is present, the number of data words stored in the

memory. The symbol value must be < or = 2^m. If LPM_NUMWORDS is

absent, the number of words is 2^m.

LPM_ADDRESS_CONTROL	String	No	Indicates whether the ADDRESS, MEMENAB, and WE ports are registered.

Default setting is REGISTERED.

LPM_OUTDATA	String	No	Indicates whether the Q and EQ ports are registered. Default setting

is REGISTERED.

Function:

OUTENAB

MEMENAB	WE	|	Function

L	X	X	|	Memory inactive. Outputs Hi-Z

|

H	L	H	|	Clock present

|	DATA on DATA pins is written into the memory on the L-to-H clock transition.

|	Clock not present

|	DATA is latched into memory with WE acting as the latch gate.

H	H	L	|	Contents of memory location is output on DATA .

|

H	H	H	|	Illegal

Resource Usage:

Expect 1 logic cellper bit for Classic, MAX 5000, MAX 7000, MAX 9000, and FLEX 8000 devices. For FLEX 10K devices, expect 1 logic cell per EAB.

See also:

Megafunctions/LPM


LPM_rom
LPM_ROM ( )

Read-Only Memory

Altera recommends that you use the LPM_ROM function for asynchronous ROM functions. The LPM_ROM function is available only for FLEX 10K devices.

Function Prototype:     FUNCTION lpm_rom(address[LPM_WIDTHAD-1..0], inclock, outclock, memenab)

                        WITH {LPM_WIDTH, LPM_WIDTHAD, LPM_NUMWORDS, LPM_FILE,

                              LPM_ADDRESS_CONTROL, LPMOUTDATA)

                        RETURNS (q[LPM_WIDTH-1..0]);

Ports:

INPUTS

Port Name	Required	Description	Comments

ADDRESS	Yes	Address input to the memory 	Input port n bits wide

INCLOCK	No	Synchronous ADDRESS	The ADDRESS port is synchronous

(registered) when the INCLOCK port is

connected, and is asynchronous

(registered) when the INCLOCK port is

not connected.

OUTCLOCK	No	Synchronous Q outputs from memory.	The addressed memory content to Q

response is synchronous when the

OUTCLOCK port is connected, and

asynchronous when it is not connected.

MEMENAB	No	Memory enable input	H igh = Data Output on Q, Low = Outputs

are Hi-Z

OUTPUTS

Port Name	Required	Description	Comments

Q	Yes	Data (output only)	Output port n bits wide

Parameters:

Parameter	Type	Required	Description

LPM_WIDTH	Integer	Yes	Width of the Q port.

LPM_WIDTHAD 	Integer	Yes	Width of the ADDRESS port.

LPM_NUMWORDS	Integer	No	If LPM_NUMWORDS is present, the number of data words stored in the

memory. The symbol value must be < or = 2^m. If LPM_NUMWORDS is

absent, the number of words is 2^m.

LPM_FILE	String	Yes	Name of the file containing the contents in Hexadecimal format.

LPM_ADDRESS_CONTROL	String	No	Indicates whether the ADDRESS port is registered. The default setting is

REGISTERED.

LPM_OUTDATA	String	No	Indicates whether the Q and EQ ports are registered. The default setting

is REGISTERED.

Function:

MEMENAB  |	Function

L	|	Memory inactive. Outputs Hi-Z.

|

H	|	Contents of memory location is output on DATA.

Resource Usage:

Uses EAB bits.

See also:

Megafunctions/LPM


LPM_TFF (Register)

Parameterized T-Type Flipflop Module

Altera recommends that you use the LPM_TFF function only if you need to use its specical features; otherwise, Altera recommends that you use the TFF primitive.

Function Prototype:     FUNCTION lpm_tff(data[LPM_WIDTH-1..0], clock, enable, sclr, sset, sconst,

                        sload, aclr, aset, aconst, aload)

                        WITH {LPM_WIDTH, LPM_AVALUE, LPM_SVALUE)

                        RETURNS (q[LPM_WIDTH-1..0]);

Ports:

INPUTS

Port Name	Required	Description	Comments

DATAn 	No	Data inputs/bit enables for the toggle 	Input port n bits wide

flipflops.

ENABLE	No	Clock enable input

CLOCK	Yes	Clock, positive edge triggered

ASET	No	Asynchonous set input	Default = 0. If ASET is used ACONST

cannot be used. If both ASET and ACLR

are used and both are asserted, ACLR is

dominant.

ACLR	No	Asynchronous clear input	Default = 0. If ACLR is used ACONST

cannot be used. If both ASET and ACLR

are used and both are asserted, ACLR is

dominant.

ALOAD	No	Asynchronous load input.	Default = 0. If ALOAD is used, DATA

Asynchronously loads the T-type 	must be used

flipflops wirh the value on the DATA

input.

ACONST	No	Asynchronous set/clear input. Sets 	Default = 0. If ACONST is used, neither

the T-type flipflops to the value 	ASET nor ACLR may be used, and the

described by the LPM_AVALUE 	LPM_AVALUE parameter must be

parameter.	specified.

SSET	No	Synchronous set input. Sets the 	Default = 0. If SSET is used, SCONST

T-type flipflop on the next active 	cannot be  used. If both SSET and

Clock edge.	SCLR are used and both are asserted,

SCLR is dominant.

SCLR	No	Synchronous clear input. Clears 	Default = 0. If SCLR is used, SCONST

the T-type flipflip on the next active 	cannot be used. If both SSET and

Clock edge.	SCLR are used and both are asserted,

SCLR is dominant.

SLOAD	No	Synchronous load input. Loads the 	Default = 0. If SLOAD is used, DATA

T-type flipflops with the value on 	must be used.

the DATA input on the next active

Clock edge.

SCONST	No	Synchronous set/clear input. Sets 	Default = 0. If SCONST is used, neither

the T-type flipflops to the value 	SSET nor SCLR may be used, and the

described by the LPM_SVALUE 	LPM_SVALUE parameter must be

parameter on the next active 	specified.

Clock edge.

where 0 <= n <= LPM_WIDTH-1

OUTPUTS

Port Name	Required	Description	Comments

Qn	Yes	Data output from T-type flipflops	Output port n bits wide

where 0 <= n <= LPM_WIDTH-1

Parameters:

Parameter	Type	Required	Description

LPM_WIDTH	Integer	Yes	Width of the DATA, Q, and TESTOUT ports.

LPM_AVALUE	Integer	No	Constant value that is loaded when ACONST is high. Must be used if

ACONST is used

LPM_SVALUE	Integer	No	Constant value that is loaded on the rising edge of CLOCK when SCONST

is high. Must be used if SCONST is used.

Function:

Inputs	|	Outputs

|

ACLR	ACONST	ENABLE	SCLR	SCONST	|

ASET	ALOAD	CLOCK	SSET	SLOAD	|	Q[LPM_WIDTH-1 .. 0]

1	X	X	X	X	X	X	X	X	X	|	000...

0	1	X	X	X	X	X	X	X	X	|	111...

X	X	1	X	X	X	X	X	X	X	|	LPM_AVALUE

0	0	0	1	X	X	X	X	X	X	|	DATA[LPM_WIDTH-1 .. 0]

0	0	0	0	0	X	X	X	X	X	|	Q[LPM_WIDTH-1 .. 0]

0	0	0	0	1	1	X	X	X	|	000...

0	0	0	0	1	0	1	X	X	|	111...

0	0	0	0	1	X	X	1	X	|	LPM_SVALUE

0	0	0	0	1	0	0	0	1	|	DATA[LPM_WIDTH-1 .. 0]

0	0	0	0	1	0	0	0	0	|	Q[LPM_WIDTH-1 .. 0]

|	XOR DATA[LPM_WIDTH-1 .. 0]

Resource Usage:

Expect 1 logic cell per bit.

See also:

Megafunctions/LPM

Register Macrofunctions

TFF Primitive


LPM_XOR (XOR Gate)

Parameterized XOR Gate

Altera recommends that you use the XOR primitive rather than LPM_XOR for easier implementation and to improve compilation time. However, LPM_XOR may be useful if parameterized input size is needed.

Function Prototype:     FUNCTION lpm_xor(data[LPM_SIZE-1..0], [LPM_WIDTH-1..0])

                        WITH {LPM_WIDTH, LPM_SIZE)

                        RETURNS (result[LPM_WIDTH-1..0]);

Ports:

INPUTS

Port Name	Required	Description	Comments

DATAmn	Yes	Data input to the OR	Input port with n elements each m bits

wide

where 0 <= n <= LPM_WIDTH-1 and 0 <= m <= LPM_SIZE-1

OUTPUTS

Port Name	Required	Description	Comments

RESULTn	Yes	Each RESULT bit is the xoR of m bits	Output port n bits wide

where 0 <= n <= LPM_WIDTH-1 and 0 <= m <= LPM_SIZE-1

Parameters:

Parameter	Type	Required	Description

LPM_WIDTH	Integer	Yes	Width of the DATA and RESULT ports.

LPM_SIZE	Integer	Yes	Number of inputs to each XOR gate.

Function:

Each LPM_XOR module defines LPM_WIDTH XOR gates. Each XOR gate has the following function:

Inputs	|	Output

Number of 1’s at DATA0xn through DATA LPM_SIZE-1xn	|	RESULTn

Even	|	0

Odd	|	1

See also:

Megafunctions/LPM

XOR Primitive

7486 Macrofunction


CSFIFO (Cycle-Shared FIFO)

Cycle Shared FIFO megafunction

Altera recommends that you use CSFIFO in place of all cycle-shared FIFO functions.

Function Prototype:     FUNCTION csfifo(data[LPM_WIDTH-1..0], wreq, rreq, cloc, clock2,

                              clr, threshlevel(CEIL(LOG2[LPM_NUMWORDS-1..0])))

                        WITH {LPM_WIDTH, LPM_NUMWORDS)

                        RETURNS (Q[LPM_WIDTH-1..0], threshold, empty, full);

Ports:

INPUTS

Port Name	Required	Description	Comments

DATAn	Yes	Data input to the FIFO	Input port n bits wide

WREQ                    Yes	Write request

RREQ                    Yes	Read request

CLOCK                   Yes	Clock, positive edge triggered

CLOCKX2                 Yes	Clock, positive edge triggered

CLR                     No	Resets FIFO to empty

THRESHLEVEL             No	Level (number of words) that the

THRESHOLD output signal gets asserted

where 0 <= n <= LPM_WIDTH-1

OUTPUTS

Port Name	Required	Description	Comments

Qn	Yes	Data output from FIFO	Output port n bits wide

FULL                    No	Indicates that FIFO is full

EMPTY                   No	Indicates that FIFO is empty

THRESHOLD               No	Indicates that FIFO contains greater

than the THRESHLEVEL number of words.

where 0 <= n <= LPM_WIDTH-1

Parameters:

Parameter	Type	Required	Description

LPM_WIDTH	Integer	Yes	Width of the DATA and Q ports.

LPM_NUMWORDS	Integer	No	Depth of memory

See also:

Megafunctions/LPM

XOR Primitive

7486 Macrofunction


DPRAM (Dual-Port RAM)
CSDPRAM (Dual-Port RAM)

Cycle Shared Dual-Port RAM megafunction

Altera recommends that you use CSDPRAM in place of all cycle-shared dual-port RAM functions.

Function Prototype:     FUNCTION csdpram(dataa[LPM_WIDTH-1..0], datab[LPM_WIDTH-1..0],

                              addressa[LPM_WIDTHAD-1..0], addressb[LPM_WIDTHAD-1..0],

                              wea, web, clock, clockx2)

                        WITH (LPM_WIDTH, LPM_WIDTHAD, LPM_NUMWORDS)

                        RETURNS (qa[LPM_WIDTH-1..0], qb[LPM_WIDTH-1..0], busy);

Ports:

INPUTS

Port Name	Required	Description	Comments

DATAn	Yes	Data input to the memory	Input port n bits wide

DATBn	Yes	Data input to the memory	Input port n bits wide

ADDRESSA                Yes	Address input to the memory

ADDRESSB                Yes	Address input to the memory

WEA                     Yes	Write enable input

WEB	Yes	Write enable input

CLOCK                   Yes	Clock, positive edge triggered

CLOCKX2                 Yes	Clock, positive edge triggered

where 0 <= n <= LPM_WIDTH-1

OUTPUTS

Port Name	Required	Description	Comments

QAn	Yes	Data output from the memory	Output port n bits wide

QBn	Yes	Data output from the memory	Output port n bits wide

BUSY                    No	Indicates that ADDRESSA = ADDRESSB

and that DATAA is writing data.

where 0 <= n <= LPM_WIDTH-1

Parameters:

Parameter	Type	Required	Description

LPM_WIDTH	Integer	Yes	Width of the DATA, DATAB, QA, and QB ports.

LPM_WIDTHAD	Integer	Yes	Width of the ADDRESSA and ADDRESSB ports.

LPM_NUMWORDS	Integer	No	Depth of memory (defaults to 2^LPM__WIDTHAD)

See also:

Megafunctions/LPM

XOR Primitive

7486 Macrofunction


NTSC (Pattern Generator)

NTSC Video Control Signal Generator

Default Signal Levels:	GND--Clock

VCC--Reset

Function Prototype:

FUNCTION NTSC (clock, reset)

RETURNS (csync, hd, vd, blank, burst, field);

The NTSC macrofunction is a registered complex pattern generator. The pattern generated follows the published NTSC specification:

910 pixels are in each line.

525 lines are on each screen.

CSYNC pulses are formatted according to the current NTSC phase.

HD signal is deasserted to indicate the next line.

VD signal is deasserted to indicate the next frame.

BLANK signal is asserted to indicate a "blanked" portion of the scan.

BURST and FIELD signals are deasserted according to the NTSC specification.

The logic for this function is implemented in the AHDL TDF ntsc.tdf, which includes a full functional description of this macrofunction and extensive comments throughout the file.

See also:

Macrofunctions (by function)

Recommended reading:

AN25 (Controlling Complex CCD Imaging Systems with the EPS464 STG EPLD)


PLL (Digital Phase Detector)

Rising- and Falling-Edge Detector

Default Signal Levels:	VCC--all input pins

Function Prototype:

FUNCTION PLL (a, b, nset)

RETURNS (nup, tri-up, ndown, tri-down);

This macrofunction is not directly supported by VHDL because it contains one or more port names with a slash (/) or dash (-). These characters are illegal in VHDL port names. However, you can use this macrofunction in your project by incorporating it into a lower-level design file, then inserting an instance of the lower-level file into your VHDL Design File. See Using a MAX+PLUS II Primitive or Macrofunction for more information.

The PLL (phase-locked loop) macrofunction is a digital phase detector that provides information on the phase and frequency differences between an input signal and a reference signal. It also generates the control signals necessary to synchronize the reference signal with the data input.

This function determines the time difference between corresponding rising (or falling) edges in the two input signals, and indicates this difference by asserting control signals. In a complete PLL circuit, these signals would be routed to a voltage- or current-controlled reference oscillator. The reference oscillator would be configured so that the signal generated by the phase detector correctly adjusts the frequency to bring the reference signal into phase lock and frequency lock with the input signal.

When a PLL is implemented in digital logic, the term "phase-locked loop" is not strictly accurate. The digital portion of the circuit is used only to detect the differences in phase and frequency, but does not perform the actual correcting or restoring functions to bring the data signals under control. The restoring path (i.e., the "loop") must be implemented with external components or discrete circuitry.

The PLL macrofunction can also be used to determine the level and phase differences between unrelated, periodic signals. However, it does not work well with asynchronous or random circuits. The circuitry that keeps track of the phase difference between input signals depends on restoring signals that are generating by input transitions. Therefore, a single pulse on an input makes the circuit unpredictable. To recover control of the circuit, you must drive the nSET input with GND for one propagation delay of the device.

The TRI-DOWN and TRI-UP outputs are provided for PLL circuits that require mutually exclusive control signals, one of which is always tri-stated, e.g., certain types of controlled oscillators. In the PLL function, TRI-DOWN drives GND when it is active, and is tri-stated when it is inactive. TRI-UP drives VCC when it is active, and is tri-stated when it is inactive.

The PLL macrofunction is dynamic and depends on prior-state occurrences. The UP output is asserted whenever the B input leads the A input, regardless of whether A and B are rising or falling. The DOWN output is asserted whenever the A input leads the B input.

For more information on the PLL macrofunction, refer to Application Brief 95 (Designing Phase-Locked Loops with Altera EPLDs).

See also:

Macrofunctions (by function)


 BARRLSTB (Shift Register)

8-Bit Barrel Shifter

Default Signal Levels:	VCC--all input pins

Function Prototype:

FUNCTION BARRLSTB (s[2..0], ldst, d[7..0], clk)

RETURNS (q[7..0]);

Inputs	|	Outputs

S2	S1	S0	LDST	D0..D7	CLK	|	Q0	Q1..Q6	Q7

X	X	X	X	X	L	|	Q0o	Q1o..Q6o	Q7o

X	X	X	H	D0..D7	|	D0	D1..D6	D7

L	L	L	L	X	|	Q0n	Q1n..Q6n	Q7n

L	L	H	L	X	|	Q1n	Q2n..Q7n	Q0n

L	H	L	L	X	|	Q2n	Q3n..Q0n	Q1n

L	H	H	L	X	|	Q3n	Q4n..Q1n	Q2n

H	L	L	L	X	|	Q4n	Q5n..Q2n	Q3n

H	L	H	L	X	|	Q5n	Q6n..Q3n	Q4n

H	H	L	L	X	|	Q6n	Q7n..Q4n	Q5n

H	H	H	L	X	|	Q7n	Q0n..Q5n	Q6n

See also:

Bus-to-Macrofunction Connections

Macrofunctions (by function)

Shift Register Macrofunctions


 MULT4B (Multiplier)

4-Bit Parallel Binary Multiplier

Default Signal Levels:	GND--A[5..1], B[5..1]

VCC--G

Function Prototype:

FUNCTION MULT4B (a[5..1], b[5..1], g)

RETURNS (y[9..1]);

Inputs	|	Outputs

A5*	A4..A1	B5*	B4..B1	G	|	Y9*	Y8..Y1

X	X	X	X	X	X	L	|	L	L ..L

L	a4	a1	L	b4	b1	H	|	L

L	a4	a1	H	b4	b1	H	|	H	A multiplied by B

H	a4	a1	L	b4	b1	H	|	H

H	a4	a1	H	b4	b1	H	|	L

*	Sign bits for sign-magnitude multiplication

See also:

Bus-to-Macrofunction Connections

Macrofunctions (by function)

Multiplier Macrofunctions


 16CUDSRB (Counter)

16-Bit Binary Up/Down Counter with Left/Right Shift Register, Asynchronous Clear, and Asynchronous Set

Default Signal Levels:	GND--CLK, STCT, DATA, LTRT, DNUP

VCC--CLRN, SETN

Function Prototype:

FUNCTION 16CUDSRB (clk, clrn, setn, data, stct, dnup, ltrt)

RETURNS (q[16..1]);

Inputs (1)	|	Operation

CLRN	SETN	STCT	DNUP	LTRT	|

L	X	X	X	X	|	Clear all outputs to low level

H	L	X	X	X	|	Reset all outputs to high level

H	H	H	X	H	|	Shift Left

H	H	H	X	L	|	Shift Right

H	H	L	H	X	|	Count Down

H	H	L	L	X	|	Count Up

See also:

Bus-to-Macrofunction Connections

Counter Macrofunctions

Macrofunctions (by function)


 8FADDB (Adder)

8-Bit Full Adder

Default Signal Levels:	GND--all input pins

Function Prototype:

FUNCTION 8FADDB (cin, a[8..1], b[8..1])

RETURNS (cout, sum[8..1]);

Inputs	|	Outputs

CIN	A8..A1	B8..B1	|	SUM8..SUM1

0	00000000	00000000	|	00000000

1	00000000	00000000	|	00000001  (CIN  +  A  +  B  =  SUM)

.	.	|	.

.	.	|	.

.	.	|	.

1	00001001	00011000	|	00100010  (1  +  9  +  24  =  34)

.	.	|	.

.	.	|	.

.	.	|	.

See also:

Adder Macrofunctions

Bus-to-Macrofunction Connections

Macrofunctions (by function)


 8MCOMPB (Comparator)

8-Bit Magnitude Comparator

Default Signal Levels:	GND--all input pins

Function Prototype:

FUNCTION 8MCOMPB (a[7..0], b[7..0])

RETURNS (altb, aeqb, agtb, aeb[7..0]);

Inputs	|	Outputs

A	B	|	ALTB	AEQB	AGTB	AEBx

A[7..0]	=	B[7..0]	|	0	1	0

|

A[7..0]	<	B[7..0]	|	1	0	0

A[7..0]	>	B[7..0]	|	0	0	1

|

Ax	=	Bx*	|	1

Ax	!=	Bx*	|	0

*	x = bit position

See also:

Bus-to-Macrofunction Connections

Comparator Macrofunctions

Macrofunctions (by function)


 74151B (Multiplexer)

8-Line to 1-Line Multiplexer

Default Signal Levels:	GND--all input pins

Function Prototype:

FUNCTION 74151B (c, b, a, d[7..0], gn)

RETURNS (y, wn);

Inputs	|	Outputs

Select	|	Enable	|

C	B	A	|	GN	|	Y	WN

X	X	X	|	H	|	L	H

L	L	L	|	L	|	D0	/D0

L	L	H	|	L	|	D1	/D1

L	H	L	|	L	|	D2	/D2

L	H	H	|	L	|	D3	/D3

H	L	L	|	L	|	D4	/D4

H	L	H	|	L	|	D5	/D5

H	H	L	|	L	|	D6	/D6

H	H	H	|	L	|	D7	/D7

See also:

Bus-to-Macrofunction Connections

Macrofunctions (by function)

Multiplexer Macrofunctions


 74164B (Shift Register)

Serial-In Parallel-Out Shift Register

Default Signal Levels:	GND--CLK

VCC--A, B, CLRN

Function Prototype:

FUNCTION 74164B (clk, clrn, a, b)

RETURNS (q[7..0]);

Inputs	|	Outputs*

CLK	CLRN	A	B	|	Q0	Q1..Q7

X	L	X	X	|	L	L..L

L	H	X	X	|	Q0o	Q1o..Q7o

H	H	H	|	H	Q0n..Q6n

H	L	X	|	L	Q0n..Q6n

H	X	L	|	L	Q0n..Q6n

*	Q0n, Q7n = level of Q0 or Q7 before the most recent [image] transition of the Clock; indicates a one-bit shift.

See also:

Bus-to-Macrofunction Connections

Macrofunctions (by function)

Shift Register Macrofunctions


 74165B (Shift Register)

Parallel Load 8-Bit Shift Register

Default Signal Levels:	GND--SER, D[7..0], CLKIH, CLK

VCC--STLD

Function Prototype:

FUNCTION 74165B (clk, clkih, stld, ser, d[7..0])

RETURNS (q7, q7n);

Inputs	|	Outputs

Parallel	|	Internal	|	Output

CLK	CLKIH	STLD	SER	D0..D7	|	Q0	Q1	|	Q7	Q7N

X	X	L	X	D0..D7	|	D0	D1	|	D7	/D7

L	L	H	X	X	|	Q0o	Q1o	|	Q7o	/Q6n

L	H	H	X	|	H	Q0n	|	Q6n	/Q6n

L	H	L	X	|	L	Q0n	|	Q6n	/Q6n

X	H	H	X	X	|	Q0o	Q1o	|	Q7o	/Q7o

See also:

Bus-to-Macrofunction Connections

Macrofunctions (by function)

Shift Register Macrofunctions


 74174B (Register)

Hex D-Type Flipflop with Common Clear

Default Signal Levels:	GND--D[6..1], CLK

VCC--CLRN

Function Prototype:

FUNCTION 74174B (clrn, clk, d[6..1])

RETURNS (q[6..1]);

Inputs	|	Outputs

CLRN	CLK	D	|	Q

L	X	X	|	L

H	L	|	L

H	H	|	H

H	L	X	|	Qo

See also:

Bus-to-Macrofunction Connections

Macrofunctions (by function)

Register Macrofunctions


 74180B (Parity Generator/Checker)

9-Bit Odd/Even Parity Generator/Checker

Default Signal Levels:	GND--all input pins

Function Prototype:

FUNCTION 74180B (d[7..0], evni, oddi)

RETURNS (evns, odds);

Inputs	|	Outputs

# of Hs at	|	|

D0 through D7	|	EVNI	ODDI	|	EVNS	ODDS

Even	|	H	L	|	H	L

Odd	|	H	L	|	L	H

Even	|	L	H	|	L	H

Odd	|	L	H	|	H	L

X	|	H	H	|	L	L

X	|	L	L	|	H	H

See also:

Bus-to-Macrofunction Connections

Macrofunctions (by function)

Parity Generator/Checker Macrofunctions


 74240B (Octal Buffer)

Octal Inverter Tri-State Buffer with Two Sections

Default Signal Levels:	GND--AGN, BGN

VCC--A[4..1], B[4..1]

Function Prototype:

FUNCTION 74240B (a[4..1], b[4..1], agn, bgn)

RETURNS (ay[4..1], by[4..1]);

Inputs	|	Outputs

AGN	BGN	|	AY[4..1]	BY[4..1]

H	H	|	Z	Z

H	L	|	Z	/B[4..1]

L	H	|	/A[4..1]	Z

L	L	|	/A[4..1]	/B[4..1]

See also:

Buffer Macrofunctions

Bus-to-Macrofunction Connections

Macrofunctions (by function)


 74241B (Octal Buffer)

Octal Tri-State Buffer with Two Sections

Default Signal Levels:	GND--AGN

VCC--A[4..1], B[4..1], BG

Function Prototype:

FUNCTION 74241B (a[4..1], b[4..1], agn, bg)

RETURNS (ay[4..1], by[4..1]);

Inputs	|	Outputs

AGN	BGN	|	AY[4..1]	BY[4..1]

H	L	|	Z	Z

H	H	|	Z	B[4..1]

L	L	|	A[4..1]	Z

L	H	|	A[4..1]	B[4..1]

See also:

Buffer Macrofunctions

Bus-to-Macrofunction Connections

Macrofunctions (by function)


 74244B (Octal Buffer)

Octal Tri-State Buffer with Two Sections

Default Signal Levels:	GND--AGN, BGN

VCC--A[4..1], B[4..1]

Function Prototype:

FUNCTION 74244B (a[4..1], b[4..1], agn, bgn)

RETURNS (ay[4..1], by[4..1]);

Inputs	|	Outputs

AGN	BGN	|	AY	BY

H	H	|	Z	Z

H	L	|	Z	B

L	H	|	A	Z

L	L	|	A	B

See also:

Buffer Macrofunctions

Bus-to-Macrofunction Connections

Macrofunctions (by function)


 74273B (Register)

Octal D-Type Flipflop with Asynchronous Clear

Default Signal Levels:	GND--D[8..1], CLK

VCC--CLRN

Function Prototype:

FUNCTION 74273B (clrn, clk, d[8..1])

RETURNS (q[8..1]);

Inputs	|	Outputs

CLRN	CLK	D	|	Q

L	X	X	|	L

H	H	|	H

H	L	|	L

H	L	X	|	Qo

See also:

Bus-to-Macrofunction Connections

Macrofunctions (by function)

Register Macrofunctions


 74280B (Parity Generator/Checker)

9-Bit Odd/Even Parity Generator/Checker

Default Signal Levels:	GND--all input pins

Function Prototype:

FUNCTION 74280B (d[8..0])

RETURNS (evns, odds);

Inputs	|	Outputs

# of Hs at D0 through D8	|	EVNS	ODDS

Even	|	H	L

Odd	|	L	H

See also:

Bus-to-Macrofunction Connections

Macrofunctions (by function)

Parity Generator/Checker Macrofunctions


 74373B (Latch)

Octal Transparent D-Type Latch with Tri-State Outputs

Default Signal Levels:	GND--all input pins

Function Prototype:

FUNCTION 74373B (oen, g, d[8..1])

RETURNS (q[8..1]);

Inputs	|	Outputs

OEN	G	D	|	Q

H	X	X	|	Z

L	H	H	|	H

L	H	L	|	L

L	L	X	|	Qo

See also:

Bus-to-Macrofunction Connections

Latch Macrofunctions

Macrofunctions (by function)


 74374B (Register)

Octal D-Type Flipflop with Tri-State Outputs and Output Enable

Default Signal Levels:	GND--all input pins

Function Prototype:

FUNCTION 74374B (clk, oen, d[8..1])

RETURNS (q[8..1]);

Inputs	|	Outputs

OEN	CLK	D	|	Q

H	X	X	|	Z

L	H	|	H

L	L	|	L

L	L	X	|	Qo

See also:

Bus-to-Macrofunction Connections

Macrofunctions (by function)

Register Macrofunctions


 74377B (Register)

Octal D-Type Flipflop with Enable

Default Signal Levels:	GND--EN, CLK

VCC--D1, D2 ,D3, D4, D5, D6, D7, D8

Function Prototype:

FUNCTION 74377B (en, clk, d[8..1])

RETURNS (q[8..1]);

Inputs	|	Outputs

EN	CLK	D	|	Q

H	X	X	|	Qo

L	H	|	H

L	L	|	L

X	L	X	|	Qo

See also:

Bus-to-Macrofunction Connections

Macrofunctions (by function)

Register Macrofunctions


 74518B (Comparator)

8-Bit Identity Comparator

Default Signal Levels:	GND--all input pins

Function Prototype:

FUNCTION 74518B (p[7..0], q[7..0], gn)

RETURNS (pq);

Inputs	|	Output

Data	Enable	|

P, Q	GN	|	PQ

P = Q	L	|	H

P > Q	L	|	L

P < Q	L	|	L

X	H	|	L

See also:

Bus-to-Macrofunction Connections

Comparator Macrofunctions

Macrofunctions (by function)


 74821B (Register)

10-Bit D-Type Flipflop with Tri-State Outputs

Default Signal Levels:	GND--OEN, CLK

VCC--D[10..1]

Function Prototype:

FUNCTION 74821B (d[10..1], oen, clk)

RETURNS (q[10..1]);

Inputs	|	Outputs

OEN	CLK	D	|	Q

H	X	X	|	Z

L	H	|	H

L	L	|	L

L	L	X	|	Qo

See also:

Bus-to-Macrofunction Connections

Macrofunctions (by function)

Register Macrofunctions


 74822B (Register)

10-Bit D-Type Inverting Flipflop with Tri-State Inverting Outputs

Default Signal Levels:	GND--OEN, CLK

VCC--DN[10..1]

Function Prototype:

FUNCTION 74822B (dn[10..1], oen, clk)

RETURNS (q[10..1]);

Inputs	|	Outputs

OEN	CLK	DN	|	Q

H	X	X	|	Z

L	L	|	H

L	H	|	L

L	L	X	|	Qo

See also:

Bus-to-Macrofunction Connections

Macrofunctions (by function)

Register Macrofunctions


 74823B (Register)

9-Bit D-Type Flipflop with Tri-State Outputs

Default Signal Levels:	GND--OEN, CLK, CLKENN

VCC--D[9..1], CLRN

Function Prototype:

FUNCTION 74823B (d[9..1], oen, clk, clrn, clkenn)

RETURNS (q[9..1]);

Inputs	|	Outputs

OEN	CLRN	CLKENN	CLK	D	|	Q

L	L	X	X	X	|	L

L	H	L	H	|	H

L	H	L	L	|	L

L	H	H	X	X	|	Qo

H	X	X	X	X	|	Z

See also:

Bus-to-Macrofunction Connections

Macrofunctions (by function)

Register Macrofunctions


 74824B (Register)

9-Bit D-Type Inverting Flipflop with Tri-State Inverting Outputs

Default Signal Levels:	GND--OEN, CLK, CLKENN

VCC--DN[9..1], CLRN

Function Prototype:

FUNCTION 74824B (dn[9..1], oen, clk, clrn, clkenn)

RETURNS (q[9..1]);

Inputs	|	Outputs

OEN	CLRN	CLKENN	CLK	DN	|	Q

L	L	X	X	X	|	L

L	H	L	L	|	H

L	H	L	H	|	L

L	H	H	X	X	|	Qo

H	X	X	X	X	|	Z

See also:

Bus-to-Macrofunction Connections

Macrofunctions (by function)

Register Macrofunctions


 74825B (Register)

Octal D-Type Flipflop with Tri-State Outputs

Default Signal Levels:	GND--OE1N, OE2N, OE3N, CLK, CLKENN

VCC--D[8..1], CLRN

Function Prototype:

FUNCTION 74825B (d[8..1], oe1n, oe2n, oe3n, clk, clrn, clkenn)

RETURNS (q[8..1]);

Inputs	|	Outputs

OEN*	CLRN	CLKENN	CLK	D	|	Q

L	L	X	X	X	|	L

L	H	L	H	|	H

L	H	L	L	|	L

L	H	H	X	X	|	Qo

H	X	X	X	X	|	Z

*	OEN = /OE1N & /OE2N & /OE3N

See also:

Bus-to-Macrofunction Connections

Macrofunctions (by function)

Register Macrofunctions


 74826B (Register)

Octal D-Type Inverting Flipflop with Tri-State Inverting Outputs

Default Signal Levels:	GND--OE1N, OE2N, OE3N, CLK, CLKENN

VCC--DN[8..1], CLRN

Function Prototype:

FUNCTION 74826B (dn[8..1], oe1n, oe2n, oe3n, clk, clrn, clkenn)

RETURNS (q[8..1]);

Inputs	|	Outputs

OEN*	CLRN	CLKENN	CLK	DN	|	Q

L	L	X	X	X	|	L

L	H	L	L	|	H

L	H	L	H	|	L

L	H	H	X	X	|	Qo

H	X	X	X	X	|	Z

*	OEN = /OE1N & /OE2N & /OE3N

See also:

Bus-to-Macrofunction Connections

Macrofunctions (by function)

Register Macrofunctions


 74841B (Latch)

10-Bit D-Type Latch with Tri-State Outputs

Default Signal Levels:	GND--OEN, C

VCC--D[10..1]

Function Prototype:

FUNCTION 74841B (d[10..1], oen, c)

RETURNS (q[10..1]);

Inputs	|	Outputs

OEN	C	D	|	Q

H	X	X	|	Z

L	H	L	|	L

L	H	H	|	H

L	L	X	|	Qo

See also:

Bus-to-Macrofunction Connections

Latch Macrofunctions

Macrofunctions (by function)


 74842B (Latch)

10-Bit D-Type Inverting Latch with Tri-State Outputs

Default Signal Levels:	GND--OEN, C

VCC--DN[10..1]

Function Prototype:

FUNCTION 74824B (dn[10..1], oen, c)

RETURNS (q[10..1]);

Inputs	|	Outputs

OEN	C	D	|	Q

H	X	X	|	Z

L	H	L	|	H

L	H	H	|	L

L	L	X	|	Qo

See also:

Bus-to-Macrofunction Connections

Latch Macrofunctions

Macrofunctions (by function)


BARRELST (Shift Register)

8-Bit Barrel Shifter

Default Signal Levels:	VCC--all input pins

Function Prototype:

FUNCTION BARRELST (s[2..0], ldst, a, b, c, d, e, f, g, h, clk)

RETURNS (qa, qb, qc, qd, qe, qf, qg, qh);

Inputs	|	Outputs

S2	S1	S0	LDST	A..H	CLK	|	QA	QB..QG	QH

X	X	X	X	X	L	|	QAo	QBo..QGo	QHo

X	X	X	H	a..h	|	a	b..g	h

L	L	L	L	X	|	QAn	QBn..QGn	QHn

L	L	H	L	X	|	QBn	QCn..QHn	QAn

L	H	L	L	X	|	QCn	QDn..QAn	QBn

L	H	H	L	X	|	QDn	QEn..QBn	QCn

H	L	L	L	X	|	QEn	QFn..QCn	QDn

H	L	H	L	X	|	QFn	QGn..QDn	QEn

H	H	L	L	X	|	QGn	QHn..QEn	QFn

H	H	H	L	X	|	QHn	QAn..QFn	QGn

See also:

Macrofunctions (by function)

Shift Register Macrofunctions


BTRI (Buffer)

Active-Low Tri-State Buffer

Default Signal Levels:	VCC--all input pins

Function Prototype:

FUNCTION BTRI (oen, in)

   RETURNS (out);

Inputs	|	Output

OEN	IN	|	OUT

L	L	|	L

L	H	|	H

H	L	|	Z

H	H	|	Z

The BTRI macrofunction is an active-low version of the TRI primitive.

See also:

Buffer Macrofunctions

Macrofunctions (by function)


CBUF (SSI Function)

Complementary Buffer

Default Signal Levels:	GND--all input pins

Function Prototype:

FUNCTION CBUF (1)

RETURNS (2, 3);

Inputs	|	Outputs

DATA	|	OUT	/OUT

L	|	L	H

H	|	H	L

See also:

Macrofunctions (by function)

SSI Functions


ENADFF (Register)

Enabled D-Type Flipflop

Default Signal Levels:	GND--CLK

VCC--PRN, D, ENA, CLRN

Function Prototype:

FUNCTION ENADFF (d, clk, clrn, prn, ena)

RETURNS (q);

Inputs	|	Output

CLRN	PRN	ENA	D	CLK	|	Q

L	H	X	X	X	|	L

H	L	X	X	X	|	H

L	L	X	X	X	|	Illegal

H	H	L	X	X	|	Qo

H	H	H	L	|	L

H	H	H	H	|	H

H	H	X	X	L	|	Qo

The DFFE primitive has the same functionality as  the ENADFF macrofunction.

See also:

Macrofunctions (by function)

Register Macrofunctions


EXPDFF (Register)

D-Type Flipflop Implemented with Expanders (or with DFF Primitive for FLEX 8000 Projects) Note

Default Signal Levels:	GND--CLK

VCC--PRN, D, CLRN

1.	For non-FLEX 8000 projects, you should only use the EXPDFF macrofunction to provide additional registers in the device when all macrocells are used. Registers created with EXPDFF macrofunctions have lower speed performance than registers created with DFF primitives. For FLEX 8000 projects, the EXPDFF macrofunction has no advantage over the DFF primitive.

2.	Do not create your own cross-coupled structures; use only the EXPDFF, EXPLATCH, INPLTCH, NANDLTCH, and NORLTCH macrofunctions provided with the MAX+PLUS II Macrofunction Library. (These macrofunctions are not optimized for FLEX 8000 architecture.) Avoid tying multiple instances of EXPDFF, EXPLATCH, INPLTCH, NANDLTCH, and NORLTCH macrofunctions together. Multiple instances of these macrofunctions should always be separated by LCELL primitives.

Function Prototype:

FUNCTION EXPDFF (d, clk, clrn, prn)

RETURNS (q, /q);

This macrofunction is not directly supported by VHDL because it contains one or more port names with a slash (/) or dash (-). These characters are illegal in VHDL port names. However, you can use this macrofunction in your project by incorporating it into a lower-level design file, then inserting an instance of the lower-level file into your VHDL Design File. See Using a MAX+PLUS II Primitive or Macrofunction for more information.

Inputs	|	Outputs

CLRN	PRN	D	CLK	|	Q	/Q

L	H	X	X	|	L	H

H	L	X	X	|	H	L

L	L	X	X	|	Illegal	Illegal

H	H	L	|	L	H

H	H	H	|	H	L

H	H	X	L	|	Qo	/Qo

See also:

Macrofunctions (by function)

Register Macrofunctions

Recommended reading:

AN26 (EPLD/MPLD Design Guidelines)


EXPLATCH (Latch)

Latch Implemented with Expanders

Default Signal Levels:	VCC--all input pins

Function Prototype:

FUNCTION EXPLATCH (d, ena)

RETURNS (q);

1.	For non-FLEX 8000 projects, you should only use the EXPLATCH macrofunction to provide additional latches in the device when all macrocells are used. Latches created with EXPLATCH macrofunctions have lower speed performance than latches created with LATCH primitives. For FLEX 8000 projects, the EXPLATCH macrofunction has no advantage over the LATCH primitive.

2.	Do not create your own cross-coupled structures; use only the EXPDFF, EXPLATCH, INPLTCH, NANDLTCH, and NORLTCH macrofunctions provided with the MAX+PLUS II Macrofunction Library. (These macrofunctions are not optimized for FLEX 8000 architecture.) Avoid tying multiple instances of EXPDFF, EXPLATCH, INPLTCH, NANDLTCH, and NORLTCH macrofunctions together. Multiple instances of these macrofunctions should always be separated by LCELL primitives.

Inputs	|	Output

ENA	D	|	Q

L	X	|	Qo

H	L	|	L

H	H	|	H

See also:

Latch Macrofunctions

Macrofunctions (by function)

Recommended reading:

AN17 (Integrating an Intelligent I/O Subsystem with a Single EPM5130 MAX EPLD)

AN26 (EPLD/MPLD Design Guidelines)

AB9 (Asynchronous Latches in Classic, MAX & STG EPLDs)


FREQDIV (Frequency Divider)

Frequency Divider

Default Signal Levels:	GND--all input pins

Function Prototype:

FUNCTION FREQDIV (clr, clk, g)

RETURNS (dv2, dv4, dv8, dv16);

Inputs	|	Outputs

CLR	CLK	G	|	DV2	DV4	DV8	DV16

H	X	X	|	L	L	L	L

L	L	|	Hold

L	H	|	Divide

See also:

Frequency Divider Macrofunctions

Macrofunctions (by function)


GRAY4 (Counter)

Gray-Code Counter Note

Default Signal Levels:	GND--CLK

VCC--ENA

Function Prototype:

FUNCTION GRAY4 (clk, ena)

RETURNS (qd, qc, qb, qa);

Inputs	|	Outputs

CLK	ENA	|	QD	QC	QB	QA

X	L	|	Hold Count

H	|	L	L	L	L

H	|	L	L	L	H

H	|	L	L	H	H

H	|	L	L	H	L

H	|	L	H	H	L

H	|	L	H	H	H

H	|	L	H	L	H

H	|	L	H	L	L

H	|	H	H	L	L

H	|	H	H	L	H

H	|	H	H	H	H

H	|	H	H	H	L

H	|	H	L	H	L

H	|	H	L	H	H

H	|	H	L	L	H

H	|	H	L	L	L

See also:

Counter Macrofunctions

Macrofunctions (by function)


INHB (SSI Function)

Inhibit Gate

Default Signal Levels:	VCC--all input pins

Function Prototype:

FUNCTION INHB (2, 3)

RETURNS (1);

Inputs	|	Output

2	3	|	1

L	L	|	L

L	H	|	L

H	L	|	H

H	H	|	L

See also:

Macrofunctions (by function)

SSI Functions


INPLTCH (Latch)

Input Latch Implemented with Expanders

Default Signal Levels:	VCC--all input pins

Function Prototype:

FUNCTION INPLTCH (d, g)

RETURNS (q);

1.	For non-FLEX 8000 projects, you should only use the INPLATCH macrofunction to provide additional latches in the device when all macrocells are used. Latches created with INPLATCH macrofunctions have lower speed performance than latches created with LATCH primitives. For FLEX 8000 projects, the INPLATCH macrofunction has no advantage over the LATCH primitive.

2.	Do not create your own cross-coupled structures; use only the EXPDFF, EXPLATCH, INPLTCH, NANDLTCH, and NORLTCH macrofunctions provided with the MAX+PLUS II Macrofunction Library. (These macrofunctions are not optimized for FLEX 8000 architecture.) Avoid tying multiple instances of EXPDFF, EXPLATCH, INPLTCH, NANDLTCH, and NORLTCH macrofunctions together. Multiple instances of these macrofunctions should always be separated by LCELL primitives.

Inputs	|	Output

D	G	|	Q

X	L	|	Qo

L	H	|	L

H	H	|	H

See also:

Latch Macrofunctions

Macrofunctions (by function)


MULT2 (Multiplier)

2-Bit Sign Magnitude Multiplier

Default Signal Levels:	GND--A0, B0, A1, B1, A2, B2

VCC--G

Function Prototype:

FUNCTION MULT2 (a[2..0], b[2..0], g)

RETURNS (y[4..0]);

Inputs	|	Outputs

A2*	A1	A0	B2*	B1	B0	G	|	Y4*	Y3	Y2	Y1	Y0

X	X	X	X	X	X	L	|	L	L	L	L	L

L	a1	a0	L	b1	b0	H	|	L

L	a1	a0	H	b1	b0	H	|	H	A multiplied by B

H	a1	a0	L	b1	b0	H	|	H

H	a1	a0	H	b1	b0	H	|	L

*	Sign bits for sign-magnitude multiplication.

See also:

Macrofunctions (by function)

Multiplier Macrofunctions


MULT24 (Multiplier)

2-Bit-by-4-Bit Parallel Binary Multiplier

Default Signal Levels:	GND--A1, A2, A3, A4, A5, B1, B2, B3

VCC--G

Function Prototype:

FUNCTION MULT24 (a[5..1], b[3..1], g)

RETURNS (y[7..1]);

Inputs	|	Outputs

A5*	A4	A3	A2	A1	B3*	B2	B1	G	|	Y7*	Y6	Y5	Y4	Y3	Y2	Y1

X	X	X	X	X	X	X	X	L	|	L	L	L	L	L	L	L

L	a4	a3	a2	a1	L	b2	b1	H	|	L

L	a4	a3	a2	a1	H	b2	b1	H	|	H	A multiplied by B

H	a4	a3	a2	a1	L	b2	b1	H	|	H

H	a4	a3	a2	a1	H	b2	b1	H	|	L

*	Sign bits for sign-magnitude multiplication.

See also:

Macrofunctions (by function)

Multiplier Macrofunctions


MULT4 (Multiplier)

4-Bit Parallel Binary Multiplier

Default Signal Levels:	GND--A1, A2, A3, A4, A5, B1, B2, B3, B4, B5

VCC--G

Function Prototype:

FUNCTION MULT4 (a[5..1], b[5..1], g)

RETURNS (y[9..1]);

Inputs	|	Outputs

A5*	A4..A1	B5*	B4..B1	G	|	Y9*	Y8..Y1

X	X	X	X	X	X	L	|	L	L..L

L	a4	a1	L	b4	b1	H	|	L

L	a4	a1	H	b4	b1	H	|	H	A multiplied by B

H	a4	a1	L	b4	b1	H	|	H

H	a4	a1	H	b4	b1	H	|	L

*	Sign bits for sign-magnitude multiplication.

See also:

Macrofunctions (by function)

Multiplier Macrofunctions


NANDLTCH (Latch)

/SR NAND Latch Implemented with Expanders

Default Signal Levels:	VCC--all input pins

Function Prototype:

FUNCTION NANDLTCH (sn, rn)

RETURNS (q, qn);

1.	For non-FLEX 8000 projects, you should only use the NANDLTCH macrofunction to provide additional latches in the device when all macrocells are used. Latches created with NANDLTCH macrofunctions have lower speed performance than latches created with LATCH primitives. For FLEX 8000 projects, the NANDLTCH macrofunction has no advantage over the LATCH primitive.

2.	Do not create your own cross-coupled structures; use only the EXPDFF, EXPLATCH, INPLTCH, NANDLTCH, and NORLTCH macrofunctions provided with the MAX+PLUS II Macrofunction Library. (These macrofunctions are not optimized for FLEX 8000 architecture.) Avoid tying multiple instances of EXPDFF, EXPLATCH, INPLTCH, NANDLTCH, and NORLTCH macrofunctions together. Multiple instances of these macrofunctions should always be separated by LCELL primitives.

Inputs	|	Outputs

SN	RN	|	Q	QN

L	L	|	H	H

L	H	|	H	L

H	L	|	L	H

H	H	|	Q	QN

See also:

Latch Macrofunctions

Macrofunctions (by function)

Recommended reading:

AN26 (EPLD/MPLD Design Guidelines)

AB9 (Asynchronous Latches in Classic, MAX & STG EPLDs)


NORLTCH (Latch)

SR NOR Latch Implemented with Expanders

Default Signal Levels:	VCC--all input pins

Function Prototype:

FUNCTION NORLTCH (s, r)

RETURNS (q, qn);

1.	For non-FLEX 8000 projects, you should only use the NORLTCH macrofunction to provide additional latches in the device when all macrocells are used. Latches created with NORLTCH macrofunctions have lower speed performance than latches created with LATCH primitives. For FLEX 8000 projects, the NORLTCH macrofunction has no advantage over the LATCH primitive.

2.	Do not create your own cross-coupled structures; use only the EXPDFF, EXPLATCH, INPLTCH, NANDLTCH, and NORLTCH macrofunctions provided with the MAX+PLUS II Macrofunction Library. (These macrofunctions are not optimized for FLEX 8000 architecture.) Avoid tying multiple instances of EXPDFF, EXPLATCH, INPLTCH, NANDLTCH, and NORLTCH macrofunctions together. Multiple instances of these macrofunctions should always be separated by LCELL primitives.

Inputs	|	Outputs

S	R	|	Q	QN

L	L	|	Q	QN

L	H	|	L	H

H	L	|	H	L

H	H	|	H	H

See also:

Latch Macrofunctions

Macrofunctions (by function)

Recommended reading:

AN26 (EPLD/MPLD Design Guidelines)

AB9 (Asynchronous Latches in Classic, MAX & STG EPLDs)

AB95 (Designing Phase-Locked Loops with Altera EPLDs)


TMULT4 (Multiplier)

4-Bit-by-4-Bit Parallel Binary Multiplier

Default Signal Levels:	GND--GAN, GBN

VCC--A1, A2, A3, A4, B1, B2, B3, B4, A5, B5

Function Prototype:

FUNCTION TMULT4 (gan, gbn, a[5..1], b[5..1])

RETURNS (y[9..1]);

Inputs	|	Outputs

GAN	GBN	A5..A1	B5..B1	|	Y9..Y1

H	H	X	X	|	000000000

H	L	X	X	|	000000000

L	H	X	X	|	000000000

L	L	00001	00001	|	000000001	(Y = A * B)

.	.	|

.	.	|

.	.	|

L	L	00100	00011	|	000001100	(12 = 4 * 3)

See also:

Macrofunctions (by function)

Multiplier Macrofunctions


UNICNT (Counter)

Universal 4-Bit Up/Down Counter Left/Right Shift Register with Asynchronous Set and Load, Clear, and Cascade

Default Signal Levels:	GND--LOAD, A, B, C, D, DATA, SET, CLR, CLK

VCC--CTST, DNUP, RTLT, CIN

Function Prototype:

FUNCTION UNICNT (clk, clr, set, load, ctst, dnup, rtlt, cin, data, d, c, b, a)

RETURNS (qd, qc, qb, qa, cout);

Inputs	|	Outputs

CLK	CLR	SET	LOAD	CTST	DNUP	RTLT	CIN	|	QD	QC	QB	QA	COUT

X	H	X	X	X	X	X	X	|	L	L	L	L	X

X	L	H	X	X	X	X	X	|	H	H	H	H	X

X	L	L	H	X	X	X	X	|	d	c	b	a	X

L	L	L	H	L	X	H	|	Count Up	X

L	L	L	H	L	X	L	|	Hold	X

L	L	L	H	H	X	H	|	Count Down	X

L	L	L	H	H	X	L	|	Hold	X

L	L	L	L	X	H	X	|	QCn	QBn	QAn	Data	X

L	L	L	L	X	L	X	|	Data	QDn	QCn	QBn	X

L	L	L	H	L	X	H	|	H	H	H	H	H

L	L	L	H	H	X	H	|	L	L	L	L	H

See also:

Counter Macrofunctions

Macrofunctions (by function)


16CUDSLR (Counter)

16-Bit Binary Up/Down Counter Left/Right Shift Register with Asynchronous Set

Default Signal Levels:	GND--STCT, DATA, LTRT, DNUP, CLK

VCC--SETN, CLRN

Function Prototype:

FUNCTION 16CUDSLR (clk, clrn, setn, data, stct, dnup, ltrt)

RETURNS (q[16..1]);

Inputs (1)	|	Operation

CLRN	SETN	STCT	DNUP	LTRT	|	Q

L	X	X	X	X	|	Clear all outputs to low level

H	L	X	X	X	|	Reset all outputs to high level

H	H	H	X	H	|	Shift Left

H	H	H	X	L	|	Shift Right

H	H	L	H	X	|	Count Down

H	H	L	L	X	|	Count Up

See also:

Counter Macrofunctions

Macrofunctions (by function)


Note: 16CUDSLR
The DATA input loads data into the shift register.


16DMUX (Decoder)

4-Bit Binary-to-16-Line Decoder

Default Signal Levels:	GND--all input pins

Function Prototype:

FUNCTION 16DMUX (d, c, b, a)

RETURNS (q[15..0])

Inputs	|	Outputs

D	C	B	A	|	Q15	Q14	Q13	Q12	Q11	Q10	Q9	Q8	Q7	Q6	Q5	Q4	Q3	Q2	Q1	Q0

L	L	L	L	|	L	L	L	L	L	L	L	L	L	L	L	L	L	L	L	H

L	L	L	H	|	L	L	L	L	L	L	L	L	L	L	L	L	L	L	H	L

L	L	H	L	|	L	L	L	L	L	L	L	L	L	L	L	L	L	H	L	L

L	L	H	H	|	L	L	L	L	L	L	L	L	L	L	L	L	H	L	L	L

L	H	L	L	|	L	L	L	L	L	L	L	L	L	L	L	H	L	L	L	L

L	H	L	H	|	L	L	L	L	L	L	L	L	L	L	H	L	L	L	L	L

L	H	H	L	|	L	L	L	L	L	L	L	L	L	H	L	L	L	L	L	L

L	H	H	H	|	L	L	L	L	L	L	L	L	H	L	L	L	L	L	L	L

H	L	L	L	|	L	L	L	L	L	L	L	H	L	L	L	L	L	L	L	L

H	L	L	H	|	L	L	L	L	L	L	H	L	L	L	L	L	L	L	L	L

H	L	H	L	|	L	L	L	L	L	H	L	L	L	L	L	L	L	L	L	L

H	L	H	H	|	L	L	L	L	H	L	L	L	L	L	L	L	L	L	L	L

H	H	L	L	|	L	L	L	H	L	L	L	L	L	L	L	L	L	L	L	L

H	H	L	H	|	L	L	H	L	L	L	L	L	L	L	L	L	L	L	L	L

H	H	H	L	|	L	H	L	L	L	L	L	L	L	L	L	L	L	L	L	L

H	H	H	H	|	H	L	L	L	L	L	L	L	L	L	L	L	L	L	L	L

See also:

Decoder Macrofunctions

Macrofunctions (by function)


16NDMUX (Decoder)

4-Bit Binary-to-16-Line Decoder

Default Signal Levels:	GND--all input pins

Function Prototype:

FUNCTION 16NDMUX (d, c, b, a)

RETURNS (qn[15..0]);

Inputs	|	Outputs

D	C	B	A	|	QN15	QN14	QN13	QN12	QN11	QN10	QN9	QN8	QN7	QN6	QN5	QN4	QN3	QN2	QN1	QN0

L	L	L	L	|	H	H	H	H	H	H	H	H	H	H	H	H	H	H	H	L

L	L	L	H	|	H	H	H	H	H	H	H	H	H	H	H	H	H	H	L	H

L	L	H	L	|	H	H	H	H	H	H	H	H	H	H	H	H	H	L	H	H

L	L	H	H	|	H	H	H	H	H	H	H	H	H	H	H	H	L	H	H	H

L	H	L	L	|	H	H	H	H	H	H	H	H	H	H	H	L	H	H	H	H

L	H	L	H	|	H	H	H	H	H	H	H	H	H	H	L	H	H	H	H	H

L	H	H	L	|	H	H	H	H	H	H	H	H	H	L	H	H	H	H	H	H

L	H	H	H	|	H	H	H	H	H	H	H	H	L	H	H	H	H	H	H	H

H	L	L	L	|	H	H	H	H	H	H	H	L	H	H	H	H	H	H	H	H

H	L	L	H	|	H	H	H	H	H	H	L	H	H	H	H	H	H	H	H	H

H	L	H	L	|	H	H	H	H	H	L	H	H	H	H	H	H	H	H	H	H

H	L	H	H	|	H	H	H	H	L	H	H	H	H	H	H	H	H	H	H	H

H	H	L	L	|	H	H	H	L	H	H	H	H	H	H	H	H	H	H	H	H

H	H	L	H	|	H	H	L	H	H	H	H	H	H	H	H	H	H	H	H	H

H	H	H	L	|	H	L	H	H	H	H	H	H	H	H	H	H	H	H	H	H

H	H	H	H	|	L	H	H	H	H	H	H	H	H	H	H	H	H	H	H	H

See also:

Decoder Macrofunctions

Macrofunctions (by function)


21MUX (Multiplexer)

2-Line-to-1-Line Multiplexer

Default Signal Levels:	VCC--all input pins

Function Prototype:

FUNCTION 21MUX (s, a, b)

RETURNS (y);

Inputs	|	Output

S	A	B	|	Y

L	X	H	|	H

L	X	L	|	L

H	H	X	|	H

H	L	X	|	L

See also:

Macrofunctions (by function)

Multiplexer Macrofunctions


161MUX (Multiplexer)

16-Line-to-1-Line Multiplexer

Default Signal Levels:	VCC--GN, SEL[3..0], IN[15..0]

Function Prototype:

FUNCTION 161MUX (gn, sel[3..0], in[15..0])

RETURNS (out);

Inputs	|	Output

GN	SEL3	SEL2	SEL1	SEL0	|	OUT

0	0	0	0	0	|	IN0

0	0	0	0	1	|	IN1

0	0	0	1	0	|	IN2

0	0	0	1	1	|	IN3

0	0	1	0	0	|	IN4

0	0	1	0	1	|	IN5

0	0	1	1	0	|	IN6

0	0	1	1	1	|	IN7

0	1	0	0	0	|	IN8

0	1	0	0	1	|	IN9

0	1	0	1	0	|	IN10

0	1	0	1	1	|	IN11

0	1	1	0	0	|	IN12

0	1	1	0	1	|	IN13

0	1	1	1	0	|	IN14

0	1	1	1	1	|	IN15

1	X	X	X	X	|	0

See also:

Macrofunctions (by function)

Multiplexer Macrofunctions


2X8MUX (Multiplexer)

2-Line-to-1-Line Multiplexer for 8-Bit Buses

Default Signal Levels:	VCC--all input pins

Function Prototype:

FUNCTION 2X8MUX (sel, a[7..0], b[7..0])

RETURNS (y[7..0]);

Inputs	|	Outputs

SEL	A[7..0]	B[7..0]	|	Y[7..0]

H	a[7..0]	b[7..0]	|	a[7..0]

L	a[7..0]	b[7..0]	|	b[7..0]

See also:

Macrofunctions (by function)

Multiplexer Macrofunctions


4COUNT (Counter)

4-Bit Binary Up/Down Counter with Synchronous Load (LDN), Asynchronous Clear, and Asynchronous Load (SETN)

Default Signal Levels:	GND--A, B, C, D, CLK

VCC--LDN, CIN, DNUP, SETN, CLRN

Function Prototype:

FUNCTION 4COUNT (clk, clrn, setn, ldn, cin, dnup, d, c, b, a)

RETURNS (qd, qc, qb, qa, cout);

Inputs	|	Outputs

CLK	CLRN	SETN	LDN	CIN	DNUP	D	C	B	A	|	QD	QC	QB	QA	COUTNote4

X	L	X	X	X	X	|	L	L	L	L	X

X	H	L	X	X	X	|	H	H	H	H	X

H	H	L	X	X	d	c	b	a	|	d	c	b	a	X

H	H	H	L	X	|	Hold	X

H	H	H	H	H	|	Count Down	L

H	H	H	H	L	|	Count Up	 	L

X	X	X	X	H	H	|	L	L	L	L	H

X	X	X	X	H	L	|	H	H	H	H	H

See also:

Counter Macrofunctions

Macrofunctions (by function)


Note

The condition of the COUT output is dependent on the condition of the CIN input.


81MUX (Multiplexer)

8-Line-to-1-Line Multiplexer Note

Default Signal Levels:	GND--all input pins

Function Prototype:

FUNCTION 81mux (d0, d1, d2, d3, d4, d5, d6, d7, a, b, c, gn)

RETURNS (wn, y);

Inputs	|	Outputs

Select	|	Enable	|

C	B	A	|	GN	|	Y	WN

X	X	X	|	H	|	L	H

L	L	L	|	L	|	D0	/D0

L	L	H	|	L	|	D1	/D1

L	H	L	|	L	|	D2	/D2

L	H	H	|	L	|	D3	/D3

H	L	L	|	L	|	D4	/D4

H	L	H	|	L	|	D5	/D5

H	H	L	|	L	|	D6	/D6

H	H	H	|	L	|	D7	/D7

See also:

Macrofunctions (by function)

Multiplexer Macrofunctions


8COUNT (Counter)

8-Bit Binary Up/Down Counter with Synchronous Load (LDN), Asynchronous Clear, and Asynchronous Load (SETN) Note

Default Signal Levels:	GND--A, B, C, D, E, F, G, H, GN, CLK

VCC--LDN, DNUP, SETN, CLRN

Function Prototype:

FUNCTION 8COUNT (clk, clrn, setn, ldn, dnup, gn, h, g, f, e, d, c, b, a)

RETURNS (qh, qg, qf, qe, qd, qc, qb, qa, cout);

Inputs	|	Outputs

CLK	CLRN	SETN	LDN	DNUP	GN	|	QH	QG..QB	QA

X	L	H	X	X	X	|	L	L..L	L

X	H	L	X	X	X	|	h	g..b	a

H	H	L	X	X	|	h	g..b	a

H	H	H	H	L	|	Count Down

H	H	H	L	L	|	Count Up

H	H	H	X	H	|	Hold Count

Inputs	|	Outputs

DNUP	LDN*	GN	QH	QG..QB	QA	|	COUT

L	H	L	H	H..H	H	|	H

H	H	L	L	L..L	L	|	H

Others	|	L

* FLEX 8000 devices do not include LDN in COUT equation.

See also:

Counter Macrofunctions

Macrofunctions (by function)


8count note
Note (1)

These conditions are rollover conditions that affect the COUT output.


8FADD (Full Adder)

8-Bit Full Adder Note

Default Signal Levels:	GND--all input pins

Function Prototype:

FUNCTION 8FADD (cin, a[8..1], b[8..1])

RETURNS (cout, sum[8..1]);

Inputs	|	Outputs

CIN	A8 .. A1	B8 .. B1	|	SUM8 .. SUM1

L	00000000	00000000	|	00000000

H	00000000	00000000	|	00000001 (CIN  +  A  +  B  =  SUM)

.	.	|	.

.	.	|	.

.	.	|	.

H	00001001	00011000	|	00100010 (1  +  9  +  24  =  34)

.	.	|	.

.	.	|	.

.	.	|	.

See also:

Adder Macrofunctions

Macrofunctions (by function)


8MCOMP (Comparator)

8-Bit Magnitude Comparator Note

Default Signal Levels:	GND--all input pins

Function Prototype:

FUNCTION 8MCOMP (a[7..0], b[7..0])

RETURNS (altb, aeqb, agtb, aeb[7..0]);

Inputs	|	Outputs

A	B	|	ALTB	AEQB	AGTB	AEBx

A	=	B	|	L	H	L

A	<	B	|	H	L	L

A	>	B	|	L	L	H

Ax	=	Bx*	|	H

Ax	!=	Bx*	|	L

*	x = Bit position

See also:

Comparator Macrofunctions

Macrofunctions (by function)


7400 (SSI Function)

NAND2 Gate

Default Signal Levels:	VCC--all input pins

Function Prototype:

FUNCTION 7400 (2, 3)

RETURNS (1);

Inputs	|	Output

A	B	|	OUT

L	L	|	H

H	L	|	H

L	H	|	H

H	H	|	L

See also:

Macrofunctions (by function)

SSI Functions


7402 (SSI Function)

NOR2 Gate

Default Signal Levels:	GND--all input pins

Function Prototype:

FUNCTION 7402 (2, 3)

RETURNS (1);

Inputs	|	Output

A	B	|	OUT

L	L	|	H

H	L	|	L

L	H	|	L

H	H	|	L

See also:

Macrofunctions (by function)

SSI Functions


7404 (SSI Function)

NOT Gate

Default Signal Levels:	GND--all input pins

Function Prototype:

FUNCTION 7404 (2)

RETURNS (1);

Input	|	Output

L	|	H

H	|	L

See also:

Macrofunctions (by function)

SSI Functions


7408 (SSI Function)

AND2 Gate

Default Signal Levels:	VCC--all input pins

Function Prototype:

FUNCTION 7408 (2, 3)

RETURNS (1);

Inputs	|	Output

A	B	|	OUT

L	L	|	L

H	L	|	L

L	H	|	L

H	H	|	H

See also:

Macrofunctions (by function)

SSI Functions


7410 (SSI Function)

NAND3 Gate

Default Signal Levels:	VCC--all input pins

Function Prototype:

FUNCTION 7410 (2, 3, 4)

RETURNS (1);

Inputs	|	Output

A	B	C	|	OUT

L	L	L	|	H

H	L	L	|	H

L	H	L	|	H

H	H	L	|	H

L	L	H	|	H

H	L	H	|	H

L	H	H	|	H

H	H	H	|	L

See also:

Macrofunctions (by function)

SSI Functions


74690 (Counter)

Synchronous Decade Counter with Output Registers, Multiplexed Tri-State Outputs, and Asynchronous Clear

Default Signal Levels:	GND--GN, RCLK, CCLK

VCC--R/CN, RCLRN, D0, D1, D2, D3, ENT, ENP, CCLRN, LDN

Function Prototype:

FUNCTION 74690 (gn, cclrn, ldn, enp, ent, rclrn, rclk, r/cn, cclk, d[3..0])

RETURNS (q[3..0], rco);

This macrofunction is not directly supported by VHDL because it contains one or more port names with a slash (/) or dash (-). These characters are illegal in VHDL port names. However, you can use this macrofunction in your project by incorporating it into a lower-level design file, then inserting an instance of the lower-level file into your VHDL Design File. See Using a MAX+PLUS II Primitive or Macrofunction for more information.

Inputs	|	Outputs

GN	CLRN	LDN	ENP	ENT	RCLRN	RCLK	R/CN	CCLK	D	|	Q	RCO

L	X	X	X	X	X	X	X	X	X..X	|	Z..Z

H	L	X	X	X	X	X	L	X	X..X	|	L..L	L

H	H	L	X	X	X	X	L	d..a	|	d..a

H	H	H	H	H	X	X	L	X..X	|	Count

H	H	H	H	H	X	X	L	L	X..X	|	Hold

H	H	X	X	X	X	X	X	X	X..X	|	H L L H	H

H	X	X	X	X	L	X	H	X	X..X	|	L..L

H	X	X	X	X	H	H	X	X..X	|	C3..C0*

*	C3..C0 are the outputs of the counter registers.

See also:

Counter Macrofunctions

Macrofunctions (by function)


74691 (Counter)

Synchronous Binary Counter with Output Registers, Multiplexed Tri-State Outputs, and Asynchronous Clear

Default Signal Levels:	GND--GN, RCLK, CCLK

VCC--R/CN, RCLRN, D0, D1, D2, D3, ENT, ENP, CCLRN, LDN

Function Prototype:

FUNCTION 74691 (gn, cclrn, ldn, enp, ent, rclrn, rclk, r/cn, cclk, d[3..0])

RETURNS (q[3..0], rco);

This macrofunction is not directly supported by VHDL because it contains one or more port names with a slash (/) or dash (-). These characters are illegal in VHDL port names. However, you can use this macrofunction in your project by incorporating it into a lower-level design file, then inserting an instance of the lower-level file into your VHDL Design File. See Using a MAX+PLUS II Primitive or Macrofunction for more information.

Inputs	|	Outputs

GN	CCLRN	LDN	ENP	ENT	RCLRN	RCLK	R/CN	CCLK	D	|	Q	RCO

L	X	X	X	X	X	X	X	X	X..X	|	Z..Z

H	L	X	X	X	X	X	L	X	X..X	|	L..L	L

H	H	L	X	X	X	X	L	d..a	|	d..a

H	H	H	H	H	X	X	L	X..X	|	Count

H	H	H	H	H	X	X	L	L	X..X	|	Hold

H	H	X	X	X	X	X	X	X	X..X	|	H..H	H

H	X	X	X	X	L	X	H	X	X..X	|	L..L

H	X	X	X	X	H	H	X	X..X	|	C3..C0*

*	C3..C0 are the outputs of the counter registers.

See also:

Counter Macrofunctions

Macrofunctions (by function)


74693 (Counter)

Synchronous Binary Counter with Output Registers, Multiplexed Tri-State Outputs, and Synchronous Clear

Default Signal Levels:	GND--GN, RCLK, CCLK

VCC--R/CN, RCLRN, D0, D1, D2, D3, ENT, ENP, CCLRN, LDN

Function Prototype:

FUNCTION 74693 (gn, cclrn, ldn, enp, ent, rclrn, rclk, r/cn, cclk, d[3..0])

RETURNS (q[3..0], rco);

This macrofunction is not directly supported by VHDL because it contains one or more port names with a slash (/) or dash (-). These characters are illegal in VHDL port names. However, you can use this macrofunction in your project by incorporating it into a lower-level design file, then inserting an instance of the lower-level file into your VHDL Design File. See Using a MAX+PLUS II Primitive or Macrofunction for more information.

Inputs	|	Outputs

GN	CCLRN	LDN	ENP	ENT	RCLRN	RCLK	R/CN	CCLK	D	|	Q	RCO

L	X	X	X	X	X	X	X	X	X..X	|	Z..Z

H	L	X	X	X	X	X	L	X..X	|	L..L	L

H	H	L	X	X	X	X	L	d..a	|	d..a

H	H	H	H	H	X	X	L	X..X	|	Count

H	H	H	H	H	X	X	L	L	X..X	|	Hold

H	H	X	X	X	X	X	X	X	X..X	|	H..H	H

H	X	X	X	X	L	H	X	X..X	|	L..L

H	X	X	X	X	H	H	X	X..X	|	C3..C0*

*	C3..C0 are the outputs of the counter registers.

See also:

Counter Macrofunctions

Macrofunctions (by function)


74696 (Counter)

Synchronous Decade Up/Down Counter with Output Registers, Multiplexed Tri-State Outputs, and Asynchronous Clear

Default Signal Levels:	GND--GN, RCLK, ENTN, ENPN, CCLK

VCC--R/CN, D0, D1, D2, D3, U/DN, CCLRN, LDN

Function Prototype:

FUNCTION 74696 (u/dn, r/cn, rclk, ldn, gn, entn, enpn, d3, d2, d1, d0, cclrn, cclk)

RETURNS (tcn, q3, q2, q1, q0);

This macrofunction is not directly supported by VHDL because it contains one or more port names with a slash (/) or dash (-). These characters are illegal in VHDL port names. However, you can use this macrofunction in your project by incorporating it into a lower-level design file, then inserting an instance of the lower-level file into your VHDL Design File. See Using a MAX+PLUS II Primitive or Macrofunction for more information.

Inputs	|	Outputs

GN	CCLRN	LDN	ENPN	ENTN	U/DN	RCLK	R/CN	CCLK	D	|	Q	TCN

L	X	X	X	X	X	X	X	X	X..X	|	Z..Z

H	L	X	X	X	X	X	L	X	X..X	|	L..L	H

H	H	L	X	X	X	X	L	d..a	|	d..a

H	H	H	H	H	H	X	L	X..X	|	Count Up

H	H	H	H	H	L	X	L	X..X	|	Count Dn

H	H	H	H	H	X	X	L	L	X..X	|	Hold

H	H	X	X	X	X	X	X	X	X..X	|	H L L H	L

H	X	X	X	X	X	H	X	X..X	|	C3..C0*

*	C3..C0 are the outputs of the counter registers.

See also:

Counter Macrofunctions

Macrofunctions (by function)


74697 (Counter)

Synchronous Binary Up/Down Counter with Output Registers, Multiplexed Tri-State Outputs, and Asynchronous Clear

Default Signal Levels:	GND--GN, RCLK, ENTN, ENPN, CCLK

VCC--R/CN, D0, D1, D2, D3, U/DN, CCLRN, LDN

Function Prototype:

FUNCTION 74697 (u/dn, r/cn, rclk, ldn, gn, entn, enpn, d3, d2, d1, d0, cclrn, cclk)

RETURNS (tcn, q3, q2, q1, q0);

This macrofunction is not directly supported by VHDL because it contains one or more port names with a slash (/) or dash (-). These characters are illegal in VHDL port names. However, you can use this macrofunction in your project by incorporating it into a lower-level design file, then inserting an instance of the lower-level file into your VHDL Design File. See Using a MAX+PLUS II Primitive or Macrofunction for more information.

Inputs	|	Outputs

GN	CCLRN	LDN	ENPN	ENTN	U/DN	RCLK	R/CN	CCLK	D	|	Q	TCN

L	X	X	X	X	X	X	X	X	X..X	|	Z..Z

H	L	X	X	X	X	X	L	X	X..X	|	L..L	H

H	H	L	X	X	X	X	L	d..a	|	d..a

H	H	H	H	H	H	X	L	X..X	|	Count Up

H	H	H	H	H	L	X	L	X..X	|	Count Dn

H	H	H	H	H	X	X	L	L	X..X	|	Hold

H	H	X	X	X	X	X	X	X	X..X	|	H..H	L

H	X	X	X	X	X	H	X	X..X	|	C3..C0*

*	C3..C0 are the outputs of the counter registers.

See also:

Counter Macrofunctions

Macrofunctions (by function)


74698 (Counter)

Synchronous Decade Up/Down Counter with Output Registers, Multiplexed Tri-State Outputs, and Synchronous Clear

Default Signal Levels:	GND--GN, RCLK, ENTN, ENPN, CCLK

VCC--R/CN, D0, D1, D2, D3, U/DN, CCLRN, LDN

Function Prototype:

FUNCTION 74698 (u/dn, r/cn, rclk, ldn, gn, entn, enpn, d3, d2, d1, d0, cclrn, cclk)

RETURNS (tcn, q3, q2, q1, q0);

This macrofunction is not directly supported by VHDL because it contains one or more port names with a slash (/) or dash (-). These characters are illegal in VHDL port names. However, you can use this macrofunction in your project by incorporating it into a lower-level design file, then inserting an instance of the lower-level file into your VHDL Design File. See Using a MAX+PLUS II Primitive or Macrofunction for more information.

Inputs	|	Outputs

GN	CCLRN	LDN	ENPN	ENTN	U/DN	RCLK	R/CN	CCLK	D	|	Q	TCN

L	X	X	X	X	X	X	X	X	X..X	|	Z..Z

H	L	X	X	X	X	X	L	X..X	|	L..L	H

H	H	L	X	X	X	X	L	d..a	|	d..a

H	H	H	H	H	H	X	L	X..X	|	Count Up

H	H	H	H	H	L	X	L	X..X	|	Count Dn

H	H	H	H	H	X	X	L	L	X..X	|	Hold

H	H	X	X	X	X	X	X	X	X..X	|	H L L H	L

H	X	X	X	X	X	H	X	X..X	|	C3..C0*

*	C3..C0 are the outputs of the counter registers.

See also:

Counter Macrofunctions

Macrofunctions (by function)


74699 (Counter)

Synchronous Binary Up/Down Counter with Output Registers, Multiplexed Tri-State Outputs, and Synchronous Clear

Default Signal Levels:	GND--GN, RCLK, ENTN, ENPN, CCLK

VCC--R/CN, D0, D1, D2, D3, U/DN, CCLRN, LDN

Function Prototype:

FUNCTION 74699 (u/dn, r/cn, rclk, ldn, gn, entn, enpn, d3, d2, d1, d0, cclrn, cclk)

RETURNS (tcn, q3, q2, q1, q0);

This macrofunction is not directly supported by VHDL because it contains one or more port names with a slash (/) or dash (-). These characters are illegal in VHDL port names. However, you can use this macrofunction in your project by incorporating it into a lower-level design file, then inserting an instance of the lower-level file into your VHDL Design File. See Using a MAX+PLUS II Primitive or Macrofunction for more information.

Inputs	|	Outputs

GN	CCLRN	LDN	ENPN	ENTN	U/DN	RCLK	R/CN	CCLK	D	|	Q	TCN

L	X	X	X	X	X	X	X	X	X..X	|	Z..Z

H	L	X	X	X	X	X	L	X..X	|	L..L	H

H	H	L	X	X	X	X	L	d..a	|	d..a

H	H	H	H	H	H	X	L	X..X	|	Count Up

H	H	H	H	H	L	X	L	X..X	|	Count Dn

H	H	H	H	H	X	X	L	L	X..X	|	Hold

H	H	X	X	X	X	X	X	X	X..X	|	H..H	L

H	X	X	X	X	X	H	X	X..X	|	C3..C0*

*	C3..C0 are the outputs of the counter registers.

See also:

Counter Macrofunctions

Macrofunctions (by function)


74821 (Register)

10-Bit Bus Interface Flipflop with Tri-State Outputs

Default Signal Levels:	GND--OEN, CLK

VCC--D1, D2, D3, D4, D5, D6, D7, D8, D9, D10

Function Prototype:

FUNCTION 74821 (oen, clk, d[1..10])

RETURNS (q[1..10]);

Inputs	|	Outputs

OEN	CLK	D	|	Q

H	X	X	|	Z

L	L	|	L

L	H	|	H

L	L	X	|	Qo

See also:

Macrofunctions (by function)

Register Macrofunctions


74822 (Register)

10-Bit Bus Interface Flipflop with Tri-State Inverting Outputs

Default Signal Levels:	GND--OEN, CLK

VCC--DN1, DN2, DN3, DN4, DN5, DN6, DN7, DN8, DN9, DN10

Function Prototype:

FUNCTION 74822 (oen, clk, d[1..10])

RETURNS (q[1..10]);

Inputs	|	Outputs

OEN	CLK	D	|	Q

H	X	X	|	Z

L	L	|	H

L	H	|	L

L	L	X	|	Qo

See also:

Macrofunctions (by function)

Register Macrofunctions


74823 (Register)

9-Bit Bus Interface Flipflop with Tri-State Outputs

Default Signal Levels:	GND--OEN, CLKENN, CLK

VCC--D1, D2, D3, D4, D5, D6, D7, D8, D9, CLRN

Function Prototype:

FUNCTION 74823 (oen, clrn, clkenn, clk, d[1..9])

RETURNS (q[1..9]);

Inputs	|	Outputs

OEN	CLRN	CLKENN	CLK	D	|	Q

H	X	X	X	X	|	Z

L	L	X	X	X	|	L

L	H	H	X	X	|	Qo

L	H	L	L	|	L

L	H	L	H	|	H

See also:

Macrofunctions (by function)

Register Macrofunctions


74824 (Register)

9-Bit Bus Interface Flipflop with Tri-State Inverting Outputs

Default Signal Levels:	GND--OEN, CLKENN, CLK

VCC--DN1, DN2, DN3, DN4, DN5, DN6, DN7, DN8, DN9, CLRN

Function Prototype:

FUNCTION 74824 (oen, clrn, clkenn, clk, dn[1..9])

RETURNS (q[1..9]);

Inputs	|	Outputs

OEN	CLRN	CLKENN	CLK	D	|	Q

H	X	X	X	X	|	Z

L	L	X	X	X	|	L

L	H	H	X	X	|	Qo

L	H	L	L	|	H

L	H	L	H	|	L

See also:

Macrofunctions (by function)

Register Macrofunctions


74825 (Register)

8-Bit Bus Interface Flipflop with Tri-State Outputs

Default Signal Levels:	GND--OE1N, OE2N, OE3N, CLKENN, CLK

VCC--D1, D2, D3, D4, D5, D6, D7, D8, CLRN

Function Prototype:

FUNCTION 74825 (oe1n, oe2n, oe3n, clrn, clkenn, clk, d[1..8])

RETURNS (q[1..8]);

Inputs	|	Outputs

OE*	CLRN	CLKENN	CLK	D	|	Q

L	X	X	X	X	|	Z

H	L	X	X	X	|	L

H	H	H	X	X	|	Qo

H	H	L	L	|	L

H	H	L	H	|	H

*	OE = /OE1N & /OE2N & /OE3N

See also:

Macrofunctions (by function)

Register Macrofunctions


74826 (Register)

9-Bit Bus Interface Flipflop with Tri-State Inverting Outputs

Default Signal Levels:	GND--OE1N, OE2N, OE3N, CLKENN, CLK

VCC--DN1, DN2, DN3, DN4, DN5, DN6, DN7, DN8, CLRN

Function Prototype:

FUNCTION 74826 (oe1n, oe2n, oe3n, clrn, clkenn, clk, d[1..8])

RETURNS (q[1..8]);

Inputs	|	Outputs

OE*	CLRN	CLKENN	CLK	D	|	Q

L	X	X	X	X	|	Z

H	L	X	X	X	|	L

H	H	H	X	X	|	Qo

H	H	L	L	|	H

H	H	L	H	|	L

*	OE = /OE1N & /OE2N & /OE3N

See also:

Macrofunctions (by function)

Register Macrofunctions


74841 (Latch)

10-Bit D-Type Latch with Tri-State Outputs

Default Signal Levels:	GND--OEN

VCC--D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, C

Function Prototype:

FUNCTION 74841 (oen, c, d[1..10])

RETURNS (q[1..10]);

Inputs	|	Outputs

OEN	C	D	|	Q

H	X	X	|	Z

L	H	L	|	L

L	H	H	|	H

L	L	X	|	Qo

See also:

Latch Macrofunctions

Macrofunctions (by function)


74842 (Latch)

10-Bit D-Type Latch with Tri-State Outputs

Default Signal Levels:	GND--OEN

VCC--DN1, DN2, DN3, DN4, DN5, DN6, DN7, DN8, DN9, DN10, C

Function Prototype:

FUNCTION 74842 (oen, c, d[1..10])

RETURNS (q[1..10]);

Inputs	|	Outputs

OEN	C	DN	|	Q

H	X	X	|	Z

L	H	d[10..1]	|	d[10..1]

L	H	d[10..1]	|	d[10..1]

L	L	X	|	Qo

See also:

Latch Macrofunctions

Macrofunctions (by function)


74843 (Latch)

9-Bit Bus Interface D-Type Latch with Tri-State Outputs

Default Signal Levels:	GND--OEN

VCC--D1, D2, D3, D4, D5, D6, D7, D8, D9, CLRN, PREN, ENA

Function Prototype:

FUNCTION 74843 (oen, clrn, pren, ena, d[1..9])

RETURNS (q[1..9]);

Inputs	|	Outputs

OEN	CLRN	PREN	ENA	D	|	Q

H	X	X	X	X	|	Z

L	L	H	X	X	|	L

L	H	L	X	X	|	H

L	L	L	X	X	|	Illegal

L	H	H	H	L	|	L

L	H	H	H	H	|	H

L	H	H	L	X	|	Qo

See also:

Latch Macrofunctions

Macrofunctions (by function)


74844 (Latch)

9-Bit Bus Interface D-Type Inverting Latch with Tri-State Outputs

Default Signal Levels:	GND--OEN

VCC--DN1, DN2, DN3, DN4, DN5, DN6, DN7, DN8, DN9, CLRN, PREN, ENA

Function Prototype:

FUNCTION 74844 (oen, clrn, pren, ena, dn[1..9])

RETURNS (q[1..9]);

Inputs	|	Outputs

OEN	CLRN	PREN	ENA	D	|	Q

H	X	X	X	X	|	Z

L	L	H	X	X	|	L

L	H	L	X	X	|	H

L	L	L	X	X	|	Illegal

L	H	H	H	L	|	H

L	H	H	H	H	|	L

L	H	H	L	X	|	Qo

See also:

Latch Macrofunctions

Macrofunctions (by function)


74845 (Latch)

8-Bit Bus Interface D-Type Latch with Tri-State Outputs

Default Signal Levels:	GND--OEN1, OEN2, OEN3

VCC--D1, D2, D3, D4, D5, D6, D7, D8, CLRN, PREN, ENA

Function Prototype:

FUNCTION 74845 (oen1, oen2, oen3, clrn, pren, ena, d[1..8])

RETURNS (q[1..8]);

Inputs	|	Outputs

OE*	CLRN	PREN	ENA	D	|	Q

L	X	X	X	X	|	Z

H	L	H	X	X	|	L

H	H	L	X	X	|	H

H	L	L	X	X	|	Illegal

H	H	H	H	L	|	L

H	H	H	H	H	|	H

H	H	H	L	X	|	Qo

*	OE = /OEN1 & /OEN2 & /OEN3

See also:

Latch Macrofunctions

Macrofunctions (by function)


74846 (Latch)

8-Bit Bus Interface D-Type Inverting Latch with Tri-State Outputs

Default Signal Levels:	GND--OEN1, OEN2, OEN3

VCC--DN1, DN2, DN3, DN4, DN5, DN6, DN7, DN8, CLRN, PREN, ENA

Function Prototype:

FUNCTION 74846 (oen1, oen2, oen3, clrn, pren, ena, d[1..8])

RETURNS (q[1..8]);

Inputs	|	Outputs

OE*	CLRN	PREN	ENA	D	|	Q

L	X	X	X	X	|	Z

H	L	H	X	X	|	L

H	H	L	X	X	|	H

H	L	L	X	X	|	Illegal

H	H	H	H	L	|	H

H	H	H	H	H	|	L

H	H	H	L	X	|	Qo

*	OE = /OEN1 & /OEN2 & /OEN3

See also:

Latch Macrofunctions

Macrofunctions (by function)


74990 (Latch)

8-Bit Transparent Read-Back Latch

Default Signal Levels:	GND--C, OERB

VCC--D1, D2, D3, D4, D5, D6, D7, D8

Function Prototype:

FUNCTION 74990 (oerb, c)

RETURNS (d[1..8], q[1..8]);

Inputs	|	Outputs

C	OERB	D	|	D	Q

L	H	X	|	N/A	HOLD

H	H	D1	|	N/A	D1

L	L	Z	|	Q1	HOLD

H	L	Z	|	Q1	HOLD

See also:

Latch Macrofunctions

Macrofunctions (by function)


74604 (Latch)

Octal 2-Input Multiplexed Latch with Tri-State Outputs

Default Signal Levels:	VCC--all input pins

Function Prototype:

FUNCTION 74604 (clk, sel, a[1..8], b[1..8])

RETURNS (y[1..8]);

Inputs	|	Outputs

A[1..8]	B[1..8]	SEL	CLK	|	Y[1..8]

a[1..8]	b[1..8]	L	|	b[1..8]

a[1..8]	b[1..8]	H	|	a[1..8]

X	X	X	L	|	Z..Z

X	X	L	H	|	bo[1..8]

X	X	H	H	|	ao[1..8]

See also:

Latch Macrofunctions

Macrofunctions (by function)


74630 (EDAC)

16-Bit Parallel Error Detection and Correction Circuit

Default Signal Levels:	VCC--all input pins

Function Prototype:

FUNCTION 74630 (s1, s0, db[15..0], cb[5..0])

RETURNS (dbo[15..0], cbo[5..0], sef, def);

Control Function Table:

Memory	|	Control	|	EDAC Function	|	Data 	|	Check Word I/O	|	Error

Cycle	|	|	|	I/O	|	|	Flags

|	S1	S2	|	|	|	|	|	SEF	DEF

WRITE	|	L	L	|	Generate Check Word	|	Inp Data	|	Output Check Word	|	L	L

READ	|	L	H	|	Read Data & Check Word	|	Inp Data	|	Input Check Word	|	L	L

READ	|	H	H	|	Latch & Flag Errors	|	Latch D	|	Latch Check Word	|	Enabled

READ	|	H	L	|	Correct Data & Synd Bits	|	Cor Data	|	Syndrome Bits	|	Enabled

Error Function Table:

Total Number of Errors	|	Error Flags	|	Data Correction

Data Word	Check Word	|	SEF	DEF	|

0	0	|	L	L	|	Not Applicable

1	0	|	H	L	|	Correction

0	1	|	H	L	|	Correction

1	1	|	H	H	|	Interrupt

2	0	|	H	H	|	Interrupt

0	2	|	H	H	|	Interrupt

Check-Word Bits are derived from parity bits as follows:

Check Word	|	16-Bit Data Word*

CB0	|	DB0, DB1, DB3, DB4, DB8, DB9, DB10, DB13

CB1	|	DB0, DB2, DB3, DB5, DB6, DB8, DB11, DB14

CB2	|	DB1, DB2, DB4, DB5, DB7, DB9, DB12, DB15

CB3	|	DB0, DB1, DB2, DB6, DB7, DB10, DB11, DB12

CB4	|	DB3, DB4, DB5, DB6, DB7, DB13, DB14, DB15

CB5	|	DB8, DB9, DB10, DB11, DB12, DB13, DB14, DB15

*	The six check bits are parity bits derived from the data bits listed.

Error Syndrome Table:

Error Location	|	Syndrome Error Code

|	CB0	CB1	CB2	CB3	CB4	CB5

DB0	|	L	L	H	L	H	H

DB1	|	L	H	L	L	H	H

DB2	|	H	L	L	L	H	H

DB3	|	L	L	H	H	L	H

DB4	|	L	H	L	H	L	H

DB5	|	H	L	L	H	L	H

DB6	|	H	L	H	L	L	H

DB7	|	H	H	L	L	L	H

DB8	|	L	L	H	H	H	L

DB9	|	L	H	L	H	H	L

DB10	|	L	H	H	L	H	L

DB11	|	H	L	H	L	H	L

DB12	|	H	H	L	L	H	L

DB13	|	L	H	H	H	L	L

DB14	|	H	L	H	H	L	L

DB15	|	H	H	L	H	L	L

CB0	|	L	H	H	H	H	H

CB1	|	H	L	H	H	H	H

CB2	|	H	H	L	H	H	H

CB3	|	H	H	H	L	H	H

CB4	|	H	H	H	H	L	H

CB5	|	H	H	H	H	H	L

No Error	|	H	H	H	H	H	H

See also:

EDAC Macrofunctions

Macrofunctions (by function)


74636 (EDAC)

8-Bit Parallel Error Detection and Correction Circuit

Default Signal Levels:	VCC--all input pins

Function Prototype:

FUNCTION 74636 (s1, s0, db[7..0], cb[4..0])

RETURNS (dbo[7..0], cbo[4..0], sef, def);

Control Function Table:

Memory	|	Control	|	EDAC Function	|	Data	|	Check Word I/O	|	Error

Cycle	|	|	|	I/O	|	|	Flags

|	S1	S2	|	|	|	|	SEF	DEF

WRITE	|	L	L	|	Generate Check Word	|	Inp Data	|	Output Check Word	|	L	L

READ	|	L	H	|	Read Data & Check Word	|	Inp Data	|	Input Check Word	|	L	L

READ	|	H	H	|	Flag Errors	|	Latch D	|	Latch Check Write	|	Enabled

READ	|	H	L	|	Correct Data & Synd Bits	|	Cor Data	|	Syndrome Bits	|	Enabled

Error Function Table:

Total Number of Errors	|	Error Flags	|	Data Correction

Data Word	Check Word	|	SEF	DEF	|

0	0	|	L	L	|	Not Applicable

1	0	|	H	L	|	Correction

0	1	|	H	L	|	Correction

1	1	|	H	H	|	Interrupt

2	0	|	H	H	|	Interrupt

0	2	|	H	H	|	Interrupt

Check-Word Bits are derived from parity bits as follows:

Check Word	|	8-Bit Data Word*

CB0	|	DB0, DB1, DB3, DB4

CB1	|	DB0, DB2, DB3, DB5, DB6

CB2	|	DB1, DB2, DB4, DB5, DB7

CB3	|	DB0, DB1, DB2, DB6, DB7

CB4	|	DB3, DB4, DB5, DB6, DB7

*	The five check bits are parity bits derived from the data bits listed.

Error Syndrome Table:

Error Location	|	Syndrome Error Code

|	CB0	CB1	CB2	CB3	CB4

DB0	|	L	L	H	L	H

DB1	|	L	H	L	L	H

DB2	|	H	L	L	L	H

DB3	|	L	L	H	H	L

DB4	|	L	H	L	H	L

DB5	|	H	L	L	H	L

DB6	|	H	L	H	L	L

DB7	|	H	H	L	L	L

CB0	|	L	H	H	H	H

CB1	|	H	L	H	H	H

CB2	|	H	H	L	H	H

CB3	|	H	H	H	L	H

CB4	|	H	H	H	H	L

No Error	|	H	H	H	H	H

See also:

EDAC Macrofunctions

Macrofunctions (by function)


74668 (Counter)

Synchronous Decade Up/Down Counter

Default Signal Levels:	GND--ENTN, ENPN, CLK

VCC--D0, D1, D2, D3, U/DN, LDN

Function Prototype:

FUNCTION 74668 (clk, entn, enpn, u/dn, ldn, d[3..0])

RETURNS (q[3..0], tcn);

This macrofunction is not directly supported by VHDL because it contains one or more port names with a slash (/) or dash (-). These characters are illegal in VHDL port names. However, you can use this macrofunction in your project by incorporating it into a lower-level design file, then inserting an instance of the lower-level file into your VHDL Design File. See Using a MAX+PLUS II Primitive or Macrofunction for more information.

Inputs	|	Outputs

LDN	ENTN	ENPN	U/DN	CLK	|	D3	D2	D1	D0	|	Q3	Q2	Q1	Q0	|	TCN

L	X	X	X	|	D[3..0]	|	D[3..0]	|

H	H	X	X	X	|	X	X	X	X	|	Q3o..Q0o	|

H	X	H	X	X	|	X	X	X	X	|	Q3o..Q0o	|

H	L	L	H	|	X	X	X	X	|	Count Up	|	*

H	L	L	L	|	X	X	X	X	|	Count Down	|	**

*	TCN goes low when the count is 9.

**	TCN goes low when the count is 0.

See also:

Counter Macrofunctions

Macrofunctions (by function)


74669 (Counter)

Synchronous 4-Bit Binary Up/Down Counter

Default Signal Levels:	GND--ENTN, ENPN, CLK

VCC--D0, D1, D2, D3, U/DN, LDN

Function Prototype:

FUNCTION 74669 (clk, entn, enpn, u/dn, ldn, d[3..0])

RETURNS (q[3..0], tcn);

This macrofunction is not directly supported by VHDL because it contains one or more port names with a slash (/) or dash (-). These characters are illegal in VHDL port names. However, you can use this macrofunction in your project by incorporating it into a lower-level design file, then inserting an instance of the lower-level file into your VHDL Design File. See Using a MAX+PLUS II Primitive or Macrofunction for more information.

Inputs	|	Outputs

LDN	ENTN	ENPN	U/DN	CLK	|	D3	D2	D1	D0	|	Q3..Q2	Q1..Q0	|	TCN

L	X	X	X	|	D[3..0]	|	D[3..0]	|

H	H	X	X	X	|	X	X	X	X	|	Q3o..Q0o	|

H	X	H	X	X	|	X	X	X	X	|	Q3o..Q0o	|

H	L	L	H	|	X	X	X	X	|	Count Up	|	*

H	L	L	L	|	X	X	X	X	|	Count Down	|	**

*	TCN goes low when the count is 15.

**	TCN goes low when the count is 0.

See also:

Counter Macrofunctions

Macrofunctions (by function)


74670 (Register)

4-Bit-by-4-Bit Register File with Tri-State Outputs

Default Signal Levels:	GND--GWN, WA, WB, GRN, RA, RB

VCC--D1, D2, D3, D4

Function Prototype:

FUNCTION 74670 (wb, wa, gwn, rb, ra, grn, d[1..4])

RETURNS (q[1..4]);

Write Function Table:

Write Inputs	|	Word

GWN	WB	WA	|	W0	W1	W2	W3

H	X	X	|	Qo	Qo	Qo	Qo

L	L	L	|	D	Qo	Qo	Qo

L	L	H	|	Qo	D	Qo	Qo

L	H	L	|	Qo	Qo	D	Qo

L	H	H	|	Qo	Qo	Qo	D

Read Function Table:

Read Inputs	|	Outputs

GRN	RB	RA	|	Q1	Q2	Q3	Q4

H	X	X	|	Z	Z	Z	Z

L	L	L	|	W0B1	W0B2	W0B3	W0B4

L	L	H	|	W1B1	W1B2	W1B3	W1B4

L	H	L	|	W2B1	W2B2	W2B3	W2B4

L	H	H	|	W3B1	W3B2	W3B3	W3B4

See also:

Macrofunctions (by function)

Register Macrofunctions


74671 (Shift Register)

4-Bit Universal Shift Register/ Latch with Direct-Overriding Clear and Tri-State Outputs

Default Signal Levels:	GND--GN, RCLK, SRCLK

VCC--R/SN, SRCLRN, SERR, A, B, C, D, SERL, S0, S1

Function Prototype:

FUNCTION 74671 (gn, r/sn, srclrn, s1, s0, srclk, serl, serr, a, b, c, d, rclk)

RETURNS (qa, qb, qc, qd, casc);

This macrofunction is not directly supported by VHDL because it contains one or more port names with a slash (/) or dash (-). These characters are illegal in VHDL port names. However, you can use this macrofunction in your project by incorporating it into a lower-level design file, then inserting an instance of the lower-level file into your VHDL Design File. See Using a MAX+PLUS II Primitive or Macrofunction for more information.

Inputs	|	Outputs

GN	R/SN	SRCLRN	S1	S0	SRCLK	SERL	SERR	A..D	|	QA	QB	QC	QD	|	CASC

H	X	X	X	X	X	X	X	X..X	|	Z	Z	Z	Z	|	*

L	L	L	X	X	X	X	X	X..X	|	L	L	L	L	|	*

L	L	H	X	X	L	X	X	X..X	|	QAo	QBo	QCo	QDo	|	*

L	L	H	L	L	X	X	X	X..X	|	QAo	QBo	QCo	QDo	|	H

L	L	H	L	H	X	H	X..X	|	H	QAn	QBn	QCn	|	QCn

L	L	H	L	H	X	L	X..X	|	L	QAn	QBn	QCn	|	QCn

L	L	H	H	L	H	X	X..X	|	QBn	QCn	QDn	H	|	QBn

L	L	H	H	L	L	X	X..X	|	QBn	QCn	QDn	L	|	QBn

L	L	H	H	H	X	X	a..d	|	a	b	c	d	|	H

L	H	X	X	X	X	X	X	X..X	|	Int. Reg. Contents	|	*

*	The cascade output displays the D bit of the shift register in Mode 1 (S1, S0 = L, H), the A bit in Mode 2 (S1, S0 = H, L), and is inactive (H) in modes 0 and 3 (S1, S0 = L, L and H, H, respectively).

See also:

Macrofunctions (by function)

Shift Register Macrofunctions


74672 (Shift Register)

4-Bit Universal Shift Register/Latch with Synchronous Clear and Tri-State Outputs

Default Signal Levels:	GND--GN, RCLK, SRCLK, S0, S1

VCC--R/SN, SRCLRN, SERR, A, B, C, D, SERL

Function Prototype:

FUNCTION 74672 (gn, r/sn, srclrn, s1, s0, srclk, serl, serr, a, b, c, d, rclk)

RETURNS (qa, qb, qc, qd, casc);

This macrofunction is not directly supported by VHDL because it contains one or more port names with a slash (/) or dash (-). These characters are illegal in VHDL port names. However, you can use this macrofunction in your project by incorporating it into a lower-level design file, then inserting an instance of the lower-level file into your VHDL Design File. See Using a MAX+PLUS II Primitive or Macrofunction for more information.

Inputs	|	Outputs

GN	R/SN	SRCLRN	S1	S0	SRCLK	SERL	SERR	A..D	|	QA	QB	QC	QD	|	CASC

H	X	X	X	X	X	X	X	X..X	|	Z	Z	Z	Z	|	*

L	L	L	X	X	X	X	X..X	|	L	L	L	L	|	*

L	L	H	X	X	L	X	X	X..X	|	QAo	QBo	QCo	QDo	|	*

L	L	H	L	L	X	X	X	X..X	|	QAo	QBo	QCo	QDo	|	H

L	L	H	L	H	X	H	X..X	|	H	QAn	QBn	QCn	|	QCn

L	L	H	L	H	X	L	X..X	|	L	QAn	QBn	QCn	|	QCn

L	L	H	H	L	H	X	X..X	|	QBn	QCn	QDn	H	|	QBn

L	L	H	H	L	L	X	X..X	|	QBn	QCn	QDn	L	|	QBn

L	L	H	H	H	X	X	a..d	|	a	b	c	d	|	H

L	H	X	X	X	X	X	X	X..X	|	Internal Reg. Contents	|	*

*	The cascade output displays the D bit of the shift register in Mode 1 (S1, S0 = L, H), the A bit in Mode 2 (S1, S0 = H, L), and is inactive (H) in modes 0 and 3 (S1, S0 = L, L and H, H, respectively).

See also:

Macrofunctions (by function)

Shift Register Macrofunctions


74673 (Shift Register)

16-Bit Shift Register

Default Signal Levels:	VCC--all input pins

Function Prototype:

FUNCTION 74673 (csn, r/wn, srclk, stclrn, mode, ser)

RETURNS (y[0..15], q15);

This macrofunction is not directly supported by VHDL because it contains one or more port names with a slash (/) or dash (-). These characters are illegal in VHDL port names. However, you can use this macrofunction in your project by incorporating it into a lower-level design file, then inserting an instance of the lower-level file into your VHDL Design File. See Using a MAX+PLUS II Primitive or Macrofunction for more information.

Inputs	|	Internal	|	Outputs

|	Registers	|

CSN	R/WN	SRCLK	STCLRN	MODE	SER	|	SRO..SR15*	|	Y[0..15]	Q15

H	X	X	X	X	X	|	SR0o..SR15o	|	Y[0..15]	Q15o

X	X	X	L	X	X	|	X..X	|	L..L

L	H	H	X	L	|	L, SR0o ...	|	Y[0..15]	SR14o

L	L	H	X	H	|	H, SR0o ...	|	Y[0..15]	SR14o

L	H	H	X	Q15	|	SR15o, SROo	|	Yo	SR14o

L	L	H	H	X	|	|	SR0o..SR15o

*	These values are for the internal shift registers (Q15 = SR15).

See also:

Macrofunctions (by function)

Shift Register Macrofunctions


74674 (Shift Register)

16-Bit Shift Register

Default Signal Levels:	VCC--all input pins

Function Prototype:

FUNCTION 74674 (csn, r/wn, clk, mode, ser, p[15..0])

RETURNS (q15);

This macrofunction is not directly supported by VHDL because it contains one or more port names with a slash (/) or dash (-). These characters are illegal in VHDL port names. However, you can use this macrofunction in your project by incorporating it into a lower-level design file, then inserting an instance of the lower-level file into your VHDL Design File. See Using a MAX+PLUS II Primitive or Macrofunction for more information.

Inputs	|	Internal	|	Output

|	Registers	|

CSN	R/WN	CLK	MODE	SER	|	SRO..SR15*	|	Q15

H	X	X	X	X	|	SR0o..SR15o	|	Q15o

L	L	X	L	|	L, SR0o ...	|	SR14o

L	L	X	H	|	H, SR0o ...	|	SR14o

L	H	L	Q15	|	Q15, SR0o ...	|	SR14o

L	H	H	X	|	P0..P15	|	P15

*	These values are for the internal shift registers (Q15 = SR15).

See also:

Macrofunctions (by function)

Shift Register Macrofunctions


74684 (Comparator)

8-Bit Magnitude/Identity Comparator

Default Signal Levels:	VCC--all input pins

Function Prototype:

FUNCTION 74684 (p[7..0], q[7..0])

RETURNS (equaln, p_gr_qn);

Inputs	|	Outputs

DATA	|	EQUALN	P_GR_QN

P = Q	|	L	H

P > Q	|	H	L

P < Q	|	H	H

See also:

Comparator Macrofunctions

Macrofunctions (by function)


74686 (Comparator)

8-Bit Magnitude/Identity Comparator

Default Signal Levels:	VCC--all input pins

Function Prototype:

FUNCTION 74686 (g1n, g2n, p[7..0], q[7..0])

RETURNS (equaln, p_gr_qn);

Inputs	|	Outputs

G1N	G2N	DATA	|	EQUALN	P_GR_QN

H	X	X	|	H	H

X	H	X	|	H	H

L	L	P = Q	|	L	H

L	L	P > Q	|	H	L

L	L	P < Q	|	H	H

See also:

Comparator Macrofunctions

Macrofunctions (by function)


74688 (Comparator)

8-Bit Identity Comparator

Default Signal Levels:	VCC--all input pins

Function Prototype:

FUNCTION 74688 (gn, p[7..0], q[7..0])

RETURNS (equaln);

Inputs	|	Output

GN	DATA	|	EQUALN

H	X	|	H

L	P = Q	|	L

L	P <> Q	|	H

See also:

Comparator Macrofunctions

Macrofunctions (by function)


74445 (Decoder)

BCD-to-Decimal Decoder

Default Signal Levels:	GND--all input pins

Function Prototype:

FUNCTION 74445 (d, c, b, a)

RETURNS (o0n, o1n, o2n, o3n, o4n, o5n, o6n, o7n, o8n, o9n);

No.	|	Inputs	|	Outputs

|	D	C	B	A	|	O0N	O1N	O2N	O3N	O4N	O5N	O6N	O7N	O8N	O9N

0	|	L	L	L	L	|	L	H	H	H	H	H	H	H	H	H

1	|	L	L	L	H	|	H	L	H	H	H	H	H	H	H	H

2	|	L	L	H	L	|	H	H	L	H	H	H	H	H	H	H

3	|	L	L	H	H	|	H	H	H	L	H	H	H	H	H	H

4	|	L	H	L	L	|	H	H	H	H	L	H	H	H	H	H

5	|	L	H	L	H	|	H	H	H	H	H	L	H	H	H	H

6	|	L	H	H	L	|	H	H	H	H	H	H	L	H	H	H

7	|	L	H	H	H	|	H	H	H	H	H	H	H	L	H	H

8	|	H	L	L	L	|	H	H	H	H	H	H	H	H	L	H

9	|	H	L	L	H	|	H	H	H	H	H	H	H	H	H	L

I	|	H	L	H	L	|	H	H	H	H	H	H	H	H	H	H

N	|	H	L	H	H	|	H	H	H	H	H	H	H	H	H	H

V	|	H	H	L	L	|	H	H	H	H	H	H	H	H	H	H

A	|	H	H	L	H	|	H	H	H	H	H	H	H	H	H	H

L	|	H	H	H	L	|	H	H	H	H	H	H	H	H	H	H

I	|	H	H	H	H	|	H	H	H	H	H	H	H	H	H	H

D	|

See also:

Decoder Macrofunctions

Macrofunctions (by function)


74465 (Buffer)

Octal Tri-State Buffer

Default Signal Levels:	GND--GN1, GN2

VCC--A1, A2, A3, A4, A5, A6, A7, A8

Function Prototype:

FUNCTION 74465 (gn[1..2], a[1..8])

RETURNS (y[1..8]);

Inputs	|	Outputs

GN1	GN2	A	|	Y

H	X	X	|	Z

X	H	X	|	Z

L	L	L	|	L

L	L	H	|	H

See also:

Macrofunctions (by function)


74466 (Buffer)

Octal Inverting Tri-State Buffer

Default Signal Levels:	GND--GN1, GN2

VCC--A1, A2, A3, A4, A5, A6, A7, A8

Function Prototype:

FUNCTION 74466 (gn[1..2], a[1..8])

RETURNS (yn[1..8]);

Inputs	|	Outputs

GN1	GN2	A	|	YN

H	X	X	|	Z

X	H	X	|	Z

L	L	L	|	H

L	L	H	|	L

See also:

Buffer Macrofunctions

Macrofunctions (by function)


74467 (Buffer)

Octal Tri-State Buffer

Default Signal Levels:	GND--1GN, 2GN

VCC--1A1, 1A2, 1A3, 1A4, 2A1, 2A2, 2A3, 2A4

Function Prototype:

FUNCTION 74467 (1gn, 1a[1..4], 2gn, 2a[1..4])

RETURNS (1y[1..4], 2y[1..4]);

Inputs	|	Outputs

1GN	2GN	1A[4..1]	2A[4..1]	|	1Y[4..1]	2Y[4..1]

H	H	X	X	|	Z	Z

H	L	X	2a[4..1]	|	Z	2a[4..1]

L	H	1a[4..1]	X	|	1a[4..1]	Z

L	L	1a[4..1]	2a[4..1]	|	1a[4..1]	2a[4..1]

See also:

Buffer Macrofunctions

Macrofunctions (by function)


74468 (Buffer)

Octal Inverting Tri-State Buffer

Default Signal Levels:	GND--1GN, 2GN

VCC--1A1, 1A2, 1A3, 1A4, 2A1, 2A2, 2A3, 2A4

Function Prototype:

FUNCTION 74468 (1gn, 1a[1..4], 2gn, 2a[1..4])

RETURNS (1yn[1..4], 2yn[1..4]);

Inputs	|	Outputs

1GN	2GN	1A[4..1]	2A[4..1]	|	1Y[4..1]	2Y[4..1]

H	H	X	X	|	Z	Z

H	L	X	2a[4..1]	|	Z	/(2a[4..1])

L	H	1a[4..1]	X	|	/(1a[4..1])	Z

L	L	1a[4..1]	2a[4..1]	|	/(1a[4..1])	/(2a[4..1])

See also:

Buffer Macrofunctions

Macrofunctions (by function)


74490 (Counter)

Dual 4-Bit Decade Counter

Default Signal Levels:	GND--1SET9, 1CLR, 2SET9, 2CLR

VCC--1CLK, 2CLK

Function Prototype:

FUNCTION 74490 (1set9, 1clr, 1clk, 2set9, 2clr, 2clk)

RETURNS (1qd, 1qc, 1qb, 1qa, 2qd, 2qc, 2qb, 2qa);

No.	|	Inputs	|	Outputs

|	CLR	SET9	CLK	|	QA	QB	QC	QD

0	|	H	L	X	|	L	L	L	L

9	|	L	H	X	|	H	L	L	H

0	|	L	L	|	L	L	L	L

1	|	L	L	|	L	L	L	H

2	|	L	L	|	L	L	H	L

3	|	L	L	|	L	L	H	H

4	|	L	L	|	L	H	L	L

5	|	L	L	|	L	H	L	H

6	|	L	L	|	L	H	H	L

7	|	L	L	|	L	H	H	H

8	|	L	L	|	H	L	L	L

9	|	L	L	|	H	L	L	H

X	|	H	H	X	|	Illegal

See also:

Counter Macrofunctions

Macrofunctions (by function)


74518 (Comparator)

8-Bit Identity Comparator Note

Default Signal Levels:	GND--all input pins

Function Prototype:

FUNCTION 74518 (p[7..0], q[7..0], gn)

RETURNS (pq);

Inputs	|	Output

Data	Enable	|

P, Q	GN	|	PQ

P = Q	L	|	H

P > Q	L	|	L

P < Q	L	|	L

X	H	|	L

See also:

Comparator Macrofunctions

Macrofunctions (by function)


74540 (Buffer)

Octal Inverting Tri-State Buffer

Default Signal Levels:	GND--GN1, GN2

VCC-A1, A2, A3, A4, A5, A6, A7, A8

Function Prototype:

FUNCTION 74540 (gn[1..2], a[1..8])

RETURNS (yn[1..8]);

Inputs	|	Outputs

GN1	GN2	A	|	YN

H	X	X	|	Z

X	H	X	|	Z

L	L	L	|	H

L	L	H	|	L

See also:

Buffer Macrofunctions

Macrofunctions (by function)


74541 (Buffer)

Octal Tri-State Buffer

Default Signal Levels:	GND--GN1, GN2

VCC--A1, A2, A3, A4, A5, A6, A7, A8

Function Prototype:

FUNCTION 74541 (gn[1..2], a[1..8])

RETURNS (y[1..8]);

Inputs	|	Outputs

GN1	GN2	A	|	Y

H	X	X	|	Z

X	H	X	|	Z

L	L	L	|	L

L	L	H	|	H

See also:

Buffer Macrofunctions

Macrofunctions (by function)


74548 (Register)

8-Bit 2-Stage Pipelined Register with Tri-State Outputs

Default Signal Levels:	GND--OEN, CLKENN1, CLKENN2, CLK

VCC--INSEL, OUTSEL, D0, D1, D2, D3, D4, D5, D6, D7

Function Prototype:

FUNCTION 74548 (clk, clkenn1, clkenn2, insel, d[7..0], outsel, oen)

RETURNS (y[7..0]);

Inputs	|	Register Contents

CLK	CLKENN1	CLKENN2	INSEL	|	RANK1*	RANK2**

L	X	X	X	|	RANK1-Q	RANK2-Q

H	H	X	|	RANK1-Q	RANK2-Q

L	H	X	|	D	RANK2-Q

L	L	L	|	D	RANK1-Q

L	L	H	|	D	D

H	L	L	|	RANK1-Q	RANK1-Q

H	L	H	|	RANK1-Q	D

*	RANK1 is the first set of registers.

**	RANK2 is the second set of registers.

Inputs	|	Outputs

OUTSEL	OEN	|	Y

L	L	|	RANK2-Q

H	L	|	RANK1-Q

X	H	|	Z

See also:

Macrofunctions (by function)

Register Macrofunctions


74549 (Latch)

8-Bit 2-Stage Pipelined Latch

Default Signal Levels:	GND--OEN, G

VCC--INSEL, OUTSEL, D0, D1, D2, D3, D4, D5, D6, D7, G1N, G2N

Function Prototype:

FUNCTION 74549 (g, g1n, g2n, insel, d[7..0], outsel, oen)

RETURNS (y[7..0]);

Inputs	|	Latch Contents

CLK	G1N	G2N	INSEL	|	RANK1*	RANK2**

X	L	L	L	|	D	RANK1-Q

X	L	L	H	|	D	D

L	L	H	X	|	D	RANK2-Q

L	H	L	L	|	RANK1-Q	RANK1-Q

L	H	L	H	|	RANK1-Q	D

L	H	H	X	|	RANK1-Q	RANK2-Q

H	X	X	L	|	D	RANK1-Q

H	X	X	H	|	D	D

*	RANK1 is the first set of registers.

**	RANK2 is the second set of registers.

Inputs	|	Outputs

OUTSEL	OEN	|	Y

L	L	|	RANK2-Q

H	L	|	RANK1-Q

X	H	|	Z

See also:

Latch Macrofunctions

Macrofunctions (by function)


74568 (Counter)

Decade Up/Down Counter with Synchronous Load and Clear and Asynchronous Clear

Default Signal Levels:	GND--OEN, CLK

VCC--ACLRN, SCLRN, LDN, D0, D1, D2, D3, U/DN, ENPN, ENTN

Function Prototype:

FUNCTION 74568 (clk, entn, enpn, aclrn, sclrn, u/dn, ldn, d[3..0], oen)

RETURNS (q[3..0], rcon, ccon);

This macrofunction is not directly supported by VHDL because it contains one or more port names with a slash (/) or dash (-). These characters are illegal in VHDL port names. However, you can use this macrofunction in your project by incorporating it into a lower-level design file, then inserting an instance of the lower-level file into your VHDL Design File. See Using a MAX+PLUS II Primitive or Macrofunction for more information.

Inputs	|	Outputs

OEN	ACLRN	SCLRN	LDN	D	ENTN	ENPN	U/DN	CLK	|	Q	RCON	CCON

H	X	X	X	X..X	X	X	X	X	|	Z..Z

L	L	X	X	X..X	X	X	X	X	|	L..L

L	H	L	X	X..X	X	X	X	|	L..L

L	H	H	L	d[3..0]	X	X	X	|	d[3..0]

L	H	H	H	X..X	L	L	H	|	Count Up

L	H	H	H	X..X	L	L	L	|	Count Down

L	X	X	X	X..X	L	L	L	X	|	L..L	L

L	X	X	X	X..X	L	L	L	L	|	L..L	L

L	H	H	X	X..X	L	L	H	X	|	H,L,L,H	L

L	H	H	X	X..X	L	L	H	L	|	H,L,L,H	L

L	H	H	H	X..X	H	X	X	X	|	Inhibit Count

L	H	H	H	X..X	X	H	X	X	|	Inhibit Count

See also:

Counter Macrofunctions

Macrofunctions (by function)


74569 (Counter)

Binary Up/Down Counter with Synchronous Load and Clear and Asynchronous Clear

Default Signal Levels:	GND--OEN, CLK

VCC--ACLRN, SCLRN, LDN, D0, D1, D2, D3, U/DN, ENPN, ENTN

Function Prototype:

FUNCTION 74569 (clk, entn, enpn, aclrn, sclrn, u/dn, ldn, d[3..0], oen)

RETURNS (q[3..0], rcon, ccon);

This macrofunction is not directly supported by VHDL because it contains one or more port names with a slash (/) or dash (-). These characters are illegal in VHDL port names. However, you can use this macrofunction in your project by incorporating it into a lower-level design file, then inserting an instance of the lower-level file into your VHDL Design File. See Using a MAX+PLUS II Primitive or Macrofunction for more information.

Inputs	|	Outputs

OEN	ACLRN	SCLRN	LDN	D	ENTN	ENPN	U/DN	CLK	|	Q	RCON	CCON

H	X	X	X	X..X	X	X	X	X	|	Z..Z

L	L	X	X	X..X	X	X	X	X	|	L..L

L	H	L	X	X..X	X	X	X	|	L..L

L	H	H	L	d[3..0]	X	X	X	|	d[3..0]

L	H	H	H	X..X	L	L	H	|	Count Up

L	H	H	H	X..X	L	L	L	|	Count Down

L	X	X	X	X..X	L	L	L	X	|	L..L	L

L	X	X	X	X..X	L	L	L	L	|	L..L	L

L	H	H	X	X..X	L	L	H	X	|	H..H	L

L	H	H	X	X..X	L	L	H	L	|	H..H	L

L	H	H	H	X..X	H	X	X	X	|	Inhibit Count

L	H	H	H	X..X	X	H	X	X	|	Inhibit Count

See also:

Counter Macrofunctions

Macrofunctions (by function)


74589 (Shift Register)

8-Bit Shift Register with Input Latches and Tri-State Output

Default Signal Levels:	GND--OEN, SRCLK, SER, RCLK

VCC--SRLDN, D0, D1, D2, D3, D4, D5, D6, D7

Function Prototype:

FUNCTION 74589 (oen, srclk, ser, srldn, rclk, d[0..7])

RETURNS (qhn);

Inputs	|	Input	|	Shift	|	Output

|	Registers	|	Registers	|

OEN	SRCLK	SER	SRLDN	RCLK	D0..D7	|	I0..I7*	|	Q7..Q0**	|	QHN

H	X	X	X	X	X..X	|	i0..i7	|	q0..q7	|	Z

L	X	X	X	X	X..X	|	i0..i7	|	q0..q7	|	/Q7

X	L	H	X	X..X	|	i0..i7	|	q0..q6, L	|

X	H	H	X	X..X	|	i0..i7	|	q0..q6, H	|

X	L	H	H	X	X..X	|	i0..i7	|	q0..q7	|

X	X	X	L	X	X..X	|	i0..i7	|	I0..I7	|

X	X	X	X	a..h	|	a..h	|	q0..q7	|

*	I7..I0 are internal input registers.

**	Q7..Q0 are internal shift registers.

See also:

Macrofunctions (by function)

Shift Register Macrofunctions


74590 (Counter)

8-Bit Binary Counter with Tri-State Output Registers

Default Signal Levels:	GND--GN, CCKEN, CCLK, RCLK

VCC--CCLRN

Function Prototype:

FUNCTION 74590 (gn, cclrn, ccken, cclk, rclk)

RETURNS (qh, qg, qf, qe, qd, qc, qb, qa, rcon);

Inputs	|	Internal	|	Outputs

|	Registers	|

GN	CCLRN	CCKEN	CCLK	RCLK	|	CH..CA*	|	QH..QA	RCON

H	H	L	X	|	Count	|	Z

H	H	H	X	X	|	ch..ca	|	Z

L	L	X	X	X	|	L..L	|

L	H	H	X	|	ch..ca	|	ch..ca

L	H	L	L	|	Count	|	QH0..QA0

L	X	X	X	X	|	H..H	|	L

*	CH..CA are internal counter registers.

See also:

Counter Macrofunctions

Macrofunctions (by function)


74592 (Counter)

8-Bit Binary Counter with Input Registers

Default Signal Levels:	GND--RCLK, CCKEN, CCLK

VCC--CLOADN, CCLRN, A, B, C, D, E, F, G, H

Function Prototype:

FUNCTION 74592 (cclrn, cloadn, rclk, ccken, cclk, h, g, f, e, d, c, b, a)

RETURNS (rcon);

Inputs	|	Input	|	Counter	|	Output

|	Register	|	|

CCLRN	CLOADN	RCLK	CCKEN	CCLK	H..A	|	IH..IA*	|	CH..CA**	|	RCON

L	X	X	X	X	X..X	|	iH..iA	|	L..L	|	H

H	L	X	X	X	X..X	|	iH..iA	|	IH..IA	|

H	H	X	X	h..a	|	h..a	|	CH..CA	|

H	H	X	L	X..X	|	iH..iA	|	Count	|

H	H	X	H	X..X	|	iH..iA	|	cH..cA	|

H	X	X	X	X	X..X	|	iH..iA	|	L..L	|	L

*	IH..IA are internal input registers.

**	CH..CA are internal counters.

See also:

Counter Macrofunctions

Macrofunctions (by function)


74594 (Shift Register)

8-Bit Shift Register with Output Latches

Default Signal Levels:	GND--RCLK, SRCLK, SER

VCC--RCLRN, SRCLRN

Function Prototype:

FUNCTION 74594 (srclrn, rclrn, srclk, rclk, ser)

RETURNS (qa, qb, qc, qd, qe, qf, qg, qh, qhn);

Inputs	|	Internal	|	Outputs

|	Registers	|

SRCLRN	RCLRN	SRCLK	RCLK	SER	|	SRA..SRH*	|	QA..QH	QHN

L	X	X	X	X	|	L..L	|	H

X	L	X	X	X	|	|	L..L

H	H	L	a	|	a, SRA..SRG	|	QA..QH	/SRG

H	H	L	X	|	|	SRA..SRH	/SRH

*	SRA..SRH are the internal outputs of the shift register.

See also:

Macrofunctions (by function)

Shift Register Macrofunctions


74595 (Shift Register)

8-Bit Shift Register with Output Latches and Tri-State Outputs

Default Signal Levels:	GND--RCLK, SRCLK, SER, GN

VCC--SRCLRN

Function Prototype:

FUNCTION 74595 (gn, srclrn, srclk, rclk, ser)

RETURNS (qa, qb, qc, qd, qe, qf, qg, qh, qhn);

Inputs	|	Internal	|	Outputs

|	Registers	|

GN	SRCLRN	SRCLK	RCLK	SER	|	SRA..SRH*	|	QA..QH	QHN

H	X	X	X	X	|	X..X	|	Z..Z

L	L	X	X	X	|	L..L	|	L..L	H

L	H	L	a	|	a, SRAo..SRG	|	QA..QH	/SRG

L	H	L	X	|	|	SRA..SRH	/SRH

*	SRA..SRH are the internal outputs of the shift registers.

See also:

Macrofunctions (by function)

Shift Register Macrofunctions


74597 (Shift Register)

8-Bit Shift Register with Input Register

Default Signal Levels:	GND--SRCLK, SER, RCLK

VCC--SRCLRN, SRLDN, D0, D1, D2, D3, D4, D5, D6, D7

Function Prototype:

FUNCTION 74597 (srclrn, srldn, rclk, d[7..0], srclk, ser)

RETURNS (qhn);

Inputs	|	Input	|	Shift	|	Output

|	Register	|	Register	|

SRCLRN	SRLDN	RCLK	D	SRCLK	SER	|	I	|	SRA..SRH	|	QHN

L	H	X	X..X	X	X	|	i0..i7	|	L..L	|	H

H	L	X	X..X	X	X	|	i0..i7	|	I0..I7	|	/SRH

H	H	a..h	X	X	|	a..h	|	SRA..SRH	|	/SRH

H	H	L	X..X	L	|	i0..i7	|	SRA..SRG, L	|	/SRG

H	H	L	X..X	H	|	i0..i7	|	SRA..SRG, H	|	/SRG

See also:

Macrofunctions (by function)

Shift Register Macrofunctions


74365 (Buffer)

Hex Tri-State Buffer

Default Signal Levels:	GND--GN1, GN2

VCC--A1, A2, A3, A4, A5, A6

Function Prototype:

FUNCTION 74365 (gn1, gn2, a[1..6])

RETURNS (y[1..6]);

Inputs	|	Outputs

GN1	GN2	A	|	Y

H	X	X	|	Z

X	H	X	|	Z

L	L	L	|	L

L	L	H	|	H

See also:

Buffer Macrofunctions

Macrofunctions (by function)


74366 (Buffer)

Hex Inverting Tri-State Buffer

Default Signal Levels:	GND--GN1, GN2

VCC--A1, A2, A3, A4, A5, A6

Function Prototype:

FUNCTION 74366 (gn1, gn2, a[1..6])

RETURNS (yn[1..6]);

Inputs	|	Outputs

GN1	GN2	A	|	YN

H	X	X	|	Z

X	H	X	|	Z

L	L	L	|	H

L	L	H	|	L

See also:

Buffer Macrofunctions

Macrofunctions (by function)


74367 (Buffer)

Hex Tri-State Buffer

Default Signal Levels:	GND--1GN, 2GN

VCC--1A1, 1A2, 1A3, 1A4, 2A1, 2A2

Function Prototype:

FUNCTION 74367 (1gn, 1a[1..4], 2gn, 2a[1..2])

RETURNS (1y[1..4], 2y[1..2]);

Inputs	|	Outputs

1GN	2GN	1A	2A	|	1Y	2Y

H	H	X	X	|	Z	Z

L	L	X	L	|	L

L	L	X	H	|	H

L	L	L	X	|	L

L	L	H	X	|	H

See also:

Buffer Macrofunctions

Macrofunctions (by function)


74368 (Buffer)

Hex Inverting Tri-State Buffer

Default Signal Levels:	GND--1GN, 2GN

VCC--1A1, 1A2, 1A3, 1A4, 2A1, 2A2

Function Prototype:

FUNCTION 74368 (1gn, 1a[1..4], 2gn, 2a[1..2])

RETURNS (1yn[1..4], 2yn[1..2]);

Inputs	|	Outputs

1GN	2GN	1A	2A	|	1YN	2YN

H	H	X	X	|	Z	Z

L	L	X	L	|	H

L	L	X	H	|	L

L	L	L	X	|	H

L	L	H	X	|	L

See also:

Buffer Macrofunctions

Macrofunctions (by function)


74373 (Latch)

Octal Transparent D-Type Latch with Tri-State Outputs

Default Signal Levels:	GND--all input pins

Function Prototype:

FUNCTION 74373 (oen, g, d[8..1])

RETURNS (q[8..1]);

Inputs	|	Outputs

OEN	G	D	|	Q

H	X	X	|	Z

L	X	X	|	X

L	H	L	|	L

L	H	H	|	H

L	L	X	|	Qo

See also:

Latch Macrofunctions

Macrofunctions (by function)


74374 (Register)

Octal D-Type Flipflop with Output Enable and Tri-State Outputs

Default Signal Levels:	GND--all input pins

Function Prototype:

FUNCTION 74374 (clk, oen, d[8..1])

RETURNS (q[8..1]);

Inputs	|	Outputs

OEN	CLK	D	|	Q

H	X	X	|	Z

L	X	X	|	X

L	L	|	L

L	H	|	H

L	L	X	|	Qo

See also:

Macrofunctions (by function)

Register Macrofunctions


74375 (Latch)

4-Bit Bistable Latch

Default Signal Levels:	GND--1D, 2D, 3D, 4D

VCC--E12, E34

Function Prototype:

FUNCTION 74375 (1d, 2d, 3d, 4d, e12, e34)

RETURNS (1q, 1qn, 2q, 2qn, 3q, 3qn, 4q, 4qn);

Inputs	|	Outputs

D	E	|	Q	QN

L	H	|	L	H

H	H	|	H	L

X	L	|	Qo	/Qo

See also:

Latch Macrofunctions

Macrofunctions (by function)


74376 (Register)

Quad JK-Type Flipflop with Common Clock and Common Clear

Default Signal Levels:	GND--CLK, 1J, 2J, 3J, 4J

VCC--CLRN, 1KN, 2KN, 3KN, 4KN

Function Prototype:

FUNCTION 74376 (clk, clrn, 1j, 1kn, 2j, 2kn, 3j, 3kn, 4j, 4kn)

RETURNS (1q, 2q, 3q, 4q);

Inputs	|	Outputs

CLRN	CLK	J	KN	|	Q

L	X	X	X	|	L

H	L	H	|	Qo

H	H	H	|	H

H	L	L	|	L

H	H	L	|	Toggle

H	L	X	X	|	Qo

See also:

Macrofunctions (by function)

Register Macrofunctions


74377 (Register)

Octal D-Type Flipflop with Enable

Default Signal Levels:	GND--EN, CLK

VCC--D1, D2 ,D3, D4, D5, D6, D7, D8

Function Prototype:

FUNCTION 74377 (en, clk, d[8..1])

RETURNS (q[8..1]);

Inputs	|	Outputs

EN	CLK	D	|	Q

H	X	X	|	Qo

L	H	|	H

L	L	|	L

X	L	X	|	Qo

See also:

Macrofunctions (by function)

Register Macrofunctions


74378 (Register)

Hex D-Type Flipflop with Enable

Default Signal Levels:	GND--EN, CLK

VCC--D1, D2, D3, D4, D5, D6

Function Prototype:

FUNCTION 74378 (en, clk, d[6..1])

RETURNS (q[6..1]);

Inputs	|	Outputs

EN	CLK	D	|	Q

H	X	X	|	Qo

L	H	|	H

L	L	|	L

X	L	X	|	Qo

See also:

Macrofunctions (by function)

Register Macrofunctions


74379 (Register)

Quad D-Type Flipflop with Enable

Default Signal Levels:	GND--EN, CLK

VCC--D1, D2, D3, D4

Function Prototype:

FUNCTION 74379 (en, clk, d[4..1])

RETURNS (q[4..1], qn[4..1]);

Inputs	|	Outputs

EN	CLK	D	|	Q	QN

H	X	X	|	Qo	/Qo

L	H	|	H	L

L	L	|	L	H

X	L	X	|	Qo	/Qo

See also:

Macrofunctions (by function)

Register Macrofunctions


74381 (Arithmetic Logic Unit)

Arithmetic Logic Unit/Function Generator

Default Signal Levels:	GND--all input pins

Function Prototype:

FUNCTION 74381 (s[2..0], a[3..0], b[3..0], cin)

RETURNS (pn, gn, f[3..0]);

Inputs	|	Outputs

Operation	S2	S1	S0	|	F[3..0]

Clear	L	L	L	|	L

B - A	L	L	H	|	B - A - Cn

A - B	L	H	L	|	A - B - Cn

A + B	L	H	H	|	A + B + Cn

A $ B	H	L	L	|	A $ B

A # B	H	L	H	|	A # B

A & B	H	H	L	|	A & B

Preset	H	H	H	|	H

The GN and PN outputs are for cascading multiple 74381’s with a 74182.

See also:

Arithmetic Logic Unit Macrofunctions

Macrofunctions (by function)


74382 (Arithmetic Logic Unit)

Arithmetic Logic Unit/Function Generator

Default Signal Levels:	GND--all input pins

Function Prototype:

FUNCTION 74382 (s[2..0], a[3..0], b[3..0], cin)

RETURNS (ovr, cn4, f[3..0]);

Inputs	|	Outputs

Operation	S2	S1	S0	|	F[3..0]

Clear	L	L	L	|	L

B - A	L	L	H	|	B - A - Cn

A - B	L	H	L	|	A - B - Cn

A + B	L	H	H	|	A + B + Cn

A $ B	H	L	L	|	A $ B

A # B	H	L	H	|	A # B

A & B	H	H	L	|	A & B

Preset	H	H	H	|	H

A typical application for a 74382 is to cascade three 74381 macrofunctions before it and use a 74182 to generate carry look-aheads, resulting in overflows (OVR) and a carry-out (CN4) for 16-bit operations.

See also:

Arithmetic Logic Unit Macrofunctions

Macrofunctions (by function)


74385 (Adder)

4-Bit Adder/Subtractor with Clear

Default Signal Levels:	GND--CLK, 1A, 1B, 2A, 2B, 3A, 3B, 4A, 4B

VCC--1S/AN, 2S/AN, 3S/AN, 4S/AN, CLRN

Function Prototype:

FUNCTION 74385 (clrn, 1s/an, 1a, 1b, 2s/an, 2a, 2b, 3s/an, 3a, 3b, 4s/an, 4a, 4b, clk)

RETURNS (1s, 2s, 3s, 4s);

This macrofunction is not directly supported by VHDL because it contains one or more port names with a slash (/) or dash (-). These characters are illegal in VHDL port names. However, you can use this macrofunction in your project by incorporating it into a lower-level design file, then inserting an instance of the lower-level file into your VHDL Design File. See Using a MAX+PLUS II Primitive or Macrofunction for more information.

Inputs	|	Data-In Carry	|	Outputs	|	Function

|	Flipflop	|	|

CLRN	S/AN	A	B	CLK	|	Before 	After 	|	S	|

L	L	X	X	X	|	L	L	|	L	|	Clear

L	H	X	X	X	|	H	H	|	L	|	Clear

H	L	L	L	|	L	L	|	L	|	Add

H	L	L	L	|	H	L	|	H	|	Add

H	L	L	H	|	L	L	|	H	|	Add

H	L	L	H	|	H	H	|	L	|	Add

H	L	H	L	|	L	L	|	H	|	Add

H	L	H	L	|	H	H	|	L	|	Add

H	L	H	H	|	L	H	|	L	|	Add

H	L	H	H	|	H	H	|	H	|	Add

H	H	L	L	|	L	L	|	H	|	Subtract

H	H	L	L	|	H	H	|	L	|	Subtract

H	H	L	H	|	L	L	|	L	|	Subtract

H	H	L	H	|	H	L	|	H	|	Subtract

H	H	H	L	|	L	H	|	L	|	Subtract

H	H	H	L	|	H	H	|	H	|	Subtract

H	H	H	H	|	L	L	|	H	|	Subtract

H	H	H	H	|	H	H	|	L	|	Subtract

See also:

Adder Macrofunctions

Macrofunctions (by function)


74386 (SSI Function)

Quad XOR Gate

Default Signal Levels:	VCC--all input pins

Function Prototype:

FUNCTION 74386 (a[1..4], b[1..4])

RETURNS (y[1..4]);

Inputs	|	Outputs

A	B	|	Y

L	L	|	L

L	H	|	H

H	L	|	H

H	H	|	L

See also:

Macrofunctions (by function)

SSI Functions


74390 (Counter)

Dual Decade Counter

Default Signal Levels:	GND--1CLR, 1CLKB, 2CLR, 2CLKB

VCC--1CLKA, 2CLKA

Function Prototype:

FUNCTION 74390 (1clr, 1clka, 1clkb, 2clr, 2clka, 2clkb)

RETURNS (1qd, 1qc, 1qb, 1qa, 2qd, 2qc, 2qb, 2qa);

Inputs	|	Outputs

CLR	CLK	|	QD	QC	QB	QA

H	X	|	L	L	L	L

L	|	Count

Possible Counting Configurations:

Decade: QA Connected to CLKB	|	Bi-Quinary: QD Connected to CLKA

Count	|	QD	QC	QB	QA	|	Count	|	QA	QD	QC	QB

0	|	L	L	L	L	|	0	|	L	L	L	L

1	|	L	L	L	H	|	1	|	L	L	L	H

2	|	L	L	H	L	|	2	|	L	L	H	L

3	|	L	L	H	H	|	3	|	L	L	H	H

4	|	L	H	L	L	|	4	|	L	H	L	L

5	|	L	H	L	H	|	5	|	H	L	L	L

6	|	L	H	H	L	|	6	|	H	L	L	H

7	|	L	H	H	H	|	7	|	H	L	H	L

8	|	H	L	L	L	|	8	|	H	L	H	H

9	|	H	L	L	H	|	9	|	H	H	L	L

See also:

Counter Macrofunctions

Macrofunctions (by function)


74393 (Counter)

Dual 4-Bit Up Counter with Asynchronous Clear

Default Signal Levels:	GND--CLR1, CLR2

VCC--A1, A2

Function Prototype:

FUNCTION 74393 (a1, clr1, a2, clr2)

RETURNS (q1a, q1b, q1c, q1d, q2a, q2b, q2c, q2d);

Count	|	Inputs	|	Outputs

|	A	CLR	|	QD	QC	QB	QA

|	X	H	|	L	L	L	L

0	|	L	|	L	L	L	L

1	|	L	|	L	L	L	H

2	|	L	|	L	L	H	L

3	|	L	|	L	L	H	H

4	|	L	|	L	H	L	L

5	|	L	|	L	H	L	H

6	|	L	|	L	H	H	L

7	|	L	|	L	H	H	H

8	|	L	|	H	L	L	L

9	|	L	|	H	L	L	H

10	|	L	|	H	L	H	L

11	|	L	|	H	L	H	H

12	|	L	|	H	H	L	L

13	|	L	|	H	H	L	H

14	|	L	|	H	H	H	L

15	|	L	|	H	H	H	H

See also:

Counter Macrofunctions

Macrofunctions (by function)


74395 (Shift Register)

4-Bit Cascadable Shift Register with Tri-State Outputs

Default Signal Levels:	GND--OEN

VCC--LD/SHN, SER, D1, D2, D3, D4, CLRN, CLK

Function Prototype:

FUNCTION 74395 (clrn, ld/shn, clk, ser, d[1..4], oen)

RETURNS (q[1..4], q4b);

This macrofunction is not directly supported by VHDL because it contains one or more port names with a slash (/) or dash (-). These characters are illegal in VHDL port names. However, you can use this macrofunction in your project by incorporating it into a lower-level design file, then inserting an instance of the lower-level file into your VHDL Design File. See Using a MAX+PLUS II Primitive or Macrofunction for more information.

Inputs	|	Outputs

CLRN	LD/SHN	CLK	SER	D1	D2	D3	D4	|	Q1*	Q2*	Q3*	Q4*	Q4B

L	X	X	X	X	X	X	X	|	L	L	L	L	L

H	H	H	X	X	X	X	X	|	Q1o	Q2o	Q3o	Q4o	Q4o

H	H	X	a	b	c	d	|	a	b	c	d	d

H	L	H	X	X	X	X	X	|	Q1o	Q2o	Q3o	Q4o	Q4o

H	L	H	X	X	X	X	|	H	Q1n	Q2n	Q3n	Q3n

H	L	L	X	X	X	X	|	L	Q1n	Q2n	Q3n	Q3n

*	When OEN is H, Q[1..4] are Z, but the shift register continues to operate.

See also:

Macrofunctions (by function)

Shift Register Macrofunctions


74396 (Register)

Octal Storage Register

Default Signal Levels:	GND--STRBN, CLK

VCC--D1, D2, D3, D4

Function Prototype:

FUNCTION 74396 (strbn, clk, d1, d2, d3, d4)

RETURNS (1q1, 1q2, 1q3, 1q4, 2q1, 2q2, 2q3, 2q4);

Inputs	|	Outputs

STRBN	CLK	D1	D2	D3	D4	|	1Q1	1Q2	1Q3	1Q4	2Q1	2Q2	2Q3	2Q4

H	X	X	X	X	X	|	L	L	L	L	L	L	L	L

L	a	b	c	d	|	a	b	c	d	1Q1n	1Q2n	1Q3n	1Q4o

See also:

Macrofunctions (by function)

Register Macrofunctions


74398 (Multiplexer)

Quad 2-Input Multiplexer with Storage

Default Signal Levels:	GND--CLK

VCC--SEL, A1, A2, B1, B2, C1, C2, D1, D2

Function Prototype:

FUNCTION 74398 (sel, a1, b1, c1, d1, a2, b2, c2, d2, clk)

RETURNS (qa, qan, qb, qbn, qc, qcn, qd, qdn);

Inputs	|	Outputs

SEL	CLK	|	QA	QB	QC	QD

L	|	A1	B1	C1	D1

H	|	A2	B2	C2	D2

X	L	|	QAo	QBo	QCo	QDo

QAN = /QA, QBN = /QB, QCN = /QC, QDN = /QD

See also:

Macrofunctions (by function)

Multiplexer Macrofunctions


74399 (Multiplexer)

Quad 2-Input Multiplexer with Storage

Default Signal Levels:	GND--CLK

VCC--SEL, A1, A2, B1, B2, C1, C2, D1, D2

Function Prototype:

FUNCTION 74399 (sel, a1, b1, c1, d1, a2, b2, c2, d2, clk)

RETURNS (qa, qb, qc, qd);

Inputs	|	Outputs

SEL	CLK	|	QA	QB	QC	QD

L	|	A1	B1	C1	D1

H	|	A2	B2	C2	D2

X	L	|	QAo	QBo	QCo	QDo

See also:

Macrofunctions (by function)

Multiplexer Macrofunctions


74259 (Latch)

8-Bit Addressable Latch with Clear

Default Signal Levels:	VCC--all input pins

Function Prototype:

FUNCTION 74259 (clrn, gn, s[2..0], data)

RETURNS (q[7..0]);

Inputs	|	Outputs	|	Function

|	Addressed	|	Other	|

CLRN	GN	|	Latch	|	Latches	|

H	L	|	DATA	|	Qio	|	Addressable Latch

H	H	|	Qio	|	Qio	|	Memory

L	L	|	DATA	|	L	|	8-Line Demux

L	H	|	L	|	L	|	Clear

Qio = level of Q (i = 0..7) before the indicated steady-state input conditions were established.

Latch Selection Table:

Select Inputs	|	Latch Addressed

S2	S1	S0	|

L	L	L	|	0

L	L	H	|	1

L	H	L	|	2

L	H	H	|	3

H	L	L	|	4

H	L	H	|	5

H	H	L	|	6

H	H	H	|	7

See also:

Latch Macrofunctions

Macrofunctions (by function)


74260 (SSI Function)

Dual 5-Input Positive NOR Gates

Default Signal Levels:	GND--all input pins

Function Prototype:

FUNCTION 74260 (a[0..4], b[0..4])

RETURNS (ayn, byn);

Inputs	|	Outputs

A0(B0)	A1(B1)	A2(B2)	A3(B3)	A4(B4)	|	AYN(BYN)

L	L	L	L	L	|	H

H	X	X	X	X	|	L

X	H	X	X	X	|	L

X	X	H	X	X	|	L

X	X	X	H	X	|	L

X	X	X	X	H	|	L

See also:

Macrofunctions (by function)

SSI Functions


74261 (Multiplier)

2-Bit Parallel Binary Multiplier

Default Signal Levels:	GND--B0, B1, B2, B3, B4, M0, M1, M2

VCC--G

Function Prototype:

FUNCTION 74261 (b[4..0], m[2..0], g)

RETURNS (q4n, q[3..0]);

Inputs	|	Outputs

Latch	|	Multiplier	|

Control G	|	M2	M1	M0	|	Q4N	Q3	Q2	Q1	Q0

L	|	X	X	X	|	/Q4o	Q3o	Q2o	Q1o	Q0o

H	|	L	L	L	|	H	L	L	L	L

H	|	L	L	H	|	/B4	B4	B3	B2	B1

H	|	L	H	L	|	/B4	B4	B3	B2	B1

H	|	L	H	H	|	/B4	B3	B2	B1	B0

H	|	H	L	L	|	B4	/B3	/B2	/B1	/B0

H	|	H	L	H	|	B4	/B4	/B3	/B2	/B1

H	|	H	H	L	|	B4	/B4	/B3	/B2	/B1

H	|	H	H	H	|	H	L	L	L	L

B4..B0 = the logic level of the indicated multiplicand (B) input.

Q4o..Qo = the logic level of the same output before the [image] transition of G.

See also:

Macrofunctions (by function)

Multiplier Macrofunctions


74265 (True/Complement I/O Element)

Quad Complementary Output Elements

Default Signal Levels:	VCC--all input pins

Function Prototype:

FUNCTION 74265 (1a, 2a, 2b, 3a, 3b, 4a)

RETURNS (1w, 1yn, 2w, 2yn, 3w, 3yn, 4w, 4yn);

Inputs	|	Outputs

1A (4A)	|	1W(4W)	1YN(4YN)

L	|	L	H

H	|	H	L

Inputs	|	Outputs

2A(3A)	2B(3B)	|	2W(3W)	2YN(3YN)

L	X	|	L	H

X	L	|	L	H

H	H	|	H	L

See also:

Macrofunctions (by function)

True/Complement I/O Element Macrofunctions


74273 (Register)

Octal D-Type Flipflop with Asynchronous Clear

Default Signal Levels:	GND--D1, D2, D3, D4, D5, D6, D7, D8, CLK

VCC--CLRN

Function Prototype:

FUNCTION 74273 (clrn, clk, d[8..1])

RETURNS (q[8..1]);

Inputs	|	Outputs

CLRN	CLK	D	|	Q

L	X	X	|	L

H	H	|	H

H	L	|	L

H	L	X	|	Qo

See also:

Macrofunctions (by function)

Register Macrofunctions


74276 (Register)

Quad J/K-Type Flipflop Register with Common Preset and Clear

Default Signal Levels:	GND--1J, 1CLK, 2J, 2CLK, 3J, 3CLK, 4J, 4CLK

VCC--PRN, CLRN, 1KN, 2KN, 3KN, 4KN

Function Prototype:

FUNCTION 74276 (prn, clrn, 1j, 1kn, 1clk, 2j, 2kn, 2clk, 3j, 3kn, 3clk, 4j, 4kn, 4clk)

RETURNS (1q, 1qn, 2q, 2qn, 3q, 3qn, 4q, 4qn);

Inputs	|	Outputs

CLRN	PRN	J	KN	CLK	|	Q	QN

L	H	X	X	X	|	L	H

H	L	X	X	X	|	H	L

L	L	X	X	X	|	Illegal

H	H	L	H	|	Qo	QNo

H	H	H	H	|	H	L

H	H	L	L	|	L	H

H	H	H	L	|	Toggle

H	H	X	X	H	|	Qo	QNo

See also:

Macrofunctions (by function)

Register Macrofunctions


74278 (Storage Register)

4-Bit Cascadable Priority Register

Default Signal Levels:	GND--D1, D2, D3, D4, P0

VCC--G

Function Prototype:

FUNCTION 74278 (p0, g, d[4..1])

RETURNS (y[4..1], p1);

Inputs	|	Internal Latch Nodes	|	Outputs

P0	G	|	D1	D2	D3	D4	|	/Q1	/Q2	/Q3	/Q4	|	Y1	Y2	Y3	Y4	P1

L	H	|	H	X	X	X	|	L	X	X	X	|	H	L	L	L	H

L	H	|	L	H	X	X	|	H	L	X	X	|	L	H	L	L	H

L	H	|	L	L	H	X	|	H	H	L	X	|	L	L	H	L	H

L	H	|	L	L	L	H	|	H	H	H	L	|	L	L	L	H	H

L	H	|	L	L	L	L	|	H	H	H	H	|	L	L	L	L	L

L	L	|	X	X	X	X	|	Latched when G goes low	|	Same function of /Q

|	|	|	as on first 5 lines

H	L	|	X	X	X	X	|	|	L	L	L	L	H

H	H	|	Internal /Q levels are the same function of D	|	L	L	L	L	H

|	inputs as on the first 5 lines.	|

See also:

Macrofunctions (by function)

Storage Register Macrofunctions


74279 (Latch)

Quad /SR Latch

Default Signal Levels: GND--all input pins

Function Prototype:

FUNCTION 74279 (s11n, s12n, r1n, s2n, r2n, s31n, s32n, r3n, s4n, r4n)

RETURNS (q[4..1]);

Inputs	|	Output

SN*	RN	|	Q

H	H	|	Qo

L	H	|	H

H	L	|	L

L	L	|	H**

*	For latches with double S inputs:

H = both SN inputs high.

L = one or both SN inputs low.

**	This configuration is nonstable; that is, it may not persist when the SN and RN inputs return to their inactive (high) level.

See also:

Latch Macrofunctions

Macrofunctions (by function)


74280 (Parity Generator/Checker)

9-Bit Odd/Even Parity Generator/Checker

Default Signal Levels: GND--all input pins

Function Prototype:

FUNCTION 74280 (a, b, c, d, e, f, g, h, i)

RETURNS (even, odd);

Number of Inputs A	|	Outputs

through I that are High	|

|	EVEN	ODD

0, 2, 4, 6, 8	|	H	L

1, 3, 5, 7, 9	|	L	H

See also:

Macrofunctions (by function)

Parity Generator/Checker Macrofunctions


74283 (Full Adder)

4-Bit Full Adder with Fast Carry Note

Default Signal Levels:	GND--all input pins

Function Prototype:

FUNCTION 74283 (a[4..1], b[4..1], cin)

RETURNS (cout, sum[4..1]);

Inputs	|	Outputs

|	When COUT0 = L	|	When COUT0 = H

|	[When COUT2 = L]	|	[When COUT2 = H]

|	SUM1	SUM2	COUT2	|	SUM1	SUM2	COUT2

A1 [A3]	B1 [B3]	A2 [A4]	B2 [B4]	|	[SUM3]	[SUM4]	[COUT4]	|	[SUM3]	[SUM4]	[COUT4]

L	L	L	L	|	L	L	L	|	H	L	L

H	L	L	L	|	H	L	L	|	L	H	L

L	H	L	L	|	H	L	L	|	L	H	L

H	H	L	L	|	L	H	L	|	H	H	L

L	L	H	L	|	L	H	L	|	H	H	L

H	L	H	L	|	H	H	L	|	L	L	H

L	H	H	L	|	H	H	L	|	L	L	H

H	H	H	L	|	L	L	H	|	H	L	H

L	L	L	H	|	L	H	L	|	H	H	L

H	L	L	H	|	H	H	L	|	L	L	H

L	H	L	H	|	H	H	L	|	L	L	H

H	H	L	H	|	L	L	H	|	H	L	H

L	L	H	H	|	L	L	H	|	H	L	H

H	L	H	H	|	H	L	H	|	L	H	H

L	H	H	H	|	H	L	H	|	L	H	H

H	H	H	H	|	L	H	H	|	H	H	H

Input conditions at A1, B1, A2, B2, COUT0 are used to determine outputs SUM1 and SUM2 and the value of internal carry COUT2. The values at COUT2, A3, B3, A4, B4 are then used to determine outputs SUM3, SUM4, and COUT4 (COUT).

See also:

Adder Macrofunctions

Macrofunctions (by function)


74284 (Multiplier)

4-Bit-by-4-Bit Parallel Binary Multiplier (Upper 4 Bits of Result)

Default Signal Levels:	GND--GAN, GBN

VCC--A1, A2, A3, A4, B1, B2, B3, B4

Function Prototype:

FUNCTION 74284 (gan, gbn, a[4..1], b[4..1])

RETURNS (y[8..5]);

Inputs	|	Outputs

GAN	GBN	A[4..1]	B[4..1]	|	Y[8..5]

1	1	X	X	|	0

1	0	X	X	|	0

0	1	X	X	|	0

0	0	A[4..1]	B[4..1]	|	Y[8..5] = A [4..1] * B[4..1]

See also:

Macrofunctions (by function)

Multiplier Macrofunctions


74285 (Multiplier)

4-Bit-by-4-Bit Parallel Binary Multiplier (Lower 4 Bits of Result)

Default Signal Levels:	GND--GAN, GBN

VCC--A1, A2, A3, A4, B1, B2, B3, B4

Function Prototype:

FUNCTION 74285 (gan, gbn, a[4..1], b[4..1])

RETURNS (y[4..1]);

Inputs	|	Outputs

GAN	GBN	A[4..1]	B[4..1]	|	Y[4..1]

1	1	X	X	|	0

1	0	X	X	|	0

0	1	X	X	|	0

0	0	A[4..1]	B[4..1]	|	Y[4..1] = A [4..1] * B[4..1]

See also:

Macrofunctions (by function)

Multiplier Macrofunctions


74290 (Counter)

Decade Counter with Clear

Default Signal Levels:	GND--SET9A, SET9B, CLRA, CLRB

VCC--CLKA, CLKB

Function Prototype:

FUNCTION 74290 (clka, clkb, clra, clrb, set9a, set9b)

RETURNS (qd, qc, qb, qa);

Inputs	|	Outputs

CLR*	SET**	CLK	|	QD	QC	QB	QA

H	L	X	|	L	L	L	L

L	H	X	|	H	L	L	H

H	H	X	|	Illegal

L	L	|	Count

*	CLR = CLRA & CLRB

**	SET = SET9A & SET9B

Possible Counting Configurations:

Decade: QA Connected to CLKB	|	Bi-Quinary: QD Connected to CLKA

Count	|	QD	QC	QB	QA	|	Count	|	QD	QC	QB	QA

0	|	L	L	L	L	|	0	|	L	L	L	L

1	|	L	L	L	H	|	1	|	L	L	L	H

2	|	L	L	H	L	|	2	|	L	L	H	L

3	|	L	L	H	H	|	3	|	L	L	H	H

4	|	L	H	L	L	|	4	|	L	H	L	L

5	|	L	H	L	H	|	5	|	H	L	L	L

6	|	L	H	H	L	|	6	|	H	L	L	H

7	|	L	H	H	H	|	7	|	H	L	H	L

8	|	H	L	L	L	|	8	|	H	L	H	H

9	|	H	L	L	H	|	9	|	H	H	L	L

See also:

Counter Macrofunctions

Macrofunctions (by function)


74292 (Counter)

Programmable Frequency Divider/Digital Timer

Default Signal Levels:	GND--CLK1, CLK2

VCC--A, B, C, D, E, CLRN

Function Prototype:

FUNCTION 74292 (clk1, clk2, clrn, e, d, c, b, a)

RETURNS (q, tp1, tp2, tp3);

Inputs	|	Outputs

E	D	C	B	A	|	Q	|	TP1	|	TP2	|	TP3

|	BIN	DEC	|	|	|	BIN	DEC

L	L	L	L	L	|	Inhb	Inhb	|	Inhb	Inhb	|	Inhb	Inhb	|	Inhb	Inhb

L	L	L	L	H	|	Inhb	Inhb	|	Inhb	Inhb	|	Inhb	Inhb	|	Inhb	Inhb

L	L	L	H	L	|	2^2	4	|	2^9	512	|	2^17	131,072	|	2^24	16,777,216

L	L	L	H	H	|	2^3	8	|	2^9	512	|	2^17	131,072	|	2^24	16,777,216

L	L	H	L	L	|	2^4	16	|	2^9	512	|	2^17	131,072	|	2^24	16,777,216

L	L	H	L	H	|	2^5	32	|	2^9	512	|	2^17	131,072	|	2^24	16,777,216

L	L	H	H	L	|	2^6	64	|	2^9	512	|	2^17	131,072	|	2^24	16,777,216

L	L	H	H	H	|	2^7	128	|	2^9	512	|	2^17	131,072	|	2^24	16,777,216

L	H	L	L	L	|	2^8	256	|	2^9	512	|	2^17	131,072	|	2^2	4

L	H	L	L	H	|	2^9	512	|	2^9	512	|	2^17	131,072	|	2^2	4

L	H	L	H	L	|	2^10	1,024	|	2^9	512	|	2^17	131,072	|	2^4	16

L	H	L	H	H	|	2^11	2,048	|	2^9	512	|	2^17	131,072	|	2^4	16

L	H	H	L	L	|	2^12	4,096	|	2^9	512	|	2^17	131,072	|	2^6	64

L	H	H	L	H	|	2^13	8,192	|	2^9	512	|	2^17	131,072	|	2^6	64

L	H	H	H	L	|	2^14	16,384	|	2^9	512	|	Disabled Low	|	2^8	256

L	H	H	H	H	|	2^15	32,768	|	2^9	512	|	Disabled Low	|	2^8	256

H	L	L	L	L	|	2^16	65,436	|	2^9	512	|	2^3	8	|	2^10	1,024

H	L	L	L	H	|	2^17	131,072	|	2^9	512	|	2^3	8	|	2^10	1,024

H	L	L	H	L	|	2^18	262,144	|	2^9	512	|	2^5	32	|	2^12	4,096

H	L	L	H	H	|	2^19	524.288	|	2^9	512	|	2^5	32	|	2^12	4,096

H	L	H	L	L	|	2^20	1,048,576	|	2^9	512	|	2^7	128	|	2^14	16,384

H	L	H	L	H	|	2^21	2,097,152	|	2^9	512	|	2^7	128	|	2^14	16,384

H	L	H	H	L	|	2^22	4,194,304	|	Disabled Low	|	2^9	512	|	2^16	65,436

H	L	H	H	H	|	2^23	8,388,608	|	Disabled Low	|	2^9	512	|	2^16	65,436

H	H	L	L	L	|	2^24	16,777,216	|	2^3	8	|	2^11	2,048	|	2^18	262,144

H	H	L	L	H	|	2^25	33,554,432	|	2^3	8	|	2^11	2,048	|	2^18	262,144

H	H	L	H	L	|	2^26	67,777,216	|	2^5	32	|	2^13	8,192	|	2^20	1,048,576

H	H	L	H	H	|	2^27	134,217,728	|	2^5	32	|	2^13	8,192	|	2^20	1,048,576

H	H	H	L	L	|	2^28	268,435,456	|	2^7	128	|	2^16	65,436	|	2^22	4,194,304

H	H	H	L	H	|	2^29	536,870,912	|	2^7	128	|	2^16	65,436	|	2^22	4,194,304

H	H	H	H	L	|	2^30	1,073,741,824	|	2^9	512	|	2^17	131,072	|	2^24	16,777,216

H	H	H	H	H	|	2^31	2,147,483,648	|	2^9	512	|	2^17	131,072	|	2^24	16,777,216

Inputs	|	Outputs

CLRN	CLK1	CLK2	|

L	X	X	|	Cleared to Low

H	L	|	Count

H	L	|	Count

H	H	X	|	Inhibit

H	X	H	|	Inhibit

See also:

Counter Macrofunctions

Macrofunctions (by function)


74293 (Counter)

Binary Counter with Clear

Default Signal Levels:	GND--all input pins

Function Prototype:

FUNCTION 74293 (clka, clkb, clra, clrb)

RETURNS (qd, qc, qb, qa);

Inputs	|	Outputs

CLR*	CLKA	CLKB	|	QD..QB	QA

H	X	X	|	L	L

L	X	|	Qd..Qb	Qa

L	X	|	Count	Qa

*	CLR = CLRA & CLRB

See also:

Counter Macrofunctions

Macrofunctions (by function)


74294 (Counter)

Programmable Frequency Divider/Digital Timer

Default Signal Levels: 	GND--CLK1, CLK2

VCC--CLRN, A, B, C, D

Function Prototype:

FUNCTION 74294 (clk1, clk2, clrn, d, c, b, a)

RETURNS (q, tp);

Inputs	|	Outputs

|	Q	|	TP

D	C	B	A	|	BIN	DEC	|	BIN	DEC

L	L	L	L	|	Inhb	Inhb	|	Inhb	Inhb

L	L	L	H	|	Inhb	Inhb	|	Inhb	Inhb

L	L	H	L	|	2^2	4	|	2^9	512

L	L	H	H	|	2^3	8	|	2^9	512

L	H	L	L	|	2^4	16	|	2^9	512

L	H	L	H	|	2^5	32	|	2^9	512

L	H	H	L	|	2^6	64	|	2^9	512

L	H	H	H	|	2^7	128	|	Disabled Low

H	L	L	L	|	2^8	256	|	2^2	4

H	L	L	H	|	2^9	512	|	2^3	8

H	L	H	L	|	2^10	1,024	|	2^4	16

H	L	H	H	|	2^11	2,048	|	2^5	32

H	H	L	L	|	2^12	4,096	|	2^6	64

H	H	L	H	|	2^13	8,192	|	2^7	128

H	H	H	L	|	2^14	16,384	|	2^8	256

H	H	H	H	|	2^15	32,768	|	2^9	512

Inputs	|	Outputs

CLRN	CLK1	CLK2	|

L	X	X	|	Cleared To Low

H	L	|	Count

H	L	|	Count

H	H	X	|	Inhibit

H	X	H	|	Inhibit

See also:

Counter Macrofunctions

Macrofunctions (by function)


74295 (Shift Register)

4-Bit Right-Shift Left-Shift Register with Tri-State Outputs

Default Signal Levels: VCC--all input pins

Function Prototype:

FUNCTION 74295 (oe, ld/shn, clk, ser, d[3..0])

RETURNS (q[3..0]);

This macrofunction is not directly supported by VHDL because it contains one or more port names with a slash (/) or dash (-). These characters are illegal in VHDL port names. However, you can use this macrofunction in your project by incorporating it into a lower-level design file, then inserting an instance of the lower-level file into your VHDL Design File. See Using a MAX+PLUS II Primitive or Macrofunction for more information.

Inputs	|	Outputs

OE	LD/SHN	CLK	SER	D0	D1	D2	D3	|	Q0	Q1	Q2	Q3

L	X	X	X	X	X	X	X	|	Z	Z	Z	Z

H	H	H	X	X	X	X	X	|	Q0o	Q1o	Q2o	Q3o

H	H	X	a	b	c	d	|	a	b	c	d

H	H	X	Q1*	Q2*	Q3*	d	|	Q1n	Q2n	Q3n	d

H	L	H	X	X	X	X	X	|	Q0o	Q1o	Q2o	Q3o

H	L	H	X	X	X	X	|	H	Q0n	Q1n	Q2n

H	L	L	X	X	X	X	|	L	Q0n	Q1n	Q2n

*	Left shift requires external connection of Q1 to D0, Q2 to D1, and Q3 to D2.

See also:

Macrofunctions (by function)

Shift Register Macrofunctions


74297 (Digital Filter)

Digital Phase-Locked Loop Filter

Default Signal Levels:	GND--KCLK, IDCLK, PHASE_A1, PHASE_B, PHASE_A2

VCC--D/UPN, ENCTR, D, C, B, A

Function Prototype:

FUNCTION 74297 (kclk, d/upn, enctr, d, c, b, a, idclk, phase_a1, phase_b, phase_a2)

RETURNS (idout, ecpd, xorpd);

This macrofunction is not directly supported by VHDL because it contains one or more port names with a slash (/) or dash (-). These characters are illegal in VHDL port names. However, you can use this macrofunction in your project by incorporating it into a lower-level design file, then inserting an instance of the lower-level file into your VHDL Design File. See Using a MAX+PLUS II Primitive or Macrofunction for more information.

K Counter Function Table:

Inputs	|	Output

D	C	B	A	|	Modulo (K)

L	L	L	L	|	Inhibited

L	L	L	H	|	2^3

L	L	H	L	|	2^4

L	L	H	H	|	2^5

L	H	L	L	|	2^6

L	H	L	H	|	2^7

L	H	H	L	|	2^8

L	H	H	H	|	2^9

H	L	L	L	|	2^10

H	L	L	H	|	2^11

H	L	H	L	|	2^12

H	L	H	H	|	2^13

H	H	L	L	|	2^14

H	H	L	H	|	2^15

H	H	H	L	|	2^16

H	H	H	H	|	2^17

XOR Phase Detector:

Inputs	|	Output

Phase_A1	Phase_B	|	XORPD

L	L	|	L

L	H	|	H

H	L	|	H

H	H	|	L

Edge-Controlled Phase Detector:

Inputs	|	Output

Phase_A2	Phase_B	|	ECPD

H or L	|	H

H or L	|	L

H or L	|	No Change

H or L	|	No Change

See also:

Digital Filter Macrofunctions

Macrofunctions (by function)


74298 (Multiplexer)

Quad 2-Input Multiplexer with Storage

Default Signal Levels:	GND--A1, A2, B1, B2, C1, C2, D1, D2, WRSL

VCC--CLKN

Function Prototype:

FUNCTION 74298 (wrsl, clkn, a1, b1, c1, d1, a2, b2, c2, d2)

RETURNS (qa, qb, qc, qd);

Inputs	|	Outputs

WRSL	CLKN	|	QA	QB	QC	QD

L	|	A1	B1	C1	D1

H	|	A2	B2	C2	D2

X	H	|	QAo*	QBo*	QCo*	QDo*

*	QAo..QDo = level of QA to QD entered on the most recent [image] transition of the Clock.

See also:

Macrofunctions (by function)

Multiplexer Macrofunctions


74299 (Shift Register)

8-Bit Universal Shift/Storage Register

Default Signal Levels:	GND--G1N, G2N, CLK, S0, S1, SL

VCC--CLRN, SR

Function Prototype:

FUNCTION 74299 (clrn, s1, s0, g1n, g2n, clk, sr, sl)

RETURNS (a/qa, b/qb, c/qc, d/qd, e/qe, f/qf, g/qg, h/qh, qa2, qh2);

This macrofunction is not directly supported by VHDL because it contains one or more port names with a slash (/) or dash (-). These characters are illegal in VHDL port names. However, you can use this macrofunction in your project by incorporating it into a lower-level design file, then inserting an instance of the lower-level file into your VHDL Design File. See Using a MAX+PLUS II Primitive or Macrofunction for more information.

Inputs	|	Outputs

CLRN	S1	S0	G1N	G2N	CLK	SL	SR	|	A/QA	|	B/QB..G/QG	|	H/QH	QA2	QH2

L	X	L	L	L	X	X	X	|	L	|	L..L	|	L	L	L

L	L	X	L	L	X	X	X	|	L	|	L..L	|	L	L	L

L	H	H	X	X	X	X	X	|	X	|	X	|	X	L	L

H	L	L	L	L	X	X	X	|	QAo	|	QBo..QGo	|	QHo	QAo	QHo

H	X	X	L	L	L	X	X	|	QAo	|	QBo..QGo	|	QHo	QAo	QHo

H	L	H	L	L	X	H	|	H	|	QAn..QFn	|	QGn	H	QGn

H	L	H	L	L	X	L	|	L	|	QAn..QFn	|	QGn	L	QGn

H	H	L	L	L	H	X	|	QBn	|	QCn..QHn	|	H	QBn	H

H	H	L	L	L	L	X	|	QBn	|	QCn..QHn	|	L	QBn	L

H	H	H	X	X	X	X	|	a	|	b..g	|	h	a	h

The macrofunction can only be fully utilized if A/QA..H/QH are connected to bidirectional I/O pins. There are no internal tri-state buffers in Altera devices. To use this macrofunction in a subdesign, you must select either pur inputs or pure outputs for the I/O pins.

This macrofunction can only be used at the top level or in a subdesign if A/QA..H/QH are connected to bidirectional I/O pins. There are no internal tri-state buffers in Altera devices.

To use this macrofunction in a subdesign, you must select either pure inputs or pure outputs for the I/O pins.

See also:

Macrofunctions (by function)

Shift Register Macrofunctions


74348 (Priority Encoder)

8-Line to 3-Line Priority Encoder with Tri-State Outputs

Default Signal Levels:	GND--EI

VCC--D0, D1, D2, D3, D4, D5, D6, D7

Function Prototype:

FUNCTION 74348 (ei, d[0..7])

RETURNS (eo, gs, a[2..0]);

Inputs	|	Outputs

EI	D0	D1	D2	D3	D4	D5	D6	D7	|	EO	GS	A2	A1	A0

H	X	X	X	X	X	X	X	X	|	H	H	Z	Z	Z

L	H	H	H	H	H	H	H	H	|	H	L	Z	Z	Z

L	X	X	X	X	X	X	X	L	|	L	H	L	L	L

L	X	X	X	X	X	X	L	H	|	L	H	L	L	H

L	X	X	X	X	X	L	H	H	|	L	H	L	H	L

L	X	X	X	X	L	H	H	H	|	L	H	L	H	H

L	X	X	X	L	H	H	H	H	|	L	H	H	L	L

L	X	X	L	H	H	H	H	H	|	L	H	H	L	H

L	X	L	H	H	H	H	H	H	|	L	H	H	H	L

L	L	H	H	H	H	H	H	H	|	L	H	H	H	H

See also:

Encoder Macrofunctions

Macrofunctions (by function)


74350 (Shift Register)

4-Bit Shift Register with Tri-State Outputs

Default Signal Levels:	GND--OEN

VCC--S1, S0, D0, D1, D2, D3, D-1, D-2, D-3

Function Prototype:

FUNCTION 74350 (oen, s0, s1, d-[3..1], d[0..3])

RETURNS (y[0..3]);

This macrofunction is not directly supported by VHDL because it contains one or more port names with a slash (/) or dash (-). These characters are illegal in VHDL port names. However, you can use this macrofunction in your project by incorporating it into a lower-level design file, then inserting an instance of the lower-level file into your VHDL Design File. See Using a MAX+PLUS II Primitive or Macrofunction for more information.

Inputs	|	Outputs

OEN	S0	S1	|	Y0	Y1	Y2	Y3

H	X	X	|	Z	Z	Z	Z

L	L	L	|	D0	D1	D2	D3

L	L	L	|	D-1	D0	D1	D2

L	L	H	|	D-2	D-1	D0	D1

L	H	H	|	D-3	D-2	D-1	D0

See also:

Macrofunctions (by function)

Shift Register Macrofunctions


74352 (Multiplexer)

Dual 4-Line-to-1-Line Data Selector/Multiplexer with Inverting Outputs

Default Signal Levels:	GND--all input pins

Function Prototype:

FUNCTION 74352 (b, a, 1gn, 1c[0..3], 2gn, 2c[0..3])

RETURNS (1yn, 2yn);

Inputs	|	Outputs

GN	B	A	C0	C1	C2	C3	|	YN

H	X	X	X	X	X	X	|	H

L	L	L	L	X	X	X	|	H

L	L	L	H	X	X	X	|	L

L	L	H	X	L	X	X	|	H

L	L	H	X	H	X	X	|	L

L	H	L	X	X	L	X	|	H

L	H	L	X	X	H	X	|	L

L	H	H	X	X	X	L	|	H

L	H	H	X	X	X	H	|	L

See also:

Macrofunctions (by function)

Multiplexer Macrofunctions


74353 (Multiplexer)

Dual 4-Line-to-1-Line Data Selector/Multiplexer with Tri-State Inverting Outputs

Default Signal Levels:	GND--1GN, 2GN

VCC--1C0, 1C1, 1C2, 1C3, A, B, 2C0, 2C1, 2C2, 2C3

Function Prototype:

FUNCTION 74353 (b, a, 1gn, 1c[0..3], 2gn, 2c[0..3])

RETURNS (1yn, 2yn);

Inputs	|	Outputs

GN	B	A	C0	C1	C2	C3	|	YN

H	X	X	X	X	X	X	|	Z

L	L	L	L	X	X	X	|	H

L	L	L	H	X	X	X	|	L

L	L	H	X	L	X	X	|	H

L	L	H	X	H	X	X	|	L

L	H	L	X	X	L	X	|	H

L	H	L	X	X	H	X	|	L

L	H	H	X	X	X	L	|	H

L	H	H	X	X	X	H	|	L

See also:

Macrofunctions (by function)

Multiplexer Macrofunctions


74354 (Multiplexer)

8-Line-to-1-Line Data Selector/Multiplexer/Register with Tri-State Outputs

Default Signal Levels:	GND--GN1, GN2, SCN, DCN

VCC--G3, S0, S1, S2, D0, D1, D2, D3, D4, D5, D6, D7

Function Prototype:

FUNCTION 74354 (gn1, gn2, g3, s[2..0], scn, dcn, d[7..0])

RETURNS (y, wn);

Inputs	|	Outputs

GN1	GN2	G3	S2	S1	S0	SCN	DCN	D[7..0]	|	Y	WN

H	X	X	X	X	X	X	X	X	|	Z	Z

X	H	X	X	X	X	X	X	X	|	Z	Z

X	X	L	X	X	X	X	X	X	|	Z	Z

L	L	H	L	L	L	L	L	d[7..0]	|	d0	/d0

L	L	H	L	L	H	L	L	d[7..0]	|	d1	/d1

L	L	H	L	H	L	L	L	d[7..0]	|	d2	/d2

L	L	H	L	H	H	L	L	d[7..0]	|	d3	/d3

L	L	H	H	L	L	L	L	d[7..0]	|	d4	/d4

L	L	H	H	L	H	L	L	d[7..0]	|	d5	/d5

L	L	H	H	H	L	L	L	d[7..0]	|	d6	/d6

L	L	H	H	H	H	L	L	d[7..0]	|	d7	/d7

L	L	H	X	X	X	H	X	d[7..0]	|	d of the address

|	stored when SCN

|	went high

L	L	L	X	X	X	X	H	X	|	d stored when

|	DCN went high

See also:

Macrofunctions (by function)

Multiplexer Macrofunctions


74356 (Multiplexer)

8-Line-to-1-Line Data Selector/Multiplexer/Register with Tri-State Outputs

Default Signal Levels:	GND--GN1, GN2, SCN, CLK

VCC--G3, S0, S1, S2, D0, D1, D2, D3, D4, D5, D6, D7

Function Prototype:

FUNCTION 74356 (gn1, gn2, g3, s[2..0], scn, clk, d[7..0])

RETURNS (y, wn);

Inputs	|	Outputs

GN1	GN2	G3	S2	S1	S0	SCN	CLK	D	|	Y	WN

H	X	X	X	X	X	X	X	X	|	Z	Z

X	H	X	X	X	X	X	X	X	|	Z	Z

X	X	L	X	X	X	X	X	X	|	Z	Z

L	L	H	L	L	L	L	d[7..0]	|	d0	/d0

L	L	H	L	L	H	L	d[7..0]	|	d1	/d1

L	L	H	L	H	L	L	d[7..0]	|	d2	/d2

L	L	H	L	H	H	L	d[7..0]	|	d3	/d3

L	L	H	H	L	L	L	d[7..0]	|	d4	/d4

L	L	H	H	L	H	L	d[7..0]	|	d5	/d5

L	L	H	H	H	L	L	d[7..0]	|	d6	/d6

L	L	H	H	H	H	L	d[7..0]	|	d7	/d7

L	L	H	X	X	X	H	X	d[7..0]	|	d of the address

|	stored when SCN

|	went high

L	L	L	X	X	X	X	L	X	|	d stored on CLK’s

|	rising edge

See also:

Macrofunctions (by function)

Multiplexer Macrofunctions


74185 (Converter)

Binary-to-BCD Converter

Default Signal Levels:	GND--all input pins

Function Prototype:

FUNCTION 74185 (e, d, c, b, a, gn)

RETURNS (y[8..1]);

BCD	|	Inputs	|	Outputs

Words	|	|

|	E	D	C	B	A	GN	|	Y8	Y7	Y6	Y5	Y4	Y3	Y2	Y1

0-1	|	L	L	L	L	L	L	|	H	H	L	L	L	L	L	L

2-3	|	L	L	L	L	H	L	|	H	H	L	L	L	L	L	H

4-5	|	L	L	L	H	L	L	|	H	H	L	L	L	L	H	L

6-7	|	L	L	L	H	H	L	|	H	H	L	L	L	L	H	H

8-9	|	L	L	H	L	L	L	|	H	H	L	L	L	H	L	L

10-11	|	L	L	H	L	H	L	|	H	H	L	L	H	L	L	L

12-13	|	L	L	H	H	L	L	|	H	H	L	L	H	L	L	H

14-15	|	L	L	H	H	H	L	|	H	H	L	L	H	L	H	L

16-17	|	L	H	L	L	L	L	|	H	H	L	L	H	L	H	H

18-19	|	L	H	L	L	H	L	|	H	H	L	L	H	H	L	L

20-21	|	L	H	L	H	L	L	|	H	H	L	H	L	L	L	L

22-23	|	L	H	L	H	H	L	|	H	H	L	H	L	L	L	H

24-25	|	L	H	H	L	L	L	|	H	H	L	H	L	L	H	L

26-27	|	L	H	H	L	H	L	|	H	H	L	H	L	L	H	H

28-29	|	L	H	H	H	L	L	|	H	H	L	H	L	H	L	L

30-31	|	L	H	H	H	H	L	|	H	H	L	H	H	L	L	L

32-33	|	H	L	L	L	L	L	|	H	H	L	H	H	L	L	H

34-35	|	H	L	L	L	H	L	|	H	H	L	H	H	L	H	L

36-37	|	H	L	L	H	L	L	|	H	H	L	H	H	L	H	H

38-39	|	H	L	L	H	H	L	|	H	H	L	H	H	H	L	L

40-41	|	H	L	H	L	L	L	|	H	H	H	L	L	L	L	L

42-43	|	H	L	H	L	H	L	|	H	H	H	L	L	L	L	H

44-45	|	H	L	H	H	L	L	|	H	H	H	L	L	L	H	L

46-47	|	H	L	H	H	H	L	|	H	H	H	L	L	L	H	H

48-49	|	H	H	L	L	L	L	|	H	H	H	L	L	H	L	L

50-51	|	H	H	L	L	H	L	|	H	H	H	L	H	L	L	L

52-53	|	H	H	L	H	L	L	|	H	H	H	L	H	L	L	H

54-55	|	H	H	L	H	H	L	|	H	H	H	L	H	L	H	L

56-57	|	H	H	H	L	L	L	|	H	H	H	L	H	L	H	H

58-59	|	H	H	H	L	H	L	|	H	H	H	L	H	H	L	L

60-61	|	H	H	H	H	L	L	|	H	H	H	H	L	L	L	L

62-63	|	H	H	H	H	H	L	|	H	H	H	H	L	L	L	H

Any	|	X	X	X	X	X	H	|	H	H	H	H	H	H	H	H

See also:

Converter Macrofunctions

Macrofunctions (by function)


74190 (Counter)

4-Bit Decade Up/Down Counter with Asynchronous Load

Default Signal Levels:	GND--A, B, C, D, GN, CLK

VCC--LDN, DNUP

Function Prototype:

FUNCTION 74190 (clk, gn, ldn, dnup, d, c, b, a)

RETURNS (qd, qc, qb, qa, mxmn, rcon);

Inputs	|	Outputs

CLK	GN	LDN	DNUP	D	C	B	A	|	QD	QC	QB	QA	|	MXMN	|	RCON  Note (1)

X	X	L	X	d	c	b	a	|	d	c	b	a	|	X	|	X

X	L	H	L	|	H	L	L	H	|	H	|	L

X	L	H	H	|	L	L	L	L	|	H	|	L

L	H	L	|	Count Up	|	L	|	H

L	H	H	|	Count Down	|	L	|	H

H	H	X	|	Hold Count	|	L	|	H

See also:

Counter Macrofunctions

Macrofunctions (by function)


74191 (Counter)

4-Bit Binary Up/Down Counter with Asynchronous Load Note

Default Signal Levels:	GND--A, B, C, D, GN, CLK

VCC--LDN, DNUP

Function Prototype:

FUNCTION 74191 (clk, gn, ldn, dnup, d, c, b, a)

RETURNS (qd, qc, qb, qa, mxmn, rcon);

Inputs	|	Outputs

CLK	GN	LDN	DNUP	D	C	B	A	|	QD	QC	QB	QA	|	MXMN	|	RCON  Note (1)

X	X	L	X	d	c	b	a	|	d	c	b	a	|	X	|	X

L	H	H	L	L	L	L	|	|	H	|	L

L	H	L	H	H	H	H	|	|	H	|	L

L	H	L	|	Count Up	|	L	|	H

L	H	H	|	Count Down	|	L	|	H

H	H	X	|	Hold Count	|	L	|	H

See also:

Counter Macrofunctions

Macrofunctions (by function)


Note 1
Note (1)

Ripple Clock Out signal (RCON)


74192 (Counter)

4-Bit Decade Up/Down Counter with Asynchronous Clear

Default Signal Levels:	GND--A, B, C, D, CLR

VCC--LDN, DN, UP

Function Prototype:

FUNCTION 74192 (clr, up, dn, ldn, d, c, b, a)

RETURNS (qd, qc, qb, qa, con, bon);

Inputs	|	Outputs	|	Notes

CLR	UP	DN	LDN	D	C	B	A	|	QD	QC	QB	QA	|	CON	|	BON	|

H	X	X	X	X	X	X	X	|	L	L	L	L	|	X	|	X	|

L	X	X	L	d	c	b	a	|	d	c	b	a	|	X	|	X	|

L	H	H	X	X	X	X	|	Count Up	|	H	|	H	|

L	H	H	X	X	X	X	|	Count Down	|	H	|	H	|

*L	H	H	X	X	X	X	|	H	L	L	H	|	L	|	H	|	*

*L	H	H	X	X	X	X	|	L	L	L	L	|	H	|	L	|	*

L	H	H	H	X	X	X	X	|	Hold Count	|	X	|	X	|

L	H	X	X	X	X	|	Illegal	|	X	|	X	|

Notes:

*	These conditions represent roll-over counter values. Previous values are not shown. Loading a value greater than 10 can result in unpredictable counter behavior.

See also:

Counter Macrofunctions

Macrofunctions (by function)


74193 (Counter)

4-Bit Binary Up/Down Counter with Asynchronous Clear

Default Signal Levels:	GND--A, B, C, D, CLR

VCC--LDN, DN, UP

Function Prototype:

FUNCTION 74193 (clr, up, dn, ldn, d, c, b, a)

RETURNS (qd, qc, qb, qa, con, bon);

Inputs	|	Outputs	|	Notes

CLR	UP	DN	LDN	D	C	B	A	|	QD	QC	QB	QA	|	CON	|	BON	|

H	X	X	X	X	X	X	X	|	L	L	L	L	|	X	|	X	|

L	X	X	L	d	c	b	a	|	d	c	b	a	|	X	|	X	|

L	H	H	X	X	X	X	|	Count Up	|	H	|	H	|

L	H	H	X	X	X	X	|	Count Down	|	H	|	H	|

*L	H	H	X	X	X	X	|	H	H	H	H	|	L	|	H	|	*

*L	H	H	X	X	X	X	|	L	L	L	L	|	H	|	L	|	*

L	H	H	H	X	X	X	X	|	Hold Count	|	X	|	X	|

L	H	X	X	X	X	|	Illegal	|	X	|	X	|

Notes:

*	These conditions represent roll-over counter values. Previous values are not shown.

See also:

Counter Macrofunctions

Macrofunctions (by function)


74194 (Shift Register)

4-Bit Bidirectional Shift Register with Parallel Load

Default Signal Levels:	GND--SLSI, SRSI, A, B, C, D, S0, S1, CLK

VCC--CLRN

Function Prototype:

FUNCTION 74194 (clrn, s1, s0, clk, slsi, srsi, d, c, b, a)

RETURNS (qd, qc, qb, qa);

Inputs	|	Outputs

|	Mode	|	|	Serial	|	Parallel	|

CLRN	|	S1	S0	|	CLK	|	SLSI	SRSI	|	A	B	C	D	|	QA	QB	QC	QD

L	|	X	X	|	X	|	X	X	|	X	X	X	X	|	L	L	L	L

H	|	X	X	|	L	|	X	X	|	X	X	X	X	|	QAo	QBo	QCo	QDo

H	|	H	H	|	|	X	X	|	a	b	c	d	|	a	b	c	d

H	|	L	H	|	|	X	H	|	X	X	X	X	|	H	QAn	QBn	QCn

H	|	L	H	|	|	X	L	|	X	X	X	X	|	L	QAn	QBn	QCn

H	|	H	L	|	|	H	X	|	X	X	X	X	|	QBn	QCn	QDn	H

H	|	H	L	|	|	L	X	|	X	X	X	X	|	QBn	QCn	QDn	L

H	|	L	L	|	|	X	X	|	X	X	X	X	|	QAo	QBo	QCo	QDo

See also:

Macrofunctions (by function)

Shift Register Macrofunctions


74195 (Shift Register)

4-Bit Parallel-Access Shift Register

Default Signal Levels:	GND--J, D0, D1, D2, D3, CLK

VCC--CLRN, KN, ST/LDN

Function Prototype:

FUNCTION 74195 (clrn, st/ldn, clk, j, kn, d[0..3])

RETURNS (q[0..3], q3n);

This macrofunction is not directly supported by VHDL because it contains one or more port names with a slash (/) or dash (-). These characters are illegal in VHDL port names. However, you can use this macrofunction in your project by incorporating it into a lower-level design file, then inserting an instance of the lower-level file into your VHDL Design File. See Using a MAX+PLUS II Primitive or Macrofunction for more information.

Inputs	|	Outputs

CLRN	ST/LDN	CLK	J	KN	D0	D1	D2	D3	|	Q0	Q1	Q2	Q3	Q3N

L	X	X	X	X	X	X	X	X	|	L	L	L	L	H

H	L	X	X	a	b	c	d	|	a	b	c	d	/d

H	H	L	X	X	X	X	X	X	|	Q0o	Q1o	Q2o	Q3o	/Q3o

H	H	L	H	X	X	X	X	|	Q0o	Q0n	Q1n	Q2n	/Q2n

H	H	L	L	X	X	X	X	|	L	Q0n	Q1n	Q2n	/Q2n

H	H	H	H	X	X	X	X	|	H	Q0n	Q1n	Q2n	/Q2n

H	H	H	L	X	X	X	X	|	/Q0n	Q0n	Q1n	Q2n	/Q2n

See also:

Macrofunctions (by function)

Shift Register Macrofunctions


74196 (Counter)

Presettable Decade Counter

Default Signal Levels:	VCC--all input pins

Function Prototype:

FUNCTION 74196 (clrn, ldn, clk1, clk2, d, c, b, a)

RETURNS (qd, qc, qb, qa);

Inputs	|	Outputs

CLRN	LDN	CLK	D	C	B	A	|	QD	QC	QB	QA

L	H	X	x	x	x	x	|	L	L	L	L

H	L	X	d	c	b	a	|	d	c	b	a

L	L	X	x	x	x	x	|	Illegal condition

H	H	|	Count

Possible Counting Configurations:

Decade: QA Connected to CLK2	|	Bi-Quinary: QD Connected to CLK1

Count	|	QD	QC	QB	QA	|	Count	|	QD	QC	QB	QA

0	|	L	L	L	L	|	0	|	L	L	L	L

1	|	L	L	L	H	|	1	|	L	L	L	H

2	|	L	L	H	L	|	2	|	L	L	H	L

3	|	L	L	H	H	|	3	|	L	L	H	H

4	|	L	H	L	L	|	4	|	L	H	L	L

5	|	L	H	L	H	|	5	|	H	L	L	L

6	|	L	H	H	L	|	6	|	H	L	L	H

7	|	L	H	H	H	|	7	|	H	L	H	L

8	|	H	L	L	L	|	8	|	H	L	H	H

9	|	H	L	L	H	|	9	|	H	H	L	L

See also:

Counter Macrofunctions

Macrofunctions (by function)


74197 (Counter)

Presettable Binary Counter

Default Signal Levels:	VCC--all input pins

Function Prototype:

FUNCTION 74197 (clrn, ldn, clk1, clk2, d, c, b, a)

RETURNS (qd, qc, qb, qa);

Inputs	|	Outputs

CLRN	LDN	CLK	D	C	B	A	|	QD	QC	QB	QA

L	H	X	x	x	x	x	|	L	L	L	L

H	L	X	d	c	b	a	|	d	c	b	a

L	L	X	x	x	x	x	|	Illegal condition

H	H	|	Count

Possible Counting Configurations:

Binary: QA Connected to CLK2

Count	|	QD	QC	QB	QA*

0	|	L	L	L	L

1	|	L	L	L	H

2	|	L	L	H	L

3	|	L	L	H	H

4	|	L	H	L	L

5	|	L	H	L	H

6	|	L	H	H	L

7	|	L	H	H	H

8	|	H	L	L	L

9	|	H	L	L	H

10	|	H	L	H	L

11	|	H	L	H	H

12	|	H	H	L	L

13	|	H	H	L	H

14	|	H	H	H	L

15	|	H	H	H	H

*	QA is connected to the CLK2 input.

See also:

Counter Macrofunctions

Macrofunctions (by function)


74198 (Shift Register)

8-Bit Bidirectional Shift Register

Default Signal Levels:	GND--SLSI, SRSI, A, B, C, D, E, F, G, H, S0, S1, CLK

VCC--CLRN

Function Prototype:

FUNCTION 74198 (clrn, s1, s0, clk, slsi, srsi, a, b, c, d, e, f, g, h)

RETURNS (qa, qb, qc, qd, qe, qf, qg, qh);

Inputs	|	Outputs

|	Mode	|	|	Serial	|	Parallel	|	|	|

CLRN	|	S1	S0	|	CLK	|	SLSI	SRSI	|	A ..H	|	QA	|	QB..QG	|	QH

L	|	X	X	|	X	|	X	X	|	X	|	L	|	L..L	|	L

H	|	X	X	|	L	|	X	X	|	X	|	QAo	|	QBo..QGo	|	QHo

H	|	H	H	|	|	X	X	|	a..h	|	a	|	b..g	|	h

H	|	L	H	|	|	X	H	|	X	|	H	|	QAn..QFn	|	QGn

H	|	L	H	|	|	X	L	|	X	|	L	|	QAn..QFn	|	QGn

H	|	H	L	|	|	H	X	|	X	|	QBn	|	QCn..QHn	|	H

H	|	H	L	|	|	L	X	|	X	|	QBn	|	QCn..QHn	|	L

H	|	L	L	|	|	X	X	|	X	|	QAo	|	QBo..QGo	|	QHo

See also:

Macrofunctions (by function)

Shift Register Macrofunctions


74199 (Shift Register)

8-Bit Parallel-Access Shift Register

Default Signal Levels:	GND--J, D0, D1, D2, D3, D4, D5, D6, D7, CLK, CLKIH

VCC--CLRN, KN, ST/LDN

Function Prototype:

FUNCTION 74199 (clrn, st/ldn, clkih, clk, j, kn, d[0..7])

RETURNS (q[0..7]);

This macrofunction is not directly supported by VHDL because it contains one or more port names with a slash (/) or dash (-). These characters are illegal in VHDL port names. However, you can use this macrofunction in your project by incorporating it into a lower-level design file, then inserting an instance of the lower-level file into your VHDL Design File. See Using a MAX+PLUS II Primitive or Macrofunction for more information.

Inputs	|	Outputs

CLRN	ST/LDN	CLKIH	CLK	J	KN	D[0..7]	|	Q0	|	Q1..Q6	|	Q7

L	X	X	X	X	X	X	|	L	|	L	|	L

H	X	H	X	X	X	X	|	Q0o	|	Q1o..Q6o	|	Q7o

H	L	L	X	X	a..h	|	a	|	b..g	|	h

H	H	L	L	X	X	X	|	Q0o	|	Q1o..Q6o	|	Q7o

H	H	L	L	H	X	|	Q0o	|	Q1o..Q6o	|	Q7o

H	H	L	L	L	X	|	L	|	Q0n..Q5n	|	Q6n

H	H	L	H	H	X	|	H	|	Q0n..Q5n	|	Q6n

H	H	L	H	L	X	|	/Q0o	|	Q0n..Q5n	|	Q6n

See also:

Macrofunctions (by function)

Shift Register Macrofunctions


74240 (Buffer)

Octal Inverting Tri-State Buffer

Default Signal Levels:	GND--1GN, 2GN

VCC--1A1, 1A2, 1A3, 1A4, 2A1, 2A2, 2A3, 2A4

Function Prototype:

FUNCTION 74240 (1gn, 1a[1..4], 2gn, 2a[1..4])

RETURNS (1y[1..4], 2y[1..4]);

Inputs	|	Outputs

GN	A	|	Y

H	X	|	Z

L	L	|	H

L	H	|	L

See also:

Buffer Macrofunctions

Macrofunctions (by function)


74241 (Buffer)

Octal Tri-State Buffer

Default Signal Levels:	GND--1GN

VCC--1A1, 1A2, 1A3, 1A4, 2G, 2A1, 2A2, 2A3, 2A4

Function Prototype:

FUNCTION 74241 (1gn, 1a[1..4], 2g, 2a[1..4])

RETURNS (1y[1..4], 2y[1..4]);

Inputs	|	Outputs

1GN(/2G)	A	|	Y

H	X	|	Z

L	L	|	L

L	H	|	H

See also:

Buffer Macrofunctions

Macrofunctions (by function)


74244 (Buffer)

Octal Tri-State Buffer

Default Signal Levels:	GND--1GN, 2GN

VCC--1A1, 1A2, 1A3, 1A4, 2A1, 2A2, 2A3, 2A4

Function Prototype:

FUNCTION 74244 (1gn, 1a[1..4], 2gn, 2a[1..4])

RETURNS (1y[1..4], 2y[1..4]);

Inputs	|	Outputs

GN	A	|	Y

H	X	|	Z

L	L	|	L

L	H	|	H

See also:

Buffer Macrofunctions

Macrofunctions (by function)


74246 (Decoder)

BCD-to-7-Segment Decoder

Default Signal Levels:	VCC--all input pins

Function Prototype:

FUNCTION 74246 (ltn, rbin, bin, d, c, b, a)

RETURNS (oa, ob, oc, od, oe, ‘of’, og, rbon);

Inputs	|	Outputs

LTN	RBIN	BIN	D	C	B	A	|	OA	OB	OC	OD	OE	OF	OG	RBON

H	H	H	L	L	L	L	|	On	On	On	On	On	On	Off	H

H	L	H	L	L	L	L	|	Off	Off	Off	Off	Off	Off	Off	L

H	X	H	L	L	L	H	|	Off	On	On	Off	Off	Off	Off	H

H	X	H	L	L	H	L	|	On	On	Off	On	On	Off	On	H

H	X	H	L	L	H	H	|	On	On	On	On	Off	Off	On	H

H	X	H	L	H	L	L	|	Off	On	On	Off	Off	On	On	H

H	X	H	L	H	L	H	|	On	Off	On	On	Off	On	On	H

H	X	H	L	H	H	L	|	On	Off	On	On	On	On	On	H

H	X	H	L	H	H	H	|	On	On	On	Off	Off	Off	Off	H

H	X	H	H	L	L	L	|	On	On	On	On	On	On	On	H

H	X	H	H	L	L	H	|	On	On	On	On	Off	On	On	H

H	X	H	H	L	H	L	|	Off	Off	Off	On	On	Off	On	H

H	X	H	H	L	H	H	|	Off	Off	On	On	Off	Off	On	H

H	X	H	H	H	L	L	|	Off	On	Off	Off	Off	On	On	H

H	X	H	H	H	L	H	|	On	Off	Off	On	Off	On	On	H

H	X	H	H	H	H	L	|	Off	Off	Off	On	On	On	On	H

H	X	H	H	H	H	H	|	Off	Off	Off	Off	Off	Off	Off	H

L	X	H	X	X	X	X	|	On	On	On	On	On	On	On	H

H	X	L	X	X	X	X	|	Off	Off	Off	Off	Off	Off	Off	H

See also:

Decoder Macrofunctions

Macrofunctions (by function)


74247 (Decoder)

BCD-to-7-Segment Decoder

Default Signal Levels:	VCC--all input pins

Function Prototype:

FUNCTION 74247 (ltn, rbin, bin, d, c, b, a)

RETURNS (oa, ob, oc, od, oe, ‘of’, og, rbon);

Inputs	|	Outputs

LTN	RBIN	BIN	D	C	B	A	|	OA	OB	OC	OD	OE	OF	OG	RBON

H	H	H	L	L	L	L	|	On	On	On	On	On	On	Off	H

H	L	H	L	L	L	L	|	Off	Off	Off	Off	Off	Off	Off	L

H	X	H	L	L	L	H	|	Off	On	On	Off	Off	Off	Off	H

H	X	H	L	L	H	L	|	On	On	Off	On	On	Off	On	H

H	X	H	L	L	H	H	|	On	On	On	On	Off	Off	On	H

H	X	H	L	H	L	L	|	Off	On	On	Off	Off	On	On	H

H	X	H	L	H	L	H	|	On	Off	On	On	Off	On	On	H

H	X	H	L	H	H	L	|	On	Off	On	On	On	On	On	H

H	X	H	L	H	H	H	|	On	On	On	Off	Off	Off	Off	H

H	X	H	H	L	L	L	|	On	On	On	On	On	On	On	H

H	X	H	H	L	L	H	|	On	On	On	On	Off	On	On	H

H	X	H	H	L	H	L	|	Off	Off	Off	On	On	Off	On	H

H	X	H	H	L	H	H	|	Off	Off	On	On	Off	Off	On	H

H	X	H	H	H	L	L	|	Off	On	Off	Off	Off	On	On	H

H	X	H	H	H	L	H	|	On	Off	Off	On	Off	On	On	H

H	X	H	H	H	H	L	|	Off	Off	Off	On	On	On	On	H

H	X	H	H	H	H	H	|	Off	Off	Off	Off	Off	Off	Off	H

L	X	H	X	X	X	X	|	On	On	On	On	On	On	On	H

H	X	L	X	X	X	X	|	Off	Off	Off	Off	Off	Off	Off	H

See also:

Decoder Macrofunctions

Macrofunctions (by function)


74248 (Decoder)

BCD-to-7-Segment Decoder

Default Signal Levels:	VCC--all input pins

Function Prototype:

FUNCTION 74248 (ltn, rbin, bin, d, c, b, a)

RETURNS (oa, ob, oc, od, oe, ‘of’, og, rbon);

Inputs	|	Outputs

LTN	RBIN	BIN	D	C	B	A	|	OA	OB	OC	OD	OE	OF	OG	RBON

H	H	H	L	L	L	L	|	H	H	H	H	H	H	L	H

H	L	H	L	L	L	L	|	L	L	L	L	L	L	L	L

H	X	H	L	L	L	H	|	L	H	H	L	L	L	L	H

H	X	H	L	L	H	L	|	H	H	L	H	H	L	H	H

H	X	H	L	L	H	H	|	H	H	H	H	L	L	H	H

H	X	H	L	H	L	L	|	L	H	H	L	L	H	H	H

H	X	H	L	H	L	H	|	H	L	H	H	L	H	H	H

H	X	H	L	H	H	L	|	H	L	H	H	H	H	H	H

H	X	H	L	H	H	H	|	H	H	H	L	L	L	L	H

H	X	H	H	L	L	L	|	H	H	H	H	H	H	H	H

H	X	H	H	L	L	H	|	H	H	H	H	L	H	H	H

H	X	H	H	L	H	L	|	L	L	L	H	H	L	H	H

H	X	H	H	L	H	H	|	L	L	H	H	L	L	H	H

H	X	H	H	H	L	L	|	L	H	L	L	L	H	H	H

H	X	H	H	H	L	H	|	H	L	L	H	L	H	H	H

H	X	H	H	H	H	L	|	L	L	L	H	H	H	H	H

H	X	H	H	H	H	H	|	L	L	L	L	L	L	L	H

L	X	H	X	X	X	X	|	H	H	H	H	H	H	H	H

H	X	L	X	X	X	X	|	L	L	L	L	L	L	L	H

See also:

Decoder Macrofunctions

Macrofunctions (by function)


74251 (Multiplexer)

8-Line-to-1-Line Data Selector with Tri-State Outputs

Default Signal Levels:	VCC--all input pins

Function Prototype:

FUNCTION 74251 (c, b, a, d[7..0], gn)

RETURNS (y, wn);

Inputs	|	Outputs

GN	C	B	A	|	Y	WN

H	X	X	X	|	Z	Z

L	L	L	L	|	D0	/D0

L	L	L	H	|	D1	/D1

L	L	H	L	|	D2	/D2

L	L	H	H	|	D3	/D3

L	H	L	L	|	D4	/D4

L	H	L	H	|	D5	/D5

L	H	H	L	|	D6	/D6

L	H	H	H	|	D7	/D7

See also:

Macrofunctions (by function)

Multiplexer Macrofunctions


74253 (Multiplexer)

Dual 4-Line-to-1-Line Data Selector with Tri-State Outputs

Default Signal Levels:	VCC--all input pins

Function Prototype:

FUNCTION 74253 (b, a, 1gn, 1c[0..3], 2gn, 2c[0..3])

RETURNS (1y, 2y);

Inputs	|	Outputs

GN	B	A	|	Y

H	X	X	|	Z

L	L	L	|	C0

L	L	H	|	C1

L	H	L	|	C2

L	H	H	|	C3

See also:

Macrofunctions (by function)

Multiplexer Macrofunctions


74257 (Multiplexer)

Quad 2-Line-to-1-Line Multiplexer with Tri-State Outputs

Default Signal Levels:	GND--GN

VCC--A1, B1, A2, B2, A3, B3, A4, B4, SEL

Function Prototype:

FUNCTION 74257 (gn, sel, a[4..1], b[4..1])

RETURNS (y[4..1]);

Inputs	|	Outputs

GN	SEL	A	B	|	Y

H	X	X	X	|	Z

L	L	L	X	|	L

L	L	H	X	|	H

L	H	X	L	|	L

L	H	X	H	|	H

See also:

Macrofunctions (by function)

Multiplexer Macrofunctions


74258 (Multiplexer)

Quad 2-Line-to-1-Line Multiplexer with Inverting Tri-State Outputs

Default Signal Levels:	GND--GN

VCC--A1, B1, A2, B2, A3, B3, A4, B4, SEL

Function Prototype:

FUNCTION 74258 (gn, sel, a[4..1], b[4..1])

RETURNS (yn[4..1]);

Inputs	|	Outputs

GN	SEL	A	B	|	YN

H	X	X	X	|	Z

L	L	L	X	|	H

L	L	H	X	|	L

L	H	X	L	|	H

L	H	X	H	|	L

See also:

Macrofunctions (by function)

Multiplexer Macrofunctions


74172 (Register)

Multi-Port Register File with Tri-State Outputs

Default Signal Levels:	GND--1GRN, 2GRN, 1GWN, CLK

VCC--1R0, 1R1, 1R2, 2W/R0, 2W/R1, 2W/R2, 1W0, 1W1, 1W2, 1DA, 1DB, 2DA, 2DB, 2GWN

Function Prototype:

FUNCTION 74172 (1grn, 2grn, 1r0, 1r1, 1r2, 2w/r0, 2w/r1, 2w/r2, 1w0, 1w1, 1w2, 1da, 1db, 2da, 2db, 1gwn, 2gwn, clk)

RETURNS (1qa, 1qb, 2qa, 2qb);

This macrofunction is not directly supported by VHDL because it contains one or more port names with a slash (/) or dash (-). These characters are illegal in VHDL port names. However, you can use this macrofunction in your project by incorporating it into a lower-level design file, then inserting an instance of the lower-level file into your VHDL Design File. See Using a MAX+PLUS II Primitive or Macrofunction for more information.

Function	|	Sec 1	|	Sec 2	|	Description

Write Address	|	1WO	|	2W/RO	|	Selects one of the eight 2-bit data words.

|	1W1	|	2W/R1	|

|	1W2	|	2W/R2	|

Write Enable	|	1GWN	|	2GWN	|	When low, data is written into the

|	|	|	location selected by the write address on

|	|	|	the rising edge of the clock.

Data Inputs	|	1DA	|	2DA	|	Consists of the 2-bit word written into

|	1DB	|	2DB	|	the write address. If both write addresses

|	|	|	are the same and active, the low data will

|	|	|	predominate.

Read Address	|	1R0	|	2W/2R0	|	Selects one of the eight 2-bit data words.

|	1R1	|	2W/2R1	|

|	1R2	|	2W/2R2	|

Read Enable	|	1GRN	|	2GRN	|	When low, the outputs reflect the data

|	|	|	stored in the read address. When high, the

|	|	|	outputs are in the high-impedance state.

Data Outputs	|	1QA	|	2QA	|	Consists of the outputs.

|	1QB	|	2QB	|

Clock	|	CLK	|	CLK	|	The clock is common to both sections.

See also:

Macrofunctions (by function)

Register Macrofunctions


74173 (Register)

4-Bit D-Type Register

Default Signal Levels:	GND--all input pins

Function Prototype:

FUNCTION 74173 (clr, clk, mn, nn, g1n, g2n, 1d, 2d, 3d, 4d)

RETURNS (1q, 2q, 3q, 4q);

Inputs	|	Outputs

|	Data Enable	|	|

CLR	CLK	|	G1N	G2N	|	D	|	Q

H	X	|	X	X	|	X	|	L

L	L	|	X	X	|	X	|	Qo

L	|	H	X	|	X	|	Qo

L	|	X	H	|	X	|	Qo

L	|	L	L	|	L	|	L

L	|	L	L	|	H	|	H

When either MN or NN is high, the OE output is low; however, sequential operation of the flipflop is not affected.

See also:

Macrofunctions (by function)

Register Macrofunctions


74174 (Register)

Hex D-Type Flipflop with Common Clear

Default Signal Levels: 	GND--1D, 2D, 3D, 4D, 5D, 6D, CLK

VCC--CLRN

Function Prototype:

FUNCTION 74174 (clrn, clk, 1d, 2d, 3d, 4d, 5d, 6d)

RETURNS (1q, 2q, 3q, 4q, 5q, 6q);

Inputs	|	Outputs

CLRN	CLK	D	|	Q

L	X	X	|	L

H	L	|	L

H	H	|	H

H	L	X	|	Qo

See also:

Macrofunctions (by function)

Register Macrofunctions


74175 (Register)

Quad D-Type Flipflop with Common Clock and Clear

Default Signal Levels: 	GND--1D, 2D, 3D, 4D, CLK

VCC--CLRN

Function Prototype:

FUNCTION 74175 (clrn, clk, 1d, 2d, 3d, 4d)

RETURNS (1q, 1qn, 2q, 2qn, 3q, 3qn, 4q, 4qn);

Inputs	|	Outputs

CLRN	CLK	D	|	Q	QN

L	X	X	|	L	H

H	H	|	H	L

H	L	|	L	H

H	L	X	|	Qo	/Qo

See also:

Macrofunctions (by function)

Register Macrofunctions


74176 (Counter)

Presettable Decade Counter

Default Signal Levels:	VCC--all input pins

Function Prototype:

FUNCTION 74176 (clrn, ldn, clk1, clk2, d, c, b, a)

RETURNS (qd, qc, qb, qa);

Inputs	|	Outputs

CLRN	LDN	CLK	D	C	B	A	|	QD	QC	QB	QA

L	H	X	x	x	x	x	|	L	L	L	L

H	L	X	d	c	b	a	|	d	c	b	a

L	L	X	x	x	x	x	|	Illegal condition

H	H	|	Count

Possible Counting Configurations:

Decade: QA Connected to CLK2	|	Bi-Quinary: QD Connected to CLK1

Count	QD	QC	QB	QA	|	Count	QD	QC	QB	QA

0	L	L	L	L	|	0	L	L	L	L

1	L	L	L	H	|	1	L	L	L	H

2	L	L	H	L	|	2	L	L	H	L

3	L	L	H	H	|	3	L	L	H	H

4	L	H	L	L	|	4	L	H	L	L

5	L	H	L	H	|	5	H	L	L	L

6	L	H	H	L	|	6	H	L	L	H

7	L	H	H	H	|	7	H	L	H	L

8	H	L	L	L	|	8	H	L	H	H

9	H	L	L	H	|	9	H	H	L	L

See also:

Counter Macrofunctions

Macrofunctions (by function)


74177 (Counter)

Presettable Binary Counter

Default Signal Levels: 	VCC--all input pins

Function Prototype:

FUNCTION 74177 (clrn, ldn, clk1, clk2, d, c, b, a)

RETURNS (qd, qc, qb, qa);

Inputs	|	Outputs

CLRN	LDN	CLK	D	C	B	A	|	QD	QC	QB	QA

L	H	X	x	x	x	x	|	L	L	L	L

H	L	X	d	c	b	a	|	d	c	b	a

L	L	X	x	x	x	x	|	Illegal condition

H	H	|	Count

Possible Counting Configurations:

Binary: QA Connected to CLK2

Count	QD	QC	QB	QA*

0	L	L	L	L

1	L	L	L	H

2	L	L	H	L

3	L	L	H	H

4	L	H	L	L

5	L	H	L	H

6	L	H	H	L

7	L	H	H	H

8	H	L	L	L

9	H	L	L	H

10	H	L	H	L

11	H	L	H	H

12	H	H	L	L

13	H	H	L	H

14	H	H	H	L

15	H	H	H	H

*	QA is connected to the CLK2 input.

See also:

Counter Macrofunctions

Macrofunctions (by function)


74178 (Shift Register)

4-Bit Shift Register

Default Signal Levels: 	GND--A, B, C, D, LD, SER

VCC--ST, CLK

Function Prototype:

FUNCTION 74178 (st, ld, ser, clk, a, b, c, d)

RETURNS (qa, qb, qc, qd);

Inputs	|	Outputs

|	Parallel	|

ST	LD	SER	CLK	|	A	B	C	D	|	QA	QB	QC	QD

X	X	X	H	|	X	X	X	X	|	QAo	QBo	QCo	QDo

L	L	X	|	X	X	X	X	|	QAo	QBo	QCo	QDo

L	H	X	|	a	b	c	d	|	a	b	c	d

H	X	H	|	X	X	X	X	|	H	QAn	QBn	QCn

H	X	L	|	X	X	X	X	|	L	QAn	QBn	QCn

See also:

Macrofunctions (by function)

Shift Register Macrofunctions


74179 (Shift Register)

4-Bit Shift Register with Clear

Default Signal Levels: 	GND--A, B, C, D, LD, SER

VCC--ST, CLRN, CLK

Function Prototype:

FUNCTION 74179 (clrn, st, ld, clk, ser, a, b, c, d)

RETURNS (qa, qb, qc, qd, qdn);

Inputs	|	Outputs

|	Parallel	|

CLRN	ST	LD	CLK	SER	|	A	B	C	D	|	QA	QB	QC	QD	QDN

L	X	X	X	X	|	X	X	X	X	|	L	L	L	L	H

H	X	X	H	X	|	X	X	X	X	|	QAo	QBo	QCo	QDo	/QDo

H	L	L	X	|	X	X	X	X	|	QAo	QBo	QCo	QDo	/QDo

H	L	H	X	|	a	b	c	d	|	a	b	c	d	/d

H	H	X	H	|	X	X	X	X	|	H	QAn	QBn	QCn	/QCn

H	H	X	L	|	X	X	X	X	|	L	QAn	QBn	QCn	/QCn

See also:

Macrofunctions (by function)

Shift Register Macrofunctions


74180 (Parity Generator/Checker)

9-Bit Odd/Even Parity Generator/Checker

Default Signal Levels: 	GND--all input pins

Function Prototype:

FUNCTION 74180 (a, b, c, d, e, f, g, h, evni, oddi)

RETURNS (evns, odds);

Inputs	|	Outputs

# of H’s at 	|

A through H	EVNI	ODDI	|	Σ EVNS	Σ ODDS

Even	H	L	|	H	L

Odd	H	L	|	L	H

Even	L	H	|	L	H

Odd	L	H	|	H	L

X	H	H	|	L	L

X	L	L	|	H	H

See also:

Macrofunctions (by function)

Parity Generator/Checker Macrofunctions


74181 (Arithmetic Logic Unit)

Arithmetic Logic Unit

Default Signal Levels: 	GND--all input pins

Function Prototype:

FUNCTION 74181 (s[3..0], m, cn, a3n, a2n, a1n, a0n, b3n, b2n, b1n, b0n)

RETURNS (gn, pn, f3n, f2n, f1n, f0n, aeqb, cn4);

Selection	|	Active Low Data

|	M = H	|	M = L; Arithmetic Operations

|	Logic	|	Cn = L 	|	Cn = H

S3	S2	S1	S0	|	Functions	|	(No Carry)	|	(With Carry)

L	L	L	L	|	F = /A	|	F = A minus 1	|	F = A

L	L	L	H	|	F = /(AB)	|	F = AB minus 1	|	F = AB

L	L	H	L	|	F = /A + B 	|	F = A(/B) minus 1	|	F = A(/B)

L	L	H	H	|	F = 1	|	F = minus 1 (2s Comp)	|	F = ZERO

L	H	L	L	|	F = /(A + B)	|	F = A plus ( A + /B)	|	F = A plus ( A + /B) plus 1

L	H	L	H	|	F = /B	|	F = AB plus ( A + /B)	|	F = AB plus ( A + /B) plus 1

L	H	H	L	|	F = /(A $ B)	|	F = A minus B minus 1	|	F = A minus B

L	H	H	H	|	F = A + /B	|	F = A + /B	|	F = (A + /B) plus 1

H	L	L	L	|	F = (/A)B	|	F = A plus ( A + B )	|	F = A plus ( A + B ) plus 1

H	L	L	H	|	F = A $ B	|	F = A plus B	|	F = A plus B plus 1

H	L	H	L	|	F = B	|	F = A(/B) plus ( A + B )	|	F = A(/B) plus ( A + B ) plus 1

H	L	H	H	|	F = A + B	|	F = ( A + B )	|	F = ( A + B ) plus 1

H	H	L	L	|	F = 0 	|	F = A plus A*	|	F = A plus A plus 1

H	H	L	H	|	F = A(/B)	|	F = AB plus A 	|	F = AB plus A plus 1

H	H	H	L	|	F = AB	|	F = A(/B) plus A	|	F = A(/B) plus A plus 1

H	H	H	H	|	F = A 	|	F =  A	|	F = A plus 1

*	Each bit is shifted to the next more significant position

74181 Function Table (2):

Selection	|	Active High Data

|	M = H	|	M = L; Arithmetic Operations

|	Logic	|	/Cn = H	|	/Cn = L

S3	S2	S1	S0	|	Functions	|	(No Carry)	|	(With Carry)

L	L	L	L	|	F = /A	|	F = A	|	F = A plus 1

L	L	L	H	|	F = /(A + B)	|	F = A + B	|	F = ( A + B ) plus 1

L	L	H	L	|	F = (/A)B	|	F = A + /B	|	F = ( A +  /B) plus 1

L	L	H	H	|	F = 0	|	F = minus 1 (2s Comp)	|	F = ZERO

L	H	L	L	|	F = /(AB)	|	F = A plus A(/B)	|	F = A plus A(/B) plus 1

L	H	L	H	|	F = /B	|	F = ( A + B ) plus A(/B)	|	F = ( A + B ) plus A(/B) plus 1

L	H	H	L	|	F = A $ B	|	F = A minus B minus 1	|	F = A minus B

L	H	H	H	|	F = A(/B)	|	F = A(/B) minus 1	|	F = A(/B)

H	L	L	L	|	F = /A+ B 	|	F = A plus AB	|	F = A plus AB plus 1

H	L	L	H	|	F = /(A $ B)	|	F = A plus B	|	F = A plus B plus 1

H	L	H	L	|	F = B	|	F = ( A + /B ) plus AB	|	F = ( A +  /B) plus AB plus 1

H	L	H	H	|	F = AB	|	F = AB minus 1	|	F = AB

H	H	L	L	|	F = 1 	|	F = A plus A*	|	F = A plus A plus 1

H	H	L	H	|	F = A + /B	|	F = ( A + B ) plus A 	|	F = ( A + B ) plus A plus 1

H	H	H	L	|	F = A + B	|	F = ( A + /B) plus A	|	F = ( A + /B) plus A plus 1

H	H	H	H	|	F = A 	|	F = A minus 1	|	F = A

*	Each bit is shifted to the next more significant position

See also:

Arithmetic Logic Unit Macrofunctions

Macrofunctions (by function)


74182 (Look-Ahead Carry Generator)

Look-Ahead Carry Generator

Default Signal Levels: 	GND--PN3, PN2, PN1, PN0, GN3, GN2, GN1, GN0

VCC--CI

Function Prototype:

FUNCTION 74182 (pn3, pn2, pn1, pn0, gn3, gn2, gn1, gn0, ci)

RETURNS (pn, gn, cz, cy, cx);

Function Table for GN Output:

Inputs	|	Output

GN3	GN2	GN1	GN0	PN3	PN2	PN1	|	GN

L	X	X	X	X	X	X	|	L

X	L	X	X	L	X	X	|	L

X	X	L	X	L	L	X	|	L

X	X	X	L	L	L	L	|	L

All Other Combinations	|	H

Function Table for PN Output:

Inputs	|	Output

PN3	PN2	PN1	PN0	|	PN

L	L	L	L	|	L

All Other Combinations	|	H

Function Table for CX Output:

Inputs	|	Output

GN0	PN0	CI	|	CX

L	X	X	|	H

X	L	H	|	H

All Other Combinations	|	L

Function Table for CY Output:

Inputs	|	Output

GN1	GN0	PN1	PN0	CI	|	CY

L	X	X	X	X	|	H

X	L	L	X	X	|	H

X	X	L	L	H	|	H

All Other Combinations	|	L

Function Table for CZ Output:

Inputs	|	Output

GN2	GN1	GN0	PN2	PN1	PN0	CI	|	GN

L	X	X	X	X	X	X	|	H

X	L	X	L	X	X	X	|	H

X	X	L	L	L	X	X	|	H

X	X	X	L	L	L	H	|	H

All Other Combinations	|	L

See also:

Arithmetic Logic Unit Macrofunctions

Macrofunctions (by function)


74183 (Full Adder)

Dual Carry-Save Full Adder

Default Signal Levels: 	GND--all input pins

Function Prototype:

FUNCTION 74183 (1cn0, 1b, 1a, 2cn0, 2a, 2b)

RETURNS (1sum, 1cn1, 2sum, 2cn1);

Inputs	|	Outputs

CNO	B	A	|	SUM	CN1

L	L	L	|	L	L

L	L	H	|	H	L

L	H	L	|	H	L

L	H	H	|	L	H

H	L	L	|	H	L

H	L	H	|	L	H

H	H	L	|	L	H

H	H	H	|	H	H

See also:

Adder Macrofunctions

Macrofunctions (by function)


74184 (Converter)

BCD-to-Binary Converter

Default Signal Levels: 	GND--all input pins

Function Prototype:

FUNCTION 74184 (e, d, c, b, a, gn)

RETURNS (y[8..1]);

BCD	|	Inputs	|	Outputs

Words	|	|

|	E	D	C	B	A	GN	|	Y5	Y4	Y3	Y2	Y1

0-1	|	L	L	L	L	L	L	|	L	L	L	L	L

2-3	|	L	L	L	L	H	L	|	L	L	L	L	H

4-5	|	L	L	L	H	L	L	|	L	L	L	H	L

6-7	|	L	L	L	H	H	L	|	L	L	L	H	H

8-9	|	L	L	H	L	L	L	|	L	L	H	L	L

10-11	|	L	H	L	L	L	L	|	L	L	H	L	H

12-13	|	L	H	L	L	H	L	|	L	L	H	H	L

14-15	|	L	H	L	H	L	L	|	L	L	H	H	H

16-17	|	L	H	L	H	H	L	|	L	H	L	L	L

18-19	|	L	H	H	L	L	L	|	L	H	L	L	H

20-21	|	H	L	L	L	L	L	|	L	H	L	H	L

22-23	|	H	L	L	L	H	L	|	L	H	L	H	H

24-25	|	H	L	L	H	L	L	|	L	H	H	L	L

26-27	|	H	L	L	H	H	L	|	L	H	H	L	H

28-29	|	H	L	H	L	L	L	|	L	H	H	H	L

30-31	|	H	H	L	L	L	L	|	L	H	H	H	H

32-33	|	H	H	L	L	H	L	|	H	L	L	L	L

34-35	|	H	H	L	H	L	L	|	H	L	L	L	H

36-37	|	H	H	L	H	H	L	|	H	L	L	H	L

38-39	|	H	H	H	L	L	L	|	H	L	L	H	H

Any	|	X	X	X	X	X	H	|	H	H	H	H	H

Input conditions other than those shown produce high levels at outputs Y1 to Y5.

Outputs Y6, Y7, and Y8 are not used for BCD-to-binary conversion.

74184 Function Table (2):

BCD	|	Inputs	|	Outputs

Words	|	|

|	E*	D	C	B	A	|	GN	Y8	Y7	Y6

0	|	L	L	L	L	L	|	L	H	L	H

|	L	L	L	L	H	|	L	H	L	L

2	|	L	L	L	H	L	|	L	L	H	H

3	|	L	L	L	H	H	|	L	L	H	L

4	|	L	L	H	L	L	|	L	L	H	H

5	|	L	L	H	L	H	|	L	L	H	L

6	|	L	L	H	H	L	|	L	L	L	H

7	|	L	L	H	H	H	|	L	L	L	L

8	|	L	H	L	L	L	|	L	L	L	H

9	|	L	H	L	L	H	|	L	L	L	L

0	|	H	L	L	L	L	|	L	L	L	L

1	|	H	L	L	L	H	|	L	H	L	L

2	|	H	L	L	H	L	|	L	H	L	L

3	|	H	L	L	H	H	|	L	L	H	H

4	|	H	L	H	L	L	|	L	L	H	H

5	|	H	L	H	L	H	|	L	L	H	L

6	|	H	L	H	H	L	|	L	L	H	L

7	|	H	L	H	H	H	|	L	L	L	H

8	|	H	H	L	L	L	|	L	L	L	H

9	|	H	H	L	L	H	|	L	L	L	L

Any	|	X	X	X	X	X	|	H	H	H	H

*	When these devices are used as complement converters, input E is used as a mode control. When this input is low, the BCD 9’s complement is generated; when it is high, the BCD 10’s complement is generated.

Input conditions other than those shown produce high levels at outputs Y6, Y7, and Y8.

Outputs Y1 through Y5 are not used for BCD 9’s or 10’s complement conversion.

See also:

Converter Macrofunctions

Macrofunctions (by function)


74151 (Multiplexer)

8-Line-to-1-Line Multiplexer Note

Default Signal Levels:	GND--all input pins

Function Prototype:

FUNCTION 74151 (c, b, a, d[7..0], gn)

RETURNS (y, wn);

Inputs	|	Outputs

Select	|	Enable	|

C	B	A	|	GN	|	Y	WN

X	X	X	|	H	|	L	H

L	L	L	|	L	|	D0	/D0

L	L	H	|	L	|	D1	/D1

L	H	L	|	L	|	D2	/D2

L	H	H	|	L	|	D3	/D3

H	L	L	|	L	|	D4	/D4

H	L	H	|	L	|	D5	/D5

H	H	L	|	L	|	D6	/D6

H	H	H	|	L	|	D7	/D7

See also:

Macrofunctions (by function)

Multiplexer Macrofunctions


74153 (Multiplexer)

Dual 4-Line-to-1-Line Multiplexer

Default Signal Levels:	GND--all input pins

Function Prototype:

FUNCTION 74153 (b, a, 1gn, 1c[3..0], 2gn, 2c[3..0])

RETURNS (1y, 2y);

Inputs	|	Outputs

Select*	|	Data	|	Enable	|

B	A	|	C0	C1	C2	C3	|	GN	|	Y

X	X	|	X	X	X	X	|	H	|	L

L	L	|	L	X	X	X	|	L	|	L

L	L	|	H	X	X	X	|	L	|	H

L	H	|	X	L	X	X	|	L	|	L

L	H	|	X	H	X	X	|	L	|	H

H	L	|	X	X	L	X	|	L	|	L

H	L	|	X	X	H	X	|	L	|	H

H	H	|	X	X	X	L	|	L	|	L

H	H	|	X	X	X	H	|	L	|	H

*	Select inputs A and B are common to both sections.

See also:

Macrofunctions (by function)

Multiplexer Macrofunctions


74154 (Decoder)

4-Line-to-16-Line Decoder

Default Signal Levels:	GND--all input pins

Function Prototype:

FUNCTION 74154 (g1n, g2n, d, c, b, a)

RETURNS (o0n, o1n, o2n, o3n, o4n, o5n, o6n, o7n, o8n, o9n, o10n, o11n, o12n, o13n, o14n, o15n);

Inputs	|	Outputs

G1N	G2N	D	C	B	A	|	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15

L	L	L	L	L	L	|	L	H	H	H	H	H	H	H	H	H	H	H	H	H	H	H

L	L	L	L	L	H	|	H	L	H	H	H	H	H	H	H	H	H	H	H	H	H	H

L	L	L	L	H	L	|	H	H	L	H	H	H	H	H	H	H	H	H	H	H	H	H

L	L	L	L	H	H	|	H	H	H	L	H	H	H	H	H	H	H	H	H	H	H	H

L	L	L	H	L	L	|	H	H	H	H	L	H	H	H	H	H	H	H	H	H	H	H

L	L	L	H	L	H	|	H	H	H	H	H	L	H	H	H	H	H	H	H	H	H	H

L	L	L	H	H	L	|	H	H	H	H	H	H	L	H	H	H	H	H	H	H	H	H

L	L	L	H	H	H	|	H	H	H	H	H	H	H	L	H	H	H	H	H	H	H	H

L	L	H	L	L	L	|	H	H	H	H	H	H	H	H	L	H	H	H	H	H	H	H

L	L	H	L	L	H	|	H	H	H	H	H	H	H	H	H	L	H	H	H	H	H	H

L	L	H	L	H	L	|	H	H	H	H	H	H	H	H	H	H	L	H	H	H	H	H

L	L	H	L	H	H	|	H	H	H	H	H	H	H	H	H	H	H	L	H	H	H	H

L	L	H	H	L	L	|	H	H	H	H	H	H	H	H	H	H	H	H	L	H	H	H

L	L	H	H	L	H	|	H	H	H	H	H	H	H	H	H	H	H	H	H	L	H	H

L	L	H	H	H	L	|	H	H	H	H	H	H	H	H	H	H	H	H	H	H	L	H

L	L	H	H	H	H	|	H	H	H	H	H	H	H	H	H	H	H	H	H	H	H	L

L	H	X	X	X	X	|	H	H	H	H	H	H	H	H	H	H	H	H	H	H	H	H

H	L	X	X	X	X	|	H	H	H	H	H	H	H	H	H	H	H	H	H	H	H	H

H	H	X	X	X	X	|	H	H	H	H	H	H	H	H	H	H	H	H	H	H	H	H

See also:

Decoder Macrofunctions

Macrofunctions (by function)


74155 (Decoder)

Dual 2-Line-to-4-Line Decoder/Demultiplexer

Default Signal Levels: 	GND--2CN, SELA, SELB, 1GN, 2GN

VCC--1C

Function Prototype:

FUNCTION 74155 (2cn, 1c, selb, sela, 2gn, 1gn)

RETURNS (2y0n, 2y1n, 2y2n, 2y3n, 1y0n, 1y1n, 1y2n, 1y3n);

Inputs	|	Outputs

Select	|	Strobe	|	Data	|

SELB	SELA	|	1GN	|	1C	|	1Y0N	1Y1N	1Y2N	1Y3N

X	X	|	H	|	X	|	H	H	H	H

L	L	|	L	|	H	|	L	H	H	H

L	H	|	L	|	H	|	H	L	H	H

H	L	|	L	|	H	|	H	H	L	H

H	H	|	L	|	H	|	H	H	H	L

X	X	|	X	|	L	|	H	H	H	H

Inputs	|	Outputs

Select	|	Strobe	|	Data	|

SELB	SELA	|	2GN	|	2CN	|	2Y0N	2Y1N	2Y2N	2Y3N

X	X	|	H	|	X	|	H	H	H	H

L	L	|	L	|	L	|	L	H	H	H

L	H	|	L	|	L	|	H	L	H	H

H	L	|	L	|	L	|	H	H	L	H

H	H	|	L	|	L	|	H	H	H	L

X	X	|	X	|	H	|	H	H	H	H

74155 Function Table (2):

Inputs	|	Outputs

|	Strobe	|

Select	|	or Data	|

C*	SELB	SELA	|	GN**	|	2Y0	2Y1	2Y2	2Y3	1Y0	1Y1	1Y2	1Y3

X	X	X	|	H	|	H	H	H	H	H	H	H	H

L	L	L	|	L	|	L	H	H	H	H	H	H	H

L	L	H	|	L	|	H	L	H	H	H	H	H	H

L	H	L	|	L	|	H	H	L	H	H	H	H	H

L	H	H	|	L	|	H	H	H	L	H	H	H	H

H	L	L	|	L	|	H	H	H	H	L	H	H	H

H	L	H	|	L	|	H	H	H	H	H	L	H	H

H	H	L	|	L	|	H	H	H	H	H	H	L	H

H	H	H	|	L	|	H	H	H	H	H	H	H	L

* 	C = Inputs 1C and 2CN connected together.

** 	GN = Inputs 1GN and 2GN connected together.

See also:

Decoder Macrofunctions

Macrofunctions (by function)


74156 (Decoder)

Dual 2-Line-to-4-Line Decoder/Demultiplexer

Default Signal Levels:	GND--2CN, SELA, SELB, 1GN, 2GN

VCC--1C

Function Prototype:

FUNCTION 74156 (2cn, 1c, selb, sela, 2gn, 1gn)

RETURNS (2y0n, 2y1n, 2y2n, 2y3n, 1y0n, 1y1n, 1y2n, 1y3n);

Inputs	|	Outputs

Select	|	Strobe	|	Data	|

SELB	SELA	|	1GN	|	1C	|	1Y0N	1Y1N	1Y2N	1Y3N

X	X	|	H	|	X	|	H	H	H	H

L	L	|	L	|	H	|	L	H	H	H

L	H	|	L	|	H	|	H	L	H	H

H	L	|	L	|	H	|	H	H	L	H

H	H	|	L	|	H	|	H	H	H	L

X	X	|	X	|	L	|	H	H	H	H

Inputs	|	Outputs

Select	|	Strobe	|	Data	|

SELB	SELA	|	2GN	|	2CN	|	2Y0N	2Y1N	2Y2N	2Y3N

X	X	|	H	|	X	|	H	H	H	H

L	L	|	L	|	L	|	L	H	H	H

L	H	|	L	|	L	|	H	L	H	H

H	L	|	L	|	L	|	H	H	L	H

H	H	|	L	|	L	|	H	H	H	L

X	X	|	X	|	H	|	H	H	H	H

74156 Function Table (2):

Inputs	|	Outputs

|	Strobe	|

Select	|	or Data	|

C*	SELB	SELA	|	GN**	|	2Y0	2Y1	2Y2	2Y3	1Y0	1Y1	1Y2	1Y3

X	X	X	|	H	|	H	H	H	H	H	H	H	H

L	L	L	|	L	|	L	H	H	H	H	H	H	H

L	L	H	|	L	|	H	L	H	H	H	H	H	H

L	H	L	|	L	|	H	H	L	H	H	H	H	H

L	H	H	|	L	|	H	H	H	L	H	H	H	H

H	L	L	|	L	|	H	H	H	H	L	H	H	H

H	L	H	|	L	|	H	H	H	H	H	L	H	H

H	H	L	|	L	|	H	H	H	H	H	H	L	H

H	H	H	|	L	|	H	H	H	H	H	H	H	L

*	C = Inputs 1C and 2CN connected together.

**	GN = Inputs 1GN and 2GN connected together.

See also:

Decoder Macrofunctions

Macrofunctions (by function)


74157 (Multiplexer)

Quad 2-Line-to-1-Line Multiplexer

Default Signal Levels: 	GND--all input pins

Function Prototype:

FUNCTION 74157 (gn, sel, a[4..1], b[4..1])

RETURNS (y[4..1]);

Inputs	|	Outputs

GN	SEL	A	B	|	Y

H	X	X	X	|	L

L	L	L	X	|	L

L	L	H	X	|	H

L	H	X	L	|	L

L	H	X	H	|	H

See also:

Macrofunctions (by function)

Multiplexer Macrofunctions


74158 (Multiplexer)

Quad 2-Line-to-1-Line Multiplexer with Inverting Outputs

Default Signal Levels:	GND--all input pins

Function Prototype:

FUNCTION 74158 (gn, sel, 1a, 2a, 3a, 4a, 1b, 2b, 3b, 4b)

RETURNS (1yn, 2yn, 3yn, 4yn);

Inputs	|	Outputs

GN	SEL	A	B	|	Y

H	X	X	X	|	H

L	L	L	X	|	H

L	L	H	X	|	L

L	H	X	L	|	H

L	H	X	H	|	L

See also:

Macrofunctions (by function)

Multiplexer Macrofunctions


74160 (Counter)

4-Bit Decade Counter with Synchronous Load and Asynchronous Clear

Default Signal Levels: 	GND--A, B, C, D, CLK

VCC--LDN, ENT, ENP, CLRN

Function Prototype:

FUNCTION 74160 (clk, ldn, clrn, enp, ent, d, c, b, a)

RETURNS (qd, qc, qb, qa, rco);

Inputs	|	Outputs

CLK	LDN	CLRN	ENP	ENT	D	C	B	A	|	QD	QC	QB	QA	RCO

X	X	L	X	X	|	L	L	L	L	L

L	H	X	X	d	c	b	a	|	d	c	b	a	*

H	H	X	L	|	QD	QC	QB	QA	*

H	H	L	X	|	QD	QC	QB	QA	L

H	H	H	H	|	L	L	L	L	L

H	H	H	H	|	L	L	L	H	L

H	H	H	H	|	L	L	H	L	L

H	H	H	H	|	L	L	H	H	L

H	H	H	H	|	L	H	L	L	L

H	H	H	H	|	L	H	L	H	L

H	H	H	H	|	L	H	H	L	L

H	H	H	H	|	L	H	H	H	L

H	H	H	H	|	H	L	L	L	L

H	H	H	H	|	H	L	L	H	H

*	RCO = QD & QA & ENT

See also:

Counter Macrofunctions

Macrofunctions (by function)


74161 (Counter)

4-Bit Binary Up Counter with Synchronous Load and Asynchronous Clear Note

Default Signal Levels: 	GND--A, B, C, D, CLK

VCC--LDN, ENT, ENP, CLRN

Function Prototype:

FUNCTION 74161 (clk, ldn, clrn, enp, ent, d, c, b, a)

RETURNS (qd, qc, qb, qa, rco);

Inputs	|	Outputs

CLK	LDN	CLRN	ENP	ENT	D	C	B	A	|	QD	QC	QB	QA	RCO

X	X	L	X	X	|	L	L	L	L	L

L	H	X	X	d	c	b	a	|	d	c	b	a	*

H	H	X	L	|	QD	QC	QB	QA	*

H	H	L	X	|	QD	QC	QB	QA	*

H	H	H	H	|	L	L	L	L	L

H	H	H	H	|	L	L	L	H	L

H	H	H	H	|	L	L	H	L	L

H	H	H	H	|	L	L	H	H	L

H	H	H	H	|	L	H	L	L	L

H	H	H	H	|	L	H	L	H	L

H	H	H	H	|	L	H	H	L	L

H	H	H	H	|	L	H	H	H	L

H	H	H	H	|	H	L	L	L	L

H	H	H	H	|	H	L	L	H	L

H	H	H	H	|	H	L	H	L	L

H	H	H	H	|	H	L	H	H	L

H	H	H	H	|	H	H	L	L	L

H	H	H	H	|	H	H	L	H	L

H	H	H	H	|	H	H	H	L	L

X	H	H	H	H	|	H	H	H	H	H

*	RCO = QD & QC & QB & QA & ENT

See also:

Counter Macrofunctions

Macrofunctions (by function)


74162 (Counter)

4-Bit Decade Up Counter with Synchronous Load and Synchronous Clear

Default Signal Levels: 	GND--A, B, C, D, CLK

VCC--LDN, ENT, ENP, CLRN

Function Prototype:

FUNCTION 74162 (clk, ldn, clrn, enp, ent, d, c, b, a)

RETURNS (qd, qc, qb, qa, rco);

Inputs	|	Outputs

CLK	LDN	CLRN	ENP	ENT	D	C	B	A	|	QD	QC	QB	QA	RCO

X	L	X	X	|	L	L	L	L	L

L	H	X	X	d	c	b	a	|	d	c	b	a	*

H	H	X	L	|	QD	QC	QB	QA	*

H	H	L	X	|	QD	QC	QB	QA	L

H	H	H	H	|	L	L	L	L	L

H	H	H	H	|	L	L	L	H	L

H	H	H	H	|	L	L	H	L	L

H	H	H	H	|	L	L	H	H	L

H	H	H	H	|	L	H	L	L	L

H	H	H	H	|	L	H	L	H	L

H	H	H	H	|	L	H	H	L	L

H	H	H	H	|	L	H	H	H	L

H	H	H	H	|	H	L	L	L	L

H	H	H	H	|	H	L	L	H	H

*	RCO = QD & QA & ENT

See also:

Counter Macrofunctions

Macrofunctions (by function)


74163 (Counter)

4-Bit Binary Up Counter with Synchronous Load and Synchronous Clear Note

Default Signal Levels: 	GND--A, B, C, D, CLK

VCC--LDN, ENT, ENP, CLRN

Function Prototype:

FUNCTION 74163 (clk, ldn, clrn, enp, ent, d, c, b, a)

RETURNS (qd, qc, qb, qa, rco);

Inputs	|	Outputs

CLK	LDN	CLRN	ENP	ENT	D	C	B	A	|	QD	QC	QB	QA	RCO

X	L	X	X	|	L	L	L	L	L

L	H	X	X	d	c	b	a	|	d	c	b	a	*

H	H	L	H	|	QD	QC	QB	QA	*

H	H	H	L	|	QD	QC	QB	QA	L

H	H	H	H	|	L	L	L	L	L

H	H	H	H	|	L	L	L	H	L

H	H	H	H	|	L	L	H	L	L

H	H	H	H	|	L	L	H	H	L

H	H	H	H	|	L	H	L	L	L

H	H	H	H	|	L	H	L	H	L

H	H	H	H	|	L	H	H	L	L

H	H	H	H	|	L	H	H	H	L

H	H	H	H	|	H	L	L	L	L

H	H	H	H	|	H	L	L	H	L

H	H	H	H	|	H	L	H	L	L

H	H	H	H	|	H	L	H	H	L

H	H	H	H	|	H	H	L	L	L

H	H	H	H	|	H	H	L	H	L

H	H	H	H	|	H	H	H	L	L

H	H	H	H	|	H	H	H	H	H

*	RCO = QD & QC & QB & QA & ENT

See also:

Counter Macrofunctions

Macrofunctions (by function)


74164 (Shift Register)

Serial-In Parallel-Out Shift Register

Default Signal Levels: 	GND--CLK

VCC--A, B, CLRN

Function Prototype:

FUNCTION 74164 (clk, clrn, a, b)

RETURNS (qa, qb, qc, qd, qe, qf, qg, qh);

Inputs	|	Outputs*

CLK	CLRN	A	B	|	QA	QB ..QH

X	L	X	X	|	L	L..L

L	H	X	X	|	QAo	QBo..QHo

H	H	H	|	H	QAn..QGn

H	L	X	|	L	QAn..QGn

H	X	L	|	L	QAn..QGn

*	QAn, QGn = level of QA or QG before the most recent [image] transition of the Clock; indicates a one-bit shift.

See also:

Macrofunctions (by function)

Shift Register Macrofunctions


74165 (Shift Register)

Parallel Load 8-Bit Shift Register

Default Signal Levels: 	GND--SER, A, B, C, D, E, F, G, H, CLKIH, CLK

VCC--STLD

Function Prototype:

FUNCTION 74165 (clk, clkih, stld, ser, a, b, c, d, e, f, g, h)

RETURNS (qh, qhn);

Inputs	|	Outputs

Parallel	|	Internal	|	Output

CLK	CLKIH	STLD	SER	A..H	|	QA	QB	|	QH	QHN

X	X	L	X	a..h	|	a	b	|	h	/h

L	L	H	X	X	|	QAo	QBo	|	QHo	/QGn

L	H	H	X	|	H	QAn*	|	QGn*

L	H	L	X	|	L	QAn	|	QGn	/QGn

X	H	H	X	X	|	QAo	QBo	|	QHo	/QHo

*	QAn, QGn = level of QA or QG before the most recent [image] transition of the Clock

See also:

Macrofunctions (by function)

Shift Register Macrofunctions


74166 (Shift Register)

8-Bit Shift Register with Clock Inhibit

Default Signal Levels:	GND--SER, A, B, C, D, E, F, G, H, CLKIH, CLK

VCC--STLD, CLRN

Function Prototype:

FUNCTION 74166 (clrn, stld, clkih, clk, ser, a, b, c, d, e, f, g, h)

RETURNS (qh);

Inputs	|	Outputs

Parallel	|	Internal	|	Output

CLRN	STLD	CLKIH	CLK	SER	A..H	|	QA	QB	|	QH

L	X	X	X	X	X	|	L	L	|	L

H	X	L	L	X	X	|	QAo	QBo	|	QHo

H	L	L	X	a..h	|	a	b	|	h

H	H	L	H	X	|	H	QAn	|	QGn

H	H	L	L	X	|	L	QAn	|	QGn

H	X	H	X	X	X	|	QAo	QBo	|	QHo

See also:

Macrofunctions (by function)

Shift Register Macrofunctions


74167 (Rate Multiplier)

Synchronous Decade Rate Multiplier

Default Signal Levels: 	GND--SET9, CLR, CLK, ENN, STRBN, UNI/CAS

VCC--BO, B1, B2, B3

Function Prototype:

FUNCTION 74167 (clk, clr, enn, strbn, b[3..0], uni/cas, set9)

RETURNS (y, zn, eno);

This macrofunction is not directly supported by VHDL because it contains one or more port names with a slash (/) or dash (-). These characters are illegal in VHDL port names. However, you can use this macrofunction in your project by incorporating it into a lower-level design file, then inserting an instance of the lower-level file into your VHDL Design File. See Using a MAX+PLUS II Primitive or Macrofunction for more information.

Inputs	|	Outputs	|	Notes

# Clock	|	|

CLR	ENN	STRBN	B3	B2	B1	B0	Pulses	UNI/CAS	|	Y	ZN	ENO	|

H	X	H	X	X	X	X	X	H	|	L	H	H	|	*

L	L	L	L	L	L	L	10	H	|	L	H	1	|	**

L	L	L	L	L	L	H	10	H	|	1	1	1	|	**

L	L	L	L	L	H	L	10	H	|	2	2	1	|	**

L	L	L	L	L	H	H	10	H	|	3	3	1	|	**

L	L	L	L	H	L	L	10	H	|	4	4	1	|	**

L	L	L	L	H	L	H	10	H	|	5	5	1	|	**

L	L	L	L	H	H	L	10	H	|	6	6	1	|	**

L	L	L	L	H	H	H	10	H	|	7	7	1	|	**

L	L	L	H	L	L	L	10	H	|	8	8	1	|	**

L	L	L	H	L	L	H	10	H	|	9	9	1	|	**

L	L	L	H	L	H	L	10	H	|	8	8	1	|	**, ***

L	L	L	H	L	H	H	10	H	|	9	9	1	|	**, ***

L	L	L	H	H	L	L	10	H	|	8	8	1	|	**, ***

L	L	L	H	H	L	H	10	H	|	9	9	1	|	**, ***

L	L	L	H	H	H	L	10	H	|	8	8	1	|	**, ***

L	L	L	H	H	H	H	10	H	|	9	9	1	|	**, ***

L	L	L	X	X	X	X	10	L	|	H	9	1	|	****

*	This is a simplified illustration of the clear function. The states of Clocks and the strobe can affect the logic level of Y and  Z. A low UNI/CAS will cause output Y to remain high.

**	Each rate illustrated assumes a constant value at rate inputs; however, these illustrations in no way prohibit variable-rate inputs.

***	These input conditions exceed the range of the decimal rate inputs.

****	UNI/CAS can be used to inhibit output Y.

See also:

Macrofunctions (by function)

Rate Multiplier Macrofunctions


74168 (Counter)

Synchronous 4-Bit Decade Up/Down Counter

Default Signal Levels: 	GND--ENTN, ENPN, CLK,

VCC--D0, D1, D2, D3, U/DN, LDN

Function Prototype:

FUNCTION 74168 (ldn, entn, enpn, u/dn, clk, d[3..0])

RETURNS (q[3..0], tcn);

This macrofunction is not directly supported by VHDL because it contains one or more port names with a slash (/) or dash (-). These characters are illegal in VHDL port names. However, you can use this macrofunction in your project by incorporating it into a lower-level design file, then inserting an instance of the lower-level file into your VHDL Design File. See Using a MAX+PLUS II Primitive or Macrofunction for more information.

Inputs	|	Outputs

LDN	ENTN	ENPN	U/DN	CLK	D3	D2	D1	D0	|	Q3	Q2	Q1	Q0	TCN

L	X	X	X	D[3..0]	|	D[3..0]

H	H	X	X	X	X	X	X	X	|	Q3o..Q0o

H	X	H	X	X	X	X	X	X	|	Q3o..Q0o

H	L	L	H	X	X	X	X	|	Count Up	*

H	L	L	L	X	X	X	X	|	Count Down	**

*	TCN goes low when the count is 9.

**	TCN goes low when the count is 0.

See also:

Counter Macrofunctions

Macrofunctions (by function)


74169 (Counter)

Synchronous 4-Bit Binary Up/Down Counter

Default Signal Levels:	GND--ENTN, ENPN, CLK

VCC--D0, D1, D2, D3, U/DN, LDN

Function Prototype:

FUNCTION 74169 (ldn, entn, enpn, u/dn, clk, d[3..0])

RETURNS (q[3..0], tcn);

This macrofunction is not directly supported by VHDL because it contains one or more port names with a slash (/) or dash (-). These characters are illegal in VHDL port names. However, you can use this macrofunction in your project by incorporating it into a lower-level design file, then inserting an instance of the lower-level file into your VHDL Design File. See Using a MAX+PLUS II Primitive or Macrofunction for more information.

Inputs	|	Outputs

LDN	ENTN	ENPN	U/DN	CLK	D3	D2	D1	D0	|	Q3	Q2	Q1	Q0	TCN

L	X	X	X	D[3..0]	|	D[3..0]

H	H	X	X	X	X	X	X	X	|	Q3o..Q0o

H	X	H	X	X	X	X	X	X	|	Q3o..Q0o

H	L	L	H	X	X	X	X	|	Count Up	*

H	L	L	L	X	X	X	X	|	Count Down	**

*	TCN goes low when the count is 15.

**	TCN goes low when the count is 0.

See also:

Counter Macrofunctions

Macrofunctions (by function)


74171 (Register)

Quad D-Type Flipflops with Clear

Default Signal Levels:	GND--CLK

VCC--CLRN, D1, D2, D3, D4

Function Prototype:

FUNCTION 74171 (clrn, clk, d1, d2, d3, d4)

RETURNS (q1, qn1, q2, qn2, q3, qn3, q4, qn4);

Inputs	|	Outputs

CLRN	CLK	D	|	Q	QN

L	X	X	|	L	H

H	L	|	L	H

H	H	|	H	L

See also:

Macrofunctions (by function)

Register Macrofunctions


7491 (Shift Register)

Serial-In Serial-Out Shift Register

Default Signal Levels:	GND--CLK

VCC--A, B

Function Prototype:

FUNCTION 7491 (clk, a, b)

RETURNS (qh, qhn);

Inputs at tn*	|	Outputs at tn + 8**

CLK	A	B	|	QH	QHN

H	H	|	H	L

L	X	|	L	H

X	L	|	L	H

*	tn = reference bit time, Clock low

**	tn + 8 = bit time after 8 [image] Clock transitions

See also:

Macrofunctions (by function)

Shift Register Macrofunctions


7492 (Counter)

Divide-by-12 Counter

Default Signal Levels:	GND--CLRA, CLRB

VCC--CLKA, CLKB

Function Prototype:

FUNCTION 7492 (clra, clrb, clka, clkb)

RETURNS (qd, qc, qb, qa);

Inputs	|	Outputs

CLR*	CLK	|	Q

L	X	|	L

H	|	Count**

*	CLR = CLRA & CLRB

**	QA is connected to CLKB for divide-by-12 count.

Count Sequence:

Inputs	|	Outputs

COUNT	|	QD	QC	QB	QA

0	|	L	L	L	L

1	|	L	L	L	H

2	|	L	L	H	L

3	|	L	L	H	H

4	|	L	H	L	L

5	|	L	H	L	H

6	|	H	L	L	L

7	|	H	L	L	H

8	|	H	L	H	L

9	|	H	L	H	H

10	|	H	H	L	L

11	|	H	H	L	H

See also:

Counter Macrofunctions

Macrofunctions (by function)


7493 (Counter)

4-Bit Binary Counter

Default Signal Levels:	GND--RO1, RO2

VCC--CLKA, CLKB

Function Prototype:

FUNCTION 7493 (clka, clkb, ro1, ro2)

RETURNS (qd, qc, qb, qa);

Count*	|	Outputs

CLKB = QA	|	QD	QC	QB	QA

0	|	L	L	L	L

1	|	L	L	L	H

2	|	L	L	H	L

3	|	L	L	H	H

4	|	L	H	L	L

5	|	L	H	L	H

6	|	L	H	H	L

7	|	L	H	H	H

8	|	H	L	L	L

9	|	H	L	L	H

10	|	H	L	H	L

11	|	H	L	H	H

12	|	H	H	L	L

13	|	H	H	L	H

14	|	H	H	H	L

15	|	H	H	H	H

*	QA is connected to CLKB for binary count.

Reset Inputs	|	Outputs

RO1	RO2	|	QD	QC	QB	QA

H	H	|	L	L	L	L

L	X	|	Count

X	L	|	Count

See also:

Counter Macrofunctions

Macrofunctions (by function)


7494 (Shift Register)

4-Bit Shift Register with Asynchronous Preset and Asynchronous Clear

Default Signal Levels:	GND--all input pins

Function Prototype:

FUNCTION 7494 (p1a, p2a, p1b, p2b, p1c, p2c, p1d, p2d, pe1, pe2, clr, clk, ser)

RETURNS (out);

Internal	|	Inputs	|	Internal	|	Output

Presets	|	|	Outputs	|

A	B	C	D	|	CLR	CLK	SER	|	QA	QB	QC	|	OUT (QD)

H	H	H	H	|	H	X	X	|	L	L	L	|	L

L	L	L	L	|	L	X	X	|	H	H	H	|	H

H	H	H	H	|	L	L	X	|	QAo	QBo	QCo	|	QDo

L	H	L	H	|	L	L	X	|	H	QBo	H	|	QDo

H	H	H	H	|	L	L	|	L	QAn	QBn	|	QCn

H	H	H	H	|	L	H	|	H	QAn	QBn	|	QCn

7494 Preset Function Table:

Preset Inputs	|	Internal

|	Preset A*

PE1	P1A	PE2	P2A	|

L	X	L	X	|	H (Inactive)

L	X	X	L	|	H (Inactive)

X	L	L	X	|	H (Inactive)

X	L	X	L	|	H (Inactive)

H	H	X	X	|	L (Active)

X	X	H	H	|	L (Active)

*	Bit A is typical of all internal presets.

See also:

Macrofunctions (by function)

Shift Register Macrofunctions


7495 (Shift Register)

4-Bit Parallel-Access Shift Register

Default Signal Levels:	VCC--all input pins

Function Prototype:

FUNCTION 7495 (mode, clkl, clkr, ser, d[0..3])

RETURNS (q[0..3]);

Inputs	|	Outputs

MODE	CLKL	CLKR	SER	D0	D1	D2	D3	|	Q0	Q1	Q2	Q3

H	H	X	X	X	X	X	X	|	Q0o	Q1o	Q2o	Q3o

H	X	X	a	b	c	d	|	a	b	c	d

H	X	X	Q1*	Q2*	Q3*	d	|	Q1n	Q2n	Q3n	d

L	L	H	X	X	X	X	X	|	Q0o	Q1o	Q2o	Q3o

L	X	H	X	X	X	X	|	H	Q0n	Q1n	Q2n

L	X	L	X	X	X	X	|	L	Q0n	Q1n	Q2n

L	L	X	X	X	X	X	|	Q0o	Q1o	Q2o	Q3o

L	L	X	X	X	X	X	|	Q0o	Q1o	Q2o	Q3o

L	H	X	X	X	X	X	|	Q0o	Q1o	Q2o	Q3o

H	L	X	X	X	X	X	|	Q0o	Q1o	Q2o	Q3o

H	H	X	X	X	X	X	|	Q0o	Q1o	Q2o	Q3o

*	Shifting left requires the following connections:

Q1 to D0

Q2 to D1

Q3 to D2

Serial data is entered at input D3.

See also:

Macrofunctions (by function)

Shift Register Macrofunctions


7496 (Shift Register)

5-Bit Shift Register

Default Signal Levels:	GND--A, B, C, D, E, SER, PE, CLK

VCC--CLRN

Function Prototype:

FUNCTION 7496 (clrn, pe, a, b, c, d, e, clk, ser)

RETURNS (qa, qb, qc, qd, qe);

Inputs	|	Outputs

|	Preset	|	|

CLRN	PE	|	A	B	C	D	E	|	CLK	SER	|	QA	QB	QC	QD	QE

L	L	|	X	X	X	X	X	|	X	X	|	L	L	L	L	L

L	X	|	L	L	L	L	L	|	X	X	|	L	L	L	L	L

H	H	|	H	H	H	H	H	|	X	X	|	H	H	H	H	H

H	H	|	L	L	L	L	L	|	L	X	|	QAo	QBo	QCo	QDo	QEo

H	H	|	H	L	H	L	H	|	L	X	|	H	QBo	H	QDo	H

H	L	|	X	X	X	X	X	|	L	X	|	QAo	QBo	QCo	QDo	QEo

H	L	|	X	X	X	X	X	|	H	|	H	QAn	QBn	QCn	QDn

H	L	|	X	X	X	X	X	|	L	|	L	QAn	QBn	QCn	QDn

See also:

Macrofunctions (by function)

Shift Register Macrofunctions


7497 (Multiplier)

Synchronous 6-Bit Rate Multiplier

Default Signal Levels:	GND--ENN, STRBN, CLK, CLR

VCC--B5, B4, B3, B2, B1, B0, UNI/CAS

Function Prototype:

FUNCTION 7497 (clk, clr, enn, strbn, b[5..0], uni/cas)

RETURNS (y, zn, tcn);

This macrofunction is not directly supported by VHDL because it contains one or more port names with a slash (/) or dash (-). These characters are illegal in VHDL port names. However, you can use this macrofunction in your project by incorporating it into a lower-level design file, then inserting an instance of the lower-level file into your VHDL Design File. See Using a MAX+PLUS II Primitive or Macrofunction for more information.

Inputs	|	Outputs

CLR	ENN	STRBN	B5	B4	B3	B2	B1	B0	UNI/CAS	|	Y	ZN	TCN

H	X	H	X	X	X	X	X	X	H	|	L	H	L

L	L	L	B[5..0]	H	|	*	**	***

L	H	X	X	X	X	X	X	X	H	|	Yo	ZNo	H

L	L	L	X	X	X	X	X	X	L	|	H

*	Y has B[5..0] low pulses in 64 Clock cycles.

**	ZN has B[5..0] high pulses in 64 Clock cycles.

***	TCN pulses low every 64 Clock cycles for cascading.

See also:

Macrofunctions (by function)

Multiplier Macrofunctions


7498 (Storage Register)

4-Bit Data Selector/Storage Register

Default Signal Levels:	VCC all input pins

Function Prototype:

FUNCTION 7498 (clkn, wrdsl, a1, b1, c1, d1, a2, b2, c2, d2)

RETURNS (qa, qb, qc, qd);

Inputs	|	Outputs

CLKN	WRDSL	A1	B1	C1	D1	A2	B2	C2	D2	|	QA	QB	QC	QD

L	a1	b1	c1	d1	X	X	X	X	|	a1	b1	c1	d1

H	X	X	X	X	a2	b2	c2	d2	|	a2	b2	c2	d2

See also:

Macrofunctions (by function)

Storage Register Macrofunctions


7499 (Shift Register)

4-Bit Shift Register with /JK Serial Inputs and Parallel Outputs

Default Signal Levels:	GND--J, A, B, C, D, MODE, CLK1, CLK2

VCC--KN

Function Prototype:

FUNCTION 7499 (mode, clk2, clk1, j, kn, a, b, c, d)

RETURNS (qa, qb, qc, qd, qdn);

Inputs	|	Outputs

|	Clocks	|	Serial	|	Parallel	|

MODE	|	CLK2	CLK1	|	J	KN	|	A	B	C	D	|	QA	QB	QC	QD	QDN

H	|	H	X	|	X	X	|	|	Hold

H	|	X	|	X	X	|	a	b	c	d	|	a	b	c	d	/d

H	|	X	|	X	X	|	QB*	QC*	QD	d*	|	QBn	QCn	QDn	d	/d

L	|	X	H	|	X	X	|	|	Hold

L	|	X	|	L	H	|	|	QAo	QAo	QBn	QCn	/QCn

L	|	X	|	L	L	|	|	L	QAn	QBn	QCn	/QCn

L	|	X	|	H	H	|	|	H	QAn	QBn	QCn	/QCn

L	|	X	|	H	L	|	|	/QAn	QAn	QBn	QCn	/QCn

X	|	L	L	|	X	X	|	|	Hold

*	Shifting left requires connection of QB to A, QC to B, and QD to C; serial data is entered at input D.

See also:

Macrofunctions (by function)

Shift Register Macrofunctions


74107 (Register)

Dual JK Flipflop with Clear

Default Signal Levels:	GND--1J, 1K, 1CLK, 2J, 2K, 2CLK

VCC--1CLRN, 2CLRN

Function Prototype:

FUNCTION 74107 (1j, 1k, 1clrn, 1clk, 2j, 2k, 2clrn, 2clk)

RETURNS (1q, 1qn, 2q, 2qn);

Inputs	|	Outputs

CLRN	CLK	J	K	|	Q	QN

L	X	X	X	|	L	H

H	L	L	|	Qo	/Qo

H	H	L	|	H	L

H	L	H	|	L	H

H	H	H	|	Toggle

See also:

Macrofunctions (by function)

Register Macrofunctions


74109 (Register)

Dual JK Flipflop with Preset and Clear

Defaule Signal Levels:	GND--1J, 1CLK, 2J, 2CLK

VCC--1PRN, 1KN, 1CLRN, 2PRN, 2KN, 2CLRN

Function Prototype:

FUNCTION 74109 (1prn, 1j, 1kn, 1clrn, 1clk, 2prn, 2j, 2kn, 2clrn, 2clk)

RETURNS (1q, 1qn, 2q, 2qn);

Inputs	|	Outputs

PRN	CLRN	CLK	J	KN	|	Q	QN

L	H	X	X	X	|	H	L

H	L	X	X	X	|	L	H

L	L	X	X	X	|	Illegal

H	H	L	L	|	L	H

H	H	H	L	|	Toggle

H	H	L	H	|	Qo	/Qo

H	H	H	H	|	H	L

H	H	L	X	X	|	Qo	/Qo

See also:

Macrofunctions (by function)

Register Macrofunctions


74112 (Register)

Dual JK Negative-Edge-Triggered Flipflop with Preset and Clear

Default Signal Levels:	GND--1J, 1K, 2J, 2K

VCC--1PRN, 1CLRN, 1CLK, 2PRN, 2CLRN, 2CLK

Function Prototype:

FUNCTION 74112 (1prn, 1j, 1k, 1clrn, 1clk, 2prn, 2j, 2k, 2clrn, 2clk)

RETURNS (1q, 1qn, 2q, 2qn);

Inputs	|	Outputs

PRN	CLRN	CLK	J	K	|	Q	QN

L	H	X	X	X	|	H	L

H	L	X	X	X	|	L	H

L	L	X	X	X	|	Illegal

H	H	L	L	|	Qo	/Qo

H	H	H	L	|	H	L

H	H	L	H	|	L	H

H	H	H	H	|	Toggle

H	H	H	X	X	|	Qo	/Qo

See also:

Macrofunctions (by function)

Register Macrofunctions


74113 (Register)

Dual JK Negative-Edge-Triggered Flipflop with Preset

Default Signal Levels:	GND--1J, 1K, 2J, 2K

VCC--1PRN, 1CLK, 2PRN, 2CLK

Function Prototype:

FUNCTION 74113 (1prn, 1j, 1k, 1clk, 2prn, 2j, 2k, 2clk)

RETURNS (1q, 1qn, 2q, 2qn);

Inputs	|	Outputs

PRN	CLK	J	K	|	Q	QN

L	X	X	X	|	H	L

H	L	L	|	Qo	/Qo

H	H	L	|	H	L

H	L	H	|	L	H

H	H	H	|	Toggle

H	H	X	X	|	Qo	/Qo

See also:

Macrofunctions (by function)

Register Macrofunctions


74114 (Register)

Dual JK Negative-Edge-Triggered Flipflop with Preset, Common Clear, and Common Clock

Default Signal Levels:	GND--1J, 1K, 2J, 2K

VCC--1PRN, 2PRN, CLRN, CLK

Function Prototype:

FUNCTION 74114 (1prn, 1j, 1k, 1clk, 2prn, 2j, 2k, clrn, clk)

RETURNS (1q, 1qn, 2q, 2qn);

Inputs	|	Outputs

PRN	CLRN	CLK	J	K	|	Q	QN

L	H	X	X	X	|	H	L

H	L	X	X	X	|	L	H

L	L	X	X	X	|	Illegal

H	H	L	L	|	Qo	/Qo

H	H	H	L	|	H	L

H	H	L	H	|	L	H

H	H	H	H	|	Toggle

H	H	H	X	X	|	Qo	/Qo

See also:

Macrofunctions (by function)

Register Macrofunctions


74116 (Latch)

Dual 4-Bit Latch with Clear

Default Signal Levels:	GND--1D1, 1D2, 1D3, 1D4, 2D1, 2D2, 2D3, 2D4, 1G1N, 1G2N, 2G1N, 2G2N

VCC--1CLRN, 2CLRN

Function Prototype:

FUNCTION 74116 (1clrn, 2clrn, 1g1n, 1g2n, 2g1n, 2g2n, 1d[4..1], 2d[4..1])

RETURNS 1q[4..1], 2q[4..1]);

Inputs	|	Outputs

|	Enable	|	|

CLRN	|	G1N	G2N	|	D	|	Q

L	|	X	X	|	X	|	L

H	|	L	L	|	L	|	L

H	|	L	L	|	H	|	H

H	|	X	H	|	X	|	Qo

H	|	H	X	|	X	|	Qo

See also:

Macrofunctions (by function)

Latch Macrofunctions


74133 (SSI Function)

13-Input NAND Gate

Default Signal Levels:	VCC--all input pins

Function Prototype:

FUNCTION 74133 (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)

RETURNS (1);

Inputs	|	Output

A through M	|	Y

All inputs H	|	L

One or more L	|	H

See also:

Macrofunctions (by function)

SSI Functions


74134 (SSI Function)

12-Input NAND Gate with Tri-State Output

Default Signal Levels:	GND--OEN

VCC--all other input pins

Function Prototype:

FUNCTION 74134 (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, oen)

RETURNS (1);

Inputs	|	Output

OEN	A through L	|	Y

H	X	|	Z

L	All inputs H	|	L

L	One or more L	|	H

See also:

Macrofunctions (by function)

SSI Functions


74135 (SSI Function)

Quad XOR/XNOR Gates

Default Signal Levels:	GND--all input pins

Function Prototype:

FUNCTION 74135 (1a, 2b, 12c, 2a, 2b, 3a, 3b, 34c, 4a, 4b)

RETURNS (1y, 2y, 3y, 4y);

Inputs	|	Outputs

A	B	C	|	Y

L	L	L	|	L

L	H	L	|	H

H	L	L	|	H

H	H	L	|	L

L	L	H	|	H

L	H	H	|	L

H	L	H	|	L

H	H	H	|	H

See also:

Macrofunctions (by function)

SSI Functions


74137 (Decoder)

3-Line-to-8-Line Decoder with Address Latches

Default Signal Levels:	GND--GLN, G2N

VCC--G1, A, B, C

Function Prototype:

FUNCTION 74137 (gln, g1, g2n, c, b, a)

RETURNS (y[0..7]);

Inputs	|	Outputs

GLN	G1	G2N	C	B	A	|	Y0	Y1	Y2	Y3	Y4	Y5	Y6	Y7

X	X	H	X	X	X	|	H	H	H	H	H	H	H	H

X	L	X	X	X	X	|	H	H	H	H	H	H	H	H

L	H	L	L	L	L	|	L	H	H	H	H	H	H	H

L	H	L	L	L	H	|	H	L	H	H	H	H	H	H

L	H	L	L	H	L	|	H	H	L	H	H	H	H	H

L	H	L	L	H	H	|	H	H	H	L	H	H	H	H

L	H	L	H	L	L	|	H	H	H	H	L	H	H	H

L	H	L	H	L	H	|	H	H	H	H	H	L	H	H

L	H	L	H	H	L	|	H	H	H	H	H	H	L	H

L	H	L	H	H	H	|	H	H	H	H	H	H	H	L

H	H	L	X	X	X	|	Low output corresponds to address stored in latches

See also:

Decoder Macrofunctions

Macrofunctions (by function)


74138 (Decoder)

3-Line-to-8-Line Decoder

Default Signal Levels:	GND--A, B, C, G2AN, G2BN

VCC--G1

Function Prototype:

FUNCTION 74138 (g1, g2an, g2bn, c, b, a)

RETURNS (y0n, y1n, y2n, y3n, y4n, y5n, y6n, y7n);

Inputs	|	Outputs

Enable	|	Select	|

G1	G2*	|	C	B	A	|	Y0N	Y1N	Y2N	Y3N	Y4N	Y5N	Y6N	Y7N

X	H	|	X	X	X	|	H	H	H	H	H	H	H	H

L	X	|	X	X	X	|	H	H	H	H	H	H	H	H

H	L	|	L	L	L	|	L	H	H	H	H	H	H	H

H	L	|	L	L	H	|	H	L	H	H	H	H	H	H

H	L	|	L	H	L	|	H	H	L	H	H	H	H	H

H	L	|	L	H	H	|	H	H	H	L	H	H	H	H

H	L	|	H	L	L	|	H	H	H	H	L	H	H	H

H	L	|	H	L	H	|	H	H	H	H	H	L	H	H

H	L	|	H	H	L	|	H	H	H	H	H	H	L	H

H	L	|	H	H	H	|	H	H	H	H	H	H	H	L

*	G2 = G2AN + G2BN

See also:

Decoder Macrofunctions

Macrofunctions (by function)


74139 (Decoder)

Dual 2-Line-to-4-Line Decoder

Default Signal Levels:	GND--all input pins

Function Prototype:

FUNCTION 74139 (g1n, b1, a1, g2n, b2, a2)

RETURNS (y10n, y11n, y12n, y13n, y20n, y21n, y22n, y23n);

Inputs	|	Outputs

Enable	|	Select	|

GN	|	B	A	|	Y0N	Y1N	Y2N	Y3N

H	|	X	X	|	H	H	H	H

L	|	L	L	|	L	H	H	H

L	|	L	H	|	H	L	H	H

L	|	H	L	|	H	H	L	H

L	|	H	H	|	H	H	H	L

See also:

Decoder Macrofunctions

Macrofunctions (by function)


74143 (Counter)

4-Bit Counter/Latch, 7-Segment Driver

Default Signal Levels:	GND--PCEIN, SCEIN, STRBN, BIN

VCC--CLK, CLRN, RBIN, DPI

Function Prototype:

FUNCTION 74143 (clk, clrn, strbn, pcein, scein, bin, rbin, dpi)

RETURNS (qd, qc, qb, qa, max, a, b, c, d, e, f, g, dpo, rbon);

Inputs	|	Outputs

CLK	CLRN	STRBN	PCEIN	SCEIN	BIN	RBIN	|	DPI	QD..QA	MAX	A ..G	DPO	RBON

H	L	L	L	L	X	|	X	Count	H	Count	H

H	L	L	L	L	H	|	X	L	H	Off	L

H	L	L	L	L	X	|	X	9	L	*	H

X	L	X	X	X	X	X	|	X	L	H	Off	Off	L

X	H	H	X	X	L	X	|	X	Latch	Latch	H

X	H	L	H	X	L	X	|	X	Hold	Hold	H

X	H	L	X	H	L	X	|	X	Hold	Hold	H

H	L	L	L	H	X	|	X	Count	Off	Off	L

H	L	L	L	L	X	|	H	Count	Count	On	H

*	See the Count Sequence table.

Count Sequence:

COUNT	A	B	C	D	E	F	G

0	On	On	On	On	On	On	Off

1	Off	On	On	Off	Off	Off	Off

2	On	On	Off	On	On	Off	On

3	On	On	On	On	Off	Off	On

4	Off	On	On	Off	Off	On	On

5	On	Off	On	On	Off	On	On

6	On	Off	On	On	On	On	On

7	On	On	On	Off	Off	Off	Off

8	On	On	On	On	On	On	On

9	On	On	On	On	Off	On	On

See also:

Counter Macrofunctions

Macrofunctions (by function)


74145 (Decoder)

BCD-to-Decimal Decoder

Default Signal Levels:	GND--all input pins

Function Prototype:

FUNCTION 74145 (d, c, b, a)

RETURNS (o0n, o1n, o2n, o3n, o4n, o5n, o6n, o7n, o8n, o9n);

Inputs	|	Outputs

D	C	B	A	|	O0N	O1N	O2N	O3N	O4N	O5N	O6N	O7N	O8N	O9N

L	L	L	L	|	L	H	H	H	H	H	H	H	H	H

L	L	L	H	|	H	L	H	H	H	H	H	H	H	H

L	L	H	L	|	H	H	L	H	H	H	H	H	H	H

L	L	H	H	|	H	H	H	L	H	H	H	H	H	H

L	H	L	L	|	H	H	H	H	L	H	H	H	H	H

L	H	L	H	|	H	H	H	H	H	L	H	H	H	H

L	H	H	L	|	H	H	H	H	H	H	L	H	H	H

L	H	H	H	|	H	H	H	H	H	H	H	L	H	H

H	L	L	L	|	H	H	H	H	H	H	H	H	L	H

H	L	L	H	|	H	H	H	H	H	H	H	H	H	L

H	L	H	L	|	H	H	H	H	H	H	H	H	H	H	(Invalid)

H	L	H	H	|	H	H	H	H	H	H	H	H	H	H	(Invalid)

H	H	L	L	|	H	H	H	H	H	H	H	H	H	H	(Invalid)

H	H	L	H	|	H	H	H	H	H	H	H	H	H	H	(Invalid)

H	H	H	L	|	H	H	H	H	H	H	H	H	H	H	(Invalid)

H	H	H	H	|	H	H	H	H	H	H	H	H	H	H	(Invalid)

See also:

Decoder Macrofunctions

Macrofunctions (by function)


74147 (Encoder)

10-Line-to-4-Line BCD Encoder

Default Signal Levels:	VCC--all input pins

Function Prototype:

FUNCTION 74147 (1n, 2n, 3n, 4n, 5n, 6n, 7n, 8n, 9n)

RETURNS (dn, cn, bn, an);

Inputs	|	Outputs

1N	2N	3N	4N	5N	6N	7N	8N	9N	|	DN	CN	BN	AN

H	H	H	H	H	H	H	H	H	|	H	H	H	H

X	X	X	X	X	X	X	X	L	|	L	H	H	L

X	X	X	X	X	X	X	L	H	|	L	H	H	H

X	X	X	X	X	X	L	H	H	|	H	L	L	L

X	X	X	X	X	L	H	H	H	|	H	L	L	H

X	X	X	X	L	H	H	H	H	|	H	L	H	L

X	X	X	L	H	H	H	H	H	|	H	L	H	H

X	X	L	H	H	H	H	H	H	|	H	H	L	L

X	L	H	H	H	H	H	H	H	|	H	H	L	H

L	H	H	H	H	H	H	H	H	|	H	H	H	L

See also:

Encoder Macrofunctions

Macrofunctions (by function)


74148 (Encoder)

8-Line-to-3-Line Octal Encoder

Default Signal Levels:	GND--all input pins

Function Prototype:

FUNCTION 74148 (ein, 0n, 1n, 2n, 3n, 4n, 5n, 6n, 7n)

RETURNS (a2n, a1n, a0n, gsn, eon);

Inputs	|	Outputs

EIN	0N	1N	2N	3N	4N	5N	6N	7N	|	A2N	A1N	A0N	GSN	EON

H	X	X	X	X	X	X	X	X	|	H	H	H	H	H

L	H	H	H	H	H	H	H	H	|	H	H	H	H	L

L	X	X	X	X	X	X	X	L	|	L	L	L	L	H

L	X	X	X	X	X	X	L	H	|	L	L	H	L	H

L	X	X	X	X	X	L	H	H	|	L	H	L	L	H

L	X	X	X	X	L	H	H	H	|	L	H	H	L	H

L	X	X	X	L	H	H	H	H	|	H	L	L	L	H

L	X	X	L	H	H	H	H	H	|	H	L	H	L	H

L	X	L	H	H	H	H	H	H	|	H	H	L	L	H

L	L	H	H	H	H	H	H	H	|	H	H	H	L	H

See also:

Encoder Macrofunctions

Macrofunctions (by function)


7452 (SSI Function)

AND-OR Gate

Default Signal Levels:	VCC--all input pins

Function Prototype:

FUNCTION 7452 (x, a, b, c, d, e, f, g, h, i)

RETURNS (y);

Inputs	|	Output

X	A	B	C	D	E	F	G	H	I	|	Y

H	X	X	X	X	X	X	X	X	X	|	H

X	H	H	X	X	X	X	X	X	X	|	H

X	X	X	H	H	H	X	X	X	X	|	H

X	X	X	X	X	X	H	H	X	X	|	H

X	X	X	X	X	X	X	X	H	H	|	H

All Others	|	L

See also:

Macrofunctions (by function)

SSI Functions


7453 (SSI Function)

Expandable 4-Wide AND-OR-INVERT Gate

Default Signal Levels:	VCC--all input pins

Function Prototype:

FUNCTION 7453 (xn, x, a, b, c, d, e, f, g, h)

RETURNS (yn);

Inputs	|	Outputs

X	XN	A	B	C	D	E	F	G	H	|	YN

L	H	H	H	X	X	X	X	X	X	|	L

L	H	X	X	H	H	X	X	X	X	|	L

L	H	X	X	X	X	H	H	X	X	|	L

L	H	X	X	X	X	X	X	H	H	|	L

H	X	X	X	X	X	X	X	X	X	|	L

X	L	X	X	X	X	X	X	X	X	|	L

All Others	|	H

See also:

Macrofunctions (by function)

SSI Functions


7454 (SSI Function)

4-Wide AND-OR-INVERT Gate

Default Signal Levels:	VCC--all input pins

Function Prototype:

FUNCTION 7454 (a, b, c, d, e, f, g, h, i, j)

RETURNS (yn);

Inputs	|	Output

A	B	C	D	E	F	G	H	I	J	|	YN

H	H	X	X	X	X	X	X	X	X	|	L

X	X	H	H	H	X	X	X	X	X	|	L

X	X	X	X	X	H	H	H	X	X	|	L

X	X	X	X	X	X	X	X	H	H	|	L

All Others	|	H

See also:

Macrofunctions (by function)

SSI Functions


7455 (SSI Function)

2-Wide, 4-Input AND-OR-INVERT Gate

Default Signal Levels:	VCC--all input pins

Function Prototype:

FUNCTION (a, b, c, d, e, f, g, h)

RETURNS (yn);

Inputs	|	Output

A	B	C	D	E	F	G	H	|	YN

H	H	H	H	X	X	X	X	|	L

X	X	X	X	H	H	H	H	|	L

All Others	|	H

See also:

Macrofunctions (by function)

SSI Functions


7456 (Frequency Divider)

Frequency Divider

Default Signal Levels:	GND--CLR

VCC--CLKA, CLKB

Function Prototype:

FUNCTION 7456 (clr, clkb, clka)

RETURNS (qc, qb, qa);

Count	|	Inputs	|	Outputs

|	CLR	CLKA	|	QA

X	|	L	X	|	L

1	|	H	|	L

2	|	H	|	L

3	|	H	|	L

4	|	H	|	L

5	|	|	H

|	|	Repeat from 1

Count	|	Inputs	|	Outputs

|	CLR	CLKB	|	QB	QC

X	|	L	X	|	L	L

1	|	H	|	L	L

2	|	H	|	L	L

3	|	H	|	L	L

4	|	H	|	L	L

5	|	|	H	L

6	|	|	Repeat from 1	H

7	|	|	H

8	|	|	H

9	|	|	H

10	|	|	H

|	|	Repeat from 1

See also:

Frequency Divider Macrofunctions

Macrofunctions (by function)


7457 (Frequency Divider)

Frequency Divider

Default Signal Levels:	GND--CLR

VCC--CLKA, CLKB

Function Prototype:

FUNCTION 7457 (clr, clkb, clka)

RETURNS (qc, qb, qa);

Count	|	Inputs	|	Outputs

|	CLR	CLKA	|	QA

X	|	L	X	|	L

1	|	H	|	L

2	|	H	|	L

3	|	H	|	L

4	|	H	|	H

5	|	H	|	H

6	|	H	|	H

|	|	Repeat from 1

Count	|	Inputs	|	Outputs

|	CLR	CLKB	|	QB	QC

X	|	L	X	|	L	L

1	|	H	|	L	L

2	|	H	|	L	L

3	|	H	|	L	L

4	|	H	|	L	L

5	|	H	|	H	L

6	|	H	|	Repeat from 1	H

7	|	H	|	H

8	|	H	|	H

9	|	H	|	H

10	|	H	|	H

|	|	Repeat from 1

See also:

Frequency Divider Macrofunctions

Macrofunctions (by function)


7464 (SSI Function)

4-2-3-2 Input AND-OR-INVERT Gate

Default Signal Levels:	VCC--all input pins

Function Prototype:

FUNCTION 7464 (a, b, c, d, e, f, g, h, i, j, k)

RETURNS (y);

Inputs	|	Output

A	B	C	D	E	F	G	H	I	J	K	|	Y

H	H	H	H	X	X	X	X	X	X	X	|	L

X	X	X	X	H	H	X	X	X	X	X	|	L

X	X	X	X	X	X	H	H	H	X	X	|	L

X	X	X	X	X	X	X	X	X	H	H	|	L

All Others	|	H

See also:

Macrofunctions (by function)

SSI Functions


7468 (Counter)

Dual Decade Counter

Default Signal Levels:	VCC--all input pins

Function Prototype:

FUNCTION 7468 (1clk1, 1clk2, 1clrn, 2clk, 2clrn)

RETURNS (1qd, 1qc, 1qb, 1qa, 2qd, 2qc, 2qb, 2qa);

Inputs	|	Outputs

CLRN	CLK	|	Q

L	X	|	L

H	|	Count*

*	Counter 2 is a BCD Counter only. Counter 1 can have the configurations described in the following table.

Possible Counting Configurations:

Decade: QA connected to CLK	|	Bi-Quinary: QD connected to CLK1

Count	QD	QC	QB	QA	|	Count	QD	QC	QB	QA

0	L	L	L	L	|	0	L	L	L	L

1	L	L	L	H	|	1	L	L	L	H

2	L	L	H	L	|	2	L	L	H	L

3	L	L	H	H	|	3	L	L	H	H

4	L	H	L	L	|	4	L	H	L	L

5	L	H	L	H	|	5	H	L	L	L

6	L	H	H	L	|	6	H	L	L	H

7	L	H	H	H	|	7	H	L	H	L

8	H	L	L	L	|	8	H	L	H	H

9	H	L	L	H	|	9	H	H	L	L

See also:

Counter Macrofunctions

Macrofunctions (by function)


7469 (Counter)

Dual Binary Counter

Default Signal Levels:	VCC--all input pins

Function Prototype:

FUNCTION 7469 (1clk1, 1clk2, 1clrn, 2clk, 2clrn)

RETURNS (1qd, 1qc, 1qb, 1qa, 2qd, 2qc, 2qb, 2qa);

Inputs	|	Outputs

CLRN	CLK	|	Q

L	X	|	L

H	|	Count*

*	1QA is connected to 1CLK2 for binary count.

See also:

Counter Macrofunctions

Macrofunctions (by function)


7470 (Register)

AND-Gated JK Flipflop with Preset and Clear

Default Signal Levels:	GND--JN, KN, CLK

VCC--PRN, J1, J2, K1, K2, CLRN

Function Prototype:

FUNCTION 7470 (prn, clrn, clk, j1, j2, jn, k1, k2, kn)

RETURNS (q, qn);

Inputs	|	Outputs

PRN	CLRN	CLK	J*	K**	|	Q	QN

L	H	X	X	X	|	H	L

H	L	X	X	X	|	L	H

L	L	X	X	X	|	Illegal

H	H	L	L	|	Qo***	/Qo

H	H	H	L	|	H	L

H	H	L	H	|	L	H

H	H	H	H	|	Toggle

H	H	L	X	X	|	Qo***	/Qo

*	J = J1 & J2 & JN

**	K = K1 & K2 & KN

***	Qo = level of Q before Clock pulse

If inputs J and K are not used, they must be GND.

See also:

Macrofunctions (by function)

Register Macrofunctions


7471 (Register)

JK Flipflop with Preset

Default Signal Levels:	GND--CLK

VCC--PRN, J1A, J1B, J2A, J2B, K1A, K1B, K2A, K2B

Function Prototype:

FUNCTION 7471 (prn, clk, j1a, j1b, j2a, j2b, k1a, k1b, k2a, k2b)

RETURNS (q, qn);

Inputs	|	Outputs

PRN	CLK	J*	K**	|	Q	QN

L	X	X	X	|	H	L

H	L	X	X	|	Qo***	/Qo

H	L	L	|	Qo***	/Qo

H	H	L	|	H	L

H	L	H	|	L	H

H	H	H	|	Toggle

*	J = (J1A & J1B) + (J2A & J2B)

**	K = (K1A & K1B) + (K2A & K2B)

***	Qo = level of Q before Clock pulse

See also:

Macrofunctions (by function)

Register Macrofunctions


7472 (Register)

AND-Gated JK Flipflop with Preset and Clear

Default Signal Levels:	GND--CLK

VCC--PRN, J1, J2, J3, K1, K2, K3, CLRN

Function Prototype:

FUNCTION 7472 (prn, clrn, clk, j1, j2, j3, k1, k2, k3)

RETURNS (q, qn);

Inputs	|	Outputs

PRN	CLRN	CLK	J*	K**	|	Q	QN

L	H	X	X	X	|	H	L

H	L	X	X	X	|	LH

L	L	X	X	X	|	Illegal

H	H	L	X	X	|	Qo***	/Qo

H	H	L	L	|	Qo***	/Qo

H	H	L	H	|	L	H

H	H	H	L	|	H	L

H	H	H	H	|	Toggle

*	J = J1 & J2 & J3

**	K = K1 & K2 & K3

***	Qo = level of Q before clock pulse

See also:

Macrofunctions (by function)

Register Macrofunctions


7473 (Register)

Dual JK Flipflop with Clear

Default Signal Levels:	VCC--all input pins

Function Prototype:

FUNCTION 7473 (1clrn, 1clk, 1j, 1k, 2clrn, 2clk, 2j, 2k)

RETURNS (1q, 1qn, 2q, 2qn);

Inputs	|	Outputs

CLRN	CLK	J	K	|	Q	QN

L	X	X	X	|	L	H

H	L	X	X	|	Qo*	/Qo

H	L	L	|	Qo*	/Qo

H	H	L	|	H	L

H	L	H	|	L	H

H	H	H	|	Toggle

*	Qo = level of Q before Clock pulse

See also:

Macrofunctions (by function)

Register Macrofunctions


7474 (Register)

Dual D-Type Flipflop with Asynchronous Preset and Asynchronous Clear

Default Signal Levels:	GND--1D, 1CLK, 2D, 2CLK

VCC--1PRN, 1CLRN, 2PRN, 2CLRN

Function Prototype:

FUNCTION 7474 (1prn, 1clrn, 1clk, 1d, 2prn, 2clrn, 2clk, 2d)

RETURNS (1q, 1qn, 2q, 2qn);

Inputs	|	Outputs

PRN	CLRN	CLK	D	|	Q	QN

L	H	X	X	|	H	L

H	L	X	X	|	L	H

L	L	X	X	|	Illegal

H	H	L	|	L	H

H	H	H	|	H	L

H	H	L	X	|	Qo*	/Qo

*	Qo = level of Q before clock pulse

See also:

Macrofunctions (by function)

Register Macrofunctions


7475 (Latch)

4-Bit Bistable Latch

Default Signal Levels:	GND--1D, 2D, 3D, 4D

VCC--E12, E34

Function Prototype:

FUNCTION 7475 (1d, 2d, 3d, 4d, e12, e34)

RETURNS (1q, 1qn, 2q, 2qn, 3q, 3qn, 4q, 4qn);

Inputs	|	Outputs

D	E	|	Q	QN

L	H	|	L	H

H	H	|	H	L

X	L	|	Qo*	/Qo

*	Qo = level of Q before [image] transition on E

See also:

Latch Macrofunctions

Macrofunctions (by function)


7476 (Register)

Dual JK Flipflop with Asynchronous Preset and Asynchronous Clear

Default Signal Levels:	GND--1J, 1K, 1CLK, 2J, 2K, 2CLK

VCC--1PRN, 1CLRN, 2PRN, 2CLRN

Function Prototype:

FUNCTION 7476 (1prn, 1clrn, 1clk, 1j, 1k, 2prn, 2clrn, 2clk, 2j, 2k)

RETURNS (1q, 1qn, 2q, 2qn);

Inputs	|	Outputs

PRN	CLRN	CLK	J	K	|	Q	QN

L	H	X	X	X	|	H	L

H	L	X	X	X	|	L	H

L	L	X	X	X	|	Illegal

H	H	L	X	X	|	Qo*	/Qo

H	H	L	L	|	Qo*	/Qo

H	H	H	L	|	H	L

H	H	L	H	|	L	H

H	H	H	H	|	Toggle

*	Qo = level of Q before Clock pulse

See also:

Macrofunctions (by function)

Register Macrofunctions


7477 (Latch)

4-Bit Bistable Latch

Default Signal Levels:	VCC--all input pins

Function Prototype:

FUNCTION 7477 (1d, 2d, 3d, 4d, e12, e34)

RETURNS (1q, 2q, 3q, 4q);

Inputs	|	Outputs

D	E	|	Q

L	H	|	L

H	H	|	H

X	L	|	Qo*

*	Qo = level of Q before [image] transition on E

See also:

Latch Macrofunctions

Macrofunctions (by function)


7478 (Register)

Dual JK Flipflop with Asynchronous Preset, Common Clear, and Common Clock

Default Signal Levels:	GND--1J, 1K, 2J, 2K, CLK

VCC--1PRN, 2PRN, CLRN

Function Prototype:

FUNCTION 7478 (clrn, 1prn, 1j, 1k, 2prn, 2j, 2k, clk))

RETURNS (1q, 1qn, 2q, 2qn);

Inputs	|	Outputs

PRN	CLRN	CLK	J	K	|	Q	QN

L	H	X	X	X	|	H	L

H	L	X	X	X	|	L	H

L	L	X	X	X	|	Illegal

H	H	L	L	|	Qo*	/Qo

H	H	H	L	|	H	L

H	H	L	H	|	L	H

H	H	H	H	|	Toggle

H	H	L	X	X	|	Qo*	/Qo

*	Qo = level of Q before Clock pulse

See also:

Macrofunctions (by function)

Register Macrofunctions


7480 (Full Adder)

Gated Full Adder

Default Signal Levels:	GND--CN0, A1, A2, B1, B2

VCC--AS, AC, BS, BC

Function Prototype:

FUNCTION 7480 (cn0, a1, a2, as, ac, b1, b2, bs, bc)

RETURNS (cn1n, sum, sumn);

Inputs	|	Outputs

CN0	A*	B**	|	CN1N	SUM	SUMN

L	L	L	|	H	L	H

L	L	H	|	H	H	L

L	H	L	|	H	H	L

L	H	H	|	L	L	H

H	L	L	|	H	H	L

H	L	H	|	L	L	H

H	H	L	|	L	L	H

H	H	H	|	L	H	L

*	A = /AC + /AS + A1 & A2

**	B = /BC + /BS + B1 & B2

See also:

Adder Macrofunctions

Macrofunctions (by function)


7482 (Full Adder)

2-Bit Binary Full Adder

Default Signal Levels:	VCC--all input pins

Function Prototype:

FUNCTION 7482 (a[2..1], b[2..1], c0)

RETURNS (sum[2..1], c2);

Inputs	|	Outputs

|	When C0 = L	|	When C0 = H

A1	B1	A2	B2	|	SUM1	SUM2	C2	|	SUM1	SUM2	C2

L	L	L	L	|	L	L	L	|	H	L	L

H	L	L	L	|	H	L	L	|	L	H	L

L	H	L	L	|	H	L	L	|	L	H	L

H	H	L	L	|	L	H	L	|	H	H	L

L	L	H	L	|	L	H	L	|	H	H	L

H	L	H	L	|	H	H	L	|	L	L	H

L	H	H	L	|	H	H	L	|	L	L	H

H	H	H	L	|	L	L	H	|	H	L	H

L	L	L	H	|	L	H	L	|	H	H	L

H	L	L	H	|	H	H	L	|	L	L	H

L	H	L	H	|	H	H	L	|	L	L	H

H	H	L	H	|	L	L	H	|	H	L	H

L	L	H	H	|	L	L	H	|	H	L	H

H	L	H	H	|	H	L	H	|	L	H	H

L	H	H	H	|	H	L	H	|	L	H	H

H	H	H	H	|	L	H	H	|	H	H	H

See also:

Adder Macrofunctions

Macrofunctions (by function)


7483 (Full Adder)

4-Bit Binary Full Adder with Fast Carry

Default Signal Levels:	GND--all input pins

Function Prototype:

FUNCTION 7483 (a[4..1], b[4..1], c0)

RETURNS (s[4..1], c4);

Inputs	|	Outputs

|	When C0 = L	|	When C0 = H

|	[When C2 = L]	|	[When C2 = H]

A1[A3]	B1[B3]	A2[A4]	B2[B4]	|	S1[S3]	S2[S4]	C2[C4]	|	S1[S3]	S2[S4]	C2[C4]

L	L	L	L	|	L	L	L	|	H	L	L

H	L	L	L	|	H	L	L	|	L	H	L

L	H	L	L	|	H	L	L	|	L	H	L

H	H	L	L	|	L	H	L	|	H	H	L

L	L	H	L	|	L	H	L	|	H	H	L

H	L	H	L	|	H	H	L	|	L	L	H

L	H	H	L	|	H	H	L	|	L	L	H

H	H	H	L	|	L	L	H	|	H	L	H

L	L	L	H	|	L	H	L	|	H	H	L

H	L	L	H	|	H	H	L	|	L	L	H

L	H	L	H	|	H	H	L	|	L	L	H

H	H	L	H	|	L	L	H	|	H	L	H

L	L	H	H	|	L	L	H	|	H	L	H

H	L	H	H	|	H	L	H	|	L	H	H

L	H	H	H	|	H	L	H	|	L	H	H

H	H	H	H	|	L	H	H	|	H	H	H

Input conditions at A1, B1, B2, C0 are used to determine outputs S1 and S2 and the value of internal carry C2. The values at C2, A3, B3, A4, B4 are then used to determine outputs S3, S4, C4.

See also:

Adder Macrofunctions

Macrofunctions (by function)


7485 (Comparator)

4-Bit Magnitude Comparator Note

Default Signal Levels:	VCC--all input pins

Function Prototype:

FUNCTION 7485 (a[3..0], b[3..0], agbi, albi, aebi)

RETURNS (agbo, albo, aebo);

Comparing Inputs	|	Cascading Inputs	|	Outputs

A3, B3	A2, B2	A1, B1	A0, B0	|	AGBI	ALBI	AEBI	|	AGBO	ALBO	AEBO

A3>B3	X	X	X	|	X	X	X	|	H	L	L

A3<B3	X	X	X	|	X	X	X	|	L	H	L

A3=B3	A2>B2	X	X	|	X	X	X	|	H	L	L

A3=B3	A2<B2	X	X	|	X	X	X	|	L	H	L

A3=B2	A2=B2	A1>B1	X	|	X	X	X	|	H	L	L

A3=B3	A2=B2	A1<B1	X	|	X	X	X	|	L	H	L

A3=B3	A2=B2	A1=B1	A0>B0	|	X	X	X	|	H	L	L

A3=B3	A2=B2	A1=B1	A0<B0	|	X	X	X	|	L	H	L

A3=B3	A2=B2	A1=B1	A0=B0	|	H	L	L	|	H	L	L

A3=B3	A2=B2	A1=B1	A0=B0	|	L	H	L	|	L	H	L

A3=B3	A2=B2	A1=B1	A0=B0	|	L	L	H	|	L 	L	H

A3=B3	A2=B2	A1=B1	A0=B0	|	X	X	H	|	L	L	H

A3=B3	A2=B2	A1=B1	A0=B0	|	H	H	L	|	L	L	L

A3=B3	A2=B2	A1=B1	A0=B0	|	L	L	L	|	H	H	L

See also:

Comparator Macrofunctions

Macrofunctions (by function)


7486 (SSI Function)

XOR Gate

Default Signal Levels:	VCC--all input pins

Function Prototype:

FUNCTION 7486 (2, 3)

RETURNS (1);

Inputs	|	Output

A	B	|	OUT

L	L	|	L

L	H	|	H

H	L	|	H

H	H	|	L

See also:

Macrofunctions (by function)

SSI Functions


7487 (True/Complement I/O Element)

4-Bit True/Complement I/O Element

Default Signal Levels:	GND--A1, A2, A3, A4, B

VCC--C

Function Prototype:

FUNCTION 7487 (a[4..1], b, c)

RETURNS (y[4..1]);

Control Inputs	|	Outputs

B	C	|	Y1	Y2	Y3	Y4

L	L	|	/A1	/A2	/A3	/A4

L	H	|	A1	A2	A3	A4

H	L	|	H	H	H	H

H	H	|	L	L	L	L

See also:

Macrofunctions (by function)

True/Complement I/O Element Macrofunctions


7490 (Counter)

Decade or Binary Counter with Clear and Set-to-9

Default Signal Levels:	GND--SET9A, SET9B, CLRA, CLRB

VCC--CLKA, CLKB

Function Prototype:

FUNCTION 7490 (set9a, set9b, clra, clrb, clka, clkb)

RETURNS (qd, qc, qb, qa);

Inputs	|	Outputs

CLR*	SET**	CLK	|	QD	QC	QB	QA

H	L	X	|	L	L	L	L

L	H	X	|	H	L	L	H

H	H	X	|	Illegal

L	L	|	Count

*	CLR = CLRA & CLRB

** 	SET = SET9A & SET9B

Possible Counting Configurations:

DECADE: QA connected to CLKB

Count	QD	QC	QB	QA

0	L	L	L	L

1	L	L	L	H

2	L	L	H	L

3	L	L	H	H

4	L	H	L	L

5	L	H	L	H

6	L	H	H	L

7	L	H	H	H

8	H	L	L	L

9	H	L	L	H

BI-QUINARY: QD connected to CLKA

Count	QD	QC	QB	QA

0	L	L	L	L

1	L	L	L	H

2	L	L	H	L

3	L	L	H	H

4	L	H	L	L

5	H	L	L	L

6	H	L	L	H

7	H	L	H	L

8	H	L	H	H

9	H	H	L	L

Binary: This mode can be an inefficient implementation of a binary counter and is not recommended by Altera. Refer to AB88 (Optimizing Counter Design for Altera EPLDs) for more information. For a four bit counter with similar features, use the 74161 or 4COUNT macrofunction.

See also:

Counter Macrofunctions

Macrofunctions (by function)

Recommended reading:

AB88 (Optimizing Counter Design for Altera EPLDs)


7411 (SSI Function)

AND3 Gate

Default Signal Levels:	VCC--all input pins

Function Prototype:

FUNCTION 7411 (2, 3, 4)

RETURNS (1);

Inputs	|	Output

A	B	C	|	OUT

L	L	L	|	L

H	L	L	|	L

L	H	L	|	L

H	H	L	|	L

L	L	H	|	L

H	L	H	|	L

L	H	H	|	L

H	H	H	|	H

See also:

Macrofunctions (by function)

SSI Functions


7420 (SSI Function)

NAND4 Gate

Default Signal Levels:	VCC--all input pins

Function Prototype:

FUNCTION 7420 (2, 3, 4, 5)

RETURNS (1);

Inputs	|	Output

A	B	C	D	|	OUT

L	X	X	X	|	H

X	L	X	X	|	H

X	X	L	X	|	H

X	X	X	L	|	H

H	H	H	H	|	L

See also:

Macrofunctions (by function)

SSI Functions


7421 (SSI Function)

AND4 Gate

Default Signal Levels:	VCC--all input pins

Function Prototype:

FUNCTION 7421 (2, 3, 4, 5)

RETURNS (1);

Inputs	|	Output

A	B	C	D	|	OUT

L	X	X	X	|	L

X	L	X	X	|	L

X	X	L	X	|	L

X	X	X	L	|	L

H	H	H	H	|	H

See also:

Macrofunctions (by function)

SSI Functions


7423 (SSI Function)

Dual 4-Input NOR Gate with Strobe

Default Signal Levels:	VCC--all input pins

Function Prototype:

FUNCTION 7423 (1a, 1b, 1c, 1d, 1g, 2a, 2b, 2c, 2d, 2g)

RETURNS (1y, 2y);

Inputs	|	Outputs

A	B	C	D	G	|	Y

H	X	X	X	H	|	L

X	H	X	X	H	|	L

X	X	H	X	H	|	L

X	X	X	H	H	|	L

L	L	L	L	X	|	H

X	X	X	X	L	|	H

See also:

Macrofunctions (by function)

SSI Functions


7425 (SSI Function)

Dual 4-Input NOR Gate with Strobe

Default Signal Levels:	VCC--all input pins

Function Prototype:

FUNCTION 7425 (1a, 1b, 1c, 1d, 1g, 2a, 2b, 2c, 2d, 2g)

RETURNS (1y, 2y);

Inputs	|	Outputs

A	B	C	D	G	|	Y

H	X	X	X	H	|	L

X	H	X	X	H	|	L

X	X	H	X	H	|	L

X	X	X	H	H	|	L

L	L	L	L	X	|	H

X	X	X	X	L	|	H

See also:

Macrofunctions (by function)

SSI Functions


7427 (SSI Function)

NOR3 Gate

Default Signal Levels:	GND--all input pins

Function Prototype:

FUNCTION 7427 (2, 3, 4)

RETURNS (1);

Inputs	|	Output

A	B	C	|	OUT

H	X	X	|	L

X	H	X	|	L

X	X	H	|	L

L	L	L	|	H

See also:

Macrofunctions (by function)

SSI Functions


7428 (SSI Function)

Quad 2-Input Positive NOR Gate

Default Signal Levels:	VCC--all input pins

Function Prototype:

FUNCTION 7428 (a1, b1, a2, b2, a3, b3, a4, b4)

RETURNS (y1, y2, y3, y4);

Inputs	|	Output

A	B	|	OUT

H	X	|	L

X	H	|	L

L	L	|	H

See also:

Macrofunctions (by function)

SSI Functions


7430 (SSI Function)

NAND8 Gate

Default Signal Levels:	VCC--all input pins

Function Prototype:

FUNCTION 7430 (2, 3, 4, 5, 6, 7, 8, 9)

RETURNS (1);

Inputs	|	Output

A	B	C	D	E	F	G	H	|	OUT

L	X	X	X	X	X	X	X	|	H

X	L	X	X	X	X	X	X	|	H

X	X	L	X	X	X	X	X	|	H

X	X	X	L	X	X	X	X	|	H

X	X	X	X	L	X	X	X	|	H

X	X	X	X	X	L	X	X	|	H

X	X	X	X	X	X	L	X	|	H

X	X	X	X	X	X	X	L	|	H

H	H	H	H	H	H	H	H	|	L

See also:

Macrofunctions (by function)

SSI Functions


7432 (SSI Function)

OR2 Gate

Default Signal Levels:	GND--all input pins

Function Prototype:

FUNCTION 7432 (2, 3)

RETURNS (1);

Inputs	|	Output

A	B	|	OUT

L	L	|	L

H	L	|	H

L	H	|	H

H	H	|	H

See also:

Macrofunctions (by function)

SSI Functions


7437 (SSI Function)

Quad 2-Input Positive NAND Gate

Default Signal Levels:	VCC--all input pins

Function Prototype:

FUNCTION 7437 (1a, 1b, 2a, 2b, 3a, 3b, 4a, 4b)

RETURNS (1y, 2y, 3y, 4y);

Inputs	|	Output

A	B	|	OUT

H	H	|	L

L	X	|	H

X	L	|	H

See also:

Macrofunctions (by function)

SSI Functions


7440 (SSI Function)

Dual 4-Input Positive NAND Gate

Default Signal Levels:	VCC--all input pins

Function Prototype:

FUNCTION 7440 (1a, 1b, 1c, 1d, 2a, 2b, 2c, 2d)

RETURNS (1y, 2y);

Inputs	|	Output

A	B	C	D	|	Y

H	H	H	H	|	L

L	X	X	X	|	H

X	L	X	X	|	H

X	X	L	X	|	H

X	X	X	L	|	H

See also:

Macrofunctions (by function)

SSI Functions


7442 (Decoder)

1-Line-to-10-Line BCD-to-Decimal Decoder

Default Signal Levels:	GND--all input pins

Function Prototype:

FUNCTION 7442 (d, c, b, a)

RETURNS (o0n, o1n, o2n, o3n, o4n, o5n, o6n, o7n, o8n, o9n);

No.	|	BCD Inputs	|	Decimal Outputs

|	D	C	B	A	|	0	1	2	3	4	5	6	7	8	9

0	|	L	L	L	L	|	L	H	H	H	H	H	H	H	H	H

1	|	L	L	L	H	|	H	L	H	H	H	H	H	H	H	H

2	|	L	L	H	L	|	H	H	L	H	H	H	H	H	H	H

3	|	L	L	H	H	|	H	H	H	L	H	H	H	H	H	H

4	|	L	H	L	L	|	H	H	H	H	L	H	H	H	H	H

5	|	L	H	L	H	|	H	H	H	H	H	L	H	H	H	H

6	|	L	H	H	L	|	H	H	H	H	H	H	L	H	H	H

7	|	L	H	H	H	|	H	H	H	H	H	H	H	L	H	H

8	|	H	L	L	L	|	H	H	H	H	H	H	H	H	L	H

9	|	H	L	L	H	|	H	H	H	H	H	H	H	H	H	L

I	|	H	L	H	L	|	H	H	H	H	H	H	H	H	H	H

N	|	H	L	H	H	|	H	H	H	H	H	H	H	H	H	H

V	|	H	H	L	L	|	H	H	H	H	H	H	H	H	H	H

A	|	H	H	L	H	|	H	H	H	H	H	H	H	H	H	H

L	|	H	H	H	L	|	H	H	H	H	H	H	H	H	H	H

I	|	H	H	H	H	|	H	H	H	H	H	H	H	H	H	H

D	|	|

See also:

Decoder Macrofunctions

Macrofunctions (by function)


7443 (Decoder)

Excess-3-to-Decimal Decoder

Default Signal Levels:	GND--all input pins

Function Prototype:

FUNCTION 7443 (d, c, b, a)

RETURNS (o0n, o1n, o2n, o3n, o4n, o5n, o6n, o7n, o8n, o9n);

No.	|	Excess-3 Inputs	|	Decimal Outputs

|	D	C	B	A	|	0	1	2	3	4	5	6	7	8	9

0	|	L	L	H	H	|	L	H	H	H	H	H	H	H	H	H

1	|	L	H	L	L	|	H	L	H	H	H	H	H	H	H	H

2	|	L	H	L	H	|	H	H	L	H	H	H	H	H	H	H

3	|	L	H	H	L	|	H	H	H	L	H	H	H	H	H	H

4	|	L	H	H	H	|	H	H	H	H	L	H	H	H	H	H

5	|	H	L	L	L	|	H	H	H	H	H	L	H	H	H	H

6	|	H	L	L	H	|	H	H	H	H	H	H	L	H	H	H

7	|	H	L	H	L	|	H	H	H	H	H	H	H	L	H	H

8	|	H	L	H	H	|	H	H	H	H	H	H	H	H	L	H

9	|	H	H	L	L	|	H	H	H	H	H	H	H	H	H	L

I	|	H	H	L	H	|	H	H	H	H	H	H	H	H	H	H

N	|	H	H	H	L	|	H	H	H	H	H	H	H	H	H	H

V	|	H	H	H	H	|	H	H	H	H	H	H	H	H	H	H

A	|	L	L	L	L	|	H	H	H	H	H	H	H	H	H	H

L	|	L	L	L	H	|	H	H	H	H	H	H	H	H	H	H

I	|	L	L	H	L	|	H	H	H	H	H	H	H	H	H	H

D	|	|

See also:

Decoder Macrofunctions

Macrofunctions (by function)


7444 (Decoder)

Excess-3-Gray-to-Decimal Decoder

Default Signal Levels:	GND--all input pins

Function Prototype:

FUNCTION 7444 (d, c, b, a)

RETURNS (o0n, o1n, o2n, o3n, o4n, o5n, o6n, o7n, o8n, o9n);

No.	|	Excess-3 Gray Inputs	|	Decimal Outputs

|	D	C	B	A	|	0	1	2	3	4	5	6	7	8	9

0	|	L	L	H	L	|	L	H	H	H	H	H	H	H	H	H

1	|	L	H	H	L	|	H	L	H	H	H	H	H	H	H	H

2	|	L	H	H	H	|	H	H	L	H	H	H	H	H	H	H

3	|	L	H	L	H	|	H	H	H	L	H	H	H	H	H	H

4	|	L	H	L	L	|	H	H	H	H	L	H	H	H	H	H

5	|	H	H	L	L	|	H	H	H	H	H	L	H	H	H	H

6	|	H	H	L	H	|	H	H	H	H	H	H	L	H	H	H

7	|	H	H	H	H	|	H	H	H	H	H	H	H	L	H	H

8	|	H	H	H	L	|	H	H	H	H	H	H	H	H	L	H

9	|	H	L	H	L	|	H	H	H	H	H	H	H	H	H	L

I	|	H	L	H	H	|	H	H	H	H	H	H	H	H	H	H

N	|	H	L	L	H	|	H	H	H	H	H	H	H	H	H	H

V	|	H	L	L	L	|	H	H	H	H	H	H	H	H	H	H

A	|	L	L	L	L	|	H	H	H	H	H	H	H	H	H	H

L	|	L	L	L	H	|	H	H	H	H	H	H	H	H	H	H

I	|	L	L	H	H	|	H	H	H	H	H	H	H	H	H	H

D	|	|

See also:

Decoder Macrofunctions

Macrofunctions (by function)


7445 (Decoder)

BCD-to-Decimal Decoder

Default Signal Levels:	GND--all input pins

Function Prototype:

FUNCTION 7445 (d, c, b, a)

RETURNS (o0n, o1n, o2n, o3n, o4n, o5n, o6n, o7n, o8n, o9n);

No.	|	BCD Inputs	|	Decimal Outputs

|	D	C	B	A	|	0	1	2	3	4	5	6	7	8	9

0	|	L	L	L	L	|	L	H	H	H	H	H	H	H	H	H

1	|	L	L	L	H	|	H	L	H	H	H	H	H	H	H	H

2	|	L	L	H	L	|	H	H	L	H	H	H	H	H	H	H

3	|	L	L	H	H	|	H	H	H	L	H	H	H	H	H	H

4	|	L	H	L	L	|	H	H	H	H	L	H	H	H	H	H

5	|	L	H	L	H	|	H	H	H	H	H	L	H	H	H	H

6	|	L	H	H	L	|	H	H	H	H	H	H	L	H	H	H

7	|	L	H	H	H	|	H	H	H	H	H	H	H	L	H	H

8	|	H	L	L	L	|	H	H	H	H	H	H	H	H	L	H

9	|	H	L	L	H	|	H	H	H	H	H	H	H	H	H	L

I	|	H	L	H	L	|	H	H	H	H	H	H	H	H	H	H

N	|	H	L	H	H	|	H	H	H	H	H	H	H	H	H	H

V	|	H	H	L	L	|	H	H	H	H	H	H	H	H	H	H

A	|	H	H	L	H	|	H	H	H	H	H	H	H	H	H	H

L	|	H	H	H	L	|	H	H	H	H	H	H	H	H	H	H

I	|	H	H	H	H	|	H	H	H	H	H	H	H	H	H	H

D	|	|

See also:

Decoder Macrofunctions

Macrofunctions (by function)


7446 (Decoder)

BCD-to-7-Segment Decoder

Default Signal Levels:	GND--A, B, C, D

VCC--LTN, RBIN, BIN

Function Prototype:

FUNCTION 7446 (ltn, rbin, d, c, b, a, bin)

RETURNS (oa, ob, oc, od, oe, 'of', og, rbon);

Decimal	|	|	|

or	|	Inputs	|	Outputs	|	Notes

Function	|	|	|

|	LTN	RBIN	D	C	B	A	BIN	|	OA	OB	OC	OD	OE	OF	OG	RBON	|

0	|	H	H	L	L	L	L	H	|	L	L	L	L	L	L	H	H	|	*

1	|	H	X	L	L	L	H	H	|	H	L	L	H	H	H	H	H	|

2	|	H	X	L	L	H	L	H	|	L	L	H	L	L	H	L	H	|

3	|	H	X	L	L	H	H	H	|	L	L	L	L	H	H	L	H	|

4	|	H	X	L	H	L	L	H	|	H	L	L	H	H	L	L	H	|	*

5	|	H	X	L	H	L	H	H	|	L	H	L	L	H	L	L	H	|

6	|	H	X	L	H	H	L	H	|	H	H	L	L	L	L	L	H	|

7	|	H	X	L	H	H	H	H	|	L	L	L	H	H	H	H	H	|

8	|	H	X	H	L	L	L	H	|	L	L	L	L	L	L	L	H	|	*

9	|	H	X	H	L	L	H	H	|	L	L	L	H	H	L	L	H	|

10	|	H	X	H	L	H	L	H	|	H	H	H	L	L	H	L	H	|

11	|	H	X	H	L	H	H	H	|	H	H	L	L	H	H	L	H	|

12	|	H	X	H	H	L	L	H	|	H	L	H	H	H	L	L	H	|	*

13	|	H	X	H	H	L	H	H	|	L	H	H	L	H	L	L	H	|

14	|	H	X	H	H	H	L	H	|	H	H	H	L	L	L	L	H	|

15	|	H	X	H	H	H	H	H	|	H	H	H	H	H	H	H	H	|

BI	|	X	X	X	X	X	X	L	|	H	H	H	H	H	H	H	X	|	**

RBI	|	H	L	L	L	L	L	X	|	H	H	H	H	H	H	H	L	|	***

LT	|	L	X	X	X	X	X	H	|	H	L	L	L	L	L	L	H	|	****

Notes:

*	The blanking input (BIN) must be held at a high logic level when output functions 0 through 15 are desired. RBIN must be held high if blanking of a decimal zero is not desired.

**	When a low logic level is applied directly to the blanking input (BIN), all segment outputs are high regardless of the level of any other input.

***	When RBIN, A, B, C, D are low and LTN is high, RBON goes low.

****	When LTN is held low, all outputs are low unless BIN is low.

See also:

Decoder Macrofunctions

Macrofunctions (by function)


7447 (Decoder)

BCD-to-7-Segment Decoder

Default Signal Levels:	GND--A, B, C, D

VCC--LTN, RBIN, BIN

Function Prototype:

FUNCTION 7447 (ltn, rbin, d, c, b, a, bin)

RETURNS (oa, ob, oc, od, oe, 'of', og, rbon);

Decimal	|	|	|

or	|	Inputs	|	Outputs	|	Notes

Function	|	|	|

|	LTN	RBIN	D	C	B	A	BIN	|	OA	OB	OC	OD	OE	OF	OG	RBON	|

0	|	H	H	L	L	L	L	H	|	L	L	L	L	L	L	H	H	|	*

1	|	H	X	L	L	L	H	H	|	H	L	L	H	H	H	H	H	|

2	|	H	X	L	L	H	L	H	|	L	L	H	L	L	H	L	H	|

3	|	H	X	L	L	H	H	H	|	L	L	L	L	H	H	L	H	|

4	|	H	X	L	H	L	L	H	|	H	L	L	H	H	L	L	H	|	*

5	|	H	X	L	H	L	H	H	|	L	H	L	L	H	L	L	H	|

6	|	H	X	L	H	H	L	H	|	H	H	L	L	L	L	L	H	|

7	|	H	X	L	H	H	H	H	|	L	L	L	H	H	H	H	H	|

8	|	H	X	H	L	L	L	H	|	L	L	L	L	L	L	L	H	|	*

9	|	H	X	H	L	L	H	H	|	L	L	L	H	H	L	L	H	|

10	|	H	X	H	L	H	L	H	|	H	H	H	L	L	H	L	H	|

11	|	H	X	H	L	H	H	H	|	H	H	L	L	H	H	L	H	|

12	|	H	X	H	H	L	L	H	|	H	L	H	H	H	L	L	H	|	*

13	|	H	X	H	H	L	H	H	|	L	H	H	L	H	L	L	H	|

14	|	H	X	H	H	H	L	H	|	H	H	H	L	L	L	L	H	|

15	|	H	X	H	H	H	H	H	|	H	H	H	H	H	H	H	H	|

BI	|	X	X	X	X	X	X	L	|	H	H	H	H	H	H	H	X	|	**

RBI	|	H	L	L	L	L	L	X	|	H	H	H	H	H	H	H	L	|	***

LT	|	L	X	X	X	X	X	H	|	L	L	L	L	L	L	L	H	|	****

Notes:

*	The blanking input (BIN) must be held at a high logic level when output functions 0 through 15 are desired. RBIN must be held high if blanking of a decimal zero is not desired.

**	When a low logic level is applied directly to the blanking input (BIN), all segment outputs are high regardless of the level of any other input.

***	When RBIN, A, B, C, D are low and LTN is high, RBON goes low.

****	When LTN is held low, all outputs are low unless BIN is low.

See also:

Decoder Macrofunctions

Macrofunctions (by function)


7448 (Decoder)

BCD-to-7-Segment Decoder

Default Signal Levels:	GND--A, B, C, D

VCC--LTN, RBIN, BIN

Function Prototype:

FUNCTION 7448 (ltn, rbin, d, c, b, a, bin)

RETURNS (oa, ob, oc, od, oe, 'of', og, rbon);

Decimal	|	|	|

or	|	Inputs	|	Outputs	|	Notes

Function	|	|	|

|	LTN	RBIN	D	C	B	A	BIN	|	OA	OB	OC	OD	OE	OF	OG	RBON	|

0	|	H	H	L	L	L	L	H	|	H	H	H	H	H	H	L	H	|	*

1	|	H	X	L	L	L	H	H	|	L	H	H	L	H	L	L	H	|

2	|	H	X	L	L	H	L	H	|	H	H	L	H	H	L	H	H	|

3	|	H	X	L	L	H	H	H	|	H	H	H	H	H	L	H	H	|

4	|	H	X	L	H	L	L	H	|	L	H	H	L	L	H	H	H	|	*

5	|	H	X	L	H	L	H	H	|	H	L	H	H	L	H	H	H	|

6	|	H	X	L	H	H	L	H	|	L	L	H	H	H	H	H	H	|

7	|	H	X	L	H	H	H	H	|	H	H	H	L	L	L	L	H	|

8	|	H	X	H	L	L	L	H	|	H	H	H	H	H	H	H	H	|	*

9	|	H	X	H	L	L	H	H	|	H	H	H	L	L	H	H	H	|

10	|	H	X	H	L	H	L	H	|	L	L	L	H	H	L	H	H	|

11	|	H	X	H	L	H	H	H	|	L	L	H	H	L	L	H	H	|

12	|	H	X	H	H	L	L	H	|	L	H	L	L	L	H	H	H	|	*

13	|	H	X	H	H	L	H	H	|	H	L	L	H	L	H	H	H	|

14	|	H	X	H	H	H	L	H	|	L	L	L	H	H	H	H	H	|

15	|	H	X	H	H	H	H	H	|	L	L	L	L	L	L	L	H	|

BI	|	X	X	X	X	X	X	L	|	L	L	L	L	L	L	L	X	|	**

RBI	|	H	L	L	L	L	L	X	|	L	L	L	L	L	L	L	L	|	***

LT	|	L	X	X	X	X	X	H	|	H	H	H	H	H	H	H	H	|	****

Notes:

*	The blanking input (BIN) must be held at a high logic level when output functions 0 through 15 are desired. RBIN must be held high if blanking of a decimal zero is not desired.

**	When a low logic level is applied directly to the blanking input (BIN), all segment outputs are low regardless of the level of any other input.

***	When RBIN, A, B, C, D are low and LTN is high, RBON goes low.

****	When LTN is held low, all outputs are high unless BIN is low.

See also:

Decoder Macrofunctions

Macrofunctions (by function)


7449 (Decoder)

BCD-to-7-Segment Decoder

Default Signal Levels:	GND--A, B, C, D

VCC--BIN

Function Prototype:

FUNCTION 7449 (d, c, b, a, bin)

RETURNS (oa, ob, oc, od, oe, 'of', og);

Decimal	|	|	|

or	|	Inputs	|	Outputs	|	Notes

Function	|	|	|

|	D	C	B	A	BIN	|	OA	OB	OC	OD	OE	OF	OG	|

0	|	L	L	L	L	H	|	H	H	H	H	H	H	L	|	*

1	|	L	L	L	H	H	|	L	H	H	L	L	L	L	|

2	|	L	L	H	L	H	|	H	H	L	H	H	L	H	|

3	|	L	L	H	H	H	|	H	H	H	H	L	L	H	|

4	|	L	H	L	L	H	|	L	H	H	L	L	H	H	|	*

5	|	L	H	L	H	H	|	H	L	H	H	L	H	H	|

6	|	L	H	H	L	H	|	L	L	H	H	H	H	H	|

7	|	L	H	H	H	H	|	H	H	H	L	L	L	L	|

8	|	H	L	L	L	H	|	H	H	H	H	H	H	H	|	*

9	|	H	L	L	H	H	|	H	H	H	L	L	H	H	|

10	|	H	L	H	L	H	|	L	L	L	H	H	L	H	|

11	|	H	L	H	H	H	|	L	L	H	H	L	L	H	|

12	|	H	H	L	L	H	|	L	H	L	L	L	H	H	|	*

13	|	H	H	L	H	H	|	H	L	L	H	L	H	H	|

14	|	H	H	H	L	H	|	L	L	L	H	H	H	H	|

15	|	H	H	H	H	H	|	L	L	L	L	L	L	L	|

BI	|	X	X	X	X	L	|	L	L	L	L	L	L	L	|	**

Notes:

*	The blanking input (BIN) must be held at a high logic level when output functions 0 through 15 are desired.

**	When a low logic level is applied directly to the blanking input (BIN), all segment outputs are  low regardless of the level of any other input.

See also:

Decoder Macrofunctions

Macrofunctions (by function)


7450 (SSI Function)

Dual 2-Wide 2-Input AND-OR-INVERT Gate

Default Signal Levels:	GND--1X

VCC--1A, 1B, 1C, 1D, 1XN, 2A, 2B, 2C, 2D

Function Prototype:

FUNCTION 7450 (1x, 1xn, 1a, 1b, 1c, 1d, 2a, 2b, 2c, 2d)

RETURNS (1yn, 2yn);

Inputs	|	Output

1X	1XN	1A	1B	1C	1D	|	1YN

L	H	H	H	X	X	|	L

L	H	X	X	H	H	|	L

L	H	All Others	|	H

H	X	X	X	X	X	|	H

X	L	X	X	X	X	|	H

Inputs	|	Output

2A	2B	2C	2D	|	2YN

H	H	X	X	|	H

X	X	H	H	|	H

All Others	|	L

See also:

SSI Functions

Macrofunctions (by function)


7451 (SSI Function)

Dual AND-OR-INVERT Gate

Default Signal Levels:	VCC--all input pins

This implementation is for the 74LS51.

Function Prototype:

FUNCTION 7451 (1a, 1b, 1c, 1d, 1e, 1f, 2a, 2b, 2c, 2d)

RETURNS (1yn, 2yn);

Inputs	|	Outputs

1A	1B	1C	1D	1E	1F	|	1YN

H	H	H	X	X	X	|	L

X	X	X	H	H	H	|	L

All Others	|	H

Inputs	|	Outputs

2A	2B	2C	2D	|	2YN

H	H	X	X	|	L

X	X	H	H	|	L

All Others	|	H

See also:

Macrofunctions (by function)

SSI Functions


MAX+PLUS II Help Contents
MAX+PLUS II ver. 6.0 Help Contents

Introduction to MAX+PLUS II	New Features in This Release

MAX+PLUS II Applications:

MAX+PLUS II Manager	Compiler

Hierarchy Display	Simulator

Graphic & Symbol Editors	Timing Analyzer

Text Editor	Programmer

Waveform Editor	Message Processor

Floorplan Editor

Other Information:

AHDL	Design Doctor

VHDL	Devices & Adapters

Third-Party Interfaces	Recommended Reading

Messages	How to Use MAX+PLUS II Help

Glossary	Contacting Altera

Guidelines for Workstation Users


Contacting Altera

You can contact Altera by telephone between the hours of 7:30 a.m. and 5:00 p.m. Pacific Time. Altera also maintains 24-hour file electronic mail, file transfer protocol (FTP) and World-Wide Web (WWW) sites, a literature fax-back service, a forum on CompuServe, and an electronic bulletin board service:

Name:	Service:

Applications Department	Technical assistance with Altera devices and development tools via telephone, fax, or email

Literature Department	Altera data sheets, data books, application notes and briefs, and other documents

Marketing Department	Information on ordering Altera products and services

Altera Express	Automated fax-back system for Altera documents

CompuServe Forum	Messages and interactive conferencing; access to library files

Customer Service Hotline	Help with non-technical customer service issues

Electronic bulletin board service (BBS)	Device and development tool information, electronic application notes and briefs, data sheet updates, customer newsletters, software utility programs, and file upload/download

Electronic mail address	Technical assistance with Altera devices and development tools

FTP Site	Application notes and briefs, recent quarterly newsletters, software utility programs, and file upload/download

Technical Support Hotline	Technical assistance with Altera devices and development tools

WWW Site	Product information, press releases, employment opportunities, and a corporate profile


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The style toc2col is used in this file and not in other files. Therefore, be sure to preserve this style when updating the style sheet in the future.

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MAX+PLUS II Introduction
Introduction

The MAX+PLUS II development software provides a complete design environment that easily adapts to your specific design needs. Regardless of whether you use a personal computer or a workstation, MAX+PLUS II ensures easy design entry, fast processing, and straightforward device programming.

MAX+PLUS II software is a fully integrated, architecture-independent package for designing logic with Altera programmable logic devices, including Classic, MAX 5000, MAX 7000, MAX 9000, FLEX 8000, and FLEX 8000M devices. (MAX+PLUS II also allows you to program FLASHlogic devices. Full support for FLASHlogic devices will be available in a future release of MAX+PLUS II.) MAX+PLUS II offers a full spectrum of logic design capabilities: three design entry methods for hierarchical designs; floorplan editing; powerful logic synthesis; design partitioning; functional, timing, and board-level-type linked simulation; detailed timing analysis; automatic error location; and device programming and verification. MAX+PLUS II also reads standard EDIF netlist files, VHDL netlist files, OrCAD Schematic Files, and Xilinx Netlist Format Files, and writes EDIF, VHDL, and Verilog netlist files for a convenient interface to other industry-standard CAE software. Show me

You can integrate existing designs created with Altera’s A+PLUS, SAM+PLUS, and MAX+PLUS (DOS) software packages into MAX+PLUS II designs. The MAX+PLUS II Compiler ensures that a design--called a project in MAX+PLUS II--fits into the device architecture in the most efficient way possible.

MAX+PLUS II Highlights

MAX+PLUS II offers a rich graphical user interface complemented with an illustrated, easy-to-use on-line help system. The complete MAX+PLUS II system includes ten fully integrated applications that take you through every step from design entry to device programming.

Many features and commands are shared by the different MAX+PLUS II applications, so that learning to use one application gives you a head start on learning to use the others. For example, you use identical commands in each MAX+PLUS II application to open files, to assign project devices, and to begin compiling the current project. The design editors in MAX+PLUS II--the Graphic, Text, and Waveform Editors--and the auxiliary editors--the Floorplan and Symbol Editors--also share numerous design entry tools and features. Each editor allows you to perform similar tasks, such as assigning a pin, in the same way.

You can easily combine different types of design files in a hierarchical project, choosing the design entry format that works best for each functional block. Over 300 primitives and macrofunctions, AHDL, and the built-in EDIF, VHDL, OrCAD, and Xilinx interfaces simplify design entry. Architecture-independent design entry gives you the freedom to create logic without worrying about the final device implementation.

You can work with different MAX+PLUS II applications at the same time. For example, you can open multiple design files and transfer information between them, while simultaneously compiling or simulating another project. You can view an entire hierarchy of design files and move smoothly from one hierarchical level to another. As you open a design file, MAX+PLUS II automatically starts the appropriate design editor.

The MAX+PLUS II Compiler lies at the heart of the MAX+PLUS II system, providing powerful design processing that you can customize to achieve the best possible silicon implementation of your project. Automatic error location and extensive documentation on error and warning messages make design modifications as simple as possible. You can create output files in a variety of formats for simulation, timing analysis, and device programming, including EDIF, Verilog, and VHDL files for use with other industry-standard CAE tools. At every step in the design process, MAX+PLUS II software makes it easy for you to focus on your design--not on how to use the software.

The superb integration of MAX+PLUS II software improves your efficiency and productivity, putting you in control of your logic design environment.

Where to Start

Altera offers a variety of information to help you create designs with MAX+PLUS II.

On-Line Help

With a click of the mouse, MAX+PLUS II Help supplies complete information on how to use each MAX+PLUS II application. Context-sensitive help is also available on all menu commands, dialog boxes, and keywords in text files, as well as on most items displayed in the application windows.

You can start learning more about MAX+PLUS II with the following on-line help:

MAX+PLUS II Help Contents provides access to all on-line help for MAX+PLUS II. In addition to a wealth of general information, you can find complete help on each MAX+PLUS II application. Application-specific help includes an introduction, as well as everything you need to know about basic tools, commands, procedures, and shortcuts.

Golden Rules summarize essential guidelines and recommendations for using each MAX+PLUS II application.

How to Use MAX+PLUS II Help describes the structure of MAX+PLUS II Help and how to use it to your best advantage.

Recommended Reading

Altera publishes a variety of useful literature on specific design applications and software and hardware features. The current Data Book, 1992 Applications Handbook, data sheets, application notes, application briefs, product information bulletins, and the quarterly Applications Engineering News & Views newsletter are all designed to help make logic design fast and easy. The following publications provide information to help you use MAX+PLUS II as a whole. See the complete Recommended Reading list for references to other useful publications.

AB98 (Configuring Your PC for MAX+PLUS II Software)

AB99 (Design Flow between Workstations & PCs)


MAX+PLUS II Golden Rules

The following golden rules are also accessible from the Help Contents and the <application name> Help submenu for each individual MAX+PLUS II application:

MAX+PLUS II Manager Golden Rules

Hierarchy Display Golden Rules

Graphic & Symbol Editor Golden Rules

Text Editor Golden Rules

Waveform Editor Golden Rules

Floorplan Editor Golden Rules

AHDL Golden Rules

VHDL Golden Rules

Compiler Golden Rules

Simulator Golden Rules

Timing Analyzer Golden Rules

Programmer Golden Rules

Message Processor Golden Rules


MAX+PLUS II--Context-Sensitive Help
Context-Sensitive Help

You have requested context-sensitive help on a screen region that is not specific to MAX+PLUS II. For information on the following screen items, consult Windows Program Manager Help or the Microsoft Windows User’s Guide:

Control-menu boxes

Maximize buttons

Menu bars

Minimize buttons

Scroll bars

Title bars

Window borders and corners

See also:

Getting Context-Sensitive Help


special MAX+PLUS II glossary entry
MAX+PLUS II

Multiple Array MatriX Programmable Logic User System II.


MAX+PLUS II Block Diagram


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Taken out until ??? release	Syntaxvhdl_syn_index

************************ END OF NON-TRANSLATED TEXT ********************************


Text Editor Basic Tools
Basic Tools

AHDL Help Contents

How to Use AHDL

Elements

Design Structure

Syntax

Style Guide

Fields & Buttons

Line Field

Column (Col) Field

Insert/Overwrite (INS/OVR) Button

MAX+PLUS II Initialization & System Files

maxplus2.idx File

maxplus2.ini File

MAX+PLUS II Text Files

AHDL Text Design File (.tdf)

Text Design File Format

Altera Design File (.adf)

Assignment & Configuration File (.acf)

ACF Format

Assignment & Configuration Output File (.aco)

Command File (.cmd)

Command File Format

EDIF Command File (.edc)

EDIF Command File Format

EDIF Input File (.edf)

EDIF Output File (.edo)

Fit File (.fit)

History File (.hst)

Include File (.inc)

JTAG Configuration File (.jcf)

Library Mapping File (.lmf)

Library Mapping File Format

Memory Initialization File (.mif)

Memory Initialization Output File (.mio)

Log File (.log)

Message Text File (.mtf)

Programmer Log File (.plf)

Report File (.rpt)

Report File Format

State Machine File (.smf)

Table File (.tbl)

Tabular Text File (.ttf)

Text Design Export File (.tdx)

Text Design Output File (.tdo)

Timing Analyzer Output File (.tao)

Vector File (.vec)

Vector File Format

Verilog Output File (.vo)

VHDL Design File (.vhd)

VHDL Output File (.vho)

Xilinx Netlist Format File (.xnf)

Mouse Behavior

Output Files

Symbol File (.sym)

Probe, Resource & Device Assignments

Clique Assignments

Connected Pin Assignments

Device Assignments

Logic Option Assignments

Pin, Location & Chip Assignments

Probe Assignments

Timing Assignments

Status Bar & Toolbar

Status Bar

Toolbar

VHDL Help Contents

Style Guide


Line & Column Fields (Text Editor)
Line & Column Fields

Show the line and column number of the insertion point. Show me

Double-clicking Button 1 on the Line or Column (Col) field opens the Go To dialog box, which displays the line and column number of the insertion point. You can type a new line and/or column number and choose OK to move the insertion point to that location.

See also:

Going to a Specific Line or Column


Insert/Overwrite (INS/OVR) Button (Text Editor)
Insert/Overwrite (INS/OVR) Button

Sets the Text Editor insertion point to the Insert (INS) or Overwrite (OVR) mode. Show me

The Insert mode allows you to insert new text at the insertion point. In this mode, typed text is inserted before the text on the right side of the insertion point.

The Overwrite mode allows you to type new text over existing text. In this mode, each character you type replaces the character to the right of the insertion point.

See also:

Adding & Changing Text


Mouse Behavior (Text Editor)
Mouse Behavior

Use a two- or three-button mouse for the MAX+PLUS II Text Editor. You can use Button 1 to click on Text Editor fields and buttons and to select text in a dialog box. Button 2 is used to effect changes to selected text with pop-up command menus.

Button 1 corresponds to the left mouse button. Button 2 corresponds to the right button on a two-button mouse or the middle and right buttons on a three-button mouse.

See also:

Selecting Text


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File updated to include shorter files 8/20/93

*************** END OF NON-TRANSLATED TEXT *************************


Text Editor Help Contents

Introduction

Basic Tools

Commands

Procedures

Golden Rules

Shortcuts

AHDL (including primitives & macrofunctions)

VHDL (including primitives & macrofunctions)

Messages

Glossary


Text Editor--Context-Sensitive Help
Text Editor Context-Sensitive Help

To obtain context-sensitive help for a MAX+PLUS II text file, you must first save the file with the appropriate filename extension, type Shift+F1 to display the Help pointer, and click Button 1 on an item in the window.

Context-sensitive help is available for all Text Editor commands, dialog boxes, and messages, and the following basic tools:

Text Editor Window:

Column (Col) Field

Insert/Overwrite (INS/OVR) Button

Line Field

Status Bar

Toolbar

AHDL

Arithmetic Operators (in Boolean Expressions)

Arithmetic Operators (in Constant Statements & Group Ranges)

Comparators

Logical Operators

Macrofunctions

Primitives

Reserved Identifiers

Reserved Keywords

Symbols

MAX+PLUS II Text Files

AHDL Text Design File (.tdf)

Altera Design File (.adf)

Assignment & Configuration File (.acf)

Assignment & Configuration Output File (.aco)

Command File (.cmd)

EDIF Command File (.edc)

EDIF Input File (.edf)

EDIF Output File (.edo)

Fit File (.fit)

History File (.hst)

Include File (.inc)

Library Mapping File (.lmf)

Log File (.log)

Message Text File (.mtf)

Programmer Log File (.plf)

Report File (.rpt)

State Machine File (.smf)

Table File (.tbl)

Tabular Text File (.ttf)

Text Design Export File (.tdx)

Text Design Output File (.tdo)

Timing Analyzer Output File (.tao)

Vector File (.vec)

Verilog Output File (.vo)

VHDL Design File (.vhd)

VHDL Output File (.vho)

Xilinx Netlist Format File (.xnf)

For information on other basic tools, see Text Editor Basic Tools.

See also:

Getting Context-Sensitive Help


Text Design File--Context-Sensitive Help
Text Design File Context-Sensitive Help

To obtain context-sensitive help for AHDL TDFs, you must first save your text file with the extension .tdf.

Context-sensitive help is available for the following TDF elements:

Arithmetic Operators (in Boolean Expressions)

Arithmetic Operators (in Constant Statements & Group Ranges)

Comparators

Logical Operators

Macrofunctions

Primitives

Reserved Identifiers

Reserved Keywords

Symbols

See also:

Getting Context-Sensitive Help


Text Editor Introduction
Introduction

The MAX+PLUS II Text Editor is a flexible tool for entering text-based designs in the high-level, modular AHDL and VHDL languages that are integrated into the MAX+PLUS II system. You can also use the Text Editor to enter, edit, and view other ASCII files. Show me

How Does the Text Editor Work?

The Text Editor is versatile and easy to use. You can use the Text Editors menu-based commands and text entry and editing features to create TDFs with AHDL and VHDL Design Files with VHDL. In MAX+PLUS II, you can freely combine TDFs and VHDL Design Files with other types of design files in a hierarchical project.

You can use any ASCII text editor to create AHDL and VHDL designs. However, with the MAX+PLUS II Text Editor, you can take advantage of unique MAX+PLUS II features while you enter, compile, and debug a project. For example, the Message Processor automatically locates and highlights errors in the Text Editor window.

You can get context-sensitive help on all AHDL elements, keywords, and statements. Since the Text Editor is completely integrated into MAX+PLUS II, you can check AHDL and VHDL syntax or perform a full compilation or simulation, all from the Text Editor window.

The Text Editor also allows you to view, enter, and edit any ASCII file created for or by MAX+PLUS II. You can create text files for use with other MAX+PLUS II applications, such as EDIF Command Files, LMFs, Vector Files, and Command Files. Moreover, you can obtain context-sensitive help on syntax elements in these files. You can also edit  EDIF Input Files, ADFs, and SMFs and integrate them into a project hierarchy.

You can make resource and device assignments to allocate device resources with menu-based commands in the MAX+PLUS II Text Editor. The Text Editor also allows you to tag timing source and destination nodes for timing analysis, and create a default symbol--for use in a GDF--that represents the current design file. You can also traverse the hierarchy of a project; as you open a design file, MAX+PLUS II automatically opens the appropriate design editor.

Where to Start

Altera offers a variety of information to help you create designs with the Text Editor, AHDL, and VHDL.

On-Line Help

On-line help supplies complete reference and how-to information on using the Text Editor to enter, edit, and view text files.

Text Editor Help Contents provides access to all on-line Text Editor Help.

AHDL Help Contents provides access to all on-line AHDL Help.

VHDL Help Contents provides access to all on-line VHDL Help.

Text Editor Golden Rules, AHDL Golden Rules, and VHDL Golden Rules summarizes essential rules and guidelines for design entry with the Text Editor, AHDL, and VHDL.

Recommended Reading

Additional Altera publications help you understand MAX+PLUS II and the Text Editor. The following application brief is relevant to using the Text Editor:

AB93 (Partitioning a Project with MAX+PLUS II Software)

See also:

AHDL Introduction

How to Use MAX+PLUS II Help

VHDL Introduction


Text Editor Golden Rules
Golden Rules

The following golden rules will help you use the Text Editor effectively:

Be sure to refer to Guidelines for Working with Assignments for absolutely essential information on using all types of resource, probe, and device assignments.

If you wish to load a register on a specific rising edge of the global Clock, Altera recommends that you use the Clock Enable input of one of the Enable-type flipflops such as DFFE, TFFE, JKFFE, or SRFFE to control when the register is loaded.

When you start work on a new design file, specify the target device family with Device right away so that you can take advantage of family-specific macrofunctions. If you dont specify a device family, the family for the current project is assumed.

Use the Design Doctor to check the reliability of your project logic during compilation. Follow Project Reliability Guidelines to create reliable projects.

The Altera-provided default logic synthesis styles have different settings for different device families to ensure that each architecture is used most efficiently. When you use an Altera-provided style, the settings for that style will change when you change the device family. After changing the device family, check the new style settings to ensure that they conform to your needs.

Dont edit a Fit File. If you wish to edit the assignments for a project, back-annotate the assignments with Back-Annotate Project  and edit them with the Assign menu commands.

Do not create your own cross-coupled structures; use only the EXPDFF, EXPLATCH, INPLTCH, NANDLTCH, and NORLTCH macrofunctions provided with the MAX+PLUS II Macrofunction Library. (These macrofunctions are not optimized for FLEX 8000 architecture.) Avoid tying multiple instances of EXPDFF, EXPLATCH, INPLTCH, NANDLTCH, and NORLTCH macrofunctions together. Multiple instances of these macrofunctions should always be separated by LCELL primitives.

General MAX+PLUS II Golden Rules

When you start work on a new design file, name it as the current project with Project Name right away so that you can compile it easily. You can always change the project name later.

Use the built-in hierarchy traversal features in MAX+PLUS II to move between design files for the current hierarchy tree. To open a lower-level file in a hierarchy, open the top-level file and then use the Hierarchy Display window or Hierarchy Down to open the lower-level files. If you choose Open or Retrieve to open a lower-level file, it is considered to be the top of a different hierarchy tree, and resource, device, and probe assignments that you enter are saved only for that hierarchy, not for the project.

When you create an ancillary file for a project, the icon for the file will appear in the Hierarchy Display if you use the same filename as the project.

Dont edit any MAX+PLUS II system files, including .HIFs, maxplus2.idx, or the maxplus2.ini file.

Use the Save As command if you wish to rename a design file or an ancillary file. Dont rename design files from outside of MAX+PLUS II system (e.g., from DOS or with the Windows File Manager).

When you have completed a project, use Project Archive to ensure that you save a complete backup copy of all project files that will not be affected by future edits or deletions.

See also:

AHDL Golden Rules

VHDL Golden Rules


Text Editor Shortcuts
Shortcuts

The following list provides shortcuts for Text Editor commands:

Command:	Shortcut:

AHDL Template

Context-Sensitive Help	Shift+F1 or

Cascade	Shift+F5

Close	Ctrl+F4 or double-click Button 1 on the Document Control Menu box

Compiler

Copy	Ctrl+C or Ctrl+Insert, or [image] or Press Ctrl+Button 1, drag, and release with the Selection pointer

Cut	Ctrl+X or Shift+Del, or

Decrease Indent	F3 or

Delete	Del or Backspace

Exit MAX+PLUS II	Alt+F4 or double-click Button 1 on the Application Control Menu box

Find Next	Ctrl+N

Find Node in Design File	Ctrl+B or

Find Node in Floorplan Editor

Find Previous	Ctrl+Shift+N

Find Text	Ctrl+F or

Floorplan Editor

Font

Go To	Ctrl+G or double-click Button 1 on Line or Column field

Hierarchy Display

Hierarchy Down	Ctrl+D

Hierarchy Project Top	Ctrl+T or

Hierarchy Up	Ctrl+U

Increase Indent	F2 or

Info	Ctrl+I

New

Next	Ctrl+F6

Open	Ctrl+O or

Paste	Ctrl+V or Shift+Insert, or

Print	Ctrl+P or

Programmer

Project Name	Ctrl+J or

Project Save & Check	Ctrl+K or

Project Save & Compile	Ctrl+L or

Project Save & Simulate	Ctrl+Shift+L or

Project Set Project to Current File	Ctrl+Shift+J or

Save	Ctrl+S or

Save & Check	Ctrl+K or

Search & Replace	Ctrl+R or

Simulator

Switch To	Ctrl+Esc

Text Size

Tile	Shift+F4

Timing Analyzer

Timing Analysis Cutoff	Ctrl+Alt+C

Timing Analysis Destination	Ctrl+Alt+D

Timing Analysis Source	Ctrl+Alt+S

Undo	Ctrl+Z or Alt+Backspace, or

VHDL Template

See also:

Selecting Text

Showing the Toolbar


Text Editor Procedures
 Procedures

Assignments & Compiler Configuration Settings

Assigning a Clique

Assigning a Device

Assigning a Pin, Location, or Chip

Assigning a Probe

Assigning an Individual Logic Option or Synthesis Style

Assigning Connected Pins

Assigning Individual Timing Requirements

Bank-Annotating Assignments for a Project

Clearing Assignments for a Project

Converting an Obsolete Assignment Format

Copying a Resource Assignment

Defining a Logic Synthesis Style

Deleting an Assignment

Guidelines for Achieving Maximum Speed Performance

Guidelines for First-Time Project Fitting

Guidelines for Timing Assignments

Guidelines for Working with Assignments

Ignoring Project Assignments during Compilation

Logic Synthesis Style & Logic Option Rules

Searching the Node Database

Specifying Devices for Automatic Device Selection

Specifying Global Project FLEX 8000 Device & Pin Options

Specifying Global Project Logic Synthesis Settings

Specifying Global Project Security Bit & Reserved Resource Settings

Specifying Global Project Timing Requirements

Specifying Individual Device Security & Turbo Bit Options

Specifying Individual FLEX 8000 Device & Pin Options

File Management

Closing a File

Creating a Default Include File

Creating a New File

Getting Information on a File

Opening a File

Printing a File

Retrieving a File

Saving a File

Hierarchy

Navigating the Hierarchy

Updating the Hierarchy

MAX+PLUS II Management

Changing Colors in MAX+PLUS II

Closing a MAX+PLUS II Application

Creating & Using a Local Copy of the maxplus2.ini File

Entering an Authorization Code

Exiting from MAX+PLUS II Applications

Specifying a User Library

Starting MAX+PLUS II Applications

Switching Between MAX+PLUS II Applications

Messages

Getting Help on a Message

Locating the Source of a Message

Project Management

Archiving a Project

Changing the Project Name

Combining Multiple Projects for Simulation

Compiling a Project

Ensuring Project Reliability

Project Reliability Guidelines

Partitioning a Project

Automatic Partitioning

Guiding the Partitioner

Viewing the Results of Partitioning

Renaming a Macrofunction in the Current Project

Status Bar & Toolbar

Showing the Status Bar

Showing the Toolbar

Symbols & Nodes

Clearing Timing Tags

Creating the Default Symbol for a File

Editing the Symbol for a File

Finding Nodes & Pins in the Floorplan Editor

Finding Nodes & Symbols in Design Files

Tagging Timing Cutoff Nodes

Tagging Timing Source & Destination Nodes

Text

Adding & Changing Text

Changing the Font

Changing the Text Size

Copying, Cutting & Pasting Text

Deleting Text

Finding a Matching Section Delimiter

Finding Text

Finding & Replacing Text

Going to a Specific Line or Column

Indenting Text

Inserting an AHDL Template

Inserting a Page Break

Inserting a VHDL Template

Moving Text with Drag & Drop

Selecting Text

Setting the Tab Stops

Using Syntax Coloring in Text Files

Timing Analysis

Running a Timing Analysis

Undoing Edits


Printing a File (Text Editor)
 Printing a File

To print the current file:

1.	Open the Print dialog box by choosing Print (File menu) or with a shortcut.

2.	Turn on one or more of the following options:

Option:	Action:

Copies	Specifies the number of copies to print. Multiple copies are collated.

Pages	Specifies the pages to print.

All	Prints the entire text file.

Selected Area	Prints only the currently selected text.

Print Page Headers	Prints a header on each page that includes the MAX+PLUS II version number, filename, date, and page number.

Print Quality	Specifies Proof or Draft print quality for the file.

Text Size	Specifies the text size for the file. You can change the printed text size without changing the text size in the file.

3.	Choose OK.

To change the printer and printer options:

1.	Choose Print Setup (File menu). The Print Setup dialog box is displayed.

2.	Select the correct printer.

3. 	If necessary, choose Setup to open a dialog box that controls options for your printer, change any desired options, and choose OK to return to the Print Setup dialog box.

4.	Choose OK in the Print Setup dialog box.


Adding & Changing Text (Text Editor)
Adding & Changing Text

To add text:

1.	If necessary, click Button 1 on the Insert/Overwrite button at the bottom of the window to display INS.

2.	Click Button 1 or use arrow keys to place the insertion point at the correct position.

3.	Type new text. The text is inserted at the insertion point.

To change text:

1.	If necessary, click Button 1 on the Insert/Overwrite button at the bottom of the window to display OVR.

2.	Click Button 1 or use arrow keys to place the insertion point before the text you wish to change.

3.	Type new text. The typed text overwrites the text to the right of the insertion point.

or:

1.	Select the text you wish to change.

2.	Type new text. The typed text overwrites the selected text.

See also:

Moving Text with Drag & Drop

Setting the Tab Stops


Changing the Text Size (Text Editor)
Changing the Text Size

To change the text size for the current text file:

Choose Text Size (Options menu) and select a text size from the list or use a shortcut.

All text in the file is changed to the specified point size. The Text Size drop-down list box on the toolbar displays the current text size for the file.

See also:

Changing the Font


Changing the Font (Text Editor)
Changing the Font

To change the font for the current text file:

Choose Font (Options menu) and select a font from the list or use a shortcut.

All text in the file is changed to the specified font. The Font drop-down list box on the toolbar displays the current font for the file.

See also:

Changing the Text Size


Finding a Matching Section Delimiter (Text Editor)
Finding a Matching Section Delimiter

The Text Editor allows you to find start-of-section, end-of-section, and other syntax delimiters in a variety of different text file formats. For instance, if you select a "9", the Text Editor can find the next opposite delimiter, ")".

The types of delimiters you can find depend on the extension of the current file. Show me

The following list shows some of the most common section delimiters.

()

[]

BEGIN END

IF END

CASE END

TABLE END

To find a specific section delimiter:

1.	Select or place the insertion point in the delimiter keyword you wish to match.

2.	Choose Find Matching Delimiter (Utilities menu) or use a shortcut.

See also:

Finding Text

Selecting Text

Using Syntax Coloring in Text Files


File Types Applicable for Delimiter Matching

Altera Design File (.adf)	Memory Information Output File (.mio)

Assignment & Configuration File (.acf)	Standard Delay Format File (.sdf)

Assignment & Configuration Output File (.aco)	Standard Delay Format Output File (.sdo)

Command File (.cmd)	State Machine File (.smf)

EDIF Command File (.edc)	Table File (.tbl)

EDIF Input File (.edf)	Text Design Export File (.tdx)

EDIF Output File (.edo)	Text Design File (.tdf)

Fit File (.fit)	Text Design Output File (.tdo)

Include File (.inc)	Vector File (.vec)

Library Mapping File (.lmf)	Verilog Output File (.vo)

Log File (.log)	VHDL Design File (.vhd)

Memory Information File (.mif)	VHDL Output File (.vho)


Finding Text (Text Editor)
Finding Text

To find a specific string of text:

1.	Move the insertion point to define where the search will begin or select the text you wish to search for.

2.	Open the Find Text dialog box by choosing Find Text (Utilities menu) or using a shortcut.

3.	If you did not select text in step 1, type the search text in the Search For box, including optional wildcard and/or special characters.

4.	If necessary, turn on one or more of the following options:

Option:	Action:

Whole Word	Finds occurrences of the search text that are whole words only.

Match Upper/Lowercase	Matches capitalization exactly.

Pause at End	Pauses the search when the Text Editor reaches the end of the file.

5.	Select the Up or Down option to search up or down within the file.

6.	Choose OK to begin the search.

7.	If necessary, after the search text has been found, choose Find Text, Find Next, or Find Previous to find the search text again.

See also:

Finding a Matching Section Delimiter

Finding & Replacing Text

Selecting Text


Finding & Replacing Text (Text Editor)
Finding & Replacing Text

To find and replace text:

1.	Move the insertion point to define where the search will begin or select a word or phrase on a single line.

If you select a region (i.e., several lines of text), the line up to the first paragraph break is automatically designated as the Search for text. In addition, choosing OK at this point would perform the search only in the selected region.

2.	Choose Search & Replace. The Search & Replace dialog box is displayed.

3.	If you did not select text in step 1, type the search text in the Search For box, including optional wildcard and/or special characters.

4.	Type the new text in the Replace With box.

5.	If necessary, turn on one or more of the following options:

Option:	Action:

Whole Word	Finds occurrences of the search text that are whole words only.

Mach Upper/Lowercase	Matches capitalization exactly.

Pause at End	Pauses the search when the Text Editor reaches the end of the file.

Confirm Each Change	Specifies that the Text Editor must ask before replacing an occurrence of the search text.

6.	Select the Up or Down option to search up or down within the file.

7.	Choose OK to begin the search.

8.	If necessary, choose Find Text, Find Next, or Find Previous to find the search text again.

If the Text Editor finds the search text when the Confirm Each Change option is turned on, you are asked whether you wish to replace the selection. Choose one of the following options:

Button/Option:	Action:

Confirm Each Change	Specifies that the Text Editor must ask before replacing an occurrence of the search text. If you turn this option off, the Text Editor replaces all occurrences.

Yes	Replaces the currently selected search text, then continues the search.

No	Does not replace the currently selected search text, but continues the search.

Cancel	Ends the search.

See also:

Adding & Changing Text

Finding Text

Selecting Text


Going to a Specific Line or Column (Text Editor)
Going to a Specific Line or Column

To move the insertion point to a specific line and/or column:

1.	Open the Go To dialog box by choosing Go To (Utilities menu) or using a shortcut.

2.	Type a line number and/or column number.

3.	Choose OK.

Type Ctrl+Home or Ctrl+End to move the insertion point to the beginning or end of a file.

or:

Press an arrow key to move to a different line or column number.

The window scrolls to the specified line and places the insertion point directly before the character at the specified column number. If you specify only a line number, the insertion point is placed in the first column of the specified line. If you specify only a column number, the insertion point is placed in the specified column of the current line.

See also:

Finding a Matching Section Delimiter


Indenting Text (Text Editor)
Indenting Text

You can use the automatic indenting feature to easily align text as you type new lines without having to press Tab or Space to move the insertion point to the appropriate column number. You can also increase or decrease the indent of an existing line or section of text.

To turn the automatic indent on and off:

Choose Auto-Indent (Options menu).

To increase or decrease the indent of existing text:

Choose Increase Indent or Decrease Indent (Edit menu) or use a shortcut.

See also:

Setting the Tab Stops


Inserting a Page Break (Text Editor)
Inserting a Page Break

To insert a page break at the current insertion point or to replace selected text with a page break:

Choose Insert Page Break (Edit menu) or use a shortcut.

The page break appears as a § symbol.


Inserting an AHDL Template (Text Editor)
Inserting an AHDL Template

The Text Editor allows you to insert a template for any AHDL statement or section into the current file. AHDL templates provide an easy way for you to enter AHDL syntax, increasing the speed and accuracy of design entry.

To insert an AHDL template at the current insertion point:

1.	Open the AHDL Template dialog box by choosing AHDL Template (Templates menu) or using a shortcut.

2.	Select a name in the Template Section box.

3.	Choose OK.

Once you have inserted a template into your TDF, you must replace all variables in the template with your own logic. Each AHDL keyword is capitalized and each variable name starts with two underscores (_ _) to help you identify them. You can also use Syntax Coloring (Options menu) to make keywords and variables easy to see.

See also:

AHDL Help Contents

Getting Context-Sensitive Help

Recommended File Structure (AHDL)

Using Syntax Coloring in Text Files


Inserting a VHDL Template (Text Editor)
Inserting a VHDL Template

The Text Editor allows you to insert a template for any supported VHDL construct into the current file. VHDL templates provide an easy way for you to enter VHDL syntax, increasing the speed and accuracy of design entry.

To insert an VHDL template at the current insertion point:

1.	Open the VHDL Template dialog box by choosing VHDL Template (Templates menu) or using a shortcut.

2.	Select a name in the Template Section box.

3.	Choose OK.

Once you have inserted a template into your VHDL design file, you must replace all variables in the template with your own logic. Each VHDL keyword is capitalized and each variable name starts with two underscores (_ _) to help you identify them. You can also use Syntax Coloring (Options menu) to make keywords and variables easy to see.

See also:

VHDL Help Contents

Getting Context-Sensitive Help

Using Syntax Coloring in Text Files


Moving Text with Drag & Drop (Text Editor)
Moving Text with Drag & Drop

To move selected text with drag and drop:

1.	Select the text to move.

2.	Point to the selection.

3.	Press Button 1 and drag the cursor to place the insertion point at the new location.

4.	Release Button 1.

The text is inserted at the new location.

See also:

Copying, Cutting & Pasting Text

Selecting Text


Setting the Tab Stops (Text Editor)
Setting the Tab Stops

You can specify the number of spaces that a tab stop represents. This setting also controls the indenting used by Auto-Indent (Options menu) and the Increase Indent and Decrease Indent commands (Edit menu). The default tab stop setting is four spaces.

1.	Choose Tab Stops (Options menu). The Tab Stops dialog box is displayed.

2.	Type an integer between 1 and 16.

3.	Choose OK.

When you press Tab, the insertion point moves ahead to the next tab stop.

See also:

Indenting Text


Using Syntax Coloring in Text Files (Text Editor)
Using Syntax Coloring in Text Files

The Text Editor allows you to view various elements of a text file in different colors. Syntax Coloring can improve your file readability and accuracy. For instance, it can help you identify misspelled keywords and sections of files that have been commented out by mistake.

To turn the syntax coloring option on and off:

Choose Syntax Coloring (Options menu).

Syntax coloring is available for the following text files:

Altera Design File (.adf)	Memory Information Output File (.mio)

Assignment & Configuration File (.acf)	Standard Delay Format File (.sdf)

Assignment & Configuration Output File (.aco)	Standard Delay Format Output File (.sdo)

Command File (.cmd)	State Machine File (.smf)

EDIF Command File (.edc)	Table File (.tbl)

EDIF Input File (.edf)	Text Design Export File (.tdx)

EDIF Output File (.edo)	Text Design File (.tdf)

Fit File (.fit)	Text Design Output File (.tdo)

Include File (.inc)	Vector File (.vec)

Library Mapping File (.lmf)	Verilog Output File (.vo)

Log File (.log)	VHDL Design File (.vhd)

Memory Information File (.mif)	VHDL Output File (.vho)

You can use the Screen Elements box in the Color Palette dialog box to customize the assigned colors for the following text elements:

Comments

Illegal characters

Macrofunctions

Reserved identifiers

Reserved keywords

Strings

See also:

Changing Colors in MAX+PLUS II


************************* BEGINNING OF NON-TRANSLATED TEXT **********************************

 Remember to fix the curly quote problem. (I added this sentence to facilitate putting unchanged files requiring Kerrys curly quote fix. KAW)

The following messages from tedmsgs.msg are documented elsewhere:

sted_file_open	glmess

sted_file_read	glmess

sted_file_write	glmess

sted_dlg_text_not_found	edmess

sted_dlg_search_complete	edmess

sted_last_edit_not_found	edmess

sted_no_timer	edmess

sted_out_of_resources	glmess

sted_no_print_dc	glmess

sted_print_start_fail	glmess

sted_disk_space_err	glmess

cted_overwrite_file_err	glmess

sted_print_out_of_memory_err	glmess

sted_print_err

sted_print_line_text_err	glmess

qted_cont_search_at_top	edmess

qted_cont_search_at_end	edmess

************************* END OF NON-TRANSLATED TEXT ****************************************


 File <name> on disk is newer than file being edited. OK to open newer file without saving current file?

CAUSE:	The file on disk has a date that is more recent than the file being edited. The newer file was probably created by a background process. For example, if you recompile a project while the Report File for the project is open, the Compiler creates a newer project Report File on disk.

ACTION:	Choose Save As (File menu) to save your changes to a file with a different name, or load the new file.

See also:

MAX+PLUS II Messages

Message Format

Saving a File


File <name> on disk is newer than file being edited. Close all windows of older file without saving?
 File <name> on disk is newer than file being edited. Close all windows of older file without saving before opening the newer file on disk.

CAUSE:	The file on disk has a date that is more recent than the file being edited. The newer file was probably created by a background process. For example, if you recompile a project while the Report File for the project is open, the Compiler creates a newer project Report File on disk.

ACTION:	Close all open windows that contain the older file, then open the newer file from the disk.

See also:

Closing a File

MAX+PLUS II Messages

Message Format

Opening a File


 Illegal line or column number

CAUSE:	You entered a line or column number with the Go To command (Utilities menu) that is not an integer.

ACTION:	Type an integer that is greater than zero and choose OK.

See also:

MAX+PLUS II Messages

Message Format


 Illegal tab stop value (min. = 1; max. = 16)

CAUSE:	You entered a number with the Tab Stops command (Options menu) that is less than 1 or greater than 16.

ACTION:	Type a number between 1 and 16 and choose OK.

See also:

MAX+PLUS II Messages

Message Format


Line <number. truncated
 Line <number> truncated

CAUSE:	The file you opened in the Text Editor contains a line with more than the maximum number of characters allowed, so the line was truncated. A single line of text can contain only 2,000 characters.

ACTION:	Close the file without saving. If you save the file, the excess characters in the line will not be saved. Use another text editor to split the text so that each line contains fewer than 2,000 characters.

See also:

MAX+PLUS II Messages

Message Format


 Line is too long -- has more than 2000 characters

CAUSE:	You tried to insert or paste text into a line of text that would cause the line to contain more than the maximum number of characters allowed. A single line of text can contain only 2,000 characters.

ACTION:	Split the line into two or more lines with less than 2,000 characters.

See also:

MAX+PLUS II Messages

Message Format


Name is not a macrofunction name
 Name is not a megafunction or macrofunction name

CAUSE:	You highlighted text in the current Text Editor file and chose Hierarchy Down (File menu). The selected text is not the name of a lower-level design file in the current hierarchy.

ACTION:	Ensure that you have highlighted the name of a lower-level design file, then choose Hierarchy Down again.

See also:

MAX+PLUS II Messages

Message Format

Navigating the Hierarchy


 Search or replacement text currently cannot contain any text after ^n

CAUSE:	You entered text after ^n or ^N (which represents an end-of-line character) in the Search For or Replace With box in the Text Editors Find Text or Search & Replace dialog box. The current version of MAX+PLUS II does not support this feature.

ACTION:	Make sure that your search or replacement text contains a single occurrence of ^n or ^N, and do not enter any text after ^n or ^N. Any text after ^n or ^N will be ignored.

See also:

MAX+PLUS II Messages

Message Format


Search text contains too many wildcard characters

CAUSE:	The expression you instructed MAX+PLUS II to search for is too complicated for the text editor to find. Example: * all by itself.

ACTION:	Specify an expression that is less complicated or contains fewer wildcard characters.

See also:

MAX+PLUS II Messages

Message Format


Search text contains illegal character after ^

CAUSE:	The expression you instructed MAX+PLUS II to search for contains a special character that the Text Editor does not understand. The Text Editor supports: ^n, ^N, ^l, ^L, ^t, ^T, ^*, ^?, and ^^. If anything other than the above characters are placed after a carat, or if nothing follows the carat, MAX+PLUS II will be unable to complete the desired search.

ACTION:	Designate a new search expression containing legal special characters.

See also:

MAX+PLUS II Messages

Message Format


Finished searching the selection. <number> replacements were made. Do you want to search the remainder of the file?

CAUSE:	MAX+PLUS II performed a Search and Replace (with the Confirm Each Change option turned off) on a selected block of text, and made all possible replacements within the selected area.

ACTION:	Choose Yes if to scan the remainder of the file scanned for replacement or No to prevent replacement in any other part of the file.

See also:

MAX+PLUS II Messages

Message Format


Cant find matching section delimiter for <text>

CAUSE:	The following three situations cause this message to appear:

1.	MAX+PLUS II was unable to find the opening brace for the end brace that you defined. The program reached the beginning of the file without finding a match, or, if the selected brace is a comment or string, the program reached the beginning of that comment or string without finding a match.

2.	MAX+PLUS II was unable to find the ending brace for the beginning brace that you defined. The program reached the end of a file without finding a match, or, if the selected brace is in a comment or string, the program reached the end of the comment or string without finding a match.

3.	If the style of the file is sufficiently strange, it may not be possible for MAX+PLUS II to find a match. Example: the program expects IF to be on one line and END IF to be matching braces for a section of code. If you entered the commands thusly:

IF...

...

...

END

IF

the results are not guaranteed.

ACTION:	You must either enter a legal matching brace or conform to a more consistent style.

See also:

MAX+PLUS II Messages

Message Format


Text on the current line does not contain a section delimiter

CAUSE:	You instructed MAX+PLUS II to search for a matching delimiter with the Find Matching Delimiter command, however, there are no legal section delimiters on the line with the insertion point.

ACTION:	Place the cursor on a line with a legal section delimiter for the file type.

See also:

MAX+PLUS II Messages

Message Format


Selected text must be a section delimiter

CAUSE:	You instructed MAX+PLUS II to search for a matching delimiter with the Find Matching Delimiter command, however, the block of text that you have selected is not a legal section delimiter.

ACTION:	Select an appropriate section delimiter for the file type.

See also:

MAX+PLUS II Messages

Message Format


MAX+PLUS II system software problem: <name> is missing, so syntax coloring and section delimiter matching in the Text Editor wil
MAX+PLUS II system software problem: <name> is missing, so syntax coloring and section delimiter matching in the Text Editor will be disabled

CAUSE:	The file <TTED_DEFAULT_TOKEN_FILE_NAME> is not present in the MAX+PLUS II install directory. This will disable syntax coloring in the Text Editor.

ACTION:	Please re-install MAX+PLUS II to get a clean version of this file.

See also:

MAX+PLUS II Messages

Message Format


MAX+PLUS II system software problem: cant read file <name>

CAUSE:	The MAX+PLUS II system file <TTED_DEFAULT_TOKEN_FILE_NAME> contains data that initializes syntax coloring information in the Text Editor. An error was encountered while reading this file.

ACTION:	Please re-install MAX+PLUS II to get a clean version of this file.

See also:

MAX+PLUS II Messages

Message Format


Cant open encrypted file <name>

CAUSE:	You do not have the authorization code necessary to open this Altera Encrypted file.

ACTION:	Return to MAX+PLUS II and work with a different file.

See also:

MAX+PLUS II Messages

Message Format


Text Editor Commands
Commands

For Help, choose a command name or dialog box name from the following list. Menu names are not included on the list.

About MAX+PLUS II	MAX+PLUS II Registration

Advanced Options	MAX+PLUS II Table of Contents

AHDL Template	Maximize

AHDL	Message Processor

Analyze Timing	Messages

Archive	Minimize

Arrange Icons	More Windows

Authorization Code	Move

Auto Device Selection	Name

Auto-Indent	New Features in This Release

Back-Annotate Project	New Window

Basic Tools	New

Cascade	Next

Classic & MAX Global Project Device Options	Open

Classic & MAX Individual Device Options	Paste

Clear All Timing Tags	Pin/Location/Chip

Clear Project Assignments	Preferences

Clique	Primitives

Close (File menu)	Print Setup

Close ( [image] and [image] menus)	Print

Color Palette	Probe

Commands	Procedures

Compiler	Programmer

Connected Pins	Project 1, 2, 3, 4...

Convert Obsolete Assignment Format	Project Archive

Copy	Project Name

Create Default Include File	Project Save & Check

Create Default Symbol	Project Save & Compile

Cut	Project Save & Simulate

Decrease Indent	Project Save, Compile & Simulate

Define Synthesis Style	Project Set Project to Current File

Delete File	READ.ME

Delete	Rename Chip

Device	Restore

Devices & Adapters	Retrieve

Edit Symbol	Save & Check

ES Site License Authorization Request	Save & Compile

Exit MAX+PLUS II	Save & Simulate

Find Last Edit	Save As

Find Matching Delimiter	Save Style As

Find Next	Save, Compile & Simulate

Find Node in Design File	Save

Find Node in Floorplan	Search & Replace

Find Previous	Search for Help on

Find Text	Search Node Database

FLEX 10K Global Project Device Options	Set Project to Current File

FLEX 10K Individual Device Options	Shortcuts

FLEX 8000 Global Project Device Options	Show Status Bar

FLEX 8000 Individual Device Options	Show Toolbar

Floorplan Editor	Simulator

Font	Size

Global Project Device Options	Switch To

Global Project Logic Synthesis 	Symbol Editor

Global Project Parameters	Syntax Coloring

Global Project Timing Requirements	Tab Stops

Glossary	Table of Contents

Go To	Text Editor

Golden Rules	Text Editor Help Basic Tools

Graphic Editor	Text Editor Help Commands

Hierarchy Display	Text Editor Help Golden Rules

Hierarchy Down	Text Editor Help Introduction

Hierarchy Project Top	Text Editor Help Procedures

Hierarchy Top	Text Editor Help Shortcuts

Hierarchy Up	Text Editor Help Table of Contents

How to Use Help	Text Size

How to Use MAX+PLUS II Help	Tile Horizontally

Ignore Project Assignments	Tile Vertically

Increase Indent	Timing Analysis Cutoff

Individual Logic Options	Timing Analysis Destination

Info	Timing Analysis Source

Insert Page Break	Timing Analyzer

Introduction	Timing Requirements

Logic Options	Undo

Macrofunctions	User Libraries

MAX 7000S Global Project Device Options	VHDL Template

MAX 7000S Individual Device Options	VHDL

Waveform Editor


Save As Command (Text Editor)
Save As Command (File Menu)

Saves a new version of the current file under a different name, in a different directory, or on a different drive. Save As also saves a new file for the first time.

Click Button 1 on any item in this dialog box for information on that item:

If you wish to save the file without an extension, type a period (.) at the end of the name, e.g., type mult2. to save the file under the name mult2.

See also:

Creating the Default Symbol for a File

Project Save & Compile Command

Save & Check Command

Save Command

Saving a File


Print Command (Text Editor)
Print Command (File Menu)

Shortcuts

Prints the file in the currently active Text Editor window.

Click Button 1 on any item in this dialog box for information on that item:

MAX+PLUS II prints the file according to the settings for the current printer, which are specified with Print Setup (File menu).

See also:

Printing a File


Pages

All	Prints all pages in the current file.

Selected Area	Prints only the current selected area within the file.


Print Quality

Proof	Prints the file slowly with maximum resolution.

Draft	Prints the file quickly with lesser resolution.

Print quality is printer-dependent; for some printers, proof and draft printing are the same.


Text Size

Specifies the text size for printing the file. You can change the printed text size without changing size of text displayed in the file.


Print Dialog Box (Text Editor)
 Print dialog box

Click Button 1 on any item in this dialog box for information on that item:


Cut Command (Text Editor)
Cut Command (Edit Menu)

Shortcuts

Deletes the selected text from the file and places it on the Clipboard. The previous contents of the Clipboard are erased.

Use Paste (Edit menu) to insert cut text into a file. The contents of the Clipboard can be pasted repeatedly.

Cut text can be pasted into different MAX+PLUS II files and into different types of text fields. For example, a pin name from a GDF can be pasted into a TDF. A graphical object can be pasted only if it is compatible with the target file format.

Use Delete (Edit menu) instead of Cut to remove text from the file without affecting the contents of the Clipboard.

See also:

Copying, Cutting & Pasting Text

Deleting Text

Selecting Text


Copy Command (Text Editor)
Copy Command (Edit Menu)

Shortcuts

Copies selected text from the file and places it on the Clipboard. The previous contents of the Clipboard are erased.

Use Paste (Edit menu) to place the copied text into a file. The contents of the Clipboard can be pasted repeatedly.

After you choose Copy, the text remains selected.

Copied text can be pasted into different MAX+PLUS II files and into different types of text fields. For example, a pin name from a GDF can be pasted into a TDF. A graphical object can be pasted only if it is compatible with the target file format.

See also:

Copying, Cutting & Pasting Text

Selecting Text


Paste Command (Text Editor)
Paste Command (Edit Menu)

Shortcuts

Places a copy of the Clipboard’s contents at the insertion point or overwrites selected text.

The Clipboard’s contents are defined with the last Cut or Copy command (Edit menu).

If an insertion point is selected, Paste inserts the contents of the Clipboard to the left of the insertion point. If text is selected, Paste overwrites the selected text.

The contents of the Clipboard can be pasted repeatedly.

Copied or cut text can be pasted into different MAX+PLUS II files and into different types of text fields. For example, a pin name from a GDF can be pasted into a TDF. A graphical object can be pasted only if it is compatible with the target file format.

If you paste a column of text at the beginning or middle of a text file, the column is inserted into the file at the insertion point and into subsequent lines. Each line of text in the column is pasted into an existing line (if any). Existing text is not moved down to the end of the column.

See also:

Copying, Cutting & Pasting Text

Selecting Text


Insert Page Break Command (Text Editor)
Insert Page Break Command (Edit Menu)

Shortcuts

Inserts a page break at the current insertion point, which appears as a § character.

You can select the § character and copy and paste it in the same manner as any other character in the file.

See also:

Inserting a Page Break


Increase Indent & Decrease Indent Commands (Text Editor)
Increase Indent & Decrease Indent Commands (Edit Menu)

Shortcuts

Increases or decreases the indent of the line at the cursor position or any selected lines of text according to the number of spaces designated by the Tab Stops command (Options menu).

You can also use the Auto-Indent command (Options menu) to automatically indent new lines of text, according to the number of spaces designated by the Tab Stops command, as you enter them in a TDF.

See also:

Indenting Text

Setting the Tab Stops


AHDL Template Command (Text Editor)
AHDL Template Command (Templates Menu)

Shortcuts

Inserts an AHDL template at the current insertion point.

Click Button 1 on any item in this dialog box for information on that item:

AHDL templates provide an easy way for you to enter AHDL syntax, increasing the speed and accuracy of design entry. Once you have inserted a template into your TDF, you must replace all variables in the template with your own logic. Each variable name starts with two underscores (_ _) to help you identify it; each keyword is capitalized.

A single template is available for the overall AHDL file structure. This template, called "Overall Structure," lists all AHDL sections and statements in separate comment lines in the order in which they appear in the TDF. The syntax of these sections and statements is not included; you must replace the comment line with the correct AHDL syntax for each section you wish to use in your TDF. The "Overall Structure" template is listed first in the Template Section box.

In addition, individual templates are available for the following AHDL sections and statements. These templates are listed in the order in which they appear in the TDF, and can be used to replace the comment lines in the "Overall Structure" template.

Include Statement

Title Statement

Constant Statement

Function Prototype Statement

Options Statement

Subdesign Section

Variable Section

Node Declaration

Instance Declaration

Register Declaration

State Machine Declaration

Machine Alias Declaration

Logic Section

Defaults Statement

Boolean Equation

Case Statement

If Statement

In-Line Macrofunction & Primitive Reference

Truth Table Statement

See also:

AHDL Help Contents

Getting Context-Sensitive Help

Inserting an AHDL Template

Recommended File Structure (AHDL)


Template Section

Displays a list of AHDL section and statement template names. You can select a template name in the Template Section box and choose OK to insert a template at the current insertion point.


AHDL Template Dialog Box (Text Editor)
 AHDL Template dialog box

Click Button 1 on any item in this dialog box for information on that item:


VHDL Template Command (Text Editor)
VHDL Template Command (Templates Menu)

Shortcuts

Inserts a VHDL template at the current insertion point.

Click Button 1 on any item in this dialog box for information on that item:

VHDL templates provide an easy way for you to enter VHDL syntax, increasing the speed and accuracy of design entry. Once you have inserted a template into your VHDL Design File, you must replace all variables in the template with your own logic. Each variable name starts with two underscores (_ _) to help you identify it; each keyword is capitalized.

MAX+PLUS II provides templates for complete flipflop, counter, and tri-state designs. In addition, a single template is available for the overall VHDL file structure. This template, called "Overall Structure," lists all VHDL constructs in separate comment lines in the order in which they appear in a VHDL Design File. The syntax of these sections and statements is not included; you must replace the comment line with the correct VHDL syntax for each section you wish to use in your file.

In addition, individual templates are available for the following VHDL constructs. You can use these templates to replace the comment lines in the "Overall Structure" template.

Architecture Body

Case Statement

Component Declaration

Component Instantiation Statement

Concurrent Procedure Call

Concurrent Signal Assignment Statement

Conditional Signal Assignment

Constant Declaration

Entity Declaration

For Statement

If Statement

Library Clause

Package Declaration

Procedure Call Statement

Process (Combinatorial Logic)

Process (Sequential Logic)

Selected Signal Assignment Statement

Signal Declaration

Signal Assignment Statement

State Machine

Subtype

Type

Use Clause

Wait Statement

Variable Declaration Statement

Variable Assignment Statement

While Statement

See also:

VHDL Help Contents

Getting Context-Sensitive Help

Inserting a VHDL Template


Template Section

Displays a list of VHDL construct template names. You can select a template name in the Template Section box and choose OK to insert a template at the current insertion point.


VHDL Template Dialog Box (Text Editor)
 VHDL Template dialog box

Click Button 1 on any item in this dialog box for information on that item:


Select the Appropriate Template Command

The behavior of the toolbar button you have selected depends on the current filename extension.

If the current file has the extension .vhd, this button opens the VHDL Template dialog box. Otherwise, this button opens the AHDL Template dialog box.


Go To Command (Text Editor)
Go To Command (Utilities Menu)

Shortcuts

Moves the insertion point to the specified line and/or column number.

Click Button 1 on any item in this dialog box for information on that item:

The window scrolls to the specified line and places the insertion point directly before the character at the specified column number.

See also:

Going to a Specific Line or Column


Line Number

Specifies the line number.

If you specify only a line number, the insertion point is placed in the first column of the specified line. If you enter a line number that does not exist, the insertion point is placed at the beginning of the last line in the file.


Column Number

Specifies the column number.

If you specify only a column number, the insertion point is placed in the specified column of the current line. If you enter a column number that does not exist, the insertion point is placed after the last character in the line.


Go To Dialog Box (Text Editor)
 Go To dialog box

Click Button 1 on any item in this dialog box for information on that item:


Find Text Command (Text Editor)
Find Text Command (Utilities Menu)

Shortcuts

Searches from the insertion point for the first occurrence of the specified text in the current file.

Click Button 1 on any item in this dialog box for information on that item:

After the first occurrence of the search text is found, you can choose Find Next or Find Previous (Utilities menu) to continue the search.

See also:

Finding Text

Finding & Replacing Text

Search & Replace Command


Match Upper/Lowercase

Finds only the text that has the same capitalization as the text entered in the Search For box.


Search For; Find Text and Search & Replace dialog boxes TED only
Search For

Specifies the text to be found. You can enter up to 256 characters, including optional wildcard and special characters, in the search text.

If text is selected in the file or was entered in another editor’s Find Text or Search & Replace dialog box, it appears as the default search text.


Find Text Dialog Box (Text Editor)
 Find Text dialog box

Click Button 1 on any item in this dialog box for information on that item:


Find Next Command (Text Editor)
Find Next Command (Utilities Menu)

Shortcuts

Finds the next occurrence of the search text specified with Find Text or Search & Replace (Utilities menu).

Find Next searches in the direction specified in Find Text or Search & Replace. If you specified Down, it searches down the file; if you specified Up, it searches up.

See also:

Finding Text

Finding & Replacing Text


Find Previous Command (Text Editor)
Find Previous Command (Utilities Menu)

Shortcuts

Finds the previous occurrence of the search text specified with Find Text or Search & Replace (Utilities menu).

Find Previous searches opposite to the direction specified in Find Text or Search & Replace. If you specified Down, it searches up the file; if you specified Up, it searches down.

See also:

Finding Text

Finding & Replacing Text


Find Matching Delimiter Command (Text Editor)
Find Matching Delimiter (Utilities Menu)

Shortcuts

Finds and highlights the start-of-section, end-of-section, or other syntax delimiter that matches your selection.

Matching delimiters are pairs of symbols or keywords that open and close sections of code or message(s).

The following list shows some of the most common section delimiters:

()

[]

BEGIN END

IF END

CASE END

TABLE END

See also:

Finding a Matching Section Delimiter

Finding Text


Search & Replace Command (Text Editor)
Search & Replace Command (Utilities Menu)

Shortcuts

Searches from the insertion point for specified text in the current file and replaces it.

Click Button 1 on any item in this dialog box for information on that item:

If the Text Editor finds the search text when the Confirm Each Change option is turned on, a dialog box appears. Click Button 1 on any item in this dialog box for information on that item:

After you finish using the Search & Replace command, you can choose Find Text, Find Next, or Find Previous (Utilities menu) to locate the search text again.

See also:

Finding Text

Finding & Replacing Text


Match Upper/Lowercase

Finds only text that has the same capitalization as the text entered in the Search For box and replaces it with the same capitalization as the text in the Replace With box.


Search & Replace Dialog Box (Text Editor)
 Search & Replace dialog box

Click Button 1 on any item in this dialog box for information on that item:


Text Size Commands (Text Editor)
Text Size Commands (Options Menu)

Shortcuts

Change all text in the file to a specified point size.

A variety of text sizes between 6 and 96 points are available for monospace TrueType fonts installed on your computer. The Text Editor supports only monospace fonts.

The Text Size drop-down list box on the toolbar also displays the current text size. You can type a text size or choose a text size in this drop-down list box.

See also:

Changing the Text Size

Changing the Font


Font Commands (Text Editor)
Font Commands (Options Menu)

Shortcuts

Change all text in the current file to a specified font.

MAX+PLUS II provides any monospace fonts installed on your computer.

Font menu commands apply the specified font to all text in the file, but preserve existing text sizes.

The Font drop-down list box on the toolbar also displays the current font. You can type a font name or choose a font in this drop-down list box.

See also:

Changing the Font


Tab Stops Command (Text Editor)
Tab Stops Command (Options Menu)

Specifies the number of spaces represented by each tab stop.

Click Button 1 on any item in this dialog box for information on that item:

When you press Tab, the insertion point moves ahead to the next tab stop.

See also:

Setting the Tab Stops


Tab Stop

Specifies the number of spaces that the Tab key represents.

You can enter any integer between 1 and 16; the default is 4.


Tab Stops Dialog Box (Text Editor)
 Tab Stops dialog box

Click Button 1 on any item in this dialog box for information on that item:


Auto-Indent Command (Text Editor)
Auto-Indent Command (Options Menu)

Turns automatic indentation on or off for subsequent text entry.

When Auto-Indent is turned on and you press Enter, the insertion point moves to the next line and is automatically indented to the column number of the first character on the previous line. If no characters were typed in the previous line, the insertion point moves to the column number of the last tab or space character typed.

You can use the automatic indenting feature to easily align text without having to press Tab or Space to move the insertion point to the appropriate column number.

See also:

Indenting Text

Setting the Tab Stops


Syntax Coloring Command (Text Editor)
Syntax Coloring Command (Options Menu)

Turns the Syntax Coloring feature on and off.

Syntax Coloring displays keywords and other elements of text in a TDF in different colors to distinguish them from other forms of syntax.

See also:

Using Syntax Coloring in Text Files


Specify Macrofunction Dialog Box

Specifies the name of the lower-level macrofunction you wish to open. This dialog box appears if you choose Hierarchy Down (File menu) after selecting a decimal group name.

Because the decimal group name refers to multiple macrofunctions, MAX+PLUS II cannot determine which macrofunction you wish to open. The Specify Macrofunction dialog box allows you to specify a single instance of the macrofunction.

Click Button 1 on any item in this dialog box for information on that item:

See also:

Navigating the Hierarchy


Ambiguous Macrofunction Name

Displays the decimal group name you selected before choosing Hierarchy Down (File menu). Since this name refers to multiple macrofunctions, it is ambiguous.


Specify a Single Macrofunction Name

Specifies the group member, i.e., the macrofunction, you wish to open. Enter the name of a single macrofunction that is part of the group.


Specify Macrofunction dialog box

Click Button 1 on any item in this dialog box for information on that item:


MAX+PLUS II Text Editor (plain)
 Text Editor Window


MAX+PLUS II Text Editor (callouts)
 Text Editor Window


Timing Analyzer Basic Tools
Basic Tools

Analysis Displays

Delay Matrix

Registered Performance

Setup/Hold Matrix

Buttons

List Paths

Start

Stop

Input & Output Files

Assignment & Configuration File (.acf)

ACF Format

Simulator Netlist File (.snf)

Timing Analyzer Output File (.tao)

MAX+PLUS II Initialization & System Files

maxplus2.idx File

maxplus2.ini File

Probe, Resource & Device Assignments

Clique Assignments

Connected Pin Assignments

Device Assignments

Logic Option Assignments

Pin, Location & Chip Assignments

Probe Assignments

Timing Assignments

Status Bar & Toolbar

Status Bar

Toolbar

Widgets

Progress Bar


Delay Matrix Display (Timing Analyzer)
Delay Matrix Display

Displays the results of propagation delay analysis. Show me.

The Delay Matrix display is the default analysis display; you can also select it with the Delay Matrix command (Analysis menu). If you are using default timing tagging, the display is blank before you run the Timing Analyzer. Otherwise, the matrix shows all source nodes and destination nodes that have been selected with Timing Analysis Source and Timing Analysis Destination (Node menu). Destination node names are listed across the top of the matrix; source node names are listed along the left side.

The matrix is filled in after you run the Timing Analyzer. By default, each cell in the matrix shows the minimum and maximum propagation delays between the two nodes. A single delay time shows that all delays are the same length. You can use Time Restrictions (Options menu) to exclude the minimum or the maximum delays from the display, and to restrict the lengths of the delay paths used for the analysis. You can also exclude all logic that feeds a node from the analysis with Timing Analysis Cutoff (Node menu). An empty cell indicates that no connection exists between the two nodes, or that there is a flipflop between them. The Timing Analyzer cannot calculate a propagation delay that passes through the primary (data) input to a flipflop or the Clock Enable input of a DFFE, JKFFE, SRFFE, or TFFE flipflop.

You can select a matrix cell and choose List Paths to open a Message Processor window that lists all propagation delays calculated between the two nodes. The Message Processor lists all paths, including paths not shown in the cell. You can use the Message Processor’s Locate button to locate and display each delay path between the two nodes in the appropriate design file(s).

See also:

Changing the Matrix Cell Width

Choosing an Analysis Mode

Listing & Locating Signal Paths

Running a Timing Analysis

Specifying Time Restrictions

Starting & Stopping the Timing Analyzer


Registered Performance Display (Timing Analyzer)
Registered Performance Display

Shows the worst-case registered performance as given by the minimum required Clock period and the maximum Clock frequency for every Clock signal in the circuit. Show me.

The Registered Performance display is selected with Registered Performance (Analysis menu). The display fields are blank until you run the Timing Analyzer.

Performance is calculated on the basis of all source nodes and destination nodes selected with Timing Analysis Source and Timing Analysis Destination (Node menu). You can also restrict the lengths of the delay paths used for the analysis with Time Restrictions (Options menu), and exclude nodes from the analysis with Timing Analysis Cutoff (Node menu). If you do not tag source and destination nodes, the Timing Analyzer uses default timing tagging.

After the timing analysis is finished, the following information is displayed:

Field:	Definition:

Clock	Shows the name of the Clock signal analyzed in the current timing analysis. The Timing Analyzer first displays the Clock signal with the worst-case registered performance overall. You can select a different Clock signal name from the drop-down list box to view its registered performance.

Source	Displays the name of the performance-limiting source node, which is always the Q output of a flipflop, for the specified Clock signal.

Destination	Displays the name of the performance-limiting destination node, which is always the data input to a flipflop, for the specified Clock signal.

Clock Period	Shows the minimum Clock period required for registered logic for the specified Clock signal; the minimum Clock period equals the maximum delay from the Q output of a flipflop to the data input of a flipflop, plus the internal setup time and propagation delay through the flipflop.

Frequency	Shows the maximum Clock frequency for the specified Clock signal (= 1/Clock Period).

The meter in the center of the window provides a graphical representation of the time displayed in the Frequency field. The Timing Analyzer cannot calculate registered performance for a signal path that passes through the primary (data) input to a flipflop.

You can choose List Paths to open a Message Processor window that lists all propagation delays calculated between the two nodes. The delays shown also include the internal setup time and the propagation delay through the flipflop. You can use the Message Processor’s Locate button to locate and highlight each signal path between the two nodes in the appropriate design file(s).

See also:

Choosing an Analysis Mode

Listing & Locating Signal Paths

Running a Timing Analysis

Specifying Time Restrictions

Starting & Stopping the Timing Analyzer


Setup/Hold Matrix Display (Timing Analyzer)
Setup/Hold Matrix Display

Shows the results of setup and hold time analysis. Show me.

The Setup/Hold Matrix display is selected with Setup/Hold Matrix (Analysis menu). If you are using default timing tagging, the display is blank before you run the Timing Analyzer. Otherwise, the matrix shows all source nodes and destination nodes that have been selected with Timing Analysis Source and Timing Analysis Destination (Node menu). Destination "nodes" are always flipflops (or latches), which are listed along the left side of the matrix. The source nodes, which drive the data or Clock Enable inputs, are listed below each flipflop (or latch) name. The source nodes that drive the Clock (or Latch Enable) inputs to the flipflops (or latches) are listed across the top of the matrix. You can use Time Restrictions (Options menu) to exclude the minimum or the maximum delays from the display, and to restrict the lengths of the delay paths used for the analysis. You can also exclude nodes from the analysis with Timing Analysis Cutoff (Node menu).

The matrix is filled in after you run the Timing Analyzer. Each cell in the matrix shows the setup time and hold time required for the input pins that feed the Clock (or Latch Enable) and data or Clock Enable inputs to the destination flipflop (or latch). A negative hold time is possible if a data (or Clock Enable) input signal can be released from the pin before the active transition occurs at the Clock (or Latch Enable) pin.

You can select a matrix cell and choose List Paths to open a Message Processor window that lists all signal paths calculated between the source and destination nodes. The Message Processor lists all paths, including paths not shown in the cell. You can use the Message Processor’s Locate button to locate and highlight each signal path between the source and destination nodes in the appropriate design file(s).

See also:

Changing the Matrix Cell Width

Choosing an Analysis Mode

Listing & Locating Signal Paths

Running a Timing Analysis

Starting & Stopping the Timing Analyzer


List Paths Button (Timing Analyzer)
List Paths Button

Opens the Message Processor window and lists all delay paths for the selected source nodes and destination nodes. Show me

List Paths becomes available only after you have run the Timing Analyzer. In the Delay Matrix or Setup/Hold Matrix display, you must first select a cell to specify the nodes whose paths you wish to list. In the Registered Performance display, you must select a Clock signal name from the drop-down list box to specify the nodes.

After you choose List Paths, the Message Processor displays a list of messages that show all possible paths between the nodes represented in the display. In the Registered Performance analysis mode, the message shows the delay from the Q output of a flipflop to the data input of a flipflop, plus the internal setup time and propagation delay through the flipflop. You can select a message and choose Locate to find and highlight the path between the two nodes in the design file(s) for the project.

When the List Only Longest Path (Options menu) command is turned on, List Paths shows only the longest delay path between any pair of nodes.

See also:

Listing & Locating Signal Paths


Start Button (Timing Analyzer)
Start Button

Begins timing analysis. Show me

The type of analysis the Timing Analyzer performs is set with the Delay Matrix, Setup/Hold Matrix, or Registered Performance command (Analysis menu).

Timing analysis is performed under the conditions specified with the Time Restrictions (Options menu) and Timing Analysis Cutoff (Node menu) commands. All nodes and groups selected with the Timing Analysis Source and Timing Analysis Destination commands (Node menu) in the Timing Analyzer, Graphic Editor, Text Editor, and Waveform Editor are included in the analysis. If no nodes or groups are tagged as source or destination nodes, the Timing Analyzer uses default timing tagging.

See also:

Choosing an Analysis Mode

Running a Timing Analysis

Starting & Stopping the Timing Analyzer

Specifying Time Restrictions

Tagging Timing Analysis Source or Destination Nodes

Tagging Timing Analysis Cutoff Nodes


Stop Button (Timing Analyzer)
Stop Button

Stops the timing analysis. Show me

Stop halts the timing analysis. You can restart it from the beginning with the Start button.

See also:

Starting & Stopping the Timing Analyzer


Timing Analyzer Output File (.tao) Description
Timing Analyzer Output File (.tao)

An ASCII text file (with the extension .tao) that contains the results of a timing analysis.

The .tao file is created after a timing analysis with the Save Analysis As (File menu) command.

The contents of the .tao file depend on the type of analysis that was saved in the file, i.e., a Delay Matrix, Setup/Hold Matrix, or Registered Performance analysis.

The file icon for a .tao file with the same filename as the top-level design file in the current hierarchy tree appears in the Hierarchy Display window.

See also:

Printing the Timing Analysis

Saving a Timing Analysis to a File


Progress Bar (Timing Analyzer)
Progress Bar

Shows how much of the current analysis has been completed. Show me

After you choose Start or Analyze Timing to begin timing analysis, the progress bar shows how much of the analysis has been completed. When the progress bar reaches 100%, you can analyze the outputs or specify a different type of analysis and run the Timing Analyzer again.

See also:

Starting & Stopping the Timing Analyzer


Timing Analyzer Contents
Timing Analyzer Help Contents

Introduction

Basic Tools

Commands

Procedures

Golden Rules

Shortcuts

Messages


Timing Analyzer Introduction
Introduction

The MAX+PLUS II Timing Analyzer allows you to analyze the performance of a project after it has been synthesized by the Compiler. You can trace all signal paths in the project, determining critical speed paths and paths that limit its performance. Show me

How Does the Timing Analyzer Work?

After you successfully compile your project, you can analyze its performance with the MAX+PLUS II Timing Analyzer. The Timing Analyzer uses the timing SNF generated during compilation, as well as device hardware information from the DMF for the device(s) used in the project. If you are compiling a super-project for multi-project simulation and generate a linked SNF that contains timing information only, you can also use the linked SNF to run a timing analysis.

The Timing Analyzer offers three types of analysis:

Delay Matrix	Analyzes the propagation delay paths between multiple source and destination nodes, and displays them in a matrix that shows the shortest and longest paths between them.

Registered Performance	Analyzes registered logic, determining the performance-limiting delay, minimum Clock period, and maximum Clock frequency for the project.

Setup/Hold Matrix	Calculates the minimum required setup and hold times from input pins to the data, Clock, Clock Enable, and Latch Enable inputs to flipflops and latches.

Default timing tagging is provided for each type of analysis, eliminating the need to tag (select) individual nodes for analysis. As an alternative, you can use the Timing Analyzer to tag multiple source and destination nodes to be included in the analysis, or tag nodes directly in design file(s). In either case, if you tag specific nodes, the default tagging is canceled.

The Timing Analyzer also allows you to exclude a signal path from timing analysis by tagging a node as a cutoff node. When a cutoff node is tagged, all signals that use the node are excluded from the analysis. You can also define the maximum and minimum delays to be included in the analysis, and restrict the lengths of paths shown in the Delay Matrix display.

After the timing analysis is completed, the Timing Analyzer--in conjunction with the Message Processor--allows you to list the delay path(s) associated with a particular source and destination node. You can then select and locate a delay path in the project’s original design file(s).

You can also save the results of a timing analysis to a Timing Analyzer Output File or print the results directly from the Timing Analyzer.

Where to Start

Altera offers a variety of information to help you analyze designs with MAX+PLUS II and the Timing Analyzer.

On-Line Help

On-line help supplies complete reference and how-to information on analyzing the timing of your project.

Timing Analyzer Help Contents provide access to all on-line Timing Analyzer Help.

Timing Analyzer Golden Rules summarize essential guidelines and recommendations for using the Timing Analyzer.

Recommended Reading

Additional Altera publications help you understand MAX+PLUS II and the Timing Analyzer. The following application notes and briefs are relevant to using the Timing Analyzer:

AB94 (Solutions to Design Timing Problems)

AB100 (Understanding Classic, MAX 5000 & MAX 7000 Timing)

See also:

Compiler Introduction

How to Use MAX+PLUS II Help

Third-Party Interfaces Introduction


Timing Analyzer Golden Rules
Golden Rules

The following golden rules will help you use MAX+PLUS II and the Timing Analyzer effectively:

Timing Analyzer Golden Rules

Default timing tagging is provided for each type of analysis, eliminating the need to tag individual nodes.

Not all delay paths are relevant to your project. Locate the critical paths in your project and use the Timing Analysis Cutoff (Node menu) to exclude the delay paths that are not critical.

General MAX+PLUS II Golden Rules

When you start work on a new design file, name it as the current project with Project Name (File menu) right away so that you can compile it easily. You can always change the project name later.

Use the built-in hierarchy traversal features in MAX+PLUS II to move between design files for the current hierarchy. To open a lower-level file in a hierarchy, open the top-level file and then use the Hierarchy Display window or Hierarchy Down (File menu) to open the lower-level files. If you choose Open (File menu) or Retrieve (File menu) to open a lower-level file, it is considered to be the top of a different hierarchy tree, and resource, device, and probe assignments that you enter are saved only for that hierarchy, not for the project.

When you create an ancillary file for a project, the icon for the file will appear in the Hierarchy Display if you use the same filename as the project.

Don’t edit any MAX+PLUS II system files, including HIFs, maxplus2.idx and the maxplus2.ini files.

Use the Save As (File menu) command if you wish to rename a design file or an ancillary file. Don’t rename design files from outside of MAX+PLUS II system (e.g., from DOS or with the Windows File Manager).

When you have completed a project, use Project Archive (File menu) to ensure that you save a complete backup copy of all project files that will not be affected by future edits or deletions.


Timing Analyzer--Context-Sensitive Help
Timing Analyzer Context-Sensitive Help

Context-sensitive help is available for all Timing Analyzer commands, dialog boxes, and messages, and the following basic tools:

Analysis Displays

Delay Matrix

Registered Performance

Setup/Hold Matrix

Buttons

List Paths

Start

Stop

Status Bar and Toolbar

Status Bar

Toolbar

Widgets

Progress Bar

For information on other basic tools, see Timing Analyzer Basic Tools.

See also:

Getting Context-Sensitive Help


Timing Analyzer Shortcuts
Shortcuts

The following list provides shortcuts for Timing Analyzer commands:

Command:	Shortcut:

Context-Sensitive Help	Shift+F1 or

Cascade	Shift+F5

Close	Alt+F4

Compiler

Delay Matrix

Exit MAX+PLUS II	Alt+F4 or double-click Button 1 on the Application Control Menu box

Find Next	Ctrl+N

Find Previous	Ctrl+Shift+N

Find Text	Ctrl+F or

Floorplan Editor

Hierarchy Display

Hierarchy Project Top	Ctrl+T or

New

Next	Ctrl+F6

Open	Ctrl+O or

Print	Ctrl+P or choose [image] to print the current timing analysis with the settings last specified with the Print dialog box.

Programmer

Project Name	Ctrl+J or

Project Save & Check	Ctrl+K or

Project Save & Compile	Ctrl+L or

Project Save & Simulate	Ctrl+Shift+L or

Registered Performance

Save Analysis As

Setup/Hold Matrix

Simulator

Switch To	Ctrl+Esc

Tile Horizontally	Shift+F4

Timing Analyzer

Timing Analysis Cutoff	Ctrl+Alt+C

Timing Analysis Destination	Ctrl+Alt+D

Timing Analysis Source	Ctrl+Alt+S

See also:

Selecting Text


Timing Analyzer Procedures
Procedures

Assignments & Compiler Configuration Settings

Assigning a Clique

Assigning a Device

Assigning a Pin, Location, or Chip

Assigning a Probe

Assigning an Individual Logic Option or Synthesis Style

Assigning Connected Pins

Assigning Individual Timing Requirements

Bank-Annotating Assignments for a Project

Clearing Assignments for a Project

Converting an Obsolete Assignment Format

Copying a Resource Assignment

Defining a Logic Synthesis Style

Deleting an Assignment

Guidelines for Working with Assignments

Ignoring Project Assignments during Compilation

Logic Synthesis Style & Logic Option Rules

Searching the Node Database

Specifying Devices for Automatic Device Selection

Specifying Global Project Classic & MAX Device Options

Specifying Global Project MAX 7000S Device Options

Specifying Global Project FLEX 8000 Device Options

Specifying Global Project FLEX 10K Device Options

Specifying Global Project Logic Synthesis Settings

Specifying Global Project Parameters

Specifying Global Project Security Bit & Reserved Resource Settings

Specifying Global Project Timing Requirements

Specifying Individual Classic & MAX Device Options

Specifying Individual MAX 7000S Device Options

Specifying Individual FLEX 10K Device Options

Specifying Individual Device Security & Turbo Bit Options

Specifying Individual FLEX 8000 Device & Pin Options

File Management

Creating a New File

Deleting a file

Opening a File

Hierarchy

Navigating the Hierarchy

Updating the Hierarchy

Input & Output Files

Saving a Timing Analysis to a File

MAX+PLUS II Management

Changing Colors in MAX+PLUS II

Closing a MAX+PLUS II Application

Creating & Using a Local Copy of the maxplus2.ini File

Exiting from MAX+PLUS II

Obtaining a Site License Registration Code

Registering Your Software

Setting MAX+PLUS II Preferences

Setting Up Your Authorization Code or Network License File

Specifying a User Library

Starting MAX+PLUS II Applications

Switching between MAX+PLUS II Applications

Messages

Getting Help on a Message

Locating the Source of a Message

Nodes

Clearing Timing Analysis Tags

Cutting Off Clear & Preset Timing Paths

Cutting Off I/O Pin Feedback

Tagging Timing Analysis Cutoff Nodes

Tagging Timing Analysis Source & Destination Nodes

Project Management

Archiving a Project

Changing the Project Name

Compiling a Project

Running the Timing Analyzer

Recalculating the Analysis Automatically

Running a Timing Analysis

Saving a Timing Analysis to a File

Starting & Stopping the Timing Analyzer

Text

Finding Text

Selecting Text

Timing Analysis

Choosing an Analysis Mode

Listing & Locating Signal Paths

Printing the Timing Analysis

Specifying Time Restrictions

Window Display

Changing the Matrix Cell Width


Saving a Timing Analysis to a File (Timing Analyzer)
Saving a Timing Analysis to a File

The ASCII-format Timing Analyzer Output File records the results of the timing analysis that is currently displayed in the Timing Analyzer window.

To create a TAO File:

1.	Open the Save Analysis As dialog box by choosing Save Analysis As (File menu) or using a shortcut.

2.	If necessary, select a different drive and/or directory.

3.	Select an existing filename in the Files box or type a filename in the File Name box. The filename can contain up to eight name characters. The default filename displayed in the File Name box is <project name>.tao. If you type or select the name of an existing file, it will be overwritten. If you type the name of a directory that does not exist, MAX+PLUS II will offer to create it for you.

4.	If you wish to create a file without any extension, type an extension, or type a period (.) after the filename. Otherwise, the extension .tao is automatically appended to the filename.

5.	Choose OK.

If you selected the name of an existing file, you are asked to choose between overwriting the file or appending the current analysis to it.

See also:

Timing Analyzer Output File (.tao)


Cutting Off Clear & Preset Timing Paths (Timing Analyzer)
Cutting Off Clear & Preset Timing Paths

You can set up the Timing Analyzer to cut off the timing paths for all Clear and Preset signals in a project, so that the delays along these paths are not included in the timing analysis. Cutting off these signal paths may help eliminate invalid paths from the timing analysis.

To cut off Clear & Preset timing paths during timing analysis:

Turn on Cut Off Clear & Preset Paths (Options menu).

Cut Off Clear & Preset Paths is unrelated to the Cut All Clear & Preset Timing Paths option in the Global Project Timing Requirements (Assign menu) dialog box. The Timing Analyzer’s Cut Off Clear & Preset Paths command controls post-compilation timing analysis, while the Global Project Default Timing command option helps guide compilation.

See also:

Cutting Off I/O Pin Feedback

Running a Timing Analysis

Tagging Timing Cutoff Nodes


Cutting Off I/O Pin Feedback (Timing Analyzer)
Cutting Off I/O Pin Feedback

You can set up the Timing Analyzer to cut off the delay that is fed back from a bidirectional (BIDIR or BIDIRC) pin.

Cutting off I/O pin feedback is especially useful when a bidirectional pin is connected directly or indirectly to both the input and the output of a latch. This type of feedback path is continuous since it is not interrupted by any clocked logic primitives. As additional, interconnected latch-to-pin loops are added, the number of hidden paths grows exponentially, e.g., when latches are used with bidirectional buses. Example

To cut off I/O pin feedback during timing analysis:

Turn on Cut Off I/O Pin Feedback (Options menu).

See also:

Cutting Off Clear & Preset Timing Paths

Running a Timing Analysis

Tagging Timing Cutoff Nodes

Tagging Timing Source & Destination Nodes


Recalculating the Analysis Automatically (Timing Analyzer)
Recalculating the Analysis Automatically

You can set up the Timing Analyzer to automatically recalculate the current timing analysis whenever the Compiler creates a new timing SNF for the current project or a new linked SNF that contains timing information only.

To automatically recalculate the timing analysis:

1.	Choose Auto-Recalculate (Options menu).

2.	Recompile the project with Timing SNF Extractor or Linked SNF Extractor (Processing menu) turned on.

See also:

Compiling the Project

Creating a Timing Simulator Netlist File

Running a Timing Analysis


Starting & Stopping the Timing Analyzer

To start the Timing Analyzer:

Choose Start in the Timing Analyzer window.

or:

Choose Analyze Timing (Utilities menu) in the Graphic, Text, or Waveform Editor.

To stop the Timing Analyzer:

Choose Stop in the Timing Analyzer window.

See also:

Running a Timing Analysis


Changing the Matrix Cell Width (Timing Analyzer)
Changing the Matrix Cell Width

You can adjust width of the cells in the Timing Analyzer’s Delay Matrix and Setup/Hold Matrix displays to suit your individual needs.

To change the matrix cell width:

1.	Choose Cell Width (Options menu). The Cell Width dialog box is displayed.

2.	Type an integer between 4 and 128. The number is interpreted as the number of average-width characters and is not a precise figure. An average-width character is wider than an "i" but narrower than a "w".

3.	Choose OK.


Finding Text (Timing Analyzer)
Finding Text

To find a specific string of text:

1.	Select a cell in the matrix to define where the search will begin.

2.	Open the Find Text dialog box by choosing Find Text (Utilities menu) or using a shortcut.

3.	Type up to 256 characters of search text, including optional wildcard characters, in the Search For box.

4.	If you wish to find occurrences of the search text that are whole words only, turn on the Whole Word option.

5.	Turn on Up or Down to search up (top-to-bottom and left-to-right) or down (bottom-to-top and right-to-left) within the display.

6.	Choose OK to begin the search.

7.	If you wish to find the next or previous occurrence of the search text after the first occurrence has been found, choose Find Next or Find Previous (Utilities menu).


Choosing an Analysis Mode (Timing Analyzer)
Choosing an Analysis Mode

The Timing Analyzer provides three analysis modes, each of which provides default timing tagging.

To choose an analysis mode, select one of the following commands from the Analysis menu:

Command:	Analysis Type:

Delay Matrix	Propagation delay analysis, which analyzes the propagation delay paths between multiple source and destination nodes, and lists the shortest and longest paths between them. This mode is selected by default.

Setup/Hold Matrix	Setup and hold time analysis, which determines the minimum required setup and hold times from input pins to the data, Clock, Clock Enable, and Latch Enable inputs of flipflops and latches.

Registered Performance	Registered logic performance analysis, which determines the performance-limiting delay, minimum Clock period, and maximum Clock frequency for all Clock signals in the project.

See also:

Running a Timing Analysis


Listing & Locating Signal Paths (Timing Analyzer)
Listing & Locating Signal Paths

After you run a timing analysis, you can list selected signal paths and locate them in the original design file(s) for the project.

To list and locate signal paths after running a timing analysis in the Delay Matrix or Setup/Hold Matrix display:

1.	Select a cell with Button 1.

2.	If you wish to list only the longest signal path between each pair of source and destination nodes, turn on List Only Longest Path (Options menu).

3.	Choose the List Paths button. The Message Processor opens automatically. For each path in the project that connects the pair of nodes represented by the matrix cell, the Message Processor window lists a message that gives the propagation delay.

4.	In the Message Processor window, select a message and click Button 1 on the right side of the Locate button or double-click Button 1 on the message. The first time you choose Locate, MAX+PLUS II automatically locates and highlights the node or symbol that is the source of the signal in the project’s design file(s).

5.	Since paths are broken down into their individual component parts, you must choose Locate repeatedly to highlight the next portion of the delay path until you have traced the entire path.

To list and locate signal paths after running a timing analysis in the Registered Performance display:

1.	Select a Clock signal name from the drop-down list box.

2.	If you wish to list only the longest signal path between each pair of source and destination nodes, turn on List Only Longest Path.

3.	Choose List Paths. The Message Processor opens automatically. For each path that connects the pair of performance-limiting source and destination nodes shown in the Registered Performance display, the Message Processor window lists a message that gives the propagation delay.

4.	Repeat steps 4 and 5 above.

See also:

Locating the Source of a Message


Printing the Timing Analysis (Timing Analyzer)
Printing the Timing Analysis

To print the current timing analysis:

1.	Open the Print dialog box by choosing Print (File menu) or using a shortcut.

2.	Turn on the desired printing options.

3.	Choose OK.

To change the printer and printer options:

1.	Choose Print Setup (File menu). The Print Setup dialog box is displayed.

2.	Select the correct printer.

3.	Choose Setup to change the printer options that are available with your printer. Choose OK when you are done to close the Setup dialog box.

4.	Choose OK in the Print Setup dialog box.


Specifying Time Restrictions (Timing Analyzer)
Specifying Time Restrictions

You can use Time Restrictions or List Only Longest Path (Options menu) to specify time restrictions during a timing analysis. Time Restrictions allows you to define the maximum and minimum delay paths and the types of delay paths displayed in the Delay Matrix display, as well as the length or number of paths to list in the Registered Performance display. List Only Longest Path designates that only the longest delay path(s) be listed in the Delay Matrix or Setup/Hold Matrix display.

To restrict the lengths of delay paths in a Delay Matrix timing analysis:

1.	Choose Delay Matrix (Analysis menu) or use a shortcut.

2.	Choose Time Restrictions. The Time Restrictions dialog box is displayed.

3.	If you wish to specify a minimum path length, turn on the Greater Than option and type a time. The time you enter should be followed immediately (i.e., with no space in between) by a time unit; the default is ns. The default minimum path length is 0.

4.	If you wish to specify a maximum path length, turn on the Less Than option and type a time. The time you enter should be followed immediately (i.e., with no space in between) by a time unit; the default is ns. The default shown is over 214 milliseconds, the maximum time value permitted in the Timing Analyzer.

5.	Choose Show All Paths, Show Only Longest Paths, or Show Only Shortest Paths under Delay Matrix Options to specify whether you wish to show all paths, only the longest paths, or only the shortest paths in the Delay Matrix display, respectively. The default is Show All Paths.

6.	Choose OK to save the restrictions.

To force the Message Processor to list only the longest delay path when you chose List Paths in the Delay Matrix or Setup/Hold Matrix analysis mode:

1.	Choose Delay Matrix or use a shortcut.

or:

Choose Setup/Hold Matrix (Analysis menu) or use a shortcut.

2.	Turn on List Only Longest Path.

To determine the lengths or number of paths to list in a Registered Performance timing analysis:

1.	Choose Registered Performance (Analysis menu) or use a shortcut.

2.	Choose Time Restrictions. The Time Restrictions dialog box is displayed.

3.	Select Number of Paths per Clock to List  and type the number of worst-case delay paths to list per Clock signal. Type an integer between 1 and 99; the default is 10 paths.

or:

Select List Paths with Frequency Less Than and type the maximum frequency for the paths to be listed. The number you enter should be followed immediately (i.e., with no space in between) by a time unit; the default is MHz. The default frequency is 10.0MHz.

See also:

Choosing an Analysis Mode

Cutting Off I/O Pin Feedback

Listing & Locating Signal Paths

Tagging Timing Analysis Cutoff Nodes


-------------------BEGINNING OF NON-TRANSLATED TEXT--------------------

October 22 	STAN_PATHS_LISTED and STAN_SUCCESS were changed to HTAN_PATHS_LISTED and HTAN_SUCCESS. Topic strings ($) were not changed, only the context-sensitive help link.

This file contains messages both from the Timing Analyzer and from the Compiler’s timing checker. The two sets of messages are kept separate

Messages from tanmsgs.msg and tpdmsgs.msg that are documented elsewhere (not in this file):

STAN_SNF_IS_IN_USE	simess.mac

FTPD_SNF_IS_IN_USE	simess.mac

QTAN_STOP_ANALYSIS	comess.mac

STAN_TOO_MANY_NODES	wemess.mac

STAN_TOO_MANY_NODES_ABORTED	wemess.mac

Messages from applications/files that are documented here:

SWPR_IP_COPIES_ERROR	wprmsgs.msg

--------------------------END OF NON-TRANSLATED TEXT-------------------


Can’t analyze timing -- no SNF exists for the project
 Can’t analyze timing -- no timing SNF exists for the project

CAUSE:	You chose Analyze Timing (Utilities menu) in the Graphic, Text, or Waveform Editor to run the Timing Analyzer, but no timing SNF exists for the current project. (Timing analysis is not available when a functional SNF exists for the project.)

ACTION:	Recompile the current project with the Compiler's Timing SNF Extractor (Processing menu) command turned on to create a timing SNF, then run the Timing Analyzer.

See also:

MAX+PLUS II Messages

Message Format


 Can’t create fonts -- reinstall Windows fonts

CAUSE:	The Windows system Helvetica fonts are not installed correctly.

ACTION:	Reinstall the Windows fonts. See the Microsoft Windows User’s Guide for more information.

See also:

MAX+PLUS II Messages

Message Format


 Can’t find text <text> in matrix

CAUSE:	You chose Find Text (Utilities menu) and typed a string of search text. The Timing Analyzer cannot find a node name that matches the search text in the current matrix.

ACTION:	Check to be sure that you typed the text correctly. You may also use wildcard characters to find help find a node.

See also:

Finding Text

MAX+PLUS II Messages

Message Format


 Can’t list more than <number> Clock signals -- others are ignored

CAUSE:	You chose Registered Performance  (Analysis menu) and tried to run a timing analysis, but your project contains more Clock signals than the Timing Analyzer can list.

ACTION:	Compile lower-level design files in the project and analyze the performance of the lower-level functions.

See also:

MAX+PLUS II Messages

Message Format

Running a Timing Analysis


 Cell width must be between <number> and <number>

CAUSE:	You used Cell Width (Options menu) to set the width of the cells in the Delay Matrix or Setup/Hold Matrix display, but the number you entered is illegal.

ACTION:	Enter a whole number between 4 and 128.

See also:

Changing the Matrix Cell Width

MAX+PLUS II Messages

Message Format


Delay path from <node name> to <node name>: <time>
 Delay path [for <text>] from <node name> to <node name>: <delay time> [Clock period <time>]

CAUSE:	This information message lists the delay paths after you have chosen the List Paths button. If you used the Registered Performance analysis mode, this message shows the delay between the data output of one register and the data input of another register, as well as the Clock period, which includes additional delays for the internal setup time and propagation delay through the register.

ACTION:	No action is required. You can use the Message Processor’s Locate button to locate the path in the design files for the project.

See also:

Listing & Locating Signal Paths

MAX+PLUS II Messages

Message Format


Delay path from <node name> to <node name>: <time>
 Delay path from <node name> to <node name>: <delay time> [Clock period <time>]

CAUSE:	This information message lists the delay paths after you have chosen the List Paths button. If you used the Registered Performance analysis mode, this message shows the delay between the data output of one register and the data input of another register, as well as the Clock period, which includes additional delays for the internal setup time and propagation delay through the register.

ACTION:	No action is required. You can use the Message Processor’s Locate button to locate the path in the design files for the project.

See also:

Listing & Locating Signal Paths

MAX+PLUS II Messages

Message Format


No register-to-register paths exist for this project
 No register-to-register paths exist for this project -- Clock period represents the maximum toggle frequency of an individual register

CAUSE:	You chose Registered Performance (Analysis menu) and ran a timing analysis, but your project does not contain any register-to-register paths. This error could be the result of Timing Analysis Cutoff Nodes eliminating appropriate register-to-register paths from this analysis.

ACTION:	If your project contains no register-to-register paths, choose Delay Matrix or Setup/Hold Matrix (Analysis menu) for your Timing Analysis. If your project contains register-to-register paths, you may need to review your placement of Timing Analysis Cutoff Nodes.

See also:

Tagging Timing Analysis Cutoff Nodes

Choosing an Analysis Mode

MAX+PLUS II Messages

Message Format


 Finished listing [longest] delay path[s]

CAUSE:	You chose List Paths, and the Timing Analyzer has finished listing the delay path(s) in the Message Processor window.

ACTION:	No action is required. You can use the Message Processor’s Locate button to locate the path in the design files for the project.

See also:

Listing & Locating Signal Paths

MAX+PLUS II Messages

Message Format


Ignored illegal timing assignment <text>

CAUSE:	The specified <text> is not a legal timing assignment, so the Compiler has ignored it.

ACTION:	Delete or reenter the assignment.

See also:

Assigning Individual Timing Requirements

MAX+PLUS II Messages

Message Format


 Illegal path time value: <text>

CAUSE:	You chose the Time Restrictions (Options menu) command and typed the specified illegal path time value in the Greater Than or Less Than box. The minimum time value is 0; the maximum is 214.7483647 milliseconds. A common error is to add a space between the time value and the optional time unit, e.g., 10.0 ns instead of 10.0ns.

ACTION:	Enter the path time again with a legal value in the correct format.

See also:

MAX+PLUS II Messages

Message Format

Specifying Time Restrictions


 No source nodes feed Clock inputs of registers

CAUSE:	The Timing Analyzer tried to perform a Setup/Hold Matrix analysis and found that no nodes that are tagged as timing source nodes feed the Clock inputs of registers or Latch Enable inputs of latches. Therefore, it could not complete the analysis.

ACTION:	Be sure to tag source nodes that feed the Clock with Timing Analysis Source (Node menu) in the Timing Analyzer or the Graphic, Text, or Waveform Editor or clear all timng analysis tags and use default timing tagging. You may also need to edit the design file(s) for your project.

See also:

MAX+PLUS II Messages

Message Format

Tagging Timing Analysis Source or Destination Nodes


No valid <node type> nodes are tagged for the current analysis mode
 No valid <node type> nodes are tagged for the current timing analysis mode

CAUSE:	You started the Timing Analyzer, but none of the specified source or destination nodes tagged for timing analysis were valid for the current analysis mode. For example, you may have specified only combinatorial nodes for a Registered Performance analysis.

ACTION:	Specify source and destination nodes that are appropriate for the current analysis mode, clear all timing tags and use the default timing tagging provided in the Timing Analyzer, or change the analysis mode.

See also:

Choosing an Analysis Mode

Clearing Timing Analysis Tags

MAX+PLUS II Messages

Message Format

Running a Timing Analysis

Tagging Timing Analysis Source or Destination Nodes


 Number of copies must be an integer between <number> and <number>

CAUSE:	You used Print (File menu) to print the current file or timing analysis, and typed an illegal number in the Copies box.

ACTION:	Type a different value that lies within the specified range.

See also:

MAX+PLUS II Messages

Message Format

Printing the Timing Analysis

Printing a File (Timng Analyzer)


 SNF for project does not contain node <name>

CAUSE:	You tagged the specified node as a source destination, or cutoff, node in the Graphic, Text, or Waveform Editor, but the node does not exist in the SNF for the project. The node may have been eliminated from a timing SNF during logic synthesis or you may have selected an item that is not a node name.

ACTION:	Always select the name of a node that exists in the SNF for the project when you tag a node for timing analysis. The dialog boxes for the Timing Analysis Source, Timing Analysis Destination, and Timing Analysis Cutoff commands (Node menu) in the Timing Analyzer show only nodes that exist in the SNF. You can also use the dialog box for the Simulator’s Initialize command (Options menu) to list all nodes and groups that exist in the SNF.

See also:

MAX+PLUS II Messages

Message Format

Tagging Timing Analysis Cutoff Nodes

Tagging Timing Analysis Source or Destination Nodes


 Timing analysis canceled

CAUSE:	You chose Stop in the Timing Analyzer before it finished running the current timing analysis.

ACTION:	No action is required. You can restart the timing analysis from the beginning by choosing the Start button.

See also:

MAX+PLUS II Messages

Message Format


 Timing analysis completed

CAUSE:	The Timing Analyzer has finished running the timing analysis that you started by choosing the Start button in the Timing Analyzer or the Graphic, Text, or Waveform Editor’s Analyze Timing command (Utilities menu).

ACTION:	No action is required. You can examine the analysis display to read the results of the timing analysis.

See also:

MAX+PLUS II Messages

Message Format


 Timing Analyzer is running -- command ignored

CAUSE:	You entered a timing analysis-related command (i.e., Timing Analysis Source, Timing Analysis Destination, Timing Analysis Cutoff, Analyze Timing, or Clear All Timing Analysis Tags) in the Graphic, Text, or Waveform Editor. However, the Timing Analyzer is already running, so it has ignored your command. For example, you may have tried to tag a node in a GDF while the Timing Analyzer was performing an analysis on the project that contains the file.

ACTION:	Stop the Timing Analyzer or wait for the current timing analysis to finish before entering additional timing analysis commands.

See also:

MAX+PLUS II Messages

Message Format

Starting & Stopping the Timing Analyzer


 Too many destination nodes (<number>) are tagged

CAUSE:	You chose the Start button to start timing analysis, but the Timing Analyzer found that the number of nodesd tagged as timing destinations exceeded the maximum of 4,096. This error is most likely to occur when default timing tagging is used.

ACTION:	To reduce the number of timing destinations to less than 4,096, tag the timing destination nodes for analysis manually with the Timing Analysis Destination command (Node menu) in the Timing Analyzer or the Graphic, Text, or Waveform Editor.

See also:

MAX+PLUS II Messages

Message Format

Tagging Timing Analysis Source or Destination Nodes


 Too many source nodes (<number>) are tagged

CAUSE:	You chose the Start button to start timing analysis, but the Timing Analyzer found that the number of nodes tagged as timing sources exceeded the maximum of 4,096. This error is most likely to occur when default timing tagging is used.

ACTION:	To reduce the number of timing sources to less than 4,096, tag the timing source nodes for analysis manually with the Timing Analysis Source command (Node menu) in the Timing Analyzer or the Graphic, Text, or Waveform Editor.

See also:

MAX+PLUS II Messages

Message Format

Tagging Timing Analysis Source & Destination Nodes


-------------------BEGINNING OF NON-TRANSLATED TEXT--------------------

start of timing checker messages:

--------------------------END OF NON-TRANSLATED TEXT-------------------


Can’t provide fmax of <time> on <text> <name>. Current fmax is <time>.

CAUSE:	You entered the specified timing assignment for the specified register or Clock pin, but the Compiler could not achieve the desired performance. The actual performance achieved by the Compiler is displayed for your reference.

ACTION:	You may need to relax the timing assignments on some less critical portions of you project, or change the default timing assignments. Refer to Guidelines for Timing Assignments for information on how to use timing assignments effectively.

See also:

Assigning Individual Timing Requirements

MAX+PLUS II Messages

Message Format

Specifying Global Project Timing Requirements


Can’t provide <t.a.> of <time> from <name> to <text> [using <text>]. Current <t.a.> is <time>.
Can’t provide <timing assignment> of <time> from <name> to <text> [using <text>]. Current <timing assignment> is <time>.

CAUSE:	You entered the specified tpd, tsu, or tco timing assignment for the specified pair of nodes and/or pins, but the Compiler could not achieve the desired performance. The actual performance achieved by the Compiler is displayed for your reference.

ACTION:	You may need to relax the timing assignments on some less critical portions of your project, or change the default timing assignments. Refer to Guidelines for Timing Assignments for information on how to use timing assignments effectively.

See also:

Assigning Individual Timing Requirements

MAX+PLUS II Messages

Message Format

Specifying Global Project Timing Requirements


Found a total of <number> timing assignments that were not implemented

CAUSE:	The Compiler could not implement the specified number of timing assignments for your project. These assignments include all assignments entered in design files with Timing Requirements (Assign menu) and project default timing specified with Global Project Timing Requirements (Assign menu). Each individual timing assignments that was not implemented is reported in another message.

ACTION:	You may need to relax the timing assignments on some less critical portions of your project, or change the default timing assignments. Refer to Guidelines for Timing Assignments for information on how to use timing assignments effectively.

See also:

Assigning Individual Timing Requirements

MAX+PLUS II Messages

Message Format

Specifying Global Project Timing Requirements


Found ripple clock -- warning messages and Report File information on tco, tsu, and fmax may be incorrect

CAUSE:	Your project contains a ripple Clock. The MAX+PLUS II Compiler cannot accurately report information on project timing for signal paths that include ripple Clocks. Therefore, warning messages about timing assignments that are issued during compilation, as well as information on timing assignments in the Report File, may contain inaccurate information on tco, tsu, or fmax timing.

ACTION:	Use any or all of the Timing Analyzer’s analysis modes to check the timing of your project.

See also:

MAX+PLUS II Messages

Message Format

Running a Timing Analysis


Ignored timing assignment on node <name> -- it does not exist in the current SNF

CAUSE:	You entered a timing assignment on the specified node, but the node does not exist in the project’s design files or has been eliminated by logic synthesis and minimization. Therefore, it does not exist in the SNF for the synthesized project.

ACTION:	No action is required. If you wish to prevent this message from occurring again, delete the timing assignment on the specified node. Refer to Guidelines for Timing Assignments for information on how to use timing assignments effectively.

See also:

Deleting an Assignment

MAX+PLUS II Messages

Message Format

Moving a Probe or Resource Assignment (Graphic Editor)


Ignored timing assignment for <timing assignment> on <text> <name>

CAUSE:	You entered an unsupported timing assignment on the specified node or pin,The Compiler does not accept assignments of the specified type on the specified node or pin. If this message occurs for a BIDIR or BIDIRC pin/port, the timing assignment that causes the message may be located on the TRI buffer that feeds the specified pin.

ACTION:	No action is required. If you wish to prevent this message from occurring again, delete the timing assignment on the specified node or move it to an appropriate node. Refer to Guidelines for Timing Assignments for information on how to use timing assignments effectively.

See also:

Deleting an Assignment

MAX+PLUS II Messages

Message Format

Moving a Probe or Resource Assignment (Graphic Editor)


Input or bidirectional pin <name> has a <timing assignment> assignment but does not feed any <text>

CAUSE:	The specified pin has a timing assignment, but the assignment cannot be implemented because the pin does not feed any logic that is affected by the assignment. This message can occur if you enter a tpd or tco assignment on a pin that does not feed any OUTPUT or OUTPUTC pins, if you enter a tsu assignment on a pin that does not feed any registers, or if you enter a tco or fmax assignment on a pin that does not feed the Clock inputs of any registers.

ACTION:	No action is required. If you wish to prevent this message from occurring again, delete the timing assignment on the specified register or move it to an appropriate register. Refer to Guidelines for Timing Assignments for information on how to use timing assignments effectively.

See also:

Deleting an Assignment

MAX+PLUS II Messages

Message Format

Moving a Probe or Resource Assignment (Graphic Editor)


Output or bidirectional pin <name> has a <timing assignment> assignment but is not driven by any <text>

CAUSE:	The specified pin has a timing assignment, but the assignment cannot be implemented because the pin is not fed by any logic that is affected by the assignment. This message can occur if you enter a tpd assignment on a pin that is not fed by any INPUT or INPUTC pins, or if you enter a tco assignment on a pin that is not fed by any registers.

ACTION:	No action is required. If you wish to prevent this message from occurring again, delete the timing assignment on the specified pin or move it to an appropriate pin. Refer to Guidelines for Timing Assignments for information on how to use timing assignments effectively.

See also:

Deleting an Assignment

MAX+PLUS II Messages

Message Format

Moving a Probe or Resource Assignment (Graphic Editor)


Register <node name> has an fmax assignment but does not feed any other registers

CAUSE:	The specified register has a timing assignment, but the assignment cannot be implemented because it does not feed any other registers.

ACTION:	No action is required. If you wish to prevent this message from occurring again, delete the timing assignment on the specified register or move it to an appropriate register. Refer to Guidelines for Timing Assignments for information on how to use timing assignments effectively.

See also:

Deleting an Assignment

MAX+PLUS II Messages

Message Format

Moving a Probe or Resource Assignment (Graphic Editor)


Successfully implemented all timing assignments

CAUSE:	The Compiler has successfully implemented all of the timing assignments for your project, including all assignments entered in design files with Timing Requirements (Assign menu) and project default timing specified with Global Project Timing Requirements (Assign menu).

ACTION:	No action is required.

See also:

MAX+PLUS II Messages

Message Format


TRI buffer <net ID number> has a tpd or tco timing assignment but does not feed any bidirectional pins

CAUSE:	The specified TRI buffer has a tpd or tco timing assignment, but the assignment cannot be implemented because it does not feed any BIDIR or BIDIRC pins.

ACTION:	No action is required. If you wish to prevent this message from occurring again, delete the timing assignment on the specified TRI buffer or move it to an appropriate location. Refer to Guidelines for Timing Assignments for information on how to use timing assignments effectively.

See also:

Deleting an Assignment

MAX+PLUS II Messages

Message Format

Moving a Probe or Resource Assignment (Graphic Editor)


Too many timing assignment nodes...to report whether assignments have been implemented successfully
Too many timing assignment <text> nodes (<number>) in design file(s) to report whether timing assignments have been implemented successfully

CAUSE:	Your project contains too many nodes of the specified type for the Compiler to check whether the timing assignments you have entered have been implemented successfully. Therefore, Compiler cannot include information on the actual delays implemented in the device(s) in the Report File for the project. However, the lack of timing information in the Report File does not necessarily indicate that the timing assignments were not implemented.

The source nodes reported in this message can consist of INPUT and INPUTC pins, the input portions of BIDIR and BIDIRC pins, TRI buffers, and the Q outputs of registers. Destination nodes can consist of OUTPUT or OUTPUTC pins, the output portions of BIDIR and BIDIRC pins, and the data, Clock, and Clock Enable inputs to registers.

ACTION:	Use any or all of the Timing Analyzer’s analysis modes to check the timing of your project.

See also:

MAX+PLUS II Messages

Message Format

Running a Timing Analysis


Calculated frequency may not be accurate -- project uses multiple clocks from one or more pins

CAUSE:	When MAX+PLUS II compiled your project, it found multiple Clocks that are driven by one or more pins. The Clock period displayed by the Timing Analyzer represents only the register-to-register delays when all registers are clocked simultaneously. Therefore, the Timing Analyzer results are accurate only when the design is fully synchronous.

ACTION:	 If your project requires  multiple Clocks, you should perform exhaustive simulations to determine worst-case timing results.

See also:

MAX+PLUS II Messages

Message Format

Running a Timing Analysis

Timing Simulation Mode


Project has no SNF -- Can’t analyze timing

CAUSE:	You opened the Timing Analyzer, but no timing SNF exists for the current project. A timing SNF is required to perform a timing analysis. (A functional SNF does not include timing information.)

ACTION:	Recompile the current project with the Compiler’s Timing SNF Extractor command (Processing menu) turned on to create a timing SNF, then run the Timing Analyzer.

See also:

Creating a Timing Simulator Netlist File

MAX+PLUS II Messages

Message Format

Running a Timing Analysis


Timing Analyzer commands
Commands

For Help, choose a command name or dialog box name from the following list. Menu names are not included on the list.

About MAX+PLUS II	Move

Advanced Options	Name

AHDL	New Features in This Release

Archive	New Window

Arrange Icons	New

Authorization Code	Next

Auto Device Selection	Open

Auto-Recalculate	Pin/Location/Chip

Back-Annotate Project	Preferences

Basic Tools	Primitives

Cascade	Print Setup

Cell Width	Print

Classic & MAX Global Project Device Options	Probe

Classic & MAX Individual Device Options	Procedures

Clear Project Assignments	Programmer

Clique	Project 1, 2, 3, 4...

Close ( [image] and [image] menus)	Project Archive

Color Palette	Project Name

Commands	Project Save & Check

Compiler	Project Save & Compile

Connected Pins	Project Save & Simulate

Convert Obsolete Assignment Format	Project Save, Compile & Simulate

Cut Off Clear & Preset Paths	Project Set Project to Current File

Cut Off I/O Pin Feedback	READ.ME

Define Synthesis Style	Registered Performance

Delay Matrix	Rename Chip

Delete File	Restore

Device	Save & Check

Devices & Adapters	Save & Compile

ES Site License Authorization Request	Save & Simulate

Exit MAX+PLUS II	Save Analysis As

Find Next	Save Style As

Find Previous	Save, Compile & Simulate

Find Text	Search for Help on

FLEX 10K Global Project Device Options	Search Node Database

FLEX 10K Individual Device Options	Set Project to Current File

FLEX 8000 Global Project Device Options	Setup/Hold Matrix

FLEX 8000 Individual Device Options	Shortcuts

Floorplan Editor	Show Status Bar

Global Project Device Options	Show Toolbar

Global Project Logic Synthesis 	Simulator

Global Project Timing Requirements	Size

Glossary	Switch To

Golden Rules	Symbol Editor

Graphic Editor	Table of Contents

Hierarchy Display	Text Editor

Hierarchy Project Top	Tile Horizontally

How to Use Help	Tile Vertically

How to Use MAX+PLUS II Help	Time Restrictions

Ignore Project Assignments	Timing Analysis Cutoff

Individual Logic Options	Timing Analysis Destination

Introduction	Timing Analysis Source

List Only Longest Path	Timing Analyzer Help Basic Tools

Logic Options	Timing Analyzer Help Commands

Macrofunctions	Timing Analyzer Help Golden Rules

MAX 7000S Global Project Device Options	Timing Analyzer Help Introduction

MAX 7000S Individual Device Options	Timing Analyzer Help Procedures

MAX+PLUS II Registration	Timing Analyzer Help Shortcuts

MAX+PLUS II Table of Contents	Timing Analyzer Help Table of Contents

Maximize	Timing Analyzer

Message Processor	Timing Requirements

Messages	User Libraries

Minimize	VHDL

More Windows	Waveform Editor


Save Analysis As Command (Timing Analyzer)
Save Analysis As Command (File Menu)

Shortcut

Saves the current Timing Analyzer results to a Timing Analyzer Output File.

Save Analysis As saves the information in the current timing analysis display--specified with the Delay Matrix, Setup/Hold Matrix, or Registered Performance command (Analysis menu)--to an ASCII text file with the default extension .tao.

Click Button 1 on any item in this dialog box for information on that item:

See also:

Saving a Timing Analysis to a File


Save Analysis As dialog box

Click Button 1 on any item in this dialog box for information on that item:


Print Command (Timing Analyzer)
Print Command (File Menu)

Shortcut

Prints all or part of the current timing analysis displayed in the Timing Analyzer window.

Print converts the current Timing Analyzer display--specified with the Delay Matrix, Setup/Hold Matrix, or Registered Performance command (Analysis menu)--into a format that can be printed on any printer with a graphics mode. The output printed is in the same format as the Timing Analyzer Output File.

Click Button 1 on any item in this dialog box for information on that item:

MAX+PLUS II prints the file according to the settings for the current printer, which are specified with Print Setup (File menu).

See also:

Printing the Timing Analysis


Print dialog box

Click Button 1 on any item in this dialog box for information on that item:


Pages

Fit Into

% of One Page	Scales the analysis display to fit into a percentage (up to 100%) of a single page.

Page(s)	Specifies the number of pages (1, 4, or 9) on which to print the analysis.


Timing Analysis Source Command (Timing Analyzer)
Timing Analysis Source Command (Node Menu)

Shortcut

Specifies source node(s) for timing analysis and cancels all default timing tagging for source nodes performed by the Timing Analyzer.

Source nodes are used together with destination nodes to perform timing analysis. Timing Analysis Source is available only if the project has been compiled with the Timing SNF Extractor command (Processing menu) turned on to create a timing SNF. You can also use Timing Analysis Source with a linked SNF if it contains timing information only.

Nodes that are tagged as sources or destinations are displayed in the Delay Matrix or Setup/Hold Matrix display. Nodes that are tagged by default appear in the display only after you run the Timing Analyzer.

Click Button 1 on any item in this dialog box for information on that item:

Timing tagging entered with Timing Analysis Source is unrelated to timing requirements entered with the Timing Requirements command (Assign menu). The Timing Analyzer’s Timing Analysis Source command controls post-compilation timing analysis, while the Timing Requirements command helps guide compilation.

See also:

Clearing Timing Analysis Tags

Creating a Timing Simulator Netlist File

Running a Timing Analysis

Tagging Timing Analysis Cutoff Nodes

Tagging Timing Analysis Source & Destination Nodes


Timing Analysis Source dialog box

Click Button 1 on any item in this dialog box for information on that item:


Node Name

Specifies a text string containing wildcard characters or a node name.


List

Lists the nodes that match the text string in the Node Name box and the selected Type options in the Available Nodes list box.

If Show All Node Name Synonyms is turned on, the Available Nodes box also lists all possible hierarchical node names for each node that matches the text string in the Node Name box. Synonyms are preceded by -> in the list.


Available Nodes

Displays the nodes in the current SNF that match the text string in the Node Name box and selected Type options that can be used as source nodes in a timing analysis.

You must choose List to display the node names. You can choose => to move selected node names to the Selected Nodes box.

If Show All Node Name Synonyms is turned on, the Available Nodes box also lists all possible hierarchical node names for each node that matches the text string in the Node Name box. Synonyms are preceded by -> in the list.


Selected Nodes

Shows all nodes that have been selected (tagged) as source nodes for timing analysis.

You can choose => and <= to move selected node names between the Available Nodes box and Selected Nodes box.

Source nodes can also be selected with Timing Analysis Source (Node menu) in the Graphic, Text, or Waveform Editor.


=>

Moves selected nodes from the Available Nodes box to the Selected Nodes box, i.e., tags them as timing sources.


<=

Moves selected nodes from the Selected Nodes box to the Available Nodes box.


Type

Determines which types of nodes are displayed in the Available Nodes list box. When you choose the List button, all nodes matching the selected types are displayed. You can select one or more options or select all types to be listed.

Inputs	Lists all input nodes in the Available Nodes box.

Outputs	Lists all output nodes in the Available Nodes box.

Registered	Lists all buried registered nodes in the Available Nodes box.

Combinatorial	Lists all buried combinatorial nodes in the Available Nodes box.

All	Turns on all type options, i.e., lists all types of nodes in the Available Nodes box. Turning this option off deselects all other Type options.


Show All Node Name Synonyms

Shows all possible hierarchical node names for each node in the Available Nodes box that match the text string in the Node Name box. Synonyms are preceded by -> in the list.


Clear

Moves all nodes out of the Selected Nodes box and into the Available Nodes box, i.e., clears all timing analysis tags. You can also clear all timing source, destination, and cutoff tags with Clear All Timing Analysis Tags (Utilities menu) in the Graphic, Text, or Waveform Editor.


Timing Analysis Destination Command (Timing Analyzer)
Timing Analysis Destination Command (Node Menu)

Shortcut

Specifies destination node(s) for timing analysis and cancels all default timing tagging for destination nodes performed by the Timing Analyzer.

Destination nodes are used together with source nodes to perform timing analysis. Timing Analysis Destination is only available if the project has been compiled with the Timing SNF Extractor command (Processing menu) turned on to create a timing SNF. You can also use Timing Analysis Destination with a linked SNF if it contains timing information only.

When a node is tagged as a source or destination, it is displayed in the Delay Matrix or Setup/Hold Matrix display. Nodes that are tagged by default appear in the display only after you run the Timing Analyzer.

Click Button 1 on any item in this dialog box for information on that item:

Timing tagging entered with Timing Analysis Destination is unrelated to timing requirements entered with the Timing Requirements command (Assign menu). The Timing Analyzer’s Timing Analysis Destination command controls post-compilation timing analysis, while the Timing Requirements command helps guide compilation.

See also:

Clearing Timing Analysis Tags

Creating a Timing Simulator Netlist File

Running a Timing Analysis

Tagging Timing Analysis Cutoff Nodes

Tagging Timing Analysis Source & Destination Nodes


Timing Analysis Destination dialog box

Click Button 1 on any item in this dialog box for information on that item:


Available Nodes

Displays the nodes in the current SNF that match the text string in the Node Name box and selected Type options that can be used as destination nodes in a timing analysis.

You must choose List to display the node names. You can choose => to move selected node names to the Selected Nodes box.

If Show All Node Name Synonyms is turned on, the Available Nodes box also lists all possible hierarchical node names for each node that matches the text string in the Node Name box. Synonyms are preceded by -> in the list.


Selected Nodes

Shows all nodes that have been selected (tagged) as destination nodes for timing analysis.

You can choose => and <= to move selected node names between the Available Nodes box and Selected Nodes box.

Destination nodes can also be selected with Timing Analysis Destination (Node menu) in the Graphic, Text, or Waveform Editor.


=>

Moves selected nodes from the Available Nodes box to the Selected Nodes box, i.e., tags them as Timing Analysis Destinations.


Timing Analysis Cutoff Command (Timing Analyzer)
Timing Analysis Cutoff Command (Node Menu)

Shortcut

Specifies one or more nodes as cutoff points, so that the signal paths that extend beyond the specified nodes are not included when a timing analysis is performed.

Timing Analysis Cutoff nodes reduce the number of signal paths analyzed in a timing analysis. Timing Analysis Cutoff is only available if the project has been compiled with the Timing SNF Extractor command (Processing menu) turned on to create a timing SNF. You can also use Timing Analysis Cutoff with a linked SNF if it contains timing information only.

Nodes that are specified as a source or destination are shown in the Delay Matrix or Setup/Hold Matrix display.

Click Button 1 on any item in this dialog box for information on that item:

See also:

Clearing Timing Analysis Tags

Creating a Timing Simulator Netlist File

Running a Timing Analysis

Tagging Timing Analysis Cutoff Nodes

Tagging Timing Analysis Source & Destination Nodes


Timing Analysis Cutoff dialog box

Click Button 1 on any item in this dialog box for information on that item:


Available Nodes

Displays the nodes in the current SNF that match the text string in the Node Name box and selected Type options that can be used as cutoff nodes in a timing analysis.

You must choose List to display the node names. You can choose => to move selected node names to the Selected Nodes box.

If Show All Node Name Synonyms is turned on, the Available Nodes box also lists all possible hierarchical node names for each node that matches the text string in the Node Name box. Synonyms are preceded by -> in the list.


Selected Nodes

Shows all nodes that have been selected (tagged) as cutoff nodes for timing analysis.

You can choose => and <= to move selected node names between the Available Nodes box and Selected Nodes box.

Cutoff nodes can also be selected with Timing Analysis Cutoff in the Graphic, Text, or Waveform Editor.


=>

Moves selected nodes from the Available Nodes box to the Selected Nodes box, i.e., tags them as timing analysis cutoffs.


Delay Matrix Command (Timing Analyzer)
Delay Matrix Command (Analysis Menu)

Shortcut

Turns on the Delay Matrix timing analysis mode. Show me

Delay Matrix creates a matrix for displaying propagation delays between source nodes and destination nodes in the current project. If you are using default timing tagging, the Delay Matrix display is blank before you run the Timing Analyzer. Otherwise, the display shows all nodes that have been selected with Timing Analysis Source and Timing Analysis Destination (Node menu).

When you choose Start to run the Timing Analyzer, the minimum and maximum propagation delays between the source and destination nodes are calculated and displayed in each matrix cell. If Auto-Recalculate (Options menu) is also turned on, the Timing Analyzer automatically recalculates all delays when the Compiler generates a new timing SNF or linked SNF that contains timing information only. You can use Time Restrictions (Options menu) to exclude the minimum or the maximum delays from the display, and to restrict the lengths of the delay paths used for the analysis. You can also exclude nodes from the analysis with Timing Analysis Cutoff (Node menu).

After the propagation delays have been calculated and appear in the delay matrix, you can select a cell in the matrix, and choose List Paths to open a Message Processor window that lists all propagation delays calculated between the two nodes. The Message Processor lists all paths, including paths not shown in the cell. You can use the Message Processor’s Locate button to locate and display each signal path between the two nodes in the appropriate design file(s).

You can also run a Delay Matrix timing analysis with Analyze Timing (Utilities menu) in the Graphic, Text, Floorplan,or Waveform Editor, provided that Delay Matrix is the current analysis mode in the Timing Analyzer window.

See also:

Choosing an Analysis Mode

Listing & Locating Signal Paths

Specifying Time Restrictions

Tagging Timing Analysis Cutoff Nodes

Tagging Timing Analysis Source & Destination Nodes


Delay Matrix Mode
Delay Matrix Display


Setup/Hold Matrix Command (Timing Analyzer)
Setup/Hold Matrix Command (Analysis Menu)

Shortcut

Turns on the Setup/Hold Matrix time analysis mode. Show me

Setup/Hold Matrix creates a matrix for displaying setup and hold time requirements between source nodes and destination nodes in the current project. If you are using default timing tagging, the Setup/Hold Matrix display is blank before you run the Timing Analyzer. Otherwise, the display shows all nodes that have been selected with Timing Analysis Source and Timing Analysis Destination (Node menu).

When you choose Start to run the Timing Analyzer, the setup times and hold times required between the source and destination nodes are calculated and displayed in each matrix cell. If Auto-Recalculate (Options menu) is also turned on, the Timing Analyzer automatically recalculates all setup and hold times in the matrix when the Compiler generates a new timing SNF or linked SNF that contains timing information only. You can use Time Restrictions (Options menu) to exclude the minimum or the maximum delays from the display, and to restrict the lengths of the delay paths used for the analysis. You can also exclude nodes from the analysis with Timing Analysis Cutoff (Node menu).

After the setup and hold times have been calculated and appear in the matrix, you can select a cell in the matrix, and choose List Paths to open a Message Processor window that lists all signal paths calculated between the two nodes. The Message Processor lists all paths, including paths not shown in the cell. You can use the Message Processor’s Locate button to locate and display each signal path between the two nodes in the appropriate design file(s).

You can also run a Setup/Hold Matrix timing analysis with Analyze Timing (Utilities menu) in the Graphic, Text, Floorplan, or Waveform Editor, provided that Setup/Hold Matrix is the current analysis mode in the Timing Analyzer window.

See also:

Choosing an Analysis Mode

Listing & Locating Signal Paths

Specifying Time Restrictions

Tagging Timing Analysis Cutoff Nodes

Tagging Timing Analysis Source & Destination Nodes


Setup/Hold Matrix Mode
Setup/Hold Matrix Display


Registered Performance Command (Timing Analyzer)
Registered Performance Command (Analysis Menu)

Shortcut

Turns on the Registered Performance timing analysis mode. Show me

Registered Performance creates a Registered Performance display for showing the worst-case registered performance for each Clock signal in the current project. The display is blank until you run the Timing Analyzer.

The Timing Analyzer calculates registered performance when you choose Start. Performance is calculated on the basis of all source nodes, destination nodes, and cutoff nodes selected with Timing Analysis Source, Timing Analysis Destination, and Timing Analysis Cutoff (Node menu), or on the basis of the default timing tagging provided by the Timing Analyzer. You can restrict the lengths of the delay paths used for the analysis with Time Restrictions (Options menu), and exclude nodes from the analysis with Timing Analysis Cutoff. With Time Restrictions (Options menu), you can also specify the number of paths per Clock to list, or choose to list all paths that have registered performance worse than a specified frequency.

If Auto-Recalculate  (Options menu) is also turned on, the Timing Analyzer automatically recalculates the registered performance when the Compiler generates a new timing SNF or linked SNF that contains timing information only. The display shows the minimum Clock period, which equals the maximum delay from the Q output of a flipflop to the data input of a flipflop, plus the internal setup time and propagation delay through the flipflop. The maximum Clock frequency equals 1/(Clock period).

After the calculated registered performance appears in the display, you can choose the List Paths button to open a Message Processor window that lists the signal paths calculated between performance-limiting nodes. You can choose the Message Processor’s Locate button to locate and display the signal path between the two nodes in the appropriate design file(s).

You can also run a registered performance timing analysis with Analyze Timing (Utilities menu) in the Graphic, Text, Waveform, or Floorplan Editor, provided that Registered Performance is the current analysis mode in the Timing Analyzer window.

See also:

Choosing an Analysis Mode

Listing & Locating Signal Paths

Specifying Time Restrictions

Tagging Timing Analysis Cutoff Nodes

Tagging Timing Analysis Source or Destination Nodes


Registered Performance Mode
Registered Performance Display


Find Text Command (Timing Analyzer)
Find Text Command (Utilities Menu)

Shortcut

Searches the current matrix for the first occurrence of the specified text.

This command allows you to find a node listed in the current Delay Matrix or Setup/Hold Matrix display.

Click Button 1 on any item in this dialog box for information on that item:

After the first occurrence of the search text is found, you can choose Find Next or Find Previous (Utilities menu) to continue the search.

See also:

Finding Text


Find Text dialog box

Click Button 1 on any item in this dialog box for information on that item:


Direction

Down	Searches from the currently selected cell to the end of the display, jumps to the beginning, and searches down to the selected cell.

Up	Searches from the currently selected cell to the beginning of the display, jumps to the end, and searches up to the selected cell.


Find Next Command (Timing Analyzer)
Find Next Command (Utilities Menu)

Shortcut

Finds the next occurrence of the text string specified with Find Text (Utilities menu).

Find Next searches in the direction specified in Find Text. If you specified Down, it searches down the file; if you specified Up, it searches up.

See also:

Finding Text


Find Previous Command (Timing Analyzer)
Find Previous Command (Utilities Menu)

Shortcut

Finds the previous occurrence of the text string specified with Find Text (Utilities menu).

Find Previous searches opposite to the direction specified in Find Text. If you specified Down, it searches down the file; if you specified Up, it searches up.

See also:

Finding Text


Time Restrictions Command (Timing Analyzer)
Time Restrictions Command (Options Menu)

Defines restrictions on the delay paths to be included and displayed in the next Delay Matrix or Registered Performance timing analysis.

For a Delay Matrix timing analysis, Time Restrictions specifies the lengths of delay paths (signal travel times) that can be excluded from analysis. You can also exclude the longest or shortest paths from the timing analysis results shown in the Delay Matrix display. For a Registered Performance timing analysis, Time Restrictions specifies the maximum register-to-register frequency to include in the analysis, or the number of worst-case performance paths to display per Clock signal.

Click Button 1 on any item in this dialog box for information on that item:

Specifications entered in Time Restrictions are unrelated to those entered using the Timing Requirements command (Options menu). The Timing Analyzer’s Time Restrictions command controls post-compilation timing analysis, while the Timing Requirements command helps guide compilation.

See also:

Specifying Time Restrictions


Time Restrictions dialog box

Click Button 1 on any item in this dialog box for information on that item:


Include Paths

Greater Than	Specifies the minimum signal travel time to include in the timing analysis.

Less Than	Specifies the maximum signal travel time to include in the timing analysis.

For each option, type a time followed immediately (i.e., with no space in between) by a time unit. The default is ns.


Delay Matrix Options

Show All Paths	Displays all delay paths between nodes in the Delay Matrix display.

Show Only Longest Paths	Displays only the longest delay paths between nodes in the Delay Matrix display.

Show Only Shortest Paths	Displays only the shortest delay paths between nodes in the Delay Matrix display.


Registered Performance Options

Number of Paths per Clock to List	Specifies the number of worst-performance paths to list per Clock signal.

List Paths with Frequency Less Than	Specifies the maximum frequency of the paths to be listed by the timing analysis. Type a frequency followed immediately (i.e., with no space in between) by a time unit. The default is MHz.


Auto-Recalculate Command (Timing Analyzer)
Auto-Recalculate Command (Options Menu)

Turns automatic timing analysis recalculation on and off.

When Auto-Recalculate is turned on, the Timing Analyzer automatically updates the current timing analysis when the Compiler creates a new timing SNF or linked SNF that contains timing information only. The current Timing Analyzer display--Delay Matrix, Setup/Hold Matrix, or Registered Performance--automatically reflects the new timing characteristics of the project when the Compiler’s Timing SNF Extractor module generates a new timing SNF or the Linked SNF Extractor creates a linked SNF with timing information only.

See also:

Creating a Timing Simulator Netlist File

Recalculating the Analysis Automatically


Cell Width Command (Timing Analyzer)
Cell Width Command (Options Menu)

Specifies the width of each cell in the current timing analysis matrix.

Click Button 1 on any item in this dialog box for information on that item:

Cell Width is available only when the Delay Matrix or Setup/Hold Matrix command (Analysis menu) is turned on.

See also:

Changing the Matrix Cell Width


Cell Width dialog box

Click Button 1 on any item in this dialog box for information on that item:


Width

Specifies the number of "average width" (i.e., wider than an "i" but narrower than a "w") characters to display in each cell of the Delay Matrix or Setup/Hold Matrix display.

You can type an integer between 4 and 128. The default width is 18.


Cut Off I/O Pin Feedback Command (Timing Analyzer)
Cut Off I/O Pin Feedback Command (Options Menu)

Cuts off the delay that is fed back from a bidirectional (BIDIR or BIDIRC) pin during timing analysis.

A bidirectional pin can be used as both a source and destination node. When Cut Off I/O Pin Feedback is turned on, signal feedback from within the device is not included in the timing analysis, thus eliminating invalid paths. Example

Cut Off I/O Pin Feedback is especially useful when a bidirectional pin is connected directly or indirectly to both the input and the output of a latch. This type of feedback path is continuous because it is not interrupted by any clocked logic primitives. As additional, interconnected latch-to-pin loops are added, the number of hidden paths grows exponentially, e.g., when latches are used with bidirectional buses. Cut Off I/O Pin Feedback allows you to easily eliminate the false paths caused by latch-to-pin loops. Example

When a bidirectional pin is tagged as a cutoff node with Timing Analysis Cutoff (Node menu), it is completely excluded from timing analysis, and thus cannot act as a source or destination. In contrast, Cut Off I/O Pin Feedback allows you to retain the I/O pin as a source and/or destination node while eliminating invalid paths from the timing analysis.

Cut Off I/O Pin Feedback is unrelated to the Cut Bidirectional Feedback Timing Paths option in the Global Project Timing Requirements dialog box (Assign menu). The Timing Analyzer’s Cut Off I/O Pin Feedback command controls post-compilation timing analysis, while the Cut Bidirectional Feedback Timing Paths option helps guide compilation.

See also:

Cutting Off Clear & Preset Timing Paths

Cutting Off I/O Pin Feedback

Running a Timing Analysis

Tagging Timing Analysis Cutoff Nodes


Examples of I/O pin feedback

The following examples show signal paths that are included and excluded during timing analysis when Cut Off I/O Pin Feedback is turned on:


Examples of latch-to-pin loops
Example of latch-to-pin loops


Cut Off Clear & Preset Paths Command (Timing Analyzer)
Cut Off Clear & Preset Paths Command (Options Menu)

Cuts off the timing paths for all Clear and Preset signals in the project. When this command is turned on, the Timing Analyzer does not consider the delay along these paths during timing analysis.

When Cut Off Clear & Preset Paths is turned on, the Clear and Preset signals to a D flipflop are not included in the timing analysis, thus eliminating invalid paths.

Cut Off Clear & Preset Paths is unrelated to the Cut All Clear & Preset Timing Paths option in the Compiler’s Global Project Timing Requirements dialog box (Assign menu). The Timing Analyzer’s Cut Off Clear & Preset Paths command controls post-compilation timing analysis, while the Global Project Timing Requirements command option helps guide compilation.

See also:

Cutting Off Clear & Preset Timing Paths

Cutting Off I/O Pin Feedback

Running a Timing Analysis

Tagging Timing Analysis Cutoff Nodes


List Only Longest Path Command (Timing Analyzer)
List Only Longest Path Command (Options Menu)

Directs the Timing Analyzer to calculate only the longest delay path between a pair of nodes when you choose the List Paths button.

When List Only Longest Path is turned on, the Message Processor displays only one path. Therefore, this command shortens the time required to list paths and eliminates extraneous information.

List Only Longest Path is not available in a Delay Matrix timing analysis if you specify restrictions with Time Restrictions (Options menu) before running the timing analysis, and is never available for Registered Performance timing analysis.

See also:

Listing & Locating Signal Paths

Specifying Time Restrictions


"Show me" windows used in TAN Intro and TAN Basic Tools


Timing Analyzer Window


Timing Analyzer Window


The following SN_MSGS.MSG, fsnmsgs.msg, and lnkmsgs.msg messages are not documented in this file:

FSN_SNF_IS_IN_USE	simess

flnk_cant_conk_snf	simess

FFSN_SNF_IS_IN_USE	simess

mfsn_reset_required	comess

wlnk_port_not_in_snf	ntinmess

flnk_too_many_names	comess


Can’t add <text> information to SNF -- out of space for symbols

CAUSE:	The project you are trying to compile exceeds the limit of 60 Kbytes of symbolic group and state, pin, or logic cell information.

ACTION:	Create the groups manually in an SCF or Vector File or reduce the number of groups and/or states in the project.

See also:

Creating a Group (Waveform Editor)

MAX+PLUS II Messages

Message Format

Vector File Format


I suspect that the following message could be reworded and added to the last message--check with Brent after the 3.2 release:


 Can’t add group and state information for <filename>

CAUSE:	You compiled a super-project with the Linked SNF Extractor turned on. The Linked SNF Extractor added the specified SNF to the linked SNF, but did not add the group and/or state information because of lack of space.

ACTION:	Shorten hierarchical node, group, and state names in the design files of all of the sub-projects, which will require less space in the linked SNF. Recompile the sub-project, and then recompile the super-project.

See also:

MAX+PLUS II Messages

Message Format

Updating the Hierarchy


Can’t add group or state name <name> to the linked SNF

CAUSE:	You compiled a super-project with the Linked SNF Extractor turned on, but the Linked SNF Extractor could not add the specified group or state name to the linked SNF because the new hierarchical name of the group or state would be too long.

ACTION:	Shorten the specified group or state name in the design files of the appropriate sub-project, recompile the sub-project, then recompile the super-project.

See also:

Buses (Graphic & Symbol Editors)

Groups (AHDL)

Groups (Waveform Editor)

MAX+PLUS II Messages

Message Format

Updating the Hierarchy


Can’t add group/state machine <name> to SNF -- too many <text>

CAUSE:	The <text> of this message indicates that the project you are compiling contains more than the maximum number of groups or buses, a group with too many members, or a state machine group with too many state bits. The Compiler will generate the SNF with only this specified maximum number of groups that contain the specified maximum number of members.

ACTION:	Use less than the specified maximum number of groups, buses, or state machine groups, or change the groups in the project to contain less than the maximum number of members.

See also:

Buses (Graphic & Symbol Editors)

Groups (AHDL)

Groups (Waveform Editor)

MAX+PLUS II Messages

Message Format


Can’t add state <name> to SNF -- too many states or don’t care state bits

CAUSE:	The Compiler cannot add the specified state to the SNF because the SNF already contains the 1,024 states or state bits defined as don’t care.

ACTION:	Use less than 1,024 states in the project. If state bits are the problem, you must ensure that the number of don’t care state bits created by the Functional Simulator Netlist Extractor or Timing Simulator Netlist Extractor when the project is compiled is less than 1,024. This number is equivalent to 2^n, where n = the number of state bits you have defined.

See also:

Assigning State Machine Bits & Values (AHDL)

Creating a Waveform Design File

MAX+PLUS II Messages

Message Format

State Machine Declaration


 Can’t create linked SNF -- no macrofunctions in project represent SNFs

CAUSE:	You compiled a super-project with the Compiler’s Linked SNF Extractor command turned on, but none of the sub-project macrofunction used in the super-project represent the SNFs of other previously compiled projects. The Linked SNF Extractor can only create a linked SNF if the macrofunctions used in a super-project have already been compiled separately to generate SNFs.

ACTION:	Turn Linked SNF Extractor off, change the super-project to include only those sub-project macrofunctions for which an SNF already exists, or compile each sub-project to create an SNF.

See also:

Combining Multiple Projects for Simulation

MAX+PLUS II Messages

Message Format


 Can’t create linked SNF -- top-level design file contains state machine logic (net ID <net ID number>)

CAUSE:	You compiled a super-project with the Compiler’s Linked SNF Extractor command turned on, but the top-level design file contains the specified state machine. The top-level design file in a super-project that is compiled to create a linked SNF can contain only macrofunctions that represent the SNFs of previously compiled projects and logic primitives.

ACTION:	Turn Linked SNF Extractor off, or remove the state machine from the top-level design file.

See also:

Combining Multiple Projects for Simulation

MAX+PLUS II Messages

Message Format


 Can’t include macrofunction <name> in linked SNF -- it has no inputs

CAUSE:	You compiled a super-project with the Compiler’s Linked SNF Extractor command turned on. The symbol or Function Prototype that represents the specified macrofunction has no input pinstubs or ports.This message usually occurs if you have changed the lower-level design file but have not updated the symbol or Function Prototype to reflect the changes.

ACTION:	If the error occurs for a symbol in a Graphic Editor file, open the lower-level file and use Edit Symbol to manually update the symbol that represents the file, or use Create Default Symbol to automatically generate a new symbol. Then use Update Symbol to update the higher-level file.

If the error occurs in a TDF, correct the Function Prototype for the lower-level design file. If you use an Include File to call the Function Prototype, you can open the lower-level file and use Create Default Include File to automatically generate a new Function Prototype.

Since the symbol or Function Prototype represents an SNF and not a design file, creating a new symbol or Function Prototype will only correct the error if the logic in the SNF is up-to-date. Therefore, you may also wish to recompile the project that the symbol or Function Prototype represents.

See also:

Combining Multiple Projects for Simulation

Creating a Default Include File

Creating the Default Symbol for a File

Editing the Symbol for a File

MAX+PLUS II Messages

Message Format

Updating a Symbol in a Graphic Editor File


Can't override existing external pin connections -- macrofunction <name> contains etc.
Can’t override existing external pin connections -- macrofunction <name> contains input pin <name> that is already externally connected to pin <name>

CAUSE:	You compiled a super-project with the Compiler’s Linked SNF Extractor command turned on. The specified macrofunction has an external pin connection between the specified pins. However, a higher-level design file that contains an instance of this macrofunction illegally uses a different connection for the specified input pin. The external pin connections used at a higher level of hierarchy must be the same as in the macrofunction. This message can also occur if you have changed the lower-level design file but have not updated the symbol or AHDL Function Prototype to reflect the changes.

ACTION:	It is not necessary to reconnect externally connected pins at a higher level of hierarchy. Therefore, you should edit the higher-level design file to remove the illegal connection or make the connections identical to those in the lower-level macrofunction.

If the error occurs because the macrofunction symbol or Function Prototype is out of date, you must update it. You can automatically generate a new symbol or an Include File that call the Function Prototype with Create Default Symbol or Create Default Include File, respectively. If the error occurs for a symbol in a Graphic Editor file, you must then use Update Symbol to update the symbol in the file. In addition, since the symbol or Function Prototype represents an SNF and not a design file, creating a new symbol or Function Prototype will only correct the error if the logic in the SNF is up-to-date. Therefore, you may also wish to recompile the project that the symbol or Function Prototype represents.

See also:

Combining Multiple Projects for Simulation

Creating a Default Include File

Creating the Default Symbol for a File

Editing the Symbol for a File

MAX+PLUS II Messages

Message Format

Updating a Symbol in a Graphic Editor File


External pin connections ignored for <project name>

CAUSE:	You are generating an EDIF Output File for the current project. Since the chip name is the same as the project name, the Compiler is forced to exclude information on all externally connected input pins in the timing SNF that it generates for the project.

ACTION:	If you plan only to simulate with the EDIF Output File and not with the SNF, no action is required. Otherwise, you must either change the chip name for the project or recompile the project with EDIF Netlist Writer turned off to generate an SNF that includes all external pin connections.

See also:

Assigning a Pin, Logic Cell, or Chip

MAX+PLUS II Messages

Message Format


Pinstub/port name <name> is missing from symbol or Function Prototype that represents <filename>.snf

CAUSE:	You compiled a super-project with the Compiler’s Linked SNF Extractor command turned on. The symbol or Function Prototype that represents the specified SNF does not have a pinstub or port for the specified pin that exists in the SNF. This message usually occurs if you have changed the lower-level design file and recompiled the project but have not updated the symbol or Function Prototype to reflect the changes.

ACTION:	If the error occurs for a symbol in a Graphic Editor file, open the lower-level file and use Edit Symbol to manually update the symbol that represents the file, or use Create Default Symbol to automatically generate a new symbol. Then use Update Symbol to update the higher-level file.

If the error occurs in a TDF, correct the Function Prototype for the lower-level design file. If you use an Include File to call the Function Prototype, you can open the lower-level file and use Create Default Include File to automatically generate a new Function Prototype.

Since the symbol or Function Prototype represents an SNF and not a design file, creating a new symbol or Function Prototype will only correct the error if the logic in the SNF is up-to-date. Therefore, you may also wish to recompile the project that the symbol or Function Prototype represents.

See also:

Combining Multiple Projects for Simulation

Creating a Default Include File

Creating the Default Symbol for a File

Editing the Symbol for a File

Entering & Naming a Pinstub

MAX+PLUS II Messages

Message Format

Updating a Symbol in a Graphic Editor File


Port <name> is tied to <default value>

CAUSE:	The Functional SNF Extractor detected that a Clock signal for the memory block is tied to VCC or GND. Since the Clock is constant, the RAM memory block cannot function correctly.

ACTION:	Change the Clock signal so that it is not tied to VCC or GND.

See also:

MAX+PLUS II Messages

Message Format


Project cannot be simulated -- <filename> contains the network of only one of the project devices

CAUSE:	You did not specify any chip names for a project partitioned among multiple devices and you turned on the EDIF Netlist Writers command. Therefore, the Compiler couldn’t generate a multi-chip SNF that represents the entire project because it would overwrite one of the single-chip SNFs that are created as part of the process that generates EDIF Output Files.

ACTION:	If you do not wish to simulate with MAX+PLUS II, no action is required. Otherwise, you must either make chip assignments in the project’s design files and assign chip names that are different from the project name, or turn off the EDIF Netlist Writer command and recompile to generate a multi-chip SNF.

See also:

Assigning a Pin, Logic Cell, or Chip

MAX+PLUS II Messages

Message Format


Symbol or Function Prototype for macrofunction <name> contains pinstub/port <name> with I/O type <text>, but...
Symbol or Function Prototype for macrofunction <name> contains pinstub/port <name> with I/O type <text>, but its I/O type is different in <filename>.snf

CAUSE:	You compiled a super-project with the Compiler’s Linked SNF Extractor command turned on. Although the specified pinstub or port name exists in the SNF for the macrofunction, it either has the wrong I/O type in the symbol or Function Prototype that represents it or is a buried node. This message usually occurs if you have changed the lower-level design file but have not updated the symbol or Function Prototype to reflect the changes.

ACTION:	If the error occurs for a symbol in a Graphic Editor file, open the lower-level file and use Edit Symbol to manually update the symbol that represents the file, or use Create Default Symbol to automatically generate a new symbol. Then use Update Symbol to update the higher-level file.

If the error occurs in a TDF, correct the Function Prototype for the lower-level design file. If you use an Include File to call the Function Prototype, you can open the lower-level file and use Create Default Include File to automatically generate a new Function Prototype.

Since the symbol or Function Prototype represents an SNF and not a design file, creating a new symbol or Function Prototype will only correct the error if the logic in the SNF is up-to-date. Therefore, you may also wish to recompile the project that the symbol or Function Prototype represents.

See also:

Combining Multiple Projects for Simulation

Creating a Default Include File

Creating the Default Symbol for a File

Changing the Pinstub Name & I/O Type

Editing the Symbol for a File

MAX+PLUS II Messages

Message Format

Updating a Symbol in a Graphic Editor File


-----BEGINNING OF NON-TRANSLATED TEXT-----

The following messages in the smvmsgs.msg file are documented elsewhere:

tsmv_duplicate_state_name	comess

tsmv_temp_file_error	glmess

tsmv_msyntax	comess

tsmv_io_error	glmess

-----END OF NON-TRANSLATED TEXT-----


Can’t use Case Statement in Outputs Subsection: <state machine name>

CAUSE:	You have used a Case Statement in the Outputs Subsection of the specified state machine design in an SMF.

ACTION:	Use only conditional (IF-THEN) and unconditional output statements in the Outputs Subsection (Case Statements may be used only in the Transitions Subsection).

See also:

MAX+PLUS II Messages

Message Format


Can’t use state name in expression: <state machine name>

CAUSE:	You have used a state name in an expression (i.e., the condition in a conditional or Case Statement transition) in the Transitions and/or Outputs Subsection of an SMF.

ACTION:	For each expression, use a Boolean expression consisting of input variables, intermediate variables, and/or names of states from other state machines on which the current transition depends.

See also:

MAX+PLUS II Messages

Message Format


Can’t use state output names in Inputs Section: <state machine name>

CAUSE:	You have used the name of a state output in the Inputs Section of an SMF.

ACTION:	Ensure that state outputs do not appear in the Inputs Section.

See also:

MAX+PLUS II Messages

Message Format


Can’t use state output names in Outputs Section: <state machine name>

CAUSE:	You have used the name of a state output in the Outputs Section of an SMF.

ACTION:	Ensure that state outputs do not appear in the Outputs Section.

See also:

MAX+PLUS II Messages

Message Format


Can’t use state variable names in Outputs Subsection: <state machine name>

CAUSE:	You have used a state variable name in the Outputs Subsection as well as in a state definition in the States Subsection of an SMF.

ACTION:	Ensure that state variables are unique within a single SMF. They may not appear in the design’s Outputs Subsection.

See also:

MAX+PLUS II Messages

Message Format


Duplicate state variable assignment: (<text>)

CAUSE:	More than one state in an SMF has the same state variable assignment within a single state machine.

ACTION:	Ensure that all state variable assignments are unique within a single state machine.

See also:

MAX+PLUS II Messages

Message Format


Duplicate state variable name: <name>

CAUSE:	You have used the same state variable name in two or more state machines in an SMF.

ACTION:	Ensure that all state variable names are unique within a single SMF.

See also:

MAX+PLUS II Messages

Message Format


Empty truth table: no statements

CAUSE:	The truth table of an SMF contains only one line (i.e., the T_TAB: keyword and input and output declarations are not followed by input and output arguments).

ACTION:	Enter the input and output arguments (statements) for the truth table or remove the line containing the T_TAB: keyword.

See also:

MAX+PLUS II Messages

Message Format


Equation too long

CAUSE:	An SMF contains an equation with more than 256 characters on a single line.

ACTION:	Split the equation into two lines.

See also:

MAX+PLUS II Messages

Message Format


Illegal character in <section name>

CAUSE:	An illegal or misplaced character was detected in the indicated section of an SMF.

ACTION:	Replace the character.

See also:

MAX+PLUS II Messages

Message Format


Illegal Outputs Subsection in <state machine name>

CAUSE:	The Outputs Subsection of an SMF contains an output statement whose syntax does not conform to either of the two permitted formats, or the output signal name is not a node name.

ACTION:	Ensure that output signal names are not state names or state variable names. Use conditional (IF-THEN) or unconditional output statement format in the Outputs Subsection (Case Statements are not allowed).

See also:

MAX+PLUS II Messages

Message Format


Illegal pin assignment: (<assignment>, <pin name>)

CAUSE:	The pin assignment for a pin name in an SMF contains an illegal character or an unexpected End-of-File (EOF).

ACTION:	Specify pin assignments by appending an at symbol (@) plus a one- or two-digit number to the signal name. (In the PGA-package devices, pin numbers are specified with an @ symbol plus one letter and a one- or two-digit number.)

See also:

MAX+PLUS II Messages

Message Format


Illegal state machine <text> name: (<code>, <node name>)

CAUSE:	The <node name> of an SMF state machine Clock or Clear signal is too long or contains an illegal character. (<code> is an internal diagnostic code.)

ACTION:	Ensure that all node names contain eight of the following characters A-Z, a-z, 0-9, and _ (underscore) All other characters are illegal.

See also:

MAX+PLUS II Messages

Message Format


Illegal state machine name

CAUSE:	The name of an SMF state machine contains over 32 characters or characters not permitted in state machine names.

ACTION:	Use a state machine name that contains 32 of the following characters A-Z, a-z, 0-9, and _ (underscore) All other characters are illegal.

See also:

MAX+PLUS II Messages

Message Format


Illegal Transition Statement in <state machine name>

CAUSE:	The Transitions Subsection of an SMF contains a transition statement whose syntax does not conform to any of the three permitted formats, or the destination of a transition is not a state or node name.

ACTION:	Ensure that the destinations of transitions are not state variable names. Use conditional (IF-THEN), unconditional, or Case Statement transitions in the correct format.

See also:

MAX+PLUS II Messages

Message Format


Mismatched parentheses in <state machine name>

CAUSE:	A left or right parenthesis is missing from an expression in the Transitions or Outputs Subsection of an SMF.

ACTION:	Ensure that an equal number of left and right parentheses are present in each expression.

See also:

MAX+PLUS II Messages

Message Format


Missing <section name>

CAUSE:	An End-of-File (EOF) was detected before the specified SMF or ADF section (i.e., Part, Inputs, Outputs, or Network) was found. The section may be present, but it is empty or not in the proper sequence. The Inputs, Outputs, and Part sections are required in both SMFs and ADFs; the Network Section is required only in the ADF.

ACTION:	Ensure that the file has the required sections in the order listed above. Remove blank spaces, tabs, and non-printing characters that appear before the PART:, INPUTS:, OUTPUTS:, and NETWORK: keywords. Be sure to specify a device in the Part Section.

See also:

MAX+PLUS II Messages

Message Format


Missing destination state in <state machine name>

CAUSE:	A transition in the Transitions or Outputs Subsection of an SMF does not have a destination state (i.e., there is nothing after the THEN in a conditional transition or after the colon (:) in a Case Statement or unconditional transition).

ACTION:	Add the name of a destination state to the transition statement.

See also:

MAX+PLUS II Messages

Message Format


Missing expression in <state machine name>

CAUSE:	A conditional (IF-THEN) or Case Statement transition in an SMF is missing an expression (i.e., a Boolean expression).

ACTION:	Ensure that conditional statements have the format IF <expression> THEN <name> and Case Statements have the format <expression> : <name>.

See also:

MAX+PLUS II Messages

Message Format


Missing node name in <state machine name>

CAUSE:	An expression in the Transitions and/or Outputs Subsection of an SMF is missing a node name.

ACTION:	Check the expressions for syntax errors. For example, you may have left a space between a node name and its complement, or typed two operators in succession.

See also:

MAX+PLUS II Messages

Message Format


Missing operator in <state machine name>

CAUSE:	An expression in the Machine Section of an SMF is missing a binary operator (i.e., + or &).

ACTION:	Insert one of the binary operators given above as appropriate.

:	The following NOT operators are permitted: ! and '.

See also:

MAX+PLUS II Messages

Message Format


Missing or illegal Clock Subsection: (<code>, <text>)

CAUSE:	The Compiler found <text> in an SMF instead of the required CLOCK: keyword on the first new line of text following the state machine name. (<code> is an internal diagnostic code.)

ACTION:	Insert the Clock Subsection as the first new line of text after the state machine name. Ensure that no characters other than spaces or tabs are before the CLOCK: keyword.

See also:

MAX+PLUS II Messages

Message Format


Missing or illegal States Subsection

CAUSE:	The Compiler did not find the required STATES: keyword on the first new line of text following the Clear (or if Clear is not used, Clock) Subsection of an SMF.

ACTION:	Insert the States Subsection. Ensure that there are no characters other than spaces or tabs before the STATES: keyword.

See also:

MAX+PLUS II Messages

Message Format


Missing state variable assignment

CAUSE:	You have not provided state variable values for one or more states in the States Subsection of an SMF.

ACTION:	Assign all state variable values in the States Subsection.

See also:

MAX+PLUS II Messages

Message Format


Missing state variable name

CAUSE:	You have not provided the name of one or more state variables in the States Subsection of an SMF.

ACTION:	Declare all state variable names.

See also:

MAX+PLUS II Messages

Message Format


Network Section line too long

CAUSE:	A line in an SMF Network Section contains more than 256 characters, which is the maximum permitted on a single line.

ACTION:	Split the line into two or more lines.

See also:

MAX+PLUS II Messages

Message Format


No exit from state: (<state name>) in <state machine name>

CAUSE:	The <state name> in an SMF has no transitions leading to other states (i.e., there is no way to leave the state). You may have misspelled a state name.

ACTION:	Check the current entries for destination states in the Transitions Subsection. Ensure that all transitions can lead to another state.

See also:

MAX+PLUS II Messages

Message Format


State variable definition must begin with left bracket ([): (<code>, <text>)

CAUSE:	The state variable definition field following the STATES: keyword in an SMF begins with <text> instead of the required left square bracket ([). (<code> is an internal diagnostic code.)

ACTION:	Use square brackets ([ ]) to enclose the state variable names and state variable values in the States Subsection.

See also:

MAX+PLUS II Messages

Message Format


State variable definition must end with right bracket (])

CAUSE:	The state variable definition field in the States Subsection of an SMF does not end with a right square bracket (]).

ACTION:	Ensure that the state variable names and each group of state variable values are enclosed in square brackets ([ ]).

See also:

MAX+PLUS II Messages

Message Format


States Subsection terminated incorrectly

CAUSE:	An SMF contains a state machine whose States Subsection is not terminated by a right bracket (]) or not followed by a Transitions Subsection, Machine Section, Truth Table Section, or END$ statement.

ACTION:	Ensure that the States Subsection ends with one of the items listed above.

See also:

MAX+PLUS II Messages

Message Format


Symbol too long in <state machine name>

CAUSE:	Too many characters are in a state variable name, state name, or node name in an SMF .

ACTION:	Use a maximum of eight alphanumeric characters in the names listed above.

See also:

MAX+PLUS II Messages

Message Format


Too many state variables (max. = 16)

CAUSE:	An SMF contains a state machine with more than 16 state variables, which is the maximum allowed.

ACTION:	Reduce the number of state variables in each state machine to 16 or fewer. You may use multiple state machines in a single SMF.

See also:

MAX+PLUS II Messages

Message Format


Too many/few state variable values

CAUSE:	The number of state variable values given in a state definition of an SMF is not equal to the number of state variable names listed at the beginning of the States Subsection.

ACTION:	Ensure that as many state variable values exist as state variable names.

See also:

MAX+PLUS II Messages

Message Format


Truth table: missing <text> declarations

CAUSE:	The T_TAB: keyword in an SMF is not followed by any <text> (i.e., input or output) declarations, which are required.

ACTION:	Add truth table inputs/outputs to your design file. Ensure that input and output declarations are separated by a colon (:).

See also:

MAX+PLUS II Messages

Message Format


Truth table: too many/few <text> arguments

CAUSE:	The number of arguments specified for <text> (i.e., inputs or outputs) in an SMF does not match those given in the input/output declarations of the truth table (i.e., on the first line).

ACTION:	Ensure that there are as many input and output arguments as input and output declarations in each truth table.

See also:

MAX+PLUS II Messages

Message Format


Undeclared input: <pin name>

CAUSE:	The pin name given in an INP primitive in the Network Section of an SMF was not declared in the Inputs Section.

ACTION:	Add the specified pin name to the Inputs Section or remove the INP primitive statement.

See also:

MAX+PLUS II Messages

Message Format


Undefined state: (<state name>) in <state machine name>

CAUSE:	The indicated state name used in the Transitions Subsection of an SMF is not defined in the States Subsection.

ACTION:	Define all states in the States Subsection.

See also:

MAX+PLUS II Messages

Message Format


Unexpected EOF in <section name>

CAUSE:	The End-of-File (EOF) in an SMF was reached prematurely. This message indicates that the SMF is incomplete, is not terminated with the required END$ statement, or that a statement in the Network Section has more than 256 characters on a single line.

ACTION:	Ensure that the last line of the SMF is the END$ statement and that lines in the Network Section contain 256 or fewer characters.

See also:

MAX+PLUS II Messages

Message Format


Unreachable <text> Statement: (<state name>) in <state machine name>

CAUSE:	The Compiler detected a Case Statement in an SMF that was preceded by an unconditional transition.

ACTION:	Ensure that the order of transitions allows all transitions to be reached. (All transitions are evaluated in the order in which they are entered.) If the unconditional transition represents the implied ELSE, it must follow the Case Statement transition.

See also:

MAX+PLUS II Messages

Message Format


Unreachable conditional statement: (<state name>) in <state machine name>

CAUSE:	The Compiler detected a conditional transition (IF statement) in an SMF that was preceded by an unconditional transition.

ACTION:	Ensure that the order of transitions allows all transitions to be reached. (All transitions are evaluated in the order in which they are entered.) If the unconditional transition represents the implied ELSE, it must follow the conditional transition.

See also:

MAX+PLUS II Messages

Message Format


Unreachable unconditional statement: (<state name>) in <state machine name>

CAUSE:	The Compiler detected two unconditional transition statements in succession in an SMF.

ACTION:	Check the SMF for errors and ensure that each unconditional transition follows a conditional transition.

See also:

MAX+PLUS II Messages

Message Format


Unrecognized section

CAUSE:	An SMF contains an unrecognized section keyword or symbol name.

ACTION:	Check the SMF for syntax errors and remove all keywords other than OPTIONS:, PART:, INPUTS:, OUTPUTS:, NETWORK:, EQUATIONS:, MACHINE:, CLOCK:, CLEAR:, STATES:, OUTPUTS:, and T_TAB:.

See also:

MAX+PLUS II Messages

Message Format


Unrecognized symbol in state assignment

CAUSE:	The state assignment (state variable value) in the States Subsection of an SMF contains a string that is not a 1, 0, or X (in positional format), or a complemented or uncomplemented state variable name (in keyword format).

ACTION:	Check the States Subsection for errors. Ensure that the state variable values are assigned in only one of the two formats given above.

See also:

MAX+PLUS II Messages

Message Format


---------------------------------------BEGINNING OF NON-TRANSLATED TEXT-----------------------------------------

10/15/93: Added "CMD," "HST," "LOG," "TBL," "VEC," and "SNF" (shared panels)

---------------------------------------END OF NON-TRANSLATED TEXT-----------------------------------------


Simulator Basic Tools
Basic Tools

Breakpoints

Buttons

Start

Pause

Stop

Open SCF

Fields

Simulation Input

Simulation Time

Start Time

End Time

Input & Output Files

Assignment & Configuration File (.acf)

ACF Format

Command File (.cmd)

Command File Format

Fit File (.fit)

History File (.hst)

Log File (.log)

Memory Initialization File (.mif)

Memory Initialization Output File (.mio)

Simulator Channel File (.scf)

Simulator Initialization File (.sif)

Simulator Netlist File (.snf)

Table File (.tbl)

Vector File (.vec)

Vector File Format

MAX+PLUS II Initialization & System Files

maxplus2.idx File

maxplus2.ini File

Options

Check Outputs

Glitch

Oscillation

Setup/Hold

Use Device

Probe, Resource & Device Assignments

Clique Assignments

Connected Pin Assignments

Device Assignments

Logic Option Assignments

Pin, Location & Chip Assignments

Probe Assignments

Timing Assignments

Simulation Modes

Functional

Linked

Timing

Status Bar & Toolbar

Status Bar

Toolbar

Widgets

Progress Bar


Start Button (Simulator)
Start Button

Begins simulation. Show me

Simulation is performed on the basis of the following menu commands, options, and time fields:

Command/Option:	Function:

Start Time	Specifies the time when simulation will begin.

End Time	Specifies the time when simulation will end.

Use Device	Specifies that the outputs of a programmed device will be recorded instead of simulation outputs.

Setup/Hold	Turns setup and hold time violation monitoring on or off.

Check Outputs	Specifies that simulation outputs will be compared to the outputs in the SCF or Vector File.

Glitch	Turns glitch monitoring on or off; changes the definition of the glitch time interval.

Oscillation	Turns oscillation monitoring on or off; changes the definition of the oscillation time interval.

Inputs/Outputs	Specifies the input and output files to be used for simulation, including one or more of the following: SCF, Vector File, History File, and Log File.

Initialize	Specifies initial values for nodes and/or groups in the project.

Breakpoint	Specifies breakpoint conditions.

Many of the options and functions listed above can also be specified by executing a Command File before beginning simulation.

Once simulation has started, you can choose Pause to temporarily halt it, or Stop to end it. Simulation runs as a background process, so you can locate the sources of any error or warning messages displayed in the Message Processor window, or edit files in a MAX+PLUS II editor application while the Simulator is running.

During simulation, the output logic levels in the output SCF are automatically updated. You can choose Open SCF to open the SCF in a Waveform Editor window. If the Waveform Editor is displaying the SCF, you can watch the simulated outputs as they are written to the file. However, you cannot edit the SCF while simulation is in progress.

Viewing the SCF in the Waveform Editor during simulation reduces the speed of the simulation.

You can also change the status of the Setup/Hold, Glitch, and Oscillation options as the simulation proceeds.

See also:

Executing a Command File

Running an Interactive-Mode Simulation

SIMULATE (Command File)

Starting, Pausing & Stopping the Simulator


Pause Button (Simulator)
Pause Button

Temporarily suspends simulation. Show me

Pause allows you to change certain parameters before the simulation continues. Pause becomes available only after you have started simulation by choosing the Start button or the Execute Command File command.

While the simulation is suspended, only the following Simulator-specific commands, buttons, and options are available:

Command/Option/Button:	Available Functions:

Create Table File	Creates a Table File.

Inputs/Outputs	Turns History File or Log File command recording on or off; changes the History or Log File names. You cannot change the Vector File or SCF, or edit the current SCF.

Initialize	Lists node and group values; saves current node and group values to an SIF. You cannot initialize nodes or groups or restore initialized values from an SIF during a pause.

Setup/Hold	Turns setup and hold time violation monitoring on or off.

Oscillation	Turns oscillation monitoring on or off; changes the definition of the oscillation time interval.

Glitch	Turns glitch monitoring on or off; changes the definition of the glitch time interval.

Open SCF 	Opens the SCF for the project in a Waveform Editor window.

To leave the paused state, choose Start to resume the simulation or Stop to end it.

See also:

Starting, Pausing & Stopping the Simulator


Stop Button (Simulator)
Stop Button

Stops the simulation. Show me

The Simulation Time field shows the time when simulation was halted.

If you stop simulation, you can specify a new Start Time and start the simulation again with the Start button, or start a batch-mode simulation with the Execute Command File command.

See also:

Pause Button

Running an Interactive-Mode Simulation

Starting, Pausing & Stopping the Simulator


Open SCF Button (Simulator)
Open SCF Button

Opens the Simulator Channel File (.scf) for the current project in a Waveform Editor window. Show me

Open SCF allows you to quickly open an SCF in order to display the results of simulation, view the simulation outputs as they are written, or edit the file. You can use Open SCF before, during, or after simulation.

The Simulator automatically loads the newest SCF or Vector File with the same filename as the project. You can also specify a different SCF or Vector File as the source of input vectors with the Inputs/Outputs command. MAX+PLUS II automatically converts a Vector File into an SCF before simulation or functional testing.

Open SCF is available only if an SCF or Vector File with the same name as the project exists in the project directory, or if you have specified an SCF or Vector File with Inputs/Outputs.

See also:

Opening a File


Command File (.cmd) Description
Command File (.cmd)

An ASCII text file (with the extension .cmd) that contains commands for a batch-mode simulation.

Commands in the file are entered in Command File format, which offers an easily readable alternative to the Simulator’s menu commands, on-screen options, and buttons. This format is also used to record commands in the optional Log File and/or History File created during interactive- or batch-mode simulation.

You can create a Command File with the MAX+PLUS II Text Editor or a standard text editor in non-document mode. A Log File (.log) can also be renamed with the extension .cmd and used as a Command File.

The icon for each Command File with the same filename as the top-level design file in the current hierarchy tree appears in the Hierarchy Display window.

See also:

Executing a Command File

Running a Batch-Mode Simulation

Sample Command File


History File (.hst) Description
History File (.hst)

An ASCII text file (with the extension .hst) that records the commands (including on-screen options and buttons) executed by the Simulator, command output, and messages.

Commands are recorded in Command File format. Command output is always indented to distinguish it from the command itself. Messages are the same as those displayed in the Message Processor window.

In interactive-mode simulation, you begin command history logging by turning on the History (.hst) option in the Inputs/Outputs dialog box. History logging ends when you close the Simulator or turn off the History (.hst) option. You can overwrite an existing History File by turning on the New option; commands are appended to an existing file if you turn off the New option. In batch-mode simulation, these functions are performed by the Command File’s HISTORY CREATE, HISTORY OFF, and HISTORY ON commands.

Some interactive-mode commands and options in the file are shown in comment format, enclosed within percent symbols (%). The following functions are in comment format so that the Simulator will not attempt to execute them if you edit and reuse the file as a Command File for batch-mode simulation:

% LOG CREATE %

% LOG ON %

% LOG OFF %

% USE DEVICE %

The icon for each History File with the same filename as the top-level design file in the current hierarchy tree appears in the Hierarchy Display window.

See also:

Recording Simulation Commands & Output History


Log File (.log) Description
Log File (.log)

An ASCII text file (with the extension .log) that records the commands, on-screen options, and buttons used during a simulation session. Commands are recorded in the Command File format. This file is similar to the History File, except that the output of the commands is not recorded.

In interactive-mode simulation, you begin command logging by turning on the Log (.log) option in the Inputs/Outputs dialog box. Command logging ends when you close the Simulator or turn off the Log (.log) option. You can overwrite an existing file by turning on the New option; commands are appended to an existing file if you turn off the New option. Command logging is not available during batch-mode simulation because the Log File would be identical to the Command File.

A Log File can be used as a Command File for batch-mode simulation with the Execute Command File command. However, Altera recommends that you rename the file with the Command File extension .cmd with the Text Editor’s Save As command.

Some interactive-mode commands and options in the file are shown in comment format, enclosed within percent symbols (%). The following functions are in comments so that the Simulator will not attempt to execute them if the file is reused as a Command File:

% LOG CREATE %

% LOG ON %

% LOG OFF %

% USE DEVICE %

The icon for each Log File with the same filename as the top-level design file in the current hierarchy tree appears in the Hierarchy Display window.

See also:

Executing a Command File

Logging Simulation Commands


Memory Initialization File (.mif) Description
Memory Initialization File (.mif)

An ASCII text file (with the extension .mif) that specifies the initial content of a memory block (RAM or ROM).

An MIF is used as an input file for memory initialization in the Compiler and Simulator. (You can also use a Hexadecimal File (.hex) to provide memory initialization data.) An MIF contains the initial values for each address in the memory. A separate file is required for each memory block. In an MIF, you are also required to specify the memory depth and width values. In addition, you can specify the radixes used to display and interpret addresses and data values. Following is a sample MIF:

DEPTH = 32;	% Memory depth and width are required	%

WIDTH = 14;	% Enter a decimal number	%

ADDRESS_RADIX = HEX;	% Address and value radixes are optional	%

DATA_RADIX = HEX;	% Enter BIN, DEC, HEX, or OCT; unless 	%

% otherwise specified, radixes = HEX	%

-- Specify values for addresses, which can be single address or range

CONTENT

BEGIN

[0..F]	:	3FFF;	% Range--Every address from 0 to F = 3FFF	%

6	:	F;	% Single address--Address 6 = F	%

8	:	F E 5;	% Range starting from specific address--	%

END ;	% Addr[8] = F, Addr[9] = E, Addr[A] = 5	%

You can create an MIF in the MAX+PLUS II Text Editor or any ASCII text editor. You can also very easily generate an MIF by exporting data from the Simulator’s Initialize Memory dialog box; this method is especially useful when you need to initialize a small memory block. In addition, Memory Initialization Output Files (.mio), which are generated when you create a Text Design Output File (.tdo), can be renamed and used as MIFs.

The file icon for an MIF with the same filename as the top-level design file in the current hierarchy tree appears in the Hierarchy Display window.

See also:

Creating AHDL Text Design Output Files

Initializing RAM/ROM Memory


Memory Initialization Output File (.mif) Description
Memory Initialization Output File (.mio)

An ASCII text file (with the extension .mio) that is generated when you create a Text Design Output File (.tdo) for a project.

An MIO File contains the initial memory values for each address in a memory block (RAM or ROM), similar to the information in a Memory Initialization File (.mif).

An MIO File is generated for each user-defined logical memory block. However, if the Logic Synthesizer module synthesizes away a portion of the memory block during compilation, a MIO File is created for each of the memory segments that comprises the memory block.

You can rename an MIO File as an MIF and use it with a TDO File that has been saved as a Text Design File (.tdf).

The file icon for an MIO with the same filename as the top-level design file in the current hierarchy tree appears in the Hierarchy Display window.

See also:

Changing the File Type

Initializing RAM/ROM Memory


Simulator Initialization File (.sif) Description (Simulator)
Simulator Initialization File (.sif)

A file (with the extension .sif) that records all node and group logic levels at the current Simulation Time, including input and output pins, and register inputs and outputs. Values that have been initialized with the Initialize command are included in the information saved in the SIF.

In interactive-mode simulation, you create a new SIF by choosing the Save button in the Initialize dialog box and typing a filename in the Save Initialization As dialog box. You can reuse an SIF later by choosing the Restore button in the Initialize dialog box. In batch-mode simulation, these functions are performed by the INIT WRITE and INIT READ Command File commands, respectively.

When an SIF is restored, any logic levels in the SIF that conflict with the input logic levels in the SCF or Vector File are ignored. SCF or Vector File values always have precedence over SIF values.

You should never edit the SIF. If you do edit the file, you should create a new SIF.

See also:

Restoring Node & Group Initialization Values

Saving Node & Group Initialization Values


Simulator Netlist File (.snf) Description
Simulator Netlist File (.snf)

A binary file (with the extension .snf) generated by the MAX+PLUS II Compiler that is used for functional simulation and/or for timing simulation and timing analysis.

You can generate one of three types of SNFs for a project:

A functional SNF contains only logic information.

A timing SNF contains the logic and timing information required for simulation and timing analysis.

A linked SNF contains timing and/or functional information.

When the Compiler generates a new functional, timing, or linked SNF, any existing SNF with the same name is overwritten. Therefore, only one type of SNF can exist at a time for a project.

A functional, timing, or linked SNF is generated when you turn on the Compiler’s Functional SNF Extractor, Timing SNF Extractor, or Linked SNF Extractor command before compiling the project. These commands activate the optional Functional SNF Extractor, Timing SNF Extractor, or Linked SNF Extractor modules, respectively. A successfully generated SNF indicates that the project has no syntactic errors; simulation and timing analysis help you determine whether it contains any logic errors.

From the Compiler, you can double-click Button 1 on the SNF icon to open the Simulator window and load the SNF for the project. The Simulator automatically enters the functional simulation, timing simulation, or linked simulation mode (shown in the title bar of the window) based on the type of SNF most recently generated.

Functional SNF

A functional SNF is used to test the logical performance of a project in a functional simulation. This file contains no timing information; however, it is generated much more quickly than a timing SNF and provides simulation access to all nodes and probes in the project.

Timing SNF

A timing SNF contains all timing information required for full timing simulation and timing analysis. It describes the fully optimized circuit design after all logic synthesis and design fitting have been completed. With the Simulator’s Initialize command or the Waveform Editor’s Enter Nodes from SNF or Enter Node commands, you can check whether nodes and groups in the project’s design files have been removed by logic minimization and synthesis. All "surviving" nodes, groups, and probes in the project, and hence the timing SNF, can be listed in the dialog boxes for these commands. If a project is partitioned into multiple devices, the Compiler creates a timing SNF for the project as a whole. Therefore, timing simulation is available only for the project as a whole. Neither timing simulation nor functional testing is available for individual devices in a multi-device project.

The Compiler automatically generates one or more timing SNFs when you request EDIF Output File(s) for the project with the EDIF Netlist Writer command.

If Optimize Timing SNF is turned on during timing SNF extraction, the Compiler generates a timing SNF in which sections of combinatorial logic are replaced with dynamic models. The Simulator refers to these models during simulation and thereby avoids processing large networks of combinatorial logic, reducing the time required for processing. An optimized timing SNF also improves the speed of a timing analysis.

Linked SNF

A linked SNF is created by compiling a super-project that consists of a top-level design file containing symbols or instances that represent multiple individual projects. These symbols or instances represent the existing timing, functional, or linked SNFs for each sub-project, not the actual design files. A linked SNF combines the functional and timing information in each sub-project’s SNF. You can use the linked SNF to perform a board-level-type simulation. If a linked SNF contains timing information only, you can also use it to run a timing analysis.

See also:

Combining Multiple Projects for Simulation

Creating a Functional Simulator Netlist File

Creating a Timing Simulator Netlist File

Listing Node & Group Values

Primitives in Simulator Netlist Files & EDIF Output Files


Propagation of Undefined (X) Logic Levels (Simulator)
Propagation of Undefined Logic Levels

Undefined (X) logic levels in an SCF or Vector File propagate according to the rules given below.

Logic Functions

If at all possible, defined levels are maintained. For example, if a low (0) logic level is ANDed with an X logic level, the result is a logic low. The following levels are propagated for the AND, OR, and NOT logic functions:

0 AND X = 0

1 AND X = X

X AND Z = X

X AND X = X

0 OR X = X

1 OR X = 1

X OR Z = X

X OR X = X

NOT X = X

Flipflops & Latches

If the output level of a flipflop or latch would remain constant regardless of an X input level, this output level is maintained. For example, if an X Clock is applied to a DFF flipflop with the data input at logic high (1) and the output node at 1, a 1 is maintained on the output.

If the output level of a flipflop or latch may change depending on an X input level, the output node is set to X.

If an X Clock is applied to a DFF flipflop, the output is maintained until the data input no longer equals the output. At that time, the output changes to X.

Output Enable Inputs

If a tri-state buffer has an undefined Output Enable input, the output of that buffer will be X.

When a tri-state buffer is disabled, the output on a bidirectional pin does not necessarily show a high-impedance (Z) logic level. The logic level on a bidirectional pin depends not only on the tri-state buffer output, but also on the input logic level that is applied to the bidirectional pin.


Table File (.tbl) Description
Table File (.tbl)

An ASCII text file (with the extension .tbl) that contains the same information as the current SCF or WDF, i.e., all logic levels and the names of nodes and groups in the file.

The Simulator generates a Table File when you choose Create Table File before, after, or at a pause during simulation. This Table File is a "snapshot" of the current SCF, which records all input vectors and output logic levels. Simulator-generated output logic levels are included up to the time displayed in the Simulation Time Field; undefined (X) logic levels are shown for outputs that have not yet been simulated.

The Waveform Editor generates a Table File at any time when you choose Create Table File. This Table File contains all data from a WDF or an SCF.

A Table File created by the Simulator reports logic levels for the nodes and groups in the Vector File or SCF specified with Inputs/Outputs as the source of input vectors for simulation or functional testing. The reported nodes consist of all nodes and groups in the SCF, or the nodes and groups listed in the Vector File’s Inputs, Outputs, and Buried Sections.

Table File format is a subset of Vector File format. Node and group logic levels appear in the same order as in the input Vector File or SCF. State machine values are expressed as group values or state names. Group values are listed according to their individual radixes, set with the Enter Group command in the SCF or the Radix Section of the Vector File.

A Table File can be specified as a vector input file for another simulation or functional testing with Inputs/Outputs. However, Altera recommends that you rename the file as a Vector File (with the extension .vec) with the Text Editor’s Save As command.

The icon for each Table File with the same filename as the top-level design file in the current hierarchy tree appears in the Hierarchy Display window.

See also:

Creating a Table File (Simulator)

Creating a Table File (Waveform Editor)


Vector File (.vec) Description
Vector File (.vec)

An ASCII text file (with the extension .vec) used as the input for simulation, functional testing, or waveform design entry.

A Vector File can be used as an input file for simulation or functional testing in the Simulator or Programmer. A Vector File with the same filename as the current project is loaded automatically in either application; you can use Inputs/Outputs to specify files with other names. Information in the file is entered in Vector File format.

A Vector File used for simulation or functional testing specifies the input logic levels (i.e., vectors) that drive the input pins and determine the internal logic levels throughout the project, the output nodes to be simulated, the start and stop times for applying vectors, the intervals at which vectors are applied, the nodes to be grouped during simulation, and the radix used to interpret logic levels. Project inputs without vectors are automatically assigned undefined (X) logic levels during simulation and low (0) logic levels during functional testing. The file also includes the names of any combination of output nodes to be simulated, including buried output nodes. Expected output levels are optional in a Vector File used for simulation; they are required for functional testing.

The Simulator and Programmer require a Vector File or Simulator Channel File to provide the input vectors that drive simulation or functional testing. In the Programmer, vectors that have been saved in the programming file can also be used for functional testing. If a Vector File is specified, the Simulator automatically converts it into an SCF before simulation or functional testing begins. The Vector File also determines the order of nodes, groups, and group radixes that are stored in the automatically generated SCF.

The Simulator automatically creates an SCF when you use a Vector File as the source of input vectors. The Simulator creates and/or overwrites any existing SCF with the same filename as the Vector File before simulation or functional testing begins. In the Programmer, the vectors in the Vector File or programming file are converted into a temporary data buffer with the same format as an SCF before functional testing begins.

A Vector File can be imported into the Waveform Editor with the Import Vector File command, then saved as a Waveform Design File and used for waveform design entry. This type of Vector File specifies various combinations of input signals and desired output signals. It contains nodes that represent input pins, output pins, and buried logic. The type of logic that a node represents is further categorized as fed by pin input, combinatorial, registered, or state machine logic.

You can create a Vector File with the MAX+PLUS II Text Editor or any other standard text editor in non-document mode. A Table File can also be renamed with the extension .vec and used as a Vector File.

You can switch from one Vector File to another during a simulation or functional testing session, although you can use only one file at any given time.

The following information will help you create and interpret Vector Files effectively:

Functional Testing with the SCF, Vector File, or Programming File

Output Monitoring Requirements for the SCF or Vector File

Propagation of Undefined Logic Levels

Simulating Bidirectional Pins

The icon for each Vector File with the same filename as the top-level design file in the current hierarchy tree appears in the Hierarchy Display window.

See also:

Getting Context-Sensitive Help

Importing a Vector File (Waveform Editor)

Sample Vector File

Specifying the Source of Input Vectors (Programmer)

Specifying the Source of Input Vectors (Simulator)


Breakpoints (Simulator)
Breakpoints

Consist of one or more node value, group value, and time conditions.

You can choose Breakpoint to display the Breakpoint dialog box, which allows you to add, delete, change, enable, and disable new and existing breakpoints.

When the conditions for a particular breakpoint are fulfilled during simulation, the Simulator pauses and reports the time in a message box and in the Message Processor window. During the pause, you can choose Start to resume simulation or Stop to end it.

See also:

BREAK CREATE (Command File)

BREAK DELETE & BREAK LIST (Command File)

Changing a Breakpoint

Creating a Breakpoint

Deleting a Breakpoint


Check Outputs Option (Simulator)
Check Outputs Option

Turns output monitoring on or off. Show me

Check Outputs instructs the Simulator to monitor all simulated nodes and groups. During simulation, the Simulator checks whether simulated outputs differ functionally from the outputs given in the input SCF or the SCF generated automatically for a Vector File. Check Outputs always compares outputs functionally, regardless of whether the Simulator is in functional simulation mode, timing simulation mode, or linked simulation mode.

When Check Outputs is turned on, the output logic levels generated by the Simulator are not saved in the SCF. Instead, the Simulator automatically executes the Waveform Editor’s Compare command when the SCF is opened, which superimposes the simulated outputs on the SCF outputs. In addition, a Message Processor window opens automatically and reports any differences between the simulated outputs and the SCF’s expected outputs. Outputs are compared according to functional comparison rules. When Check Outputs is turned off, the outputs that are recorded in the SCF are saved according to SCF output overwriting rules.

If Use Device is turned on when Check Outputs is on, the Simulator performs function testing, i.e., actual device outputs are compared to SCF outputs in accordance with functional comparison rules.

See also:

Checking Simulation Outputs vs. User-Defined Outputs

CHECK ON & OFF (Command File)

Comparing Files or Simulation Outputs

Testing Device Outputs vs. Simulation Outputs


Glitch Option (Simulator)
Glitch Option

Turns glitch monitoring on or off. Show me

Glitch can be turned on or off at any time, regardless of whether or not a simulation is running.

In functional simulation mode, Glitch checks only for nil-time glitches and you cannot specify the glitch interval. In timing simulation mode and linked simulation mode, you can set the time interval that defines a glitch. The time you enter in the Glitch text field should be followed immediately (i.e., with no space in between) by a time unit; the default unit is ns. The minimum glitch value for a timing or linked simulation is 0.1 ns.

If Glitch is on during simulation, the Message Processor issues a message if multiple logic level changes occur on a single node over a period less than or equal to the specified glitch time. This time is always nil in functional simulation mode.

The Glitch option can increase the time it takes to simulate a project. You may wish to monitor the project for glitches during specific simulation periods, rather than at all times.

See also:

GLITCH (Command File)

Defining & Detecting Glitches


Oscillation Option (Simulator)
Oscillation Option

Turns oscillation monitoring on or off. Show me

In timing simulation mode, Oscillation can be turned on or off at any time, regardless of whether or not a simulation is running. Oscillation is always turned on in functional simulation mode.

In functional simulation mode, Oscillation checks only for nil-period oscillation. In timing simulation mode, you can set the time interval that defines oscillation. The time you enter in the Oscillation text field should be followed immediately (i.e., with no space in between) by a time unit; the default unit is ns.

In linked simulation mode, Oscillation checks for both user-defined and nil-period oscillation. You can turn the option on or off for the timing SNFs that appear in the super-project; the check for nil-period oscillation is always turned on.

If Oscillation is on during simulation, the Message Processor issues a message if any node or group logic level does not stabilize within the specified oscillation time interval after each input vector has been applied. This time is always nil in functional simulation mode. The circuit is considered to have stabilized if no new input vectors are available and all node and group logic levels have stopped changing.

If the Simulator finds nil-period oscillation during functional simulation, it opens a message box that allows you to skip to the next set of input vectors so that the oscillation will not continue indefinitely.

The Oscillation option can increase the time it takes to simulate a project. You may wish to monitor the project for oscillations during specific simulation periods, rather than at all times.

See also:

OSCILLATION (Command File)

Defining & Detecting Oscillation


Setup/Hold Option (Simulator)
Setup/Hold Option

Turns setup time and hold time monitoring on or off. Show me

Setup/Hold can be turned on or off at any time, regardless of whether or not a simulation is running.

If Setup/Hold is on and a setup or hold time violation occurs, the Message Processor reports the hierarchical node name of the register output and the time of the violation.

In functional simulation mode, violations occur if the setup or hold time is less than 0.1 ns. In timing simulation mode, setup and hold time violations are determined by the architecture of the device being simulated. When the Compiler creates the timing SNF for a project, it refers to the DMF for the target device for specific information on timing characteristics. In linked simulation mode, setup and hold time violations are also determined by the device architecture specified for each project in the super-project.

Using the Setup/Hold option in a functional simulation may be inappropriate for projects that contain counters or shift registers, since normal operation of these functional circuits will cause numerous setup and hold time violations.

The Setup/Hold option can increase the time it takes to simulate a project. You may wish to monitor the project for setup and hold violations during specific simulation periods, rather than at all times.

See also:

SETUP ON & OFF (Command File)

Detecting Setup & Hold Violations

Locating the Source of a Message

Setup/Hold Matrix Command (Timing Analyzer)


Use Device Option (Simulator)
Use Device Option

Applies vector inputs to a programmed device and saves actual device outputs to the current Simulator Channel File. Show me

Use Device specifies that the input vectors for simulation should be applied to a single device programmed with the current project. If a project is partitioned into multiple devices, or it is a "super-project" that contains multiple projects, Use Device is not available. When Use Device is turned on, the outputs that are recorded in the SCF are saved according to SCF output overwriting rules.

All output and buried nodes that are not actual pin outputs are overwritten with undefined (X) logic levels. Only pin names in the SCF that are also listed in the Fit File for the project are used to generate the functional output data.

Actual device output transition times cannot be measured with the same accuracy as simulated outputs. Therefore, output logic level changes in the SCF are shown at the same time as the corresponding input vector changes, providing functional device outputs. These functional device outputs are recorded regardless of whether the Simulator is in the functional simulation mode or the timing simulation mode.

If Use Device is turned on, you must place a programmed device in the MPU adapter socket before choosing Start to begin simulation. If both Use Device and Check Outputs are turned on, the Simulator performs function testing, i.e., actual device outputs are compared to SCF outputs in accordance with functional comparison rules.

The Use Device option is available only if you have installed Altera’s MPU and the appropriate adapter.

See also:

Adapters

Functional Testing with the SCF, Vector File, or Programming File

Inserting a Device into the Socket

Saving Actual Device Outputs

Testing Device Outputs vs. Simulation Outputs


Functional Simulation Mode (Simulator)
Functional Simulation Mode

The Simulator enters the functional simulation mode when the Compiler’s Functional SNF Extractor module has generated a functional SNF for the current project, and the title bar of the Simulator window displays Simulator: Functional Simulation.

When the Simulator is running in the functional simulation mode, the behavior of the Glitch, Oscillation, and Setup/Hold options differs from their behavior in the timing simulation mode and linked simulation mode. The functionality of all other Simulator buttons, options, and commands remains the same.

In functional simulation mode, output logic levels change at the same time as the input vectors. No propagation delays are used.

Regardless of whether the Simulator is in functional, timing, or linked simulation mode, simulation outputs are functionally compared to the outputs in the SCF if the Check Outputs option is turned on. If Use Device is also on, the Simulator performs functional testing, i.e., actual device outputs are compared to SCF outputs. Outputs are compared according to functional comparison rules.

The Simulator automatically changes between simulation modes on the basis of which type of SNF exists for the current project, i.e., functional, timing, or linked SNF.

See also:

Simulator Netlist File (.snf)

Creating a Functional Simulator Netlist File


Linked Simulation Mode (Simulator)
Linked Simulation Mode

The Simulator enters the linked simulation mode when the Compiler’s Linked SNF Extractor module has generated a linked SNF for the current project that contains timing and/or functional information. The title bar of the Simulator window displays Simulator: Linked Simulation.

When the Simulator is running in the linked simulation mode, the functionality of all Simulator buttons, options, and commands remains the same as in the timing simulation mode, except for the Oscillation and Use Device options. In linked simulation mode, Oscillation checks for both user-defined and nil-period oscillation. The Use Device option is not available.

Regardless of whether the Simulator is in linked, timing, or functional simulation mode, simulation outputs are functionally compared to the outputs in the SCF with the Check Outputs option. Outputs are compared according to functional comparison rules.

The Simulator changes between simulation modes on the basis of which type of SNF exists for the current project. For example, the Simulator automatically changes from the linked simulation mode to the timing simulation mode when you recompile the project with the Timing SNF Extractor module of the Compiler turned on. This module generates a timing SNF, which is required to run the Simulator in the timing simulation mode.

See also:

Simulator Netlist File (.snf)

Combining Multiple Projects for Simulation


Timing Simulation Mode (Simulator)
Timing Simulation Mode

The Simulator enters the timing simulation mode when the Compiler’s Timing SNF Extractor module has generated a timing SNF for the current project, and the title bar of the Simulator window displays Simulator: Timing Simulation.

When the Simulator is running in the timing simulation mode, the behavior of the Glitch, Oscillation, and Setup/Hold options differs from their behavior in the functional simulation mode. The functionality of all other Simulator buttons, options, and commands remains the same.

Regardless of whether the Simulator is in timing, functional, or linked simulation mode, simulation outputs are functionally compared to the outputs in the SCF with the Check Outputs option; if Use Device is also on, actual device outputs are compared to SCF outputs. Outputs are compared according to functional comparison rules.

The Simulator automatically changes between simulation modes on the basis of which type of SNF exists for the current project, i.e.,  functional, timing, or linked SNF.

If a project is partitioned into multiple devices, the Compiler creates a timing SNF for the project as a whole. Therefore, timing simulation is available only for the project as a whole. Neither timing simulation nor functional testing is available for individual devices in a multi-device project. Functional testing is available only for a single-device project.

See also:

Simulator Netlist File (.snf)

Creating a Timing Simulator Netlist File


Simulation Input Field (Simulator)
Simulation Input Field

Displays the name of the Simulator Channel File or Vector File that contains the input vectors for simulation. When you first open the Simulator, an SCF or Vector File with the same name as the project is automatically loaded. Show me

You can change the simulation input for the current project with Inputs/Outputs. Double-clicking Button 1 on the Simulation Input field opens the Inputs/Outputs dialog box. After you select an input file, the Simulation Input field changes to display the name of the selected file.

See also:

CHANNEL (Command File)

Running an Interactive-Mode Simulation

VECTOR (Command File)


Simulation Time Field (Simulator)
Simulation Time Field

Shows the current simulation time. Show me

When you first open the Simulator, the Simulation Time is 0.0ns. After you choose Start to begin simulation, this field begins to change, reflecting the length of the elapsed simulation. It continues to change until the End Time is reached, or until you choose Pause or Stop.

The Simulation Time is automatically reset to 0.0ns if you close and reopen the Simulator window. It is automatically reset to the time specified in the Start Time field after you choose Start again after a simulation has been completed, i.e., when the Simulation Time equals the End Time.

See also:

SIMULATE (Command File)

Running an Interactive-Mode Simulation


Start Time Field (Simulator)
Start Time Field

Specifies the start of the time period to be simulated. Show me

When you first open the Simulator, the Start Time is 0.0ns. You can edit the Start Time field to begin or continue a simulation at a later time. The time you enter must be less than the time entered in the End Time field, and must be followed immediately (i.e., with no space in between) by a time unit; the default unit is ns.

The Start Time is automatically reset to 0.0ns if you close and reopen the Simulator window, or select a new Vector File or SCF with the Inputs/Outputs command.

See also:

SIMULATE (Command File)

Running an Interactive-Mode Simulation


End Time Field (Simulator)
End Time Field

Specifies the end of the time period to be simulated. Show me

The End Time field allows you to define the end of the time period for simulation. By default, it shows the end time of the Simulator Channel File or Vector File that is the source of input vectors for simulation. The End Time is automatically reset if you specify a new file as the source of input vectors.

After you choose Start, simulation continues until the specified end time is reached or until you choose Pause or Stop. If you specify a time past the end of the SCF, the Simulator stops automatically at the end of the SCF.

The time you enter in the End Time field must be greater than the current (elapsed) time shown in the Start Time field, and must be followed immediately (i.e., with no space in between) by a time unit; the default unit is ns. If you do not edit the End Time field, it is automatically updated if you change the end time of the current SCF or Vector File.

See also:

SIMULATE (Command File)

Running an Interactive-Mode Simulation

Specifying the Source of Input Vectors


Progress Bar (Simulator)
Progress Bar

Shows how much of the current simulation has been completed. Show me

After you choose Start, Save & Simulate, or Execute Command File to begin simulation, the progress bar shows how much of the simulation has been completed. When the progress bar reaches 100%, the simulation has reached the End Time; you can then enter new simulation conditions and run another simulation.

See also:

Starting, Pausing & Stopping the Simulator


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"Show me" window used in SIM Basic Tools

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Simulator Window
MAX+PLUS II Simulator Window


Simulator Contents
Simulator Help Contents

Introduction

Basic Tools

Commands

Procedures

Golden Rules

Shortcuts

Messages

Glossary


Simulator--Context-Sensitive Help
Context-Sensitive Help

Context-sensitive help is available for all Simulator commands, dialog boxes and messages, and the following basic tools:

Buttons

Start

Pause

Stop

Open SCF

Fields

Simulation Input

Simulation Time

Start Time

End Time

Options

Breakpoint

Check Outputs

Glitch

Oscillation

Setup/Hold

Use Device

Status Bar & Toolbar

Status Bar

Toolbar

Widgets

Progress Bar

For information on other basic tools, see Simulator Basic Tools.

See also:

Getting Context-Sensitive Help


Simulator Introduction
Introduction

The MAX+PLUS II Simulator is a powerful tool for testing the logical operation and internal timing of your project. Because the Simulator allows you to verify your project before it is actually committed to hardware, it can dramatically shorten the time it takes to transform your initial design concept into working silicon. You can simulate a complete MAX+PLUS II project, regardless of the number of devices required to implement it. Show me

How Does the Simulator Work?

The MAX+PLUS II Simulator allows you to simulate a project in interactive mode with menu commands and on-screen options and buttons, or in batch mode with a Command File. Whether you choose interactive or batch mode, the Simulator automatically loads the current project and--based on the type of SNF most recently generated for the project with the MAX+PLUS II Compiler--enters the functional, timing, or linked simulation mode.

A functional SNF is generated before logic synthesis, partitioning, or fitting are performed; therefore, functional simulation allows you to simulate all nodes in a project. In functional simulation, the output logic levels change at the same time as the input vectors and no propagation delays are used during simulation. In contrast, timing simulation uses a timing SNF that contains all the information for a fully synthesized project, i.e, it only simulates nodes that have "survived" logic synthesis. A linked SNF, used for multi-project simulation, can contain both timing and/or functional information. A linked SNF is created by compiling a super-project that consists of a top-level design file that contains symbols or instances representing multiple individual projects. Functional, timing, and linked simulation are performed at a resolution of up to 0.1 ns.

You can choose to accelerate the timing simulation process by allowing the Compiler to replace sections of combinatorial logic in the timing SNF with dynamic models. Each dynamic model represents a particular combinatorial logic network. Instead of interpreting all the logic in a combinatorial network, the Simulator can refer to a representative dynamic model, thus reducing simulation time.

The Simulator uses an SCF or Vector File as the source of simulation input vectors. With the MAX+PLUS II Waveform Editor, you can create a default SCF directly from the project’s SNF and edit it to provide the input vectors. If you create a Vector File, the Simulator automatically generates an SCF from the Vector File before simulation begins.

The SCF also includes output and buried nodes for the project. During simulation or functional testing, input waveforms in the SCF remain unchanged. The output and buried logic levels in the file are either updated or are preserved and compared to other outputs according to your specifications. The Simulator allows you to check simulation outputs against any outputs in the SCF. The outputs in the SCF can be expected outputs, outputs from a previous simulation, or actual device outputs. You can also perform functional testing to compare the outputs of a programmed device against the simulation outputs. Other Simulator options allow you to monitor how your project responds to glitches, oscillations, and setup and hold time violations.

With the Waveform Editor, you can view the SCF as it is being updated by the Simulator or after simulation is completed. You can also save simulation outputs to a Table File.

Where to Start

Altera offers a variety of information to help you create and verify a project with MAX+PLUS II and the Simulator.

On-Line Help

On-line help supplies complete reference and how-to information on simulating your project.

Simulator Help Contents provide access to all on-line Simulator Help.

Simulator Golden Rules summarize essential guidelines and recommendations for using the Simulator.

Recommended Reading

Additional Altera publications help you understand MAX+PLUS II and the Simulator. The following application notes and briefs are relevant to using the Simulator:

AB86 (Designing & Simulating Bidirectional Buses with MAX+PLUS II Software)

AB92 (Simulating Internal Nodes with MAX+PLUS II Software)

AB100 (Understanding EPLD Timing)

See also:

How to Use MAX+PLUS II Help

Compiler Introduction

Waveform Editor Introduction


Simulator Window
MAX+PLUS II Simulator Window


Simulator Golden Rules
Golden Rules

The following golden rules will help you use MAX+PLUS II and the Simulator effectively. The time-savers will help you speed up the simulation process:

Golden Rules for the Simulator

Create a default SCF with the Waveform Editor’s Enter Nodes from SNF command or enter individual nodes (Enter Node command) from the project’s SNF instead of manually creating an SCF from "scratch," especially if your project contains state machine logic. The project’s SNF, which automatically includes state bits generated by the Compiler.

When you wish to simulate a state machine, create a default SCF. After compilation, the state bits in the SNF are automatically combined into a group with the same name as the state machine, regardless of whether you named the state bits in the original design files. The default SCF automatically contains the state machine group and bits.

If you prefer to use a text-based file rather than a waveform file, you can create a Vector File from an existing SCF by choosing Create Table File.

Ensure that the SCF or Vector File used in functional testing conforms to the rules in Functional Testing with the SCF, Vector File, or Programmer File.

When you use the Check Outputs option to check SCF outputs against simulation outputs, ensure that the SCF or Vector File used in simulation follows the guidelines in Output Monitoring Requirements for the SCF or Vector File.

When you wish to simulate a bidirectional pin, ensure that the SCF or Vector File used in simulation conforms to the rules in Simulating Bidirectional Pins.

Time-Savers for the Simulator

You can rename a Log File (.log) with the extension .cmd and use it as a Command File for batch-mode simulation. You can use the file as is or edit it to repeat all or part of an earlier simulation.

If you are simulating a project that contains a large, complex network of combinatorial logic, optimizing the timing SNF with dynamic models can significantly reduce simulation times. See Creating a Timing Simulator Netlist File.

Close the Waveform Editor window containing the SCF for the project you are simulating. Viewing the simulated outputs as they are written to the SCF reduces the speed of the simulation.

Turn off the Glitch, Oscillation, and/or Setup/Hold options.

Insert probes in the design files of a complex hierarchical project to replace lengthy hierarchical node names. See Assigning a Probe.

You can view node, group, and probe names that exist in the SNF by choosing the List button in the Initialize dialog box. All nodes, group, and probe names from the SNF appear in the Nodes & Groups box. Any additional groups defined in the SCF or Vector File are also listed.

General MAX+PLUS II Golden Rules

When you start work on a new design file, name it as the current project with Project Name right away so that you can compile it easily. You can always change the project name later.

Use the built-in hierarchy traversal features in MAX+PLUS II to move between design files for the current hierarchy. To open a lower-level file in a hierarchy, open the top-level file and then use the Hierarchy Display window or Hierarchy Down to open the lower-level files. If you choose Open or Retrieve to open a lower-level file, it is considered to be the top of a different hierarchy, and resource, device, and probe assignments that you enter are saved only for that hierarchy, not for the project.

When you create an ancillary file for a project, the icon for the file will appear in the Hierarchy Display if you use the same filename as the project.

Don’t edit any MAX+PLUS II system files, including HIFs, maxplus2.idx File, or the maxplus2.ini or file.

Use the Save As command if you wish to rename a design file or an ancillary file. Don’t rename design files from outside of MAX+PLUS II system (e.g., from DOS or with the Windows File Manager).

When you have completed a project, use Project Archive to ensure that you save a complete backup copy of all project files that will not be affected by future edits or deletions.

See also:

Simulator Introduction

Waveform Editor Golden Rules


Simulator Shortcuts
Shortcuts

The following list provides shortcuts for Simulator commands:

Command:	Shortcut:

Context-Sensitive Help	Shift+F1 or

Cascade	Shift+F5

Close	Alt+F4

Compiler

Exit MAX+PLUS II	Alt+F4 or double-click Button 1 on the Application Control Menu box

Floorplan Editor

Hierarchy Display

Hierarchy Project Top	Ctrl+T or

Initialize

New

Next	Ctrl+F6

Open	Ctrl+O or

Programmer

Project Name	Ctrl+J or

Project Save & Compile	Ctrl+L or

Project Save & Simulate	Ctrl+Shift+L or

Simulator

Switch To	Ctrl+Esc

Tile	Shift+F4

Timing Analyzer

See also:

Selecting Text


Simulator Procedures
Procedures

Assignments & Compiler Configuration Settings

Assigning a Clique

Assigning a Device

Assigning a Pin, Location, or Chip

Assigning a Probe

Assigning an Individual Logic Option or Synthesis Style

Assigning Connected Pins

Assigning Individual Timing Requirements

Back-Annotating Assignments for a Project

Clearing Assignments for a Project

Converting an Obsolete Assignment Format

Copying a Resource Assignment

Defining a Logic Synthesis Style

Deleting an Assignment

Guidelines for Achieving Maximum Speed Performance

Guidelines for First-Time Project Fitting

Guidelines for Timing Assignments

Guidelines for Working with Assignments

Ignoring Project Assignments during Compilation

Logic Synthesis Style & Logic Option Rules

Renaming a Chip

Searching the Node Database

Specifying Devices for Automatic Device Selection

Specifying Global Project Classic & MAX Device Options

Specifying Global Project FLEX 10K Device & Pin Options

Specifying Global Project FLEX 8000 Device & Pin Options

Specifying Global Project Logic Synthesis Settings

Specifying Global Project Parameters

Specifying Global Project Timing Requirements

Specifying Individual Classic & MAX Device Options

Specifying Individual FLEX 10K Device & Pin Options

Specifying Individual FLEX 8000 Device & Pin Options

Breakpoints

Changing a Breakpoint

Creating a Breakpoint

Deleting a Breakpoint

Checking Simulator Outputs vs. Other Outputs

Changing the Hardware Setup

Checking Simulation Outputs vs. User-Specified Outputs

Inserting a Device into the Socket

Testing Device Outputs vs. Simulation Outputs

Detecting Timing Problems

Defining & Detecting Glitches

Defining & Detecting Oscillation

Detecting Setup & Hold Violations

File Management

Comparing Files or Simulation Outputs

Creating a New File

Opening a File

Hierarchy

Navigating the Hierarchy

Updating the Hierarchy

Input & Output Files

Creating a Table File

Executing a Command File

Logging Simulation Commands

Recording Simulation Commands & Output History

Restoring Node & Group Initialization Values

Saving Actual Device Outputs

Saving Node & Group Initialization Values

Specifying the Source of Input Vectors

MAX+PLUS II Management

Changing Colors in MAX+PLUS II

Closing a MAX+PLUS II Application

Creating & Using a Local Copy of the maxplus2.ini File

Entering an Authorization Code

Exiting from MAX+PLUS II

Specifying a User Library

Starting MAX+PLUS II Applications

Switching Between MAX+PLUS II Applications

Messages

Getting Help on a Message

Locating the Source of a Message

Nodes, Groups & Memories

Exporting Memory Values

Importing Memory Values

Initializing Node & Group Values

Initializing RAM or ROM

Listing Node & Group Values

Resetting Node, Group & Memory Values to Initial SNF Values

Restoring Node, Group & Memory Values

Saving Node, Group & Memory Values

Project Management

Archiving a Project

Changing the Project Name

Combining Multiple Projects for Simulation

Compiling a Project

Running the Simulator

Running a Batch-Mode Simulation

Running an Interactive-Mode Simulation

Starting, Pausing & Stopping the Simulator

Status Bar & Toolbar

Showing the Status Bar

Showing the Toolbar

Text

Selecting Text


Changing a Breakpoint (Simulator)
Changing a Breakpoint

To change an existing breakpoint:

1.	Choose Breakpoint (Options menu). The Breakpoint dialog box is displayed.

2.	Choose a breakpoint name from the Existing Breakpoints box. The Breakpoint Name box and the Conditions list box show the current breakpoint name and its associated conditions.

3.	Change the selected breakpoint in one or more of the following ways:

Choose Disable to make the breakpoint inactive.

Choose Enable to reactivate a disabled breakpoint.

Select an existing condition from the Conditions list box and choose Delete Condition to delete it.

Create a new condition by entering information under Node/Group, Operator, Value, and Radix and choosing Add Condition. If you first select an existing condition from the Conditions list box, its Node/Group, Operator, Value, and Radix information can be copied for the new condition.

4.	Choose Change to record the changes and add them to the Existing Breakpoints box.

5.	If you wish to change additional breakpoints, repeat steps 2 through 4.

6.	Choose OK to save all changes.

The Existing Breakpoints box shows all existing breakpoints and breakpoint conditions for the current project. An asterisk (*) appears before the name of a breakpoint in the Existing Breakpoints box to indicate that the breakpoint is enabled; disabled breakpoints are denoted by the lack of an initial asterisk.

When the Simulator evaluates a breakpoint, it tests each condition by comparing the specified Value to the Node/Group with the Operator. When the breakpoint conditions are fulfilled during simulation, the Simulator pauses and reports the time in a message box and in the Message Processor window. At the pause, you can choose Start to resume simulation or Stop to end it.

See also:

Creating a Breakpoint


Creating a Breakpoint (Simulator)
Creating a Breakpoint

Breakpoints are advanced simulation controls that consist of one or more node value, group value, and time conditions. When these conditions are met, the Simulator pauses and reports that the breakpoint has been hit.

To create a breakpoint:

1.	Choose Breakpoint (Options menu). The Breakpoint dialog box is displayed.

2.	Type a name in the Breakpoint Name box. The breakpoint name can contain up to 32 name characters.

3.	To list all possible hierarchical node names for each node or group displayed in the Node/Group list box, turn on Show all Node Name Synonyms . Synonyms are preceded by -> in the list.

4.	Select a node name, group name, or .TIME variable from the Node/Group drop-down list box. You can type a string of text to bring a name that matches it to the top of the list.

5.	Select a breakpoint operator from the Operator drop-down list box or type an operator. The default is >-> ("changes to").

6.	Type a time value or logic level in the Value box. If you enter a time, it should be followed immediately (i.e., with no space in between) by a time unit; the default unit is ns.

7.	If necessary, change the radix that will be used to interpret the logic level for a group by selecting a Radix option. The default radix is HEX.

8.	Choose Add Condition to add the condition to the Conditions list box.

9.	If you wish to enter additional breakpoint conditions, repeat steps 4 through 8.

10.	Choose Add to add the breakpoint name and its associated conditions list to the Existing Breakpoints box.

11.	If you wish to create additional breakpoints, repeat steps 2 through 10.

12.	Choose OK to save all changes.

The Existing Breakpoints box shows all existing breakpoints and breakpoint conditions for the current project. An asterisk (*) appears before the name of a breakpoint in the Existing Breakpoints box to indicate that the breakpoint is enabled.

When the Simulator evaluates a breakpoint, it tests each condition by comparing the specified Value to the Node/Group with the Operator. When the breakpoint conditions are fulfilled during simulation, the Simulator pauses and reports the time in a message box and in the Message Processor window. At the pause, you can choose Start to resume simulation or Stop to end it.

See also:

Changing a Breakpoint


Deleting a Breakpoint (Simulator)
Deleting a Breakpoint

You can delete a breakpoint when you have finished using it, or disable a breakpoint so that it is inactive.

To delete or disable a breakpoint:

1.	Choose Breakpoint (Options menu). The Breakpoint dialog box is displayed.

2.	Choose one or more breakpoint names from the Existing Breakpoints box.

3.	Choose Delete to delete the breakpoint(s) and all of the associated conditions or choose Disable to make the selected breakpoint(s) inactive.

4.	Choose OK to save all changes.

The Existing Breakpoints box shows all existing breakpoints and breakpoint conditions for the current project. An asterisk (*) appears before the name of a breakpoint in the Existing Breakpoints box to indicate that the breakpoint is enabled; disabled breakpoints are denoted by the lack of an initial asterisk.

See also:

Changing a Breakpoint

Creating a Breakpoint


Checking Simulation Outputs vs. User-Specified Outputs (Simulator)
Checking Simulation Outputs vs. User-Specified Outputs

The Simulator allows you to check the outputs of simulation against any outputs that are present in the Simulator Channel File or Vector File that contains the inputs for simulation. This file can contain any outputs you wish: your own expected outputs, outputs of a previous simulation, or actual device outputs.

To check simulation outputs against other outputs:

1.	Create a Vector File or SCF that contains outputs for the entire period to be simulated.

2.	If necessary, specify a non-default source of input vectors by choosing Inputs/Outputs (File menu) or by double-clicking Button 1 on the Simulation Input Field. Otherwise, the Simulator automatically loads the newest Vector File or SCF with the same filename as the project.

3.	Turn on the Check Outputs option.

4.	Ensure that the Use Device option is turned off.

5.	Choose Start to run the simulation.

A Message Processor window opens automatically to report any differences between the two sets of outputs. Outputs are always compared according to functional comparison rules, regardless of whether the Simulator is in the functional simulation, timing simulation, or linked simulation mode.

You can view and analyze the results during simulation, when the simulation is paused, or after simulation with the following procedure:

1.	Choose the Open SCF button.

or:

Choose Open (File menu) and open the SCF specified in step 2 above (or the SCF generated automatically for a Vector File). The Waveform Editor automatically executes its Compare command (File menu) and superimposes the simulation outputs on the SCF outputs. The Compare command is also executed automatically if the SCF is left open during simulation.

2.	When you have finished comparing the simulation and SCF outputs, choose Compare in the Waveform Editor to turn off the compare mode.

or:

1.	From the Message Processor window, select a message that reports the differences between simulation outputs and SCF outputs, then choose Locate. MAX+PLUS II automatically opens the Waveform Editor window and highlights the portion of the SCF where the differences occur.

2.	If necessary, choose Locate again one or more times to find the location(s) in the project’s design files where the problem occurs. Multiple locations are possible.

The Simulator assumes X (undefined) logic levels for outputs that are not provided in a Vector File, and does not check simulation outputs against them. To ensure meaningful simulation results, you can open the SCF that is automatically generated for a Vector File, and examine it to check whether 0, 1, and Z (but not X) expected output waveforms exist for the period you wish to simulate.

See also:

Comparing Files or Simulation Outputs

Locating the Source of a Message

Saving Actual Device Outputs

Testing Device Outputs vs. Simulation Outputs

Vector File Format


Testing Device Outputs vs. Simulation Outputs

The MAX+PLUS II Simulator and Programmer both allow you to perform functional testing, in which the outputs of a programmed or configured device are tested against the simulation outputs in the current Simulator Channel File or Vector File. In the Programmer only, you can also perform functional testing with simulation vectors and outputs that have been stored in the programming file.

1.	You can only test devices for single-device projects. Since an SCF or Vector File is for an entire project, it cannot be compared with the actual device outputs of a device that is only part of a multi-device project. You also cannot test projects that contain bidirectional buses.

2.	Functional testing is not available for FLEX 8000 devices. However, you can configure devices in-system for prototyping purposes, as described in Configuring a FLEX 8000 Device with the FLEX Download Cable and Configuring a FLEX 8000 Device with the BitBlaster.

To test device outputs against simulation outputs in the Simulator:

1.	Program a device.

2.	Create a Vector File or SCF that contains input vectors and the names of output nodes and groups to be tested for the project.

3.	Specify a non-default source of input vectors with Inputs/Outputs (File menu), as described in Specifying the Source of Input Vectors. Otherwise, the Simulator automatically loads the newest Vector File or SCF with the same filename as the project. If a Vector File is the source of input vectors, the Simulator automatically converts it into an SCF.

4.	Choose Start to run the Simulator and overwrite the outputs in the SCF with simulation outputs.

5.	If necessary, change the time in the Start Time field to 0.

6.	Turn on the Use Device option.

7.	Turn on the Check Outputs option.

8.	Insert the programmed device into the programming socket.

9.	Choose Start.

The Simulator applies the input vectors to the device and compares the SCF outputs to the actual device outputs. Outputs are always compared according to functional comparison rules, regardless of whether the Simulator is in the functional simulation mode or the timing simulation mode. A Message Processor window opens automatically to report all cases in which the outputs are not functionally equivalent.

To test device outputs against simulation outputs in the Programmer:

1.	Simulate the project in interactive or batch mode.

2.	Open the Programmer window.

3.	If necessary, specify the name of the file that contains the outputs of simulation using the Programmer’s Inputs/Outputs command (File menu). The Programmer automatically loads the newest Vector File or SCF with the same filename as the project or the vectors stored in the current programming file, if any. If a Vector File or a programming file is the source of input vectors, the Programmer automatically converts it into a temporary data buffer with the same format as an SCF.

4.	Turn on Auto-Testing.

5.	Program the device. Each device programmed when Auto-Testing is turned on is automatically tested with the input vectors in the current SCF, Vector File, or programming file.

or:

1.	Repeat steps 1 through 3 immediately above.

2.	Insert a programmed device into the programming socket or program a device.

3.	Choose the Test button.

The Programmer applies the input vectors to the device and compares the simulation outputs in the SCF, Vector File, or programming file to the actual device outputs. Outputs are compared according to functional comparison rules. If the Programmer finds outputs that are not functionally equivalent, it stops. A Message Processor window then opens automatically to report the error.

See also:

Checking Simulation Outputs vs. User-Specified Outputs

Comparing Files or Simulation Outputs

Functional Testing with the SCF, Vector File, or Programming File

Inserting a Device into the Socket

Output Monitoring Requirements for the SCF or Vector File

Programming a Device

Propagation of Undefined Logic Levels

Saving Programming Data to a File

Selecting a Programming File (Programmer)

Specifying the Source of Input Vectors (Programmer)

Specifying the Source of Input Vectors (Simulator)

Recommended reading:

AB87 (Troubleshooting Functional Problems in EPLDs)

AB92 (Simulating Internal Nodes with MAX+PLUS II Software)


Functional Testing with the SCF, Vector File, or Programming File

If you choose Test in the Programmer, if the Programmer’s Auto-Testing command is turned on during programming, or if both of the Simulator’s Check Outputs and Use Device options are turned on, actual device outputs are functionally tested against the SCF or Vector File outputs. In the Programmer, vectors that have been saved in the programming file can also be used for functional testing.

An SCF, Vector File, or programming file that is used for functional testing must contain all input vector logic levels, and expected output logic levels that are typically derived from a simulation or from a previously tested device. In addition, the file must conform to the following rules:

Inputs:

Only low, high, and high-impedance (0, 1, and Z) input logic levels are permitted. Undefined (X) logic levels cannot be applied to a device.

All inputs in the file must also be listed in the Fit File for the project.

All input pins that are in the Fit File but not in the SCF, Vector File, or programming file are assigned a low (0) logic level.

All input pins on the device that are not used in the project are assigned a low (0) logic level.

You must use pin names rather than probe or buried node names for all nodes in the file.

Outputs:

All I/O pins that are in the Fit File but not in the SCF, Vector File, or programming file are assigned a high-impedance (Z) logic level.

All I/O pins on the device that are not used in the project are assigned a high-impedance (Z) logic level.

All buried nodes and outputs in the SCF, Vector File, or programming file that are not listed in the Fit File are assigned an undefined (X) logic level as soon as testing begins.

You must use node names rather than probe names for all nodes in the file.

During functional testing, outputs are compared according to functional comparison rules.

If a project is partitioned into multiple devices, functional testing is not available.

See also:

Probe Assignments Section (Report File)

Saving Programming Data to a File

Specifying the Source of Input Vectors (Programmer)

Specifying the Source of Input Vectors (Simulator)


Defining & Detecting Glitches (Simulator)
Defining & Detecting Glitches

The Simulator lets you monitor your project for glitches during any part of the simulation. In functional simulation mode, the Simulator detects nil-time glitches; in timing simulation mode and linked simulation mode, you can specify the period of time that defines a glitch.

To monitor the project for glitches:

1.	Turn on the Glitch option. You can turn the option on or off at any time, regardless of whether or not a simulation is running.

2.	(Timing and linked simulation modes only) Type a glitch time in the text field for the Glitch option. The time you enter should be followed immediately (i.e., with no space in between) by a time unit; the default unit is ns.

3.	If necessary, choose Start to start or restart the simulation. A Message Processor window opens automatically to report multiple logic level changes that occur on a single node over a period less than or equal to the specified glitch time. In functional simulation mode, the glitch time is always nil.

4.	Select a message in the Message Processor window that reports a glitch, then choose Locate. MAX+PLUS II automatically opens the SCF and highlights the portion of the input vectors where the glitch occurred. (If a Vector File was the source of input vectors, an SCF is generated automatically from it.) You can locate the errors as the simulation proceeds or after it has finished.

5.	If necessary, choose Locate again one or more times to find the location(s) in the project’s design files that caused the glitch. MAX+PLUS II always locates the glitch in the SCF or Vector File before it locates the corresponding logic in the project’s design files.

See also:

Locating the Source of a Message

Running an Interactive-Mode Simulation

Starting, Pausing & Stopping the Simulator


Defining & Detecting Oscillation (Simulator)
Defining & Detecting Oscillation

The Simulator allows you to monitor your project for oscillation during any part of the simulation. In functional simulation mode, oscillation detection is always turned on and the Simulator detects only nil-period oscillation. In timing simulation mode, you can turn oscillation monitoring on and off, regardless of whether the Simulator is running, and specify the period of time that defines oscillation. In linked simulation mode, the Simulator checks for both user-defined and nil-period oscillation.

To monitor the project for oscillation:

1.	(Timing and linked simulation modes only) Turn on the Oscillation option. In timing simulation mode, you can turn the option on or off at any time, regardless of whether or not a simulation is running. In functional simulation mode, this option is always turned on.

2.	(Timing and linked simulation modes only) Type an oscillation time in the text field for the Oscillation option. The time you enter should be followed immediately (i.e., with no space in between) by a time unit; the default is ns.

3.	If necessary, choose Start to start or restart the simulation. A Message Processor window opens automatically to report any node or group logic level that does not stabilize within the specified oscillation time after each input vector has been applied. (In functional simulation mode, the oscillation time is always nil.) The circuit is considered to have stabilized if all node and group logic levels have stopped changing before new input vectors become available.

4.	Select a message in the Message Processor window that reports oscillation, then choose Locate. MAX+PLUS II automatically opens the SCF and highlights the portion of the input vectors where the oscillation occurred. (If a Vector File was the source of input vectors, an SCF is generated automatically from it.) You can locate the errors as the simulation proceeds or after it has finished.

5.	If necessary, choose Locate again one or more times to find the location(s) in the project’s design files that caused the oscillation. MAX+PLUS II always locates the oscillation in the SCF or Vector File before it locates the corresponding logic in the project’s design files.

See also:

Locating the Source of a Message

Running an Interactive-Mode Simulation

Starting, Pausing & Stopping the Simulator


Detecting Setup & Hold Violations (Simulator)
Detecting Setup & Hold Violations

The Simulator allows you to monitor your project to determine whether setup and hold time requirements are being met during any part of the simulation.

To monitor the project for setup and hold violations:

1.	Turn on the Setup/Hold option. You can turn the option on or off at any time, regardless of whether or not a simulation is running.

2.	If necessary, choose Start to start or restart the simulation. A Message Processor window opens automatically to report any setup or hold time violations that have occurred.

3.	Select a message in the Message Processor window that reports a setup or hold time violation, then choose Locate. MAX+PLUS II automatically opens the SCF and highlights the portion of the file where the setup or hold time violation occurred. (If a Vector File was the source of input vectors, an SCF is generated automatically from it.) You can locate the errors as the simulation proceeds or after it has finished.

4.	If necessary, choose Locate again one or more times to find the location(s) in the project’s design files that caused the setup or hold time violation. MAX+PLUS II always locates the setup/hold time violations in the SCF or Vector File before it locates the corresponding logic in the project’s design files.

See also:

Locating the Source of a Message

Running an Interactive-Mode Simulation

Starting, Pausing & Stopping the Simulator


Comparing Files or Simulation Outputs

You can superimpose a WDF, SCF, or the outputs of simulation on the current file to compare them. The Waveform Editor uses color and special "compared" waveforms to highlight the differences between the two sets of data. Example

The value of each node or group in the compared file or data is also displayed in parentheses, next to the node or group value in the current file, in the Value field.

To compare a file to the current file:

1.	Choose Compare (File menu) in the Waveform Editor. The Compare dialog box is displayed.

2.	If necessary, select a different extension from the drop-down list box. You can compare an SCF to a WDF or vice versa.

3.	Type a name in the File Name box or select a name in the Files box.

4.	Choose OK.

5.	When you have finished comparing the two files, choose Compare again to turn off the compare mode.

To compare simulation outputs to the current file:

1.	Turn on the Check Outputs option in the Simulator.

2.	Ensure that the Use Device option is turned off.

3.	Simulate the project.

4.	Choose the Open SCF button or choose the Open command (File menu) to open the SCF specified as the source of input vectors for simulation. If you use a Vector File as the source of input vectors instead, the Simulator automatically generates an SCF with the same filename from it. The Waveform Editor automatically enters its Compare command mode, superimposing the simulation outputs on the outputs in the SCF. The Compare command is also automatically executed if the SCF is left open during simulation.

5.	When you have finished comparing the SCF to the simulation outputs, choose Compare to turn off the compare mode.

or:

Open the SCF as described in step 3 immediately above and then follow steps 1, 2, and 4.

See also:

Checking Simulation Outputs vs. User-Specified Outputs

Functional Testing with the SCF, Vector File, or Programming File

Opening a File

Output Monitoring Requirements for the SCF or Vector File

Propagation of Undefined Logic Levels

Running an Interactive-Mode Simulation

Testing Device Outputs vs. Simulation Outputs

Recommended reading:

AB92 (Simulating Internal Nodes with MAX+PLUS II Software)


Creating a Table File (Simulator)
Creating a Table File

The Simulator allows you to create an ASCII-format Table File that records all logic level transitions for nodes and groups in the current SCF.

You can create a Table File at any time before or after simulation, or when the simulation has been temporarily halted with the Pause button.

To create a Table File:

1.	Choose Create Table File (File menu). The Create Table File dialog box is displayed.

2.	If necessary, select a different drive and/or directory.

3.	Select an existing filename in the Files box or type a filename in the File Name box. The filename can contain up to 32 name characters. The default filename displayed in the File Name box is <project name>.tbl. If you type or select the name of an existing file, it will be overwritten. If you type the name of a directory that does not exist, MAX+PLUS II will offer to create it for you.

4.	Type a filename extension or type a period (.) after the filename to create a file without any extension. Otherwise, the extension .tbl is automatically appended to the filename.

5.	Choose OK.

See also:

TABLE (Command File)


Executing a Command File (Simulator)
Executing a Command File

You can run the Simulator in batch mode with a Command File that contains commands that perform the same functions as the menu commands and on-screen options and buttons.

To execute a Command File:

1.	Choose Execute Command File (File menu). The Execute Command File dialog box is displayed.

2.	If necessary, select a different drive and/or directory.

3.	Select an existing filename in the Files box or type a filename in the File Name box.

4.	Type a filename extension or type a period (.) after the filename to specify a file without any extension. Otherwise, the extension .cmd is automatically appended to the filename.

5.	Choose OK to immediately execute the commands in the file.

See also:

Command File Format

Running a Batch-Mode Simulation


Logging Simulation Commands (Simulator)
Logging Simulation Commands

You can record the Simulator menu commands, options, and buttons that are used during an interactive-mode simulation session in an ASCII-format Log File.

You can begin command logging before you start simulation with the Start button, or when you have halted simulation temporarily with the Pause button.

To log simulation commands:

1.	Choose Inputs/Outputs (File menu) or double-click Button 1 on the Simulation Input Field. The Inputs/Outputs dialog box is displayed.

2.	Turn on the Log (.log) option under Output Files. The text field for the option is then selected, and the Files box shows all files in the current directory with the extension .log. The default filename displayed in the Log (.log) text field is <project name>.log.

3.	If necessary, select a different drive and/or directory.

4.	If you wish to log simulation commands to a non-default filename, select an existing filename in the Files box or type a filename in the text box for the Log (.log) option. The filename can contain up to 32 name characters.

5.	Type a filename extension, or type a period (.) after the filename to specify a file without any extension. Otherwise, the extension .log is appended automatically to the filename.

6.	Turn on the New option that follows the text box for the Log (.log) option to overwrite any existing file with the same name. Otherwise, the logged commands are appended to the existing file.

7.	Choose OK to begin command logging.

See also:

Recording Simulation Commands & Output History


Recording Simulation Commands & Output History (Simulator)
Recording Simulation Commands & Output History

You can record the Simulator menu commands, options, and buttons that are used during a simulation session, as well as command output and error messages reported in the Message Processor window in an ASCII-format History File.

You can begin command and output history recording before you start simulation with the Start button, or when you have halted simulation temporarily with the Pause button.

To record simulation commands and output history:

1.	Choose Inputs/Outputs (File menu) or double-click Button 1 on the Simulation Input Field. The Inputs/Outputs dialog box is displayed.

2.	Turn on the History (.hst) option under Output Files. The text field for the option is then selected, and the Files box shows all files in the current directory with the extension .hst. The default filename displayed in the History (.hst) text field is <project name>.hst.

3.	If necessary, select a different drive and/or directory.

4.	If you wish to record simulation commands and history to a non-default filename, select an existing filename in the Files box or type a filename in the text box for the History (.hst) option. The filename can contain up to 32 name characters.

5.	Type a filename extension, or type a period (.) after the filename to specify a file without any extension. Otherwise, the extension .hst is appended automatically to the filename.

6.	Turn on the New option that follows the text box for the History (.hst) option to overwrite any existing file with the same name. Otherwise, the commands and output history are appended to the existing file.

7.	Choose OK to begin command and output history recording.

See also:

Logging Simulation Commands


Restoring Node & Group Initialization Values (Simulator)
Restoring Node & Group Initialization Values

The Simulator allows you to restore initialized node and group values that have been saved in a Simulator Initialization File. The SIF allows you to restore initialization values for a project that have been specified in an earlier simulation session.

To restore initialized node and group values:

1.	Choose Restore Initialization (Initialize menu). The Restore Initialization dialog box is displayed.

2.	If necessary, select a different drive and/or directory.

3.	Select an existing filename in the Files box or type a filename in the File Name box. If you do not specify a filename extension, the extension .sif is appended automatically to the filename.

4.	Choose OK to return to the Initialize Nodes/Groups dialog box, which now displays the restored values.

5.	Choose OK in the Initialize Nodes/Groups dialog box to retain the restored values. If you choose Cancel, all changes made in the Initialize Nodes/Groups and the Restore Initialization dialog boxes are canceled.

See also:

Initializing Node & Group Values

Listing Node & Group Values

Saving Node & Group Initialization Values


Saving Actual Device Outputs (Simulator)
Saving Actual Device Outputs

The Simulator allows you to apply vector inputs to a programmed device and save actual device outputs, rather than simulation outputs, to the current SCF. Actual device outputs can be saved only if the project fits into a single device.

To save actual device outputs:

1.	Create a Vector File or SCF that contains input vectors and the names of output nodes and groups to be simulated.

2.	If necessary, specify the source of input vectors as described in Specifying the Source of Input Vectors. The Simulator automatically loads the newest Vector File or SCF with the same filename as the project. If a Vector File is the source of input vectors, the Simulator automatically converts it into an SCF.

3.	Turn on the Use Device option.

4.	Ensure that the Check Outputs option is turned off.

5.	Insert the programmed device into the programming socket of the MPU.

6.	Choose Start.

The Simulator applies the input vectors to the device and saves actual device outputs in the SCF.

See also:

Checking Simulation Outputs vs. User-Specified Outputs

Functional Testing with the SCF, Vector File, or Programming File

Inserting a Device into the Socket

Running an Interactive-Mode Simulation

Testing Device Outputs vs. Simulation Outputs


Saving Node & Group Initialization Values (Simulator)
Saving Node & Group Initialization Values

The Simulator allows you to save initialized node and group values specified with the Initialize Nodes/Groups command to a Simulator Initialization File, which can be reused for a future simulation.

To save initialized node and group values:

1.	Choose Initialize Nodes/Groups (Initialize menu). The Initialize Nodes/Groups dialog box is displayed.

2.	If you wish to list all possible hierarchical node names for each node or group displayed in the Nodes & Group list box, turn on Show all Node Name Synonyms. Synonyms are preceded by -> in the list.

3.	Specify initialization values for one or more nodes and groups, as described in Initializing Node & Group Values.

4.	Choose Save. The Save Initialization As dialog box is displayed.

5.	If necessary, select a different drive and/or directory.

6.	Select an existing filename in the Files box or type a filename in the File Name box. The filename can contain up to 32 name characters. If you do not include a filename extension, the extension .sif is automatically appended to the filename. The default filename displayed in the File Name box is <project name>.sif.

7.	Choose OK to return to the Initialize Nodes/Groups dialog box and save the SIF.

8.	If necessary, initialize additional node and group values.

9.	Choose OK. If you choose Cancel, all changes made in the Initialize Nodes/Groups dialog box (but not changes saved in the Save Initialization As dialog box) are canceled.

See also:

Restoring Node & Group Initialization Values


Specifying the Source of Input Vectors (Simulator)
Specifying the Source of Input Vectors

The Simulator requires you to specify the source of input vectors that will drive the simulation. The name of the source file is displayed in the Simulation Input field. You can create input vectors in a Simulator Channel File created with the Waveform Editor or in an ASCII Vector File.

You specify the source of input vectors before starting simulation. If no file has been specified for the project, the Simulator automatically loads the newest Vector File or SCF with the same filename as the project. Therefore, you need to specify the file explicitly only if it has a different name. You can also specify a new Vector File or SCF after simulation has stopped. You cannot specify a different file when the Simulator is paused.

To specify the source of input vectors:

1.	Choose Inputs/Outputs (File menu) or double-click Button 1 on the Simulation Input field. The Inputs/Outputs dialog box is displayed.

2.	To display all files with the extension .vec in the current directory in the Files box, type *.vec in the Input (.scf or .vec)  text field under Vector Files and choose OK. Otherwise, the Files box shows all files in the current directory with the extension .scf.

3.	If necessary, select a different drive and/or directory.

4.	If you wish to use a non-default source of input vectors, select an existing filename in the Files box or type a filename in the Input (.scf or .vec) box.

5.	If you typed a filename in step 4, type a filename extension. Otherwise, the extension .scf is automatically appended to the filename.

6.	Choose OK.

If you specify a Vector File as the source of input vectors, the Simulator automatically converts it into an SCF with the same filename. If an SCF with this name already exists, it is overwritten.

The name of the SCF where the Simulator records simulation outputs is displayed in the Output field under Vector Files in the Inputs/Outputs dialog box.

See also:

Functional Testing with the SCF, Vector File, or Programming File

Initializing Node & Group Values

Output Monitoring Requirements for the SCF or Vector File

Running an Interactive-Mode Simulation

Simulating Bidirectional Pins


Output Monitoring Requirements for the SCF or Vector File (Simulator)
Output Monitoring Requirements for the SCF or Vector File

When you use the Check Outputs option to check Simulator Channel File outputs against simulation outputs, you should define the 0, 1, and Z expected output logic levels in the SCF for all input logic levels in each time period that you simulate. When an SCF output has an undefined (X) logic level, the Simulator ignores it and therefore does not compare it to the simulated outputs. The same conditions apply to a Vector File that is used instead of an SCF.

In addition, if a Vector File is the source of input vectors, but does not contain expected (i.e., user-defined) output logic levels for each time period to be simulated, the Simulator automatically supplies X logic levels for the missing outputs. To ensure meaningful simulation results, you can open the SCF that is automatically generated for the Vector File, and examine it to check whether 0, 1, and Z (and not X) output logic levels exist for the period you wish to simulate.

See also:

Specifying the Source of Input Vectors (Simulator)


Simulating Bidirectional Pins (Simulator)
Simulating Bidirectional Pins

If you wish to simulate a project that uses bidirectional I/O pins, three additional steps are required to specify simulation vectors:

1.	Create two versions of the node in the SCF or Vector File, one with an I/O type of input and one with an I/O type of output. (In a Vector File, you must list the node in both the Inputs and Outputs Sections.)

2.	Set the input that drives the Output Enable of the TRI buffer to low (0) when the I/O pin is used for input and to high (1) when the I/O pin is used for output.

3.	When specifying input vector logic levels, use high impedance (Z) when the I/O pin is driving out.

Example

See also:

Functional Testing with the SCF, Vector File, or Programming File

Specifying the Source of Input Vectors (Simulator)


Example: Vector Pattern for Simulating Bidirectional Pins (Simulator)
Sample Vector Pattern for Simulating Bidirectional Pins

The following sample Vector File excerpt shows the vector patterns for a project with an Output Enable input pin OEPIN  and bidirectional pin IOPIN:

INPUTS OEPIN IOPIN ;

OUTPUTS IOPIN;

.

.

.

PATTERN

% Z's when pin is driving out %

       1      Z

       1      Z

       1      Z

       1      Z

       0      Z   % pin floats %

       0      0

       0      1

       0      0

       0      1

       0      Z   % pin floats %

       1      Z

       1      Z

       1      Z

       1      Z ;


Exporting Memory Initialization Values (Simulator)
Exporting Memory Initialization Values

The Simulator allows you to save the data in the Initialize Memory dialog box to a Hexadecimal File (.hex) or Memory Initialization File (.mif) for future use.

To export memory data to an MIF or Hex File:

1.	Choose Initialize Memory (Initialize menu). The Initialize Memory dialog box is displayed.

2.	Specify the the initial content of a memory block (i.e., the initial values for each address) as described in Initializing RAM or ROM.

3.	Choose the Export File button to open the Export Memory Content File dialog box. The Export Memory Content File dialog box is displayed.

4.	If necessary, select a different drive and/or directory.

5.	Select an existing filename in the Files box or type a filename in the File Name box. The filename can contain up to 32 name characters. The default filename displayed in the File Name box is <project name>.mif. If you type or select the name of an existing file, it will be overwritten. If you type the name of a directory that does not exist, MAX+PLUS II will offer to create it for you.

Do not save a Hex File as <project name>.hex or <chip name>.hex. the Compiler automatically generates Hex Files for FLEX 8000 and FLEX 10K device configuration, and filenames of this format will be overwritten.

6.	Type a filename extension, select a different extension (e.g., .hex) from the Automatic Extension drop-down list box, or type a period (.) after the filename to create a file without any extension. Otherwise, the extension .mif is automatically appended to the filename.

7.	Choose OK.

The data in the exported file applies only to the memory displayed in the Memory field; if the project contains more than one memory, separate files are required to initialize each memory.

You can import (i.e., load) data saved in Hexadecimal File or MIF format using the Import Memory Content File dialog box.

See also:

Importing Memory Values


Importing Memory Initialization Values (Simulator)
Importing Memory Initialization Values

The Simulator allows you to load the memory initialization data for a memory block that is saved in a Hexadecimal File (.hex) or Memory Initialization File (.mif) as an input for simulation.

To import memory data from an MIF or Hex File:

1.	Choose Initialize Memory (Initialize menu). The Initialize Memory dialog box is displayed.

2.	Choose the Import File button to open the Import Memory Content File dialog box. The Import Memory Content File dialog box is displayed.

3.	If necessary, select a different drive and/or directory.

4.	Select an existing filename in the Files box or type a filename in the File Name box. If you do not specify a filename extension, the extension .mif is automatically appended to the filename.

5.	Choose OK to return to the Initialize Memory dialog box, which now displays the initial memory values stored in the imported MIF or Hex File.

6.	Choose OK in the Initialize Memory dialog box to retain the imported values so that they will be used during simulation. If you choose Cancel, all changes made in the Initialize Memory and Import Memory Content File dialog boxes are canceled.

The data in the imported file applies only to the memory block displayed in the Memory field; if the project contains more than one memory, separate files are required to initialize each memory.

You can export (i.e., save) the data in the Initialize Memory dialog box using the Export Memory Content File dialog box. In addition, when you create a Simulator Initialization File (.sif), the memory initialization data, as well as initial values for all other nodes and groups in the project, is saved.

See also:

Exporting Memory Values

Initializing RAM or ROM


Initializing Node & Group Values (Simulator)
Initializing Node & Group Values

The Simulator allows you to specify initial values for nodes and groups (including groups that represent state machines) in the Simulator Netlist File for the project. By default, all registered outputs are initialized to 0 and pin inputs are initialized to the first vector value provided in the current SCF. Initialization is typically used to set the values of registered outputs or combinatorial logic outputs to non-default values.

To specify initialization values for a memory block, you must use the Initialize Memory command (Initialize menu) and follow the steps in Initializing RAM or ROM.

To initialize node and group values:

1.	Specify the source of input vectors for simulation, as described in Specifying the Source of Input Vectors.

2.	Choose Initialize Nodes/Groups (Initialize menu). The Initialize Nodes/Groups dialog box is displayed.

3.	Type a node name, group name, or a text string that contains wildcard characters in the Node/Group box. The default * wildcard character matches all names.

4.	If you wish to specify the type of nodes and/or groups to be initialized, turn on one or more options under Type. The default option is All.

5.	If you wish to list all possible hierarchical node names for each node or group displayed in the Node/Group list box, turn on Show All Node Name Synonyms. Synonyms are preceded by -> in the list.

6.	Choose List to list all nodes and groups that match the names and types you have specified in the Nodes & Groups box.

7.	Select one or more node and/or group names in the Nodes & Groups box.

8.	If necessary, change the radix that will be used to interpret the initial value for any groups you have selected in step 7 by selecting an option under Radix. The default is HEX.

9.	Type the desired initial logic level or a state name for the selected nodes and/or groups in the Value box.

10.	Choose the Initialize button. The new initial values for the nodes and/or groups are shown next to the names in the Nodes & Groups box.

11.	If you wish to initialize additional nodes and groups, repeat steps 3 through 10.

12.	Choose OK to save the changes.

See also:

Restoring Node & Group Initialization Values

Saving Node & Group Initialization Values


Initializing RAM or ROM (Simulator)
Initializing RAM or ROM

The Simulator allows you to specify the initial content of a RAM or ROM memory block, i.e., the initial values for each address. You can enter and edit values or import saved initialized values from a Memory Initialization File (.mif) or Hexadecimal File (.hex) to initialize your memory block.

To initialize memory values:

1.	Create one or more memory blocks in your project’s design file(s), e.g., with LPM functions, and compile the project to create an SNF.

2.	Choose Initialize Memory (Initialize menu). The Initialize Memory dialog box is displayed. The Memory Info box displays a  brief description of the memory name shown in the Memory box.

3.	If you wish to edit a different memory, select a different memory name from the Memory drop-down list box or type a hierarchical name.

4.	If you wish to import previously saved initialized values, choose the Import File button to open the Import Memory Content File dialog box. Follow the steps in Importing Memory Values.

5.	If you wish, specify BIN (binary), DEC (decimal), HEX (hexadecimal), or OCT (octal) radix in the Addr Radix box to designate the radix used to display the memory addresses in the Address box, and in the Value Radix box to designate the radix used to display and interpret the memory values in the Value box.

6.	If you wish to view each address and its corresponding values on a separate line, turn on the List One Address Per Line option.

7.	To edit a single memory word, click Button 1 on a memory value in the Value box and enter a new value. You can also double-click with Button 1 or use the Tab or arrow keys to select another value. (To undo an edit, press Esc.)

or:

To edit multiple values simultaneously to low or high logic levels, use area selection to select a series of values and choose the Initialize to 0’s or Initialize to 1’s button.

 	In addition, you can edit both single and multiple values by cutting, copying, and pasting values using keyboard shortcuts (i.e., Ctrl+X, Ctrl+C, and Ctrl+V, respectively).

The values you enter are automatically updated, e.g., if you enter FF for a 6-bit wide RAM, the FF value is updated to 3F when the cursor is moved to another value.

8.	If you wish to continue editing additional memories, select a different memory name from the Memory drop-down list box or type a hierarchical name, then repeat steps 4 through 7.

9.	Choose OK.

During simulation, you can pause the Simulator and open the Initialize Memory dialog box to view the results of simulation.

You can view memory values in the Initialize Memory dialog box before or after simulation, or when you have temporarily halted simulation with the Pause button.

In addition, you can save the data in the Initialize Memory dialog box to a Hex File or MIF for future use in initializing RAM or ROM memory.

See also:

Exporting Memory Values

Resetting Node, Group & Memory Values to Initial SNF Values


Listing Node & Group Values (Simulator)
Listing Node & Group Values

The Simulator’s Initialize Nodes/Groups dialog box (Initialize menu) allows you to list the current logic levels for nodes and groups in the Simulator Netlist File and the Simulator Channel File for the project.

You can list node and group values before or after simulation, or when you have temporarily halted simulation with the Pause button.

To view initialization values for a memory block, you must use the Initialize Memory command (Initialize menu) and follow the steps in Initializing RAM or ROM.

To list node and group names and values:

1.	If you wish to record the node and group values in a History File, open the Inputs/Outputs dialog box by choosing Inputs/Outputs (File menu) or double-clicking Button 1 on the Simulation Input Field. You may then turn history recording on, as described in Recording Simulation Commands & Output History.

2.	Specify the source of input vectors for simulation, as described in Specifying the Source of Input Vectors.

3.	Simulate the project to any desired time.

4.	Choose Initialize Nodes/Groups (Initialize menu). The Initialize Nodes/Groups dialog box is displayed.

5.	Type a node name, group name, or a text string that contains wildcard characters in the Node/Group box. The default * wildcard character matches all names.

6.	If you wish to specify the type of nodes and/or groups to list, turn on one or more Type options . The default option is All.

7.	If necessary, change the radix that will be used to display group values by selecting an option under Radix.

8.	If you wish to list all possible hierarchical node names for each node or group displayed in the Node/Group list box, turn on Show all Node Name Synonyms. Synonyms are preceded by -> in the list.

9.	Choose List to list all node and group names that match the names and types specified in steps 5 and 6 in the Nodes & Groups box. Group values are shown in the specified Radix. A state name can also be shown for a group of state bits that represents a state machine created in the project’s design files.

10.	If you wish to list the names and values of additional nodes and groups, repeat steps 5 through 9.

11.	Choose OK or Cancel to close the dialog box.

The node and group values you have listed are recorded in the History File, regardless of whether you choose OK or Cancel in the Initialize Nodes/Groups dialog box.

See also:

Initializing Node & Group Values


Resetting Node, Group & Memory Values to Initial SNF Values (Simulator)
Resetting Node, Group & Memory Values to Initial SNF Values

The Simulator allows you to reset initial node, group, and memory (i.e., RAM and ROM) values to the values stored in the Simulator Netlist File.

To reset node, group, and memory values:

Choose Reset to Initial SNF Values (Initialize menu).

See also:

Initializing Node & Group Values

Initializing RAM or ROM

Restoring Node, Group & Memory Values

Saving Node, Group & Memory Values


Restoring Node, Group & Memory Values (Simulator)
Restoring Node, Group & Memory Values

The Simulator allows you to retrieve initialized node, group, and memory (i.e., RAM and ROM) values stored in a Simulator Initialization File.

To restore node, group, and memory values:

1.	Choose Restore Initialization (Initialize menu). The Restore Initialization dialog box is displayed.

2.	If necessary, select a different drive and/or directory.

3.	Select an existing filename in the Files box or type a filename in the File Name box. If you do not specify a filename extension, the extension .sif is automatically appended to the filename.

4.	Choose OK. The node, group, and  memory values in the Initialize Nodes/Groups and Initialize Memory dialog boxes are re-initialized to the values in the SIF.

See also:

Initializing Node & Group Values

Initializing RAM or ROM

Saving Node, Group & Memory Values


Saving Node, Group & Memory Values (Simulator)
Saving Node, Group & Memory Values

The Simulator allows you to save current initialized node and group logic levels and memory values entered in the Initialize Nodes/Groups and Initialize Memory dialog boxes to a Simulator Initialization File for future use.

To save node, group, and memory values:

1.	Choose Save Initialization As (Initialize menu). The Save Initialization As dialog box is displayed.

2.	If necessary, select a different drive and/or directory.

3.	Select an existing filename in the Files box or type a filename in the File Name box. The filename can contain up to 32 name characters. The default filename displayed in the File Name box is <project name>.sif. If you type or select the name of an existing file, it will be overwritten. If you type the name of a directory that does not exist, MAX+PLUS II will offer to create it for you.

4.	Type a filename extension, or type a period (.) after the filename to create a file without any extension. Otherwise, the extension .sif is automatically appended to the filename.

5.	Choose OK.

See also:

Initializing Node & Group Values

Initializing RAM or ROM

Restoring Node, Group & Memory Values


Running a Batch-Mode Simulation

The Simulator provides a batch mode for running a simulation with commands in an ASCII-format Command File. The batch mode provides an alternative to interactive-mode simulation, and is useful if you wish to repeat all or part of an earlier simulation session that has been recorded in a Log File. However, interactive-mode simulation provides more options and greater flexibility.

To run the Simulator in batch mode:

1.	Generate a timing, functional, or linked SNF for the project, as described in Creating a Timing Simulator Netlist File, Creating a Functional Simulator Netlist File, or Combining Multiple Projects for Simulation.

2.	Create an SCF or Vector File that contains the vector inputs for simulation and the names of the outputs to be simulated.

3.	Create a Command File that contains the simulation instructions.

4.	Choose Simulator to open the Simulator window.

5.	Choose Execute Command File (File menu) and specify the Command File name to run the batch-mode simulation, as described in Executing a Command File.

Output is automatically sent to the output file(s) specified in the Command File; any errors or warnings are also displayed in the Message Processor window.

See also:

Command File Format

Logging Simulation Commands

Running an Interactive-Mode Simulation


Running an Interactive-Mode Simulation

Interactive-mode simulation provides more flexibility and a larger range of simulation options than batch-mode simulation.

The steps in the following procedure summarize the actions needed to run a successful simulation. Each step represents another procedure that is described elsewhere; refer to Simulator Procedures for information on each step.

To run an interactive-mode simulation:

1.	Generate a timing, functional, or linked SNF for the project, as described in Creating a Timing Simulator Netlist File, Creating a Functional Simulator Netlist File, or Combining Multiple Projects for Simulation.

2.	Use the Waveform Editor to create a Simulator Channel File or use the Text Editor to create a Vector File that contains the vector inputs for simulation and the names of the outputs to be simulated.

3.	Choose Simulator to open the Simulator window.

4.	If necessary, specify the source of input vectors as described in Specifying the Source of Input Vectors. If no file has been previously specified for the project, the Simulator automatically loads the newest Vector File or SCF with the same filename as the project. The current source of input vectors is displayed in the Simulation Input field.

5.	Enter optional monitoring conditions and output files with one or more of the following:

Log simulation commands in a Log File and/or record simulation commands and output history in a History File with Inputs/Outputs (File menu).

Turn on any desired options, including Use Device, Setup/Hold, Check Outputs, Oscillation, or Glitch.

Initialize one or more node and/or group values with Initialize Nodes/Groups (Initialize menu).

Create one or more breakpoints with Breakpoint (Options menu).

If the defaults do not suit your needs, change the time in the Start Time and/or End Time field. By default, these times are 0 and the end time of the Vector File or SCF specified with Inputs/Outputs, respectively.

6.	Choose Start in the Simulator window or choose the Project Save & Simulate command (File menu) in any MAX+PLUS II application.

A message appears that indicates whether or not the simulation was successful.  It also contains information such as the time at which the circuit stabilized, the simulation coverage (i.e., the ratio of nodes actually simulated to the number of nodes in the SNF, expressed as a percentage), and the number of errors and/or warnings.

Output is automatically sent to the output file(s) specified with Inputs/Outputs.

See also:

Running a Batch-Mode Simulation


Starting, Pausing & Stopping the Simulator

The Start, Stop, and Pause buttons control when simulation begins and ends. When the Simulator is running or paused, some commands, options, and buttons--including some elements within command dialog boxes--are dimmed to indicate that they are not available.

To start the Simulator:

1.	If necessary, specify a non-default start time for simulation by typing a time in the Start Time field. The time you enter should be followed immediately (i.e., with no space in between) by a time unit; the default unit is ns. The default start time is 0ns.

2.	If necessary, specify a non-default time to end simulation by typing a time value plus an optional time unit in the End Time field. This time must be later than the time in the Start Time field. By default, this time is equal to the end time of the current Simulator Channel File. (If a Vector File was the source of input vectors, an SCF is generated automatically from it.)

3.	Set up simulation conditions, input files, and output files with menu commands and on-screen options.

4.	Choose Start to run the simulation.

or:

Choose the Project Save & Simulate command (File menu) in any MAX+PLUS II application to first save edits to currently open files, then simulate the project.

or:

Execute a Command File.

To pause the Simulator:

Choose Pause.

To stop the Simulator:

Choose Stop.

See also:

Executing a Command File

Running a Batch-Mode Simulation

Running an Interactive-Mode Simulation


File Structure Requirements for Multi-Project Simulation (Simulator)
File Structure Requirements for Multi-Project Simulation

You can combine simulation data from multiple projects--including projects implemented in different device families--into a linked SNF that allows you to simulate them together. If a linked SNF contains timing information only, you can also use it to run a timing analysis.

To perform a multi-project simulation, you create a super-project that consists of a top-level design file that contains symbols or instances representing multiple individual sub-projects. The super-project design file should conform to the following guidelines:

You should save family-specific macrofunctions in sub-projects with unique names, and then recompile the sub-project to avoid problems with error location, hierarchy traversal, and archiving. Refer to Renaming a Macrofunction in the Current Project.

Each sub-project must be compiled to create a functional, timing, or linked SNF; symbols or macrofunction instances in the super-project represent the SNFs of each previously compiled sub-project, not actual design files. Because functional SNFs can be included in a super-project, you can create a project that represents logic that cannot actually be implemented in an Altera device.

All files for the super-project must be located in the same directory. You can use Project Archive (File menu) to copy all sub-project files to a single super-project directory when you are creating a super-project from existing projects (i.e., "bottom-up" design).

You can connect sub-project symbols or instances with nodes, and enter input and output pins to feed signals into and out of the sub-project symbols or instances.

You can enter logic primitives between symbols. Both nodes and logic primitives inserted between symbols have a 0-ns delay in the linked SNF.

Node connections between symbols or instances in the super-project indicate a board-level interconnect. Therefore, you do not need to establish board-level connections using external connection pin primitives or the Connected Pins command (Assign menu). Connected pins are only necessary in a few cases, as described in Connected Pin Assignments.

During simulation, you can specify simulation vectors for the input pins and expected outputs for the output pins. Only declared inputs and outputs of the super-project are simulated as inputs and outputs; outputs of symbols or instances that do not feed pins are treated as buried nodes, even though they may represent physical device pins in a sub-project.

The linked SNF created from a super-project combines the functional and/or timing information in each project’s SNF, i.e., data from functional, timing, or linked SNFs. When you use a linked SNF for simulation, the Simulator automatically runs in a linked simulation mode.

The linked SNF is not automatically updated whenever you make changes to a sub-project. To update a linked SNF, you must recompile the modified sub-project, and then recompile the super-project. If you have copied an existing project from another directory, you may wish to update the files in that directory and recopy them to the super-project directory.

See also:

Archiving a Project

Combining Multiple Projects for Simulation

Primitives in Simulator Netlist Files & EDIF Output Files

Simulator Netlist File (.snf)


---------------------------------------BEGINNING OF NON-TRANSLATED TEXT-----------------------------------------

Messages from simmsgs.msg that are documented elsewhere (not in this file):

EVEC_PG_SYNTAX_ERROR 	COMESS

QSIM_OK_TO_STOP_SIMULATOR	COMESS

SSIM_EMPTY_SOCKET	PRMESS

SSIM_CONTINUITY_FAILED	PRMESS

WSIM_CANT_FIND_PIN	PRMESS

SSIM_BACKWARDS	PRMESS

SSIM_WRONG_ADAPTER	PRMESS

SSIM_EPLD_NOT_SUPPORTED	PRMESS

Messages from other applications/files that are documented here:

SWED_SCF_LOCKED	WEDMSGS.MSG

SWED_SNF_LOCKED	WEDMSGS.MSG

SWED_STATE_IGNORED	WEDMSGS.MSG

HWED_TABLE_FILE_CREATED	WEDMSGS.MSG

STAN_SNF_IS_IN_USE	TANMSGS.MSG

SPGM_FILE_BUSY	PGMMSGS.MSG

FDDM_SNF_IS_IN_USE	DDMMSGS.MSG

FE2C_FET_PARSER_ERROR	E2CMSGS.MSG

FVEC_TOO_MANY_NODES	VECMSGS.MSG

flnk_cant_lock_snf	lnkmsgs.msg

ffsn_snf_is_in_use 	fsnmsgs.msg

wmpp_license_not_available	mppmsgs.msg

ecmp_license_not_available	cmpmsgs.msg

---------------------------------------END OF NON-TRANSLATED TEXT-----------------------------------------


Absolute time <time> came after <time> in Pattern Section

CAUSE:	The last time read from an absolute time vector pattern in the Pattern Section was earlier than the time read from the previous vector pattern. Absolute times in vector patterns must always increase.

ACTION:	Change the vector pattern and try again.

See also:

MAX+PLUS II Messages

Message Format


Address line <number> (<name>) changed during write at <time> on memory <name> -- information written by Simulator may be incorr
Address line <number> (<name>) changed during write at <time> on memory <name> -- information written by Simulator may be incorrect

CAUSE:	The Simulator detected an address line change at the specified time on the specified memory node. Since address changes are illegal during a write operation, this violation may indicate errors in the information being written by the Simulator.

ACTION:	Check the design file(s) for functional errors. You can use the Message Processor’s Locate button to locate the node in the design file. You should also consider editing the SCF or Vector File and re-running the simulation.

See also:

Locating the Source of a Message

MAX+PLUS II Messages

Message Format


Can’t edit memory -- memory width exceeds 256 bits

CAUSE:	You tried to load a memory block into the  Initialize Memory dialog box that exceeded the maximum width of 256 memory bits.

ACTION:	No action is required. Make sure that the memory block you are importing does not exceed 256 bits.

See also:

MAX+PLUS II Messages

Message Format


Can’t find anything that matches text pattern <pattern>

CAUSE:	In a Command File, you entered a text pattern that does not match a breakpoint name, or a pattern that does not match any node or group name in the current SCF or SNF.

ACTION:	Check the Command File for errors. You can use wildcard characters  to create a pattern that matches existing node, group, or breakpoint names.

See also:

Command File Format

MAX+PLUS II Messages

Message Format


Can’t find node <name> that is used in a breakpoint condition

CAUSE:	The Simulator could not find the node name you entered as the left-hand side of a breakpoint condition for a BREAK CREATE command in the current SNF or SCF. The Simulator can only simulate a node or group that exists in the SNF for the project or a group that is created in the SCF.

ACTION:	Substitute the correct node or group name in the BREAK CREATE command and try again.

See also:

MAX+PLUS II Messages

Message Format


Can’t generate SCF from Vector File <filename>

CAUSE:	An error occurred while a Vector File was being converted into an SCF.

ACTION:	See the on-line help for the other messages that accompany this message for more information.

See also:

MAX+PLUS II Messages

Message Format

Vector File Format


Can’t list nodes -- no SNF exists for the project

CAUSE:	You chose List in the Initialize dialog box, but no SNF exists for the current project. The Simulator can’t list nodes if no SNF exists.

ACTION:	Recompile the current project with the Compiler’s Timing SNF Extractor, Functional SNF Extractor, or Linked SNF Extractor command (Processing menu) turned on to create an SNF for simulation.

See also:

Combining Multiple Projects for Simulation

Creating a Functional Simulator Netlist File

Creating a Timing Simulator Netlist File

MAX+PLUS II Messages

Message Format


Can’t paste -- Clipboard data <text> does not match the current <text>

CAUSE:	You tried to paste memory data into the Value box of the Initialize Memory dialog box. However, the paste operation could not be completed because the radix or width of the Clipboard data does not match the radix or width of the memory data currently displayed in the dialog box.

ACTION:	No action is required. Make sure that the radix and width of the memory data you wish to insert matches the radix and width of the current data.

See also:

MAX+PLUS II Messages

Message Format


Can’t simulate -- input node names in <filename> are completely different from those in <filename>

CAUSE:	None of the input node names in the Vector File or SCF match those in the SNF for the current project.

ACTION:	Ensure that you are using the correct Vector File or SCF for the project. (The Simulator automatically loads the newest SCF or Vector File with the same filename as the project.)

See also:

MAX+PLUS II Messages

Message Format

Specifying the Source of Input Vectors


Can’t simulate -- no SCF is loaded for the project

CAUSE:	The Simulator tried to start simulation, but no SCF has been specified as the source of input vectors. You may have entered the name of an SCF or Vector File that does not exist, or the filename of the Vector File or SCF is not the same as that of the project. The Simulator automatically loads the SCF or Vector File only if it has the same filename as the project.

ACTION:	Create an SCF or Vector File with the same filename as the project, or choose Inputs/Outputs and enter the correct SCF or Vector File filename if it is different from the filename of the project.

See also:

MAX+PLUS II Messages

Message Format

Specifying the Source of Input Vectors


Can’t simulate -- no SNF exists for the project

CAUSE:	The Simulator tried to start simulation, but no SNF exists for the current project.

ACTION:	Recompile the current project with the Compiler’s Timing SNF Extractor, Functional SNF Extractor, or Linked SNF Extractor command (Processing menu) turned on to create an SNF for simulation.

See also:

Combining Multiple Projects for Simulation

Creating a Functional Simulator Netlist File

Creating a Timing Simulator Netlist File

MAX+PLUS II Messages

Message Format


Can’t simulate -- optimized SNF generated with 16-bit Windows. Recompile before simulating with 32-bit Windows
Can’t simulate -- optimized timing SNF <name> was generated with 16-bit Windows. Recompile the project before simulating with 32-bit Windows

CAUSE:	You used a pre-4.0 version of MAX+PLUS II, which runs in the 16-bit Windows environment, to create an optimized timing SNF. You then tried to simulate your project using MAX+PLUS II version 4.0 or later, which runs in the 32-bit Windows environment. The 32-bit version of Windows cannot simulate 16-bit dynamic models.

ACTION:	Recompile the project using MAX+PLUS II version 4.0 or later with the Compiler’s Timing SNF Extractor and Optimize Timing SNF commands (Processing menu) turned on to create a new SNF for simulation.

See also:

Creating a Timing Simulator Netlist File

MAX+PLUS II Messages

Message Format


Can’t simulate with a device -- project requires multiple devices

CAUSE:	You turned on the Use Device option during simulation, but the current project uses multiple devices. Since the Vector File or SCF, as well as the SNF generated during compilation, used during simulation is for an entire project, it cannot be compared with the actual device outputs of a single device. Only projects that fit into a single device are compatible with the Use Device option.

ACTION:	If you want to simulate the project with a device, you must try to fit the project into a single device. However, if you can break your project into individual device-sized functional blocks (chips), you can compile an individual functional block and simulate it with a device.

See also:

MAX+PLUS II Messages

Message Format

Partitioning a Project


 Can’t simulate a project with connected output and/or bidirectional pins

CAUSE:	You turned on the Use Device option during simulation, but the project contains a TDF with a GDF with an OUTPUTC and/or BIDIRC primitive that connects multiple output and/or bidirectional pins. A device with these types of connected pins cannot be simulated with Use Device option.

ACTION:	A set of connected pins specified in a Pin Connection Statement or with OUTPUT or BIDIRC primitives can contain one output or bidirectional pin, but not more. Edit or delete any TDFs or GDFs that connect multiple output or bidirectional pins, recompile the project, and try again.

See also:

MAX+PLUS II Messages

Message Format

Testing Device Outputs vs. Simulation Outputs


Can’t run <text>: all network licenses are in use

CAUSE:	You tried to open or use the specified MAX+PLUS II application or module. However, all of the network licenses are currently in use.

ACTION:	Wait until a network license is available or if you wish to purchase additional network licenses, contact Altera Applications.

See also:

MAX+PLUS II Messages

Message Format


Changes made with this dialog box will be lost. OK to discard changes and close this dialog box?

CAUSE:	You made edits in the Initialize Memory dialog box and then chose Cancel or Close.

ACTION:	Choose OK to ignore edits and close the dialog box. Choose Cancel or Close to return to the dialog box to save your changes.

See also:

MAX+PLUS II Messages

Message Format


Command <name> is not supported

CAUSE:	The Command File contains an obsolete command that was supported only in MAX+PLUS (DOS version), e.g., a NETLIST, DELAY, FORCE, WAVEFORM, or LOG command.

ACTION:	Remove the obsolete command from the file.

See also:

Commands Available Only in DOS MAX+PLUS

MAX+PLUS II Messages

Message Format


Conflicting vector exists for <I/O type> node <name> at <time> -- ignoring earlier vector

CAUSE:	A Pattern Section contains a vector for the specified node that conflicts with a previous vector given for the node, so the previous vector is being ignored. The conflict may occur if multiple Pattern Sections that cover the same time period exist for the node, or if a node is a member of more than one group when vectors are defined for each group.

ACTION:	No action is necessary if you wish to use the later vector. Otherwise, you should check the Start Sections and Stop Sections in the Vector File to ensure that multiple vectors are not specified for a single node in any overlapping time periods. Check to be sure that a node is not a member of more than one group for which vectors are defined at the same time.

See also:

MAX+PLUS II Messages

Message Format


ECHO command output is too long (max. = 255 characters)

CAUSE:	The output of an ECHO command in a Command File is more than 255 characters, the maximum allowed.

ACTION:	Change the ECHO command (or split it into multiple commands) to create a smaller output line.

See also:

MAX+PLUS II Messages

Message Format


Found Clock <text> time violation at <time> on node <name>

CAUSE:	The Simulator detected a Clock high time or Clock low time violation at the specified time on the specified node, which is the Clock input of a DFF or a DFFE. The logic level on the node was not maintained for the minimum time specified in the data sheet for the device.

ACTION:	Check the design file(s) for functional errors. You can use the Message Processor’s Locate button to locate the node in the design file. You may need to edit the SCF or Vector File: vectors may be applied at intervals that are too short.

See also:

MAX+PLUS II Messages

Message Format


Found glitch at <time> on node <name>

CAUSE:	The Simulator detected a glitch at the specified time on the specified node. The logic level on the node changed at least twice within the period you specified as a glitch interval. (In a functional simulation, the glitch interval is always zero.)

ACTION:	Check the design file(s) for functional errors. You can use the Message Processor’s Locate button to locate the node in the design file. You may need to increase the glitch interval or edit the SCF or Vector File: vectors may be applied at intervals that are too short. If the error occurs in a functional simulation, change the SCF or Vector File so that multiple input logic level changes do not occur at the same time.

See also:

Glitch Option

MAX+PLUS II Messages

Message Format


Found hold time violation at <time> on <text>

CAUSE:	The Simulator detected a hold time violation at the specified time on the specified register or memory node. The data inputs to the nodes are changing too soon after a Clock edge. The delay from the data pins to the node may be too short, or the vectors in the SCF or Vector File may be applied too soon after the Clock.

ACTION:	Check the design file(s) for functional errors. You can use the Message Processor’s Locate button to locate the node in the design file. You should also consider editing the SCF or Vector File: vectors may be applied at intervals that are too short.

See also:

MAX+PLUS II Messages

Message Format

Setup/Hold Option


Found logic contention at <time> on node <name>

CAUSE:	There is more than one logic level driving a bidirectional pin or a group of connected output or bidirectional pins.

ACTION:	Set the Output Enable input to the pin to low (0) when the pin is used for input and to high (1) when it is used for output. If multiple pins are tied together, only one Output Enable can be high when that output drives the bus; all others must be low. All Output Enables must be low if the bus is being driven by an input pin.

See also:

MAX+PLUS II Messages

Message Format


Found NETLIST command -- terminating Command File

CAUSE:	The Simulator found a NETLIST command, which is available only in MAX+PLUS (DOS), in the Command File. Since this is an invalid command, the Simulator assumes that all following commands are incorrect and stops executing the file.

ACTION:	Remove the NETLIST command from the Command File. Place simulation commands for different projects into separate Command Files. If you want to change the project name, choose Project Name (File menu), then execute a different Command File.

See also:

Command File Format

Commands Available Only in DOS MAX+PLUS

MAX+PLUS II Messages

Message Format


Found nil-period oscillation at <time>. Continue simulating with these inputs, or cancel simulation?

CAUSE:	The Simulator has entered a state of nil-period oscillation, e.g., a ring oscillator, at the specified time. More than one vector is being applied to a single node at the same time.

ACTION:	Choose No to make the Simulator skip to the next set of input vectors. Choose Cancel to stop the simulation. If you choose Yes, the oscillation may continue indefinitely. Check the design file(s) for functional errors. You may need to edit the SCF or Vector File.

See also:

MAX+PLUS II Messages

Message Format

Oscillation Option


Found oscillation at <time> on node[s] <name(s)>

CAUSE:	The Simulator detected oscillation at the specified time on the specified node(s). The circuit has not stabilized within the period you specified as an oscillation interval after the latest input transition.

ACTION:	Check the design file(s) for functional errors. You can use the Message Processor’s Locate button to locate the nodes in the design file. You may need to increase the oscillation interval. Or you may need to edit the SCF or Vector File: vectors may be applied at intervals that are too short.

See also:

MAX+PLUS II Messages

Message Format

Oscillation Option


Found setup and/or hold time violation at <time> in input data for memory <name>

CAUSE:	The Simulator detected a hold and/or setup time violation at the specified time on the specified memory node. The data inputs to the nodes are changing too soon before a Clock edge. The delay from the data pins to the node may be too short, or the vectors in the SCF or Vector File may be applied too soon before the Clock.

ACTION:	Check the design file(s) for functional errors. You can use the Message Processor’s Locate button to locate the node in the design file. You should also consider editing the SCF or Vector File: vectors may be applied at intervals that are too short.

See also:

Locating the Source of a Message

MAX+PLUS II Messages

Message Format

Setup/Hold Option


Found setup time violation at <time> on <text>

CAUSE:	The Simulator detected a setup time violation at the specified time on the specified register or memory node. The data inputs to the nodes are changing too soon before a Clock edge. The delay from the data pins to the node may be too short, or the vectors in the SCF or Vector File may be applied too soon before the Clock.

ACTION:	Check the design file(s) for functional errors. You can use the Message Processor’s Locate button to locate the node in the design file. You should also consider editing the SCF or Vector File: vectors may be applied at intervals that are too short.

See also:

MAX+PLUS II Messages

Message Format

Setup/Hold Option


Found <text> violation at <time> on memory <name>

CAUSE:	The Simulator detected a write pulse width or read/write-cycle violation at the specified time on the specified memory node. The data inputs to the nodes are changing too soon before a Clock edge. The delay from the data pins to the node may be too short, or the vectors in the SCF or Vector File may be applied too soon before the Clock.

ACTION:	Check the design file(s) for functional errors. You can use the Message Processor’s Locate button to locate the node in the design file. You should also consider editing the SCF or Vector File: vectors may be applied at intervals that are too short.

See also:

Locating the Source of a Message

MAX+PLUS II Messages

Message Format


Group <name> contains input nodes -- COMB or REGISTER node type is not possible

CAUSE:	You declared a group that contains input nodes to have a node type of COMB or REGISTER in a Combinatorial Section or Registered Section in the Vector File. Input nodes cannot have a node type of COMB or REGISTER.

ACTION:	Edit the Vector File.

See also:

MAX+PLUS II Messages

Message Format


Group <name> has already been created

CAUSE:	You specified a group name that has already been used to create a group in an earlier Group Create Section.

ACTION:	Remove the extra Group Create Section or use a different group name.

See also:

MAX+PLUS II Messages

Message Format


Group <name> was created but never used

CAUSE:	You created a group in a Group Create Section, but never listed its name in an Inputs Section, Outputs Section, or Buried Section, so the Simulator cannot add it to the SCF that is generated from the Vector File.

ACTION:	If you wish to include the group in your simulation, list the group name in an Inputs, Outputs, or Buried Section. Otherwise, you should remove the Group Create Section.

See also:

MAX+PLUS II Messages

Message Format


Hit breakpoint <name> at <time>

CAUSE:	A set of breakpoint conditions were met at the specified time. In interactive-mode simulation, the Simulator will enter the paused state.

ACTION:	When the Simulator pauses at a breakpoint, you can use the same limited set of capabilities that are available when you choose Pause. When you are ready to resume simulation, choose Start.

See also:

MAX+PLUS II Messages

Message Format


Ignored illegal .ini file variable: <variable>=<value>

CAUSE:	You assigned an illegal value to a variable in the maxplus.ini File. The Simulator will use the default value for the specified variable.

ACTION:	You should never edit either of the .ini files. However, you may delete the illegal variable to stop this message from recurring.

See also:

MAX+PLUS II Messages

Message Format


Ignored input node <name> -- it is an alias for input node <name>

CAUSE:	The Simulator has ignored the specified input node name because it is an alias for an input node already in the SNF. The Simulator will use the first name it finds as the "real" input node name and ignore any aliases. Therefore, the specified ignored node name will not appear in the default SCF for the project.

ACTION:	If the Simulator is choosing the incorrect name, remove the alias(es) for the input node.

See also:

MAX+PLUS II Messages

Message Format


Ignoring state <name> -- it duplicates value of <text>
Ignored state <name> -- it duplicates value of <text>

CAUSE:	The Simulator has ignored the specified state because it is a duplicate of another specified state, i.e., its combination of state bit values is the same as for the other state. Therefore, the specified ignored state will not appear in the default SCF for the project. This condition may occur if the project contains unreachable or duplicated states.

ACTION:	Unless duplicate states are not a problem, check the design file(s) for errors.

See also:

MAX+PLUS II Messages

Message Format


Illegal don’t-care value at <time> on address line of memory segment <name>
Illegal don’t-care value at <time> on <text> of memory segment <name>

CAUSE:	The Simulator detected an illegal "don’t-care" value at the specified time on the write-enable or address line of the specified memory segment.

ACTION:	Check the design file(s) for functional errors. You can use the Message Processor’s Locate button to locate the node in the design file. You should also consider editing the SCF or Vector File and re-running the simulation.

See also:

MAX+PLUS II Messages

Message Format


Illegal time and unit: <number> and <unit>

CAUSE:	The time value plus the time unit specified in the Command File is longer than the maximum of 32 characters.

ACTION:	Edit the Command File and enter the time again using fewer than 32 characters.

See also:

MAX+PLUS II Messages

Message Format


Illegal time value: glitch/oscillation = <time>

CAUSE:	You used an illegal time value with the on-screen Glitch or Oscillation option, or the equivalent Command File GLITCH or OSCILLATION command. A common error is an added space between the time value and the time unit, e.g., 10.0 ns instead of 10.0ns.

ACTION:	Enter a legal time in the correct format.

See also:

Defining & Detecting Glitches

Defining & Detecting Oscillation

MAX+PLUS II Messages

Message Format


Illegal value string <text> for radix <radix type>

CAUSE:	The group value in the Pattern Section contains characters that are not legal logic level characters for the specified group radix.

ACTION:	You have two choices: change the group radix either globally (in the Radix Section) or locally, or change the radix you use to enter the group value in the Pattern Section.

See also:

MAX+PLUS II Messages

Message Format

Overriding the Current Radix


Incomplete pattern found in Pattern Section

CAUSE:	The Pattern Section ends with an incomplete line. This error often occurs if the semicolon is omitted at the end of the section.

ACTION:	Fix the pattern and try again.

See also:

MAX+PLUS II Messages

Message Format


Inputs Section contains node/group <name> but no pattern exists for it

CAUSE:	A node or group was declared in an Inputs Section of the Vector File but no vectors were assigned to it in a Pattern Section. This message may occur if you list a node or group in an Inputs Section that follows a previous Pattern Section: the previous patterns are cleared by the following Inputs Section.

ACTION:	Either remove the unused node or group from the Inputs Section, or provide vectors for the node or group in a Pattern Section that follows the Inputs Section.

See also:

MAX+PLUS II Messages

Message Format


Installed hardware does not support Use Device option

CAUSE:	You turned on the Use Device option and chose Start, but your programming hardware is not capable of performing functional testing or reading actual device outputs.

ACTION:	Check the hardware and connections. You must have a PL-MPU to read actual device outputs or perform functional testing; the PLE3-12A programming unit does not support it. If you have the correct hardware and it appears to be correctly connected, use Hardware Setup (Options menu) in the Programmer.

See also:

MAX+PLUS II Messages

Message Format


Invalid absolute time <time> -- needs '>' character

CAUSE:	The absolute time that preceded a vector pattern in the Pattern Section of the Vector File was not followed by the required > character.

ACTION:	Insert the > character between the time value and the vector pattern and try again.

See also:

Absolute Time Vector Patterns

MAX+PLUS II Messages

Message Format


Member node names and/or state names of one or more SCF groups
Member node names and/or state names of one or more SCF groups (<group name(s)>) have changed--updating SCF

CAUSE:	The SCF (or Vector File that has been automatically converted into an SCF) that you created earlier contains one or more groups in the original design files of the project. Since you created this SCF, the project has been recompiled, and the SNF has changed. The most likely cause of this message is that the Compiler has assigned new names to individual state bits, i.e., group members. (These names are of the format ~dbxxxx.) Or, the state names in the original design file have changed, so the state names displayed in group waveforms in the SCF are incorrect. The Simulator has identified the groups with these two types of changes, and is updating the names of the group members and the state names to reflect the changes in the new SNF.

ACTION:	No action is required.

See also:

MAX+PLUS II Messages

Message Format


No Inputs Section exists for this pattern

CAUSE:	A Vector File contains a Pattern Section that contains input logic levels and an Outputs Section or Buried Section, but no Inputs Section. All logic levels listed before an = character in the Pattern Section are interpreted as input logic levels; those after it are interpreted as expected outputs.

ACTION:	Create an Inputs Section to go with the input logic levels in the Pattern Section, or edit the Pattern Section to make each line start with an = character, so that the format specifies only expected outputs.

See also:

MAX+PLUS II Messages

Message Format


No Outputs Section exists for this pattern
No Outputs or Buried Section exists for this pattern

CAUSE:	A Vector File contains a Pattern Section that contains output logic levels and an Inputs Section, but no Outputs or Buried Section. All values listed before an = character in the Pattern Section are interpreted as input logic levels; those after it are interpreted as expected outputs.

ACTION:	Create an Outputs or Buried Section to go with the expected outputs in the Pattern Section, or edit the Pattern Section to specifies only inputs.

See also:

MAX+PLUS II Messages

Message Format


Node <name> has not been created [as an output or buried node]

CAUSE:	You declared a node type for a non-existent node in a Combinatorial Section, Machine Section, or Registered Section; or you declared a node type of COMB or REGISTER for an input node.

ACTION:	Declare a node in an Inputs Section, Outputs Section, or Buried Section, before specifying its secondary inputs in Combinatorial, Machine, or Register Sections. Input nodes cannot have a node type of COMB or REGISTER.

See also:

MAX+PLUS II Messages

Message Format


Node <name> in SIF does not exist in the current SNF

CAUSE:	When you tried to restore initialization values from an SIF, the Simulator found that a node name listed in the SIF no longer exists in the SNF for the project, so it has ignored the initialization value for that node. You may have changed the project since the SIF was created, perhaps by deleting the node from a design file and recompiling the project to create a new SNF. This message can also occur if the project contains a state machine and the Compiler has assigned a different set of state bit names for the state machine during the last compilation.

ACTION:	You may wish to specify new initialization values for the current SNF and then save a new SIF with the updated values. No action is required to continue to ignore the initialization value for the specified node.

See also:

Initializing Node & Group Values

MAX+PLUS II Messages

Message Format

Restoring Node & Group Initialization Values

Saving Node & Group Initialization Values


Output logic level does not match SCF logic level for node <name> at <time>
Output logic level <logic level> does not match SCF logic level <logic level>  for node <name> at <time>

CAUSE:	The simulated output or actual device output differs functionally from the output logic level in the SCF. This message may occur if the logic of the compiled project does not meet your expectations, the device was not properly programmed, or you have used inappropriate expected output values in the SCF or Vector File.

ACTION:	Check the design file(s) for functional errors. You can use the Message Processor’s Locate button to locate the node in the design file. You should also check the SCF or Vector File for errors: you will obtain the most reliable function testing results if the file contains simulation outputs rather than other user-defined expected outputs. You may need to reprogram the device.

See also:

Checking Simulation Outputs vs. User-Specified Outputs

Functional Testing with the SCF, Vector File, or Programming File

MAX+PLUS II Messages

Message Format


Parser error: <text>

CAUSE:	The portion of MAX+PLUS II software that processes certain text files, including the Vector File, Command File, Fit File, and EDIF Input File has run out of memory or encountered an I/O error.

ACTION:	If you receive an out of memory error, try to make more memory available to MAX+PLUS II either by quitting other programs or installing more memory in your computer. If the <text> of the message is "pclex input buffer overflow," try reducing the length of comments in your EDIF Input Files to less than 100 characters. If you receive an I/O error, you may have deleted or corrupted one or more of the files required to run MAX+PLUS II. Therefore, you must reinstall the MAX+PLUS II software.

See also:

MAX+PLUS II Messages

Message Format


Pasting will cause memory data to be truncated. OK to paste?

CAUSE:	You tried to paste memory data into the Value box of the Initialize Memory dialog box. However, the paste operation will cause a portion of the memory information to be lost.

ACTION:	Choose Cancel or Close to cancel the paste operation. Choose OK to complete the paste.

See also:

MAX+PLUS II Messages

Message Format


Pattern Section exists, but Inputs, Outputs, and Buried Sections are missing

CAUSE:	A Vector File has a Pattern Section but no Inputs Section, Outputs Section, or Buried Section.

ACTION:	Add an Inputs, Outputs, or Buried Section. However, a meaningful Vector File should contain both an Inputs Section and an Outputs and/or Buried Section.

See also:

MAX+PLUS II Messages

Message Format


Preset and Clear are both active at <time> on register <node name>

CAUSE:	The Simulator has found that both the Preset and Clear pins are active for a DFF in the SNF. The behavior of the flipflop is undefined in this situation.

ACTION:	Check the SCF or Vector File for errors. Also check the design files for logic errors. You can use the Message Processor’s Locate button to locate the node in the design file.

See also:

MAX+PLUS II Messages

Message Format


Project simulation canceled.
Project simulation canceled

Simulation ended at <time>

Simulation coverage: <number> %

<number> errors

<number> warnings

CAUSE:	You chose Stop at the specified time, before the Simulator reached the time shown in the End Time field (by default, this time is the end time of the SCF). The simulation coverage is the ratio (expressed as a percentage) of nodes actually simulated to the number of nodes in the SNF. Any errors and/or warnings are listed in a Message Processor window.

ACTION:	Choose OK to close the dialog box. You can use the Locate button in the Message Processor to find the sources of error and/or warning messages. You may need to simulate for an additional period to determine whether additional output node logic level changes will occur. You can continue the simulation from the current time by changing the Start Time to be equal to the current Simulation Time and choosing Start. If the simulation coverage percentage is low, some input nodes may not have been used. Another possibility is that some logic is not attached to the inputs. You may need to change the SCF or Vector File to include more of the nodes in the project to obtain truly meaningful simulation results.

See also:

MAX+PLUS II Messages

Message Format


Project simulation was successful.
Project simulation was successful

Circuit stabilized at <time>

Simulation ended at <time>

Simulation coverage: <number> %

<number> errors

<number> warnings

CAUSE:	The Simulator has simulated to the time shown in the End Time field (by default, this time is the end time of the SCF). The logic levels of the output nodes in the SCF stabilized at the specified time. The simulation coverage is the ratio (expressed as a percentage) of nodes actually simulated to the number of nodes in the SNF. The number of errors and warnings is always zero in a successful simulation.

ACTION:	Choose OK to close the dialog box. If the simulation coverage percentage is low, some input nodes may not have been used. Another possibility is that some logic is not attached to the inputs. You may need to change the SCF or Vector File to include more of the nodes in the project to obtain truly meaningful simulation results. If you did not simulate to the end of the current SCF, you can change the End Time and choose Start to continue simulation.

See also:

MAX+PLUS II Messages

Message Format


Project simulation was unsuccessful.
Project simulation was unsuccessful

Circuit stabilized at <time>

Simulation ended at <time>

Simulation coverage: <number> %

<number> errors

<number> warnings

CAUSE:	The Simulator has encountered errors and/or warning conditions in the project itself or in the files used for simulation. These conditions have either already been reported to you in pop-up message boxes, or are listed in a Message Processor window. The simulation ended and the logic levels of the output nodes in the SCF stabilized at the specified times. The simulation coverage is the ratio (expressed as a percentage) of nodes actually simulated to the number of nodes in the SNF.

ACTION:	Choose OK to close the dialog box. You can use the Locate button in the Message Processor to find the sources of errors and/or warnings. You may need to change the SCF or Vector File, or the design file(s) for the project to simulate without errors.

See also:

MAX+PLUS II Messages

Message Format


Simulation ended at <time>

CAUSE:	The Simulator has completed simulation either successfully or unsuccessfully. Or you have canceled the simulation. The simulation ended at the specified time. This condition has either been reported to you in pop-up message box, or is listed in a Message Processor window.

ACTION:	You can use the Locate button in the Message Processor to find the sources of error and/or warning messages. If simulation was unsuccessful, you may need to change the SCF or Vector File, or the design file(s) for the project to simulate without errors. If you canceled the simulation, you may need to simulate for an additional period to determine whether additional output node logic level changes will occur. You can continue the simulation from the current time by changing the Start Time to be equal to the current Simulation Time and choosing Start. If the simulation was successful, but the simulation coverage percentage is low, some input nodes may not have been used. Another possibility is that some logic is not attached to the inputs. You may need to change the SCF or Vector File to include more of the nodes in the project to obtain truly meaningful simulation results.

See also:

MAX+PLUS II Messages

Message Format


Project SNF does not contain [<I/O type>] node <name>
Project SNF does not contain [<I/O type>] node/group <name>

CAUSE:	The specified node name or group name in an SCF or Vector File does not exist in the SNF for the project. This can happen if the name was entered incorrectly, or if the node/group was deleted, moved to another file in the project hierarchy, or did not "survive" logic synthesis when the project was compiled to create a timing SNF. This error may also occur if the node exists in the SNF but has an I/O type different from the I/O type specified in the SCF or Vector File. The I/O type problem is common in Vector Files that were originally created for MAX+PLUS (DOS), because both buried and output nodes could be listed in the Outputs Section.

ACTION:	If the node does not exist in the SNF with any I/O type, it will be ignored during simulation. If only the I/O type of the node is wrong, the node will be ignored during simulation unless it is a buried node that is listed as an output node (as in a MAX+PLUS (DOS) Vector File). In this case, the Simulator will treat the buried node as an output node. Otherwise, you must update the SCF or Vector File either by removing the node/group name or changing its I/O type. You can use the dialog box for the Initialize (Initialize menu) command to list all nodes and groups in a timing SNF that have survived logic synthesis.

See also:

MAX+PLUS II Messages

Message Format


Relative vector pattern is missing a valid stop time

CAUSE:	A relative time vector pattern in the Pattern Section in a Vector File has no stop time or the stop time given in the pattern occurs before the start time.

ACTION:	Add a Stop Section to provide the stop time. Or change the start and/or stop time so that the stop time occurs after the start time.

See also:

MAX+PLUS II Messages

Message Format

Relative Time Vector Patterns


SCF <filename> is being used by another application and is locked

CAUSE:	Another MAX+PLUS II application is using the SCF, so you cannot edit it, open it, or use it for another function. For example, this message occurs if you try to edit an SCF while it is being overwritten during simulation or used during functional testing, if you try to begin simulation while you are actively editing an SCF, or if you try to load an SCF for functional testing in the Programmer while the Simulator is running.

ACTION:	Stop the current simulation or functional test or wait for it to finish to free up the file. Or stop editing the SCF so that the simulation or functional test can begin.

See also:

MAX+PLUS II Messages

Message Format


SCF successfully generated from <filename>

CAUSE:	An SCF was successfully created from the Vector File that you specified as the source of input vectors.

ACTION:	None.

See also:

MAX+PLUS II Messages

Message Format


Secondary input <name> is defined twice

CAUSE:	You have defined the same secondary input twice in a Vector File Register Section or Machine Section, e.g., REGISTER NEWREG CLOCK = FOO CLOCK = BAR.

ACTION:	Specify only one Clock, Reset,, or Preset input per node in the Register or Machine Section.

See also:

MAX+PLUS II Messages

Message Format


Simulator is loading or converting a file. OK to stop the Simulator?

CAUSE:	While the Simulator was loading the SNF at startup, or while it was loading or creating an SCF or Table File, you tried to close the Simulator, quit MAX+PLUS II, or to change the project name.

ACTION:	Choose OK if you wish to close the Simulator or quit MAX+PLUS II and stop the current activity, or to change the project name. Choose Cancel if you wish to continue the current activity and disregard your most recent command.

See also:

Changing the Project Name

Exiting from MAX+PLUS II

MAX+PLUS II Messages

Message Format


SNF <filename> is being used by another application and is locked

CAUSE:	Another application is using the SNF, so it is not available for the action you requested. For example, this message may occur if you choose Enter Nodes from SNF (Node menu) while the Compiler is creating a new SNF, or while the Simulator or Timing Analyzer is running.

ACTION:	Wait for compilation, simulation, or timing analysis to finish, or choose Stop in the Compiler, Simulator, or Timing Analyzer and try again.

See also:

MAX+PLUS II Messages

Message Format


Start time <time> is after SCF end time <time> -- changing start time to 0.0ns

CAUSE:	You entered a start time for simulation in the Start Time field that is greater than the end time of the SCF that is loaded in the Simulator. (The Simulator automatically loads the newest SCF or Vector File with the same filename as the project.)

ACTION:	No action is required. You can specify a different SCF or Vector File as the source of input vectors for simulation and/or type a different start time.

See also:

MAX+PLUS II Messages

Message Format

Specifying the Source of Input Vectors


Successfully generated Table File <filename>

CAUSE:	A Table File was successfully generated from the current SCF or WDF.

ACTION:	No action is required.

See also:

MAX+PLUS II Messages

Message Format


Too many members in group <name> (max. = 256)

CAUSE:	The Group Create Section attempts to include more than 256 individual nodes in the specified group, which is the maximum permitted. The members of groups that are combined to create a new group count toward the total number of permitted nodes.

ACTION:	Reduce the number of nodes to be included in the specified group.

See also:

MAX+PLUS II Messages

Message Format


Too many nodes/groups in Vector File (max. = 4096)

CAUSE:	The Vector File contains over 4096 nodes and/or groups.

ACTION:	Create several Vector Files to reduce the number of nodes and/or groups in any one file.

See also:

MAX+PLUS II Messages

Message Format


Tried to compare Vector File to <filename>, but SNF is <text>

CAUSE:	When you tried to convert a Vector File to an SCF in the Simulator or Waveform Editor, MAX+PLUS II tried to compare the nodes and groups in the Vector File to those in the SNF. MAX+PLUS II could not compare the files either because another application is currently using the SNF or because the file is corrupted. For example, this message may occur if you choose Import Vector File (File menu) while the Compiler is creating a new SNF, or while the Simulator or Timing Analyzer is running.

ACTION:	If the SNF is locked, wait for compilation, simulation, or timing analysis to finish, or choose Stop in the Compiler, Simulator, or Timing Analyzer. If the SNF is corrupted, recompile the project to create a new SNF.

See also:

MAX+PLUS II Messages

Message Format


Too many transitions in Pattern Section

CAUSE:	The Pattern Section has too many transitions. The limit is approximately 8,000.

ACTION:	Use absolute time vector patterns rather than relative time vector patterns, or use smaller patterns.

See also:

MAX+PLUS II Messages

Message Format


Command File <name> calls itself -- file processing halted

CAUSE:	The specified Command File contains a COMMAND  command that calls itself. MAX+PLUS II does not support recursive Command Files.

ACTION:	Delete the recursive COMMAND command or change the name of the file that it specifies.

See also:

Command File Format

Executing a Command File

MAX+PLUS II Messages

Message Format


Vector File--Context-Sensitive Help
Vector File Context-Sensitive Help

Context-sensitive help is available for the following Vector File keywords and characters:

\ (backslash)	HEX

\BIN	INPUTS

\DEC	INTERVAL

\HEX	MACHINE

\OCT	MS

: (colon)	NS

> (greater than)	OCT

% (percent)	OUTPUTS

. (period)	PATTERN

; (semicolon)	PRESET

0 through 9 logic levels 	RADIX

= (equals)	REGISTER

| (vertical bar)	RESET

A through F logic levels	START

BIN	S

COMB	STOP

CLOCK	UNIT

CREATE	US

DEC	X logic level

GROUP	Z logic level

See also:

Vector File Format


Select the Appropriate Section

For help on the RESET, PRESET, CLEAR, or CLOCK keywords, choose a Vector File Section:

Registered Section

Machine Section


Unit Section (Vector File)

Specifies the time units used in all subsequent Start, Stop, Interval, and Pattern Sections.

The optional Unit Section consists of the keyword UNIT, followed by a time unit. If you do not enter a time unit, ns is the default throughout the Vector File, unless it is temporarily overridden in the Start, Stop, Interval, and Pattern Sections.

The Unit Section ends with a semicolon (;). Example

See also:

Functional Testing with the SCF, Vector File, or Programming File

Punctuation, White Space & Comments


Example: Unit Section (Vector File)
Sample Unit Section

UNIT ms; % millisecond units %


Start Section (Vector File)

Specifies when to start applying relative time vector patterns listed in the subsequent Pattern Section(s).

The optional Start Section consists of the keyword START, followed by a time value and an optional time unit. If you do not enter a time unit, the unit specified in the Unit Section is assumed. The Start Section ends with a semicolon (;). Example

If no Start Section is present, the start time defaults to 0. The Vector File can contain multiple Start and Stop Sections that represent overlapping time periods. However, you must ensure that different vector patterns do not apply to the same time period.

The Start Section is unnecessary if absolute time vector patterns are given in the Pattern Section.

See also:

Absolute Time Vector Pattern

Differences from MAX+PLUS (DOS) Vector File Syntax

Functional Testing with the SCF, Vector File, or Programming File

Punctuation, White Space & Comments

Relative Time Vector Pattern


Example: Start Section (Vector File)
Sample Start Section

START 5ns;  % start at 5 ns %


Stop Section (Vector File)

Specifies when to stop applying the relative time vector patterns listed in the Pattern Section.

The Stop Section consists of the keyword STOP, followed by a time value and an optional time unit. If you do not enter a time unit, the unit specified in the Unit Section is assumed. The Stop Section ends with a semicolon (;). Example

The Vector File can contain multiple Start and Stop Sections that represent overlapping time periods. However, you must ensure that different vector patterns do not apply to the same time period.

If relative time vector patterns are used in the Pattern Section, the Stop Section is required. If there is no Stop Section and absolute time vector patterns are given in the Pattern Section, the time of the last vector pattern becomes the stop time.

See also:

Absolute Time Vector Pattern

Differences from MAX+PLUS (DOS) Vector File Syntax

Functional Testing with the SCF, Vector File, or Programming File

Punctuation, White Space & Comments

Relative Time Vector Pattern


Example: Stop Section (Vector File)
Sample Stop Section

STOP 150ms;    % end pattern at 150 ms %


Interval Section (Vector File)

Specifies the intervals at which relative time vector patterns are applied.

The optional Interval Section consists of the keyword INTERVAL, followed by a time value and an optional time unit. If you do not enter a time unit, the unit specified in the Unit Section is assumed. The Interval Section ends with a semicolon (;). Example

If no Interval Section is present, the interval time defaults to 1 ns. The Interval Section is ignored if absolute time vector patterns are given in the Pattern Section.

See also:

Absolute Time Vector Pattern

Punctuation, White Space & Comments

Relative Time Vector Pattern


Example: Interval Section (Vector File)
Sample Interval Section

INTERVAL 15ns; % apply vectors every 15 ns %


Group Create Section (Vector File)

Groups up to 256 nodes so that they can be simulated as a group.

In a Vector File used for waveform design entry, a group has no logical meaning and a Group Create Section is optional.

In a Vector File used for simulation, the Group Create Section is not always required for groups, buses, or state machines that were created in the original design files for the project. However, if you wish, you can always re-create a group in a Group Create Section for documentation purposes.

The Group Create Section is required to simulate a group that does not appear in the SNF for the project. All groups created in a project’s design files appear in the functional SNF. However, unless all member nodes in a group have "survived" logic minimization and synthesis, the group does not appear in the timing SNF. If one or more group members have been eliminated through logic synthesis, only individual nodes remain in the timing SNF, and you must create a new group to simulate the remaining group members. You can list all nodes and groups in the SNF in the Nodes & Groups box in the Initialize command’s dialog box.

The Group Create Section consists of the keywords GROUP CREATE, followed by an arbitrary group name with up to 32 name characters, an equal sign (=), and a list of node names. The Group Create Section ends with a semicolon (;). The entire section is repeated for each group. Example

All nodes in the group must have the same I/O type. In a Vector File used for simulation, node names must be the same as those in the project’s original design file(s), including a hierarchy path, if needed.

The Pattern Section must contain a logic level that corresponds to a group of input nodes; the name of the group must also be listed in the Inputs Section. The names of output and buried node groups must be listed in the Outputs Section and Buried Section, respectively; expected outputs in the Pattern Section are optional. The name of a node that is a member of a group should not be listed along with the group name in the Inputs, Outputs, or Buried Sections. Otherwise, you must provide a vector pattern for both the group and the member node in the Pattern Section.

See also:

Functional Testing with the SCF, Vector File, or Programming File

Hierarchical Node & Symbol Names

Listing Node & Group Values

Simulating Bidirectional Pins


Example: Group Create Section (Vector File)
Sample Group Create Section

GROUP CREATE groupABC = nodeA nodeB nodeC;


Radix Section (Vector File)

Specifies the radix used to interpret the vector values for groups.

The optional Radix Section specifies the radix used to interpret group values given in the Pattern Section. It also determines the radix used to display all groups in the SCF that is generated automatically from the Vector File.

The Radix Section consists of the keyword RADIX, followed by BIN (binary), DEC (decimal), HEX (hexadecimal), or OCT (octal). The Radix Section ends with a semicolon (;). Example

If no Radix Section is present, the radix defaults to HEX.

See also:

Functional Testing with the SCF, Vector File, or Programming File

Overriding the Current Radix


Example: Radix Section (Vector File)
Sample Radix Section

RADIX DEC;      % set radix to decimal %


Inputs Section (Vector File)

Specifies the input node and/or group names for which vectors will be applied.

The required Inputs Section specifies the input node and/or group names that provide input vectors for simulation or waveform design entry. Vector patterns that correspond to these names must be given in the Pattern Section. Inputs that are not included in the Vector File are automatically assigned undefined (X) logic levels during simulation and low (0) logic levels during functional testing.

The Inputs Section consists of the keyword INPUTS, followed by a list of node and/or group names, and terminated with a semicolon (;). In a Vector File used for simulation, node names must be the same as those in the original design file(s) for the project, including a hierarchy path, if needed. Example

An Inputs Section applies to all Pattern Sections that follow it until the next Inputs Section. If you create a new Inputs Section and wish to use input nodes and/or groups that were listed in a previous Inputs Section, you must relist these nodes and/or groups. Example

You can include the names of groups created in the Group Create Section, or group, bus, and state machine names created in the project’s design files. State machine names are not eliminated during logic synthesis, and can be included in the Inputs Section. However, a group name from a design file can be included in a Vector File for a timing simulation only if all of its members have "survived" logic synthesis. To check which nodes and groups still exist in the synthesized project, use the Simulator’s Initialize command to list nodes and groups.

You can avoid the effort of typing full hierarchical node names by using probes in the input design file(s) for the project. Since each probe name is unique, it can be used instead of the full hierarchical node name.

Groups listed in the Inputs Section are displayed as groups in the SCF.

See also:

Functional Testing with the SCF, Vector File, or Programming File

Hierarchical Node & Symbol Names

Punctuation, White Space & Comments

Overriding the Current Radix

Simulating Bidirectional Pins


Example: Inputs Section (Vector File)
Sample Inputs Section

INPUTS databus clk OEN nodeA;


Example: Input and Pattern Sections (Vector File)
Using Inputs Sections with Pattern Sections

In this example, the first Inputs Section establishes A1 and A2 as input data for the first and second Pattern Sections, while the second Inputs Section defines A1 and B1 as the inputs for the third Pattern Section. To use A1 as an input for the third Pattern Section, you must relist it in the Inputs Section preceding the Pattern Section, since the addition of an Inputs Section clears data from all previous Inputs Sections.

INPUTS A1 A2;

START 0;

STOP 25;

PATTERN	% Pattern Section 1 with inputs A1 and A2 %

0   0   0

0   0   1;

START 26;

STOP 50;

PATTERN	% Pattern Section 2 with inputs A1 and A2 %

0   1   0

1   0   0;

INPUTS A1 B1;

START 51;

STOP 100;

PATTERN	% Pattern Section 3 with inputs A1 and B1 %

1   1   0

0   1   1;


Outputs Section (Vector File)

Specifies the output node and/or group names to be simulated or to be created for waveform design entry.

In a Vector File used for simulation, the Outputs Section is optional. This section specifies the names of output node and/or group names for which simulated output logic levels are to be reported in the SCF and the optional Table File. If you wish to compare expected outputs to simulation outputs, output logic levels that correspond to these names must be given in the Pattern Section.

In a Vector File used for waveform design entry, the Outputs Section is required. This section specifies the names of the outputs to be created. Output logic levels for these names must be given the Pattern Section.

The Outputs Section consists of the keyword OUTPUTS, followed by a list of node and/or group names, and terminated with a semicolon (;). In a Vector File used for simulation, node names must be the same as those in the original design file(s) for the project, including a hierarchy path, if needed. Example

An Outputs Section applies to all Pattern Sections that follow it until the next Outputs Section. If you create a new Outputs Section and wish to use output nodes and/or groups that were listed in a previous Outputs Section, you must relist these nodes and/or groups. Example

You can include the names of groups created in the Group Create Section or group, bus, and state machine names created in the project’s design files. State machine names are not eliminated during logic synthesis, and can be included in the Outputs Section. However, a group or bus name from a design file can be included in a Vector File for a timing simulation only if all of its members have "survived" logic synthesis. To check which nodes and groups still exist in the synthesized project, use the Simulator’s Initialize command to list nodes and groups.

You can avoid the effort of typing full hierarchical node names by using probes in the input design file(s) for the project. Since each probe name is unique, it can be used instead of the full hierarchical node name.

Groups listed in the Outputs Section are displayed as groups in the SCF.

See also:

Differences from MAX+PLUS (DOS) Vector File Syntax

Functional Testing with the SCF, Vector File, or Programming File

Overriding the Current Radix

Punctuation, White Space & Comments

Simulating Bidirectional Pins


Example: Outputs Section (Vector File)
Sample Outputs Section

OUTPUTS RCO QA QB QC;


Example: Output and Pattern Sections (Vector File)
Using Outputs Sections with Pattern Sections

In this example, the first Outputs Section establishes A1 and A2 as outputs for the first and second Pattern Sections, while the second Outputs Section defines A1 and B1 as the outputs for the third Pattern Section. To use A1 as an output for the third Pattern Section, you must relist it in the Outputs Section preceding the Pattern Section, since the addition of an Outputs Section clears data from all previous Outputs Sections.

OUTPUTS A1 A2;

START 0;

STOP 25;

PATTERN	% Pattern Section 1 with outputs A1 and A2 %

0   0   0

0   0   1;

START 26;

STOP 50;

PATTERN	% Pattern Section 2 with outputs A1 and A2 %

0   1   0

1   0   0;

OUTPUTS A1 B1;

START 51;

STOP 100;

PATTERN	% Pattern Section 3 with outputs A1 and B1 %

1   1   0

0   1   1;


Buried Section (Vector File)

Specifies the buried node and/or group names to be simulated or to be created for waveform design entry.

In a Vector File used for simulation, the optional Buried Section specifies the names of buried nodes and groups (i.e., internal node and group names that do not feed output pins) for which simulated buried logic levels are to be reported in the SCF and the optional Table File. If you wish to compare expected outputs to simulation outputs, buried logic levels that correspond to these names must be given in the Pattern Section.

In a Vector File used for waveform design entry, the optional Buried Section specifies the names of intermediate buried nodes to be used to synthesize the output nodes in the Outputs Section. Logic levels for these names must be given the Pattern Section.

The Buried Section consists of the keyword BURIED, followed by a list of node and/or group names, and terminated with a semicolon (;). In a Vector File used for simulation, node names must be the same as those in the original design file(s) for the project, including a hierarchy path, if needed. Example

A Buried Section applies to all Pattern Sections that follow it until the next Buried Section. If you create a new Buried Section and wish to use buried nodes and/or groups that were listed in a previous Buried Section, you must relist these nodes and/or groups. Example

You can include the names of groups created in the Group Create Section or group, bus, and state machine names created in the project’s design files. State machine names are not eliminated during logic synthesis, and can be included in the Buried Section. However, a group or bus name from a design file can be included in a Vector File for a timing simulation only if all of its members have "survived" logic synthesis. To check which nodes and groups still exist in the synthesized project, use the Simulator’s Initialize command to list nodes and groups.

You can avoid the effort of typing full hierarchical node names by using probes in the input design file(s) for the project. Since each probe name is unique, it can be used instead of the full hierarchical node name.

Groups listed in the Buried Section are displayed as groups in the SCF.

See also:

Differences from MAX+PLUS (DOS) Vector File Syntax

Overriding the Current Radix

Punctuation, White Space & Comments


Example: Buried Section (Vector File)
Sample Buried Section

BURIED nodeQA0 nodeQA1 nodeQB0 nodeQB1;


Example: Buried and Pattern Sections (Vector File)
Using Buried Sections with Pattern Sections

In this example, the first Buried Section establishes A1 and A2 as buried nodes for the first and second Pattern Sections, while the second Buried Section defines A1 and B1 as buried nodes for the third Pattern Section. To use A1 as an buried node for the third Pattern Section, you must relist it in the Buried Section preceding the Pattern Section, since the addition of a Buried Section clears data from all previous Buried Sections.

BURIED A1 A2;

START 0;

STOP 25;

PATTERN	% Pattern Section 1 with buried nodes A1 and A2 %

0   0   0

0   0   1;

START 26;

STOP 50;

PATTERN	% Pattern Section 2 with buried nodes A1 and A2 %

0   1   0

1   0   0;

BURIED A1 B1;

START 51;

STOP 100;

PATTERN	% Pattern Section 3 with buried nodes A1 and B1 %

1   1   0

0   1   1;


Combinatorial Section (Vector File)

Specifies that a node declared in a preceding Outputs Section or Buried Section is driven by combinatorial logic.

The optional Combinatorial Section is used only for waveform design entry, and is recognized only if the Vector File is converted into a WDF with the Waveform Editor’s Import Vector File command.

The Combinatorial Section consists of the keyword COMB, followed by the name of a node declared in a preceding Outputs or Buried Section. The Combinatorial Section ends with a semicolon (;). Example

The Combinatorial Section is equivalent to selecting the Combinatorial node type when you create a node with the Waveform Editor’s Enter Node command.

See also:

Punctuation, White Space & Comments


Example: Combinatorial Section (Vector File)
Sample Combinatorial Section

OUTPUTS IGN-LITE;

COMB IGN-LITE;      % combinatorial output %


Machine Section (Vector File)

Specifies that a node declared in a preceding Inputs Section, Outputs Section, or Buried Section is driven by state machine logic, and specifies the secondary inputs to the state machine.

The optional Machine Section is used only for waveform design entry, and is recognized only if the Vector File is converted into a WDF with the Waveform Editor’s Import Vector File command.

The Machine Section consists of the keyword MACHINE, followed by the name of a node declared in a preceding Inputs, Outputs, or Buried Section. Secondary inputs are defined with the CLOCK, PRESET, and RESET keywords, which are separated by an equal sign (=) from the name of the Clock, Preset, and Reset inputs to the node. The Machine Section ends with a semicolon (;). Example

The Machine Section is equivalent to selecting the Machine node type when you create a node with the Waveform Editor’s Enter Node command.

See also:

Punctuation, White Space & Comments


Example: Machine Section (Vector File)
Sample Machine Section

OUTPUTS OUT-MACHINE;

MACHINE OUT-MACHINE CLOCK = CLK PRESET = EX1 RESET = EX8;


Registered Section (Vector File)

Specifies that a node declared in a preceding Outputs Section or Buried Section is driven by a register, and specifies the secondary inputs to the register.

The optional Registered Section is is used only for waveform design entry, and recognized only if the Vector File is converted into a WDF with the Waveform Editor’s Import Vector File command.

The Registered Section consists of the keyword REGISTER, followed by the name of a node declared in a preceding Outputs or Buried Section. The Registered Section ends with a semicolon (;). Secondary inputs are defined with the CLOCK, PRESET, and RESET keywords, which are separated by an equal sign (=) from the name of the Clock, Preset, and Reset inputs to the node. Example

The Registered Section is equivalent to selecting the Registered node type when you create a node with the Waveform Editor’s Enter Node command.

See also:

Punctuation, White Space & Comments


Example: Registered Section (Vector File)
Sample Registered Section

BURIED NEWREG;

REGISTER NEWREG CLOCK = CLK PRESET = EX1 RESET = EX8;


Differences from MAX+PLUS (DOS) Vector File Syntax

The format of the Vector File used in MAX+PLUS II differs in several important ways from the format of the MAX+PLUS (DOS version) Vector File:

1.	Buried nodes and probes are now listed in the Buried Section of the Vector File, rather than in the Outputs Section. You can still use Vector Files created for MAX+PLUS (DOS), with the following results:

The Message Processor issues a warning if a node belongs in the Buried Section, but is in the Outputs Section. However, the Simulator still simulates buried nodes and probes correctly if they are listed in the Outputs Section.

Any node listed in the Outputs Section of the Vector File is displayed as an output node (with the I/O type shown in the node handle) in the SCF that is automatically created for the Vector File. Therefore, buried nodes and probes do not show up in the SCF as buried nodes, but as output nodes.

2.	If the Vector File contains multiple Start and Stop Sections, the time periods that they represent can overlap. In MAX+PLUS (DOS), each Start Section must be later than the most recent stop time given in the preceding Stop Section.

3.	If relative time vector patterns are used in the Pattern Section, the Stop Section is required. If there is no Stop Section and absolute time vector patterns are given in the Pattern Section, the time of the last vector pattern becomes the stop time. The Stop Section is always optional in MAX+PLUS (DOS).

4.	The following new sections have been added to allow you to specify the node type and secondary inputs of nodes in a Vector File that is imported into the Waveform Editor to become a WDF for waveform design entry:

Combinatorial Section

Machine Section

Registered Section


Pattern Section (Vector File)

In a Vector File used for simulation, specifies the required input vectors and optional expected output logic levels. In a Vector File used for waveform design entry, this section specifies all input vectors, optional buried nodes, and the desired outputs.

A Pattern Section uses data from all preceding Inputs, Outputs, and Buried Sections. The addition of a new Inputs, Outputs, and/or Buried Section  clears all previous data of the same type, e.g., the nodes in a new Inputs Section replace the data in the preceding Inputs Section. To use nodes that were listed in previous Inputs, Outputs, and Buried Sections, you must redeclare these nodes in new Inputs, Outputs, and Buried Sections to provide additional vectors in another Pattern Section. Example

The Pattern Section must specify the input vectors for each node and group name given in all Inputs Sections that follow a previous Pattern Section.

If a logic level is assigned to a group, the logic level is truncated or sign-extended to match the size of the group.

In a Vector File used for simulation, the Pattern Section can optionally include expected logic levels for the nodes and groups in the Outputs Section(s) and Buried Section(s) that follow a previous Pattern Section. If they are included, expected logic levels must be defined for both sections, and all output logic levels must be listed before buried logic levels. During simulation, the output and buried logic levels in the SCF generated for the Vector File are updated or are preserved and compared to other outputs according to SCF output overwriting rules.

In a Vector File used for waveform design entry, the Pattern Section includes logic levels for each node and group name in the Outputs Section(s) and Buried Section(s) that follow a previous Pattern Section. All output logic levels must be listed before buried logic levels.

The Pattern Section begins with the keyword PATTERN, followed by vector patterns, and terminated with a semicolon (;). Vectors can be expressed in either or both of the following formats:

Relative time vector patterns

Absolute time vector patterns

See also:

Functional Testing with the SCF, Vector File, or Programming File

Punctuation, White Space & Comments


Relative Time Vector Patterns (Vector File)

Relative time vector patterns in the Pattern Section consist of a table of logic levels. State names that were defined in the project’s design files may also be used for a group that consists of state machine bits (i.e., for a group with the same name as the state machine). Group values are interpreted according to the radix specified in the Radix Section.

A set of vectors that contains one input vector value for each node and group in the Inputs Sections is required; if output and buried values are included, the same is true for each node and group in the Outputs and Buried Sections. Each set of input vectors must be separated from output and buried values by an equals symbol (=).

If a logic level is assigned to a group, the logic level is truncated or sign-extended to match the size of the group.

For greatest readability, each row in the table should contain a complete set of vectors (and optional output values) for each each node or group in the Inputs (or Outputs and Buried) Section. The output and buried logic levels are listed together, with all buried values after the output values. Example

You can enter a vector pattern that specifies only the outputs and/or buried values if the first "value" in each row is =. Example

Relative time vector patterns consist of logic levels only. The first set of vector values is applied at the time specified in the most recent Start Section. Subsequent sets of vectors are applied at the interval specified in the most recent Interval Section. If no Interval Section is present, the interval time defaults to 1 ns. If all sets of vectors have been applied before the stop time specified in the most recent Stop Section, the entire table of relative time vector patterns is repeated until the stop time is reached. Example

The Vector File can contain multiple Start and Stop Sections that represent overlapping time periods. You must ensure that different vector patterns do not apply to the same time period.

See also:

Absolute Time Vector Patterns

Functional Testing with the SCF, Vector File, or Programming File

Overriding the Current Radix

Punctuation, White Space & Comments

Simulating Bidirectional Pins


Example: Relative Time Vector Pattern (Vector File)
Sample Relative Time Vector Pattern

GROUP CREATE Dgroup = D1 D2 D3;

INPUTS Dgroup nodea nodeb nodec;

OUTPUTS nodex nodey;

BURIED nodez;

INTERVAL 100ns;

STOP 1000ns;

PATTERN

% relative time vector pattern

  group radix is HEX (default) %

1 0 1 0 = 1 0 1  % last value is for nodez %

2 0 1 1 = 1 0 0

3 0 0 1 = 0 1 1;


Example: Relative Time Vector Pattern with expected outputs only (Vector File)
Sample Relative Time Vector Pattern with Expected Outputs Only

PATTERN

% relative time vector pattern  %

% with output logic levels only %

= 0  0  0

= 0  0  1

= 0  1  0

= 1  1  1;


Example: Three-Bit Binary Counter -- Relative vs. Absolute Time Patterns (Vector File)
Three-Bit Binary Counter

Relative Time Pattern:	Absolute Time Pattern:

UNIT ns;	UNIT ns;

START 0;

STOP 1000;	% equivalent to relative

INTERVAL 100;	  time pattern %

INPUTS A1 A2 A3;	INPUTS A1 A2 A3;

PATTERN	PATTERN

0   0   0	0>    0  0  0

0   0   1	100>  0  0  1

0   1   0	200>  0  1  0

0   1   1	300>  0  1  1

1   0   0	400>  1  0  0

1   0   1	500>  1  0  1

1   1   0	600>  1  1  0

1   1   1;	700>  1  1  1

% repeat until 1000 ns %	800>  0  0  0

900>  0  0  1

1000> X  X  X;

% last pattern is %

% stop time %


Absolute Time Vector Patterns (Vector File)

Absolute time vector patterns in the Pattern Section consist of a table of logic levels. State names that were defined in the project’s design files may also be used for a group that consists of state machine bits (i.e., for a group with the same name as the state machine). Group values are interpreted according to the radix specified in the Radix Section.

The absolute time format specifies the exact time when a set of vectors should be applied. Each set of vector values is preceded with a time value and a greater than symbol (>) The time unit used to interpret the time value is specified in the Unit Section. If no Unit Section is included, the unit defaults to ns. Example

A set of vectors that contains one input vector value for each node and group in the Inputs Sections is required; if output and buried values are included, the same is true for each node and group in the Outputs and Buried Sections. Each set of input vectors must be separated from output and buried values by an equals symbol (=). Example

If a logic level is assigned to a group, the logic level is truncated or sign-extended to match the size of the group.

You can enter a vector pattern that specifies only the outputs and/or buried values if the first "value" in each row is =. Example

When absolute time vector patterns are used, you do not need to create Start or Interval Sections. If these sections exist, they are ignored. A Stop Section is optional: if no Stop Section is included, the time of the last vector pattern becomes the stop time. Example

See also:

Functional Testing with the SCF, Vector File, or Programming File

Overriding the Current Radix

Punctuation, White Space & Comments

Relative Time Vector Patterns

Simulating Bidirectional Pins


Example: Absolute Time Vector Pattern (Vector File)
Sample Absolute Time Vector Pattern

GROUP CREATE Dgroup = D1 D2 D3;

INPUTS Dgroup nodea nodeb nodec;

OUTPUTS nodex nodey;

BURIED nodez;

PATTERN

% absolute time vector pattern %

% group radix is HEX (default) %

% time unit is NS (default)    %

 300> 1 0 1 0 = 1 0 1  % last value is for nodez %

 600> 2 0 1 1 = 1 0 0

 900> 3 0 0 1 = 0 1 1

1200> X X X X = X X X; % file ends at 1200 ns    %


Example: Absolute Time Vector Pattern with Expected Outputs Only  (Vector File)
Sample Absolute Time Vector Pattern with Expected Outputs Only

PATTERN

% absolute time vector pattern  %

% with output logic levels only %

1000> = 0  0  0

2000> = 0  0  1

3000> = 0  1  0

4000> = 1  1  1;


Example: Three-Bit Binary Counter -- Absolute vs. Relative Time Patterns (Vector File)
Three-Bit Binary Counter

Absolute Time Pattern:	Relative Time Pattern:

UNIT ns;	UNIT ns;

START 0;

% equivalent to relative	STOP 1000;

  time pattern %	INTERVAL 100;

INPUTS A1 A2 A3;	INPUTS A1 A2 A3;

PATTERN	PATTERN

0>    0  0  0	0   0   0

100>  0  0  1	0   0   1

200>  0  1  0	0   1   0

300>  0  1  1	0   1   1

400>  1  0  0	1   0   0

500>  1  0  1	1   0   1

600>  1  1  0	1   1   0

700>  1  1  1	1   1   1;

800>  0  0  0	% repeat until 1000 ns %

900>  0  0  1

1000> X  X  X;

% last pattern is %

% stop time %


Punctuation, White Space & Comments (Vector File)

The following general guidelines apply:

1.	Each section of the Vector File must be terminated with a semicolon (;).

2.	Case is not significant in names or keywords: you can mix upper- and lowercase letters freely.

3.	White space is defined as blank spaces, tabs, carriage returns, and line feeds. You can insert white space between syntax elements to enhance readability, except in the following cases:

Within any name, including hierarchical node names

Between a group name and \BIN, \DEC, \HEX, or \OCT in the Inputs, Outputs, or Buried Section

Between a time value and a time unit in the Start, Stop, Interval, or Pattern Section

4.	Comments must be enclosed within percent symbols (%). They can contain any printable character except the % delimiter. You can insert comments wherever white space is allowed.

See also:

Hierarchical Node & Symbol Names

Logic Levels


Overriding the Current Radix (Vector & Command Files)

The current radix is specified in the Radix Section of a Vector File, or with a RADIX command in a Command File. If a radix is not specified in the file, the default is hexadecimal. The radix determines how logic levels are interpreted for a group. The radix also determines how group logic levels are displayed in an SCF or WDF generated from a Vector File.

You can temporarily override the current or default radix by appending a radix suffix to a group name:

Suffix:	Action:

\BIN	Specifies a binary radix for the group.

\DEC	Specifies a decimal radix for the group.

\HEX	Specifies a hexadecimal radix for the group.

\OCT	Specifies an octal radix for the group.

Example


Example: Radix Override (Vector File)
Sample radix override

groupname\DEC  % forces decimal radix %


Time Units (Vector & Command Files)

A time value is always followed immediately (i.e., with no space in between) by a time unit. Legal time units are:

Time Unit:	Abbreviation for:

ns	nanosecond

ms	millisecond

us	microsecond

s	second

If you do not enter a time unit, ns is assumed as the default. In a Vector File, the Unit Section determines the time unit for the file unless it is overridden in the Start, Stop, or Interval Section.


Logic Levels (Vector & Command Files)

Legal characters for node and group logic levels are listed below.

Character:	Logic Level:

0	Logic low (GND)

1	Logic high (VCC)

X	Undefined/Don’t Care (not permitted for initialization)

Z	High impedance (no input to pin); e.g., used for the "output" part of a bidirectional pin when the "input" part of the pin is driving in.

0-9, A­F	Used for groups and interpreted according to the current radix as binary, decimal, hexadecimal, or octal values. The MSB is first; the LSB is last.

See also:

Functional Testing with the SCF, Vector File, or Programming File

Overriding the Current Radix

Punctuation, White Space & Comments


Breakpoint Operators (Command File)

The following breakpoint operators are used to compare node, group, and Simulation Time values in a breakpoint conditions list:

Operator:	Definition:

=	equal

!=	not equal

>	greater than

<	less than

<=	less than or equal to

>=	greater than or equal to

>->	goes to/transition

See also:

BREAK CREATE (Command File)

BREAK DELETE (Command File)

BREAK LIST (Command File)

Breakpoint Command


Wildcard Characters (Command File)

Characters used in pattern matching, to list names in a Command File. The asterisk (*) represents zero or more characters; the question mark (?) represents a single character.


Comments (Command File)

In MAX+PLUS II text files, a comment is any string of characters enclosed in percent symbols (%). You can insert comments in a Command File between the command keywords and the End-of-Line character. Comments can span multiple lines.


Commands that Appear Only in History & Log Files

Some interactive-mode commands and options in the History File and Log File are enclosed within percent symbols (%). The following functions are "commented out" so that the Simulator will not attempt to execute them if the file is reused as a Command File for batch-mode simulation:

% LOG CREATE %

% LOG ON %

% LOG OFF %

% USE DEVICE %


Do not use the Backslash (\) with the ECHO command

The ECHO command allows you to echo a text string, enclosed in double quotation marks ("), that must start and end on the same line. You cannot insert a backslash (\) to continue this type of quoted text string on another line.


Command File--Context-Sensitive Help
Command File Context-Sensitive Help

Context-sensitive help is available for the Command File command keywords and punctuation listed below. Context-sensitive help is still available if a keyword has been abbreviated to as few as the first three letters.

\ (backslash)	BREAK CREATE	NODE LIST

\BIN	BREAK DELETE	NS

\DEC	BREAK LIST	OSCILLATION

\HEX	CHANNEL	QUIT

\OCT	CHECK OFF	RADIX BINARY

: (colon)	CHECK ON	RADIX DECIMAL

=(equals)	COMMAND	RADIX HEXADECIMAL

>-> (goes to)	ECHO	RADIX OCTAL

> (greater than)	GLITCH	RESET

>= (greater than or equal to)	GROUP INIT	S

!= (not equal to)	GROUP LIST	SETUP OFF

< (less than)	HISTORY CREATE	SETUP ON

<= (less than or equal to)	HISTORY OFF	SIMULATE

% (percent)	HISTORY ON	TABLE

. (period)	INIT READ	US

| (vertical bar)	INIT WRITE	VECTOR

0 through 9 logic levels	MS	X logic level

A through F logic levels	NODE INIT	Z logic level

See also:

Command File Format

Commands Available Only in MAX+PLUS (DOS)


Commands Available Only in DOS MAX+PLUS
Commands Available Only in MAX+PLUS (DOS)

MAX+PLUS (DOS version) includes several Command File commands that do not exist in the MAX+PLUS II software. Although these commands can still be used in Command Files, most will not be executed, and the Message Processor will issue warning messages. Therefore, Altera recommends that you use only the new commands and options listed below to implement the corresponding functions.

Old Command:	New Implementation:

BREAK CREATE	When a breakpoint is reached, you can only choose Start to continue simulation, or Stop to end it. The breakpoint command list that was supported in MAX+PLUS (DOS) is not available.

CLEAR	Not available. However, RESET causes the Simulator to revert to default node and group initialization values.

CONTINUE	Not available.

DELAY	Delay prediction functions are provided in the Timing Analyzer and the Graphic, Text, and Waveform Editors.

FORCE LIST	Not available. See FORCE STICK.

FORCE STICK	Replaced with NODE INIT and GROUP INIT.

FORCE UNSTICK	Not available. See FORCE STICK.

GROUP CREATE	Groups are now created in an SCF or a Vector File.

GROUP VALUE	Now an implicit part of and executed as GROUP LIST.

LOG CREATE	A Log File is created only in interactive-mode simulation, with the Inputs/Outputs command. However, LOG CREATE does appear as a comment in the History File if you create a Log File while command history is being recorded.

LOG ON	Not available. See LOG CREATE.

LOG OFF	Not available. See LOG CREATE.

NETLIST	The project name is changed only in interactive-mode simulation, with the Project Name command.

NODE VALUE	Now an implicit part of and executed as NODE LIST.

SAVE READ	Replaced with INIT READ.

SAVE WRITE	Replaced with INIT WRITE.

STATUS	Not available.

WAVEFORM	Not available. The Waveform Editor can be invoked only during interactive use of MAX+PLUS II, not from the Simulator or from a Command File.


Select the Appropriate BREAK Command

For help, choose a command:

BREAK CREATE

BREAK DELETE

BREAK LIST


Select the Appropriate CREATE Command

For help, choose a command:

BREAK CREATE

HISTORY CREATE

See also:

GROUP CREATE and LOG CREATE in Commands Available Only in MAX+PLUS (DOS)


Select the Appropriate INITIALIZE Command

For help, choose a command:

GROUP INIT

INIT READ

INIT WRITE

NODE INIT


Select the Appropriate LIST Command

For help, choose a command:

BREAK LIST

GROUP LIST

NODE LIST

See also:

FORCE LIST in Commands Available Only in MAX+PLUS (DOS)


Select the Appropriate GROUP or NODE Command

For help, choose a command:

GROUP INIT

GROUP LIST

NODE INIT

NODE LIST

See also:

GROUP CREATE, GROUP VALUE, and NODE VALUE in Commands Available Only in MAX+PLUS (DOS)


BREAK CREATE Command (Command File)

BNF Syntax:	BREAK CREATE <breakpoint name> = (<conditions list>)

BREAK CREATE allows you to enter a set of node value, group value, and/or time conditions that define a breakpoint. When these conditions are fulfilled, the Simulator pauses and reports that a breakpoint has been reached.

The <breakpoint name> can contain up to 32 name characters and is followed by an equal sign (=).

The <conditions list> is a set of comparisons in a format similar to a Boolean expression. The list must be enclosed in parentheses(); conditions within the list must be separated with ampersands (&). It has the following syntax:

<conditions list>::= <LHS> <operator> <RHS> {& <LHS> <operator> <RHS>}

<LHS> ::= .time | <node name> | <group name>

<RHS> ::= <logic level> | <time value>[<time unit>]

<operator> ::=	breakpoint operator

A group <logic level> is interpreted according to the radix specified with the most recent RADIX command.

If the <conditions list> depends on the .time variable, the Simulator detects the breakpoint at the first transition after .time has been reached. Therefore, you must always use the <= or >= operator rather than = when establishing conditions for .time. The optional <time unit>, must immediately follow (i.e., with no space in between) a <time value>. If you do not enter a time unit, ns is the default. Example

When the Simulator pauses at the breakpoint, you can choose Start to resume simulation or Stop to end it.

BREAK CREATE is equivalent to the breakpoint creation functions in the interactive-mode Breakpoint dialog box.

See also:

BREAK DELETE (Command File)

Overriding the Current Radix


Example: BREAK CREATE Command (Command File)
BREAK CREATE Example

BREAK CREATE FIRSTBREAK = (CLOCK >-> 1 & OUTPUT1 != 0 & .time <= 1us)

The above example creates the breakpoint called FIRSTBREAK, which is hit when CLOCK has a transition to a high logic level, OUTPUT1 is not low, and the current simulation time is less than 1 us.


BREAK DELETE & BREAK LIST Commands (Command File)

BNF Syntax:	BREAK DELETE <breakpoint list>

BREAK LIST <breakpoint list>

BREAK DELETE deletes one or more breakpoints. The conditions list associated with each breakpoint is also deleted.

BREAK LIST shows the status of one or more breakpoints. For each specified breakpoint, when history logging is turned on, the History File lists whether the breakpoint has been hit, and shows the associated conditions list.

The <breakpoint list> may contain one or more breakpoint names, separated by spaces or tabs; or a text string that includes wildcard characters. The breakpoint name and text string can contain up to 32 name characters.

BREAK DELETE and BREAK LIST are equivalent to the Delete button and Existing Breakpoints box in the interactive-mode Breakpoint dialog box.

See also:

BREAK CREATE (Command File)

HISTORY CREATE, ON & OFF (Command File)


CHANNEL Command (Command File)

BNF Syntax:	CHANNEL [<pathname>][<filename>][<extension>]

CHANNEL specifies a Simulator Channel File as the source of input vectors for simulation. The <pathname>, <filename>, and an <extension> are optional; if none are entered, the current directory, project name, and the extension .scf are assumed.

The Simulator looks for an SCF or Vector File when you execute the SIMULATE command. It automatically loads the SCF or Vector File in the project directory with the same filename as the project. Therefore, this command is required only if your input vectors are in an SCF with a different filename. The SCF can contain output waveforms of any type: expected outputs, outputs from other simulations, or actual functional device outputs.

CHANNEL can be used repeatedly, with each new command indicating a change in the source of vector definitions (i.e., a different SCF). Each time the Simulator encounters the CHANNEL command, it closes the current SCF (if one exists) and opens the requested file.

CHANNEL is equivalent to the Input (.scf or .vec) option in the interactive-mode Inputs/Outputs dialog box.


CHECK ON & OFF Commands (Command File)

BNF Syntax:	CHECK ON

CHECK OFF

CHECK ON instructs the Simulator to monitor the logic levels of all simulated nodes and groups. During simulation, the Simulator checks whether simulated outputs differ functionally from the outputs given in the input Simulator Channel File or the SCF generated automatically for a Vector File. The SCF or Vector File can contain output waveforms of any type: expected outputs, outputs from other simulations, or actual functional device outputs.

CHECK OFF turns output monitoring off.

When you use CHECK ON, the output logic levels generated by the Simulator are not saved in the SCF. Instead, the Simulator automatically executes the Waveform Editor’s Compare command to superimpose the simulated outputs on the SCF outputs when the SCF is opened. The Compare command is also automatically executed if the SCF is left open during simulation. Outputs are compared according to functional comparison rules.

When you use CHECK ON and the input vectors are in a Vector File rather than an SCF, the file must include expected output logic levels for all input logic levels for each time period that you simulate. If it does not, the Simulator assumes X (undefined) logic levels for the outputs. When an output has an X logic level, the Simulator ignores it and therefore does not report that expected outputs do not match simulated outputs. To ensure meaningful simulation results, you can open the SCF that is automatically generated for the Vector File, and examine it to ensure that 0, 1, and Z (but not X) expected output node waveforms exist for the period you wish to simulate.

CHECK ON and CHECK OFF are equivalent to the interactive-mode Check Outputs option.


COMMAND Command (Command File)

BNF Syntax:	COMMAND [<pathname>][<filename>][<extension>]

COMMAND directs the Simulator to take command input from the specified Command File. The <pathname>,  <filename>, and an <extension> are optional; if none are entered, the current directory, project name, and the extension .cmd are assumed. You can execute a Command File with a non-default extension (e.g., if you wish to reuse a Log File) by specifying the appropriate extension.

If the Command File contains a QUIT command, the Simulator reads the file up to the QUIT command, closes it, and then returns to take command input from the preceding file. Any number of nesting levels is allowed. If the file does not contain a QUIT command, the Simulator reads the entire file and then treats the end-of-file as an implicit QUIT command.

COMMAND is equivalent to the interactive-mode Execute Command File command.


ECHO Command (Command File)

BNF Syntax:	ECHO <echo variables> {<echo variables>}

If history logging is turned on, ECHO writes one or more of the following to the History File: a text string, the current logic level of a node or group, or the current time.

Each <echo variable> can consist of:

An ECHO command text string

A node name or group name

.time variable

Example

A group logic level is listed according to the radix specified with the most recent RADIX command.

See also:

HISTORY CREATE, ON & OFF (Command File)

Overriding the Current Radix


Example: ECHO Command (Command File)
Sample ECHO command

ECHO "Value of RESET is " RESET

The command line above prints "Value of RESET is 1."

ECHO "Current time is " .time

The command line above prints "Current time is 10ns" when the simulation time is 10 ns.


ECHO command text string

The ECHO command text string is a string of text enclosed in double quotation marks (").

It can contain any printable ASCII character except the percent symbol (%). The text string must start and end on the same line, i.e., you cannot insert a backslash (\) to continue the text string on another line.


ECHO Command Text String (Command File)

The ECHO command text string is a string of text enclosed in double quotation marks (").

It can contain any printable ASCII character except the percent symbol (%). The text string must start and end on the same line, i.e., you cannot insert a backslash (\) to continue the text string on another line.


GLITCH Command (Command File)

BNF Syntax:	GLITCH <time value>[<time unit>]

GLITCH instructs the Simulator to monitor the logic levels of all simulated nodes and groups for glitches (spikes), i.e., two or more logic level changes that occur within a period less than or equal to the specified time.

In functional simulation mode, GLITCH checks only for nil-time glitches and you cannot specify a glitch interval. In timing simulation mode, you can set the time interval that defines a glitch. The optional <time unit> must immediately follow (i.e., with no space in between) the <time value>; the default time unit is ns. The minimum glitch value for a timing simulation is 0.2ns. If the specified value is 0, glitch monitoring is turned off.

GLITCH can increase the time it takes to simulate a project. You may wish to monitor the project for glitches during specific simulation periods, rather than at all times.

GLITCH is equivalent to the interactive-mode Glitch option.


GROUP INIT & NODE INIT Commands (Command File)

BNF Syntax:	GROUP INIT <group list> = <logic level>

NODE INIT <node list> = <logic level>

GROUP INIT initializes one or more groups in the current Simulator Netlist File and Simulator Channel File to the specified logic level, or to an equivalent state name for a group that represents a state machine. (An SCF is generated automatically for a Vector File.) The logic level for the <group list> is interpreted according to the radix specified with the most recent RADIX command.

NODE INIT initializes one or more nodes in the current SNF or to the specified logic level.

The <group list> or <node list> may consist of a text string that includes wildcard characters, or one or more node or group names. A state machine name represents a group of state bits and can be included in GROUP INIT to initialize the state bit logic levels.

By default, all register outputs are initialized to 0 and pin inputs are initialized to the first logic level provided in the current SCF. GROUP INIT and NODE INIT are typically used to initialize the values of register or combinatorial logic outputs to non-default values. For example, you can initialize the output of a register or combinatorial logic that feeds registers.

You can initialize input nodes and groups only if they are not included in the SCF or Vector File for the project. SCF or Vector File values always have precedence over initialized values.

GROUP INIT and NODE INIT are equivalent to the Initialize button in the interactive-mode Initialize dialog box.

See also:

Hierarchical Node & Symbol Names

INIT READ & INIT WRITE (Command File)

Overriding the Current Radix


GROUP LIST & NODE LIST Commands (Command File)

BNF Syntax:	GROUP LIST <group list>

NODE LIST <node list>

GROUP LIST displays a list of the members and current logic levels of one or more groups in the current Simulator Netlist File and Simulator Channel File, including groups that represent state machines. (An SCF is generated automatically for a Vector File.) A group logic level is listed according to the radix specified with the most recent RADIX command.

NODE LIST displays a list of the current logic levels, I/O types, and hierarchical node names of one or more nodes in the current SNF.

The <group list> or <node list> can consist of a text string that includes wildcard characters, or one or more node or group names. A state machine name represents a group of state bits and can be included in GROUP LIST to list the state bit logic levels.

GROUP LIST and NODE LIST are equivalent to the Type options and List button in the interactive-mode Initialize dialog box.

See also:

Hierarchical Node & Symbol Names

Overriding the Current Radix


HISTORY CREATE, ON & OFF Commands (Command File)

BNF Syntax:	HISTORY CREATE [<pathname>][<filename>][<extension>]

HISTORY ON

HISTORY OFF

HISTORY CREATE creates a new History File (.hst) that records all Simulator commands and command output, including option and button selections during interactive-mode simulation or commands from a Command File. Commands are recorded in the Command File format; command output is indented to distinguish it from the commands themselves.

The <filename> may contain up to eight name characters. The <pathname>, <filename>, and an <extension> are optional; if none are entered, the current directory, project name, and the extension .hst are assumed. Any existing file with the same filename and extension is overwritten.

HISTORY ON reopens an existing History File and appends additional command history to it. You can use HISTORY ON and HISTORY OFF as many times as you wish during a simulation session; however, only one file can be active (i.e., turned on) at a time.

HISTORY OFF stops command history logging that was started with HISTORY CREATE or HISTORY ON.

HISTORY CREATE, HISTORY ON, and HISTORY OFF are equivalent to the History (.hst) and New options in the interactive-mode Inputs/Outputs dialog box.


INIT READ & INIT WRITE Commands (Command File)

BNF Syntax:	INIT READ [<pathname>][<filename>][<extension>]

INIT WRITE [<pathname>][<filename>][<extension>]

INIT WRITE creates a Simulator Initialization File (.sif) that saves the current values of all nodes and groups. The SIF can also be created before simulation begins to save values initialized with NODE INIT and GROUP INIT.

INIT READ restores node and group values from an SIF saved with INIT WRITE.

The <filename> may contain up to eight name characters. The <pathname>, <filename>, and an <extension> are optional; if none are entered, the current directory, project name, and the extension .sif are assumed. INIT WRITE overwrites any existing file with the same filename and extension.

INIT READ and INIT WRITE are equivalent to the Restore Initialization and Save Initialization As dialog boxes opened with the Restore and Save buttons in the interactive-mode Initialize dialog box.


OSCILLATION Command (Command File)

BNF Syntax:	OSCILLATION <time value>[<time unit>]

OSCILLATION instructs the Simulator to monitor all simulated nodes and groups for logic levels that do not stabilize within the specified time period after the most recent input vector has been applied. The circuit is considered to have stabilized if all node and group logic levels have stopped changing before new input vectors become available.

In functional simulation mode, OSCILLATION is always on, and checks only for nil-period oscillation. In timing simulation mode, the optional <time unit> must immediately follow (i.e., with no space in between) a <time value>. If you do not enter a time unit, ns is the default. If the specified value is 0, oscillation monitoring is turned off.

If the Simulator finds nil-period oscillation during functional simulation, it opens a message box that allows you to skip to the next set of input vectors so that the oscillation will not continue indefinitely.

OSCILLATION can increase the time it takes to simulate a project. You may wish to monitor the project for oscillations during specific simulation periods, rather than at all times.

OSCILLATION is equivalent to the interactive-mode Oscillation option.


QUIT Command (Command File)

BNF Syntax:	QUIT

QUIT ends the batch-mode simulation, halting execution of any further commands in the current Command File.

If the Simulator encounters a QUIT command in a Command File, it closes the file and returns to take simulation command input from the Simulator menus, on-screen options, and buttons. If you are using nested Command Files, the Simulator returns to take command input from the "parent" Command File that called it.


RADIX BIN, DEC, HEX & OCT Commands (Command File)

BNF Syntax:	RADIX BINARY

RADIX DECIMAL

RADIX HEXADECIMAL

RADIX OCTAL

The RADIX commands set the radix for group logic levels used in subsequent Command File commands to binary, decimal, hexadecimal, or octal. If no radix is specified, the default is HEXADECIMAL. This radix affects how the Simulator interprets group information in the following commands:

BREAK CREATE

ECHO

GROUP INIT

GROUP LIST

RADIX commands are equivalent to the Radix options in the interactive-mode Breakpoint and Initialize dialog boxes.

See also

Overriding the Current Radix


RESET Command (Command File)

BNF Syntax:	RESET

RESET clears all node and group initialization values specified with the NODE INIT, GROUP INIT, or INIT READ commands.

Initialization is restored to default settings: all register outputs are initialized to 0, and pindef_pin inputs are initialized to the first vector value provided in the current Simulator Channel File. An SCF is generated automatically for a Vector File.

RESET is equivalent to the Reset button in the interactive-mode Initialize dialog box.


SETUP ON & OFF Commands (Command File)

BNF Syntax:	SETUP ON

SETUP OFF

SETUP ON instructs the Simulator to monitor all simulated nodes and groups for setup time and hold time violations. SETUP OFF turns setup and hold time violation monitoring off.

In functional simulation mode, violations occur if the setup or hold time is less than 0.1 ns. In timing simulation mode, setup and hold time violations are determined by the architecture of the device being simulated. When the Compiler creates the timing SNF for a project, it refers to the DMF for the target device for specific information on timing characteristics.

Using the Setup/Hold option in a functional simulation may be inappropriate for projects that contain counters or shift registers, since normal operation of these functional circuits will cause numerous setup and hold time violations.

SETUP ON can increase the time it takes to simulate a project. You may wish to monitor the project for setup and hold violations during specific simulation periods, rather than at all times.

SETUP ON and SETUP OFF are equivalent to the interactive-mode Setup/Hold option.


SIMULATE Command (Command File)

BNF Syntax:	SIMULATE <start time value>[<time unit>] TO <end time value>[<time unit>]

|	SIMULATE [<end time value>[<time unit>]]

|	SIMULATE [+]<relative time value>[<time unit>]

SIMULATE runs the Simulator for the specified time.

You can specify an end time for simulation relative to the current Simulation Time with the third syntax shown above. You can specify an exact start time and end time for simulation with the first syntax. In the second and third syntaxes, the start time is assumed to be the current simulation time. The end time is optional in the second syntax and defaults to the end time of the current Simulator Channel File. An SCF is generated automatically for a Vector File.

The optional <time unit> must immediately follow (i.e., with no space in between) a <time value>. If you specify a time past the end time of the SCF, the Simulator stops automatically at the end of the SCF.

Examples

SIMULATE is equivalent to a combination of the interactive-mode Start Time field, End Time field, and Start button.

Initialized node and group values are applied at the specified start time for simulation, i.e., a time period from 0 to the specified start time is ignored.


Example: SIMULATE Command (Command File)
Sample SIMULATE commands

SIMULATE 101 TO 123ns % absolute start and end time %

SIMULATE 123ns        % absolute end time %

SIMULATE +22ns        % relative time value %

All three examples are equivalent if the current time is 101 ns.


TABLE Command (Command File)

BNF Syntax:	TABLE [<pathname>][<filename>][<extension>]

TABLE creates an ASCII-format Table File that records all logic level transitions for all nodes and groups in the current Simulator Channel File. If input vectors for simulation are provided in a Vector File, the Simulator automatically generates an SCF from it. The Table File is a "snapshot" of the current SCF, which records all input vectors and output logic levels.

The <filename> can contain up to eight name characters. The <pathname>, <filename>, and an <extension> are optional; if none are entered, the current directory, project name, and the extension .tbl are assumed. Any existing file with the same filename and extension is overwritten.

TABLE is equivalent to the interactive-mode Create Table File command.

See also:

BREAK CREATE (Command File)


VECTOR Command (Command File)

BNF Syntax:	VECTOR [<pathname>][<filename>][<extension>]

VECTOR specifies a Vector File as the source of input vectors for simulation. The <pathname>, <filename>, and an <extension> are optional; if none are entered, the current directory, project name, and the extension .vec are assumed.

The Simulator looks for a Vector File or an Simulator Channel File when you execute the SIMULATE command. It automatically loads the newest Vector File or SCF in the project directory with the same filename as the project. Therefore, this command is required only if your input vectors are in a Vector File with a different filename. When you enter VECTOR, the Simulator automatically generates an SCF for the file. Expected output logic levels are optional. If they are included, they may be of any type: user-defined expected outputs, outputs from other simulations, or actual functional device outputs (e.g., in a Table File created during a previous simulation).

VECTOR can be used repeatedly, with each new command indicating a change in the source of vector definitions (i.e., a different Vector File). Each time the Simulator encounters the VECTOR command, it closes the current Vector File (if one exists) and opens the requested file.

VECTOR is equivalent to the Input (.scf or .vec) option in the interactive-mode Inputs/Outputs dialog box.


Vector File Format

The Vector File provides an ASCII text format for specifying simulation input conditions and the nodes to be simulated. A Vector File can also be used to create a Waveform Design File for waveform design entry.

A Vector File used for simulation or waveform design entry contains some or all of the sections listed below. Sections are listed in the order in which they are normally used. However, you can repeat any section to include a variety of input conditions within a single file.

Unit Section

Start Section

Stop Section

Interval Section

Group Create Section

Radix Section

Inputs Section

Outputs Section

Buried Section

Pattern Section

A Vector File used to create a WDF can contain the additional sections listed below. These sections are ignored if the Vector File is used for simulation.

Combinatorial Section

Machine Section

Registered Section

See also:

Creating a Waveform Design File

Differences from MAX+PLUS (DOS) Vector File Syntax

Overriding the Current Radix

Punctuation, White Space & Comments

Sample Vector File


Example: Vector File (.vec)
Sample Vector File (.vec)

The following example shows a sample Vector File, including a separate Pattern Section for optional expected output values.

% units default to ns %

START 0 ;

STOP 1000 ;

INTERVAL 100 ;

INPUTS CLOCK ;

PATTERN

0 1 ;           % relative vector values %

                % CLOCK ticks every 100 ns %

INPUTS DATAINX DATAINY ;

PATTERN         % test every combination of %

                % DATAINX and DATAINY %

0>    0 0

220>  1 0

320>  1 1       % absolute time vector values %

570>  0 1

720>  1 1

;

INPUTS CLEAR ;

PATTERN

0>    1

100>  0

;

OUTPUTS SERSUM CIN COUT ;

PATTERN         % check output at every Clock pulse %

= X X X

= 0 0 0         % relative time vector values %

= 0 0 0

= 1 0 0

= 0 0 1

= 0 0 1

= 0 1 1

= 0 1 1

= 1 1 1

= 1 1 1

= 1 1 1

= 1 1 1 ;


Command File Format

The Command File (with the extension .cmd) allows you to enter commands for batch-mode simulation. These commands duplicate the functions of the interactive-mode menu commands, options, and buttons.

Each command should be entered on a separate line. You must insert a backslash (\) immediately before the carriage return in commands that span lines. Exception

The Command File can contain any of the commands listed below. You can abbreviate each command to contain as few as the first three letters of each keyword. For example, you can abbreviate BREAK CREATE to BRE CRE.

BREAK CREATE	INIT WRITE

BREAK DELETE	NODE INIT

BREAK LIST	NODE LIST

CHANNEL	OSCILLATION

CHECK ON	QUIT

CHECK OFF	RADIX BINARY

COMMAND	RADIX DECIMAL

ECHO	RADIX HEXADECIMAL

GLITCH	RADIX OCTAL

GROUP INIT	RESET

GROUP LIST	SETUP ON

HISTORY CREATE	SETUP OFF

HISTORY ON	SIMULATE

HISTORY OFF	TABLE

INIT READ	VECTOR

See also:

Commands Available Only in MAX+PLUS (DOS)

Commands that Appear Only in History & Log Files

Sample Command File


Example: Command File (.cmd)
Sample Command File (.cmd)

HISTORY CREATE D:\MAX2WORK\TUTORIAL\T-BIRD.HST

CHANNEL D:\MAX2WORK\TUTORIAL\T-BIRD.SCF

NODE LIST *

GROUP LIST *

SETUP ON

OSCILLATION 50ns

BREAK CREATE RIGHTTEST = ( RIGHT=1 & RIGHT-I=1 & \

RIGHT-M=1 & RIGHT-O>->1 ) ( ECHO "ALL RIGHT TURN LIGHTS ON AT" \

.time )

SIMULATE 0 TO 8us

TABLE D:\MAX2WORK\TUTORIAL\T-BIRD.TBL

QUIT


Simulator Commands
Commands

For Help, choose a command name or dialog box name from the following list. Menu names are not included on the list.

About MAX+PLUS II	More Windows

Advanced Options	Move

AHDL	Name

Archive	New Features in This Release

Arrange Icons	New Window

Authorization Code	New

Auto Device Selection	Next

Back-Annotate Project	Open

Basic Tools	Pin/Location/Chip

Breakpoint	Primitives

Cascade	Probe

Classic & MAX Global Project Device Options	Procedures

Classic & MAX Individual Device Options	Programmer

Clear Project Assignments	Project 1, 2, 3, 4...

Clique	Project Archive

Close ( [image] and [image] menus)	Project Name

Color Palette	Project Save & Check

Commands	Project Save & Compile

Compiler	Project Save & Simulate

Connected Pins	Project Save, Compile & Simulate

Convert Obsolete Assignment Format	Project Set Project to Current File

Create Table File	READ.ME

Define Synthesis Style	Rename Chip

Device	Reset to Initial SNF Values

Devices & Adapters	Restore Initialization

Execute Command File	Restore

Exit MAX+PLUS II	Save & Check

Export Memory Content File	Save & Compile

FLEX 10K Global Project Device Options	Save & Simulate

FLEX 10K Individual Device Options	Save Initialization As

FLEX 8000 Global Project Device Options	Save Style As

FLEX 8000 Individual Device Options	Save, Compile & Simulate

Floorplan Editor	Search for Help on

Global Project Device Options	Search Node Database

Global Project Logic Synthesis 	Set Project to Current File

Global Project Timing Requirements	Shortcuts

Glossary	Show Status Bar

Golden Rules	Show Toolbar

Graphic Editor	Simulator

Hardware Setup	Simulator Help Basic Tools

Hierarchy Display	Simulator Help Commands

Hierarchy Project Top	Simulator Help Golden Rules

How to Use Help	Simulator Help Introduction

How to Use MAX+PLUS II Help	Simulator Help Procedures

Ignore Project Assignments	Simulator Help Shortcuts

Import Memory Content File	Simulator Help Table of Contents

Individual Logic Options	Size

Initialize Memory	Switch To

Initialize Node/Groups	Symbol Editor

Inputs/Outputs	Table of Contents

Introduction	Text Editor

Logic Options	Tile

Macrofunctions	Timing Analyzer

MAX+PLUS II Table of Contents	Timing Requirements

Maximize	User Libraries

Message Processor	VHDL

Messages	Waveform Editor

Minimize


Create Table File Command (Simulator)
Create Table File Command (File Menu)

Creates an ASCII-format Table File that records all logic level transitions for nodes and groups in the current Simulator Channel File.

The Table File is a snapshot of the current SCF, which records all input and output logic levels. Create Table File is especially useful for recording logic levels when simulation has been temporarily halted with the Pause button. The Table File format is identical to Vector File format.

Click Button 1 on any item in this dialog box for information on that item:

See also:

TABLE (Command File)

Creating a Table File


Create Table File dialog box is duplicated for WED and SIM.


Create Table File dialog box

Click Button 1 on any item in this dialog box for information on that item:


Execute Command File Command (Simulator)
Execute Command File Command (File Menu)

Executes a Command File that contains commands for batch-mode simulation.

Click Button 1 on any item in this dialog box for information on that item:

Execute Command File directs the Simulator to take command input from the specified file. The commands in the file are executed immediately. No other Simulator actions, except Pause or Stop, can be performed until all commands in the file have been executed.

Commands are entered in the Command File Format.

See also:

COMMAND (Command File)

Executing a Command File


Execute Command File dialog box

Click Button 1 on any item in this dialog box for information on that item:


Inputs/Outputs Command (Simulator)
Inputs/Outputs Command (File Menu)

Specifies the input and output files to be used for simulation, including the Vector File or Simulator Channel File that contains input vectors, and the Log File and History File for recording simulation outputs.

Click Button 1 on any item in this dialog box for information on that item:

The Simulator requires a Vector File or SCF to provide the input vectors that drive the simulation. If no file has been previously specified for the project, the Simulator automatically loads the newest Vector File or SCF in the project directory that has the same filename as the project. If a Vector File is specified, it is automatically converted into an SCF before simulation begins. Inputs/Outputs also allows you to specify an older Vector File or SCF with the same filename as the project.

If you plan to simulate with the Check Outputs option turned on, the input Vector File or SCF should include actual or expected device outputs.

Shortcut:	Double-click Button 1 on the Simulation Input field.

See also:

CHANNEL (Command File)

HISTORY CREATE, ON & OFF (Command File)

Logging Simulation Commands

Output Monitoring Requirements for the SCF or Vector File

Recording Simulation Commands & Output History

Specifying the Source of Input Vectors

VECTOR (Command File)


Inputs/Outputs dialog box

Click Button 1 on any item in this dialog box for information on that item:


Vector Files

Input (.scf or .vec)	Specifies the source of input vectors as an SCF or Vector File. The Input (.scf or .vec) box displays <project name>.scf by default, unless a different filename was specified previously. You can also specify a Table File, which has the same format as a Vector File.

Output	Shows the SCF where the simulation outputs are saved. This file always has the same filename as the input file.


Output Files

History (.hst)	Specifies the History File to be used to record simulation commands and their output.

Log (.log)	Specifies the Log File to be used to record simulation commands.

New	Overwrites an existing specified History or Log File, if any. If New is turned off, and the specified file exists, simulation history or commands are appended to the file.

The filename <project name>.hst or  <project name>.log is displayed by default, unless a different filename was specified previously.


Files

Lists all files in the current directory that match the filename extension of the selected input or output file types.

Selecting a name in the Files box copies it to the Input (.scf or .vec), History (.hst), or Log (.log) box, based on the filename extension. You can also type a text string that includes wildcard characters or a different filename extension in the Input (.scf or .vec), History (.hst), or Log (.log) box, and then choose OK to update the contents of the Files box with the filenames that match the new text string and extension.


Directory is

Displays the current directory. Files in the current directory are listed in the Files box.

You can type a different different absolute or relative pathname in the Input (.scf or .vec), History (.hst), or Log (.log) box and choose OK or double-click Button 1 on a name in the Directories box to change the current directory.


Directories

Lists all available disk drives and all subdirectories of the current directory.

You can type a different absolute or relative pathname in the Input (.scf or .vec), History (.hst), or Log (.log) box and choose OK or double-click Button 1 on a name in the Directories box to change the current directory.


Breakpoint Command (Simulator)
Breakpoint Command (Options Menu)

Creates one or more breakpoints, each of which consists of one or more node value, group value, and time conditions. When these conditions are fulfilled, the Simulator pauses during the simulation.

The Breakpoint command can create or edit breakpoint names and conditions.

Click Button 1 on any item in this dialog box for information on that item:

When the breakpoint conditions are fulfilled during simulation, the Simulator pauses and reports the time in a message box and in the Message Processor window. At the pause, you can choose Start to resume simulation.

See also:

BREAK CREATE (Command File)

BREAK DELETE & BREAK LIST (Command File)

Changing a Breakpoint

Creating a Breakpoint

Deleting a Breakpoint


Breakpoint dialog box

Click Button 1 on any item in this dialog box for information on that item:


Breakpoint Name

Specifies the breakpoint name. You can type a name with up to 32 name characters in the Breakpoint Name box or select an existing breakpoint name in the Existing Breakpoints box to copy it to the Breakpoint Name box.


Node/Group

Specifies the .time variable, a node name, or a group name.

You can type a name with up to 32 name characters or select a name from the drop-down list box that lists all nodes and groups in the project’s Simulator Netlist File and the Simulator Channel File. Typing all or part of a name brings it to the top of the list.

If Show All Node Name Synonyms is turned on, the Node/Group list box also lists all possible hierarchical node names for each node or group that match the text string in the Node/Group box. Synonyms are preceded by -> in the list.


Operator

Specifies a breakpoint operator for comparing the name or  .time variable shown in the Node/Group box to the logic level or time value in the Value box.


Value

Specifies a logic level or time value to be compared to the name or  .time variable shown in the Node/Group box. Group values are interpreted according to the current Radix. Any time value must be followed immediately (i.e., with no space in between) by a time unit; the default unit is ns.


Radix

Specifies the BIN (binary), DEC (decimal), HEX (hexadecimal), or OCT (octal) radix used to interpret and display the logic level in the Value box.


Add Condition

Adds a new condition entered in the Node/Group, Operator, and Value boxes to the list of conditions for the breakpoint shown in the Breakpoint Name box.


Delete Condition

Deletes the selected condition from the list of conditions for the breakpoint shown in the Breakpoint Name box.


Conditions List

Lists the condition(s) entered with Add Condition.


Add

Adds the breakpoint name shown in the Breakpoint Name box and its list of conditions to the Existing Breakpoints box.


Delete

Deletes one or more selected breakpoints from the Existing Breakpoints box.


Change

Saves changes to the list of conditions for the breakpoint selected in the Existing Breakpoints box. You can add or delete conditions for the current breakpoint with Add Condition and Delete Condition.


Enable

Reactivates one or more disabled breakpoints that are selected in the Existing Breakpoints box. Any breakpoint that is already enabled is marked with an asterisk (*) in the Existing Breakpoints box.


Disable

Disables (i.e., instructs the Simulator to ignore) one or more selected breakpoints in the Existing Breakpoints box. Disabled breakpoints have no asterisk (*) in the Existing Breakpoints box.


Show All Node Name Synonyms

Shows all possible hierarchical node names for each node or group in the Node/Group list box. Synonyms are preceded by -> in the list.


OK

Saves all breakpoints listed in the Existing Breakpoints box and closes the dialog box.


Existing Breakpoints

Shows all existing breakpoints and breakpoint conditions for the current project.


Initialize Nodes/Groups Command (Simulator)
Initialize Nodes/Groups Command (Initialize Menu)

Specifies initial logic levels for one or more nodes and/or groups.

Initialize Nodes/Groups allows you to change the initial logic levels of registered nodes and registered groups in the Simulator Netlist File for the project before you begin simulation. You can also specify an initial state name for a group that represents a state machine.

By default, all register outputs are initialized to 0 and pin inputs are initialized to the first logic level provided in the current SCF. Initialize Nodes/Groups is typically used to initialize the values of register or combinatorial logic outputs to non-default values. For example, you can initialize the output of a register or of combinatorial logic that feeds registers.

The Simulator defines the initial logic levels as follows:

Inputs are initialized to the values specified in the current SCF. Inputs that are not specified in the SCF remain at undefined (X) logic levels, unless you specify different values with the Initialize Nodes/Groups command.

Registers are initialized to a low (0) logic level, unless the register was initialized with another value or other initialization conditions cause the register to clear or preset asynchronously.

Click Button 1 on any item in this dialog box for information on that item:

See also:

GROUP INIT & NODE INIT (Command File)

GROUP LIST & NODE LIST (Command File)

Hierarchical Node & Symbol Names

INIT READ & INIT WRITE (Command File)

Initializing Node & Group Values

Initializing RAM/ROM Memory

Listing Node & Group Values

RADIX (Command File)

Resetting Node, Group & Memory Values to Initial SNF Values

Restoring Node, Group & Memory Values

Saving Node, Group & Memory Values


Initialize Nodes/Groups dialog box

Click Button 1 on any item in this dialog box for information on that item:


List

Lists the nodes and/or groups that match the text string in the Node/Group box and the selected Type options in the Nodes & Groups box.

If Show All Node Name Synonyms is turned on, the Nodes & Groups box also lists all possible hierarchical node names for each node or group that match the text string in the Node/Group box. Synonyms are preceded by -> in the list.


Value

Specifies an initial logic level or state name for one or more nodes and/or groups selected in the Nodes & Groups box.


Initialize

Changes the initial logic level (or state name) of the selected nodes and/or groups in the Nodes & Groups box to the logic level entered in the Value box.


Nodes & Groups

Displays the nodes and/or groups, including groups that represent state machines,in the current SNF that match the text string in the Node/Group box and the selected Type options. The Nodes & Groups box also lists the current logic levels of the nodes and groups.

You must choose List to display the node and group names. If Show All Node Name Synonyms is turned on, the Nodes & Groups box also lists all possible hierarchical node names for each node or group that match the text string in the Node/Group box. Synonyms are preceded by -> in the list.


Radix

Specifies the BIN (binary), DEC (decimal), HEX (hexadecimal), or OCT (octal) radix used to display the group values in the Nodes & Groups box and to interpret the initial logic levels entered in the Value box.


Show All Node Name Synonyms

Shows all possible hierarchical node names for each node or group in the Nodes & Groups box. Synonyms are preceded by -> in the list.


Type

Determines which types of nodes and/or groups are displayed in the Nodes & Groups list box. When you choose the List button, all nodes and/or groups matching the selected types are displayed. You can select one or more options or select all types to be listed.

Inputs	Lists all input nodes in the Nodes & Groups box.

Outputs	Lists all output nodes in the Nodes & Groups box.

Registered	Lists all buried registered nodes in the Nodes & Groups box.

Combinatorial	Lists all buried combinatorial nodes in the Nodes & Groups box.

Group	Lists all input, output, and buried groups in the Nodes & Groups box.

All	Turns on all type options, i.e., lists all types of nodes and groups in the Nodes & Groups box. Turning this option off deselects all other Type options.


Initialize Memory Command (Simulator)
Initialize Memory Command (Initialize Menu)

Specifies the initial content of a memory block (RAM or ROM); exports (i.e., saves) initialized address values to a Memory Initialization File (.mif) or Hexadecimal File (.hex) for future use; and retrieves (i.e., imports) saved initialized values from an MIF or HEX File.

Initialize Memory allows you to change the initial values for each memory address. You can also edit the radices used to display and interpret addresses and address values for the memory block.

Click Button 1 on any item in this dialog box for information on that item:

See also:

Hierarchical Node & Symbol Names

Exporting Memory Values

Importing Memory Values

Initializing RAM/ROM Memory

Resetting Node, Group & Memory Values to Initial SNF Values

Restoring Node, Group & Memory Values

Saving Node, Group & Memory Values


Initialize Memory dialog box

Click Button 1 on any item in this dialog box for information on that item:


Memory

Specifies the hierarchical name of the currently selected memory. You can select a different memory name from the drop-down list box.


Address

Lists the memory addresses for the memory currently displayed in the Memory field. The addresses are displayed with the radix selected in the Addr Radix box.


Value

Lists the memory values for memory currently displayed in the Memory field. Values are displayed as groups of memory words with the radix selected in the Value Radix box.

You can edit one value at a time or select multiple values to edit. You can also use the Initialize to 0’s or Initialize to 1’s button to change all of the selected value(s) to low or high logic levels, respectively.


Addr Radix

Specifies the BIN (binary), DEC (decimal), HEX (hexadecimal), or OCT (octal) radix used to display the memory addresses in the Address box.


Value Radix

Specifies the BIN (binary), DEC (decimal), HEX (hexadecimal), or OCT (octal) radix used to display and interpret the memory values in the Value box.


List One Address Per Line

Lists each memory address and its corresponding values on a separate line in the Address and Value boxes.


Memory Info

Depth	Specifies the depth of the memory currently displayed in the Memory field in memory words.

Width	Specifies the width of the memory currently displayed in the Memory field in memory bits..

Type	Specifies the type of memory (e.g., RAM).


Initialize to 0’s

Changes the initial logic level of the selected memory value(s) in the Value box to 0 (i.e., low).


Initialize to 1’s

Changes the initial logic level of the selected memory value(s) in the Value box to 1 (i.e., high).


Import File

Opens the Import Memory Content File dialog box, which allows you to import (i.e., load) data saved in Hexadecimal File (.hex) or Memory Initialization File (.mif) format.

The data in the imported file applies only to the memory displayed in the Memory field; if the project contains more than one memory, separate files are required to initialize each memory.


Export File

Opens the Export Memory Content File dialog box, which allows you to export (i.e., save) data in Hexadecimal File (.hex) or Memory Initialization File (.mif) format.

The data in theexported file applies only to the memory displayed in the Memory field; if the project contains more than one memory, separate files are required to initialize each memory.


Import Memory Content File Dialog Box (Simulator)
Import Memory Content File Dialog Box

Loads the data saved in a Hexadecimal File (.hex) or Memory Initialization File (.mif) into the Initialize Memory dialog box.

You open this dialog box by choosing the Import File button in the Initialize Memory dialog box.

Click Button 1 on any item in this dialog box for information on that item:

The data in the imported file applies only to the memory displayed in the Memory field; if the project contains more than one memory, separate files are required to initialize each memory.

You can export (i.e., save) the data in the Initialize Memory dialog box using the Export Memory Content File dialog box.

See also:

Importing Memory Values


Import Memory Content File dialog box

Click Button 1 on any item in this dialog box for information on that item:


Export Memory Content File Dialog Box (Simulator)
Export Memory Content File Dialog Box

Saves the data in the Initialize Memory dialog box  to a Hexadecimal File (.hex) or Memory Initialization File (.mif) for future use.

You open this dialog box by choosing the Export File button in the Initialize Memory dialog box.

Click Button 1 on any item in this dialog box for information on that item:

The data in the exported file applies only to the memory displayed in the Memory field; if the project contains more than one memory, separate files are required to initialize each memory.

You can import (i.e., load) data saved in Hexadecimal File or MIF format using the Import Memory Content File dialog box.

See also:

Exporting Memory Values


Export Memory Content File dialog box

Click Button 1 on any item in this dialog box for information on that item:


Save Initialization As Command (Simulator)
Save Initialization As Command (Initialize Menu)

Saves the current initialized node, group logic levels, and memory values entered in the Initialize Nodes/Groups and Initialize Memory dialog boxes to a Simulator Initialization File for future use.

Click Button 1 on any item in this dialog box for information on that item:

You can reuse the SIF to re-initialize node, group, or memory values using the Restore Initialization command.

See also:

INIT WRITE (Command File)

Saving Node, Group & Memory Values


Save Initialization dialog box
Save Initialization As dialog box

Click Button 1 on any item in this dialog box for information on that item:


Restore Initialization Command (Simulator)
Restore Initialization Command (Initialize Menu)

Restores the initialized node, group, and memory values from a Simulator Initialization File.

Click Button 1 on any item in this dialog box for information on that item:

Restore Initialization retrieves the initialized node and group values from a SIF created with the Save Initialization As command.

See also:

INIT READ (Command File)

Restoring Node, Group & Memory Values


Restore Initialization dialog box

Click Button 1 on any item in this dialog box for information on that item:


Reset to Initial SNF Values Command (Simulator)
Reset to Initial SNF Values Command (Initialize Menu)

Resets initial node, group, and memory values to the values stored in the Simulator Netlist File.

All register outputs are initialized to 0, and pin inputs are initialized to the first logic level provided in the current Simulator Channel File.

See also:

Resetting Node, Group & Memory Values to Initial SNF Values


Cut Command Shortcuts

Press Button 2 on a selection and choose Cut from the pop-up menu.

Type Ctrl+X or Shift+Del.

Choose [image] from the toolbar at the top of the window.


Flip Horizontal & Flip Vertical Command Shortcuts

Press Button 2 on a selection and choose Flip Horizontal or Flip Vertical from the pop-up menu.

Choose [image] or [image] from the toolbar at the top of the window.


Rotate Command Shortcuts

Press Button 2 on a selection and choose Rotate 90°, Rotate 180°, or Rotate 270° from the pop-up menu.


Find Node in Design File Command Shortcuts

(Floorplan Editor only) Press Button 2 on a node or pin and choose Find Node in Design File from the pop-up menu.

Type Ctrl+B.

Choose [image] from the toolbar at the top of the window.

The Button 2 and tool bar shortcuts for this command do not open the Find Node in Design File dialog box if an item is already selected; they immediately locate the selected item.


Delete Command Shortcuts

Press Button 2 on a selection and choose Delete from the pop-up menu.

Type Del or Backspace.


Fit in Window Command Shortcuts

Type Ctrl+W.

Choose [image] from the tool palette on the left side of the window.


Maximum Size Command Shortcuts

Type Ctrl+2.


Normal Size Command Shortcuts

Type Ctrl+1.


Line Style Command Shortcuts

Press Button 2 on a selection and choose the desired line style from the Line Style submenu on the pop-up menu.

Choose the desired line style in the [image] drop-down list box in the toolbar at the top of the window.


Align to Grid Command Shortcuts

Press Button 2 on one or more selected whole waveforms or waveform intervals and choose Align to Grid from the pop-up menu.

Type Ctrl+Y.

Choose [image] from the toolbar at the top of the window.


Snap to Grid Command Shortcuts

Choose [image] from the toolbar at the top of the window.


Show Grid Command Shortcuts

Type Ctrl+Shift+G.


Time Range Command Shortcuts

Choose [image] from the toolbar at the top of the window.


Overwrite State Name Command Shortcuts

Press Button 2 on a single selected whole waveform or waveform interval and choose Overwrite State Name from the pop-up menu.

Choose [image] from the tool palette on the left side of the window.


Insert State Name Command Shortcuts

Press Button 2 on a single selected waveform interval and choose Insert State Name from the pop-up menu.


Insert Node Command Shortcuts

Double-click Button 1 on a blank space in the node/group information area.

Press Button 2 on a selected waveform interval and choose Insert Node from the pop-up menu.


Enter Nodes from SNF Command Shortcuts

Press Button 2 in blank space that is not in the Value field or on a selection with the selection tool and choose Enter Nodes from SNF from the pop-up menu.


Edit Node Command Shortcuts

Double-click Button 1 in the node information area of an existing node.

Press Button 2 in the node information area of an existing node and choose Edit Node from the pop-up menu.


Ungroup Command Shortcuts

Press Button 2 on one or more selected groups and choose Ungroup from the pop-up menu.


Go To Command Shortcuts (Waveform Editor)
Go To Command Shortcuts

Double-click Button 1 in the Reference (Ref) field.

Type Ctrl+G.


Overwrite Group Value Command Shortcuts

Press Button 2 on a single selected whole waveform or waveform interval and choose Overwrite Group Value from the pop-up menu.

Choose [image] from the tool palette on the left side of the window.


Insert Group Value Command Shortcuts

Press Button 2 on a single selected waveform interval and choose Insert Group Value from the pop-up menu.


Overwrite Low (0), High (1), Undefined (X), High Impedance (Z) Command Shortcuts
Overwrite Low (0), Overwrite High (1), Overwrite Undefined (X) & Overwrite High Impedance (Z) Command Shortcuts

Press Button 2 on one or more selected whole waveforms or waveform intervals and choose Overwrite Low (0), Overwrite High (1), Overwrite Undefined (X), or Overwrite High Impedance (Z) from the pop-up menu.

Choose one of the following tool palette buttons from the left side of the window:

 	Overwrite Low (0).

 	Overwrite High (1).

 	Overwrite Undefined (X).

 	Overwrite High Impedance (Z).


Insert Low (0), High (1), Undefined (X), High Impedance (Z) Command Shortcuts
Insert Low (0), Insert High (1), Insert Undefined (X) & Insert High Impedance (Z) Command Shortcuts

Press Button 2 on one or more selected waveform intervals and choose Insert Low (0), Insert High (1), Insert Undefined (X), or Insert High Impedance (Z) from the pop-up menu.


Overwrite Invert Command Shortcuts

Press Button 2 on one or more selected whole waveforms or waveform intervals and choose Overwrite Invert from the pop-up menu.

Choose [image] from the tool palette on the left side of the window.


Overwrite Count Value Command Shortcuts

Press Button 2 on a single selected whole waveform or waveform interval and choose Overwrite Count Value from the pop-up menu.

Choose [image] from the tool palette on the left side of the window.


Insert Count Value Command Shortcuts

Press Button 2 on a single selected waveform interval and choose Insert Count Value from the pop-up menu.


Overwrite Clock Command Shortcuts

Press Button 2 on a single selected whole waveform or waveform interval and choose Overwrite Clock from the pop-up menu.

Choose [image] from the tool palette on the left side of the window.


Insert Clock Command Shortcuts

Press Button 2 on a selected waveform interval and choose Insert Clock from the pop-up menu.


Paste Command Shortcuts

Press Button 2 at an insertion point or on a selection and choose Paste from the pop-up menu.

Type Ctrl+V or Shift+Insert.

Choose [image] from the toolbar at the top of the window.


Exit MAX+PLUS II Command Shortcuts

Double-click Button 1 on the Application Control Menu box [image] in the top left corner of the MAX+PLUS II window.

Type Alt+F4.


Find Text Command Shortcuts

Type Ctrl+F.

Choose [image] from the toolbar at the top of the window.


Go To Command Shortcuts (Text Editor)
Go To Command Shortcuts

Double-click Button 1 on Line or Column (Col) field.

Type Ctrl+G.


Hierarchy Project Top Command Shortcuts

Type Ctrl+T.

Choose [image] from the toolbar at the top of the window.


Hierarchy Up Command Shortcuts

Type Ctrl+U.


Hierarchy Down Command Shortcuts

(Graphic Editor only) With the Selection pointer (( [image] )), double-click Button 1 on a megafunction or macrofunction symbol.

Select a megafunction or macrofunction symbol or name and type Ctrl+D.


Open Command Shortcuts

Type Ctrl+O.

Choose [image] from the toolbar at the top of the window.


Print Command Shortcuts

Type Ctrl+P.

Choose [image] from the toolbar at the top of the window.

The toolbar shortcut for this command does not open the Print dialog box: it immediately prints the current file (or hierarchy) with the settings last entered in the Print dialog box.


Project Name Command Shortcuts

Type Ctrl+J.

Choose [image] from the toolbar at the top of the window.


Project Set Project to Current File Command Shortcuts

Type Ctrl+Shift+J.

Choose [image] from the toolbar at the top of the window.


Project Save & Compile Command Shortcuts

Type Ctrl+L.

Choose [image] from the toolbar at the top of the window.


Project Save & Simulate Command Shortcuts

Type Ctrl+Shift+L.

Choose [image] from the toolbar at the top of the window.


Project Save, Compile & Simulate Command Shortcuts

Type Ctrl+Shift+K.


Save Command Shortcuts

Type Ctrl+S.

Choose [image] from the toolbar at the top of the window.


Project Save & Check Command Shortcuts

Type Ctrl+K.

Choose [image] from the toolbar at the top of the window.


Search & Replace Command Shortcuts

Type Ctrl+R.

Choose [image] from the toolbar at the top of the window.


Undo Command Shortcuts

Type Ctrl+Z or Alt+Backspace.

Choose [image] from the toolbar at the top of the window.


Show All Assignments Command Shortcuts
Show All Command Shortcuts

Type Ctrl+Shift+M.

Choose [image] from the toolbar at the top of the window.


Enter Symbol Command Shortcuts

With the Selection pointer ( [image] ), double-click Button 1 in a blank space with the selection tool.

Press Button 2 in a blank space and choose Enter Symbol from the pop-up menu.


Edit Ports/Parameters Command Shortcuts

Press Button 2 on a macrofunction in the Graphic Editor window and choose Edit Ports/Parameters from the pop-up menu.


Enter Parameters Command Shortcuts

Double-click Button 1 on an existing parameter.


Enter Pinstub Command Shortcuts

With the Selection pointer ( [image] ), double-click Button 1 on a blank space within the symbol border or on an existing pinstub "x".


Enter Group Command Shortcuts

Double-click Button 1 in the group information area of an existing group.

Press Button 2 on a multi-node selection or an existing group and choose Enter Group from the pop-up menu.


Find Node in Floorplan Command Shortcuts

(Not available in Floorplan Editor) Press Button 2 on a selection and choose Find Node in Floorplan from the pop-up menu.

Choose [image] from the toolbar at the top of the window.

In all applications except for the Floorplan Editor, the shortcuts for this command do not open the Find Node in Floorplan dialog box if an item is already selected: they immediately locate the selected item(s).


Find Previous Command Shortcuts

Type Ctrl+Shift+N.


Find Previous Transition Command Shortcuts

Click Button 1 on the Reference cursor’s left/right cursor movement buttons, which is located to the right of the Reference (Ref) field.

Press the Left Arrow key.

You can locate subsequent transitions by choosing Find Previous or using a shortcut.


Find Next Command Shortcuts

Type Ctrl+N.


Find Next Transition Command Shortcuts

Click Button 1 on the Reference cursor’s left/right cursor movement buttons, which is located to the right of the Reference (Ref) field.

Press the Right Arrow key.

You can locate subsequent transitions by choosing Find Next or using a shortcut.


Pin/Location/Chip Command Shortcuts

(Graphic Editor only) With the Selection pointer, double-click Button 1 on an existing Pin, Location & Chip Assignment with the selection tool.

Press Button 2 on a selection and choose Assign Pin/Location/Chip from the pop-up menu.


Timing Requirements Command Shortcuts

(Graphic Editor only) With the Selection pointer, double-click Button 1 on an existing timing assignment with the selection tool.

Press Button 2 on a selection and choose Assign Timing Requirements from the pop-up menu.


Clique Command Shortcuts

(Graphic Editor only) With the Selection pointer, double-click Button 1 on an existing clique assignment with the selection tool.

Press Button 2 on a selection and choose Assign Clique from the pop-up menu.


Logic Options Command Shortcuts

(Graphic Editor only) With the Selection pointer, double-click Button 1 on a logic option assignment with the selection tool.

Press Button 2 on a selection and choose Assign Logic Options from the pop-up menu.


Probe Command Shortcuts

(Graphic Editor only) With the Selection pointer, double-click Button 1 on a probe assignment with the selection tool.

Press Button 2 on a selection and choose Assign Probe from the pop-up menu.


Connected Pins Command Shortcuts

Press Button 2 on a selection and choose Assign Connected Pins from the pop-up menu.


Demote Assignments Command Shortcuts

Press Button 2 on a selection and choose Assign Demote Assignments from the pop-up menu.


Timing Analysis Source Command Shortcuts

Press Button 2 on a selection and choose Timing Analysis Source from the pop-up menu.

Type Ctrl+Alt+S.


Timing Analysis Destination Command Shortcuts

Press Button 2 on a selection and choose Timing Analysis Destination from the pop-up menu.

Type Ctrl+Alt+D.


Timing Analysis Cutoff Command Shortcuts

Press Button 2 on a selection and choose Timing Analysis Cutoff from the pop-up menu.

Type Ctrl+Alt+C.


Find Node Source Command Shortcuts

Press Button 2 on a selection and choose Find Node Source from the pop-up menu.

Type Ctrl+Shift+S.


Find Node Destination Command Shortcuts

Press Button 2 on a selection and choose Find Node Destination from the pop-up menu.

Type Ctrl+Shift+D.


Text Size Command Shortcuts

(Graphic & Symbol Editors only) Press Button 2 on a selection and select a text size from the Text Size submenu on the pop-up menu.

Type a text size or select a text size from the [image] drop-down list box on the toolbar at the top of the window.


Font Command Shortcuts

(Graphic & Symbol Editors only) Press Button 2 on a selection and select a font from the Font submenu on the pop-up menu.

Type a font name or select a font from the [image] drop-down list box on the toolbar at the top of the window.


Increase Indent & Decrease Indent Command Shortcuts

Press Button 2 on a selection and choose Increase Indent or Decrease Indent from the pop-up menu.

Type F2 or F3.

Choose [image] or [image] from the toolbar at the top of the window.


Insert Page Break Command Shortcuts

Press Button 2 at an insertion point or on a selection and choose Insert Page Break from the pop-up menu.


AHDL Template Command Shortcuts

Press Button 2 at an insertion point or on a selection and choose AHDL Template from the pop-up menu.

Choose [image] from the toolbar at the top of the window.


VHDL Template Command Shortcuts

Press Button 2 at an insertion point or on a selection and choose VHDL Template from the pop-up menu.

Choose [image] from the toolbar at the top of the window.

This toolbar shortcut is only available if the current filename extension is .vhd. For all other filename extensions, this toolbar button is a shortcut for the AHDL Template command.


Find Matching Delimiter Command Shortcuts

Press Button 2 on a selected delimiter and choose Find Matching Delimiter from the pop-up menu.


MAX+PLUS II Menu Command Shortcuts

The following toolbar button shortcuts allow you to open MAX+PLUS II applications:

Button:	Command:

Floorplan Editor.

Compiler.

Hierarchy Display.

Simulator.

Timing Analyzer.

Programmer.


New Command Shortcuts

Choose [image] from the toolbar at the top of the window.


Window Menu Command Shortcuts

The following key combinations are shortcuts for their respective Window menu commands:

Key Combination:	Command:

Type Shift+F4	Tile Horizontally.

Type Shift+F5	Cascade.


Document Control Menu Command Shortcuts

The following key combinations are shortcuts for their respective Window menu commands:

Key Combination:	Command:

Type Ctrl+Esc	Switch To.

Type Ctrl+F6	Next.

Type Ctrl+F4	Close.

(Close command only) Double-click Button 1 on the Document Control Menu box [image] in the top left corner of the current window.


Info Command Shortcuts

Type Ctrl+I.


Repeat Command Shortcuts

Press Button 2 on one or more selected waveform intervals and choose Repeat from the pop-up menu.


Grow or Shrink Command Shortcuts

Press Button 2 one or more selected whole waveforms or waveform intervals and choose Grow or Shrink from the pop-up menu.


Enter Text Command Shortcuts (Waveform Editor)
Enter Text Command Shortcuts

Press Button 2 in the waveform drawing area and choose Enter Text from the pop-up menu.


Enter Text Command Shortcuts (Graphic Editor)
Enter Text Command Shortcuts

Press Button 2 in a blank space and choose Enter Text from the pop-up menu.


Copy Command Shortcuts

Press Ctrl+Button 1 on a selection with the Selection pointer ( [image] ), drag it, and release Button 1 and the Ctrl key.

If you have already started to drag (i.e., move) a selection, you can press Ctrl to change the move operation into a copy operation. You must continue pressing Ctrl until you release Button 1 to copy a selection.

Press Button 2 on a selection and choose Copy from the pop-up menu.

Type Ctrl+C or Ctrl+Ins.

Choose [image] from the toolbar at the top of the window.


Zoom In/Out Command Shortcuts
Zoom In & Zoom Out Command Shortcuts

Type Ctrl+Space to zoom in or Ctrl+Shift+Space to zoom out.

Choose [image] or [image] from the tool palette on the left side of the window, to zoom in or out, respectively.


Show Guidelines Command Shortcuts

Type Ctrl+Shift+G.


Show Node Fan-In & Show Node Fan-Out Command Shortcuts

Choose one of the following buttons from the tool palette on the left side of the window:

Button:	Command:

Show Node Fan-In.

Show Node Fan-Out.


Show Path Command Shortcuts

Choose [image] from the tool palette on the left side of the window.


Routing Statistics Command Shortcuts

Double-click Button 1 on a pin, logic cell, I/O cell, or assignment bin.

Press Button 2 on a pin, logic cell, I/O cell, or assignment bin and choose Routing Statistics from the pop-up menu.


Edit Node/Bus Name Command Shortcuts

Double-click Button 1 on an existing node or bus name and type the new name.

Press Button 2 on a node in the Graphic Editor window and choose Edit Node/Bus Name from the pop-up menu.


Edit Pin Name Command Shortcuts

Double-click Button 1 on an existing pin name to select it and type the new name.


Edit Pin Default Value Command Shortcuts

Double-click Button 1 on an existing pin default value to select it and type the new default value.


Edit Selected Text Command Shortcuts

Double-click Button 1 on an existing symbol or pin name within the symbol border to select it and type the new name.


Current Assignments Floorplan Command Shortcuts

Choose [image] from the tool palette on the left side of the window.


Last Compilation Floorplan Command Shortcuts

Choose [image] from the tool palette on the left side of the window.


Device View Command Shortcuts

Double-click Button 1 in blank space while in the LAB View.


LAB View Command Shortcuts

Double-click Button 1 in blank space while in the Device View.


Rubberbanding Command Shortcuts

Choose [image] (On) or [image] (Off) from the toolbar at the top of the window.


Open Editor Command Shortcuts

Press Button 2 on a file icon and choose Open Editor from the pop-up menu.


Close Editor Command Shortcuts

Press Button 2 on a file icon of an open file and choose Close Editor from the pop-up menu.


Change File Type Command Shortcuts

Press Button 2 on the first file icon following a filename in the Hierarchy Display window and choose Change File Type from the pop-up menu.


Locate Command Shortcuts

Double-click Button 1 on a message in the Message Processor window.


Context-Sensitive Help Command Shortcuts

Press Shift+F1 and click Button 1 on a selection.

Type F1.

Choose [image] from the toolbar at the top of the window and click Button 1 on a selection.


Save Messages As Command Shortcuts
Save Massages As Command Shortcuts

Choose [image] from the toolbar at the top of the window.


Setup/Hold Matrix Command Shortcuts

Choose [image] from the toolbar at the top of the window.


Save Analysis As Command Shortcuts

Choose [image] from the toolbar at the top of the window.


Registered Performance Command Shortcuts

Choose [image] from the toolbar at the top of the window.


Delay Matrix Command Shortcuts

Choose [image] from the toolbar at the top of the window.


Save Programming Data As Command Shortcuts

Choose [image] from the toolbar at the top of the window.


Select Device Command Shortcuts

Double-click Button 1 on the Device field.


Select Programming File Command Shortcuts

Double-click Button 1 on the File field.

Choose [image] from the toolbar at the top of the window.


Toggle Connection Dot Command Shortcuts

Double-click Button 1 on the intersection of two lines.

Press Button 2 and choose Toggle Connection Dot from the pop-up menu.

Choose [image] from the tool palette on the left side of the window.


Recommended Reading for MAX+PLUS II

The following Altera publications are available from the Altera Literature Department or Altera Express. Many publications are also available via modem from the Altera electronic bulletin board service.

Application Notes:

AN2	Replacing 20-Pin PAL & GAL Devices with EP330 Classic EPLDs

AN16	Integrating PAL, GAL & PLA Devices with the EPM5032 MAX EPLD

AN17	Integrating an Intelligent I/O Subsystem with a Single EPM5130 MAX EPLD

AN20	Fast Bus Controllers with the EPM5016 MAX EPLD

AN21	Designing a FIFO Controller with an EPM5064 MAX EPLD

AN22	Designing with AHDL

AN25	Controlling Complex CCD Imaging Systems with the EPS464 STG EPLD

AN26	EPLD/MPLD Design Guidelines

AN27	Implementing EISA Interfaces with MAX EPLDs

AN28	Waveform Design Entry

AN30	Viewlogic Workview PLUS & MAX+PLUS II Logic Design

AN31	Fitting Designs in MAX 7000 EPLDs

AN33	Configuring FLEX 8000 Devices

AN36	Designing with FLEX 8000 Devices

AN38	Configuring Multiple FLEX 8000 Devices

AN39	JTAG Boundary-Scan Testing in FLEX 8000 Devices

AN40	FLEX 8000 Architectures

AN42	Metastability in Altera Devices

Application Briefs:

AB9	Asynchronous Latches in Classic, MAX & STG EPLDs

AB27	EP1810 Classic EPLD as a Bar Code Decoder

AB46	Selecting Sockets for J-Lead Packages

AB60	Estimating a Design Fit

AB77	Fitting Complex Designs in MAX 5000 EPLDs

AB81	Troubleshooting EPLD Programming Problems

AB82	Emulating Internal Buses in Classic, MAX & STG EPLDs

AB83	Programmable Frequency Divider with the EP610 Classic EPLD

AB84	DMA Controller with the EPM5064 MAX EPLD

AB86	Designing & Simulating Bidirectional Buses with MAX+PLUS II Software

AB87	Troubleshooting Functional Problems in EPLDs

AB88	Optimizing Counter Design for Altera EPLDs

AB89	Minimizing Output Switching Noise in Altera EPLDs

AB91	External Clock Sources for Altera EPLDs

AB92	Simulating Internal Nodes with MAX+PLUS II Software

AB93	Partitioning a Project with MAX+PLUS II Software

AB94	Solutions to Design Timing Problems for Altera EPLDs

AB95	Designing Phase-Locked Loops with Altera EPLDs

AB96	Generating Library Mapping Files

AB97	Integrating EDIF Files with AHDL Files in Hierarchical Projects

AB98	Configuring Your PC for MAX+PLUS II Software

AB99	Design Flow between Workstations & PCs

AB100	Understanding Classic, MAX 5000 & MAX 7000 Timing

AB111	Carry Look-Ahead Counters in FLEX 8000 Devices

AB113	Equality Comparators in FLEX 8000 Devices

AB114	Full Comparators in FLEX 8000 Devices

AB115	Carry-Select Adders in FLEX 8000 Devices

AB117	Barrel Shifters in FLEX 8000 Devices

AB118	Ripple-Carry Adders in FLEX 8000 Devices

AB119	High-Speed Board Designs

AB121	Designing Counters in FLEX 8000 Devices

AB122	Carry Look-Ahead Counters in FLEX 8000 Devices

AB123	Pipelined Carry Look-Ahead Counters in FLEX 8000 Devices

AB123	Accumulators in FLEX 8000 Devices

AB124	Prescaled Counters in FLEX 8000 Devices

AB125	Designing Adders, Subtractors & Accumulators in FLEX 8000 Devices

AB126	Subtractors in FLEX 8000 Devices

AB127	Designing Multipliers in FLEX 8000 Devices

AB128	Multiplexers in FLEX 8000 Devices

AB130	Parity Generators in FLEX 8000 Devices

AB131	State Machine Encoding

AB132	Ripple-Carry Multipliers in FLEX 8000 Devices

AB133	Combinatorial Multipliers in FLEX 8000 Devices

AB134	Pipelined Multipliers in FLEX 8000 Devices

AB135	Ripple-Carry Gray Code Counters in FLEX 8000 Devices

AB137	Ripple-Carry Counters in FLEX 8000 Devices

AB143	Understanding FLEX 8000 Timing

AB144	Understanding MAX 9000 Timing

Data Sheets:

Altera Device Package Outlines

Electronic Bulletin Board Service

Operating Requirements for Altera Devices

QFP Carrier & Development Socket

Thermal Resistance (°C/W)

Software Interface Guides:

Cadence & MAX+PLUS II Software Interface Guide

Mentor Graphics & MAX+PLUS II Software Interface Guide

Synopsys & MAX+PLUS II Software Interface Guide

Viewlogic Powerview & MAX+PLUS II Software Interface Guide

Other:

Workbook	MPLD Conversion Information & Order Forms

PIB 14	Mask-Programmed Logic Devices: The Fastest Route to High-Volume Production

Book	IEEE Standard VHDL Language Reference Manual

Book	VHDL


Application Note 2    Replacing 20-Pin PAL & GAL Devices with EP330 Classic EPLDs

The Altera EP330 device can be used as a drop-in replacement for all common 20-pin PAL and GAL devices. This application note describes EP330 architecture and its advantages over PALs and GALs, including very high speed, low power, and a flexible architecture.

Source:	1992 Applications Handbook


Application Note 16    Integrating PAL, GAL & PLA Devices with the EPM5032 MAX EPLD

The EPM5032 offers better integration than PAL, GAL, or PLA devices and a flexible architecture that supports a broad range of applications. A single EPM5032 typically replaces three to four conventional PLDs, and can also provide extensive TTL integration. The EPM5032 device also offers superior logic utilization, more flexible register options, better control of I/O pins, and better system performance.

This application note includes samples of converted PAL and PLA designs, which show that one EPM5032 can replace three PLAs or three PALs and two TTL devices. A PAL shaft encoder can be implemented by converting PAL 16R4, 16R8, and 20X10 JEDEC Files into AHDL TDFs with Altera’s PLD2EQN utility. The symbols for these three files are then combined with symbols for two TTL macrofunctions in a top-level GDF.

Signetics AMAZE files are easily converted manually into AHDL TDFs. To implement a PLA serial communications interface, two AMAZE files can be converted to TDFs. A third component of the interface, a cyclic redundancy check generator, is entered as a GDF. The symbols for all three design files are then combined in a top-level GDF.

Source:	1992 Applications Handbook


Application Note 17    Integrating an Intelligent I/O Subsystem with a Single EPM5130 MAX EPLD

The custom logic requirements of an intelligent I/O subsystem can be integrated into a single Altera user-configurable EPM5130 MAX device, replacing over 75 standard TTL packages.

This application note describes a serial coprocessor that consists of a combination of GDFs and AHDL TDFs. Control functions are implemented in AHDL state machines.

GDFs are used to create various components of the serial coprocessor: an error detection and correction (EDAC) function, an address generator, a buffer RAM controller, and a 4-bit parity code generator. An AHDL state machine controls data serialization. The serial coprocessor design example also includes a Report File excerpt that illustrates macrocell fan-in and expander usage and sharing, as well as a Table File that shows simulation results for the EDAC function.

Source:	1992 Applications Handbook


Application Note 20    Fast Bus Controllers with the EPM5016 MAX EPLD

The wait-state and bus-control logic for a memory interface to a high-speed microprocessor can be implemented in an Altera EPM5016 MAX device, which can then be integrated into an 80386-based system design.

This application note describes a bus controller design implemented with MAX+PLUS II. The project’s top-level design file is a GDF that integrates four TDFs: a transceiver controller state machine; a state machine that determines when the 80386 is in a bus cycle; a state machine that tracks the 80386 control signals to decode the bus cycle; and a counter that generates wait states. The Compiler fits the project into a single EPM5016 device.

This application brief also describes bus-cycle timing and provides a Vector File that can be used to simulate a read from the 200-ns EPROM in a 33-MHz 80386.

Source:	1992 Applications Handbook


Application Note 21    Designing a FIFO Controller with an EPM5064 MAX EPLD

An 8-Kbyte ∞ 16-bit first-in/first-out (FIFO) buffer controller in a data path can be designed with an Altera 64-macrocell EPM5064 device. This FIFO buffer can bridge rate and time mismatches in digital subsystems so that they function efficiently.

This application note introduces shift and pointer FIFOs, and describes a low-cost solution for pointer FIFOs that includes an EPM5064 device as the FIFO controller and two 8-Kbyte x 8-bit SRAM devices. The FIFO controller has a read, write, and peripheral read cycle, each of which is illustrated in a sample SCF that shows simulation results.

The FIFO controller is implemented in a top-level AHDL TDF that uses a Function Prototype Statement to call a lower-level GDF containing a 13-bit up/down counter. A detailed description of the constants, function prototypes, design logic, and conditional logic that defines the FIFO controller is included.

Source:	1992 Applications Handbook


Application Note 22    Designing with AHDL

The Altera Hardware Description Language (AHDL) is a powerful text-based language used to enter designs. AHDL supports Boolean equations, truth tables, state machines, and group operations.

This application note describes the AHDL design structure and shows how to use AHDL statements to implement conditional and decode logic, specify default values for constants, assign logic options, implement primitives and macrofunctions in the hierarchy, create groups, and implement state machines. This application note also describes how to back-annotate, preserve, and edit assignments, and shows a sample Fit File that can be edited and used as the Design Section in a TDF. A detailed description of top-down design with AHDL is also included.

This application note also provides the following sample files:

Address decoder for a generalized 16-bit microprocessor

8-bit counter with 74161 macrofunctions

9-bit counter with Load and Enable

16-bit accumulator

DRAM controller state machine

Synchronization detector state machine

Source:	1992 Applications Handbook


Application Note 25    Controlling Complex CCD Imaging Systems with the EPS464 STG EPLD

The Altera EPS464 STG device is ideal for implementing digital control logic to convert image data into a standard video format.

This application note describes a control system that implements the National Television System Committee (NTSC) specification to control a CCD imaging systems. MAX+PLUS II and AHDL are used to implement the NTSC standard in the NTSC macrofunction, which includes two counters, a pulse decode module, and a state machine. You can easily modify this Altera-provided macrofunction to generate your own custom control function. The Compiler fits the project into a single EPS464 device.

Source:	1992 Applications Handbook


Application Note 26    EPLD/MPLD Design Guidelines

Altera EPLDs offer the benefits of rapid prototyping and production cycles, including fast time-to-market, reduced development costs, and easy last-minute modifications. When designs enter high-volume production, Altera mask-programmed logic devices (MPLDs) provide a low per-unit-price alternative. An EPLD project can be converted into an MPLD that has guaranteed drop-in compatibility. To ensure a successful EPLD-to-MPLD conversion, you must understand the potential logic and timing problems and apply the design rules that Altera recommends.

This application note provides recommended design rules for Clock configurations such as global, gated, ripple, and multi-level Clocks; multi-Clock configurations; Clear and Preset signals; combinatorial outputs; asynchronous inputs; race conditions; minimum delays; power-on vs. master Reset; and stuck states in state machines and sequential circuits. Guidelines for implementing expander flipflops and latches with EXPDFF, EXPLATCH, NORLATCH, and NANDLATCH primitives are also included, as well as examples of acceptable and unacceptable configurations for these types of logic. A checklist that covers basic design reliability issues that should be addressed before you submit an EPLD design for MPLD conversion is also included.

1.	The information provided in this application note summarizes good design practices that should be implemented regardless of whether your project will be converted into an MPLD. These guidelines are also the foundation for the Design Doctor analysis.

2.	The information in this application note also applies to FLEX 8000 devices.

Source:	1992 Applications Handbook


Application Note 27    Implementing EISA Interfaces with MAX EPLDs

Altera’s MAX 5000 and MAX 7000 devices provide sufficient logic density to meet the requirements for complex, fast Extended Industry Standard Architecture (EISA) bus interfaces. A bus master controller can be implemented for an EISA interface card with MAX+PLUS II software and Altera devices to create a design that can be clocked at significantly faster speeds than the bus speeds found in existing EISA motherboards.

This application note describes how to implement the EISA bus master interface design with GDFs and AHDL TDFs. The interface contains three subdesigns: an EISA bus address decoder, interface logic for a local board processor, and an EISA bus arbitration state machine. All three functions are implemented in a single EPM7256 device, or partitioned between an EPM5064 device and an EPM5130 device.

Source:	1992 Applications Handbook


Application Note 28    Waveform Design Entry

The MAX+PLUS II Waveform Editor is not only a tool for entering simulation vectors and reviewing simulation results, but also a design editor that can be used to describe logic. Waveform design entry is best suited to circuits that have well-defined sequential inputs and outputs, such as state machines, counters, and registers; combinatorial functions decoded from counters; and other repeating functions.

This application note provides practical guidelines for waveform design entry and applies them to seven sample designs. Examples include a 3-input AND function, a 3-bit address decoder, and a counter decoder. Three sample state machine designs (simple, complex, and one with conditional branching inputs) are also included, as well as information on setting up input files with state machine groups for simulation. All of these examples point out possible pitfalls in creating a WDF. The application note also shows you how to ensure an adequate setup time for the Clock and how to use the waveform separator. It also illustrates how you can combine different MAX+PLUS II design entry methods (text, graphic, and waveform) in a single project.

Source:	1992 Applications Handbook


Cadence & MAX+PLUS II Software Interface Guide

Cadence design tools and Altera’s MAX+PLUS II development software together provide a complete design environment supporting graphic and text design entry, design processing and fitting, full design verification, and device programming.

This software interface guide outlines the software tools and user environment configurations needed for the Altera/Cadence interface. It describes how to enter a schematic design with Concept or Composer, a VHDL design, or a Verilog design. It then explains how to generate an EDIF 2 0 0 or 3 0 0 netlist file, and rename this netlist as a MAX+PLUS II-compatible EDIF Input File (.edf). You can also enter a Text Design File (.tdf) using the Altera Hardware Description Language (AHDL) with any standard text editor. LMFs can be used to map Cadence macrofunctions to corresponding Altera macrofunctions. Step-by-step instructions on how to compile the EDIF Input File with the MAX+PLUS II Compiler are also included. After successful compilation, the Compiler generates one or more EDIF Output Files (.edo), Verilog Output Files (.vo), or VHDL Output Files (.vho), and optional SDF Output Files (.sdo) that you can use to simulate a project, and one or more files for device programming. This software interface guide also shows how to prepare the EDIF Output File for use with RapidSIM, the Verilog Output File for use with Verilog-XL simulator, or the VHDL Output File for use with the Leapfrog simulator. It also includes general guidelines for programming devices.

In addition, this software interface guide provides examples that show how to create a schematic design with Concept or Composer or a VHDL or Verilog design and generate an EDIF netlist file or an AHDL design with a text editor, compile the EDIF Input File or TDF with MAX+PLUS II, and generate an EDIF Output File, Verilog Output File, or VHDL Output File, and optional SDF Output File for simulation.

Source:	Stand-alone software interface guide


Application Note 30    Viewlogic Workview PLUS & MAX+PLUS II Logic Design

Viewlogic Workview PLUS design tools and Altera’s MAX+PLUS II development software together provide a complete design environment supporting graphic and text design entry, design processing and fitting, full design verification, and device programming.

This application note outlines the software tools and user environment configurations needed for the Altera/Viewlogic interface. It describes how to enter a design with Workview PLUS, generate an EDIF 2 0 0 or 3 0 0 netlist file, and import it into the MAX+PLUS II Compiler as an EDIF Input File (.edf). LMFs can be used to map Viewlogic macrofunctions to corresponding MAX+PLUS II macrofunctions. Step-by-step instructions on how to compile the EDIF Input File with the MAX+PLUS II Compiler are also included. After successful compilation, the Compiler generates an EDIF Output File (.edo) that you can use to simulate a project, and one or more files for device programming. The application note also shows how to prepare the EDIF Output File for use with Viewsim, using an EDIF Command File (.edc) to customize the EDIF Output File, and offers general guidelines for programming devices.

In addition, this application note provides examples that show how to create a schematic or VHDL design with Workview PLUS, generate an EDIF netlist file, compile the file with MAX+PLUS II, and generate an EDIF Output File for simulation.

Source:	Stand-alone application note


Application Note 31    Fitting Designs in MAX 7000 EPLDs

Some projects require more logic or routing resources than are available in the target MAX 7000 device(s), or contain resource assignments that the MAX+PLUS II Compiler cannot implement automatically. These projects may require modifications to enable the Compiler to synthesize logic effectively and to obtain a fit in a MAX 7000 device.

This application note provides guidelines for fitting MAX 7000 projects and lists common Compiler error messages. It also shows how to simplify complex functions by placing LCELL and SOFT buffers at strategic locations in a project. Several guidelines and sample GDFs are presented to illustrate correct LCELL and SOFT buffer placement.

Source:	Stand-alone application note


 Mentor Graphics & MAX+PLUS II Software Interface Guide

Mentor Graphics design tools and Altera’s MAX+PLUS II development software together provide a complete design environment supporting graphic and text design entry, design processing and fitting, full design verification, and device programming.

This software interface guide outlines the software tools and user environment configurations needed for the Altera/Mentor Graphics interface. It describes how to enter a schematic design with Design Architect or enter a VHDL design and synthesize it with the Autologic VHDL synthesis tool, generate an EDIF 2 0 0 or 3 0 0 netlist file, and rename this EDIF netlist as a MAX+PLUS II-compatible EDIF Input File (.edf). You can also enter a Text Design File (.tdf) using the Altera Hardware Description Language (AHDL) with any standard text editor. LMFs can be used to map Design Architect macrofunctions to corresponding Altera macrofunctions. Step-by-step instructions on how to compile the EDIF Input File with the MAX+PLUS II Compiler are also included. After successful compilation, the Compiler generates one or more EDIF Output Files (.edo), Verilog Output Files (.vo), and VHDL Output Files (.vho), and optional SDF Output Files (.sdo), that you can use to simulate a project, and one or more files for device programming. The software interface guide also shows how to prepare the EDIF Output File for use with QuickSim or Logic Modeling SmartModels, and offers general guidelines for programming devices.

In addition, this software interface guide provides examples that show all steps required to create a schematic design with Design Architect or a VHDL or AHDL design with a text editor, generate an EDIF netlist file for the schematic or VHDL design, compile the EDIF Input File or TDF with MAX+PLUS II, and generate an EDIF Output File and optional SDF Output File (.sdo) for simulation.

Source:	Stand-alone software interface guide


Application Note 33    Configuring FLEX 8000 Devices

Individual Altera FLEX 8000 devices can be configured with several different configuration schemes. This application note describes the configuration process and circuitry for each of the six available single-device configuration schemes: Active Serial, Active Parallel Up, Active Parallel Down, Passive Parallel Synchronous, Passive Parallel Asynchronous, and Passive Serial. Explanations of how to set user-controllable configuration bit options and dual-purpose pins are also included.

This application note gives step-by-step instructions for downloading SRAM Object File (.sof) data to a device in-system via the FLEX Download Cable and for programming Programmer Object File (.pof) data into an Altera Configuration EPROM.

Source:	FLEX 8000 Handbook


Synopsys & MAX+PLUS II Software Interface Guide

Synopsys design tools and Altera’s MAX+PLUS II development software together provide a complete design environment supporting text design entry, design processing and fitting, full design verification, and device programming.

This software interface guide outlines the software tools and user environment configurations needed for the Altera/Synopsys interface. It describes how to enter a design in either the VHDL or Verilog technology-independent design language, generate an EDIF 2 0 0 or 3 0 0 netlist file, and rename this netlist as a MAX+PLUS II-compatible EDIF Input File (.edf). You can use LMFs to map Synopsys macrofunctions to corresponding Altera macrofunctions. Step-by-step instructions on how to compile the EDIF Input File with the MAX+PLUS II Compiler are also included. After successful compilation, the Compiler generates one or more Verilog Output Files (.vo), VHDL Output Files (.vho), and EDIF Output Files (.edo), and optional SDF Output Files (.sdo), that you can use to simulate a project, and one or more files for device programming. This software interface guide also offers general guidelines for programming devices.

In addition, this software interface guide provides examples that show all steps required to create a Verilog or VHDL project with a text editor, generate an EDIF netlist file, compile the EDIF Input File with MAX+PLUS II, and generate a Verilog Output File, a VHDL Output File, or an EDIF Output File and optional SDF Output File for simulation.

Source:	Stand-alone software interface guide


Application Note 36    Designing with FLEX 8000 Devices

Altera’s FLEX 8000 architecture combines the strengths of both EPLDs and FPGAs. This application note describes some of the basic characteristics of the FLEX 8000 architecture and offers several recommendations for using the architecture effectively.

This application note describes how to optimize a design for FLEX 8000 devices and discusses the advantages of different design entry methods. General design guidelines are presented, including recommendations for reserving resources, assigning pins and logic cells, balancing ripple-carry and carry look-ahead usage, using global Clock and Clear signals, using one-hot state bit encoding, and using pipelining for complex combinatorial logic. This application note also offers tips for fitting designs that require significant routing resources.

Source:	FLEX 8000 Handbook


Viewlogic Powerview & MAX+PLUS II Software Interface Guide

Viewlogic Powerview design tools and Altera’s MAX+PLUS II development software together provide a complete design environment supporting graphic and text design entry, design processing and fitting, full design verification, and device programming.

This software interface guide outlines the software tools and user environment configurations needed for the Altera/Viewlogic interface. It describes how to enter a schematic design with Viewdraw or a VHDL design, generate an EDIF 2 0 0 or 3 0 0 netlist file, and rename this netlist as a MAX+PLUS II-compatible EDIF Input File (.edf). You can also enter a Text Design File (.tdf) using the Altera Hardware Description Language (AHDL) with any standard text editor. You can use LMFs to map Viewlogic macrofunctions to corresponding Altera macrofunctions. Step-by-step instructions on how to compile the EDIF Input File with the MAX+PLUS II Compiler are also included. After successful compilation, the Compiler generates an EDIF Output File (.edo) and optional SDF Output File (.sdo) that you can use to simulate a project, and one or more files for device programming. The software interface guide also shows how to prepare the EDIF Output File for use with Viewsim, using an EDIF Command File (.edc) to customize the EDIF Output File, and offers general guidelines for programming devices.

In addition, this software interface guide provides examples that show how to create a schematic design with Viewdraw or a VHDL or AHDL design with a text editor, generate an EDIF netlist file for the schematic or VHDL design, compile the EDIF Input File or TDF with MAX+PLUS II, and generate an EDIF Output File for simulation.

Source:	Stand-alone software interface guide


Application Note 38    Configuring Multiple FLEX 8000 Devices

Multiple Altera FLEX 8000 devices can be configured with several different types of configuration circuits. This application note describes the configuration process and circuitry for each of the six available configuration circuits: Multi-Device Sequential Active Serial, Multi-Device Active Serial Bit-Slice, Multi-Device Passive Serial Bit-Slice, Multi-Device Passive Parallel Synchronous, Multi-Device Passive Parallel Asynchronous, and Multi-Device Active Parallel Hybrid. Explanations of how to set user-controllable configuration bit options and dual-purpose pins are also included.

Source:	FLEX 8000 Handbook


Application Note 39    JTAG Boundary-Scan Testing in FLEX 8000 Devices

In the 1980s, the Joint Test Action Group (JTAG) developed the IEEE 1149.1-1990 specification for boundary-scan testing. The Boundary-Scan Test (BST) architecture offers the capability to efficiently test components on circuit boards with tight lead spacing.

This application note describes how to use the JTAG BST circuitry available in the EPF81500, EPF8820, EPF8636, EPF8282, and EPF8282V FLEX 8000 devices. It provides detailed descriptions of the JTAG BST architecture and boundary-scan register, as well as the three JTAG BST instruction modes-SAMPLE/PRELOAD, EXTEST, and BYPASS. You can use these three modes to create serial patterns that internally test the pin connections between devices and check device operation.

Source:	FLEX 8000 Handbook


Application Note 40    FLEX 8000 Architecture

Altera’s Flexible Logic Element MatriX (FLEX) programmable logic combines the high register counts of FPGAs with the fast, predictable interconnect of EPLDs to make the FLEX 8000 device family ideal for a wide range of applications.

This application note describes the FLEX 8000 architecture in detail. It provides information on the FLEX 8000 logic element (LE), including the carry and cascade chain, logic element operating modes, and Clear and Preset logic control. It also describes the FLEX 8000 Logic Array Block (LAB), FastTrack Interconnect, dedicated inputs, and I/O element. These architectural features allow designers to achieve maximum optimization and performance.

Source:	FLEX 8000 Handbook


Application Note 42    Metastability in Altera Devices

An edge-triggered flipflop has two valid states: high and low. Metastability occurs when a flipflop is used to synchronize asynchronous data that violates the flipflop’s timing requirements, causing the flipflop to glitch, to oscillate, or to hover between high and low states.

This application note describes metastability, how it is quantified, and how to minimize its effects. It also includes metastability data for Altera’s MAX 7000, FLEX 8000, and EPX740 and EPX780 FLEXlogic devices that can be used to estimate the mean time between failures (MTBF) of a system that uses an Altera device to synchronize asynchronous data.

Source:	current Data Book


Application Brief 9    Asynchronous Latches in Classic, MAX & STG EPLDs

Asynchronous latches can be implemented in Altera Classic, MAX 5000, MAX 7000, and EPS464 STG devices with the fully integrated MAX+PLUS II software.

This application brief describes expander- and macrocell-based SR latches and transparent D latches. It includes information on the LATCH primitive and the NANDLTCH, NORLTCH, and EXPLATCH macrofunctions provided with MAX+PLUS II. These primitives and macrofunctions can be easily implemented with symbols in GDFs and with instance declarations or in-line references in AHDL TDFs.

Source:	1992 Applications Handbook


Application Brief 27    EP1810 Classic EPLD as a Bar Code Decoder

A bar code decoder can be implemented in an Altera EP1810 device with MAX+PLUS II software. The EP1810 device decodes a generic bar code, stores the decoded data byte, and alerts a microprocessor that data is ready.

This application brief describes bar code specifications and a bar code decoder design. The bar code decoder is implemented in a top-level GDF that contains a synchronous counter, byte counter, shift register, status outputs, and a controller state machine. Proper placement of MCELL (same as LCELL) buffers is also illustrated in this GDF. Two lower-level TDFs that describe the 8-stage Gray-code byte counter and state controller state machine are described. The Compiler fits the project into a single EP1810 device.

Source:	1992 Applications Handbook


Application Brief 46    Selecting Sockets for J-Lead Packages

Altera’s J-lead chip carrier devices are small packages generally intended for surface mounting. By using a socket with these devices, you can take advantage of these small, low-cost devices without the complications of surface mounting.

This application brief describes the types of sockets available and the criteria for selecting burn-in or production sockets. It provides evaluations of 44-, 68-, and 84-pin production sockets from seven manufacturers (vendor information is included). The application brief also discusses carrier boards for use with wire-wrap panels and J-lead packages.

Source:	current Data Book


Application Brief 60    Estimating a Design Fit

To estimate a design fit, you must evaluate the physical resources required by a design. By counting the number of input, output, and bidirectional signals in a design, you can estimate the required pin count. You can similarly estimate the number of macrocells required by counting pin inputs, outputs, and buried registers. This application brief provides formulas for estimating both pin and macrocell count for your designs.

Source:	1992 Applications Handbook


Application Brief 77    Fitting Complex Designs in MAX 5000 EPLDs

Projects containing complex combinatorial logic and/or requiring more macrocells than are available in a MAX 5000 device sometimes require subtle modifications to achieve a design fit. This application brief describes how the MAX+PLUS II Compiler fits a project and explains the error messages it generates if a fit is not achieved. Techniques for fitting complex projects into MAX 5000 devices are also suggested.

If a project is too large for a device, you can usually achieve a fit by simplifying the complex combinatorial logic to reduce the number of macrocells used. This application brief describes how to decrease project macrocell usage by eliminating MCELL (same as LCELL) or SOFT buffers that have been manually placed into combinatorial logic, removing SOFT buffers from combinatorial 74-series macrofunctions, and implementing buried registers or latches with shareable expanders.

Complex combinatorial functions can be simplified by strategically placing SOFT and MCELL buffers. Several guidelines and sample GDFs are presented to illustrate correct SOFT and MCELL buffer placement.

Source:	1992 Applications Handbook


Application Brief 81    Troubleshooting EPLD Programming Problems

Altera programming hardware and software typically provide simple, trouble-free operation. Most programming problems can be solved by updating the software and hardware and by following the solutions presented in this application brief.

This application brief describes how to calibrate programming hardware with the Altera Field Diagnostic (AFD) utility and reconfigure your software to recognize new device versions. It explains the possible causes for all common error messages that occur during programming, and provides a troubleshooting checklist that can help you and Altera Applications diagnose programming problems as quickly as possible.

Source:	1992 Applications Handbook


Application Brief 82    Emulating Internal Buses in Classic, MAX & STG EPLDs

Altera Classic, MAX 5000, MAX 7000, and EPS464 STG devices allow internal buses to be emulated with multiplexers that replace tri-state functions. Multiplexers can save device resources and help eliminate timing and loading problems.

This application brief shows how to implement multiplexers for buses with two or more sources in both GDFs and AHDL TDFs. It also describes how multiplexing reduces timing hazards, capacitive loading, and the macrocell and pin resources required by a design.

The information in this application brief also applies to FLEX 8000 devices.

Source:	1992 Applications Handbook


Application Brief 83    Programmable Frequency Divider with the EP610 Classic EPLD

Although the EP610 and 22V10 devices have several features in common, the EP610 is a superior choice, both for hardware implementation and for design entry. Together with the MAX+PLUS II software, the EP610 device offers the ideal solution for implementing a programmable frequency divider in a single device.

This application brief contrasts the architecture and design support for the EP610 and 22V10 devices. It explains the benefits of the EP610 and includes a sample GDF that shows how to enter a programmable frequency divider with MAX+PLUS II FREQDIV and 74151 macrofunctions. A Prologic text file that implements the same design in a 22V10 is also included.

Source:	1992 Applications Handbook


Application Brief 84    DMA Controller with the EPM5064 MAX EPLD

The Altera EPM5064 MAX device offers the ideal solution for implementing Direct Memory Access (DMA) controllers: it integrates the advantages of the standard off-the-shelf DMA controller with the higher performance and flexibility of the TTL approach. A DMA controller implemented in an EPM5064 device can achieve data transfer rates of up to 20 megawords per second between peripheral and subsystem memory.

This application brief describes the EPM5064 device, the DMA process, and a sample DMA controller design implemented in an EPM5064 device. The hierarchical design for the sample DMA controller consists of GDFs and AHDL TDFs in three functional blocks: a bus interface unit, a DMA control state machine, and an address generator.

Source:	1992 Applications Handbook


Application Brief 86    Designing & Simulating Bidirectional Buses with MAX+PLUS II Software

With Altera’s MAX+PLUS II software, you can create, simulate, and implement designs that contain bidirectional buses in Altera Classic, MAX 5000, MAX 7000, and EPS464 STG devices.

This application brief describes how to create and verify logic that contains bidirectional buses, and includes guidelines for working with bidirectional bus logic. Sample GDFs and TDFs show how to implement bidirectional bus logic with tri-state (TRI) buffer primitives. SCFs are included to show the simulation results for the sample designs.

The information in this application brief also applies to FLEX 8000 devices.

Source:	1992 Applications Handbook


Application Brief 87    Troubleshooting Functional Problems in EPLDs

Common functional problems in devices can be diagnosed and solved by following the suggestions offered in this application brief.

This application brief offers a number of solutions based on whether a problem occurs immediately after power-up or after successful operation. Additional suggestions to solve timing problems are provided, as well as a troubleshooting checklist that can help you and Altera Applications diagnose functional problems as quickly as possible.

Some information in this application brief also applies to FLEX 8000 devices.

Source:	1992 Applications Handbook


Application Brief 88    Optimizing Counter Design for Altera EPLDs

Most logic designs contain one or more counters, which typically require a large number of routing resources. When routing resources are limited, a macrocell can be used for a look-ahead carry function to reduce the number of resources required for the counter and improve design performance.

This application brief describes both asynchronous (ripple) and synchronous counters. It shows the AHDL implementation of the CARRY macrofunction, a counter with a look-ahead carry function. The CARRY macrofunction includes optional up/down, enable, and borrow functions, and can be modified to accommodate counters of any size.

The CARRY macrofunction described in this application brief does not use, and is not related to the CARRY primitive available in MAX+PLUS II. Do not use the CARRY macrofunction and the CARRY primitive in the same project.

Source:	1992 Applications Handbook


Application Brief 89    Minimizing Output Switching Noise in Altera EPLDs

Load capacitance, ground path inductance, and the number of switching outputs all contribute to ground bounce in a design.

This application brief describes design practices that help minimize the effect of ground bounce. A model for analyzing ground bounce is also provided.

Some information in this application brief also applies to FLEX 8000 devices.

Source:	1992 Applications Handbook


Application Brief 91    External Clock Sources for Altera EPLDs

A system Clock is usually sufficient for the clocking requirements of designs implemented in Altera devices. If no system Clock is available, it must be generated to control the registered functions.

This application brief describes the two most common approaches used in device circuits: a direct-current (DC) Clock generator and a resistor/capacitor (RC) crystal network.

Source:	1992 Applications Handbook


Application Brief 92    Simulating Internal Nodes with MAX+PLUS II Software

MAX+PLUS II software can be used to verify logic graphically, both at the device pins and at internal nodes within the device. MAX+PLUS II allows you to choose the most appropriate method for identifying and simulating internal nodes, and to perform a thorough simulation in the shortest possible time.

This application brief describes how to simulate internal nodes with the MAX+PLUS II software. It explains the differences between the nodes in functional SNFs and timing SNFs. It also provides step-by-step guidelines on how to list all nodes and groups (buses) in a functional or timing SNF in either the Waveform Editor or the Simulator. All nodes that appear in the SNF can be simulated. With the Waveform Editor, you can create a default SCF and an optional Table File, either of which can be edited to provide the vector inputs for simulation. In addition, you can save a list to a History File with the Simulator.

This application brief explains how nodes and group types are listed differently in an SCF, Table File, or History File, and illustrates node-naming conventions. Node names can be pinstub/port-based names, explicitly named nodes, and probes.

This application brief includes guidelines for simulating state machines and combinatorial nodes, and shows a sample AHDL TDF and GDF. It also offers guidelines for placing nodes into an SCF or Vector File for simulation and shows a sample Vector File.

Source:	1992 Applications Handbook


Application Brief 93    Partitioning a Project with MAX+PLUS II Software

MAX+PLUS II allows you to create large designs without regard to the capacity of a particular device. Large projects can be partitioned among multiple devices from the same device family. Partitioning can be controlled with pin and buried macrocell assignments and with grouped logic for speed-critical paths.

This application brief describes how to partition a project automatically or manually with pin, macrocell, chip, clique, and device assignments. You can make these assignments either with menu commands in the Graphic, Text, and Waveform Editors or with a variety of statements in AHDL. Information on how the Compiler prioritizes assignments from different sources is included.

This application brief also describes how to back-annotate, preserve, and edit assignments, and shows a sample Fit File that can be edited and used as the Design Section of a TDF. It also includes information on how to simulate designs that have externally connected device pins.

Source:	1992 Applications Handbook


Application Brief 94    Solutions to Design Timing Problems for Altera EPLDs

Synchronous designs can eliminate common problems affecting circuit reliability and performance. They also protect circuits from timing problems caused by external factors such as silicon processes and temperature variations. Not only are synchronous designs immune to many of the timing problems of asynchronous designs, they are easier to design and test.

This application brief describes how to create designs that prevent or eliminate glitches, ripple-clocked counters, and asynchronous input signals with synchronous Clock, Clear, and Preset signals, and input registers. Several sample GDFs illustrate these synchronous design solutions.

Some information in this application brief also applies to FLEX 8000 devices.

Source:	1992 Applications Handbook


Application Brief 95    Designing Phase-Locked Loops with Altera EPLDs

The increased density and speed of Altera devices allow you to integrate functions previously reserved for analog circuitry. Applications that require functions such as edge detectors and phase-locked loops (PLLs), i.e., digital phase detectors, can be implemented with the digital logic provided by devices.

This application brief describes PLLs and explains how to implement them in Altera devices. It shows three different phase detectors (from simplest to most complex) created with XOR gates, SR latches, and NAND gates. Sample GDFs are included. The MAX+PLUS II PLL macrofunction, which contains both rising- and falling-edge detectors, is also described. Simulation results are presented for the implementation of the PLL macrofunction in EPS464, EPM5016, EPM5032, EPM5064, and EPM5128 devices.

Source:	1992 Applications Handbook


Application Brief 96    Generating Library Mapping Files

The Altera MAX+PLUS II development systems for the PC and workstation can compile and implement logic designs created with third-party PC- or workstation-based design entry tools. With LMFs and the MAX+PLUS II Compiler, you can convert a design file created with a third-party CAE tool into a file compatible with MAX+PLUS II. You can use Altera-provided LMFs, customize existing LMFs, or create your own LMFs.

This application brief explains how to use LMFs to map third-party function names to compatible Altera macrofunction or primitive names. It defines the required LMF syntax, offers design guidelines for LMFs, and provides several sample LMFs. It also includes a table that lists the existing LMF mappings for Mentor Graphics, Cadence, and Viewlogic macrofunctions.

Source:	Stand-alone application brief


Application Brief 97    Integrating EDIF Files with AHDL Files in Hierarchical Projects

Altera’s PC- and workstation-based MAX+PLUS II development systems allow you to combine designs created with multiple third-party workstation CAE tools into a single design, so you can choose the entry method best suited to each portion of the logic. On the workstation, you can enter designs as text files created in the Altera Hardware Description Language (AHDL), as third-party schematics, or as a mix of both text and schematics.

This application brief explains how to integrate an EDIF netlist file generated from a third-party design with an AHDL TDF. It describes two methods for integrating these files: using LMFs to map third-party macrofunctions in an EDIF netlist file to Altera macrofunctions, and creating a "hollow-body" (i.e., empty) symbol to represent an AHDL TDF so that it can be incorporated in a higher-level EDIF netlist file. The application brief includes step-by-step guidelines for creating hollow-body symbols with Cadence, Viewlogic, and Mentor Graphics tools. It also provides a sample schematic that incorporates MAX+PLUS II functions with both integration methods.

Source:	1992 Applications Handbook


Application Brief 98    Configuring Your PC for MAX+PLUS II Software

You can configure IBM PCs and compatible computers to improve system operation and performance while running MAX+PLUS II software under Microsoft Windows. This application brief includes information and recommendations on how to optimize your hardware configuration, fine-tune the config.sys file, set up a Windows swap file, maintain your hard disk, and check the memory configuration.

Source:	1992 Applications Handbook


Application Brief 99    Design Flow between Workstations & PCs

The PC-based MAX+PLUS II development system draws on the strengths of both workstation and PC platforms. Through Electronic Design Interchange Format (EDIF) version 2 0 0 netlist files, you can enter a design with a workstation CAE tool, process it quickly and easily on the PC with the MAX+PLUS II Compiler, use a third-party simulation tool for board-level simulation, and program one or more devices with either MAX+PLUS II or third-party programming software.

This application brief describes the design flow between the PC-based MAX+PLUS II software and third-party workstation CAE tools. It explains how to create a schematic design with a third-party tool, generate an EDIF netlist file, and rename it as a MAX+PLUS II EDIF Input File (.edf). It provides guidelines on using LMFs to map third-party macrofunctions to Altera macrofunctions and using "hollow-body" symbols to integrate other design files into EDIF Input Files. It also describes how the MAX+PLUS II Compiler generates an EDIF Output File (.edo) for use with a workstation simulation tool, and one or more programming files for use with MAX+PLUS II or third-party programming software.

This application brief lists the system requirements for the Cadence, Viewlogic, and Mentor Graphics interfaces; offers guidelines for design entry, processing, and simulation; and includes sample EDIF Command Files (.edc) for customizing an EDIF Output File for use with Cadence and Viewlogic simulation tools.

Source:	1992 Applications Handbook


Application Brief 100    Understanding Classic, MAX 5000 & MAX 7000 Timing

The architectures of Altera devices have fixed internal timing delays that are independent of routing. You can determine the worst-case timing delays for any design before a device is programmed. MAX+PLUS II development tools can automatically calculate delay paths, or you can hand-calculate delay paths by adding the timing delays for individual architectural elements, called microparameters, for an appropriate timing model. This ability to predict worst-case timing delays helps you ensure a design’s in-system timing performance.

This application brief defines device internal delay parameters and AC timing characteristics, and shows the timing models for Altera Classic, MAX 5000, and MAX 7000 devices. These timing models illustrate the internal delay paths for devices and show how these timing parameters affect each other. Several examples show how to add microparameters to calculate the delays for real applications.

Source:	current Data Book


Application Brief 119    High-Speed Board Designs

To create a successful high-speed PC board, you must integrate the device(s), board(s), and other elements into a coherent design. Altera devices typically provide 1- to 3-ns transfer rates, which contribute to noise generation, signal reflection, crosstalk, and ground bounce. Therefore, your design must distribute power cleanly and equally to all devices, terminate signal and transmission lines to reduce signal reflection, minimize crosstalk between parallel traces, and prevent high transient currents by reducing the effects of ground bounce.

This application brief describes the problems commonly encountered when designing high-speed PC boards using Altera's MAX 7000 and FLEX 8000 devices, as well as methods that help you design more successful systems.

Source:	FLEX 8000 Handbook


Application Brief 131    State Machine Encoding

Each state of a state machine can be represented with a unique pattern of high (1) and low (0) register output signals, a process called "encoding." The two primary encoding methods are binary and one-hot encoding.

This application brief describes both methods and discusses how to select the encoding scheme that best suits your design, so that you can ensure efficient performance and resource usage.

Source:	FLEX 8000 Handbook


Application Brief 143    Understanding FLEX 8000 Timing

The architectures of Altera devices have fixed internal timing delays that are independent of routing. You can determine the worst-case timing delays for any design before a device is programmed. MAX+PLUS II development tools can automatically calculate delay paths, or you can hand-calculate delay paths by adding the timing delays for individual architectural elements, called microparameters, for an appropriate timing model. (For the most accurate results, MAX+PLUS II Timing Analyzer calculations are preferred over hand-calculations.) The ability to predict worst-case timing delays helps you ensure a design’s in-system timing performance.

This application brief defines device internal delay parameters and AC timing characteristics, and shows the timing model for Altera FLEX 8000 devices. This timing model illustrates the internal delay paths for devices and shows how these timing parameters affect each other. Several examples show how to add microparameters to calculate the delays for real applications.

Source:	current Data Book


Application Brief 144    Understanding MAX 9000 Timing

The architectures of Altera devices have fixed internal timing delays that are independent of routing. You can determine the worst-case timing delays for any design before a device is programmed. MAX+PLUS II development tools can automatically calculate delay paths, or you can hand-calculate delay paths by adding the timing delays for individual architectural elements, called microparameters, for an appropriate timing model. This ability to predict worst-case timing delays helps you ensure a design’s in-system timing performance.

This application brief defines device internal delay parameters and AC timing characteristics, and shows the timing model for Altera MAX 9000 devices. This timing model illustrates the internal delay paths for devices and shows how these timing parameters affect each other. Several examples show how to add microparameters to calculate the delays for real applications.

Source:	current Data Book


Data Sheet    Electronic Bulletin Board Service

The Altera electronic bulletin board service (BBS) provides access to up-to-date device and development tool information, electronic application notes and briefs, data sheet updates, customer newsletters, and useful utility programs. The BBS also supports file transfers to and from the Altera Applications Engineering Department.

This data sheet describes the equipment and software configuration required to connect to the BBS. It also explains how to log onto the BBS and gives a list of the types of files that you can download.

Source:	1992 Applications Handbook or current Data Book


Data Sheet    Altera Device Package Outlines

Altera devices are available in a variety of packages. This data sheet provides information on available package types, lead materials, and lead finishes, as well as detailed package outlines for Altera Classic, MAX 5000/EPS464, MAX 7000, and FLEX 8000 devices.

Source:	current Data Book


Data Sheet    Operating Requirements for Altera Devices

Systems that use high-performance CMOS devices must be designed with care to obtain maximum performance from Altera devices.

This data sheet describes operating conditions for devices and precautions that minimize system noise. It also shows how to disable the programmable Turbo Bit (available in some Classic devices) for designs that require low-power operation. Additional topics include requirements for device erasure and erasure times, electrostatic discharge and latch-up protection in device pins, and accurate calculation of power information.

Some information in this application brief also applies to FLEX 8000 devices.

Source:	current Data Book


Data Sheet    QFP Carrier & Development Socket

The Altera QFP carrier and development socket protect the fragile leads on QFP devices during shipping and throughout the development cycle. QFP carrier and development socket combinations are available for all Altera QFP devices with 100 or more pins.

This data sheet describes the carrier and development socket and provides dimensions of each. It also gives step-by-step instructions for inserting and removing a device from the QFP carrier, inserting and removing the QFP carrier from the development socket, and programming a device in the QFP carrier. Ordering information is also included.

Source:	Stand-alone data sheet


Data Sheet    Thermal Resistance (°C/W)

This data sheet contains thermal resistance data for Altera Classic and MAX 5000 devices. Information is presented for each type of device package. Thermal resistance values were measured at 25° C ambient temperature with no backplane or heat sink, and are accurate to ±5° C/W.

Source:	current Data Book


Workbook    MPLD Conversion Information & Order Forms

This workbook contains information on converting an EPLD into a Mask-Programmed Logic Device (MPLD). MPLD conversion offers customers an efficient and cost-effective means to move from prototype development to high-volume, low-cost production.

This workbook answers basic questions about MPLDs and the conversion process. For a conversion quote, you must send Altera design files and the programmed EPLD(s) to a local sales office. An Altera engineer evaluates the design and offers suggestions on how to best implement it on an MPLD. You then receive information on the cost of conversion and price per unit. After you approve an EPLD programmed with the original design file optimized for MPLD production, prototype MPLDs are created. Once you approve these prototypes, you can then order production quantities.

This workbook includes the forms necessary for the conversion process.

Source:	Stand-alone workbook


Product Information Bulletin 14    Mask-Programmed Logic Devices: The Fastest Route to High-Volume Production

EPLD-to-MPLD conversion combines the advantages of the fast time-to-market of EPLDs with the low cost of MPLDs. This bulletin discusses key business issues to aid your decision-making and shows how Altera EPLDs and MPLDs can minimize the risk of developing a new product.

A point-by-point comparison of the EPLD/MPLD development process versus the gate array method illustrates the advantages of designing with EPLDs and MPLDs. The EPLD/MPLD strategy reduces time-to-market and cost. It also offers drop-in compatibility and automatic design-for testability. Altera’s test method is contrasted to traditional scan-based testing.

This product information bulletin also discusses N-to-1 MPLDs that merge multiple EPLDs into a single device for large-volume production.

Additional comparisons point out the economic advantages of using MPLDs instead of gate arrays in two critical areas: time-to-market and development expense. A detailed time-to-market analysis, which includes revenue and profit comparison, is presented for both the EPLD/MPLD and gate array strategies. Additional data tables compare development expenses, costs of design engineering resources, and costs of design tools for MPLDs versus gate arrays.

Source:	Stand-alone product information bulletin


Counter Applications (FLEX 8000 Handbook)

You can use a variety of design techniques and built-in FLEX 8000 architectural features to design counters that are optimized for area, speed, and/or routing.

The Counter Applications section of the FLEX 8000 Handbook describes techniques for designing counters for the FLEX 8000 architecture. Design files that use these techniques are available from the Altera BBS.

This section contains the following application briefs:

AB 121 (Designing Counters in FLEX 8000 Devices)

AB 137 (Ripple-Carry Counters in FLEX 8000 Devices)

AB 135 (Ripple-Carry Gray Code Counters in FLEX 8000 Devices)

AB 122 (Carry Look-Ahead Counters in FLEX 8000 Devices)

AB 123 (Pipelined Carry Look-Ahead Counters in FLEX 8000 Devices)

AB 124 (Prescaled Counters in FLEX 8000 Devices)

Source:	FLEX 8000 Handbook


Arithmetic Applications (FLEX 8000 Handbook)

You can use a variety of design techniques and built-in FLEX 8000 architectural features to design adders, accumulators, and subtractors that are optimized for area, speed, and/or routing.

The Arithmetic Applications section of the FLEX 8000 Handbook describes techniques for designing adders, accumulators, and subtractors for the FLEX 8000 architecture. Design files that use these techniques are available from the Altera BBS.

This section contains the following application briefs:

AB 125 (Designing Adders, Subtractors & Accumulators in FLEX 8000 Devices)

AB 118 (Ripple-Carry Adders in FLEX 8000 Devices)

AB 115 (Carry-Select Adders in FLEX 8000 Devices)

AB 111 (Carry Look-Ahead Counters in FLEX 8000 Devices)

AB 123 (Accumulators in FLEX 8000 Devices)

AB 126 (Subtractors in FLEX 8000 Devices)

Source:	FLEX 8000 Handbook


Miscellaneous Applications (FLEX 8000 Handbook)

You can use a variety of design techniques and built-in FLEX 8000 architectural features to design miscellaneous applications that are optimized for area, speed, and/or routing.

The Miscellaneous Applications section of the FLEX 8000 Handbook describes techniques for designing comparators, shifters, multiplexers and parity generators for the FLEX 8000 architecture. Design files that use these techniques are available from the Altera BBS.

This section contains the following application briefs:

AB113 (Equality Comparators in FLEX 8000 Devices)

AB114 (Full Comparators in FLEX 8000 Devices)

AB117 (Barrel Shifters in FLEX 8000 Devices)

AB128 (Multiplexers in FLEX 8000 Devices)

AB130 (Parity Generators in FLEX 8000 Devices)

Source:	FLEX 8000 Handbook


Multiplier Applications (FLEX 8000 Handbook)

You can use a variety of design techniques and built-in FLEX 8000 architectural features to design multipliers that are optimized for area, speed, and/or routing.

The Multiplier Applications section of the FLEX 8000 Handbook describes techniques for designing multipliers for the FLEX 8000 architecture. Design files that use these techniques are available from the Altera BBS.

This section contains the following application briefs:

AB127 (Designing Multipliers in FLEX 8000 Devices)

AB132 (Ripple-Carry Multipliers in FLEX 8000 Devices)

AB133 (Combinatorial Multipliers in FLEX 8000 Devices)

AB134 (Pipelined Multipliers in FLEX 8000 Devices)

Source:	FLEX 8000 Handbook


VHDL (2d edition)

by Douglas L. Perry

This book provides information on how to use the Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL). This book teaches the designer with only a rudimentary understanding of VHDL how to write complex VHDL descriptions concisely and accurately. It describes VHDL features, discusses the VHDL synthesis process, and then takes the designer step by step through the development and synthesis of a top-down design.

This book should be used together with the MAX+PLUS II VHDL manual, which provides information on how to use VHDL with MAX+PLUS II.


IEEE Standard VHDL Language Reference Manual (IEEE Std 1076-1987)

by the Institute of Electrical and Electronics Engineers, Inc.

This book describes in detail all Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) statements and constructs, as defined by IEEE Std 1076-1987. This book is a reference tool for specific VHDL constructs and statements; Altera recommends that novice VHDL users learn VHDL with the help of Douglas Perry’s VHDL.

MAX+PLUS II VHDL is a subset of the complete set of VHDL statements and constructs described in this book. IEEE Standard VHDL Language Reference Manual should be used together with the MAX+PLUS II VHDL manual, which provides information on how to use VHDL with MAX+PLUS II.


Programmer Basic Tools
Basic Tools

Buttons

Program

Verify

Examine

Blank-Check

Configure

Test

Stop

Open SCF

Fields

File

Device

Checksum

Copyright

Input & Output Files

Assignment & Configuration File (.acf)

ACF Format

Fit File (.fit)

Hexadecimal (Intel-format) File (.hex)

JEDEC File (.jed)

JTAG Chain File (.jcf)

JTAGINFO (.crf)

Programmer Log File (.plf)

Programmer Object File (.pof)

Raw Binary File (.rbf)

Simulator Channel File (.scf)

Serial Bitstream File (.sbf)

SRAM Object File (.sof)

Tabular Text File (.ttf)

Vector File (.vec)

Vector File Format

MAX+PLUS II Initialization & System Files

maxplus2.idx file

maxplus2.ini File

Options

Security Bit

Probe, Resource & Device Assignments

Clique Assignments

Connected Pin Assignments

Device Assignments

Logic Option Assignments

Pin, Location & Chip Assignments

Probe Assignments

Timing Requirements Assignments

Status Bar & Toolbar

Status Bar

Toolbar

Widgets

Module Boxes

Progress Bar


Program Button (Programmer)
Program Button

Programs data loaded from one or more programming files or an examined device onto one or more blank (i.e., erased) devices. You can use Program to program Classic, MAX 5000, MAX 7000, and MAX 9000 devices, and the FLASH memory of FLASHlogic devices. Devices can be programmed in both single-device and multi-device JTAG chain modes. Show me

Before you can program a device, you must do one of the following:

Insert a device into the socket of the appropriate adapter for the MPU and connect the MPU to your computer.

Mount a device that supports ISP (e.g., a MAX 9000 or FLASHlogic device) on the circuit board and connect the BitBlaster from an RS-232 serial port on your computer to the target system.

If the current project has more than one programming file, the first file is loaded automatically when you open the Programmer. You can select a different file with Select Programming File (File menu). The current file is displayed in the File field, and the current device name is displayed in the Device field. If you are programming multiple devices in a JTAG chain, multiple programming files are loaded automatically. "Multi-Device JTAG Chain"  is displayed in the Device field and "n Programming Files" in the File field.

You can turn on various options in the Programming Options dialog box (Options menu) to automatically blank-check, verify, or test the devices when they are programmed.

When you choose Program, the Programmer optionally blank-checks the device, programs the current programming file into the device, and optionally verifies the newly programmed contents of the device against the original programming data. In a multi-device JTAG chain, the Programmer programs each device in succession.

If the Test After Programming option is turned on in the Programming Options dialog box, the Programmer also functionally tests a single programmed device with the input vectors in the current SCF, Vector File, or programming file.

The Program button is not available if the current programming file is an SOF for a FLEX 8000 or FLEX 10K device. In these cases, you can use Configure instead to configure the FLEX 8000 or FLEX 10K devices.

You cannot program a device that is not supported by MAX+PLUS II. Available devices are listed in the Select Device dialog box (Options menu).

See also:

Blank-Checking a Device

Examining a Device

Inserting a Device into the Socket

Programming a Device with the BitBlaster

Programming a Device with the Master Programming Unit

Testing Device Outputs vs. Simulation Outputs

Verifying a Device


Configure Button (Programmer)
Configure Button

Downloads configuration data from one or more programming files into the SRAM of one or more FLEX 8000, FLEX 10K, or FLASHlogic devices. Devices can be configured in both single- and multi-device JTAG chain modes. Show me

Before you can configure a device, you must do one of the following:

Insert a FLASHlogic device into the socket of the appropriate adapter for the MPU and connect the MPU to your computer.

Mount a FLEX 8000, FLEX 10K, or FLASHlogic device on the circuit board and connect the BitBlaster from an RS-232 serial port serial port on your computer to the target system.

Mount a FLEX 8000 or FLEX 10K device on the circuit board and connect the FLEX Download Cable and the MPU from your computer to the target system.

When you choose Configure, the Programmer configures the device(s). To configure and functionally test a FLASHlogic device, turn on the Test After Programming option in the Programming Options dialog box (Options menu), before choosing Configure. You can thus check the functionality of the device without programming the EPROM or FLASH memory.

Configure is not available for devices that do not contain SRAM, i.e., Classic, MAX 5000, MAX 7000, and MAX 9000 devices. Instead, you can use Program to program these devices.

See also:

Configuring a Device with the BitBlaster

Configuring a Device with the FLEX Download Cable

Inserting a Device into the Socket

Testing Device Outputs vs. Simulation Outputs

Recommended reading:

AN33 (Configuring FLEX 8000 Devices)

AN38 (Configuring Multiple FLEX 8000 Devices)

AN59 (Configuring FLEX 10K Devices)


Verify Button (Programmer)
Verify Button

Verifies the contents of a device against programming data loaded from a programming file or examined device. Show me

Before you can verify a device, you must insert it into the socket of the appropriate adapter for the MPU or connect the BitBlaster to a target system containing a MAX 9000 or FLASHlogic device. The current device name or "Multi-Device JTAG Chain" is displayed in the Device field, depending on whether you are using single-device or multi-device JTAG chain programming mode.

When you choose Verify, the Programmer begins verifying the data in the device against the current programming data. The source of the programming data is shown in the File field.

You cannot verify a device that has been programmed with the Security Bit turned on, nor can you cannot verify FLEX 8000, FLEX 10K, and devices that are not supported by MAX+PLUS II. Available devices are listed in the Select Device dialog box (Options menu).

See also:

Examining a Device

Inserting a Device into the Socket

Programming a Device with the BitBlaster

Programming a Device with the Master Programming Unit

Verifying a Device


Examine Button (Programmer)
Examine Button

Examines a device and stores the programming data in a temporary data buffer. Show me

Before you can examine a device, you must make sure that the correct device name is displayed in the Device field and insert a device into the socket of the appropriate MPU adapter or connect the BitBlaster to a target system containing a MAX 9000 or FLASHlogic device. You can choose a device name with the Select Device command (Options menu). After you examine a device, "Untitled" appears in the File field.

You can use the programming data in the buffer to program or verify another device, or you can save the data to a file.

If you examine a device protected by the Security Bit, the data read from the device will be incorrect and cannot be used to correctly program another device.

You cannot examine FLEX 8000, FLEX 10K, and devices that are not supported by MAX+PLUS II. Available devices are listed in the Select Device dialog box.

See also:

Examining a Device

Inserting a Device into the Socket

Saving Programming Data to a File

Selecting a Device

Verifying a Device


Blank-Check Button (Programmer)
 Blank-Check Button

Examines a device to ensure that it is blank. Show me

Blank-checking simply indicates whether the device is blank, i.e., completely erased; it does not save the data it finds. You can use the Examine button to store data read from a device.

Before you can blank-check a device, you must make sure that the correct device name is displayed in the Device field and insert a device into the socket of the appropriate MPU adapter or connect the BitBlaster to a target system containing a MAX 9000 or FLASHlogic device. You can choose a device name with the Select Device command (Options menu).

If a device is not blank, it must be erased before it can be programmed. Expose EPROM-based Classic, MAX 5000, and MAX 7000 devices to continuous UV light for one hour to ensure complete erasure. While an extra 15 minutes will not damage the device, longer erasure times (e.g., overnight) are not recommended. Blank-checking and erasure are not required for EEPROM-, FLASH, or SRAM-based devices.

You can automatically blank-check a device during programming by turning on the Blank Check before Programming option in the Programming Options dialog box (Options menu).

You cannot blank-check FLEX 8000, FLEX 10K, and devices that are not supported by MAX+PLUS II. Available devices are listed in the Select Device dialog box.

See also:

Blank-Checking a Device

Inserting a Device into the Socket

Selecting a Device


Test Button (Programmer)
Test Button

Tests a programmed device with the input vectors in the current SCF, Vector File, or programming file and reports whether the output logic levels in the file are functionally equivalent to actual device outputs. Show me

1.	You can only functionally test a device for a single-device project. Since the SCF or Vector File used during testing is for an entire project (regardless of the number of devices in the project), it cannot be compared with the actual outputs of a single device that is part of a multi-device project. You also cannot test projects that contain bidirectional buses.

2.	Functional testing is not available for MAX 9000 devices that are programmed in-system or for FLEX 8000 and FLEX 10K devices. However, you can configure FLEX 8000 and FLEX 10K devices in-system for prototyping purposes, as described in Configuring a Device with the FLEX Download Cable and Configuring a FLEX 8000 or FLEX 10K Device with the BitBlaster.

3.	The Test button is unavailable in the workstation version of the Programmer. However, you can use Inputs/Outputs (File menu) to load and save test Vector Files into a POF or JEDEC File.

The Test button is available only if you have installed the MPU and the appropriate adapter, and if an SCF, Vector File, or programming file test vectors have been loaded for the project. In addition, the current device and the device that is contained in the current POF must be the same. The Fit File for the project, which contains pin assignment information, must be present in the project directory when testing is performed.

When you turn on the Test After Programming option in Programming Options (Options menu), the Program button automatically performs the same tasks as the Test button. When Test After Programming is on, the Programmer automatically loads the test vectors in the current programming file or the vectors in the SCF or Vector File with the same filename as the project. If the vectors are not loaded automatically, you must specify a file with Inputs/Outputs before testing a device. The Programmer automatically generates an SCF from a Vector File or a programming file before testing begins. You must also insert a device into the socket of the appropriate adapter for the MPU. The current device name is displayed in the Device field.

The time needed for testing is roughly proportional to the size of the SCF. If the SCF outputs are not functionally equivalent to the actual device outputs, a Message Processor window opens and reports differences between the SCF and device outputs.

You can save functional testing vectors into the current POF or JEDEC File with Save Programming Data As (File menu).

Significant restrictions apply to the inputs and outputs in SCFs used in functional testing. See Functional Testing with the SCF, Vector, or Programming File.

You cannot test a device that is not supported by MAX+PLUS II. Available devices are listed in the Select Device dialog box (Options menu).

See also:

Adapters

Inserting a Device into the Socket

Programming a Device with the Master Programming Unit

Programming Options Command

Saving Programming Data to a File

Testing Device Outputs vs. Simulation Outputs


Open SCF Button (Programmer)
Open SCF Button

Opens the functional testing vectors for the current project in a Waveform Editor window. Show me

When you open the Programmer window, the Programmer automatically loads any vectors that exist in the current POF or JEDEC File, or loads the newest SCF or Vector File with the same filename as the project. You can also specify a different file as the source of input vectors with Inputs/Outputs (File menu). When you choose Open SCF, the vectors are displayed in a Waveform Editor window. If the vectors were loaded from a JEDEC File or POF, this Waveform Editor window is untitled.

Open SCF is available only if an SCF or Vector File with the same name as the project exists in the project directory, if the current JEDEC File or POF contains test vectors, or if you have specified another source of input vectors with Inputs/Outputs.

See also:

Opening a File


Stop Button (Programmer)
 Stop Button

Interrupts the programming, verifying, examining, blank-checking, or testing process. Show me

You can stop the Programmer while it is verifying, examining, blank-checking, configuring, or testing a device, and then restart it.

If you stop the Programmer after choosing Program, you must erase the device completely before programming it again.


File Field (Programmer)
 File Field

Displays the name of the current programming file. If programming data has been read from an examined device, the field displays "Untitled." Show me

You can load a different POF, SOF, or JEDEC File for the current project with Select Programming File (File menu). Double-clicking Button 1 on the File field opens the Select Programming File dialog box. After you select a different programming file, the File field changes to display the name of the selected file.

If Multi-Device JTAG Chain (JTAG menu) is turned on, you can load multiple programming files with the Multi-Device JTAG Chain Setup or Restore JCF File command (JTAG menu). The File field displays "n Programming Files," where n is the number of programming files that are loaded, and  the Device field displays "Multi-Device JTAG Chain."

If you use Select Device (Options menu) to choose a device that is different from the device specified in the current programming file, the programming file is unloaded.

See also:

Examining a Device

Programming a Device with the BitBlaster

Programming a Device with the Master Programming Unit

Selecting a Programming File

Testing Device Outputs vs. Simulation Outputs

Verifying a Device


Device Field (Programmer)
Device Field

Displays the name of the current Altera device. Show me

By default, this field shows the device specified in the current programming file, or, if Multi-Device JTAG Chain (JTAG menu) is turned on, it displays the text "Multi-Device JTAG Chain." In single-device programming mode, you can change the device name with Select Device (Options menu). Double-clicking Button 1 on the Device field opens the Select Device dialog box. In multi-device JTAG chain programming mode, you can change the device names with Multi-Device JTAG Chain Setup or Restore JCF File (JTAG menu).

After you choose a device, you can insert the specified device into the socket of the appropriate adapter for the MPU and blank-check, examine, program, verify, or test the device.

See also:

Blank-Checking a Device

Examining a Device

Inserting a Device into the Socket

Programming a Device with the BitBlaster

Programming a Device with the Master Programming Unit

Selecting a Device

Testing Device Outputs vs. Simulation Outputs

Verifying a Device


Checksum Field (Programmer)
Checksum Field

Displays the checksum number for the current programming file. Show me

When you select a programming file, the Programmer automatically inserts the checksum number into the Checksum field. The checksum is used to compare a programming file with the data in a programmed device.

Although it is highly unlikely, two different programming files can have the same checksum.

See also:

Selecting a Programming File


Copyright Field (Programmer)
Copyright Field

Displays the copyright information for the latest examined device. Show me

When you choose Blank-Check, Configure, Examine, Program, or Verify, the Programmer automatically displays the device’s copyright information in the Copyright field.

This field appears only after you have blank-checked, configured, examined, programmed, or verified a device. It is not displayed after device testing or when the Programmer window is first opened.


Security Bit Option (Programmer)
Security Bit Option

Toggles the Security Bit for the current programming file before a device is programmed. If programming in single-device mode, the Security Bit option has two settings: on or off. If multiple programming files are loaded whose security settings differ, the Security Bit option has three settings: on, off, and tri-state (a gray check). The Security Bit can also be turned on for a programmed device. Show me

The Security Bit prevents a device from being examined or inadvertently reprogrammed. When a programming file is loaded, the Security Bit in the file has the setting that was specified in the top-level design file for the project or as the project-wide default in the Compiler. If multiple programming files are loaded with different security bit settings, the Security Bit option is displayed as a gray check.

The Programmer’s Security Bit option overrides the Security Bit setting specified in the programming file.

When the Security Bit option is turned on, all devices programmed will have their Security Bits on until the option is turned off.

When the Security Bit option is turned off, all devices programmed will have their Security Bits off.

When the Security Bit option is a gray check, the default settings, whether on or off, are used from each of the programming files for the devices.

1.	If you program an erasable device with the Security Bit on, you can erase it to remove both the design data and the Security Bit.

2.	If you examine a device that is protected by the Security Bit, the data read from the device is incorrect and cannot be used to correctly program another device.

3.	The Security Bit is not available in FLEX 8000, FLEX 8000M, FLEX 10K, or EPC1213 and EPC1064 Configuration EPROM devices.

See also:

Specifying Global Project Security Bit & Reserved Resource Settings

Setting the Security Bit (Programmer)


Module Boxes (Programmer)
Module Boxes

Change color as a device is examined (including blank-checking), configured, programmed, tested, or verified. Show me

The Programmer window displays module boxes for the following processes:

Examine

Program

Test

Verify

See also:

Blank-Checking a Device

Configuring a FLEX 8000 or FLEX 10K Device with the BitBlaster

Configuring a Device with the FLEX Download Cable

Examining a Device

Programming a Device with the BitBlaster

Programming a Device with the Master Programming Unit

Testing Device Outputs vs. Simulation Outputs

Verifying a Device


Progress Bar (Programmer)
Progress Bar

Shows how much of the current Programmer action has been completed. Show me

After you choose Program, Verify, Examine, Blank-Check, Configure, or Test, the progress bar shows how much of that action has been completed. When the progress bar reaches 100%, you can program, verify, examine, blank-check, configure, or test another device.


Hexadecimal (Intel-format) File (.hex) Description
Hexadecimal (Intel-format) File (.hex)

A hexadecimal file (with the extension .hex) in the Intel Hex format, generated by the Compiler’s Assembler module, that stores configuration data for one or more FLEX 8000 or FLEX 10K devices that are configured from a parallel data source.

The MAX+PLUS II Compiler and Programmer can create Hex Files by combining the SRAM Object Files generated during compilation with the Combine Programming Files command (File menu). This command creates a Hex File that can be programmed into a parallel EPROM or a mass storage device, which in turn configures one or more FLEX 8000 or FLEX 10K devices. The configuration data for a project is always placed into a single Hex File.

Hex Files can be used to implement the AS, APU, and APD configuration schemes for FLEX 8000 devices. Hex files can be used to implement the PS, PPA, and PPS configuration schemes for FLEX 10K devices. Configuration data can be created to allow bit-slice configuration of multiple devices.

The MAX+PLUS II Simulator can also generate Hex Files to store initialized memory values for use in initializing RAM or ROM memory blocks in a FLEX 10K device. You can use the Export Memory Content File dialog box (accessible through the Simulator’s Initialize Memory dialog box) to save data in Hex File (or Memory Initialization File (.mif)) format. You can also use the Import Memory Content File dialog box (also available through Initialize Memory) to load the data saved in a Hex File (or MIF) for use in memory initialization.

The file icon for a Hex File with the same filename as the top-level design file in the current hierarchy tree appears in the Hierarchy Display window.

Hex Files are not displayed in the Select Programming File (File menu) dialog box because the Programmer cannot read the format. Use the Windows File Manager, or type dir or ls at the system prompt to see the Hex Files.

For more information on the format of the Hex File, refer to the Intel Hexadecimal Object File Format Specification, available from Intel Corporation.

See also:

Combining & Converting SRAM Object Files

Configuring a Device with the FLEX Download Cable

Device Assignments

Exporting Memory Values

Importing Memory Values

Initializing RAM/ROM Memory

Pin, Location & Chip Assignments

Programming a Device with the BitBlaster

Programming a Device with the Master Programming Unit

Recommended reading:

AN33 (Configuring FLEX 8000 Devices)

AN38 (Configuring Multiple FLEX 8000 Devices)

AN59 (Configuring FLEX 10K Devices)


JEDEC File (.jed) Description
JEDEC File (.jed)

A file (with the extension .jed), generated by the Compiler’s Assembler module, MAX+PLUS (DOS), A+PLUS, or PLDshell Plus software, that contains the data used to program or configure a device. It can also contain functional testing vectors.

The MAX+PLUS II Compiler automatically generates JEDEC Files for all devices that support the JEDEC format. The MAX+PLUS II Programmer uses JEDEC Files to program or configure the following devices:

EP330/EP320/EP220

EP610/EP600

EP910/EP900

EP1810/EP1800

EPM5016

EPM5032

EPX740

EPX780 and EPX880

EPX8160

The Assembler automatically creates both a POF and JEDEC File for each device that supports the JEDEC format in the project. When the file(s) are created, a POF/JED file icon is displayed in the Compiler window. The filenames of the JEDEC File(s) are the same as the user-defined chip name(s) for the project; if you have not assigned chip names, the Compiler assigns names that are based on the project name. Example

You can save data that the Programmer has loaded from an examined device as a JEDEC File, and you can save a POF as a JEDEC File with the Programmer’s Save Programming Data As command (File menu). Similarly, any test vectors that are loaded in the Programmer can be saved to a JEDEC File or POF with Save Programming Data As.

You can double-click Button 1 on the POF/JED File icon in the Compiler window to open the Programmer window and load the POF for the project (or the first POF for a multi-device project), and then use Select Programming File (File menu) to load the JEDEC File.

See also:

Examining a Device

Pin, Location & Chip Assignments

Programming a Device with the Master Programming Unit

Saving Programming Data to a File (Programmer)

Selecting a Programming File

Recommended reading:

AN45 (Configuring FLASHlogic Devices)


Example: Compiler-Assigned Name for JEDEC File
If multiple programming files are generated, they are uniquely identified by a sequence number appended to the project name, e.g., if the project name is myproj, the first file is myproj.jed, the second is myproj1.jed, etc.

If you’re using MAX+PLUS II on a PC and the project name has 8 characters or less, MAX+PLUS II will truncate the filename if necessary to include the numerical index and maintain the 8-character filename length. If you use a project name with more than 8 characters, the numerical index is appended to it and characters are truncated only if the project name is too long.


JTAG Configuration File (.jcf) Description
JTAG Chain File (.jcf)

An ASCII text file (with the extension .jcf) that stores device names and optional programming file names for use in programming one or more devices in a JTAG chain. If the filename is absent, no programming file is associated with that device.

You can create a JCF file from the Multi-Device JTAG Chain Setup dialog box by choosing the Save JCF File button, or choosing Save JCF File (JTAG menu). You can create or rename as many JCF files as you wish.

You can load a JCF file from the Multi-Device JTAG Chain Setup dialog box by choosing the Restore JCF File button, or choosing Restore JCF File (JTAG menu).

When you save a JCF file, the programming file names are saved as relative pathnames unless they are on a different drive. When you restore a JCF file, the programming file names expand to full path names. You can copy the JCF file and associated programming files to another directory or diskette, and then load them.

You can use MAX 9000, FLASHlogic, FLEX 8000, FLEX 10K, or non-Altera SRAM devices in a JTAG chain.

See also:

JTAGINFO.CRF File Description

Loading JTAG Configuration Data from a File

Programming Devices in a Multi-Device JTAG Chain

Saving JTAG Configuration Data to a File


JTAGINFO.CRF File

An ASCII text file (with the extension .crf), located in the maxplus2 directory, that contains a list of devices that can be programmed in a JTAG chain. MAX+PLUS II creates the JTAGINFO.CRF file automatically.

The JTAGINFO.CRF file contains the information about the devices shown in the JTAG Device Attributes dialog box, the TAP count, and a flag indicating whether the device is an Altera device.

You can view the information in the JTAGINFO.CRF file. You also can move the JTAGINFO.CRF file into a different directory by setting JTAGINFO=<full path and filename> in the system section of maxplus2.ini. Example

You can use MAX 9000, FLASHlogic, FLEX 8000, FLEX 10K, or non-Altera SRAM devices in a JTAG chain.

See also:

JTAG Chain File (.jcf) Description

Programming Devices in a Multi-Device JTAG Chain


Example: Moving the JTAGINFO.CRF File into a Different Directory
To change the location of the JTAGINFO.CRF file on a PC:

JTAGINFO=c:\localmax\jtaginfo.crf

To change the location of the JTAGINFO.CRF file on a UNIX workstation:

JTAGINFO=c:/localmax/jtaginfo.crf


Programmer Log File (.plf) Description
Programmer Log File (.plf)

An ASCII text file (with the extension .plf) that contains a record of all Programmer commands, on-screen options, buttons, and messages from a Programmer session.

You begin command logging by turning on the Log (.plf) option in the dialog box for the Programmer’s Inputs/Outputs command (File menu). Command logging ends when you close the Programmer or turn off the Log (.plf) option. You can overwrite an existing PLF by turning on the New option; commands are appended to an existing PLF if you turn off the New option.

You can create as many PLFs as you wish during a single session, but only one can be active (i.e., turned on) at a time.

The file icon for a PLF with the same filename as the top-level design file in the current hierarchy tree appears in the Hierarchy Display window.

See also:

Logging Programmer Commands & Messages


Programmer Object File (.pof) Description
Programmer Object File (.pof)

A binary file (with the extension .pof), generated by the Compiler’s Assembler module, that contains the data used to program a device. It can also contain functional testing vectors.

The MAX+PLUS II Programmer uses POFs to program Classic, MAX 5000, MAX 7000, and MAX 9000 devices. The Compiler’s Assembler module creates a POF for each device in the project. The filenames of the POF(s) are the same as the user-defined chip name(s) for the project; if you have not assigned chip names, the Compiler assigns names that are based on the project name. Example

The Programmer also uses a POF to program an Altera serial Configuration EPROM, such as the EPC1213, that is used to configure a FLEX 8000 device in-system in an AS configuration scheme, or a FLEX 10K device in a Passive Serial configuration scheme. You can combine the SOFs for multiple FLEX 8000 or FLEX 10K devices to create one or more POFs with the Combine Programming Files command (File menu) in the MAX+PLUS II Programmer or Compiler. This POF can then be used for configuring multiple FLEX 8000 or FLEX 10K devices.

You can save data that the Programmer has loaded from an examined device to a POF, and you can save a JEDEC File as a POF with the Programmer’s Save Programming Data As command (File menu). Similarly, any test vectors that are loaded in the Programmer can be saved to a JEDEC File or POF with Save Programming Data As.

You can double-click Button 1 on the POF, POF+, or POF/JED file icon in the Compiler window to open the Programmer window and load the POF for the project (or the first POF for a multi-device project).

See also:

Combining & Converting SRAM Object Files

Pin, Location & Chip Assignments

Programming a Device with the BitBlaster

Programming a Device with the Master Programming Unit

Saving Programming Data to a File

Selecting a Programming File

Recommended reading:

AN33 (Configuring FLEX 8000 Devices)

AN38 (Configuring Multiple FLEX 8000 Devices)

AN45 (Configuring FLASHlogic Devices)

AN59 (Configuring FLEX 10K Devices)


Example: CMP-Assigned Name for POF
If multiple programming files are generated, they are uniquely identified by a sequence number appended to the project name, e.g., if the project name is myproj, the first file is myproj.pof, the second is myproj1.pof, etc.

If a chip requires two POFs, the second POF for the chip has an additional "_1" appended to the name, e.g., for a two-POF chip that is the third chip in the multi-chip project zproject, the POF names would be zprojec2.pof and zprojec2_1.pof. The filename of the second POF of a two-POF chip is not truncated to add the "_1" that distinguishes it from the first POF.


Raw Binary File (.rbf) Description
Raw Binary File (.rbf)

A binary file (with the extension .rbf), that stores configuration data for one or more FLEX 8000 or FLEX 10K devices that are configured from an intelligent external controller. An RBF is the binary equivalent of a Tabular Text File (.ttf)

In the MAX+PLUS II Compiler and Programmer, you can create an RBF by using the Combine Programming Files command (File menu) to combine the SRAM Object Files (.sof) generated during compilation. This command creates an RBF that contains data which can be used for an external controller, such as a microprocessor, that configures one or more FLEX 8000 or FLEX 10K devices.

You can use RBFs to implement the PS, PPS, and PPA configuration schemes for FLEX 8000 or FLEX 10K devices. When configuring a device in PS configuration scheme, be sure to send each byte of data with the least significant bit (LSB) first. You can create configuration data to allow bit-slice configuration of multiple devices.

See also:

Combining & Converting SRAM Object Files

Recommended reading:

AN33 (Configuring FLEX 8000 Devices)

AN38 (Configuring Multiple FLEX 8000 Devices)

AN59 (Configuring FLEX 10K Devices)


SRAM Object File (.sof) Description
SRAM Object File (.sof)

A binary file (with the extension .sof), generated by the Compiler’s Assembler module, that contains the data used to configure a FLEX 8000 or FLEX 10K device.

The MAX+PLUS II Programmer uses SOFs to configure FLEX 8000 or FLEX 10K devices. The Compiler’s Assembler module automatically creates an SOF and a POF, TTF, and Hex File for each device in the project. When the files have been created, a POF+ icon is displayed in the Compiler window. The filenames of the SOF(s) are the same as the user-defined chip name(s) for the project; if you have not assigned chip names, the Compiler assigns names that are based on the project name. Example

The Programmer uses a SOF to configure a FLEX 8000 or FLEX 10K device in-system with the FLEX Download Cable or the BitBlaster. With the Combine Programming Files command (File menu) in the Programmer or Compiler, you can also convert SOFs into POFs, Tabular Text Files, Hexadecimal (Intel-format) Files, Serial Bitstream Files, and Raw Binary Files that are used to configure FLEX 8000 or FLEX 10K devices with several different configuration schemes.

You can double-click Button 1 on the POF+ icon in the Compiler window to open the Programmer window and load the POF for the project (or the first POF for a multi-device project), and then use Select Programming File (File menu) to load the SOF.

See also:

Combining & Converting SRAM Object Files

Configuring a Device with the BitBlaster

Configuring a Device with the FLEX Download Cable

Pin, Location & Chip Assignments

Selecting a Programming File

Recommended reading:

AN33 (Configuring FLEX 8000 Devices)

AN38 (Configuring Multiple FLEX 8000 Devices)

AN59 (Configuring FLEX 10K Devices)


Example: CMP-Assigned Name for SOF
If multiple programming files are generated, they are uniquely identified by a sequence number appended to the project name, e.g., if the project name is myproj, the first file is myproj.sof, the second is myproj1.sof, etc.

If you're using MAX+PLUS II on a PC and the project name has 8 characters or less, MAX+PLUS II will truncate the filename if necessary to include the numerical index and maintain the 8-character filename length. If you use a project name with more than 8 characters, the numerical index is appended to it and characters are truncated only if the project name is too long.


Tabular Text File (.ttf) Description
Tabular Text File (.ttf)

An ASCII text file (with the extension .ttf) in a tabular format that stores configuration data for one or more FLEX 8000 or FLEX 10K devices that are configured from an intelligent external controller. A TFF is the ASCII equivalent of a Raw Binary File (.rbf).

The Compiler’s Assembler module automatically creates a TTF for each device in the project. The filenames of the TTFs are the same as the user-defined chip name(s) for the project; if you have not assigned chip names, the Compiler assigns names that are based on the project name. Example

In the MAX+PLUS II Compiler and Programmer, you can also create a TTF that allows bit-slice or sequential configuration of multiple devices by combining the SRAM Object Files generated during compilation with the Combine Programming Files command (File menu).

TTFs can be used to implement the PS, PPS, and PPA configuration schemes for FLEX 8000 or FLEX 10K devices. When configuring a device in PS configuration scheme, be sure to send each byte of data with the least significant bit (LSB) first.

The file icon for a TTF with the same filename as the top-level design file in the current hierarchy tree appears in the Hierarchy Display window.

See also:

Combining & Converting SRAM Object Files

Pin, Location & Chip Assignments

Recommended reading:

AN33 (Configuring FLEX 8000 Devices)

AN38 (Configuring Multiple FLEX 8000 Devices)

AN59 (Configuring FLEX 10K Devices)


Serial Bitstream File (.sbf) Description
Serial Bitstream File (.sbf)

An ASCII file (with the extension .sbf) that stores configuration data for one or more FLEX 8000 or FLEX 10K devices.

The MAX+PLUS II Compiler and Programmer can create SBFs by using the Combine Programming Files command (File menu) to combine the SRAM Object Files generated during compilation. You can use an SBF to configure a FLEX 8000 or FLEX 10K device in-system with the BitBlaster in a PS configuration schemes by copying the file to the COM port to which the BitBlaster is attached.

See also:

Combining & Converting SRAM Object Files

Configuring a FLEX 8000 or FLEX 10K Device with the BitBlaster

Programming a Device with the BitBlaster

Programming a Device with the Master Programming Unit

Recommended reading:

AN33 (Configuring FLEX 8000 Devices)

AN38 (Configuring Multiple FLEX 8000 Devices)

AN59 (Configuring FLEX 10K Devices)


Programmer Help Contents

Introduction

Basic Tools

Commands

Procedures

Golden Rules

Shortcuts

Messages


Programmer Introduction
Introduction

The MAX+PLUS II Programmer allows you to program, verify, examine, blank-check, configure, and test Altera Classic, MAX 5000, MAX 7000, MAX 9000, Configuration EPROM, FLEX 8000, FLEX 10K, FLASHlogic, and other devices. With the Programmer and programming hardware--the Altera MPU, add-on cards, programming adapters, the FLEX Download Cable, or the BitBlaster--you can easily create a working device in minutes. Show me

How Does the Programmer Work?

After the MAX+PLUS II Compiler has processed a project, it generates one or more programming files, which the Programmer uses to program or configure one or more devices. Before programming, you can use the Programmer to check that the device is blank. After programming, you can verify its contents against the data in the programming file. In addition, the Programmer allows you to examine a programmed device and save the data to a file, or use the data to program or verify another device.

You can download configuration data into SRAM for FLASHlogic, FLEX 8000, and FLEX 10K devices through the FLEX Download Cable or the BitBlaster for prototyping purposes. You can also program FLASHlogic and MAX 9000 devices with the BitBlaster. In addition, you can configure or program multiple devices in a JTAG chain using the BitBlaster.

You can test a device based on the current contents of the EPROM or FLASH memory. The Programmer uses an SCF or Vector File, or test vectors stored in the current programming file, to functionally test actual device outputs against simulation outputs. You can manually test a device or set up the Programmer to automatically perform functional testing.

The Programmer’s features include easy-to-use file conversion: POFs can be saved in JEDEC File format for use with other industry-standard programmers; SOFs can be converted into file formats that support other FLEX 8000 device configuration schemes.

Where to Start

Altera offers a variety of information to help you create designs and program devices with MAX+PLUS II and the Programmer.

On-Line Help

On-line help supplies complete reference and how-to information on programming and testing your devices.

Programmer Help Contents provides access to all on-line Programmer Help.

Programmer Golden Rules summarizes essential guidelines and recommendations for using the Programmer.

Devices & Adapters provides information on all Altera devices and adapters supported by MAX+PLUS II, including pin-outs and logic cell interconnections.

Recommended Reading

Additional Altera publications help you understand MAX+PLUS II and the Programmer. The following application notes, application briefs, and data sheets are relevant to using the Programmer:

AB81 (Troubleshooting EPLD Programming Problems)

AB87 (Troubleshooting Functional Problems in EPLDs)

AB141 (In-System Programmability in MAX 9000 Devices)

AB145 (Designing for In-System Programmability in MAX 7000S Devices)

AN33 (Configuring FLEX 8000 Devices)

AN38 (Configuring Multiple FLEX 8000 Devices)

AN39 (JTAG Boundary-Scan Testing in Altera Devices)

AN45 (Configuring FLASHlogic Devices)

AN59 (Configuring FLEX 10K Devices)

Information regarding specific devices and requirements for working with the Programmer is also available:

AB46 (Selecting Sockets for J-Lead Packages)

Altera Device Package Outlines Data Sheet

Operating Requirements for Altera Devices Data Sheet

QFP Carrier & Development Socket Data Sheet

See also:

How to Use MAX+PLUS II Help

PIB14 (Mask-Programmed Logic Devices: The Fastest Route to High-Volume Production)


Programmer Golden Rules
Golden Rules

The following guidelines will help you use the Programmer and Altera devices effectively:

Ensure that a device is completely erased before reprogramming it. Expose EPROM-based Classic, MAX 5000, and MAX 7000 devices to continuous UV light for one hour to ensure complete erasure. While an extra 15 minutes will not damage the device, longer erasure times (e.g., overnight) are not recommended. Erasure is not required for one-time-programmable, EEPROM-based or SRAM-based (e.g., FLEX 8000, FLEX 10K, and FLASHlogic) devices.

If you stop the Programmer during programming, the device may be partially programmed. Erase the device completely before reprogramming it.

You cannot program, verify, examine, blank-check, compile, or test a device that is not supported by or enabled in MAX+PLUS II. Available devices are listed in the Select Device dialog box (Options menu). To recognize device versions released after the latest MAX+PLUS II update, you must reconfigure your software. Contact the Altera Applications Department for the passwords for new device versions.

You cannot successfully examine or verify a device that has been programmed with the Security Bit turned on. The programming data read from an examined device is scrambled and cannot be used to program another device correctly.

The setting on the Programmer’s Security Bit option overrides the Security Bit option in the programming file generated by the Compiler.

If you program an erasable device with the Security Bit option turned on, you can erase the device to remove both the design data and the Security Bit. You can also program the Security Bit into a device that is already programmed.

You can only functionally test devices for single-device projects. Since an SCF or Vector File represents an entire project, it cannot be compared with the actual device outputs of a single device that is part of a multi-device project.

Ensure that the SCF, Vector File, or programming file used in functional testing conforms to the rules in Functional Testing with the SCF, Vector, or Programming File.

Be extremely careful when using high-pin-count J-lead and QFP packages. Pins can bend easily if the device is mishandled or inserted into the programming adapter incorrectly. Altera offers a QFP carrier and development socket that protects the device during the development cycle.

General MAX+PLUS II Golden Rules

When you start work on a new design file, name it as the current project with Project Set Project to Current File or Project Name (File menu) right away so you can compile it easily. You can always change the project name later.

Use the built-in hierarchy traversal features in MAX+PLUS II to move between design files for the current hierarchy tree. To open a lower-level file in a hierarchy, open the top-level file and then use the Hierarchy Display window or Hierarchy Down (File menu) to open the lower-level files. If you choose Open or Retrieve (File menu) to open a lower-level file, that file is considered to be the top of a different hierarchy tree, and resource, device, and probe assignments that you enter are saved only for that hierarchy, not for the project.

When you create an editable ancillary file for a project, the icon for the file will appear in the Hierarchy Display if you use the same filename as the project.

Don’t edit any MAX+PLUS II system files, including HIFs, Token Files (.tok), maxplus2.idx files, or the maxplus2.ini file.

Use the Save As command (File menu) if you wish to rename a design file or an ancillary file. Don’t rename design files from outside the MAX+PLUS II system (e.g., from DOS or with the Windows File Manager).

When you have completed a project, use Project Archive (File menu) to ensure that you save a complete backup copy of all project files that will not be affected by future edits or deletions.

See also:

Programmer Introduction


Programmer--Context-Sensitive Help
Programmer Context-Sensitive Help

Context-sensitive help is available for all Programmer commands, dialog boxes, and messages, and the following basic tools:

Buttons

Program

Verify

Examine

Blank-Check

Configure

Test

Stop

Open SCF

Fields

File

Device

Checksum

Copyright

Options

Security Bit

Status Bar & Toolbar

Status Bar

Toolbar

Widgets

Module Boxes

Progress Bar

For information on other basic tools, see Programmer Basic Tools.

See also:

Getting Context-Sensitive Help


Programmer Shortcuts
Shortcuts

The following list provides shortcuts for Programmer commands:

Command:	Shortcut:

Context-Sensitive Help	Shift+F1 or

Cascade	Shift+F5

Close	Alt+F4

Compiler

Exit MAX+PLUS II	Alt+F4 or double-click Button 1 on the Application Control Menu box

Floorplan Editor

Hierarchy Display

Hierarchy Project Top	Ctrl+T or

Info	Ctrl+I

New

Next	Ctrl+F6

Open	Ctrl+O or

Programmer

Project Name	Ctrl+J or

Project Save & Check	Ctrl+K or

Project Save & Compile	Ctrl+L or

Project Save & Simulate	Ctrl+Shift+L or

Project Save, Compile & Simulate	Ctrl+Shift+K

Project Set Project to Current File	Ctrl+Shift+J or

Save Programming Data As

Select Device	Double-click Button 1 on the Device field

Select Programming File	Double-click Button 1 on the File field or

Simulator

Switch To	Ctrl+Esc

Tile Horizontally	Shift+F4

Timing Analyzer

See also:

Selecting Text


Programmer Procedures
Procedures

Assignments & Compiler Configuration Settings

Assigning a Clique

Assigning a Device

Assigning a Pin, Location, or Chip

Assigning a Probe

Assigning an Individual Logic Option or Synthesis Style

Assigning Connected Pins

Assigning Individual Timing Requirements

Back-Annotating Assignments for a Project

Clearing Assignments for a Project

Converting an Obsolete Assignment Format

Copying a Resource Assignment

Defining a Logic Synthesis Style

Deleting an Assignment

Guidelines for Achieving Maximum Speed Performance

Guidelines for First-Time Project Fitting

Guidelines for Timing Assignments

Guidelines for Working with Assignments

Ignoring Project Assignments during Compilation

Logic Synthesis Style & Logic Option Rules

Searching the Node Database

Specifying Devices for Automatic Device Selection

Specifying Global Project Classic & MAX Device Options

Specifying Global Project FLEX 10K Device Options

Specifying Global Project FLEX 8000 Device Options

Specifying Global Project Logic Synthesis Settings

Specifying Global Project MAX 7000S Device Options

Specifying Global Project Parameters

Specifying Global Project Security Bit & Reserved Resource Settings

Specifying Global Project Timing Requirements

Specifying Individual Classic & MAX Device Options

Specifying Individual Device Security & Turbo Bit Options

Specifying Individual FLEX 10K Device Options

Specifying Individual FLEX 8000 Device & Pin Options

Specifying Individual MAX 7000S Device Options

Device Programming & Testing

Archiving JTAG Programming Files

Blank-Checking a Device

Changing the Hardware Setup

Configuring a FLASHlogic Device with the BitBlaster

Configuring a FLEX 8000 or FLEX 10K Device with the BitBlaster

Configuring a Device with the FLEX Download Cable

Enabling a New Device Version

Examining a Device

Inserting a Device into the Socket

Loading JTAG Configuration Data from a File

Modifying JTAG Device Attributes

Programming a Device with the BitBlaster

Programming a Device with the Master Programming Unit

Programming Devices in a Multi-Device JTAG Chain

Saving JTAG Configuration Data to a File

Selecting a Device

Setting the Security Bit

Testing Device Outputs vs. Simulation Outputs

Turning the Sound On & Off

Verifying a Device

File Management

Creating a New File

Getting Information on a File

Opening a File

Hierarchy

Navigating the Hierarchy

Updating the Hierarchy

Input & Output Files

Combining & Converting SRAM Object Files

Logging Programmer Commands & Messages

Saving Programming Data to a File

Selecting a Programming File

Specifying the Source of Input Vectors

MAX+PLUS II Management

Changing Colors in MAX+PLUS II

Closing a MAX+PLUS II Application

Creating & Using a Local Copy of the maxplus2.ini File

Entering an Authorization Code

Exiting from MAX+PLUS II Applications

Obtaining a Site License Authorization Code

Registering Your Software

Specifying a User Library

Starting MAX+PLUS II Applications

Switching Between MAX+PLUS II Applications

Messages

Getting Help on a Message

Locating the Source of a Message

Project Management

Archiving a Project

Changing the Project Name

Compiling a Project

Status Bar & Toolbar

Setting MAX+PLUS II Preferences

Text

Selecting Text


Archiving JTAG Programming Files (Programmer)
Archiving JTAG Programming Files

You can copy JTAG Chain Files (.jcf), used for programming multi-device JTAG chains, to the Archive Directory. For example, you could archive the JCF file onto a floppy diskette in drive a: or the LAN drive for others to use.

To archive a JCF file:

1.	Choose Archive JTAG Programming Files (File menu). The Archive JTAG Programming Files dialog box is displayed.

2.	The Archive Directory box is filled in with a directory name that matches the project name, and the JCF Name box with the name of the current JCF file.

or:

You can change the archive directory name by typing a new name in the Archive Directory box. If the directory does not exist, MAX+PLUS II will create it for you.

3.	To archive the JCF file under a new name, type a new name in the JCF Name box.

4.	If necessary, select a different drive and/or directory for the Archive Directory.

5.	Choose OK to archive the JCF file.

6.	If a JCF file is already in the Archive Directory, messages display asking if you wish to overwrite the file. Choose OK to overwrite the file.

The JCF file is saved in the specified Archive Directory.

See also:

Loading JTAG Configuration Data from a File

Programming Devices in a Multi-Device JTAG Chain

Saving JTAG Configuration Data to a File


Blank-Checking a Device (Programmer)
Blank-Checking a Device

You can examine a device to ensure that it is blank. Each device is automatically blank-checked before it is programmed if Blank-Check Before Programming is turned on in the Programming Options dialog box (Options menu). Blank-checking is not required for EEPROM, FLEX 8000, FLEX 10K, and FLASHlogic devices.

To manually blank-check a device:

1.	Make sure the correct device name is displayed in the Device field. If necessary, choose a different device name with the Select Device command (Options menu) or use a shortcut.

2.	Insert a device into the adapter socket of the MPU.

3.	Choose Blank-Check.

To automatically blank-check a device before programming it:

1.	Insert a device into the adapter socket of the MPU.

2.	Turn on the Blank-Check Before Programming option in the Programming Options dialog box.

3.	Choose Program.

The Programmer examines the device and issues a message indicating whether or not the device is blank. If a device is not blank, it must be erased before it can be programmed if it is an EPROM device.

See also:

Changing the Hardware Setup

Inserting a Device into the Socket

Programming a Device with the Master Programming Unit

Selecting a Device


Changing the Hardware Setup

If you install or change your programming hardware after installing MAX+PLUS II software, you must update the hardware setup in the Programmer or Simulator.

To change the hardware setup for Logic Programmer cards:

1.	Choose Hardware Setup (Options menu). The Hardware Setup dialog box is displayed.

2.	Choose Auto-Setup to automatically update the Hardware Type and I/O Address fields with the correct information for the currently installed hardware.

or:

Select the appropriate options in the Hardware Type and I/O Address drop-down list boxes.

3.	Optionally, choose Self-Test to test your hardware setup.

4.	Choose OK.

If necessary, you can change the LP6 Logic Programmer card dipswitch settings to use a different I/O address.

To change the hardware setup and the serial port's baud rate for the BitBlaster:

1.	Choose Hardware Setup. The Hardware Setup dialog box is displayed.

2.	Specify the COM port where the BitBlaster is installed in the COM Port box.

3.	If necessary, change the baud rate of the BitBlaster using the dipswitches on its side panel. You must ensure that the COM port and baud rate of the BitBlaster are the same as your computer's selected COM port and baud rate.

4.	Choose Auto-Setup to automatically update the Hardware Type and Baud Rate fields with the correct information for the currently installed hardware.

or:

Select BitBlaster in the Hardware Type and the desired baud rate in the Baud Rate drop-down list boxes.

4.	Optionally, choose Self-Test to test your hardware setup.

5.	Choose OK.

To change the baud rate for the BitBlaster on a workstation:

Specify your computer's serial port and set its baud rate. The baud rate of the BitBlaster must be the same as that of the computer’s serial port.

On a PC, type mode com<port number>:<baud rate> from a system prompt and press Enter.

On a workstation, follow the instructions provided in your workstation documentation.

The workstation version of the Programmer supports only the BitBlaster. The range of baud rates available for the workstation is more restricted than for the PC. If you cannot set the baud rate for the workstation, contact your system administrator for assistance.

See also:

MAX+PLUS II Installation in MAX+PLUS II Getting Started


Combining & Converting SRAM Object Files

You can combine and convert SRAM Object Files into Programmer Object File, Tabular Text File, or Hexadecimal (Intel-format) File formats that support several FLEX 8000 and FLEX 10K configuration schemes.

The Compiler automatically generates SOFs, POFs, TTFs, RBFs, and Hex files when you compile a FLEX 8000 or FLEX 10K project. After compilation, you can combine and convert the SOF(s) for one or more FLEX 8000 or FLEX 10K projects into a format compatible with a different configuration scheme.

To combine and convert SOFs for use with a different configuration scheme:

1.	Choose Combine Programming Files (File menu) in the Compiler or Programmer. The Combine Programming Files dialog box is displayed.

2.	If necessary, select a different drive and/or directory.

3.	if you wish to display SOFs only from the current project, turn on Show Only Project Files.

4.	Specify an Input File by typing a filename in the File Name box or by selecting a name from the Files box.

5.	Choose Add to add the SOF to the Selected Files box. Multiple sets of configuration data can be combined.

7.	If you wish to specify additional input files, repeat steps 4 and 5.

8.	If you wish to change the order of a selected file in the Selected Files box, choose Up or Down in the Order box. When the FLEX 8000 or FLEX 10K devices are mounted in-system, they are configured in the order specified in the Order box.

9.	If you wish to remove a selected file from the Selected Files box, choose Delete.

10.	Select the configuration file format from the File Format drop-down list box.

File Format:	Usage:

.pof (Sequential)	Conversion is required to combine configuration data for multiple FLEX 8000 or FLEX 10K devices. Supports AS configuration by Altera Configuration EPROM devices.

.hex (Single-Device)	Supports APU and APD configuration of a single FLEX 8000 device, or PPA and PPS configuration of a FLEX 10K device by a parallel data source.

.hex (Bit-Slice)	Supports bit-slice AS configuration by a parallel data source.

.sbf (Sequential)	Supports sequential PS configuration with the BitBlaster from a DOS or UNIX system prompt.

.ttf (Sequential)	Supports PPS, PPA, and PS configuration by an intelligent external controller. File is in text format.

.ttf (Bit-Slice)	Supports bit-slice PS configuration by an intelligent external controller. File is in text format.

.rbf (Sequential)	Supports sequential PPS, PPA, and PS configuration by an intelligent external controller. File is in binary format.

.rbf (Bit-Slice)	Supports bit-slice PS configuration by an intelligent external controller. File is in binary format.

11.	If you choose the .hex (Single-Device) option in the File Format box:

a.	Specify the memory address in the Address box. This address applies to the file listed in the Selected Files box.

b.	Choose Up or Down in the Count box to specify the APU or APD configuration scheme.

12.	If you choose the .pof (Sequential) option in the File Format box, you can select the Configuration EPROM from the EPROM box.

13.	Specify an Output File by typing a filename in the File Name box or by selecting a name from the Files box. The current project name is displayed as the default. If multiple POFs are generated, they are uniquely identified by a sequence number appended to the filename. Example

14.	Choose OK to combine and convert the SOFs.

See also:

Changing the Project Name

Configuring a FLEX 8000 or FLEX 10K Device with the BitBlaster

Configuring a Device with the FLEX Download Cable

Programming a Device with the Master Programming Unit

Saving Programming Data to a File

Recommended reading:

AN33 (Configuring FLEX 8000 Devices)

AN38 (Configuring Multiple FLEX 8000 Devices)

AN59 (Configuring FLEX 10K Devices)


Configuring a FLEX 8000 or FLEX 10K Device with the BitBlaster

You can configure FLEX 8000 or FLEX 10K devices in a PS configuration scheme in-system by downloading configuration data from an SBF or an SOF through the BitBlaster. On a PC, you can use the BitBlaster to configure a FLEX 8000 or FLEX 10K device using the Programmer or by typing a command at a DOS prompt. On a workstation, you can use the BitBlaster to configure a FLEX 8000 or FLEX 10K device at a UNIX system prompt.

To configure a FLEX 8000 or FLEX 10K device in single-device mode with the BitBlaster using the MAX+PLUS II Programmer:

1.	By default, when you first open the Programmer window, MAX+PLUS II loads the programming file for the current project (usually a POF), or the first programming file for a multi-device project. If the current programming file displayed in the Device field is not an SOF, use Select Programming File (File menu) or double-click on the File field to load an SOF for the current project or from another project.

2.	Turn off Multi-Device JTAG Chain (JTAG menu), if necessary, to use single-device mode.

3.	Attach the BitBlaster to an RS-232 cable that is connected to a COM port on the back panel of your computer and plug it into the prototype system that contains the device to be configured. The device name displayed in the Device field must match the device that is installed in the system.

4.	Specify your computer's serial port and set its baud rate using the Hardware Setup command (Options menu), if necessary. (See the Changing the Hardware Setup procedure.)

5.	Choose Configure.

To configure FLEX 10K devices in a multi-device JTAG chain with the BitBlaster:

1.	By default, when you first open the Programmer window, MAX+PLUS II loads all the programming files for the project. To load a specific programming file, choose Multi-Device JTAG Chain Setup (JTAG menu), then choose the Select Programming File button.

2.	Turn on Multi-Device JTAG Chain, if necessary, to use multi-device JTAG chain mode.

3.	Plug the BitBlaster into the prototype system that contains the devices to be configured. The device names displayed in the Multi-Device JTAG Chain Setup dialog box must match the devices that are installed on the system.

4.	Specify your computer's serial port and set its baud rate, as described in Changing the Hardware Setup.

5.	Choose Configure to configure each device in the JTAG chain.

To configure a FLEX 8000 or FLEX 10K device with the BitBlaster from a system prompt:

1.	Create an SBF with Combine Programming Files (File menu), as described in Combining & Converting SRAM Object Files.

2.	Attach the BitBlaster to an RS-232 cable that is connected to an RS-232 serial port (called a COM port on a PC) on the back panel of your computer and plug it into the prototype system that contains the device to be configured. The device name must match the device specified in the SBF.

3.	Specify your computer's serial port and set its baud rate, if necessary, as described in Changing the Hardware Setup.

4.	Configure the device by copying the SBF to the serial port to which the BitBlaster is attached.

On a PC, type copy <filename>.sbf com<port number>: from a system prompt and press Enter.

On a workstation, type cp <filename>.sbf /dev/<port identifier> from a system prompt and press Enter.

The BitBlaster downloads the data from the SBF into the device. Once the device is successfully configured, you can remove the BitBlaster. The FLEX 8000 or FLEX 10K device will continue to operate as long as it is powered up.

You can also convert SOFs into a format compatible with different configuration schemes with Combine Programming Files in the Compiler or Programmer.

See also:

Combining & Converting SRAM Object Files

Configuring a FLASHlogic Device with the BitBlaster

Programming a Device with the BitBlaster

Programming a Device with the Master Programming Unit

Programming Devices in a Multi-Device JTAG Chain

Selecting a Programming File

Testing Device Outputs vs. Simulation Outputs

Recommended reading:

BitBlaster Serial Download Cable Data Sheet

AN33 (Configuring FLEX 8000 Devices)

AN38 (Configuring Multiple FLEX 8000 Devices)

AN59 (Configuring FLEX 10K Devices)


Configuring a FLASHlogic Device with the BitBlaster

You can configure a FLASHlogic device in single-device or multi-device mode by downloading configuration data from a JEDEC File through the BitBlaster.

To configure a FLASHlogic device in single-device mode with the BitBlaster:

1.	If you wish to load a different JEDEC File, use Select Programming File (File menu) or double-click on the File field to load that file.

2.	Turn off Multi-Device JTAG Chain (JTAG menu), if necessary, to use single-device mode.

3.	Attach the BitBlaster to an RS-232 cable that is connected to a COM port on the back panel of your computer and plug it into the prototype system that contains the device to be configured. The device name displayed in the Device field must match the device that is installed in the system.

4.	Specify your computer's serial port and set its baud rate using the Hardware Setup command (Options menu), if necessary. (See the Changing the Hardware Setup procedure.)

5.	Choose Configure.

To configure FLASHlogic or other devices in a multi-device JTAG chain with the BitBlaster:

1.	By default, when you first open the Programmer window, MAX+PLUS II loads all the programming files for the project. To load a specific programming file, choose Multi-Device JTAG Chain Setup (JTAG menu), then choose the Select Programming File button.

2.	Turn on Multi-Device JTAG Chain, if necessary, to use multi-device JTAG chain mode.

3.	Plug the BitBlaster into the prototype system that contains the devices to be configured. The device names displayed in the Multi-Device JTAG Chain Setup dialog box must match the devices that are installed on the system.

4.	Set the baud rate using the Hardware Setup command, if necessary.

5.	Choose Configure to configure each device in the JTAG chain.

Once the device is successfully configured, you can remove the BitBlaster. The FLASHlogic device will continue to operate as long as it is powered up.

You must configure an EPX8160 FLASHlogic device in multi-device mode because it has two parts. Configure EPX8160_1 first; EPX8160_0 second. You can use different JEDEC Files to configure each part, if you wish.

See also:

Changing the Hardware Setup

Configuring a FLEX 8000 or FLEX 10K Device with the BitBlaster

Programming a Device with the BitBlaster

Programming a Device with the Master Programming Unit

Programming Devices in a Multi-Device JTAG Chain

Selecting a Programming File

Testing Device Outputs vs. Simulation Outputs

Recommended reading:

BitBlaster Serial Download Cable Data Sheet

AN45 (Configuring FLASHlogic Devices)


Configuring a Device with the FLEX Download Cable (Programmer)
Configuring a Device with the FLEX Download Cable

You can configure FLEX 8000, FLEX 8000M, or FLEX 10K devices in-system by downloading configuration data from a SOF through the FLEX Download Cable. To configure a FLEX 8000, FLEX 8000M, or FLEX 10K device:

1.	If the current programming file displayed in the Device field is not a SOF, choose Select Programming File (File menu) to load a SOF for the current project or a SOF from another project. By default, when you first open the Programmer window, MAX+PLUS II loads the programming file for the current project (usually a POF), or the first programming file for a multi-device project.

2.	Attach the FLEX Download Cable to the download cable connector on the Configuration EPROM adapter and plug it into the system that contains the FLEX 8000 or FLEX 10K device you wish to configure. The device name displayed in the Device field must match the device that is installed in the system.

4.	Choose Configure.

The Programmer downloads the data from the SOF into the device. Once the device is successfully configured, you can remove the FLEX Download Cable. The FLEX 8000 or FLEX 10K device will continue to operate as long as it is powered up.

You can also convert SOFs into a compatible format for use in different configuration schemes with the Combine Programming Files command (File menu) in the Compiler or Programmer.

See also:

Changing the Hardware Setup

Combining & Converting SRAM Object Files

Programming a Device with the Master Programming Unit

Selecting a Programming File

Testing Device Outputs vs. Simulation Outputs

Recommended reading:

AN33 (Configuring FLEX 8000 Devices)

AN38 (Configuring Multiple FLEX 8000 Devices)


Enabling a New Device Version (Programmer)
Enabling a New Device Version

A password allows MAX+PLUS II to recognize a new device version number. When a new device is released, its password must be added to the list of recognized passwords. Altera Applications Department provides all passwords necessary for each device.

To enable a new device version:

1.	Open the Select Device dialog box by choosing Select Device (Options menu) or using a shortcut.

2.	Choose the appropriate device name from the Available Devices box.

3.	Choose the Enable button to open the Enable New Device Version dialog box. The device name you chose in the Select Device dialog box is displayed in the Device box.

4.	Type the correct password in the Password box.

5.	Choose Add to add the new password to the Existing Passwords box.

6.	Choose OK to save all password changes.

If necessary, you can delete a password:

1.	Repeat steps 1 through 3 above.

2.	Type the password you wish to delete or choose it from the Password box.

3.	Choose Delete to delete the password from the Existing Passwords box.

4.	Choose OK to save all password changes.

See also:

Selecting a Device


Examining a Device (Programmer)
Examining a Device

You can examine a Classic, MAX 5000, MAX 7000, or MAX 9000 device, or the EPROM or FLASH memory of a FLASHlogic device. Examining a device enables you to read programming data from a device and store the data in a temporary data buffer. You can then save this information to a file or use the data to program or verify another device.

If you examine a device that is protected by the Security Bit, the data read from the device is incorrect and cannot be used to correctly program another device.

To examine a device:

1.	Make sure the correct device name is displayed in the Device field. If necessary, choose a different device name with the Select Device command (Options menu).

2.	Insert a device into the adapter socket of the MPU.

or:

Attach the BitBlaster to an RS-232 cable that is connected to a serial port on the back panel of your computer and plug it into a system that contains a MAX 9000 or FLASHlogic device.

3.	Choose Examine.

The Programmer unloads the current programming data (if any), examines the device, and places the data from the device into a temporary buffer. When data is in the buffer, the File field displays "Untitled." The programming data can then be saved to a file or used to program another device.

You cannot examine FLEX 8000 and FLEX 10K devices, and unsupported devices. Available devices are listed in the Select Device dialog box.

See also:

Changing the Hardware Setup

Inserting a Device into the Socket

Programming a Device with the Master Programming Unit

Saving Programming Data to a File


Getting Information on a File (Programmer)
Getting Information on a File

To get information on the current programming file:

Choose Info (File menu) or use a shortcut. The Info dialog box is displayed. The Programmer displays the following information for the current programming file:

Filename

File creation date

File Size (in bytes)

File CRC or file transmission checksum (in hexadecimal format)

Whether the device contains vectors for functional testing

Device name

Device data checksum

Device option settings

Other information, which can include the version of MAX+PLUS II that created the file, or comments such as those entered in the title block of the top-level GDF, the Title Statement of the top-level TDF, or in the comment field of a JEDEC File

or:

Choose the Info button in the Select Programming File dialog box (File menu).


Inserting a Device into the Socket

To blank-check, examine, test, configure, or program a device, you must have the appropriate adapter for the MPU.

To insert an adapter and a device into the adapter socket of the MPU:

1.	If necessary, pull the locking levers on the MPU up to the vertical position.

2.	Insert the correct adapter.

3.	Push the locking levers down.

4.	Insert a device of the device name, package type, and speed grade shown in the Device field of the Programmer window as follows. If no package type or speed grade is displayed, refer to the pin-out diagram in the Report File for the default package type and speed grade.

The following table shows how to insert each device package type into the socket.

Package	Package

Suffix:	Type:	Action:

B	BGA	Press down on the inside edge of the latch and lift it up to open the adapter. Use the triangular "pin 1" marking on the adapter to insert the device the right way up. Close the adapter lid and press the outside edge of the locking lever down.

D, P	DIP	Pull the locking lever on the adapter up, insert the device with the notched end at the top, and push the lever down.

J, L	J-Lead	Press down on the inside edge of the latch to open the adapter. Use the chamfer marked on the adapter to insert the device the right way up. Close the adapter lid and press the outside edge of the locking lever down.

G	PGA	Pull the locking lever on the adapter down. Use the guideline marked on the adapter to insert the device the right way up, and push the lever up.

S	SOIC	Press down on the rocker-type locking lever to open the adapter. Use the guideline marked on the adapter to insert the device the right way up. Since this type of package is quite small, you may wish to use a vacuum handling system to pick up and set down the device. Close the adapter lid and press the locking lever down.

Q, W, T, M, R	QFP	Press down on the inside edge of the latch to open the adapter. Use the guideline marked on the adapter to insert the device the right way up. Close the adapter lid and press the outside edge of the locking lever down.

See also:

Changing the Hardware Setup

Devices & Adapters

MAX+PLUS II Installation in MAX+PLUS II Getting Started for information on hardware requirements


Loading JTAG Configuration Data from a File (Programmer)
Loading JTAG Configuration Data from a File

You can load multi-device programming settings from a previously saved JCF file. Example

You can load a JCF file by choosing Restore JCF (JTAG menu) or by choosing the Restore JCF button in the Multi-Device JTAG Chain Setup dialog box.

To load the JCF file from the Multi-Device JTAG Chain Setup dialog box:

1.	Choose Multi-Device JTAG Chain Setup (JTAG menu). The Multi-Device JTAG Chain Setup dialog box is displayed.

2.	Choose the Restore JCF button. The Restore JCF dialog box is displayed.

3.	If necessary, select a different drive in the Drives box and/or directory in the Directories box.

4.	Select an existing JCF filename in the Files box; the filename is displayed in the File Name box.

5.	Choose the extension .jcf (your only choice) from the Automatic Extension drop-down list box.

6.	Choose OK.

After the JCF file is loaded, the device and programming file names are updated in the Multi-Device JTAG Chain Setup dialog box. Ensure that you loaded the correct JCF file. The names and order of the devices listed in this dialog box should match the devices installed on your system.

To load the JCF file from the menu:

1.	Choose Restore JCF (JTAG menu). The Restore JCF dialog box is displayed.

2.	If necessary, select a different drive in the Drives box and/or directory in the Directories box.

3.	Select an existing JCF filename in the Files box; the filename is displayed in the File Name box.

4.	Choose the extension .jcf (your only choice) from the Automatic Extension drop-down list box.

5.	Choose OK. After the JCF file is loaded, the Programmer window displays the text "Multi-Device JTAG Chain" and the number of programming files that are loaded.

6.	To verify that you loaded the correct JCF file, view the Device Names and Programming File Names information in the Multi-Device JTAG Chain Setup dialog box.

See also:

Archiving JTAG Programming Files

Programming Devices in a Multi-Device JTAG Chain

Saving JTAG Configuration Data to a File


The Multi-Device JTAG Chain Setup dialog box displays information about two FLASHlogic devices. The JCF file, chiptrip.jcf, contains the name of a FLEX 10K device and its associated programming file, chiptrip.sof. When you choose Restore JCF to load chiptrip.jcf, Multi-Device JTAG Chain Setup is updated with the information about the FLEX 10K device and chiptrip.sof.


Logging Programmer Commands & Messages (Programmer)
Logging Programmer Commands & Messages

You can use a Programmer Log File (.plf) to record Programmer menu commands and buttons used during a programming session, as well as Programmer messages reported in the Message Processor window.

To create a PLF:

1.	Choose Inputs/Outputs (File menu). The Inputs/Outputs dialog box is displayed.

2.	Turn on the Log (.plf) option. The text box for the option is then selected, and the Files box shows all files in the current directory with the extension .plf.

3.	if necessary, select a different drive and/or directory.

4.	Select an existing filename in the Files box or type a filename in the Log (.plf) box. The filename may contain up to eight name characters. If you type the name of a directory that does not exist, MAX+PLUS II will offer to create it for you.

5.	If you wish to create a file without any extension, type a period after the filename. Otherwise, the extension .plf is automatically appended to the filename.

6.	If you selected an existing filename in step 4, turn on the New option to overwrite the file. Otherwise all logged commands and messages are appended to the existing file.

7.	Choose OK to begin command and message logging.

See also:

Specifying the Source of Input Vectors


Modifying JTAG Device Attributes (Programmer)
Modifying JTAG Device Attributes

You can modify the parameters of existing devices or add new devices that support programming in a JTAG chain.

To add a new device to the list of JTAG devices:

1.	Choose Multi-Device JTAG Chain Setup (JTAG menu).

2.	In the Multi-Device JTAG Chain Setup dialog box, choose JTAG Device Attributes. The JTAG Device Attributes dialog box is displayed.

3.	To add a new device, type its name in the Device Name box.

4.	Update the fields Instruction Register Length, Boundary Scan Length, and JTAG ID Code with the necessary information for the device.

5.	Choose Add to add the device to the list in Existing JTAG Devices.

6.	Choose OK to add the device name to the Device Name drop-down list box in the Multi-Device JTAG Chain Setup dialog box.

To change a device in the list of JTAG devices:

1.	In the Multi-Device JTAG Chain Setup dialog box, choose JTAG Device Attributes. The JTAG Device Attributes dialog box is displayed.

2.	To change a device, select its name in Existing JTAG Devices in the JTAG Device Attributes dialog box. Update the fields Instruction Register Length, Boundary Scan Length, or JTAG ID Code with the changes for the device.

3.	Choose Change to update the device information.

4.	Choose OK to update the device parameters in the Device Name drop-down list box in the Multi-Device JTAG Chain Setup dialog box.

To delete a device from the list of JTAG devices:

1.	In the Multi-Device JTAG Chain Setup dialog box, choose JTAG Device Attributes. The JTAG Device Attributes dialog box is displayed.

2.	To delete a device, select its name in Existing JTAG Devices.

3.	Choose Delete to remove the device from the list in Existing JTAG Devices.

4.	Choose OK to delete the device from the Device Name drop-down list box in the Multi-Device JTAG Chain Setup dialog box.

See also:

Programming Devices in a Multi-Device JTAG Chain


Programming a Device with the Master Programming Unit (Programmer)
Programming a Device with the Master Programming Unit

You can use the Master Programming Unit to program a device in single-device mode. You can program a Classic, MAX 5000, MAX 7000, MAX 9000, or FLASHlogic device with programming data from a POF or JEDEC programming file, or data read from an examined device. You can also program other devices for which MAX+PLUS II offers programming-only support.

To program a device with the MPU:

1.	If you wish to change the current programming file displayed in the Device field, choose Select Programming File (File menu) to load a different programming file for the current project or a programming file from another project. You can also examine another device to obtain the data for device programming. By default, when you first open the Programmer window, MAX+PLUS II loads the programming file for the current project (usually a POF), or the first programming file for a multi-device project.

2.	If you wish to select a non-default input SCF or Vector File for post-programming testing, and/or specify a PLF to record Programmer actions, choose the Inputs/Outputs command (File menu). The Programmer automatically loads any functional testing vectors in the current programming file or in an SCF or Vector File with the same name as the project.

3.	Turn on Test After Programming in Programming Options (Options menu) if you wish to test a device with the input vectors in the current SCF, Vector File, or programming file.

4.	If you will program a device with the MPU, insert a device into the programming socket. The appropriate device is displayed in the Device field.

5.	Choose Program.

The Programmer examines the device, programs the current programming file into the device, and optionally verifies the newly programmed contents of the device against the original programming file.

If you stop the Programmer during programming, the device may be partially programmed. Ensure that a device is completely erased before reprogramming it. Expose EPROM-based Classic, MAX 5000, and MAX 7000 devices to continuous UV light for one hour to ensure complete erasure. While an extra 15 minutes will not damage the device, longer erasure times (e.g., overnight) are not recommended. Erasure is not required for EEPROM, FLASHlogic, or SRAM-based devices.

You need to use a JEDEC File to program a FLASHlogic device.

FLEX 8000 and FLEX 10K devices cannot be programmed. For information on configuring FLEX 8000 and FLEX 10K devices, go to Configuring a FLEX 8000 or FLEX 10K Device with the BitBlaster or Configuring a Device with the FLEX Download Cable.

You must use the BitBlaster to program devices in multi-device JTAG chain mode.

See also:

Changing the Hardware Setup

Examining a Device

Inserting a Device into the Socket

Logging Programmer Commands & Messages

Programming a Device with the BitBlaster

Specifying the Source of Input Vectors

Testing Device Outputs vs. Simulation Outputs

Recommended reading:

AB81 (Troubleshooting EPLD Programming Problems)

AB87 (Troubleshooting Functional Problems in EPLDs)

AN42 (Metastability in Altera Devices)


Programming a Device with the BitBlaster (Programmer)
Programming a Device with the BitBlaster

You can use the BitBlaster to program a device in single-device or multi-device mode. You can program FLASHlogic devices with programming data from JEDEC Files, and MAX 9000 devices with POF or JEDEC programming files.

FLEX 8000 and FLEX 10K devices cannot be programmed. For information on configuring FLEX 8000 and FLEX 10K devices, go to Configuring a FLEX 8000 or FLEX 10K Device with the BitBlaster or Configuring a Device with the FLEX Download Cable.

To program a device with the BitBlaster in single-device mode:

1.	By default, when you first open the Programmer window, MAX+PLUS II loads the programming file for the current project (usually a POF), or the first programming file for a multi-device project. If you wish to change the current programming file displayed in the Device field, choose Select Programming File (File menu) to load a different programming file for the current project or a programming file from another project.

2.	If you wish to select a non-default input SCF or Vector File for post-programming testing, and/or specify a PLF to record Programmer actions, choose the Inputs/Outputs command (File menu). The Programmer automatically loads any functional testing vectors in the current programming file or in an SCF or Vector File with the same name as the project.

3.	Turn on Test After Programming in Programming Options (Options menu) if you wish to test a device with the input vectors in the current SCF, Vector File, or programming file.

4.	To program a device in-system, mount the device on the circuit board and connect the BitBlaster from an RS-232 serial port on your computer to the target system. The appropriate device is displayed in the Device field.

4.	Choose Program.

The Programmer examines the device, programs the current programming file into the device, and optionally verifies the newly programmed contents of the device against the original programming file. Once the FLASHlogic device is successfully programmed, it will continue to operate as long as it is powered up.

To program FLASHlogic or MAX 9000 devices in a multi-device JTAG chain with the BitBlaster:

1.	By default, when you first open the Programmer window, MAX+PLUS II loads all the programming files for the project. To load a specific programming file, choose Multi-Device JTAG Chain Setup (JTAG menu), then choose the Select Programming File button.

2.	Turn on Multi-Device JTAG Chain, if necessary, to use multi-device JTAG chain mode.

3.	Mount the devices on the circuit board and connect the BitBlaster from an RS-232 serial port on your computer to the target system. The device names displayed in the Multi-Device JTAG Chain Setup dialog box must match the devices that are installed on the system.

4.	Choose Program to program each device in the JTAG chain.

If you stop the Programmer during programming, the device may be partially programmed. Erase a MAX 9000 device before reprogramming it. You do not need to erase FLASHlogic devices.

You must program an EPX8160 FLASHlogic device in multi-device mode because it has two parts. Program EPX8160_1 first; EPX8160_0 second. You can use different JEDEC Files to program each part, if you wish.

See also:

Changing the Hardware Setup

Examining a Device

Logging Programmer Commands & Messages

Programming a Device with the Master Programming Unit

Programming Devices in a Multi-Device JTAG Chain

Specifying the Source of Input Vectors

Testing Device Outputs vs. Simulation Outputs

Recommended reading:

BitBlaster Serial Download Cable Data Sheet

AB81 (Troubleshooting EPLD Programming Problems)

AB87 (Troubleshooting Functional Problems in EPLDs)

AN42 (Metastability in Altera Devices)


Programming Devices in a Multi-Device JTAG Chain (Programmer)
Programming Devices in a Multi-Device JTAG Chain

You can view, update, save, restore, or verify the settings for programming multiple devices in a JTAG chain.

You can program MAX 9000, FLASHlogic, FLEX 10K, and other devices, which support JTAG programming, in a JTAG chain using the BitBlaster.

To set up programming for multiple devices in a JTAG chain:

1.	Mount the devices on the circuit board and connect the BitBlaster as described in Programming a Device with the BitBlaster.

2.	Turn on Multi-Device JTAG Chain (JTAG menu), if necessary.

3.	Choose Multi-Device JTAG Chain Setup (JTAG menu). The Multi-Device JTAG Chain Setup dialog box is displayed.

4.	Choose JTAG Device Attributes only if you wish to modify the parameters of existing devices or to add a new device to the Device Name drop-down list box.

5.	Select a device name from the Device Name drop-down list box.

6.	If you wish to program the device, choose Select Programming File to select a programming file for that device.

7.	Choose Add to add the device and associated programming file to the Device Names and Programming File Names list box. The number to the left of the device name shows its order in the JTAG chain. The associated programming file is displayed on the same line as the device name in the Device Names box. If no programming file is associated with a device, "<none>" is displayed next to the device name, and that device is not programmed.

8.	Repeat steps 5 through 7 to add additional devices and optional programming files.

9.	Each time you add or change a device, the text below the Device Names list box is updated with the number of devices in the JTAG chain and the instruction register length. The number of devices and their total instruction register length in the List Contains and Use Hardware fields should match.

10.	If you wish to skip the hardware check, go directly to steps 13 and 14.

11.	Choose Detect JTAG Chain Info to verify that the names and the order of the devices listed in the Multi-Device JTAG Chain Setup dialog box match the devices installed on the system. A message is displayed with information about the devices, and the text in the Use Hardware group box is updated.

12.	If the message shows that the device selections are incorrect, update the selections so that the device names and their order match the devices installed on the system.

13.	If the message shows that the device selections are correct, choose Save JCF to save the settings.

14.	Choose OK.

Now you are ready to configure or program the devices. The devices are configured or programmed in the sequence in which they are connected in the chain. The first device in the chain receives TDI from the BitBlaster, and the last device transmits TDO to the BitBlaster.

To modify the devices or programming files listed in the Multi-Device JTAG Chain Setup dialog box:

1.	Open the Multi-Device JTAG Chain Setup dialog box.

2.	If you wish to change the order of a selected device in the Device Names box, choose Up or Down in the Order box. The devices will be programmed in the order specified in the Order box.

3.	If you want to change the device name, select the line containing the device name. Select a new device in the Device Name box.

4.	If you want to change the programming file name, select the line containing the device name. Select a new programming file in Select Programming File.

5.	Choose Change to update the device and/or programming file names.

6.	If you wish to remove a selected device from the Device Names box, choose Delete.

7.	If you wish to clear the Device Names box, choose Delete All.

8.	Choose Save JCF to save the settings.

9.	Choose OK.

Even when the numbers in the List Contains and Use Hardware fields match, the devices might be in the wrong sequence. Choose the Detect JTAG Chain Info button to verify that the device sequence, count, JTAG ID code, and total instruction length are correct.

See also:

Changing the Hardware Setup

Archiving JTAG Programming Files

Loading JTAG Configuration Data from a File

Modifying JTAG Device Attributes

Saving JTAG Configuration Data to a File

Selecting Programming File

Recommended reading:

AN39 (JTAG Boundary-Scan Testing in Altera Devices)


Saving JTAG Configuration Data to a File (Programmer)
Saving JTAG Configuration Data to a File

You can save the multi-device programming settings to a new JCF file. You can also use the Save JCF command to update or rename a JCF file.

You can save a JCF file by choosing Save JCF (JTAG menu) or the Save JCF button in the Multi-Device JTAG Chain Setup dialog box.

To save a JCF file from the Multi-Device JTAG Chain Setup dialog box:

1.	Choose Multi-Device JTAG Chain Setup (JTAG menu). The Multi-Device JTAG Chain Setup dialog box is displayed.

2.	Choose the Save JCF button. The Save JCF dialog box is displayed.

3.	If necessary, select a different drive in the Drives box and/or directory in the Directories box.

4.	Select an existing JCF filename in the Files box or type a new filename with up to eight name characters in the File Name box.

5.	Choose the extension .jcf (your only choice) from the Automatic Extension drop-down list box.

6.	Choose OK.

7.	If the file already exists, a message displays, "File <name> already exists. OK to overwrite?" Choose Yes to update the JCF file.

The JCF file is saved to the specified filename. The JCF file contains the device names and programming file names shown in the Multi-Device JTAG Chain Setup dialog box. If you choose Restore JCF, you can see the list of saved JCF files in the Files box.

To update or rename a JCF file using the menu:

1.	Choose Save JCF (JTAG menu). The Save JCF dialog box is displayed.

2.	If necessary, select a different drive in the Drives box and/or directory in the Directories box.

3.	Select an existing JCF filename in the Files box or type a new filename with up to eight name characters in the File Name box.

4.	Choose the extension .jcf (your only choice) from the Automatic Extension drop-down list box.

5.	Choose OK.

6.	If the file already exists, a message displays, "File <name> already exists. OK to overwrite?" Choose Yes to update the JCF file.

The JCF file is now updated.

See also:

Archiving JTAG Programming Files

Loading JTAG Configuration Data from a File

Programming Devices in a Multi-Device JTAG Chain


Saving Programming Data to a File (Programmer)
Saving Programming Data to a File

The Programmer allows you to save programming data for a single device in POF or JEDEC File format. You can save data that the Programmer has loaded from a file or data that has been read from an examined device.

You can also save data for configuring FLEX 8000 or FLEX 10K devices in different file formats. See Combining & Converting SRAM Object Files for information.

To save programming data to a POF or JEDEC File:

1.	Open the Save Programming Data As dialog box by choosing Save Programming Data As. (File menu) or using a shortcut.

2.	If necessary, select a different drive and/or directory.

3.	Select an existing filename in the Files box or type a filename with up to eight name characters in the File Name box. If you type the name of a directory that does not exist, MAX+PLUS II will offer to create it for you.

4.	To add test vectors to the current POF or JEDEC File, turn on Add Test Vectors to File. The file containing the vectors is shown under Vector Input File. If Add Test Vectors to File is disabled, or if you wish to specify a different source of vectors, choose Inputs/Outputs (File menu).

5.	To save the programming data in POF format, choose the extension .pof from the Automatic Extension drop-down list box. To save the programming data in JEDEC File format, choose the extension .jed.

6.	Choose OK.

The programming data and optional test vectors are saved under the specified filename.

You may save the programming data from any examined device to a file with Save Programming Data As. However, if the device you examined was protected by a Security Bit, the data in the programming file is incorrect and cannot be used to program another device correctly.

See also:

Examining a Device

Programming a Device with the Master Programming Unit

Specifying the Source of Input Vectors


Selecting a Device (Programmer)
Selecting a Device

Before you examine or blank-check a device, the correct device name must be displayed in the Device field of the Programmer window.

To select a device:

1.	Open the Select Device dialog box by choosing Select Device (Options menu) or using a shortcut.

2.	Choose a device family from the Device Family drop-down list box.

3.	If you wish to display only generic devices, i.e., devices without a package type, operating temperature, or speed grade, in the Available Devices box, turn on Show Only Generic Devices.

4.	Select a device in the Available Devices box.

5.	Choose OK.

The selected device name is displayed in the Device field.

If you choose a device that is different from the device specified in the current programming file, the programming file is unloaded.

See also:

Inserting a Device into the Socket


Selecting a Programming File (Programmer)
Selecting a Programming File

The data contained in a programming file is used to program or configure a device. If the current project has only one programming file, it is automatically loaded when you open the MAX+PLUS II Programmer. If the current project has multiple programming files, the first programming file is automatically loaded. You must load the other programming files manually to program other devices in a project if using single-device mode.

To select (load) a programming file in single-device mode:

1.	Open the Select Programming File dialog box by choosing Select Programming File (File menu) or using a shortcut.

2.	Select an existing name in the Files box or type a name in the File Name box. If you choose a programming file from another project, you are asked whether you wish to change the current project name.

3.	Choose OK.

After you have selected a name, it is displayed in the File field in the Programmer window. This file can then be programmed onto a blank device or used to verify a programmed device.

To load a programming file in multi-device mode:

1.	Turn on Multi-Device JTAG Chain  (JTAG menu), if necessary, to use multi-device mode. MAX+PLUS II loads all the programming files for the project.

2.	Choose Multi-Device JTAG Chain Setup (JTAG menu). The Multi-Device JTAG Chain Setup dialog box is displayed.

3.	Open the Select Programming File dialog box by choosing the Select Programming File button.

4.	Select an existing name in the Files box or type a name in the File Name box. If you choose a programming file from another project, you are asked whether you wish to change the current project name.

5.	Choose OK.

After you have selected a name, it is displayed in the Programming File Name field in the Multi-Device JTAG Chain Setup dialog box. This file can then be programmed onto one or more blank devices in a JTAG chain, or used to verify programmed devices.

See also:

Blank-Checking a Device

Changing the Project Name

Configuring a FLEX 8000 or FLEX 10K Device with the BitBlaster

Configuring a Device with the FLEX Download Cable

Programming a Device with the BitBlaster

Programming a Device with the Master Programming Unit

Verifying a Device


Setting the Security Bit (Programmer)
Setting the Security Bit

The Security Bit prevents a device from being examined or inadvertently reprogrammed. You can specify the Security Bit setting for each individual device, or multiple devices in a JTAG chain, or a project default setting, before compiling a project. After compilation, you can change the Security Bit setting before you program a device, overriding all previous settings. In addition, you can add a Security Bit to a programmed device that does not already have it.

When a programming file is first loaded in the Programmer, the Security Bit in the file has the setting that was specified before compilation. If multiple programming files are loaded with different security bit settings, the Security Bit option is displayed as a gray check.

Before compilation, you can enter Security Bit settings on a device-by-device basis with the Individual Device Options dialog box that is accessible from the Device Command (Options menu) of a top-level AHDL TDF. You can set the project-wide default with the Global Project Device Options command (Assign menu).

To toggle the Security Bit between on, off, or tri-state (use default settings) before programming a device:

Select the Security Bit option in the Programmer window.

To turn the Security Bit on for all programmed devices:

1.	Load the programming files for the devices. You can either examine a device that is inserted into the programming socket by choosing the Examine button, or load the file with the Select Programming File command (File menu) or button in the Multi-Device JTAG Chain Setup dialog box (JTAG menu).

2.	If necessary, insert the device into the programming socket. The appropriate device to insert is displayed in the Device field or Multi-Device JTAG Chain Setup dialog box.

3.	Turn on the Security Bit option in the Programmer window.

4.	Choose Program.

All devices programmed when the Security Bit option is on will have their Security Bits turned on. When you erase a device, the Security Bit is also erased.

If you examine a device that is protected by the Security Bit, the data read from the device is scrambled and cannot be used to correctly program another device.

See also:

Examining a Device

Inserting a Device into the Socket

Programming a Device with the Master Programming Unit

Selecting a Programming File


Specifying the Source of Input Vectors (Programmer)
Specifying the Source of Input Vectors

You can use the input vectors in an SCF, Vector File, or the current programming file to test a programmed Classic, MAX 5000, MAX 7000, MAX 9000, or FLASHlogic device to determine whether the simulated output logic levels in the file are functionally equivalent to the actual device outputs.

If no test vector source has been specified for the project, the Programmer automatically loads any test vectors in the current programming file. If the programming file does not contain test vectors, the Programmer automatically loads the newest Vector File or SCF with the same filename as the project. Therefore, you need to specify a file explicitly only if the desired vectors are in a different file.

To load input vectors from an SCF, a Vector File, or the current programming file:

1.	Choose Inputs/Outputs (File menu). The Inputs/Outputs dialog box is displayed.

2.	Turn on the Input File option.

3.	To list files of a specific type in the Files box, select a file type from the Show Files in List box. The Files box shows all files in the current directory of the file type that you have chosen.

4.	If necessary, select a different drive and/or directory.

5.	If you wish to use a non-default source of input vectors, select an existing filename in the Files box or type a filename in the Input File box.

6.	If you typed a filename in step 5, type a filename extension, or type a period (.) after the filename to specify a Vector File without any extension. Otherwise, the extension .scf is automatically appended to the filename.

7.	Choose OK.

After you have loaded input vectors, you can save the vectors to a programming file, as described in Saving Programming Data to a File.

See also:

Functional Testing with the SCF, Vector File, or Programming File

Logging Programmer Commands & Messages

Programming a Device with the Master Programming Unit

Testing Device Outputs vs. Simulation Outputs


Turning the Sound On & Off (Programmer)
Turning the Sound On & Off

You can use the sound feature to alert you when the Programmer has finished programming, configuring, verifying, examining, blank-checking, or testing a device.

To turn the sound on and off:

Choose Sound.


Verifying a Device (Programmer)
Verifying a Device

After you have programmed a device, you can verify its contents against the programming data in a programming file, or against data that has been read from an examined device.

You cannot successfully verify a device that has been programmed with the Security Bit turned on.

To verify a device:

1.	Load the data to use for verification by selecting a programming file with the Select Programming File command (File menu) or examining a device with the Examine button. The appropriate device for the programming data is displayed in the Device field.

2.	Insert a programmed device of the same type used in step 1 into the adapter socket of the MPU.

or:

Attach the BitBlaster to an RS-232 cable that is connected to a serial port on the back panel of your computer and plug it into a system that contains a programmed MAX 9000 or FLASHlogic device of the same type used in step 1.

3.	Choose Verify.

The Programmer verifies the design data in the device against the current programming data.

An unsuccessful verification indicates one of the following problems:

The Security Bit is programmed into the device.

The programming data in the device is not the same as the data in the programming file or the data buffer.

The MPU, BitBlaster, or device is not functioning correctly.

To change the options for verifying a device:

1.	Choose Programming Options (Options menu). The Programming Options dialog box is displayed.

2.	If you wish to verify the data in the device during programming, turn on the Verify During Programming option.

or:

If you wish to verify the data in the device after it is programmed, turn on the Verify After Programming option.

or:

If you wish to skip the verify passes, uncheck the Verify During Programming and Verify After Programming options.

3.	Choose OK.

4.	Choose Verify.

See also:

Changing the Hardware Setup

Examining a Device

Inserting a Device into the Socket

Programming a Device with the Master Programming Unit

Programming Options

Selecting a Programming File


-----BEGINNING OF NON-TRANSLATED TEXT-----

Messages from pgmmsgs.msg and f2pmsgs.msg are documented in this file.

Messages from other applications that are documented in this file:

SSIM_EMPTY_SOCKET	simmsgs.msg

SSIM_CONTINUITY_FAILED	simmsgs.msg

WSIM_CANT_FIND_PIN	simmsgs.msg

ssim_backwards	simmsgs.msg

ssim_wrong_adapter	simmsgs.msg

ssim_epld_not_supported	simmsgs.msg

ssim_unknown_part	simmsgs.msg

ssim_sram_cfg_failure	simmsgs.msg

Messages from pgmmsgs.msg that are documented elsewhere:

CPGM_ABORT_OPERATION	comess.mac

cpgm_ok_to_overwrite	glmess

SPGM_FILE_BUSY	simess.mac

spgm_path_not_found	glmess

spgm_archive_dir_is_file	glmess

-----END OF NON-TRANSLATED TEXT-----


Adapter <name> is incompatible with this version of device <name>. Contact Altera Applications.
Adapter <name> is incompatible with this version of device <name>. Contact Altera Applications for up-to-date adapter information.

CAUSE:	The current device is incompatible with the current version of the programming adapter. This error can occur if, for example, you insert an EPM5128AJC-20 device into a PLEJ5128 adapter.

ACTION:	Install the latest version of the adapter. Refer to Adapters or contact Altera Applications Department for up-to-date information on adapter availability.

See also:

MAX+PLUS II Messages

Message Format


BitBlaster is not connected to a device

CAUSE:	You tried to configure a device, but MAX+PLUS II could not complete the task. The BitBlaster is properly connected to your PC or workstation, but no device is connected to the BitBlaster, or the device connected to the BitBlaster is not a FLEX 8000, FLEX 10K, FLASHlogic, or MAX 9000 device.

ACTION:	Make sure that a FLEX 8000, FLEX 10K, FLASHlogic, or MAX 9000 device is connected to the BitBlaster and try again.

See also:

Configuring a FLASHlogic Device with the BitBlaster

Configuring a FLEX 8000 or FLEX 10K Device with the BitBlaster

MAX+PLUS II Messages

Message Format

Programming a Device with the BitBlaster

Programming a Device with the Master Programming Unit


BitBlaster is not <text> -- check <text>

CAUSE:	The BitBlaster is either not properly connected to the PC or workstation, is not receiving power, or has a baud rate that does not match the baud rate of the COM port to which it is connected. The <text> of the message suggests the most likely cause of the problem.

ACTION:	Ensure that the connections between the COM port on your PC or workstation, the RS-232 serial cable, and the BitBlaster are secure. Check that the baud rate set with the BitBlaster dipswitch settings matches the baud rate set in the Hardware Setup dialog box (Options menu). Also ensure that the target system is powered up: the BitBlaster draws its power from the target system and cannot operate if it is not powered up.

See also:

Changing the Hardware Setup

Configuring a FLASHlogic Device with the BitBlaster

Configuring a FLEX 8000 or FLEX 10K Device with the BitBlaster

MAX+PLUS II Messages

Message Format

Programming a Device with the BitBlaster


Baud rate not supported by <COM port>

CAUSE:	The COM port to which the BitBlaster is connected does not support the baud rate you specified for it with the Hardware Setup command (Options menu) and BitBlaster dipswitch settings.

ACTION:	Change the baud rate setting for the COM port and/or the BitBlaster to one that is supported by the COM port. You can change the baud rate setting for the COM port from a system prompt or with the COM Port drop-down list box in the Hardware Setup dialog box (Options menu). You can change the BitBlaster’s baud rate using the dipswitches on the side of the BitBlaster. If you cannot set the baud rate for the workstation version of the Programmer, contact your system administrator for assistance. The range of baud rates available for the workstation is more restricted than for the PC.

See also:

Changing the Hardware Setup

Configuring a FLASHlogic Device with the BitBlaster

Configuring a FLEX 8000 or FLEX 10K Device with the BitBlaster

MAX+PLUS II Messages

Message Format


Blank-Check successful: <number> devices blank-checked

CAUSE:	You successfully blank-checked multiple devices.

ACTION:	No action is required.

See also:

Blank-Checking a Device

MAX+PLUS II Messages

Message Format


Can't access device driver for Altera Programmer
Can’t access device driver for Altera Programmer

CAUSE:	MAX+PLUS II cannot access the Altera Programmer driver that is needed in systems operating under Windows NT. This error occurs if you have the wrong version of the driver, or if the driver is not installed.

ACTION:	Install or re-install the Altera Programmer driver for Windows NT, as described in MAX+PLUS II Installation in MAX+PLUS II Getting Started. If problems persist, call Altera Applications Department.

See also:

MAX+PLUS II Messages

Message Format


Can't access the <hardware type> hardware
Can’t access the <hardware type> hardware

CAUSE:	MAX+PLUS II cannot find the specified programming hardware. Either the I/O address entered in the Hardware Setup dialog box (Options menu) is invalid, or the hardware driver for the programming card is missing or corrupted.

ACTION:	Choose a different I/O address from the I/O Address drop-down list box in the Hardware Setup dialog box. If you have verified the programming card I/O address, you may need to reinstall MAX+PLUS II to update the hardware driver. If the problem persists, call Altera Applications Department.

See also:

Changing the Hardware Setup

MAX+PLUS II Messages

Message Format

MAX+PLUS II Installation in MAX+PLUS II Getting Started


Can't change the JTAG attributes of device <name>

CAUSE:	You attempted to change the JTAG attributes of an Altera-provided device.

ACTION:	No action is required because you cannot change the JTAG attributes of an Altera-provided device. However, you can change the JTAG attributes of a non-Altera device by choosing Multi-Device JTAG Chain Setup (JTAG menu) and opening the JTAG Device Attributes dialog box.

See also:

MAX+PLUS II Messages

Message Format

Modifying JTAG Device Attributes

Programming Devices in a Multi-Device JTAG Chain


Can’t combine more than <number> files for bit-slice configuration

CAUSE:	You tried to add more than the specified number of SOFs to be combined for bit-slice configuration of FLEX 8000 or FLEX 10K devices to the Selected Files box in the Combine Programming Files dialog box (File menu).

ACTION:	Reduce the number of files used. If you wish to use more than the specified number of FLEX 8000 or FLEX 10K devices in your application, you must configure two or more groups of devices separately.

See also:

Combining & Converting SRAM Object Files

MAX+PLUS II Messages

Message Format

Recommended reading:

AN33 (Configuring FLEX 8000 Devices)

AN59 (Configuring FLEX 10K Devices)


Can't combine programming files from different device families

CAUSE:	You selected SOFs for FLEX 8000 and FLEX 10K device families in the Selected Files box in the Combine Programming Files dialog box (File menu).

ACTION:	Make sure only SOFs from the same device family are present in the Selected Files box in the Combine Programming Files dialog box.

See also:

Combining & Converting SRAM Object Files

MAX+PLUS II Messages

Message Format


Can’t continue hardware tests -- programming adapter is installed on the <name> unit

CAUSE:	You chose the Test button in the Hardware Setup dialog box (Options menu), but an adapter is installed on the programming unit. The hardware tests cannot run if an adapter is installed on the programming unit.

ACTION:	Remove the adapter and try again.

See also:

MAX+PLUS II Messages

Message Format


Can’t find programming card <programming card> at I/O address <I/O address>

CAUSE:	MAX+PLUS II cannot find a programming card at the I/O address you specified in the Hardware Setup dialog box (Options menu). You may have specified the wrong I/O address, the programming card may not be installed, or the programming card may be damaged.

ACTION:	Ensure that a programming card is installed at the I/O address specified in the I/O Address drop-down list box in the Hardware Setup dialog box. You can choose the Auto-Setup button to automatically update the I/O Address box.

See also:

Changing the Hardware Setup

MAX+PLUS II Installation in MAX+PLUS II Getting Started

MAX+PLUS II Messages

Message Format


Can’t find programming file <name> for the current project

CAUSE:	MAX+PLUS II cannot find the specified programming file, which is listed in the Fit File for the current project. You may have moved, deleted, or renamed the file.

ACTION:	If the file does not exist, you must recompile the project to regenerate the specified file. If you simply moved or renamed the file and you wish to perform post-programming functional testing, you must change the file’s name to its original name in the project directory before you can functionally test the device. (Both the Fit File and the programming file must specify the same filename to allow functional testing.) If you do not wish to perform post-programming testing, you can use Select Programming File (File menu) to select the modified filename, and then program the device.

See also:

MAX+PLUS II Messages

Message Format

Selecting a Programming File


Can’t find programming hardware -- use Hardware Setup command to set up hardware

CAUSE:	You opened the Programmer window, but you have not specified the correct location of the programming hardware, or the current programming hardware is not properly installed.

ACTION:	Make sure that the programming hardware is properly installed. Choose Hardware Setup (Options menu) and specify the programming hardware in the Hardware Type drop-down list box, or choose the Auto-Setup button to automatically determine which programming hardware is installed on your computer.

See also:

Changing the Hardware Setup

MAX+PLUS II Installation in MAX+PLUS II Getting Started

MAX+PLUS II Messages

Message Format


Can’t find programming unit <name>

CAUSE:	MAX+PLUS II cannot find the specified programming unit. The programming unit may not be attached to the programming card, or the programming unit or card may be damaged.

ACTION:	Re-install the programming unit as described in Installation in MAX+PLUS II Getting Started and try again. If the problem persists, call Altera Applications Department.

See also:

MAX+PLUS II Messages

Message Format


Can’t load JEDEC File <filename> -- device <device name> is not supported

CAUSE:	You tried to load a JEDEC File for a device that is not supported by MAX+PLUS II.

ACTION:	Use a device that is supported by MAX+PLUS II, and reload the JEDEC File or another programming file.

See also:

Devices & Adapters

MAX+PLUS II Messages

Message Format

Selecting a Device

Selecting a Programming File


Can't program or configure device <name> in a multi-device JTAG chain -- delete programming file from device information

CAUSE:	When you pressed OK to close the Multi-Device JTAG Chain Setup dialog box (JTAG menu), one of the entries had a non-programmable device associated with a programming file name. If you select a JTAG device that does not support in-system programming, you cannot configure it in a JTAG chain. For example, FLEX 8000 devices cannot be programmed or configured in a multi-device JTAG chain.

ACTION:	Change the device name or remove the programming file for this device. Choose the Multi-Device JTAG Chain Setup dialog box and select the entry. To change the device name, select a device that supports multi-device programming from the Device Name list box (i.e., FLEX 10K, MAX 9000, FLASHlogic). To remove the associated programming file for this device, blank out the Programming File Name box. Press the Change button to update the entry.

See also:

MAX+PLUS II Messages

Message Format

Programming Devices in a Multi-Device JTAG Chain


Can’t save JEDEC File for device:<device name>
Can’t save JEDEC File for device <device name>

CAUSE:	You tried to save a JEDEC File for a device that does not use JEDEC Files for programming.

ACTION:	Save the data as a POF with the Save Programming Data As command (File menu).

See also:

MAX+PLUS II Messages

Message Format

Saving Programming Data to a File


Can’t select file <name> -- not part of current project. M+II cannot change project name while background process is running.
Can’t select file <filename> -- it is not part of the current project. MAX+PLUS II is running a background process and cannot change the project name while this process is running.

CAUSE:	You tried to select a programming file that is not part of the current project while MAX+PLUS II was running a background process. While a background process is running, MAX+PLUS II cannot change the project name.

ACTION:	Select a programming file from the current project, stop the background process, or allow it to finish before selecting a programming file from a different project.

See also:

Changing the Project Name

MAX+PLUS II Messages

Message Format

Selecting a Programming File

Starting & Stopping the Compiler

Starting & Stopping the Timing Analyzer

Starting, Pausing & Stopping the Simulator


Can’t test <hardware type> hardware

CAUSE:	The installed programming hardware does not have any testing circuitry. For example, the BitBlaster does not have any testing circuitry.

ACTION:	No action is required.

See also:

MAX+PLUS II Messages

Message Format


Can’t test -- node names in file <filename> do not match pin names for current project

CAUSE:	You tried to functionally test a device with an SCF or Vector File from a different project.

ACTION:	Specify a different SCF or Vector File with Inputs/Outputs (File menu) and choose the Test button.

See also:

MAX+PLUS II Messages

Message Format

Specifying the Source of Input Vectors


Can’t test -- project contains externally connected output or bidirectional pins

CAUSE:	Your project contains externally connected output or bidirectional pins, created either with OUTPUTC and/or BIDIRC primitives in a GDF or with the Connected Pins command (Assign menu). A device with these types of connected pins cannot be functionally tested with the MPU.

ACTION:	A group of connected pins can contain only one output or bidirectional pin. Edit any design files that connect multiple output or bidirectional pins, recompile the project, and try again.

See also:

Assigning Connected Pins

MAX+PLUS II Messages

Message Format


Can’t test -- project requires multiple devices

CAUSE:	You tried to test a device that is part of a multi-device project. Since the Vector File or SCF used during device testing is for an entire project, you cannot compare it to the actual device outputs in a single device. You can only test devices for single-device projects.

ACTION:	No action is required.

See also:

MAX+PLUS II Messages

Message Format

Testing Device Outputs vs. Simulation Outputs


Can't use device <name> to configure <text> family devices

CAUSE:	The selected Configuration EPROM device does not support configuration for the device(s) specified in the SOF(s). This problem occurs if you have selected Configuration EPROM EPC1064 or EPC1213 for a FLEX 10K device.

ACTION:	Select a Configuration EPROM that supports the device(s) specified in the SOF, i.e., use Configuration EPROM EPC1 for FLEX 10K devices.

See also:

Configuring a FLEX 8000 or FLEX 10K Device with the BitBlaster

MAX+PLUS II Messages

Message Format

Recommended reading:

AN33 (Configuring FLEX 8000 Devices)

AN59 (Configuring FLEX 10K Devices)


COM port <COM port> is not available

CAUSE:	The COM port selected in the Hardware Setup dialog box (Options menu) is not available or does not exist.

ACTION:	Select a different COM port from the COM Port drop-down list box in the Hardware Setup dialog box.

See also:

Changing the Hardware Setup

Configuring a FLASHlogic Device with the BitBlaster

Configuring a FLEX 8000 or FLEX 10K Device with the BitBlaster

MAX+PLUS II Messages

Message Format

Programming a Device with the BitBlaster


COM port <COM port> is busy

CAUSE:	The COM port for the BitBlaster that you selected with the Hardware Setup command (Options menu) is being used by another DOS or Windows application.

ACTION:	Select a different COM port for the BitBlaster from the COM Port drop-down list box in the Hardware Setup dialog box, or change the COM port for other open applications so that the specified COM port is available for use with the BitBlaster.

See also:

Changing the Hardware Setup

Configuring a FLASHlogic Device with the BitBlaster

Configuring a FLEX 8000 or FLEX 10K Device with the BitBlaster

MAX+PLUS II Messages

Message Format

Programming a Device with the BitBlaster


Configuration complete: [<text>]

CAUSE:	The Programmer has successfully configured one or more FLEX 8000, FLEX 10K, or FLASHlogic devices. If you are programming in multi-device mode, this message shows the number of devices configured.

ACTION:	No action is required. If you wish to configure more devices, insert them into your PC board and choose Configure.

See also:

Configuring a FLASHlogic Device with the BitBlaster

Configuring a FLEX 8000 or FLEX 10K Device with the BitBlaster

Configuring a Device with the FLEX Download Cable

MAX+PLUS II Messages

Message Format

Programming a Device with the BitBlaster


Configuration failure: SRAM load unsuccessful

CAUSE:	You tried to configure a FLEX 8000 or FLEX 10K device in the Altera MPU, with the FLEX Download Cable, or with the BitBlaster, but the data did not load into the device.

ACTION:	Check that all cables are securely connected and try again, or use a new device.

See also:

Configuring a FLEX 8000 or FLEX 10K Device with the BitBlaster

Configuring a Device with the FLEX Download Cable

MAX+PLUS II Messages

Message Format

Programming a Device with the BitBlaster


Currently selected version of device <device name> cannot be programmed with Security Bit on etc.
Currently selected version of device <device name> cannot be programmed with the Security Bit turned on. Please turn off the Security Bit or use a later device version.

CAUSE:	You tried to program a device with the Programmer’s Security Bit option turned on. This feature is not available for the current version of this device.

ACTION:	Turn off the Security Bit option or use another device version.

See also:

MAX+PLUS II Messages

Message Format

Programmer Golden Rules

Programming a Device with the Master Programming Unit

Security Bit (Programmer)

Selecting a Device

Setting the Security Bit (Programmer)


Device in adapter is incompatible with current programming file -- load SOF to test a FLEX 8000 device

CAUSE:	The device in the adapter cannot be programmed or configured with the current programming file, which is displayed in the File field.

ACTION:	Use a device that is compatible with the current programming file, e.g., the device that appears in the Device field. If you wish to test or configure a FLEX 8000 device, you must select a file with a compatible format using the Select Programming File command (File menu).

See also:

Configuring a Device with the FLEX Download Cable

MAX+PLUS II Messages

Message Format

Programming a Device with the Master Programming Unit

Selecting a Device

Selecting a Programming File

Testing Device Outputs vs. Simulation Outputs


Device is backwards in socket

CAUSE:	The Programmer or Simulator found that the device is not facing the right way in the adapter socket.

ACTION:	Insert PGA, SOIC, and QFP devices so that the guideline on the adapter socket points the same way as the guideline on the device itself. Insert DIP devices so that the notch is at the top. Insert BGA devices so that pin 1 lines up with the triangular pin 1 marking. Insert J-lead devices so that the chamfer lines up with the chamfer on the adapter socket. Be extremely careful when using high-pin-count J-lead and QFP packages. Pins can bend easily if the device is mishandled or inserted into the programming adapter incorrectly.

See also:

Inserting a Device into the Socket

MAX+PLUS II Messages

Message Format

Recommended reading:

AB46 (Selecting Sockets for J-Lead Packages)

QFP Carrier & Development Socket Data Sheet


Device is erased

CAUSE:	You performed a blank-check and the Programmer found that the device is erased and ready for programming.

ACTION:	No action is required.

See also:

Blank-Checking a Device

MAX+PLUS II Messages

Message Format


Device is not erased

CAUSE 1:	The device you are attempting to program has not been erased. You may have used the Examine rather than the Blank-Check button to check whether it was erased. Only Blank-Check provides a definitive answer.

ACTION:	You are prompted to insert a device into the programming socket. Insert a blank device into the socket and choose OK.

CAUSE 2:	The erasure time was too short.

ACTION:	Expose EPROM-based Classic, MAX 5000, and MAX 7000 devices to continuous UV light for 1 hour. An extra 15 minutes will not damage the device. However, Altera does not recommend excessive erasure times (i.e., overnight).

CAUSE 3:	The specifications on your UV eraser are incorrect or the eraser needs a new bulb.

ACTION:	Check the specifications of your UV eraser, ensuring that its wavelength is not greater than 4,000 Å. Altera recommends a wavelength of 2,537 Å, and a power rating of at least 12,000 µW/cm2. Check the eraser bulb and replace it if it is not working.

See also:

Blank-Checking a Device

MAX+PLUS II Messages

Message Format


Device is not erased. Do you wish to program the Security Bit?

CAUSE:	The device you are attempting to program has already been programmed and has not been erased. However, you turned on the Programmer’s Security Bit option since you programmed the device, so the Programmer is offering to program (i.e., turn on) the Security Bit for you.

ACTION:	Choose OK to program the Security Bit or choose Cancel and try programming again with a blank (erased) device.

See also:

Blank-Checking a Device

MAX+PLUS II Messages

Message Format

Programming a Device with the Master Programming Unit

Setting the Security Bit (Programmer)


Device is not in socket

CAUSE:	The Programmer or Simulator found that the device is not in the adapter socket.

ACTION:	Insert a device and try again.

See also:

Inserting a Device into the Socket

MAX+PLUS II Messages

Message Format


Device <name> already has JTAG attribute information. OK to overwrite the existing information with new information?

CAUSE:	You pressed the Add button to add a device to the JTAG Device Attributes list box, but an entry for that device name was already in the list box.

ACTION:	Press OK to update the device entry. Press Cancel to do nothing.

See also:

MAX+PLUS II Messages

Message Format

Modifying JTAG Device Attributes

Programming Devices in a Multi-Device JTAG Chain


Device <name> does not have JTAG attribute information. [OK to add new information for this device?]

CAUSE 1:	When you pressed OK to close the Multi-Device JTAG Chain Setup dialog box (JTAG menu), one of the entries had an unknown device name. This device name was not in jtaginfo.crf.

ACTION 1:	Choose Multi-Device JTAG Chain Setup and choose the JTAG Device Attributes button to open the JTAG Device Attributes dialog box. Enter the JTAG device information for the new device, then choose Add. If you do not wish to add this device, delete its entry from the Multi-Device JTAG Chain Setup dialog box.

CAUSE 2:	You pressed the Change button to modify the JTAG device attributes for a device in the JTAG Device Attributes dialog box, but there was no entry for that device name.

ACTION 2:	Press OK to add the new device to the JTAG Device Attributes list box. Press Cancel to do nothing.

See also:

MAX+PLUS II Messages

Message Format

Modifying JTAG Device Attributes

Programming Devices in a Multi-Device JTAG Chain


Device <name> is not compatible with programming file <name>

CAUSE:	When you pressed OK to close the Multi-Device JTAG Chain Setup dialog box (JTAG menu), one of the entries had an incompatible device name and programming file pair.

ACTION:	Select a different device or programming file name. Use the Info button in Select Programming Files (File menu) to see which device a programming file requires.

See also:

MAX+PLUS II Messages

Message Format

Selecting a Programming File

Programming Devices in a Multi-Device JTAG Chain


Device pin continuity check failed at pin <number> [(<node name>)]
Device pin continuity check failed at pin <number>[(node <name>)]

CAUSE:	The Programmer or Simulator tested all pins and found at least one continuity failure on the device. This message may indicate that the device is not firmly fixed in the socket.

ACTION:	Reinsert the device into the socket and try again. If this message persists, it may mean that the leads on the device are damaged. Be extremely careful when using high-pin-count J-lead and QFP packages. Pins can bend easily if the device is mishandled or inserted into the programming adapter incorrectly.

See also:

Inserting a Device into the Socket

MAX+PLUS II Messages

Message Format

Recommended reading:

AB46 (Selecting Sockets for J-Lead Packages)

QFP Carrier & Development Socket Data Sheet


Device <text> canceled

CAUSE:	You chose the Stop button in the Programmer window, which stopped the operation specified in the message (i.e., blank-check, configure, examine, program, test, or verify) before it was complete.

ACTION:	If you were blank-checking, configuring, examining, testing, or verifying the device, resume the operation. If the device is an EPROM-based device such as a Classic or MAX 5000 device, it may be partially programmed. You must erase the device before attempting to reprogram it. Otherwise, no action is required and you may reprogram the device.

See also:

MAX+PLUS II Messages

Message Format

Programming a Device with the BitBlaster

Programming a Device with the Master Programming Unit


Device version is not enabled -- install a newer version of MAX+PLUS II software or enter a new device password

CAUSE:	The Altera device in the programming socket has a silicon ID version that is not recognized by MAX+PLUS II.

ACTION:	Choose Select Device (Options menu) and choose the Enable button to open the Enable New Device Version dialog box. Enter the new password for the device in the dialog box, choose OK twice, and try again. Also make sure you have the latest version of MAX+PLUS II installed. If not, install the latest version of the MAX+PLUS II software.

See also:

Devices & Adapters

Enabling a New Device Version

MAX+PLUS II Messages

Message Format


Examined device contains programming data that cannot be loaded

CAUSE:	The device you examined with the Examine button contains programming data that cannot be loaded. The device is either erased or has been programmed with the Programmer’s Security Bit option turned on.

ACTION:	No action is required. The programming data that was stored in the temporary data buffer before you examined the device is still loaded.

See also:

Examining a Device

MAX+PLUS II Messages

Message Format

Specifying Global Security Bit & Reserved Resource Settings

Setting the Security Bit (Programmer)


Existing files in archive directory <name> may be overwritten. OK to overwrite existing files?

CAUSE:	The archive directory you specified already exists and contains one or more JTAG chain files (.jcf).

ACTION:	Press OK to copy the JCF file into this directory and overwrite the old file. To change the archive directory, choose Cancel, then specify a new directory name in the Archive Programming Files dialog box (File menu).

See also:

Archiving JTAG Programming Files

MAX+PLUS II Messages

Message Format


File contains logic configuration not supported for this version of device. Please edit project or use later device version.
File <name> contains a logic configuration that is not supported for this version of device <device name>. Please edit the project or use a later device version.

CAUSE:	You have used a logic configuration that is not supported by the current device version.

ACTION:	Use the Locate button in the MAX+PLUS II Message Processor to locate the source of the error and edit the design to remove the portion of the design that causes the problem, or use a later device version. Refer to the data sheet or data sheet supplement for the device for more information. If the problem persists, contact Altera Applications Department.

See also:

Devices & Adapters

Locating the Source of a Message

MAX+PLUS II Messages

Message Format


File <filename> has already been selected. OK to add it again?
File <name> has already been selected. OK to add it again?

CAUSE:	In the Combine Programming Files dialog box (File menu), you tried to add a file that has already been added to the Selected Files box.

ACTION:	If you do not wish to add the file again, choose No. If you are working with multiple FLEX 8000 or FLEX 10K devices and will be using the same SOF more than once, you can add the SOF by choosing Yes.

See also:

Combining & Converting SRAM Object Files

Locating the Source of a Message

MAX+PLUS II Messages

Message Format

Programming a Device with the Master Programming Unit


Finished reading data from device

CAUSE:	The Programmer has finished reading programming data from the device that you are examining.

ACTION:	No action is required. You may save the data in a programming file with the Save Programming Data As command (File menu), or use the data to program or verify another device with the Program or Verify buttons.

See also:

MAX+PLUS II Messages

Message Format

Programming a Device with the Master Programming Unit

Saving Programming Data to a File

Verifying a Device


Incorrect adapter or hardware error

CAUSE 1:	The MAX+PLUS II Programmer requires a certain adapter to program or functionally test the device displayed in the Device field. The adapter is not installed.

ACTION:	Install the correct adapter. If you are programming MAX 5000 devices, make sure that the name of your small-format adapter has an "A" suffix. Adapters without this suffix are not compatible with current programming software. If the problem persists, contact Altera Applications Department.

CAUSE 2:	Your hardware has been damaged.

ACTION:	Choose the Test button in the Hardware Setup dialog box (Options menu) to confirm whether the hardware is performing properly. If the hardware fails the test, contact Altera Applications Department for further assistance.

See also:

Adapters

Inserting a Device into the Socket

MAX+PLUS II Messages

Message Format

Recommended reading:

AB81 (Troubleshooting EPLD Programming Problems)


Incorrect hardware type -- doesn’t match installed hardware

CAUSE:	The hardware type you selected in the Hardware Setup dialog box (Options menu) differs from the hardware type that is actually installed.

ACTION:	In the Hardware Setup dialog box, select the correct hardware in the Hardware Type drop-down list box, or choose the Auto-Setup button to automatically update the Hardware Type field to display the installed hardware.

See also:

Changing the Hardware Setup

MAX+PLUS II Messages

Message Format


Installed hardware does not support device type <name>

CAUSE:	The device specified in the Fit File for the current project cannot be programmed with the current programming hardware.

ACTION:	Install programming hardware that supports the current device. Be sure to update the current hardware configuration with Hardware Setup (Options menu). Refer to MAX+PLUS II Installation in MAX+PLUS II Getting Started for information on hardware installation.

See also:

Adapters

Changing the Hardware Setup

MAX+PLUS II Messages

Message Format


In-system programming is not supported for this device version [Continue anyway?]

CAUSE:	You tried to program a device in-system, but the current device version does not support this capability.

ACTION:	Either program the device with the MPU and an appropriate adapter, or select a different version of the device.

See also:

MAX+PLUS II Messages

Message Format


Invalid address for <hardware type> hardware

CAUSE:	The I/O address that you entered in the Hardware Setup dialog box (Options menu) is not valid for the specified hardware.

ACTION:	In the Hardware Setup dialog box, type or select the correct I/O address from the I/O Address drop-down list box, or choose the Auto-Setup button to automatically update the I/O address.

See also:

Changing the Hardware Setup

MAX+PLUS II Messages

Message Format

Installation in MAX+PLUS II Getting Started


JEDEC File <name> has incorrect transmission checksum (file value = <value>, calculated value = <value>). OK to ignore error?
JEDEC File <filename> has incorrect transmission checksum (file value = <value>, calculated value = <value>). OK to ignore error?

CAUSE:	You tried to load a JEDEC File that contains an incorrect transmission checksum.

ACTION:	Choose OK to read the file anyway with the error(s), or choose Cancel. You can recompile your project to create a new JEDEC File.

See also:

MAX+PLUS II Messages

Message Format


JTAG chain information confirmed by hardware check

CAUSE:	The JTAG information that you specified in the Multi-Device JTAG Chain Setup dialog box (JTAG menu) matches the JTAG information detected by the BitBlaster.

ACTION:	No action is required.

See also:

MAX+PLUS II Messages

Message Format

Programming Devices in a Multi-Device JTAG Chain


JTAG chain information specified in this dialog box does not match the information detected in hardware -- <text>

CAUSE:	The JTAG information specified in the Multi-Device JTAG Chain Setup dialog box (JTAG menu) does not match the JTAG information detected by the BitBlaster.

ACTION:	Correct the device name in the Device Names and Programming File Names list box in the Multi-Device JTAG Chain Setup dialog box. You might need to update the device's JTAG attributes in the JTAG Device Attributes dialog box.

See also:

MAX+PLUS II Messages

Message Format

Modifying JTAG Device Attributes

Programming Devices in a Multi-Device JTAG Chain


JTAG ID code expected for device <number> <text> does not match ID code detected in hardware -- <text>

CAUSE:	The JTAG information specified in the Multi-Device JTAG Chain Setup dialog box (JTAG menu) does not match the JTAG information detected by the BitBlaster.

ACTION:	Check the device name. If incorrect, correct the device name in the Device Names and Programming File Names list box in the Multi-Device JTAG Chain Setup dialog box. If the device name is correct, update the device's JTAG ID attributes in the JTAG Device Attributes dialog box. If the problem persists, contact Altera Applications Department for the correct JTAG ID code for the device.

See also:

MAX+PLUS II Messages

Message Format

Modifying JTAG Device Attributes

Programming Devices in a Multi-Device JTAG Chain


LAB <name> receives illegal logic cell feedback from logic cell <name>
Logic Array Block <LAB name> receives illegal logic cell feedback from logic cell <name>

CAUSE:	You have used a logic configuration that is not supported by the current device version.

ACTION:	Use the Locate button in the MAX+PLUS II Message Processor to locate the source of the error. Edit the design to remove the portion of the design that causes the problem. Refer to the data sheet or data sheet supplement for the device for more information. If the problem persists, contact Altera Applications Department.

See also:

Devices & Adapters

Locating the Source of a Message

MAX+PLUS II Messages

Message Format


Logic cell <name> uses illegal <text> architecture

CAUSE:	You have used a logic configuration that is not supported by the current device version.

ACTION:	Use the Locate button in the MAX+PLUS II Message Processor to locate the source of the error. Edit the design to remove the portion of the design that causes the problem. Refer to the data sheet or data sheet supplement for the device for more information. If the problem persists, call Altera Applications Department.

See also:

Devices & Adapters

Locating the Source of a Message

MAX+PLUS II Messages

Message Format


Multi-device JTAG chain mode, which disables the functions of this dialog box, is on. Do you want to switch etc.
Multi-device JTAG chain mode, which disables the functions of this dialog box, is on. Do you want to switch to the single device mode?

CAUSE:	You pressed OK to close the Select Programming Files dialog box (File menu) but Multi-Device JTAG Chain (JTAG menu) is turned on.

ACTION:	Choose Yes to use single-device mode and turn off multi-device mode. Press No to remain in multi-device mode.

See also:

MAX+PLUS II Messages

Message Format

Programming Devices in a Multi-Device JTAG Chain

Selecting a Programming File


Multi-device JTAG chain mode, which is needed to use the information entered in this dialog box, is off etc.
Multi-device JTAG chain mode, which is needed to use the information entered in this dialog box, is off. Do you want to switch to the multi-device JTAG chain mode?

CAUSE:	You pressed OK to close the Multi-Device JTAG Chain Setup dialog box (JTAG menu) but Multi-Device JTAG Chain (JTAG menu) is turned off.

ACTION:	Choose Yes to use multi-device JTAG chain mode. Press No to remain in single-device mode.

See also:

MAX+PLUS II Messages

Message Format

Programming Devices in a Multi-Device JTAG Chain


Multiple devices are in the adapter

CAUSE:	You inserted more than one device into the adapter and chose the Program, Verify, Examine, or Blank-Check button.

ACTION:	Make sure that only one device is in the adapter before you attempt to program, verify, examine, or blank-check a device.

See also:

Blank-Checking a Device

Examining a Device

MAX+PLUS II Messages

Message Format

Programming a Device with the Master Programming Unit

Verifying a Device


Node <name> is not a pin name for the current project -- node is ignored

CAUSE:	The SCF, Vector File, or programming file used for functional testing contains an input or output node that is not listed as an input or output pin in the Fit File for the project, so the Simulator or Programmer is ignoring it. This message may occur if a probe is placed on a buried node.

ACTION:	No action is required. To prevent the warning from occurring again, remove the node from the SCF or Vector File.

See also:

Deleting a Node or Group

Functional Testing with the SCF, Vector File, or Programming File

MAX+PLUS II Messages

Message Format


Password is not valid: <password>

CAUSE:	You entered an invalid password in the Enable New Device Version dialog box.

ACTION:	Enter the correct password. Valid passwords are provided in software updates and by Altera Applications Department.

See also:

Enabling a New Device Version

MAX+PLUS II Messages

Message Format


Program failure: <text>

CAUSE:	Due to a device, MPU, or BitBlaster hardware problem, the Programmer could not program the device.

ACTION:	Try erasing and reprogramming the device. If the problem persists, contact Altera Applications Department for assistance.

See also:

MAX+PLUS II Messages

Message Format

Programming a Device with the BitBlaster

Programming a Device with the Master Programming Unit


Program failure: FLASH bulk <operation> unsuccessful -- [check device Vpp supply voltage]

CAUSE:	Due to a device, MPU, or BitBlaster hardware problem, the Programmer could not erase or program the FLASHlogic device.

ACTION:	Check the connections and the device's Vpp voltage (if using the BitBlaster). Try erasing and reprogramming the device. If the problem persists, contact Altera Applications Department for assistance.

See also:

Blank-Checking a Device

Inserting a Device into the Socket

MAX+PLUS II Messages

Message Format

Programming a Device with the BitBlaster

Programming a Device with the Master Programming Unit


Programming complete: [<text>]

CAUSE:	The Programmer has successfully programmed one or more devices, and verified that no errors occurred during programming. If you are programming in multi-device mode, this message shows the number of devices programmed.

ACTION:	No action is required. You may now remove and use the programmed device(s). If you wish to program another device, remove the programmed device, insert a blank device into the MPU or your PC circuit board, and choose Program again.

See also:

Inserting a Device into the Socket

MAX+PLUS II Messages

Message Format

Programming a Device with the Master Programming Unit

Programming a Device with the BitBlaster


Programming hardware error -- voltage for <programming hardware> is out of tolerance

CAUSE:	A programming signal has exceeded the allowable voltage level. This voltage level may have damaged your programming hardware.

ACTION:	Call Altera Applications Department.

See also:

MAX+PLUS II Messages

Message Format


Programming hardware is busy

CAUSE:	The Simulator is currently using the programming hardware, so the Programmer couldn’t program, configure, verify, examine, blank-check, or test the device.

ACTION:	Wait until the Simulator has finished processing or terminate simulation and choose the button for the desired operation again.

See also:

Blank-Checking a Device

Examining a Device

MAX+PLUS II Messages

Message Format

Programming a Device with the Master Programming Unit

Starting, Pausing & Stopping the Simulator

Verifying a Device


Programming hardware is not installed

CAUSE 1:	MAX+PLUS II has performed a hardware check and found that programming hardware is not installed, or the programming hardware failed the diagnostic check. You cannot program, verify, configure, examine, or test devices without the correct programming hardware. This message can also occur when you open the Programmer and a device is already in the programming socket.

ACTION:	Make sure the programming socket does not contain a device.

CAUSE 2:	The programming hardware connections are loose.

ACTION:	Depending on which type of programming hardware you are using, make sure that the cable connecting the Logic Programmer card to the MPU is securely seated or that the BitBlaster is securely connected between the computer’s COM port and the target circuit board.

CAUSE 3:	The programming hardware setup is not correctly specified in MAX+PLUS II.

ACTION:	Make sure that the correct hardware configuration is displayed in the Hardware Setup dialog box (Options menu) in the Programmer or Simulator. Refer to MAX+PLUS II Installation in MAX+PLUS II Getting Started for programming hardware installation instructions.

CAUSE 4:	The Logic Programmer card address does not match the maxplus2.ini file address.

ACTION:	Check the dipswitch setting on the Logic Programmer card against the maxplus2.ini file. The address of the Logic Programmer card is initially set to 280. If this address is being used by another card, you can set the dipswitches to another value. The software configuration file must then be revised to reflect the new address. See LP6 Logic Programmer card dipswitch settings or refer to MAX+PLUS II Installation in MAX+PLUS II Getting Started for information on dipswitch settings.

In MAX+PLUS II, you can choose the Auto-Setup button in the Programmer’s Hardware Setup dialog box to automatically update the maxplus2.ini file with the new address.

CAUSE 5:	The AT bus is non-standard.

ACTION:	Enter the hardware specifications directly into the Hardware Type and I/O Address boxes in the Hardware Setup dialog box. You cannot use the Auto-Setup button if your AT bus is non-standard. Several IBM PC-AT-compatible computers contain non-standard buses that do not recognize Altera programming cards when they are used together with MAX+PLUS II.

CAUSE 6:	Your hardware has been damaged.

ACTION:	Choose the Test button in the Hardware Setup dialog box to confirm whether the hardware is performing properly. If the hardware fails the test, contact Altera Applications Department for further assistance.

If programming problems persist, contact Altera Applications Department.

See also:

Changing the Hardware Setup

MAX+PLUS II Messages

Message Format

Programming a Device with the BitBlaster

Recommended reading:

AB81 (Troubleshooting EPLD Programming Problems)


Programming hardware tests failed on <hardware type>

CAUSE:	The specified programming card or programming unit failed the diagnostic tests. These tests cannot run if a programming adapter is installed on the programming unit. If no adapter is present, this message indicates that either the programming card or the programming unit is defective.

ACTION:	If there is an adapter installed on your programming unit, remove the adapter and try again. If your programming unit fails the diagnostic tests after you remove the adapter, or if no adapter is installed, call Altera Applications Department.

See also:

MAX+PLUS II Messages

Message Format


Programming hardware tests were successful

CAUSE:	Your programming hardware passed all MAX+PLUS II hardware tests.

ACTION:	No action is required.

See also:

MAX+PLUS II Messages

Message Format


Programming unit <name> is incompatible with this version of device <name>. Contact Altera Applications.
Programming unit <name> is incompatible with this version of device <name>. Contact Altera Applications for up-to-date programming information.

CAUSE:	The current device is incompatible with the current version of the programming unit. This error can occur if, for example, you insert an EPM5128A device into an adapter that is plugged into a PLE3-12A programming unit.

ACTION:	Install the latest version of the adapter. Refer to Adapters or contact Altera Applications Department for up-to-date information on availability.

See also:

MAX+PLUS II Messages

Message Format


Security Bit programming complete

CAUSE:	MAX+PLUS II has successfully programmed the Security Bit into the current device.

ACTION:	No action is required.

See also:

MAX+PLUS II Messages

Message Format


Selected configuration scheme forces 'Disable Start-Up Time-Out' device option for all devices
Selected configuration scheme forces 'Disable Start-Up Time-Out' device option on for all devices

CAUSE:	When you combine multiple programming files so that you can configure multiple FLEX 8000 devices in a PPA or PPS configuration scheme, the 'Disable Start-Up Time-Out' option is forced on. This message would occur if you select .hex or .ttf in the dropdown for the filename extension in the Combine Programming Files dialog box (File menu).

ACTION:	No action is required. If you wish, choose Global Project Device Options (Assign menu) to open the FLEX 8000 Device Options dialog box, then turn off the Disable Start-Up Time-Out option.

See also:

Combining & Converting SRAM Object Files

MAX+PLUS II Messages

Message Format

Specifying Global Project FLEX 8000 Device & Pin Options

Specifying Individual FLEX 8000 Device & Pin Options


Test failure: <text>

CAUSE 1:	The testing hardware has detected a functional difference between the output node values specified in the SCF, Vector File, or programming file that contains test vectors and the actual outputs of the programmed device. You may be using the wrong SCF or Vector File, i.e., a file created for an earlier version of the project or for a different project.

ACTION:	Check whether you have used the correct SCF or Vector File.

CAUSE 2:	The vector inputs may cause a race condition, a setup or hold time violation, or a glitch or oscillation in the programmed device. Additionally, if your SCF, Vector File, or programming file contains expected or simulated output node values (rather than actual device outputs), this message may indicate that the outputs in the file are not functionally equivalent to actual device outputs.

ACTION:	Check the vector inputs in the Waveform Editor to ensure that they do not create race conditions, setup or hold time violations, or glitches and oscillations. For example, a Clock transition on a latch or register at the same time as a transition on the D input may cause a problem. To detect some of these conditions, simulate device projects with the Setup/Hold, Glitch, and Oscillation options turned on.

If (after erasing and reprogramming) the post-programming functional testing still yields this message, compare the differences between the expected and actual outputs with the Waveform Editor’s Compare command (File menu). After analyzing the differences, you may wish to change the SCF input vectors or expected output waveforms, or the project itself.

CAUSE 3:	If your SCF, Vector File, or programming file contains actual device outputs that were generated by running the Simulator with the Use Device option turned on, but with a different device that was programmed with the same data, this message may indicate that there is a device hardware problem.

ACTION:	Check that the actual device outputs in the file were generated with the same project and vector inputs. If the message persists after you have checked the project, vectors, and speed grade, the message indicates that the device has been damaged. If the problem persists, contact Altera Applications Department.

See also:

Comparing Files or Simulation Outputs

Functional Testing with the SCF, Vector File, or Programming File

MAX+PLUS II Messages

Message Format

Specifying the Source of Input Vectors

Testing Device Outputs vs. Simulation Outputs


Test inconclusive -- no outputs were compared

CAUSE:	All outputs in the SCF or Vector File were undefined (X) or high-impedance (Z), so no outputs were tested. This message can occur if you convert a Vector File that does not contain outputs into an SCF. If you don’t simulate, the outputs remain undefined.

ACTION:	Simulate the project and choose Test again.

See also:

MAX+PLUS II Messages

Message Format

Testing Device Outputs vs. Simulation Outputs


Test successful: no errors

CAUSE:	MAX+PLUS II has checked the actual functional device outputs against the outputs in the SCF, Vector File, or programming file and found that they match.

ACTION:	No action is required. If you wish to process (i.e., test or program) another device, insert it into the adapter socket and choose Test or Program.

See also:

MAX+PLUS II Messages

Message Format

Programming a Device with the Master Programming Unit

Testing Device Outputs vs. Simulation Outputs


Testing hardware is not installed

CAUSE:	Some MAX+PLUS II features operate only when the optional testing hardware is installed. You have chosen such a feature. If you have not installed the testing hardware, you cannot use this command. If you have installed the testing hardware, this message indicates that the Logic Programmer card, MPU, or adapter is not present or is incorrectly installed. (The MPU can only test with PLM-series adapters.)

ACTION:	Install the testing hardware, or, if you already have the Logic Programmer card in your PC, check that it is securely fastened to the card slot and that the cable from the card to the MPU is securely fastened. Refer to MAX+PLUS II Installation in MAX+PLUS II Getting Started.

See also:

Adapters

Changing the Hardware Setup

MAX+PLUS II Messages

Message Format

Recommended reading:

AB81 (Troubleshooting EPLD Programming Problems)


Unknown device <device name> [in Fit File]

CAUSE:	MAX+PLUS II checked the device name in the Fit File for the project, but did not recognize it as a legal Altera device. You may have attempted to program a non-Altera device, or you may not have updated your MAX+PLUS II system correctly, and it therefore does not recognize a new device version.

ACTION:	Use only genuine devices manufactured by Altera or Altera licensees. If the device that caused the message was a genuine Altera device, check that you have installed all MAX+PLUS II software and updates. Refer to MAX+PLUS II Installation in MAX+PLUS II Getting Started, and check the read.me file (Help menu). Also, you may need to recompile the project to generate a new, up-to-date Fit File. For the latest software release information, contact Altera Applications Department.

See also:

Devices & Adapters

Enabling a New Device Version

MAX+PLUS II Messages

Message Format


Unrecognized device or socket is empty

CAUSE 1:	The Programmer checked the MPU, but found that the socket was empty or contained a device that was not recognized as an Altera device.

ACTION:	Use only genuine devices manufactured by Altera or Altera licensees. If the device is a genuine Altera device, make sure that it is supported by your programming software. Contact Altera Applications Department for the password(s) that enable the Programmer to use new device versions.

CAUSE 2:	The device is not firmly fixed in the socket or the pins on the package are bent.

ACTION:	Carefully re-insert the device. Pins on high-pin-count J-lead and QFP packages can bend easily if the device is mishandled or inserted into the programming adapter incorrectly. VCC and GND pins can also short together and cause this error. If the message persists, contact Altera Applications Department.

CAUSE 3:	The adapter contacts are dirty.

ACTION:	Clean the adapter socket with rubbing alcohol on a regular basis. The socket contacts become dirty after several hundred parts are programmed.

CAUSE 4:	The Security Bit is turned on.

ACTION:	Be sure that the device is completely erased before reprogramming it. EPROM-based Classic, MAX 5000, and MAX 7000 devices should be exposed to continuous UV light for one hour to ensure complete erasure. While an extra 15 minutes will not damage the device, Altera does not recommend excessive erasure times (i.e., overnight).

See also:

Blank-Checking a Device

Devices & Adapters

Enabling a New Device Version

Inserting a Device into the Socket

MAX+PLUS II Messages

Message Format

Setting the Security Bit (Programmer)

Recommended reading:

AB46 (Selecting Sockets for J-Lead Packages)

QFP Carrier & Development Socket Data Sheet


Verify failure: <text>

CAUSE:	The Programmer could not verify the device. If this message occurs during device verification, it indicates that the device was programmed with the Programmer’s Security Bit option turned on or that the device does not contain the same data as the programming file. You cannot verify the data in a device that has the Security Bit turned on. If this message occurs when you try to program only the Security Bit into a device (i.e., turn on the Security Bit in a programmed device), it indicates that the Security Bit is already turned on. If it occurs during device programming, it indicates that there is a device hardware problem.

ACTION:	If this error occurs during device verification, use a different device: you can only verify devices that do not have the Security Bit turned on. If the error occurs during device programming, try erasing and reprogramming the device. If the message persists, contact Altera Applications Department.

See also:

Devices & Adapters

MAX+PLUS II Messages

Message Format

Programming a Device with the Master Programming Unit

Setting the Security Bit (Programmer)

Verify Button

Verifying a Device


Verify successful: [<text>]

CAUSE:	The Programmer has checked the device(s) against the data in the current programming file, and found that they match. If you are programming in multi-device mode, this message shows the number of devices verified.

ACTION:	No action is required. You are also prompted to insert another device into the MPU or PC circuit board. If you wish to verify another device, remove the first device, insert another device into the MPU or PC circuit board, and choose Verify.

See also:

Inserting a Device into the Socket

MAX+PLUS II Messages

Message Format

Verifying a Device


-----BEGINNING OF NON-TRANSLATED TEXT-----

The following PS_MSGS are not documented in this file:

FPS_DESIGN_TOO_COMPLEX	COMESS.MAC

EPS_SCLK_BAD_COMBIN	COMESS.MAC

MPS_RESET_REQUIRED	comess.mac

The following MLS messages are documented here:

EMLS_CANT_SEPARATE_TRI

EMLS_ILLEGAL_USE_OF_REG

EMLS_ILL_OBJ_DRIVING_IOPIN

EMLS_SCLK_BAD_SOURCE

EMLS_TRI_FEEDS_BIDIR

WMLS_WARN_IGNORE_IPIN

WMLS_WARN_LATCH_DISABLED

WMLS_WARN_NO_CLOCK_TRANSITION

WMLS_WARN_TRISTATE_DISABLED

WMLS_WARN_TRIVIAL_REG_GND

WMLS_WARN_TRIVIAL_REG_VCC

WMLS_WARN_TRIVIAL_USE_LATCH

The following messages from other modules are documented here:

-----END OF NON-TRANSLATED TEXT-----


 BIDIR pin <name> must be driven by TRI buffer, but is driven by primitive <net ID number>

CAUSE:	The specified BIDIR (or BIDIRC) pin is driven by the specified primitive, rather than by a TRI buffer primitive. BIDIR or BIDIRC pins can only be fed by a TRI buffer.

ACTION:	Use only the TRI primitive to feed a BIDIR.

See also:

MAX+PLUS II Messages

Message Format

Primitive Interconnections


Both Preset and Clear inputs are connected to GND in flipflop <net ID>
Both Preset and Clear inputs are connected to GND in flipflop <net ID number>

CAUSE:	Both the Preset and Clear inputs to the specified flipflop are set to GND. This enables both signals at once (Preset and Clear are predefined as active-low). This conflict may have occurred if logic synthesis has removed redundant logic.

ACTION:	Check the input design file for errors. Never connect both Preset and Clear to GND.

See also:

MAX+PLUS II Messages

Message Format

Primitives

Primitive Interconnections


Can’t assign two registers (<name>, <name>) to the same I/O cell

CAUSE:	You have assigned two  registers to the same I/O cell.

ACTION:	Delete one of the I/O cell assignments, or insert an LCELL buffer between one of the I/O cell registers and the pin.

See also:

Assigning a Pin, Location or Chip

Deleting an Assignment

MAX+PLUS II Messages

Message Format

Primitive Interconnections


Can’t assign input register <name> to an I/O cell because the tri-stated node <name> is always enabled

CAUSE:	You have assigned an I/O cell register to an I/O cell with a tri-stated node that is always enabled. This assignment causes the I/O cell register to behave as an input I/O cell register. MAX 9000 projects cannot physically accomodate an input I/O cell register if the tri-stated node is always active.

ACTION:	Remove the BIDIR pin or ensure that the tri-stated node is not always active. You can also force the tri-state to be active at all times if the synthesized logic reduces to a state that is always active.

See also:

Assigning a Pin, Location or Chip

Deleting an Assignment

MAX+PLUS II Messages

Message Format

Primitive Interconnections


Device requires opposite correct polarity of global signal for this port -- etc
Device requires opposite polarity of global signal for this port -- invert INPUT pin <name> that feeds the secondary input of primitive <name>

CAUSE:	The specified INPUT (or INPUTC) pin feeds a GLOBAL (or SCLK) buffer that in turn feeds the secondary input of another primitive. However, the polarity of the signal feeding the GLOBAL (or SCLK) buffer is incorrect. For this device, the secondary input does not allow the specified global signal to have this polarity.

ACTION:	Invert the specified signal by inserting or deleting a NOT gate. For a global Reset, insert a NOT gate between the INPUT (or INPUTC) primitive and the GLOBAL (or SCLK) primitive. For other global signals, delete the NOT primitive and make the INPUT (or INPUTC) primitive feed the GLOBAL (or SCLK) primitive directly. If the signal from the INPUT (or INPUTC) primitive travels through multiple hierarchy levels before it reaches the secondary input of the specified primitive, you may need to search through the hierarchy tree to locate the NOT gate that must be removed.

See also:

MAX+PLUS II Messages

Message Format

Primitive Interconnections


Device uses inverted global signal for this port -- etc
Device uses inverted global signal for this port -- a NOT gate is required between INPUT pin <name> and the secondary input of primitive <name>

CAUSE:	The specified INPUT (or INPUTC) pin feeds a GLOBAL (or SCLK) buffer that in turn feeds the secondary input of another primitive. However, the polarity of the signal feeding the GLOBAL (or SCLK) buffer is incorrect. For this device, the global signal that feeds a secondary input must be inverted.

ACTION:	Invert the specified signal by inserting a NOT gate (or, if an even number of NOT gates already exist, deleting a NOT gate) between the INPUT or INPUTC primitive and the GLOBAL (or SCLK) primitive. The INPUT or INPUTC primitive should feed the NOT primitive and the NOT primitive should feed the GLOBAL (or SCLK) primitive. If the signal from the INPUT (or INPUTC) primitive travels through multiple hierarchy levels before it reaches the secondary input of the specified primitive, you may need to search through the hierarchy tree to locate all of the existing NOT gates between the INPUT or INPUTC primitive and the secondary input of the specified primitive.

See also:

MAX+PLUS II Messages

Message Format


Flipflop <net ID number> stuck at <text>

CAUSE:	The specified flipflop reduces to VCC or GND because the inputs to the flipflop reduce to one of the combinations given below. (N represents a simple input.) This condition may be the result of logic synthesis.

Active-Low Preset:	Active-Low Clear:	Flipflop Reduces To:

GND	VCC or N	VCC

VCC or N	GND	GND

In the first case, Preset is low, so the flipflop is always Preset and the Clear is always disregarded. In the second case, Clear is low, so the flipflop is always cleared and the Preset is always disregarded.

Active-Low Preset:	D or T Input:	Flipflop Reduces To:

VCC	GND	GND

Preset is disabled, so the output of the register is always GND.

JK and SR flipflops are reduced to D or T flipflops during logic synthesis.

ACTION:	If you intended the flipflop to behave in this manner, no action is required. Otherwise, check the input design file for errors and ensure that the project’s logic does not reduce to any of these combinations.

See also:

MAX+PLUS II Messages

Message Format

Primitives


GLOBAL (or SCLK) buffer <net ID number> must be driven by an INPUT pin or a GLOBAL (or SCLK) buffer

CAUSE:	The source of the global buffer GLOBAL or synchronous Clock (SCLK) buffer is something other than an INPUT (or INPUTC pin), another GLOBAL buffer, or another SCLK buffer. No logic is allowed between the GLOBAL or SCLK buffer and the INPUT (or INPUTC) pin, GLOBAL buffer, or SCLK buffer that feeds it, unless the device requires a NOT gate between the GLOBAL or SCLK buffer and the INPUT or INPUTC pin. (Two GLOBAL or SCLK buffers in a row are redundant but not illegal.)

ACTION:	Use an INPUT (or INPUTC) pin primitive for a synchronous Clock pin or global signal pin, then feed the signal to a GLOBAL primitive. No logic or primitives are permitted between the GLOBAL primitive and the INPUT (or INPUTC) pin except another GLOBAL primitive, or in some cases, a NOT gate.

See also:

MAX+PLUS II Messages

Message Format


Ignored unnecessary INPUT pin <name>

CAUSE:	The specified INPUT (or INPUTC) pin is not connected to any outputs, or logic synthesis revealed that no design file outputs are dependent on the pin, so the pin has been ignored. This message probably indicates that you have forgotten to connect the pin to the rest of the logic.

ACTION:	If outputs should be dependent on this input, correct this design file. If you wish to ignore the pin (temporarily or permanently), no action is required.

See also:

MAX+PLUS II Messages

Message Format


LATCH <net ID number> is permanently disabled

CAUSE:	The Latch Enable (ena) input to the specified LATCH primitive is connected to GND. The latch is reduced to GND, and no signals will pass through it. This condition may result from logic synthesis.

ACTION:	Check the input design file for errors. Connect the input to something other than GND if you don’t wish to disable the latch.

See also:

MAX+PLUS II Messages

Message Format


LATCH <net ID number> is permanently enabled

CAUSE:	The Latch Enable (ena) input to the specified LATCH primitive is tied to VCC. The latch is reduced to an LCELL buffer, and will not modify signals as they pass through. This condition may be the result of logic synthesis.

ACTION:	Check the input design file for errors. Connect the Latch Enable input to something other than VCC to control the latch, or substitute an LCELL buffer for the latch.

See also:

MAX+PLUS II Messages

Message Format


No Clock transition on flipflop <net ID number>

CAUSE:	The inputs to the flipflop are as illustrated below. This condition may be the result of logic synthesis.

Active-Low Preset:	Clock:	Flipflop Reduces To:

VCC	VCC	GND

VCC	GND	GND

The Clock input to the register is constant. Normally, you can use the Preset and Clear inputs to toggle the flipflop. However, the Preset input also has a constant value, so the register reduces to GND.

ACTION:	If you intended the flipflop to behave in this manner, no action is required. Otherwise, check the design file for errors. If the Clock is constant, Preset should be variable to allow the register to change (or vice versa).

See also:

MAX+PLUS II Messages

Message Format

Primitives


Outputs of primitive <net ID> are active high and active low -- all will power up at GND

CAUSE:	A primitive (a tri-state buffer, a flipflop, or a latch) is connected to two or more output pins: one with an active-high output and the other with an active-low output. This condition may be the result of logic synthesis.

ACTION:	If both an active-high and active-low output value are desired immediately at power-up, an LCELL buffer should be inserted just before one of the output pins.

See also:

MAX+PLUS II Messages

Message Format

Primitives


Primitive <net ID number> is stuck at <text>

CAUSE:	Either, the active low Preset or Clear of a DFF primitive is GND, or some other logic minimized to GND or VCC.

ACTION:	If you intended the primitive to behave in this manner, no action is required. Otherwise, check the input design file for errors and ensure that the project’s logic does not reduce to any of these combinations.

See also:

MAX+PLUS II Messages

Message Format

Primitives


TRI buffer <net ID number > already feeds a BIDIR pin; it cannot also drive pin <name>

CAUSE:	The specified TRI buffer primitive is connected both to a BIDIR (or BIDIRC) pin and the specified OUTPUT, OUTPUTC, BIDIR, or BIDIRC pin.

ACTION:	If the TRI buffer is driving a bidirectional pin, it can directly drive other primitives, but not other pins. The TRI must be separated from other pins by logic.

See also:

MAX+PLUS II Messages

Message Format


TRI buffer <net ID number > and primitive <net ID number> cannot be assigned to different devices

CAUSE:	A TRI buffer primitive and the primitive that it feeds have different chip assignments. A TRI primitive must drive a primitive that is assigned to the same chip.

ACTION:	Either remove one of the chip assignments from either primitive or change one of the chip assignments to match the other.

See also:

Assigning a Device

Assigning a Pin, Location or Chip

Deleting an Assignment

MAX+PLUS II Messages

Message Format

Primitive Interconnections


TRI buffer <net ID> can only drive logic if connected to a BIDIR pin
TRI buffer <net ID number> can only drive logic [(<net ID>)] if connected to a BIDIR pin

CAUSE:	The specified TRI buffer primitive is connected to logic or a SOFT buffer, but not to a bidirectional (BIDIR or BIDIRC) pin. A TRI buffer can only drive logic or a SOFT buffer if it is also connected to a bidirectional pin.

ACTION:	Use a BIDIR or BIDIRC pin or remove the TRI primitive.

 	Tri-state buffers must connect to an output or bidirectional pin. Internal nodes may not be tri-stated.

See also:

MAX+PLUS II Messages

Message Format

Primitive Interconnections


TRI buffer <net ID number> drives OUTPUT pin; it cannot also drive other types of primitives
TRI buffer <net ID number> already drives OUTPUT pin; it cannot also drive other types of primitives

CAUSE:	The specified TRI buffer primitive is driving an OUTPUT (or OUTPUTC) pin and other primitives.

ACTION:	You may connect the TRI buffer to either an OUTPUT (or OUTPUTC) pin or a BIDIR (or BIDIRC) pin under the following conditions: if TRI is driving an OUTPUT or OUTPUTC pin, it can only drive other OUTPUT or OUTPUTC pins--it cannot drive any other primitive; if TRI is driving a BIDIR or BIDIRC pin, it can drive other primitives, but cannot drive other OUTPUT, OUTPUTC, BIDIR, or BIDIRC pins directly (i.e., the TRI must be separated from the pins by logic).

See also:

MAX+PLUS II Messages

Message Format

Primitive Interconnections


TRI buffer <net ID number> is permanently disabled

CAUSE:	The Output Enable input of the specified TRI buffer primitive is connected to GND. The tri-state buffer does not reduce to a simpler form. This condition may be the result of logic synthesis. If the TRI is connected to a bidirectional pin, the messages indicates that the pin will always be driving in.

ACTION:	Check the input design file for errors. Connect the input to something other than GND if you want to enable the Output Enable input. You might also wish to substitute an INPUTor INPUTC pin for the BIDIR or BIDIRC pin (and remove the TRI buffer) if the pin is always driving in.

See also:

MAX+PLUS II Messages

Message Format


Programmer commands
Commands

About MAX+PLUS II

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Waveform Editor


Select Programming File Command (Programmer)
Select Programming File Command (File Menu)

Shortcuts

Loads a programming file. Select Programming File is available from either the File menu or the Multi-Device JTAG Chain Setup dialog box (JTAG menu).

If you are programming in single-device mode, choose Select Programming File (File menu). If the current project has only one programming file, it is automatically loaded when you open the MAX+PLUS II Programmer. If the current project has multiple programming files, the first file is loaded automatically. You must load the other files manually to program other devices in a project.

If you are programming in multi-device JTAG chain mode, all the programming files are loaded automatically when you open the MAX+PLUS II Programmer. Choose the Select Programming File button in the Multi-Device JTAG Chain Setup dialog box to load specific programming files for each device, then use Save JCF to create the JCF file containing the JTAG chain settings.

Click Button 1 on any item in this dialog box for information on that item:

After you select a file with Select Programming File, the filename is displayed in the File Field.

If you choose a programming file from a different project, MAX+PLUS II offers to change the current project name to enable device programming for that project. You can then program the design data into a blank device or verify it against an existing device.

If you choose Select Programming File from the File menu while Multi-Device JTAG Chain (JTAG menu) is checked, a message displays asking if you want to use single-device mode instead. However, if you choose Select Programming File in the Multi-Device JTAG Chain Setup dialog box while Multi-Device JTAG Chain is unchecked, a message displays asking if you want to use multi-device mode instead.

See also:

Changing the Project Name

Selecting a Programming File


Show in Files List

Specifies the file type and associated filename extension of filenames displayed in the Files box. The following options are available:

Programmer Object Files (*.pof)	Displays all files in the current directory that have the extension .pof.

SRAM Object Files (*.sof)	Displays all files in the current directory that have the extension .sof.

JEDEC Files (*.jed)	Displays all files in the current directory that have the extension .jed.

All Programming Files (*.jed, *.sof, *.pof)	Displays all files in the current directory that have the extension .jed, .sof, or .pof.


Show Only Current Project Files

Displays only programming files for the current project in the Files box.


Info

Opens the Info dialog box, which displays information on the current programming file.


Select Programming File Dialog Box (Programmer)
Select Programming File dialog box

Click Button 1 on any item in this dialog box for information on that item:


Save Programming Data As Command (Programmer)
Save Programming Data As Command (File Menu)

Shortcuts

Saves the current programming data and optional functional testing vectors to a POF or JEDEC File.

This command allows you to save data that the Programmer has loaded from a programming file, or data that has been read from an examined device. You can also save test vectors from the current SCF or Vector File to a POF or JEDEC File. This file can be used to program a blank device or verify the file against a programmed device. You can also save a POF as a JEDEC File or vice versa.

Click Button 1 on any item in this dialog box for information on that item:

Save Programming Data As is available only if the current programming file is a POF or JEDEC File.

1. 	This command allows you to save the programming data from any examined device to a file. However, if the device is protected by a Security Bit, the data in the programming file is incorrect and cannot be used to program another device.

2.	You can also save data for configuring FLEX 8000 or FLEX 10K devices in different file formats. See Combining & Converting SRAM Object Files for information.

See also:

Examining a Device

Saving Programming Data to a File

Security Bit Option

Specifying the Source of Input Vectors


Test Vectors

Add Test Vectors to File	Includes the current functional testing vectors in the programming file specified in the File Name box. Pin assignment locations from the project’s Fit File are also included in the test vector information. The Add Test Vectors to File option is unavailable if the programming file does not contain test vectors.

Vector Input File	Shows the source of vectors that will be added to the file specified in the File Name box. You can specify a different source for the input vectors with Inputs/Outputs (File menu).

The Add Test Vectors to File option is available only if test vectors have been loaded for the current programming file.


Save Programming Data As Dialog Box (Programmer)
Save Programming Data As dialog box

Click Button 1 on any item in this dialog box for information on that item:


Info Command (Programmer)
Info Command (File Menu)

Shortcuts

Displays information on the current programming file.

The information displayed in the Info dialog box varies, depending on the type of the current programming file described and the type of device the file is intended to program.

Click Button 1 on any item in this dialog box for information on that item:

See also:

Getting Information on a File


File Name is

Shows the name of the current file. You can change the current filename with Select Programming File (File menu).


 File Information

Displays some or all the following information, depending on the current programming file selected:

File date is	Shows the date and time that the current file was created.

File size is	Shows the size of the current file in bytes.

File CRC is	Shows the file CRC in hexadecimal format. For JEDEC Files, shows the file transmission checksum in hex format.

File contains test vectors	Shows whether the current JEDEC File or POF contains functional testing vectors.

Device is	Displays the device for which the programming file is intended.

Device data checksum is	Displays the device data checksum for the programming file, which is used to compare a programming file with the data in a programmed device.


 Device Options are

Displays some or all the following information, depending on the target device and the type of the current programming file:

Security Bit	Shows whether the Security Bit device option is turned on or off (POF and JEDEC Files only).

User-Supplied Start-Up Clock	Shows whether the FLEX 8000, FLEX 8000M, or FLEX 10K User-Supplied Start-Up Clock device option is turned on or off. (SOFs only)

Auto-Restart Configuration on Frame Error	Shows whether the FLEX 8000, FLEX 8000M, or FLEX 10K Auto-Restart Configuration on Frame Error device option is turned on or off. (SOFs only)

Release Clears Before Tri-States	Shows whether the FLEX 8000, FLEX 8000M, or FLEX 10K Release Clears Before Tri-States device option is turned on or off. (SOFs only)

Enable DCLK Output in User Mode	Shows whether the FLEX 8000 or FLEX 8000M Enable DCLK Output in User Mode device option is turned on or off. (SOFs only)

Disable Start-Up Time-Out	Shows whether the FLEX 8000 or FLEX 8000M Disable Start-Up Time-Out device option is turned on or off. (SOFs only)

Enable JTAG Support	Shows whether the FLEX 8000 Enable JTAG Support device option is turned on or off. (SOFs only)

Enable Chip-Wide Reset	Shows whether the FLEX 10K Enable Chip-Wide Reset device option is turned on or off.

Enable Chip-Wide Output Enable	Shows whether the FLEX 10K Enable Chip-Wide Output Enable device option is turned on or off.

Enable INIT_DONE Output	Shows whether the FLEX 10K Enable INIT_DONE Output device option is turned on or off.


 Other Information

Includes additional information on the current programming file, which can include:

The version of MAX+PLUS II that created the file (POFs and SOFs only) and the copyright date.

Comments in the title block of the top-level GDF, the Title Statement of a top-level TDF, or in the comment field of a JEDEC File.


Info Dialog Box (Programmer)
Info dialog box

Click Button 1 on any item in this dialog box for information on that item:


Inputs/Outputs Command (Programmer)
Inputs/Outputs Command (File Menu)

Specifies an input Simulator Channel File, Vector File, or the current programming file for functional testing and/or an output Programmer Log File (.plf) to record the Programmer’s activities.

Click Button 1 on any item in this dialog box for information on that item:

The Programmer automatically loads vectors from the current programming file or from the newest SCF or Vector File with the same filename as the project. If vectors are present in both the programming file and in an SCF or Vector File, the programming file vectors are loaded. The vectors can contain expected device outputs from a simulation or actual device outputs from another device. If this file is a Vector File, MAX+PLUS II automatically converts it into a temporary data buffer with the same format as an SCF before functional testing begins. Inputs/Outputs allows you to explicitly specify a different, non-default Vector File, SCF, or programming file.

Functional testing is not available for MAX 9000 devices that are programmed in-system or for FLEX 8000 and FLEX 10K devices. However, you can configure FLEX 8000, FLEX 10K, and FLASHlogic devices for prototyping purposes.

See also:

Configuring a Device with the FLEX Download Cable

Configuring a FLASHlogic Device with the BitBlaster

Configuring a FLEX 8000 or FLEX 10K Device with the BitBlaster

Functional Testing with the SCF, Vector, or Programming File

Logging Programmer Commands & Messages

Specifying the Source of Input Vectors

Testing Device Outputs vs. Simulation Outputs


Vector Input File

Specifies the source of input vectors as an SCF, Vector File, or the current programming file. The Input File box displays <project name>.scf by default.


Show in Files List

Specifies the file type and associated filename extension of filenames displayed in the Files box. The following options are available:

Simulator Channel Files (*.scf)	Displays all files in the current directory that have the extension .scf.

Vector Files (*.vec)	Displays all files in the current directory that have the extension .vec.

Current Programming File	Displays the current programming file only.


Output File

Log (.plf)	Specifies the PLF to be used to record simulation commands. The filename <project name>.plf is displayed by default.

New	Overwrites an existing PLF, if any. If New is turned off, and the specified file exists, programming commands and messages are appended to the file.


Inputs/Outputs Dialog Box (Programmer)
Inputs/Outputs dialog box

Click Button 1 on any item in this dialog box for information on that item:


Combine Programming Files Command
Combine Programming Files Command (File Menu)

Combines and converts one or more SRAM Object Files into Programmer Object File(s), Raw Binary File, Tabular Text File, Serial Bitstream File, or Hexadecimal (Intel-format) File formats that support different FLEX 8000 and FLEX 10K device configuration schemes.

Combine Programming Files generates a single RBF, a single TTF, a single SBF, a single Hex File, or one or more POFs that contain configuration data for one or more FLEX 8000 or FLEX 10K devices. Combine Programming Files also allows you to combine several different sets of configuration data to support in-system reconfiguration.

Click Button 1 on any item in this dialog box for information on that item:

For each file option, you can type a filename with up to 32 name characters in the File Name box or select a file in the Files box. If you type the name of a directory that does not exist, MAX+PLUS II will offer to create it for you.

The Assembler automatically generates SOFs, Hex Files, and TTFs. However, you can use Combine Programming Files to generate a different SOF, Hex or TTF file (i.e., bit-slice or multi-device).

See also:

Combining & Converting SRAM Object Files

Configuring a FLEX 8000 or FLEX 10K Device with the BitBlaster

Configuring a Device with the FLEX Download Cable

Programming a Device with the BitBlaster

Programming a Device with the Master Programming Unit

Saving Programming Data to a File

Recommended reading:

AN33 (Configuring FLEX 8000 Devices)

AN38 (Configuring Multiple FLEX 8000 Devices)

AN59 (Configuring FLEX 10K Devices)


File Name (under Input Files)

Specifies the SOF to be added to the Selected Files box.

You can type a filename in the File Name box or select a name in the Files box to copy it to the File Name box. You can also type a text string that contains wildcard characters in the File Name box and choose OK to update the contents of the Files box with the filenames that match the text string. If Show Only Project Files is turned on, the Files box lists only files from the current project.


Add

Adds the specified File Name (listed under Input File) to the Selected Files box.


Delete

Deletes a selected file from the Selected Files box.


Address

Specifies the memory address for a selected file in the Selected Files box. This option is available only if the .hex (Single-Device) configuration scheme is selected in the File Format box.


Count

Specifies whether the configuration scheme counts Up or Down. These buttons are available only if the .hex (Sequential) configuration scheme is selected in the File Format box.


Order

Moves a selected input file Up or Down in the Selected Files box. Files are converted from top to bottom in the Selected Files box. File order is important when working with multiple FLEX 8000 or FLEX 10K devices.


Selected Files

Displays all files selected for conversion. The files are combined in the order listed in the Selected Files box, starting with the device nearest the data source.


File Name (under Output File)

Specifies an output filename.

You can type a filename with up to 32 name characters in the File Name box or select an existing filename in the Files box to copy it to the File Name box. You do not need to enter a filename extension: the extension .pof, .hex, .sbf, .ttf, or .rbf is automatically appended, based on the selected File Format. If you type the name of a directory that does not exist, MAX+PLUS II will offer to create it for you. If multiple POFs are generated, they are uniquely identified by a sequence number appended to the filename. Example

You can also type a text string that includes wildcard characters in the File Name box and choose OK to update the contents of the Files box with the filenames that match the text string.


File Format

Specifies the configuration file format for the output file shown in the File Name box (listed under Output File). You should choose the file format based on the method used to store the configuration data, the circuitry used on your PC board, and the desired FLEX 8000 or FLEX 10K device configuration scheme:

File Format:	Usage:

.pof (Sequential)	Conversion is required only to combine configuration data for multiple FLEX 8000 or FLEX 10K devices. Supports sequential AS configuration by Altera Configuration EPROM devices.

.hex (Single-Device)	Supports APU and APD configuration of a single FLEX 8000 device, or PPA and PPS configuration of a FLEX 10K device, by a parallel data source.

.hex (Bit-Slice)	Supports bit-slice AS configuration by a parallel data source.

.sbf (Sequential)	Supports sequential PS configuration with the BitBlaster from a DOS or UNIX system prompt.

.ttf (Sequential)	Supports sequential PPS, PPA, and PS configuration by an intelligent external controller. File is in text format.

.ttf (Bit-Slice)	Supports bit-slice PS configuration by an intelligent external controller. File is in text format.

.rbf (Sequential)	Supports sequential PPS, PPA, and PS configuration by an intelligent external controller. File is in binary format.

.rbf (Bit-Slice)	Supports bit-slice PS configuration by an intelligent external controller. File is in binary format.


Show Only Project Files

Displays only SOFs from the current project in the Files box.

When this option is turned off, the Files box lists all SOFs in the current directory.


Files

Lists all files in the current directory that match the text string in the File Name box. The contents of the Files box vary, depending on whether the active edit field is the File Name box listed under Input File or the File Name box listed under Output Files.

Selecting a filename in the Files box copies it to the active File Name box. If Show Only Project Files is turned on, the Files box lists only files from the current project.

You can also type a text string that includes wildcard characters in the active File Name box and then choose OK to update the contents of the Files box with the filenames that match the text string.


Directories

Lists all available all subdirectories of the current directory.

You can type a different absolute or relative pathname in the File Name box under Input Files or Output File and choose OK, or double-click Button 1 on a name in the Directories box to change the current directory.


EPROM

Lists all available Configuration EPROMs.

Select the Configuration EPROM you wish to use with these programming files.


If the specified filename is myproj, the first file is myproj.pof, the second is myproj1.pof, etc.

If you specify an output filename with 8 characters or less, MAX+PLUS II will truncate the filename if necessary to include the numerical index and maintain the 8-character filename length. If you specify an output filename with more than 8 characters, the numerical index is appended to it and characters are truncated only if the filename is too long.


 Combine Programming Files dialog box

Click Button 1 on any item in this dialog box for information on that item:


Archive JTAG Programming Files Command (Programmer)
Archive JTAG Programming Files Command (File Menu)

Copies JTAG Chain Files (.jcf), used for programming multi-device JTAG chains, to an archive directory.

Archive JTAG Programming Files saves backup copies of JCF files. This process ensures that future updates to the JCF files in the project directory do not affect the archived JCF files.

For example, you could archive a JCF file onto a floppy diskette in drive a: or a LAN drive for others to use.

Click Button 1 on any item in this dialog box for information on that item:

When you choose OK, MAX+PLUS II copies the JCF file to the archive directory. If an existing JCF file in the archive directory has the same name as the file you are archiving, you are asked if you wish to overwrite the file.

Archive JTAG Programming Files is available when programming files are entered in the list in the Multi-Device JTAG Chain Setup dialog box (JTAG menu).

See also:

Loading JTAG Configuration Data from a File

Programming Devices in a Multi-Device JTAG Chain

Saving JTAG Configuration Data to a File


Archive Directory

Specifies the name of the archive directory. The default archive directory is a subdirectory of the current project directory called <project name>.dir.

You can type an absolute or relative pathname in the Archive Directory box or select an existing directory name in the Directories box to copy it to the Archive Directory box. If you type the name of a directory that does not exist, MAX+PLUS II creates it for you.


JCF Name

Specifies the name of the JTAG Chain File (.jcf) to be archived in the directory specified in the Archive Directory box. The default JCF name is called <project name>.jcf.

You can type a filename with up to 32 name characters and the .jcf extension in the JCF Name box. If you omit the .jcf filename extension, it is not automatically appended to the filename. If you type the name of a directory that does not exist, MAX+PLUS II creates it for you.


Archive JTAG Programming Files Dialog Box (Programmer)
 Archive JTAG Programming Files dialog box

Click Button 1 on any item in this dialog box for information on that item:


Multi-Device JTAG Chain Command (Programmer)
Multi-Device JTAG Chain Command (JTAG Menu)

Turns multi-device programming mode on and off.

When multi-device programming mode is turned on, you can program one or more MAX 9000, FLASHlogic, FLEX 10K, and other devices that support JTAG programming, in a JTAG chain using the BitBlaster.

See also:

Programming Devices in a Multi-Device JTAG Chain


Multi-Device JTAG Chain Setup Command (Programmer)
Multi-Device JTAG Chain Setup Command (JTAG Menu)

Sets up the programming of multiple devices in a JTAG chain.

When multi-device programming mode is turned on, you can program one or more MAX 9000, FLASHlogic, FLEX 10K, and other devices that support JTAG programming, in a JTAG chain using the BitBlaster.

In the Multi-Device JTAG Chain Setup dialog box, select the names and sequence of devices in the JTAG chain, and optional associated programming files (SOF, POF, or JEDEC). This chain can contain any combination of Altera and non-Altera devices. Then, you can either save the current programming settings to a JCF file, or restore the settings from any JCF file.

Click Button 1 on any item in this dialog box for information on that item:

The devices are ordered in the sequence in which they are connected in the chain, with the first device receiving TDI from the BitBlaster, and the last device transmitting TDO to the BitBlaster.

If you wish to modify the JTAG parameters of existing devices, add new devices, or delete devices from the list, choose the JTAG Device Attributes button.

1. 	The names and sequence of the devices selected in the Multi-Device JTAG Chain Setup dialog box must match the devices connected to the BitBlaster hardware, or else any programming command will result in an error message.

2. 	Choose the Detect JTAG Chain Info button to verify that the device count, sequence, JTAG ID code, and total instruction length are correct. Pressing Detect JTAG Chain Info produces a message reporting whether the device information is correct, and updates the device count and total instruction register length in the Use Hardware group box.

3. 	Choosing OK accepts the device information in the dialog box without being checked by the BitBlaster.

See also:

Archiving JTAG Programming Files

Loading JTAG Configuration Data from a File

Modifying JTAG Device Attributes

Saving JTAG Configuration Data to a File

Selecting Programming File

Recommended reading:

AN39 (JTAG Boundary-Scan Testing in Altera Devices)


Device Name

Lists all Altera devices that support JTAG programming.

Select a device name from the drop-down list to copy it to the Device Name box. You can add or delete devices from this list by choosing the JTAG Device Attributes button. Then choose the Add/Change button to copy or update the device name and optional programming file in the Device Names - Programming File Names list box.


Programming File Name

Displays the name of the programming file.

You can type a programming filename or choose the Select Programming File button to select a programming file and copy it to the Programming File Name box. You can also type a text string containing wildcard characters in the Programming File Name box.

The device you select from the Device Name drop-down list box will be associated with the programming file shown in the Programming File Name box. If you do not want to program a device in the JTAG chain, blank out the Programming File Name box.

Then choose the Add/Change button to copy or update the device name and optional programming file in the Device Names - Programming File Names list box.


JTAG Device Attributes

Opens the JTAG Device Attributes dialog box where you can modify the JTAG parameters of existing devices, add new devices, or delete devices from the Device Name drop-down list box.


Select Programming File

Opens the Select Programming File dialog box where you can select a programming file and copy it to the Programming File Name box. After you click OK in Select Programming File, the dialog box closes and the selected programming filename appears in the Programming File Name box.


Device Names & Programming File Names

Device Names:	Displays the sequence of devices in the JTAG chain in numerical order. The top device is programmed first, and so on to the bottom device which is programmed last.

Programming File Names:	Displays the programming files (SOF, POF, or JEDEC) associated with each device in the JTAG chain. If no programming file is associated with a device, <none> is displayed next to the device name.

If the Device Names - Programming File Names list box is empty, no JCF file is loaded.

You can click Button 1 on an entry in this list box to select or deselect it. All items in this list box must be deselected for the Change button to change into an Add button.


List Contains n Devices with total instruction register length

Output only field that displays the number of JTAG devices listed in the Device Names - Programming File Names list box and their total instruction register length.


Detect JTAG Chain Info & Use Hardware

Use Hardware	Output-only field that displays the number of JTAG devices connected to the BitBlaster, and their total instruction register length.

Detect JTAG Chain Info	Updates the device count and total instruction register length in the Use Hardware group box. Also displays a message reporting whether the device information in the Device Names - Programming File Names list box matches the devices installed on the system.

Even if the numbers in the List Contains and Use Hardware fields match, the devices might be in the wrong sequence. Use Detect JTAG Chain Info to verify that the device count, sequence, JTAG ID code, and total instruction length of the devices in the Device Names - Programming File Names list box match those of the devices installed on the system.

The Detect JTAG Chain Info button is available only if BitBlaster is installed on your system.


Add/Change

Add	Adds a new line containing the device name and optional programming file to the Device Names - Programming File Names list box when no line is selected.

Change	Updates the selected line in the Device Names - Programming File Names list box with a different device name and/or programming filename.

If no line is selected in the Device Names - Programming File Names list box, this button says Add. If a line is selected, the Add button changes to the Change button. Both the Add and Change button copy the device name from the Device Name box and the programming file from the Programming File Name box.

You can click Button 1 on an entry in the Device Names - Programming File Names list box to select or deselect it. All items in this list box must be deselected for the Change button to change into an Add button.


Delete

Deletes the selected line from the Device Names - Programming File Names list box. You can delete only one line at a time.


Delete All

Clears the Device Names - Programming File Names list box.


Order

Moves a selected line Up or Down in the Device Names - Programming File Names list box. Device order is very important when programming multiple device JTAG chains.

The Up and Down buttons are disabled when no line is selected.


Save JCF

Opens the Save JCF dialog box, which allows you to load the multi-device programming settings from a previously saved existing JCF file.


Restore JCF

Opens the Restore JCF dialog box, which allows you to save the current multi-device programming settings to a new or existing JCF file.


 Multi-Device JTAG Chain Setup dialog box

Click Button 1 on any item in this dialog box for information on that item:


JTAG Device Attributes Dialog Box (Programmer)
JTAG Device Attributes Dialog Box

Updates the list of devices, displayed in the Existing JTAG Devices list, that support JTAG programming. You can modify the JTAG parameters of existing devices, add new devices, or delete devices from the list.

You can use the JTAG Device Attributes command in three ways:

Add new devices that support JTAG programming to the list of devices in Existing JTAG Devices. Contact Altera Applications Department to get the JTAG parameters for devices.

Change the JTAG parameters (Instruction Register Length, Boundary Scan Length, JTAG ID Code) for existing devices in the Existing JTAG Devices list.

Delete devices from the Existing JTAG Devices list.

When you choose OK, the device names and parameters are updated in the Device Name drop-down list box in the Multi-Device JTAG Chain Setup dialog box.

Click Button 1 on any item in this dialog box for information on that item:

The JTAGINFO.CRF file contains the information shown in JTAG Device Attributes, plus the TAP count and a flag indicating whether the device is an Altera device.

See also:

Programming Devices in a Multi-Device JTAG Chain


Device Name

Displays the name of the device that is selected in the Device Name drop-down list box in the Multi-Device JTAG Chain Setup dialog box.

You can type the name of a new device in the Device Name box.

or:

Select a device from the Existing JTAG Devices list to copy it to the Device Name box.


Instruction Register Length

Displays the instruction register length of the device listed in the Device Name box.

You can enter or modify the instruction register length for the device.


Boundary Scan Length

Displays the JTAG boundary scan length of the device listed in the Device Name box.

You can enter or modify the JTAG boundary scan length for the device.


JTAG ID Code

Displays a checkbox and the hexadecimal JTAG ID code of the device listed in the Device Name box.

Turn on the JTAG ID Code checkbox, then type in the JTAG ID Code for the device. Some of the Altera devices already have a JTAG ID code.


Existing JTAG Devices

Lists the Altera MAX 9000, FLASHlogic, FLEX 8000, and FLEX 10K devices that contain JTAG parameters. You can add other devices that support JTAG programming to the Existing JTAG Devices list.

Select a device from the Existing JTAG Devices list to display its JTAG parameters and copy its name to the Device Name box.


Add/Change

Is a dual-purpose button. Adds the new device specified in the Device Name box to the Existing JTAG Devices list.

or:

Changes the JTAG parameters of the device specified in the Device Name box.

When you first display JTAG Device Attributes, the Change button is disabled. If you modify the parameters of the selected device, the Change button is enabled. If you type a new name in the Device Name box, the button changes to Add.


Delete

Deletes the selected device from the Existing JTAG Devices list.


OK

Saves all changes to the device parameters, closes the dialog box, and returns you to the Multi-Device JTAG Chain Setup dialog box.


Cancel

Cancels all changes to the device parameters, closes the dialog box, and returns you to the Multi-Device JTAG Chain Setup dialog box.


JTAG Device Attributes dialog box

Click Button 1 on any item in this dialog box for information on that item:


Save JCF Command (Programmer)
Save JCF Command (JTAG Menu)

Saves the multi-device programming settings to a new or existing JCF file in the current project directory (unless otherwise specified).

JCF files are used to program one or more devices in a JTAG chain. You can save a JCF file by choosing Save JCF (JTAG menu) or the Save JCF button in the Multi-Device JTAG Chain Setup dialog box (JTAG menu). If you are updating an existing JCF file, you are asked if you wish to overwrite the file.

Click Button 1 on any item in this dialog box for information on that item:

When a JCF file is saved, the programming file names are saved as relative paths unless they are on a different drive. When a JCF file is restored, the programming file names expand to absolute paths. Thus, you can copy a JCF file and associated programming files to another directory or diskette, and load them successfully.

If you choose Restore JCF, you can see the list of saved JCF files in the Files box.

You cannot select JCF files from the Selected Programming File dialog box.

See also:

Archiving JTAG Programming Files

Loading JTAG Configuration Data from a File

Programming Devices in a Multi-Device JTAG Chain


File Name

Specifies the name of the JCF file to be saved. When you first open the Save JCF dialog box, the JCF file called <project name>.jcf is displayed in the File Name box.

You can type a filename with up to 32 name characters in the File Name box or select an existing filename in the Files box to copy it to the File Name box. You do not need to enter a filename extension: the extension shown in the Automatic Extension box is automatically appended to the filename. If you type the name of a directory that does not exist, MAX+PLUS II creates it for you.


Files

Lists all JCF files in the current directory that match the filename extension selected in the Automatic Extension box.

Selecting a filename in the Files box copies it to the File Name box.


Save JCF dialog box

Click Button 1 on any item in this dialog box for information on that item:


Restore JCF Command (Programmer)
Restore JCF Command (JTAG Menu)

Loads the multi-device programming settings from a previously saved JCF file.

Use Restore JCF to load the JCF file containing the device and programming file information for the devices you wish to program in a JTAG chain. You can load a JCF file by choosing Restore JCF (JTAG menu) or the Restore JCF button in the Multi-Device JTAG Chain Setup dialog box. After the JCF file is loaded, the device and programming file names are updated in the Multi-Device JTAG Chain Setup dialog box.

Click Button 1 on any item in this dialog box for information on that item:

When a JCF file is saved, the programming file names are saved as relative paths unless they are on a different drive. When a JCF file is restored, the programming file names expand to absolute paths. Thus, you can copy a JCF file and associated programming files to another directory or diskette, and load them successfully.

You cannot select JCF files from the Selected Programming File dialog box.

See also:

Archiving JTAG Programming Files

Programming Devices in a Multi-Device JTAG Chain

Saving JTAG Configuration Data to a File


Restore JCF dialog box

Click Button 1 on any item in this dialog box for information on that item:


Sound Command (Programmer)
Sound Command (Options Menu)

Turns the message alert sound on or off.

If Sound is turned on, the Programmer beeps when MAX+PLUS II displays a message box. For example, the computer will beep when the Programmer has finished programming a device.

See also:

Turning the Sound On & Off


Programming Options Command (Programmer)
Programming Options Command (Options Menu)

Allows you to specify options that speed up the programming of EPROM, EEPROM, and FLASHlogic devices. The four options are:

Blank-Check Before Programming

Verify During Programming

Verify After Programming

Test After Programming

By default, all four programming options are turned on.

Click Button 1 on any item in this dialog box for information on that item:

See also:

Adapters

Blank-Checking a Device

Programming a Device with the BitBlaster

Saving Programming Data to a File

Test Button

Testing Device Outputs vs. Simulation Outputs

Verifying a Device


Blank-Check Before Programming

If turned on, automatically blank-checks the device before it is programmed. By default, Blank-Check Before Programming is turned on.

If you wish to skip the automatic blank-check, turn off Blank-Check Before Programming.


Verify During Programming

If turned on, automatically verifies the device during programming. By default, Verify During Programming is turned on.

The device is verified to check that it is erased. If you wish to skip this verification step, turn off Verify During Programming.


Verify After Programming

If turned on, automatically verifies the device twice after programming. By default, Verify After Programming is turned on.

After programming is complete, the device is verified at both low and high voltage to check for insufficiently programmed and erased bits. If you wish to skip this verification step, turn off Verify After Programming.


Test After Programming

Turns automatic post-programming functional testing on or off for all devices programmed with the current programming file.

When Test After Programming is turned on, the Program button automatically performs the same tasks as the Test button. The Programmer automatically loads the SCF, Vector File, or programming file with the same filename as the project or the file specified with the Inputs/Outputs command (File menu). After the SCF is loaded, all devices are functionally tested against the input and output signals in the SCF when you choose Program.

You can also manually test a device by choosing the Test button.


Programming Options dialog box

Click Button 1 on any item in this dialog box for information on that item:


Auto-Testing Command (Options Menu)

I WILL REMOVE THIS TOPIC AFTER THE HELP FOR PROGRAMMING OPTIONS IS REVIEWED.

Turns automatic post-programming functional testing on or off for all devices programmed with the current programming file.

When you turn Auto-Testing on, the Programmer automatically loads the SCF, Vector File, or programming file with the same filename as the project or the file specified with the Inputs/Outputs command (File menu). If a Vector File or programming file is specified, the test vectors are automatically converted into SCF format before functional testing begins.

After the SCF is loaded, all devices are functionally tested against the input and output signals in the SCF when you choose Program. A Message Processor window opens automatically to report any cases in which the outputs are not functionally equivalent. The time needed for the post-programming functional testing is roughly proportional to the size of the SCF.

1. 	You can only functionally test a device for a single-device project. Since an SCF or Vector File used during testing is for an entire project (regardless of the number of devices in the project), it cannot be compared with the actual outputs of a single device that is part of a multi-device project. You also cannot test projects that contain bidirectional buses.

2. 	Functional testing is not available for MAX 9000 devices that are programmed in-system or for FLEX 8000 devices. However, you can configure FLEX 8000 devices in-system for prototyping purposes, as described in Configuring a Device with the FLEX Download Cable and Configuring a FLEX 8000 or FLEX 10K Device with the BitBlaster.

You can also manually test a device by choosing the Test button. When Auto-Testing is turned on, the Program button automatically performs the same tasks as the Test button.

Device testing is available only if you have installed the MPU and the appropriate adapter. In addition, the current device and the device that is contained in the current POF must be the same.

You can save functional testing vectors into the current POF or JEDEC File with Save Programming Data As (File menu).

Significant restrictions apply to the inputs and outputs in SCFs used with this command. For further information, see Functional Testing with the SCF, Vector, or Programming File.


Select Device Command (Programmer)
Select Device Command (Options Menu)

Shortcuts

Specifies the type of device to be examined with the Examine or Blank-Check buttons and allows you to enter and delete passwords for Altera devices.

Click Button 1 on any item in this dialog box for information on that item:

If you use Select Device to choose a device that is different from the device specified in the current programming file, the programming file is unloaded.

See also:

Enabling a New Device Version

Selecting a Device

Selecting a Programming File


Enable

Opens the Enable New Device Version dialog box, which allows you to add and delete passwords that enable you to use new device versions.


OK

Changes the current device to the device selected in the Available Devices box, saves any changes made in the Enable New Device Version dialog box, and closes the Select Device dialog box. The selected device is displayed in the Device field in the Programmer window.


Cancel

Cancels any device changes and changes made in the Enable New Device Version dialog box, and closes the Select Device dialog box.


Show All Packages & Speed Grades

Shows all speed grades available for the device family selected in the Device Family drop-down list box.


Select Device Dialog Box (Programmer)
Select Device dialog box

Click Button 1 on any item in this dialog box for information on that item:


Enable New Device Version Dialog Box (Programmer)
Enable New Device Version Dialog Box

Allows you to add or delete passwords that enable you to work with new device versions.

Click Button 1 on any item in this dialog box for information on that item:

You can obtain new device passwords by contacting Altera Applications Department.

See also:

Enabling a New Device Version

Selecting a Device


Device

Displays the device specified in the dialog box opened with the Select Device command.


Password

Displays the current password and allows you to specify a new password.


Existing Password

Lists the existing passwords for the current device.


OK

Temporarily saves all password changes, closes the dialog box, and returns you to the Select Device dialog box. To permanently save all passwords changes, you must choose OK in the Select Device dialog box.


Cancel

Cancels all password changes, closes the dialog box, and returns you to the Select Device dialog box.


Add

Adds the password displayed in the Password box to the Existing Passwords box. The Password box is then cleared, and you may enter another password. If the name in the Password box is already displayed in the Existing Passwords box, this button is not available.


Delete

Deletes the password displayed in the Password box from the Existing Passwords box.


Enable New Device Version dialog box

Click Button 1 on any item in this dialog box for information on that item:


Hardware Setup Command
Hardware Setup Command (Options Menu)

Specifies the current programming hardware installed in your MAX+PLUS II system.

If you install or change your programming hardware after installing MAX+PLUS II software, you must update the hardware setup in the Programmer or Simulator.

Click Button 1 on any item in this dialog box for information on that item:

See also:

Changing the Hardware Setup

MAX+PLUS II Installation in MAX+PLUS II Getting Started


Hardware Type

Specifies the current programming hardware, which can be either an MPU paired with a Logic Programmer card or the BitBlaster.

You can select the correct setup in the drop-down list box, or you can automatically update this field by choosing Auto-Setup. However, if your current programming hardware is the BitBlaster, you must first specify the COM port to which the BitBlaster is attached in the COM Port box before choosing Auto-Setup. If no programming hardware is installed, No Hardware is displayed when you choose Auto-Setup.

The workstation version of the Programmer supports only the BitBlaster hardware. If you cannot set the baud rate for the workstation version of the Programmer, contact your system administrator for assistance.


I/O Address

Specifies the I/O address of the Logic Programmer card. You can select an I/O address from the drop-down list box, or you can automatically update this field with Auto-Setup. If necessary, you can change the LP6 Logic Programmer card dipswitch settings to support a different I/O address.

This option is not available if the BitBlaster is shown as the current programming hardware under Hardware Type.


Auto-Setup

Automatically updates the Hardware Type, I/O Address, and Baud Rate boxes with the correct settings for the currently installed hardware. You can also specify these settings manually by selecting options in the Hardware Type, I/O Address, and Baud Rate drop-down list boxes.

If your current programming hardware is the BitBlaster, you must first specify the COM port to which it is attached in the COM Port box before choosing Auto-Setup.


COM Port

Specifies the COM port to which the BitBlaster is attached. You must manually specify the COM port before choosing Auto-Setup to correctly update the Hardware Type and Baud Rate boxes.

This option is not available if anything other than the BitBlaster is selected under Hardware Type.


Baud Rate

Specifies the baud rate to be used for transferring programming data to a FLEX 8000, FLEX 10K, or FLASHlogic device via the BitBlaster. You can automatically update this field to reflect the baud rate of the currently selected COM port shown in the COM Port drop-down list box by choosing Auto-Setup.

This option is not available if anything other than the BitBlaster is specified under Hardware Type.

The baud rate specified in the Hardware Setup dialog box must match the baud rate of the BitBlaster. To change the baud rate of the BitBlaster, use the dipswitches on the BitBlaster’s side panel.

If you do not own the TTY device attached to the BitBlaster, you might not be able to set the baud rate in the Baud Rate field in Hardware Type. If you cannot set the baud rate for the workstation version of the Programmer, contact your system administrator for assistance. The range of baud rates available for the workstation is more restricted than for the PC.


Self-Test

Runs diagnostic tests to verify all field-testable programming hardware circuitry. A message is displayed to indicate whether the circuitry passed or failed the tests.


Hardware Setup dialog box

Click Button 1 on any item in this dialog box for information on that item:


Programmer Window


Programmer Window


-----BEGINNING OF NON-TRANSLATED TEXT-----

All MPPMSGS.MSG messages are documented in this file:

except

EMPP_NO_CLKIO	COMESS

FMPP_bad_partinfp	glmess

FMPP_CANCELLED_BY_USER	COMESS

FMPP_OUT_OF_MEMORY	COMESS

FMPP_OUT_OF_STACK	COMESS

Messages from other files documented here:

EML_ILLEGAL_RESOURCE_NAME	ml_msgs.msg

-----END OF NON-TRANSLATED TEXT-----


Can’t find a partition with clique assignments

CAUSE:	The cliques in the project contain too many logic functions. In standard synthesis, this message indicates that the cliques contain too many hard logic functions.

ACTION:	Choose to ignore clique assignments in the Override User Assignments dialog box, as described in Adjusting the Fit During Compilation, to create smaller cliques, or specify larger devices for the project.

See also:

Assigning a Clique

Assigning a Device

Deleting an Assignment

Fitting & Refitting a Project

MAX+PLUS II Messages

Message Format


Chip assignment for <node name> conflicts with clique assignment for clique <name>
Can’t accept chip <name> for EPF8050M device -- too many chips for this device

CAUSE:	You assigned a chip to an EPF8050M device. However, only four chip assignments are allowed for EPF8050M devices, and there are already four chip assignments for the current project.

ACTION:	Delete one of the assignments so that no more than four chips are assigned to the EPF8050M device, or specify a different device family.

See also:

Assigning a Pin, Location, or Chip

Deleting an Assignment

MAX+PLUS II Messages

Message Format


Chip assignment for <node name> conflicts with clique assignment for clique <name>

CAUSE:	You assigned a node that is part of the specified clique to more than one chip or assigned two nodes that are in the same clique to different chips. Therefore, the members of the clique have conflicting chip assignments.

ACTION:	Make all of the assignments agree for the members of the clique, or turn on the OK to Ignore Cliques or OK to Ignore Chips/Pins/Buried LCs option in the Override User Assignments dialog box, as described in Adjusting the Fit During Compilation.

See also:

Assigning a Clique

Assigning a Pin, Location, or Chip

Deleting an Assignment

MAX+PLUS II Messages

Message Format


Chip assignment for <node name> conflicts with chip assignment for node <node name>

CAUSE:	You assigned logic cells in the same carry chain or cascade chain to different chips, or you assigned an output pin and the logic cell feeding the pin to different chips in a FLEX 8000 project.

ACTION:	Ensure that all of the logic cells in a carry or cascade chain are assigned to the same chip, and ensure that the output pin and the logic cell that feeds it are assigned to the same chip.

See also:

Assigning a Pin, Location, or Chip

Deleting an Assignment

MAX+PLUS II Messages

Message Format


Chip <name> did not fit into AUTO device <device>

CAUSE:	You used automatic device selection, but the device(s) you specified were not large enough to fit the project.

ACTION:	Refer to the messages that follow this message for information on why the chip did not fit. You may wish to change the range of Selected Devices specified in the Auto Device Selection dialog box (Processing menu)  to include larger devices, or allow the Compiler to ignore your reserved resources or to add extra devices as needed with the Override User Assignments dialog box, as described in Adjusting the Fit During Compilation.

See also:

Devices & Adapters

MAX+PLUS II Messages

Message Format

Specifying Devices for Automatic Device Selection


Chip <name> is not used

CAUSE:	A chip assignment you made is being ignored because it was not needed, i.e., no logic functions have been assigned to the chip.

ACTION:	No action is required.

See also:

MAX+PLUS II Messages

Message Format


Chip <name> successfully fit into AUTO device <device>

CAUSE:	The Compiler has successfully fitted the specified chip into the specified device during automatic partitioning.

ACTION:	No action is required.

See also:

MAX+PLUS II Messages

Message Format


Clique <name> too large to handle with <number> members
Clique <name> is too large -- it has <number> members

CAUSE:	The specified clique has too many members for the Compiler to process.

ACTION:	Reduce the number of items that are assigned to the clique.

See also:

Assigning a Clique

Deleting an Assignment

MAX+PLUS II Messages

Message Format


Compiling empty design file or file has no output pins

CAUSE:	You are compiling an empty design file or there are no output pins specified in the design file.

ACTION:	Check to make sure the project has a design file associated with it. Also, check to make sure the design file has output pins. The Compiler only generates the logic required to produce the specified output signals.

See also:

Changing the Project Name

MAX+PLUS II Messages

Message Format


Conflicting Slow Slew Rate settings for node <name> -- using SLOW_SLEW_RATE=ON

CAUSE:	The same logic cell was given conflicting Slow Slew Rate settings on the pin, register, and TRI buffer, so the Compiler has used ON as the setting.

ACTION:	Delete or change the assignments so they do not conflict.

See also:

Assigning an Individual Logic Option or Synthesis Style

Deleting an Assignment

Logic Option Assignments

MAX+PLUS II Messages

Message Format


Conflict on Turbo attribute for node <name> -- TURBO=ON selected
Conflicting Turbo Bit settings for node <name> -- using TURBO=ON

CAUSE:	The same logic cell was given conflicting Turbo Bit settings on the pin, register, and TRI buffer, so the Compiler has used ON as the setting.

ACTION:	Delete or change the assignments so they do not conflict.

See also:

Assigning an Individual Logic Option or Synthesis Style

Deleting an Assignment

Logic Option Assignments

MAX+PLUS II Messages

Message Format


 Connect input pin <name> and output pin <name> to support inversion of active-low Output Enable signal <name>

CAUSE:	Your MAX 7000 project uses an active-high Output Enable signal. MAX 7000 devices support only active-low Output Enable signals, i.e., OE signals that consist of an INPUT pin that feeds a NOT gate, so the Compiler has implemented your signal by adding the specified output pin and a NOT gate.

ACTION:	Connect the specified output and input pins.

See also:

Assigning a Pin, Location, or Chip

Assigning Connected Pins

MAX+PLUS II Messages

Message Format


 Connect input pin <name> and output pin <name> to support logic on the Output Enable signal

CAUSE:	Your MAX 7000 project has logic on the Output Enable of a TRI buffer that does not consist of an INPUT pin that feeds a NOT gate. MAX 7000 devices do not support other Output Enable configurations. Therefore, an output pin was created with your logic. This output pin feeds an input pin which in turn drives the Output Enable.

ACTION:	Connect the specified input and output pins. To retain pin assignments for pins used to generate an Output Enable signal, feed the logic to an output pin, and use an input pin to drive the Output Enable through a NOT gate. You can then connect these pins with the Connected Pins command (Assign menu) or with INPUTC and OUTPUTC primitives in a GDF to create named pins that can be assigned to a specific pin number.

See also:

Assigning a Pin, Location, or Chip

Assigning Connected Pins

Devices & Adapters

MAX+PLUS II Messages

Message Format


Creating <chip name> as an <EPLD>
Creating chip <chip name> from <family name> device family

CAUSE:	The Partitioner created a device from the specified device family in order to fit the project.

ACTION:	No action is required.

See also:

Devices & Adapters

MAX+PLUS II Messages

Message Format


Device <name> assigned <number> <text>, but has room for <number>

CAUSE:	The specified device has more logic cells, dual I/O feedback logic cells, shareable expanders, output pins, I/O pins (which may or may not include reserved dual-purpose programming pins), I/O cell registers, Embedded Array Blocks,or global signals assigned to it than are available in the device.

ACTION:	Change chip assignments to AUTO, remove chip assignments, assign some of the logic functions to a different chip, or specify a different device or device family.

See also:

Adjusting the Fit During Compilation

Assigning a Device

Deleting an Assignment

Devices & Adapters

Fitting & Refitting a Project

MAX+PLUS II Messages

Message Format

Specifying Devices for Automatic Device Selection


Device <name> assigned too many parallel expanders

CAUSE:	Too many logic cells that use parallel expanders are assigned to the specified device.

ACTION:	Turn off the Parallel Expanders logic option on one or more logic functions, use a larger device, or allow the Compiler to ignore chip assignments and/or reserved resources.

See also:

Assigning a Device

Assigning an Individual Logic Option or Synthesis Style

Deleting an Assignment

Devices & Adapters

Fitting & Refitting a Project

MAX+PLUS II Messages

Message Format

Specifying Global Project Security Bit & Reserved Resource Settings


Found possible source of logic contention: <text> pin <name>, etc
 Found possible source of logic contention: <text> pin <name>, which is always enabled, is tied to output/bidirectional pin <name>

CAUSE:	You have tied an output or bidirectional pin to an output or bidirectional pin. This may result in logic contention errors in the programmed device.

ACTION:	Change the project so that the two specified pins are not tied together.

See also:

MAX+PLUS II Messages

Message Format

Primitive Interconnections


Ignored assignment on <text> <node name>  to <assignment>  -- assignment on <text> <node name>  to <assignment> has precedence
Ignored assignment on <text> node <name> to <pin or LC number> -- assignment on <text> node <name> to <pin or LC number> has precedence

CAUSE:	There is a conflicting assignment between a combination of the pin, TRI buffer, or register. Since the pin, TRI buffer, and register are implemented in the same logic cell in the device, they cannot be assigned to different logic cells or pins. The conflict was resolved by prioritizing the assignments in the following order: pin, TRI buffer, register.

ACTION:	Delete or change assignments so that they do not conflict.

See also:

Assigning a Pin, Location, or Chip

Deleting an Assignment

MAX+PLUS II Messages

Message Format


Ignored assignment on pin <name> to clique <name>

CAUSE:	You have assigned the specified pin to the specified clique. However, MAX+PLUS II does not support clique assignments for pins or I/O cell registers in a FLEX 8000 project.

ACTION:	Delete the assignment or change it so it does not conflict by assigning the clique to the logic cell that feeds or is fed by the pin.

See also:

Assigning a Pin, Location, or Chip

Deleting an Assignment

MAX+PLUS II Messages

Message Format


Ignored I/O Cell Register logic option assignment for register <name>

CAUSE:	You have turned on the I/O Cell Register logic option for the specified register in a MAX 7000E device so that the register can be implemented as a fast input register. However, the specified register does not qualify to be a fast input register for one of the following reasons:

The register is not implemented as a D flipflop.

The data input to the register is not directly fed by a single input pin; i.e., if there is logic between the pin and the register.

The register feeds an output pin.

The register is assigned to a buried logic cell.

ACTION:	Perform one of the following actions:

Implement the register as a D flipflop.

Change the logic so that only a single input pin feeds the data input to the register.

Change the logic so that the register does not feed an output pin.

Make sure the register is not assigned to a buried logic cell.

See also:

Assigning an Individual Logic Option or Synthesis Style

Assigning a Pin, Location, or Chip


Illegal logic cell [or pin] number <number> for node <name>
Illegal logic cell [or pin] <number> for node <name>

CAUSE:	You assigned a node to a pin or a logic cell that does not exist on the currently selected device. This message can occur if, for example, you assigned a node to LC100 or a pin to 100 in a 16-pin device.

ACTION:	Reassign the node to a legal pin or logic cell, or turn on the OK to Ignore All Pins/All Buried LCs, OK to Ignore Minimal Pins/All Buried LCs, or the OK to Ignore Buried LCs option in the Override User Assignments dialog box, as described in Adjusting the Fit During Compilation. Refer to Devices & Adapters or to individual device data sheets for legal pin and logic cell numbers.

See also:

Assigning a Pin, Location, or Chip

Devices & Adapters

MAX+PLUS II Messages

Message Format


Illegal assignment to <text> on node <name>

CAUSE:	You assigned a node to a LAB, row, column that does not exist on the currently selected device. For example, you may have assigned a node to a row on a MAX 7000 device, but rows only exist on FLEX 8000 devices.

ACTION:	Reassign the node to a legal LAB, or turn on the OK to Ignore All Pins/All Buried LCs, OK to Ignore Minimal Pins/All Buried LCs, or OK to Ignore Buried LCs option in the Override User Assignments dialog box, as described in Adjusting the Fit During Compilation. Refer to Devices & Adapters or to individual device data sheets for legal LAB names.

See also:

Assigning a Pin, Location, or Chip

Devices & Adapters

MAX+PLUS II Messages

Message Format


Illegal logic cell [or pin] syntax <text> [for node <name>]

CAUSE:	You entered one or more illegal characters when you entered a logic cell or pin assignment.

ACTION:	Delete or re-enter the assignment. In FLEX 8000 and MAX 9000 devices, logic cells have "numbers" of the format LC<number>_<LAB name>, where <number> ranges from 1 to 8 and <LAB name> consists of the row letter and column number of the LAB. In Classic, MAX 5000, and MAX 7000 devices, logic cells have numbers of the format LC<number>, where <number> is specified in Devices & Adapters or individual device data sheets.

See also:

Assigning a Pin, Location, or Chip

Deleting an Assignment

MAX+PLUS II Messages

Message Format


Logic cell <name> in device <name> requires too many <number> expanders
Logic cell <name> in device <name> requires too many (<number>/<number>) shareable expanders

CAUSE:	The specified logic cell requires too many shareable expanders, which have been implemented with EXP buffers.

ACTION:	Change the project to use fewer EXP buffers, insert LCELL buffers after EXP buffers, or turn on the Multi-Level Synthesis option in the Global Project Logic Synthesis dialog box (Assign menu). If you still get this message, call Altera Applications for assistance.

See also:

MAX+PLUS II Messages

Message Format


Logic cell <node name> requires too many <resource>
Logic cell <name> requires too many (<number>/<number>) [<text>]

CAUSE:	To implement your project, the specified logic cell requires more of the specified resource than is available in a single logic cell. This resource may be inputs from the PIA or shareable expanders.

ACTION:	Try to simplify the project’s logic by inserting LCELL or SOFT buffers. During project processing, these buffers may allow the Compiler to reduce the number of unique inputs that feed the logic cell. Or, change the project to use fewer EXP buffers.

See also:

Fitting & Refitting a Project

MAX+PLUS II Messages

Message Format


Too many inputs or buried logic cells assigned to I/O pins [as a result of user assignments]

CAUSE:	The device has adequate logic capacity for the project, but you have assigned too many input pins or buried logic cells to I/O pins, so there are not enough I/O pins left to implement the project.

ACTION:	Remove some of the input pin or buried logic cell assignments from the I/O pins. You can assign an input pin to a dedicated input pin instead of an I/O pin, or allow the Compiler to ignore pin and buried logic cell assignments with the Override User Assignments dialog box, as described in Adjusting the Fit During Compilation.

See also:

Assigning a Pin, Location, or Chip

Deleting an Assignment

Devices & Adapters

Fitting & Refitting a Project

MAX+PLUS II Messages

Message Format


Merging cliques <name> and <name>

CAUSE:	The same logic cell was assigned to multiple cliques, so the cliques were merged into one clique.

ACTION:	No action is required.

See also:

Assigning a Clique

MAX+PLUS II Messages

Message Format


Multiple nodes assigned to same location <name>

CAUSE:	You have assigned two or more nodes to the specified logic cell. Register packing can only occur when of a combinatorial logic function and a register with a single data input are placed in the same logic cell.

ACTION:	If register packing is not desired, assign the nodes to different logic cells. If register packing is desired, assign only an appropriate combinatorial logic function and register to the specified logic cell.

See also:

Assigning a Pin, Location, or Chip

Deleting an Assignment

MAX+PLUS II Messages

Message Format


No fit found, generating Report File

CAUSE:	The Compiler could not find a fit for the project. For example, you may have a single logic cell with a very large fan-in in a low-pin-count device, such as an EPM5016.

ACTION:	Check the other messages issued by the Compiler. You may need to change resource and/or device assignments, or remove assignments to allow the Compiler to fit an automatic fit. If you recompile the project, you can also try allowing the Compiler to ignore assignments in the Override User Assignments dialog box, as described in Adjusting the Fit During Compilation. If no other remedies work, contact Altera Applications for assistance.

See also:

Assigning a Pin, Location, or Chip

Assigning a Clique

Assigning a Device

Devices & Adapters

Fitting & Refitting a Project

MAX+PLUS II Messages

Message Format

Partitioning a Project

Recommended reading:

AB60 (Estimating a Design Fit)


No fit possible because there are no dual I/O feedback logic cells in selected devices

CAUSE:	The project has a logic cell that uses dual I/O feedback, but the specified device(s) do not support this feature.

ACTION:	Choose different devices.

See also:

Assigning a Device

Devices & Adapters

MAX+PLUS II Messages

Message Format


No fit possible due to too many expanders feeding one logic cell
No fit possible because too many shareable expanders feed one logic cell

CAUSE:	There are too many shareable expanders feeding one logic cell to fit in the selected device.

ACTION:	Try to simplify the project’s logic by inserting LCELL or SOFT buffers. During project processing, these buffers may allow the Compiler to reduce the number of unique inputs that feed the logic cell.

See also:

Fitting & Refitting a Project

MAX+PLUS II Messages

Message Format


No fit possible for <name> family due to use of array clock and output enable/global clock equation on the same logic cell
No fit possible for <name> family because there is an array Clock and Output Enable equation on the same logic cell

CAUSE:	The project contains logic cells that use array Clocks and Output Enable equations, which are not supported in the specified family.

ACTION:	Change to a different device family or change the array Clock into a global Clock.

See also:

Assigning a Device

Devices & Adapters

MAX+PLUS II Messages

Message Format


No fit possible for <name> family because there is an illegal equation on <text>

CAUSE:	The project has an equation on a register input (such as a Preset), that is not supported for the current device family.

ACTION:	Change the device family or change the project logic.

See also:

Assigning a Device

Devices & Adapters

MAX+PLUS II Messages

Message Format

Preset & Clear Configuration Guidelines

Project Reliability Guidelines


No partition possible because logic cell <name> requires too many (<number>/<number>) inputs from PIA

CAUSE:	To implement your project, the specified logic cell requires more inputs from the PIA than are available in the current device. The ratio shown is the number of PIA inputs requested to the number available in the current device requested.

ACTION:	Try to simplify the project’s logic by inserting LCELL or SOFT buffers. During project processing, these buffers may allow the Compiler to reduce the number of unique inputs that feed the logic cell.

See also:

Devices & Adapters

Fitting & Refitting a Project

MAX+PLUS II Messages

Message Format


Node <name> assigned to <location> and <location>
Node <name> assigned to <text> and <text>

CAUSE:	The specified node was assigned to different locations on the same device.

ACTION:	Remove or change one of the assignments, or allow the Compiler to ignore assignments with the Override User Assignments dialog box, as described in Adjusting the Fit During Compilation.

See also:

Assigning a Pin, Location, or Chip

Deleting an Assignment

MAX+PLUS II Messages

Message Format


Node <name> assigned to a VCC or GND pin

CAUSE:	You assigned a node to a VCC or GND pin on the device.

ACTION:	Change the assignments or choose to ignore pin assignments with the Override User Assignments dialog box, as described in Adjusting the Fit During Compilation, or reassign the node to another pin. Refer to Devices & Adapters for legal pin numbers.

See also:

Assigning a Pin, Location, or Chip

Deleting an Assignment

MAX+PLUS II Messages

Message Format


Node <name> assigned to multiple output positions
Node <name> assigned to multiple output pins

CAUSE:	The specified node was assigned to more than one output pin.

ACTION:	Change or remove all but one of the assignments, or allow the Compiler to ignore pin assignments with the Override User Assignments dialog box, as described in Adjusting the Fit During Compilation.

See also:

Assigning a Pin, Location, or Chip

Deleting an Assignment

MAX+PLUS II Messages

Message Format


Node <name> is assigned to more than one device
Node <name> assigned to more than one device

CAUSE:	The specified node was assigned to more than one device. Only input pins can be assigned to more than one chip.

ACTION:	Change or remove all but one of the assignments, or allow the Compiler to ignore chip assignments in the Override User Assignments dialog box, as described in Adjusting the Fit During Compilation.

See also:

Assigning a Pin, Location, or Chip

Deleting an Assignment

MAX+PLUS II Messages

Message Format


Nodes <name> and <name> are assigned to the same location ... they require too many (<number>/<number>) product terms
Nodes <name> and <name> are assigned to the same location -- can’t implement register packing because they require too many (<number>/<number>) product terms

CAUSE:	You have assigned the specified nodes to the same location. Register packing cannot be implemented because it would require too many product terms.

ACTION:	If you did not intend to assign the nodes to the same location, or if register packing is not required, assign the specified nodes to different locations. If register packing is required, simplify the logic that feeds the specified nodes to reduce the number of product terms required to implement both nodes in the same logic cell.

See also:

Assigning a Pin, Location, or Chip

Deleting an Assignment

MAX+PLUS II Messages

Message Format


Nodes <name> and <name> are assigned to the the same location ... both feed I/O cells or Embedded Array Blocks
Nodes <name> and <name> are assigned to the the same location -- can’t implement register packing because both feed I/O cells or Embedded Array Blocks

CAUSE:	You have assigned the specified nodes to the same location, and both nodes feed I/O cells or Embedded Array Blocks. Register packing cannot be implemented because one node can feed an I/O cell.

ACTION:	If you did not intend to assign the nodes to the same location, or if register packing is not required, assign the specified nodes to different locations.

See also:

Assigning a Pin, Location, or Chip

Deleting an Assignment

MAX+PLUS II Messages

Message Format


Nodes <name> and <name> are assigned to the the same location ...the same Logic Array Block
Nodes <name> and <name> are assigned to the the same location -- can’t implement register packing because it would require too many (<number>/<number>) nodes to be in the same LAB

CAUSE:	You have assigned the specified nodes to the same location. Register packing cannot be implemented because it would require too many nodes to be in the same LAB.

ACTION:	If you did not intend to assign the nodes to the same location, or if register packing is not required, assign the specified nodes to different locations. If register packing is required, reduce the fan-out  of the specified nodes or remove the nodes or their fan-out from any cliques to which they are assigned.

See also:

Assigning a Pin, Location, or Chip

Deleting an Assignment

MAX+PLUS II Messages

Message Format


Nodes <name> and <name> are assigned to the the same location ...feed the same LAB
Nodes <name> and <name> are assigned to the the same location -- can’t implement register packing because it would require too many (<number>/<number>) signals to feed the same LAB

CAUSE:	You have assigned the specified nodes to the same location. Register packing can not be implemented because it would require too many signals to feed the same LAB.

ACTION:	If register packing is not required, assign the specified nodes to different locations. If register packing is required, reduce the fan-in of the specified nodes or reduce the fan-in or the fan-out of cells in which register packing has been implemented.

See also:

Assigning a Pin, Location, or Chip

Deleting an Assignment

MAX+PLUS II Messages

Message Format


Nodes <name> and <name> are assigned to the the same location ...currently assigned to <text>
Nodes <name> and <name> are assigned to the the same location -- can’t implement register packing because node <name> must be in the same LAB, but is currently assigned to <text>

CAUSE:	You have assigned the specified nodes to the same location. Register packing can not be implemented because one of the nodes drives another node that is currently assigned to a different chip, LAB, column, or row. The other node must be in the same LAB as the two specified nodes in order to implement register packing.

ACTION:	If register packing is not required, assign the specified nodes to different locations. If register packing is required, reassign the other node to be in the same chip, column, row, and LAB as the two specified nodes.

See also:

Assigning a Pin, Location, or Chip

Deleting an Assignment

MAX+PLUS II Messages

Message Format


Nodes <name> and <name> are assigned to the the same location ... nodes are not compatible
Nodes <name> and <name> are assigned to the the same location -- can’t implement register packing because nodes are not compatible

CAUSE:	You have assigned the specified nodes to the same location. Register packing can only occur when of a combinatorial logic function and a register with a single data input are placed in the same logic cell.

ACTION:	Assign the specified nodes to different locations.

See also:

Assigning a Pin, Location, or Chip

Deleting an Assignment

MAX+PLUS II Messages

Message Format


 Node <name> has an input assignment to chip <name> but is not used as an input on this chip

CAUSE:	You assigned the specified node to an input pin on the specified chip, but the node is not an input to this chip.

ACTION:	Check whether the node is an input to the assigned chip and whether it actually drives logic in the chip.

See also:

MAX+PLUS II Messages

Message Format


Node <name> has assignments but doesn’t exist or is a primitive array

CAUSE:	You assigned resources to a node that does not exist. The node either never existed in the project’s design files, or was removed during logic synthesis and minimization. Or, you may have entered a resource assignment on a primitive that is connected to one or more buses to form a primitive array. This message may also occur if you assigned resources to a macrofunction that does not contain any hard logic functions when you used pre-version 5.0 synthesis.

ACTION:	Check the design files for accuracy. Remove unused resource assignments and make sure you have not entered assignments on symbols in a primitive array. Refer to Guidelines for Working with Assignments for more information on how to enter assignments for a primitive array.

See also:

Deleting an Assignment

MAX+PLUS II Messages

Message Format

Partitioning a Project


Node <name> has conflicting assignments for Turbo Bit and Slow Slew Rate options -- ignoring Turbo Bit assignment

CAUSE:	The specified node has conflicting assignments for the Slow Slew Rate and Turbo Bit options: both options are either turned off or turned on. In MAX 7000E devices, the Slow Slew Rate option and the Turbo Bit option are controlled by a single bit. Therefore, only one of these options can be turned on at any one time. If both options are turned on or if both options are turned off, the Compiler uses the Slow Slew Rate setting and ignores the Turbo Bit setting.

ACTION:	Change the Slow Slew Rate and Turbo Bit option settings so that one option is turned on and the other is turned off.

See also:

Assigning an Individual Logic Option or Synthesis Style

Defining a Logic Synthesis Style

Deleting an Assignment

Logic Synthesis Style & Logic Option Rules

MAX+PLUS II Messages

Message Format


Non-input node <name> assigned to dedicated input

CAUSE:	You assigned an OUTPUT, OUTPUTC, BIDIR, or BURIED node to a dedicated pin on the device.

ACTION:	Choose to ignore pin assignments in the Override User Assignments dialog box, as described in Adjusting the Fit During Compilation, or reassign the node to a legal pin. Refer to Devices & Adapters for legal pin numbers.

See also:

Assigning a Pin, Location, or Chip

Deleting an Assignment

MAX+PLUS II Messages

Message Format


Partitioner device limit exceeded

CAUSE:	You have tried to partition the project among 99 or more devices, which is the maximum allowed.

ACTION:	Specify a smaller number of devices for partitioning.

See also:

Devices & Adapters

MAX+PLUS II Messages

Message Format

Partitioning a Project


Partitioning is not available for FLEX architecture in the current version of MAX+PLUS II
Partitioning support is not yet available for the <device family name> family in the current version of MAX+PLUS II

CAUSE:	You attempted to partition a project that is implemented with the specified device family, however, the current version of MAX+PLUS II does not support partitioning for this device family.

ACTION:	Fit the project into a larger device from the specified device family or use devices from a different device family.

See also:

Assigning a Device

Devices & Adapters

MAX+PLUS II Messages

Message Format


Partitioning will result in utilization less than <number>
Partitioning will result in utilization less than <number>%

CAUSE:	The project is difficult to partition because there are too many I/O pins, the percentage of reserved resources is too high, or the device(s) specified are large for the amount of logic. A large number of chips have thus been created relative to the number of logic cells in the project. The partitioning in progress may take a long time or may not be successful at all, and it will result in low device resource utilization (i.e., less than 50%).

ACTION:	Specify a smaller percentage of reserved resources, choose smaller devices or devices with more pins, or partition the project by entering your own resource assignments.

See also:

Assigning a Device

Deleting an Assignment

Devices & Adapters

MAX+PLUS II Messages

Message Format

Partitioning a Project

Specifying Global Project Security Bit & Reserved Resource Settings


Pin or logic cell assignment ignored for chip assigned to AUTO

CAUSE:	You made a pin or logic cell assignment, but did not assign the chip with the Device command (Assign menu) or assigned the chip to AUTO.

ACTION:	Remove the pin or logic cell assignment, or assign the chip to a specific device.

See also:

Adjusting the Fit During Compilation

Assigning a Device

Deleting an Assignment

Devices & Adapters

MAX+PLUS II Messages

Message Format

Specifying Devices for Automatic Device Selection


Pin or logic cell assignment ignored for node <name> -- logic is implemented in a different pin or logic cell

CAUSE:	You made a pin or logic cell assignment on the specified node, but the Compiler has ignored it because the node is not implemented as a pin or logic cell in the final synthesized project. This message may occur regardless of whether you are using standard synthesis or multi-level synthesis if the logic is implemented in another pin or logic cell. This message is also likely to occur if you are compiling with pre-version 5.0 synthesis and have assigned a pin or logic cell to a logic function that is not a hard logic function.

ACTION:	Remove the pin or logic cell assignment, or move the assignment to a logic function that is implemented in a pin or logic cell that the node feeds.

See also:

Adjusting the Fit During Compilation

Assigning a Device

Deleting an Assignment

Devices & Adapters

MAX+PLUS II Messages

Message Format


Pin assignment ignored for node <name>

CAUSE:	In your FLEX 8000 or MAX 9000 project, you assigned a buried node to a pin, but this signal does not feed another device in the project. You can only assign a buried node to a pin in a partitioned FLEX 8000 project. Therefore, the Compiler has ignored the assignment.

ACTION:	Remove the pin assignment, or assign the node to a logic cell instead.

See also:

Adjusting the Fit During Compilation

Assigning a Device

Assigning a Pin, Location, or Chip

Deleting an Assignment

MAX+PLUS II Messages

Message Format


Project does not fit in specified device(s)

CAUSE:	The project does not fit into the device(s) you specified, and you turned on the Ask Before Adding Extra Devices option in the Auto Device Selection dialog box (Assign menu).

ACTION:	To attempt to achieve a fit during the current compilation, turn on the Add Extra Devices as Needed, OK to Ignore Reserved Resources, or the Change to Auto Device Selection option in the Override User Assignments dialog box, as described in Adjusting the Fit During Compilation.

If you choose to stop the compilation and change settings before recompiling, you may wish to reduce the amount of reserved resources with the Global Project Device Options dialog box (Assign menu) before recompiling. If your project is partitioned among several devices, you may wish to remove chip assignments. You can also use the Auto Device Selection dialog box to turn off the Ask Before Adding Extra Devices option and/or specify larger device(s) for the project.

See also:

Deleting an Assignment

MAX+PLUS II Messages

Message Format

Specifying Devices for Automatic Device Selection


Project doesn’t fit. Do you wish to override some existing settings and/or assignments?etc
Project doesn’t fit. Do you wish to override some existing settings and/or assignments? Choosing No will end compilation and generate a Report File.

CAUSE:	With the resource and/or device assignments that currently exist, or the current settings in the Auto Device Selection dialog box (Assign menu), the project will not fit.

ACTION:	Choose Yes to open the Override User Assignments dialog box, as described in Adjusting the Fit During Compilation, which allows you to change some compilation settings and discard some or all device or resource assignments before continuing compilation. Choose No to terminate the compilation and generate a Report File that will help you identify problems in the project.

See also:

Fitting & Refitting a Project

MAX+PLUS II Messages

Message Format

Recommended reading:

AB60 (Estimating a Design Fit)


Project doesn’t fit -- no more AUTO devices allowed for <project name>

CAUSE:	You limited the number of devices that are available for automatic project partitioning in the Auto Device Selection dialog box (Assign menu), but the project requires more devices.

ACTION:	In the Auto Device Selection dialog box, change the # Allowed to a higher number or Unlimited.

See also:

MAX+PLUS II Messages

Message Format

Specifying Devices for Automatic Device Selection


Project has conflicting default assignments for Turbo Bit and Slow Slew Rate options -- etc
Project has conflicting default assignments for Turbo Bit and Slow Slew Rate options -- ignoring default Turbo Bit assignment

CAUSE:	The current project has conflicting default assignments for the Slow Slew Rate and Turbo Bit options: both options are either turned off or turned on. In MAX 7000E devices, the Slow Slew Rate and Turbo Bit options are controlled by a single bit. Therefore, only one of these options can be turned on at any one time. If both options are turned on or if both options are turned off, the Compiler uses the Slow Slew Rate setting and ignores the Turbo Bit setting.

ACTION:	Change the default Slow Slew Rate and Turbo Bit option settings so that one option is turned on and the other is turned off.

See also:

Assigning an Individual Logic Option or Synthesis Style

Defining a Logic Synthesis Style

Deleting an Assignment

Logic Synthesis Style & Logic Option Rules

MAX+PLUS II Messages

Message Format

Specifying Global Project Logic Synthesis Settings


Project has user pin or logic cell assignments, but has never been compiled before. For best fitting results, etc.
Project has user pin or logic cell assignments, but has never been compiled before. For best fitting results, let the Compiler choose the first set of assignments instead.

CAUSE:	You entered resource assignments for a new project. However, in the current device family, Altera recommends allowing the Compiler to make the first set of assignments.

ACTION:	If you cannot fit your project, clear your assignments, then recompile the project to allow the Compiler to choose completely new assignments.

See also:

Clearing Assignments for a Project

Fitting & Refitting a Project

MAX+PLUS II Messages

Message Format


Project won’t fit with current constraints for <device name>

CAUSE:	In order to find a legal partition, resources need to be moved out of the specified device.

ACTION:	Select any item in the Override User Assignments dialog box to ignore, as described in Adjusting the Fit During Compilation.

See also:

Fitting & Refitting a Project

MAX+PLUS II Messages

Message Format


Register <name> and node <name> are assigned to the same location...2 or more product terms etc.
Register <name> and node <name> are assigned to the same location -- can’t implement register packing because the register has 2 or more product terms on its data input

CAUSE:	You have assigned the specified register to the same location as another register, so that more than one product term feeds the data input to the register. Register packing cannot be implemented because it allows only one product term to feed the register.

ACTION:	If register packing is not required, assign the specified nodes to different locations. If register packing is required, simplify the logic that feeds the primary input of the specified register to reduce the required number of product terms to one.

See also:

Assigning a Pin, Location, or Chip

Deleting an Assignment

MAX+PLUS II Messages

Message Format


Reserve resources for <text> is <number>
Reserved resource percentage for <text>: <number>

CAUSE:	You have reserved the specified percentage of logic cells or pins.

ACTION:	No action is required.

See also:

Fitting & Refitting a Project

MAX+PLUS II Messages

Message Format


Reserved unused input pin <name> for future use because it has a pin assignment -- etc.
Reserved unused input pin <name> for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board

CAUSE:	The Compiler has reserved the specified input pin because it has a pin assignment. However, this input pin is not currently used in the project (i.e., the pin is unconnected). This message may indicate that you have forgotten to connect the pin to the rest of the logic.

ACTION:	If you did not intend to reserve an unconnected input pin, either delete the pin assignment or connect the pin to logic. If you intended to reserve the pin, you must ensure that the pin is driven by a signal on your board and is not left unconnected. If necessary, you can tie the input to GND until you are ready to use it.

See also:

Assigning a Pin, Location, or Chip

Deleting an Assignment

MAX+PLUS II Messages

Message Format


Selecting an <EPLD> as an AUTO device for <chip name>
Selecting a device from <device family> family for AUTO device <chip name>

CAUSE:	The Compiler is selecting a device from the specified device family for a chip that you have assigned to an AUTO device.

ACTION:	No action is required.

See also:

Assigning a Device

MAX+PLUS II Messages

Message Format


Stopping after current fitting attempt by request

CAUSE:	You chose the Stop After This Attempt button in the Partitioner/Fitter Status dialog box. The Fitter will complete the current fitting attempt. If the fitting attempt is successful, the Compiler will continue project compilation. If the fitting attempt is unsuccessful, the Compiler will stop compiling the project and generate a Report File.

ACTION:	No action is required.

See also:

Checking the Partitioner & Fitter Status During Compilation

Fitting & Refitting a Project

Partitioning a Project

MAX+PLUS II Messages

Message Format


Stopping after generating Report File by request

CAUSE:	You chose the Stop & Create Report File button in the Partitioner/Fitter Status dialog box. The Fitter will stop the current fitting attempt and generate a Report File for the project.

ACTION:	No action is required.

See also:

Checking the Partitioner & Fitter Status During Compilation

Fitting & Refitting a Project

Partitioning a Project

MAX+PLUS II Messages

Message Format


Trying to find partition/fit with items ignored by user
 Trying to find new partition/fit after discarding assignments by request of the user

CAUSE:	You selected one or more types of resource assignments to ignore with the Override User Assignments dialog box, as described in Adjusting the Fit During Compilation, so the Compiler is attempting to find a partition or fit for the project by overriding the resource assignments you have specified.

ACTION:	No action is required. After compilation, you may wish to back-annotate the assignments made by the Compiler.

See also:

Back-Annotating Assignments for a Project

Fitting & Refitting a Project

MAX+PLUS II Messages

Message Format


The following messages must be re-checked after 6.0


Project contains <number> pins driven by Output Enable signals that could be implemented using open-drain outputs -- to improve
Project contains <number> pins driven by Output Enable signals that could be implemented using open-drain outputs -- to improve timing and fitting, turn on the Automatic Open-Drain Pins option in the Global Project Synthesis dialog box

CAUSE:	The current project contains pins that could be better implemented using open-drain outputs.

ACTION:	No action is necessary. To improve project performance and fitting, follow the instructions listed in the message.

See also:

MAX+PLUS II Messages

Message Format


Nodes <name> and <name> are assigned to the same location -- can’t implement register packing because they require too many (<nu
Nodes <name> and <name> are assigned to the same location -- can’t implement register packing because they require too many (<number>/<number>) LUT inputs

CAUSE:	You have assigned the specified nodes to the same location. Register packing cannot be implemented because it would require too many Look Up Table (LUT) inputs.

ACTION:	If you did not intend to assign the nodes to the same location, or if register packing is not required, assign the specified nodes to different locations. If register packing is required, simplify the logic that feeds the specified nodes to reduce the number of Look Up Table inputs required to four or less.

See also:

MAX+PLUS II Messages

Message Format


Insert LCELL after node <name> to satisfy fan-out limit

CAUSE:	You have specified a value for the Fan-In per Logic Cell option in the Custom Fitting Settings section of the Fitter Settings dialog box (Processing menu). However, the secondary fan-outs for the specified node are greater than the limit, so MAX+PLUS II will insert an LCELL after this node to reduce the fan-out.

ACTION:	No action is required if you are satisfied with the current fan-out limit. If you want to change the current limit to allow more fan-out, edit the value for the Fan-In per Logic Cell option in the Custom Fitting Settings section of the Fitter Settings dialog box.

See also:

MAX+PLUS II Messages

Message Format


Ignored fan-out limit set on node <name> -- has to be at least 2

CAUSE:	You have specified a value for the Fan-In per Logic Cell option in the Custom Fitting Settings section of the Fitter Settings dialog box (Processing menu). However, the value specified is less than 2., which is the minimum allowed

ACTION:	Edit the value for the Fan-In per Logic Cell option in the Custom Fitting Settings section of the Fitter Settings dialog box so that the value is greater than 2.

See also:

MAX+PLUS II Messages

Message Format


NOT Gate Push-Back has occurred on some registers -- if the power-up condition is crucial to the operation of the circuit, use t
NOT Gate Push-Back has occurred on some registers -- if the power-up condition is crucial to the operation of the circuit, use the asynchronous Clear/Preset on the register to ensure proper operation

CAUSE:	NOT Gate Push-Back has occurred on some registers in the current project.

ACTION:	No action is required if the power-up state of the circuit is not crucial to its operation. If the power-up state of the circuit is crucial to its operation then you should exchange the existing asynchronous Clear and Preset signals to the flipflop on which NOT Gate Push-Back has occurred. If you do not want NOT Gate Push-Back to occur, turn off the NOT Gate Push-Back option in the Advanced Options dialog box (Assign menu).

See also:

MAX+PLUS II Messages

Message Format


NOT Gate Push-Back has occurred for some registers -- if the power-up condition is crucial to the operation of the circuit, add
NOT Gate Push-Back has occurred for some registers -- if the power-up condition is crucial to the operation of the circuit, add an asynchronous Clear/Preset signal to correct the power-up condition and ensure proper operation

CAUSE:	NOT Gate Push-Back has occurred on some registers in the current project.

ACTION:	No action is required if the power-up state of the circuit is not crucial to its operation. If the power-up state of the circuit is crucial to its operation then you should add an asynchronous Clear or Preset signal to the flipflop on which NOT Gate Push-Back has occurred. If you do not want NOT Gate Push-Back to occur, turn off the NOT Gate Push-Back option in the Advanced Options dialog box (Assign menu).

See also:

MAX+PLUS II Messages

Message Format


-----BEGINNING OF NON-TRANSLATED TEXT-----

The following ni_msgs.msg messages are not documented in this file:

FNI_PROJECT_TOO_COMPLEX	COMESS.MAC

ENI_NODE_MISSING_SOURCE	COMESS.MAC

other info:

FNI_ILLEGAL_CONNECTION	SPR 16496

ENI_ILLEGAL RESOURCE	SPR 16507	?probe file

ENI_NULL_CHIP_ASSIGNMENT	SPR 16508	?probe file

ENI_MISSING_AT_SIGN	SPR 16509	? probe file

The following messages from other .msg files are documented here

wlnk_port_not_in_snf	lnkmsgs.msg

-----END OF NON-TRANSLATED TEXT-----


Can’t find a pin that corresponds to [macrofunction <name>] pinstub <name> [in <filename>.snf]
Can’t find a pin that corresponds to [macrofunction <name>] pinstub/port <name> [in <filename>.snf]

CAUSE:	There is a discrepancy between the inputs and outputs of a design file (or, if you are compiling a super-project with the Linked SNF Extractor, of an SNF) and the symbol or Function Prototype that represents it.

If the error occurs for a Graphic Editor file, the file contains a symbol that includes the specified pinstub name, but this name does not exist in the design file (or SNF) that the symbol represents. This message usually occurs if you have changed the lower-level design file’s inputs or outputs but have not updated the symbol or Function Prototype to reflect the changes.

If the error occurs in a TDF, the Logic Section uses a port of an instance of a primitive or macrofunction that does not exist in the design file (or SNF) for that instance. This message can occur in a TDF if a port name in the Function Prototype for the design file does not match a pin or port name in the design file (or SNF).

ACTION:	If the error occurs for a symbol in a Graphic Editor file, open the lower-level file and use Edit Symbol (File menu) to manually update the symbol that represents the file, or use Create Default Symbol (File menu) to automatically generate a new symbol. Then use Update Symbol (Symbol menu) to update the higher-level file.

If the error occurs in a TDF, correct the Function Prototype for the lower-level design file. If you use an Include File to call the Function Prototype, you can open the lower-level file and use Create Default Include File (File menu)  to automatically generate a new Function Prototype.

If the symbol or Function Prototype represents an SNF and not a design file, creating a new symbol or Function Prototype will only correct the error if the logic in the SNF is up-to-date. Therefore, you may wish to also recompile the project that the symbol or Function Prototype represents.

See also:

Combining Multiple Projects for Simulation

Creating a Default Include File

Creating the Default Symbol for a File

Editing the Symbol for a File

Implementing a Hierarchical Project (AHDL)

MAX+PLUS II Messages

Message Format

Updating a Symbol in a Graphic Editor File


Can't import state machine <node name> -- it is not an output

CAUSE:	You have attempted to import a TDF state machine from another design file but the state machine in that file was not an output.

ACTION:	Only import state machines that are valid outputs of another design file.

See also:

Importing & Exporting State Machines (AHDL)

MAX+PLUS II Messages

Message Format


Devices from more than one family specified

CAUSE:	You have created a multi-device project that uses devices from more than one device family.

ACTION:	Use devices from only one device family.

See also:

Assigning a Device

Devices & Adapters

MAX+PLUS II Messages

Message Format


Flattened project hierarchy reveals a node loop near node <name>

CAUSE:	As the Database Builder flattened the hierarchy of design files, a node loop (i.e., wire loop) was detected.

ACTION:	Check the logic associated with the specified node name and remove the node loop.

See also:

MAX+PLUS II Messages

Message Format


Ignored illegal assignment for node <name>

CAUSE:	Your default logic synthesis style for the project uses pre-version 5.0 logic synthesis. Therefore, all resource assignments are ignored if they are not entered on hard logic functions. Since you entered an assignment on a node that does not represent hard logic, the assignment has been ignored. If the error appears in an EDIF Input File, the message may not report the node name.

ACTION:	When you use pre-version 5.0 synthesis, make resource assignments only on hard logic functions.

See also:

Assigning a Clique

Assigning a Pin, Location, or Chip

Assigning an Individual Logic Option or Synthesis Style

Defining a Logic Synthesis Style

Guidelines for Working with Assignments

MAX+PLUS II Messages

Message Format

Specifying Global Project Logic Synthesis Settings


Ignored I/O Cell Register logic option setting for node <name>

CAUSE:	You have specified an I/O Cell Register logic option assignment as "Off" (IO_CELL_REGISTERS = OFF) on the specified node, which is also assigned to a physical I/O cell register location on a chip. Since the node is assigned to a physical I/O cell, the Compiler has ignored the logic option assignment.

ACTION:	Either remove the I/O Cell Register logic option assignment on the node, or turn the I/O Cell Register logic option "On."

See also:

Assigning a Pin, Location, or Chip

Assigning an Individual Logic Option or Synthesis Style

Defining a Logic Synthesis Style

Guidelines for Working with Assignments

MAX+PLUS II Messages

Message Format

Specifying Global Project Logic Synthesis Settings


Ignored all <assignment type> assignments by request of the user

CAUSE:	You used the Ignore Project Assignments command to specify that the specified assignment type should be ignored during project compilation.

ACTION:	No action is required. If you did not intend for the specified assignment type to be ignored, choose Ignore Project Assignments and change the appropriate settings.

See also:

Guidelines for Working with Assignments

Ignoring Project Assignments during Compilation

MAX+PLUS II Messages

Message Format


Ignored pin assignment for node <name>

CAUSE:	An ADF or SMF in the project contains the specified pin assignment. MAX+PLUS II no longer accepts resource assignments from ADFs or SMFs, so the pin assignment has been ignored.

ACTION:	Delete the pin assignment from the ADF or SMF. You can then choose Pin/Location/Chip (Assign menu)  or use the Floorplan Editor to make a new pin assignment.

See also:

Assigning a Pin, Location, or Chip

Clearing Assignments for a Project

Guidelines for Working with Assignments

MAX+PLUS II Messages

Message Format


Ignored redefinition of resource assignment (<resource> assignment) for node <name>

CAUSE:	You have made two or more conflicting pin, logic cell, embedded cell, I/O cell, chip, clique, LAB, EAB, row, column, timing, or logic option assignments for the same node, so the Compiler has ignored all but the first assignment. (Logic option assignments also include logic synthesis style assignments.)

ACTION:	Either remove one of the assignments or make both assignments the same.

See also:

Assigning a Clique

Assigning a Pin, Location, or Chip

Assigning an Individual Logic Option or Synthesis Style

Assigning Connected Pins

Assigning Individual Timing Requirements

Deleting an Assignment

Guidelines for Working with Assignments

Logic Synthesis Style & Logic Option Rules

MAX+PLUS II Messages

Message Format


Ignored redefinition of Security [or Turbo] Bit setting for device [or node] <name>

CAUSE:	The Turbo or Security Bit assignment for the specified node or device has been given two conflicting values.

ACTION:	Either remove the conflicting assignments or change them so that they do not conflict.

See also:

Assigning an Individual Logic Option or Synthesis Style

Deleting an Assignment

MAX+PLUS II Messages

Message Format

Specifying Individual Device Security & Turbo Bit Options


Illegal connection between port <name> and pin <name>

CAUSE:	You have changed the I/O type of a pin type in a subdesign file and compiled the project without updating the old symbol. For example, this message occurs if you change an OUTPUT to an INPUT in a subdesign but do not update the symbol in the GDF before recompiling.

ACTION:	Open the lower-level file and use Edit Symbol (File menu)  to manually update the symbol that represents the file, or use Create Default Symbol (File menu)  to automatically generate a new symbol. Then use Update Symbol (Symbol menu)  to update the higher-level file.

See also:

Creating the Default Symbol for a File

Editing the Symbol for a File

MAX+PLUS II Messages

Message Format

Updating a Symbol in a Graphic Editor File


Illegal machine output pin <name>

CAUSE:	A MACHINE OUTPUT port was found in the top-level TDF, or the top-level WDF of your project contains a node with an I/O type of output pin and a node type of MACH (machine). These ports/pins may only be used to connect lower-level design files together in a hierarchical project; they may not be used as physical output pins for your project.

ACTION:	If the top-level file is a TDF, remove the MACHINE OUTPUT port or replace it with an OUTPUT port that is connected to a bit in the state machine. If the file is a WDF, you must use it at a lower level of the project hierarchy.

See also:

MAX+PLUS II Messages

Message Format

Ports (AHDL)

State Machines (AHDL)


Illegal or missing resource assignment <name> for node <name>

CAUSE:	You have either made an illegal resource assignment for a node or you have left out a pin or logic cell assignment after an at symbol (@).

ACTION:	Put a correct pin or logic cell assignment after the chip assignment.

See also:

Assigning a Clique

Assigning a Device

Assigning a Pin, Location, or Chip

Guidelines for Working with Assignments

MAX+PLUS II Messages

Message Format


Input pinstub/port <name> is not connected and has no default value

CAUSE:	The input to this pinstub (called a port in AHDL) has no default value. If the pinstub is in an Altera-provided symbol, you must connect an input. For TDFs, the default is the value that follows the port declaration in the Subdesign Section, e.g. <name> : INPUT = VCC;.

ACTION:	If the specified pinstub is in an Altera-provided symbol, connect an input to the pinstub. In a TDF, enter a default port value as shown above.

See also:

MAX+PLUS II Messages

Message Format

Ports (AHDL)


Missing a resource assignment for node <name>

CAUSE:	You have made a chip assignment for a node but one of the resource assignments in the list is missing or you have typed too many commas.

ACTION:	Remove any unnecessary commas in the chip assignment or make sure the assignment name is typed correctly.

See also:

Assigning a Clique

Assigning a Pin, Location, or Chip

Assigning an Individual Logic Option or Synthesis Style

Guidelines for Working with Assignments

MAX+PLUS II Messages

Message Format


Project has multiple devices -- <text> assignment for <pin/node name> must be associated with a device
Project has multiple devices -- <resource> assignment for <pin/node name> must be associated with a chip

CAUSE:	You made a pin or logic cell assignment for a node in a multi-device project but did not specify the chip.

ACTION:	Either specify the chip to which this pin or logic cell assignment belongs or fit the project into one device.

See also:

Assigning a Device

Assigning a Pin, Location, or Chip

MAX+PLUS II Messages

Message Format


Security Bit can only be set for devices -- ignored Security Bit setting for node <name>

CAUSE:	You have made a Security Bit assignment for an individual node. The Security Bit can only be set for entire devices.

ACTION:	Remove the Security Bit assignment from the node and set the Security Bit for the entire device.

See also:

Assigning a Device

Deleting an Assignment

MAX+PLUS II Messages

Message Format

Specifying Global Project Security Bit & Reserved Resource Settings

Specifying Individual Device Security & Turbo Bit Options


State machine <name> feeds logic

CAUSE:	The specified state machine in a TDF or WDF feeds a logic primitive in another file in the project hierarchy.

ACTION:	Remove all the connections between the state machine outputs and the logic primitive.

See also:

MAX+PLUS II Messages

Message Format


State name <name> has no corresponding definition in state machine <name>

CAUSE:	You have used a state name that was not defined for the imported state machine.

ACTION:	Use a state that has been defined for the state machine.

See also:

MAX+PLUS II Messages

Message Format

State Machines (AHDL)


Symbol <net ID number> does not match its design file: it has <number> pinstubs, but the design file has <number> pins
Symbol or Function Prototype <net ID number> does not match its design file: it has <number> pinstubs/ports, but the design file has <number> pins

CAUSE:	The specified symbol or Function Prototype has a different number of pinstubs (called ports in AHDL) than the design file that it represents. This message usually occurs if you have changed the number of inputs and outputs in a lower-level design file since you last created or edited the symbol or Function Prototype for it, so the symbol or Function Prototype does not reflect the changes.

ACTION:	If the error occurs for a symbol in a Graphic Editor file, open the lower-level file and use Edit Symbol (File menu)  to manually update the symbol that represents the file, or use Create Default Symbol (File menu)  to automatically generate a new symbol. Then use Update Symbol (Symbol menu)  to update the higher-level file.

If the error occurs in a TDF, correct the Function Prototype for the lower-level design file. If you use an Include File to call the Function Prototype, you can open the lower-level file and use Create Default Include File (File menu)  to automatically generate a new Function Prototype.

See also:

Creating a Default Include File

Creating the Default Symbol for a File

Editing the Symbol for a File

Function Prototype Statement (AHDL)

MAX+PLUS II Messages

Message Format


Too many characters in <node/pin name> (max.=32) [<text>]

CAUSE:	The specified node, pin name , or EDIF macrofunction or port name contains over 32 name characters, which is the maximum permitted. If this error occurs in an EDIF Input File, the project will still compile correctly, but some name information may be lost.

ACTION:	Change the name to be 32 name characters or less.

If this message occurs for an EDIF Input File, try generating a new hierarchical EDIF netlist file (not flattened), then recompiling the project.

If this message occurs for an XNF File, you may wish to turn on the Translate Internal Node Names into N<number> Format option available in the Compiler’s XNF Netlist Reader Settings dialog box (Processing menu)  before recompiling the project.

See also:

Compiling XNF Files

MAX+PLUS II Messages

Message Format


Duplicate name <name> for two or more primitives

CAUSE:	The Compiler found two or more node names, primitives, or macrofunctions that have the same name or instance name, or net (symbol ID). This message can occur if you are compiling files created with previous versions of MAX+PLUS II.

ACTION:	If the error occurs in a GDF, you must delete each of the specified duplicate symbols, then re-enter them with symbols from the current version of MAX+PLUS II. However, if you try to find the duplicate symbols with Message Processor’s Locate button, it can only locate the first symbol because all the duplicate symbols have the same symbol ID number. To find the other symbol(s) in the Graphic Editor, choose Find Text (Utilities menu) and specify the symbol ID number of the duplicate symbol, without the colon. If you don’t know the symbol ID number, use the Locate button to find the first symbol and make a note of the symbol ID number.

If the error occurs in another design file, call Altera Applications.

See also:

MAX+PLUS II Messages

Message Format


--------------------BEGINNING OF NON-TRANSLATED TEXT------------------------------------

The following messages are DBBMSGS.MSG messages documented by Sarah at the last minute. Need to be reviewed.

In the following cases, the messages should go into other .mac message files.

EDBB_RAM_FAMILY_HAS_NO_MEMORY	lpmmess.mac

--------------------END OF NON-TRANSLATED TEXT-----------------------------------------------


Illegal or missing device family -- use the Device command to select a device family

CAUSE:	The Compiler detected an illegal or missing device family name. The project’s AC may have been inadvertently edited by a user or corrupted by the system.

ACTION:	Choose Device (Assign menu), assign a device family from the Device Family drop-down list box, and then recompile the project.

See also:

Assigning a Device

Compiling a Project

MAX+PLUS II Messages

Message Format


Can’t find a pinstub or port that corresponds to pin <name>

CAUSE:	There is a discrepancy between the ports in a symbol or the Function Prototype that represents it and the design file (or, if you are compiling a super-project with the Linked SNF Extractor, the SNF). The port in the symbol or logic function has no corresponding pinstub or port in the design file.

ACTION:	If the error occurs for a symbol in a Graphic Editor file, open the lower-level file and use Edit Symbol (File menu) to manually update the symbol that represents the file, or use Create Default Symbol (File menu) to automatically generate a new symbol. Then use Update Symbol (Symbol menu) to update the higher-level file.

If the error occurs in a TDF, correct the Function Prototype for the lower-level design file. If you use an Include File to call the Function Prototype, you can open the lower-level file and use Create Default Include File (File menu)  to automatically generate a new Function Prototype.

If the symbol or Function Prototype represents an SNF and not a design file, creating a new symbol or Function Prototype will only correct the error if the logic in the SNF is up-to-date. Therefore, you may wish to also recompile the project that the symbol or Function Prototype represents.

See also:

MAX+PLUS II Messages

Message Format


Initial memory content file <name> contains errors

CAUSE:	The Compiler has detected errors in the Hexadecimal File (.hex) or Memory Initialization File (.mif) used to specify the initial content of a RAM or ROM memory block.

ACTION:	Use the Message Processor’s Locate button to locate the error(s) in the MIF or Hex File. After you correct the error(s), recompile the project.

See also:

Compiling a Project

Locating the Source of a Message

MAX+PLUS II Messages

Message Format


Memory <location> requires initialization

CAUSE:	You created a ROM memory block, but did not specify a Hexadecimal File (.hex) or Memory Initialization File (.mif) to use for initialization. A ROM memory block requires an initialization file.

ACTION:	Create or specify a MIF or Hex File for initialization of the ROM block, as described in Initializing RAM or ROM.

See also:

MAX+PLUS II Messages

Message Format


Segment <text> requires a connection to <name>, but this connection is illegal in memory <location> which has an incompatible me
Segment <text> requires a connection to <name>, but this connection is illegal in memory <location> which has an incompatible memory node

CAUSE:	The specified memory mode or configuration is illegally connected (i.e., it should not be connected to anything). For example, when you create a ROM memory, you must leave the Write-Enable and data-in nodes unconnected.

ACTION:	Remove the connection.

See also:

MAX+PLUS II Messages

Message Format


Segment <text> has a connection to <name>, but this connection is illegal for device <name>

CAUSE:	The specified device is illegally connected (i.e., the device pinstubs should not be connected to anything). For example, since a FLEX10K device does not contain a Block Enable, you should not connect anything to the BE.

ACTION:	Remove the connection.

See also:

MAX+PLUS II Messages

Message Format


Segment <text> requires a connection to <name> in memory <location>, which has an incompatible memory node

CAUSE:	The specified memory mode or configuration requires the designated connection, which does not currently exist. For example, If the memory is in syncronous mode, you must ensure that the Clock is connected.

ACTION:	Make a connection to the specified node.

See also:

MAX+PLUS II Messages

Message Format


Address and control inputs must be registered simultaneously for memory <location>

CAUSE:	You either set the address (i.e., RAM_ADDR_REG) or control (i.e., RAM_CTRL_REG) inputs. However, both of these inputs must be set at the same time in order to function correctly.

ACTION:	Either register both inputs or neither.

See also:

MAX+PLUS II Messages

Message Format


Segment <text> is too large (<number>) -- specify a smaller segment size

CAUSE:	You specified a segment size that exceeds the largest available space in the device.

ACTION:	Specify a segment size that is withing the maximum available (e.g., the maximum segment size for FLEX10K devices is 2048).

See also:

MAX+PLUS II Messages

Message Format


Memory <location> has a mode that is illegal for device family <name>

CAUSE:	The memory block has an invalid mode (or configuration) for the specified device family.

ACTION:	Remove the invalid mode (or configuration).

See also:

MAX+PLUS II Messages

Message Format


Current device family (<name>) does not support implementation of RAM or ROM

CAUSE:	You assigned a device family that does not offer RAM or ROM support.

ACTION:	Choose Device (Assign menu), and assign a device family that implements RAM or ROM (i.e., FLEX10K).

See also:

Assigning a Device

MAX+PLUS II Messages

Message Format


Node <name> must be fed by TRI primitive

CAUSE:	When a node is fed by more than one instance, the node is considered a tri_node and must be fed ONLY by TRI buffers. (The TRI buffers can be at different hierarchy levels.)

ACTION:	Replace the primitive that feeds the node with a TRI buffer, or add a TRI buffer after the primitive.

See also:

MAX+PLUS II Messages

Message Format


Hex file <name> cannot have the same name as the project or a chip within the project -- rename the file

CAUSE:	The Compiler cannot compile a Hexadecimal File (.hex) used for memory initialization that has the same name as the project or a chip name in the project. Since the Assembler module automatically generates <project name>.hex and/or <chip name>.hex for programming purposes, a memory initialization file with the same name will be overwritten.

ACTION:	Rename the memory initialization file or change the file extension to .mif (since the Compiler and Simulator also accepts Memory Initialization File for initialization). (MAX+PLUS II automatically assumes that the memory initialization file is in Hex File format if no file exists with a .mif extension.)

See also:

MAX+PLUS II Messages

Message Format


All assignments from EDIF Input File(s) have been added to the project’s ACF

CAUSE:	All assignments in EDIF files are automatically copied to the project’s ACF. This message is displayed if any of the EDIF input source files contain assignments (i.e., through property records).

ACTION:	If you wish to delete these assignments, you must do so by removing them from the EDIF file. If you remove the assignments from the ACF only, they will be copied into the ACF again when you recompile the project.

See also:

MAX+PLUS II Messages

Message Format


Logic successfully implemented in an EAB: <location> Number of inputs: <number> Number of outputs: <number> Required memory bits
Logic successfully implemented in an EAB: <location> Number of inputs: <number> Number of outputs: <number> Required memory bits = <number>

CAUSE:	This message displays the logic implementation in an EAB. If you turn on the Automatic Implement in EAB logic option, you may have difficulty fitting projects in FLEX 10K devices.

ACTION:	Use the the Automatic Implement in EAB logic option to identify possible subdesigns that can be implemented in an EAB. Once you determine which subdesigns are best implemented in an EAB, set the Implement in EAB  logic option (i.e., individual logic option) for those subdesigns. The number of inputs, outputs, and required memory bits can help you decide which macrofunctions are best implemented in an EAB (i.e., number of inputs should be less than but as close as possible to 11, e.g., 10 inputs is preferable to 6 inputs). You must also check that the number of required memory bits is not larger than the total number of memory bits in the device.

See also:

MAX+PLUS II Messages

Message Format


-----BEGINNING OF NON-TRANSLATED TEXT-----

I (Sarah) couldn’t get to the following messages. Sorry.

-----END OF NON-TRANSLATED TEXT-----


Using Automatic Implement in EAB option

CAUSE:	You turned on the Automatic Implement in EAB option.

ACTION:	No action. Compilation may be slower.

See also:

MAX+PLUS II Messages

Message Format


Illegal value <text> for logic option, which was used as a parameter -- ignored parameter

CAUSE:	You has instantiated a macrofunction and have specified a parameter (that is really a logic option) with an illegal value. For example, you would receive this message if you had set  TURBO_BIT to the value "FOO", because TURBO_BIT can only be set to  ON or OFF.

ACTION:	Read the appropriate help for the specific logic option to determine the value that should be specified. Then replace value with a valid one.

See also:

MAX+PLUS II Messages

Message Format


Can’t use logic option or predefined parameter <name> as a global parameter -- ignored parameter name

CAUSE:	You have defined a parameter with an illegal name. For example, this message would occur if you had specified  the device_family parameter, because  it is a system parameter, and illegal for a user to edit.

ACTION:	Remmove the illegal parameter, or change the parameter name to a legal parameter name.

See also:

MAX+PLUS II Messages

Message Format


Initial memory content file is required for memory <location> -- setting all initial values to 0

CAUSE:	The EAB is set to DB_RAM_INITIALIZE (i.e., the memory is either a ROM or a RAM with initialization content). This setting requires a memory initialization contents file.

ACTION:	Create a memory content file if one does not already exist, then specify the location, including the filename and extension, of the memory content file for the LPM_FILE parameter in the memory function. If the memory content file is in another directory (i.e. not the project directory) enter the absolute path.

You can also ignore this warning and and create initial values using the Initialize Memory command (Initialize menu) in the MAX+PLUS II SImulator.

See also:

MAX+PLUS II Messages

Message Format


Address inputs to all memory segments should be fed by the same node

CAUSE:	One or more memory segments in a RAM function have different address inputs. However, all address inputs to memory segments must be fed by the same node.

ACTION:	Make sure that every address input in the segment is connected to the same node.

See also:

MAX+PLUS II Messages

Message Format


Data inputs to all memory segments should be fed by the same node

CAUSE:	One or more memory segments in a RAM function have different data inputs. However, all data inputs to memory segments must be fed by the same node.

ACTION:	Make sure that every data input in the segment is connected to the same node.

See also:

MAX+PLUS II Messages

Message Format


Write Enable inputs to all memory segments should be fed by the same node

CAUSE:	One or more memory segments in a RAM function have different Write Enable inputs. However, all Write Enable inputs to memory segments must be fed by the same node.

ACTION:	Make sure that every Write Enable input in the segment is connected to the same node.

See also:

MAX+PLUS II Messages

Message Format


Can’t implement logic in an EAB <text>

CAUSE:	You have turned on the Implement in EAB logic option for the project. However, MAX+PLUS II could not implement the logic in an EAB for one of the following reasons:

IThe  logic has a combinatorial  loop

IOnly part of the outputs are fed by flipflops, but either all or none of the outputs must be fed by flipflops.

IThe specified pinstub must be fed by the specified pin in the function where the Implement in EAB logic option was set.

IThe specified pinstub in all registers must be fed by the same pin.

IThe logic contains one or more memory megafunctions, ADFs, WDFs, TRI primtives, BIDIR primtives, LATCH primtives, or state machines.

IThe logic contains too many inputs (i.e more than the maximum number of address lines in an EAB). The maximum number for FLEX 10k devices is 11.

ACTION:	Turn off the Implement in EAB logic option. Or read the text of the message and try one or more of the following actions:

If the logic contains a combinatorial loop, remove the combinatorial loop

IIf only part of the outputs are fed by flipflops, make sure that either all or none of the outputs are fed by flipflops

IIf the specified pinstub must be fed by the specified pin in the function where the Implement in EAB logic option was set, make sure the pin feeds the specified pinstub.

IIf the specified pinstub in all registers must be fed by the same pin, make sure the same pin feeds the specified pinstub in all registers.

IIf the logic contains one or more memory functions, lADFs, WDFs, TRI primtives, BIDIR primtives, LATCH primtives, or state machines remove the memory function(s), ADFs, WDFs, TRI primtives, BIDIR primtives, LATCH primtives, or state machines.

IIf the logic has too many inputs, subdivide the design into sub-blocks of the allowed number of inputs.

See also:

MAX+PLUS II Messages

Message Format


Parameter <name> was not used in <text>

CAUSE:	If an extensive parameter (e.g LATENCY) is passed to a macrofunction it must be used by this macrofunction. In not, this error will occur

ACTION:	Remove the extensive parameter from the macrofunction's parameter list (i.e. the list of parameters that are being passed to the  	macrofunction

See also:

MAX+PLUS II Messages

Message Format


Automatic Implement in EAB option successfully mapped more than the number of EABs available in the selected device -- multiple
Automatic Implement in EAB option successfully mapped more than the number of EABs available in the selected device -- multiple devices will be required

CAUSE:	User selected AUTO IMPLEMENT_IN_EAB in a large design. MPII has successfully implemented more macrofunctions in EABs than the limit in the device. This means than You will require several devices to fit his/her design.

ACTION:	If You does not want to use several devices, he/she should  select the best candidate macrofunctions and tag then with the  implement_in_eab individual logic option. Then, turn OFF the AUTO_IMPLEMENT_IN_EAB. We can recomend for You to select the biggest macrofunctions as candidates for the individual logic option. Steps: 1.- From the MDBB_IMPLEMENTED_IN_EAB message, select the required candidate. 2.- Locate the macrofunction with the LOCATE button. 3.- Using the Assign Logic Options command, assign the IMPLEMENT IN EAB logic option. 4.- Repeat 1 through 3 for all desired macrofunctions 5.- Turn OFF Automatic Implement_in_eab using the Global Logic Synthesis Assign Command

See also:

MAX+PLUS II Messages

Message Format


Message Processor Basic Tools
Basic Tools

Buttons & Options

Message Button

Locate Button

Locate in Floorplan Editor Option

Locate All Button

Help on Message Button

Input & Output Files

Assignment & Configuration File (.acf)

ACF Format

MAX+PLUS II Message File (.mmf)

Message Text File (.mtf)

MAX+PLUS II Initialization & System Files

maxplus2.idx file

maxplus2.ini File

Messages

MAX+PLUS II Messages

Message Format

Message Text

Probe, Resource & Device Assignments

Clique Assignments

Connected Pin Assignments

Device Assignments

Logic Option Assignments

Pin, Location & Chip Assignments

Probe Assignments

Timing Assignments

Status Bar & Toolbar

Status Bar

Toolbar


Message Button (Message Processor)
Message Button

Selects the next or previous message shown in the Message Processor window. Show me

Clicking Button 1 on the right side of the Message button select the next message in the list. Clicking Button 1 on the left side selects the previous message.

The text to the right of the Message button shows which numbered message is currently selected and the total number of messages.

See also:

Getting Help on a Message

Locating the Source of a Message


Locate Button (Message Processor)
Locate Button

Shortcut

Locates the source(s) of a selected message in a design file or ancillary file for the current project or in the Floorplan Editor. The text to the right of the Locate button shows which numbered location has been located and the total number of locations for the currently selected message. Show me

If you select a message in the Message Processor window and choose Locate, the design file or ancillary file that contains the source of the message is opened or brought to the front in a Graphic, Text, or Waveform Editor window on a PC, or in a File Viewer window on a workstation. The first location of the message is highlighted in the file. If you turn on the Locate in Floorplan Editor option, the Locate button locates message source(s) in the Floorplan Editor instead of the design files or ancillary files.

If the message has multiple locations, you can click Button 1 on the right side of the Locate button to find the next location or the left side to find the previous location. If you are locating a message that occurs during simulation, the first location found is in the SCF for the project unless the Locate in Floorplan Editor option is turned on. The Message Processor finds subsequent locations in the design files for the project.

This button is available only if the source of a message can be traced to a physical location in the project.

See also:

Getting Help on a Message

Locating the Source of a Message


Locate in Floorplan Editor Option (Message Processor)
Locate in Floorplan Editor Option

Directs the Message Processor to locate the source(s) of a selected message in the Floorplan Editor.  Show me

If this option is turned on, when you select a message in the Message Processor window and choose Locate, the Floorplan Editor window is opened or brought to the front, and the first location of the message is highlighted in the display area. If the message has multiple locations, you can then click Button 1 on the right side of the Locate button to find the next location or the left side to find the previous location. The Message Processor initially searches for location(s) in the Last Compilation Floorplan (Layout menu).

If this option is turned off, the Locate button locates the source(s) of a selected message in a design file or ancillary file for the current project.

If you wish to view all sources of a message in the Floorplan Editor simultaneously, you can turn on the Locate in Floorplan Editor option and then choose Locate All.

See also:

Getting Help on a Message

Locating the Source of a Message


Locate All Button (Message Processor)
Locate All Button

Simultaneously locates all source(s) of a selected message in the Floorplan Editor. The text to the left of the Locate All button shows the total number of locations for the currently selected message. Show me

When you turn on the Locate in Floorplan Editor option, select a message in the Message Processor window, and choose Locate All, the Floorplan Editor window is opened or brought to the front, and all location(s) of the message are highlighted in the first chip for the project. If the source(s) of a particular message are located in multiple chips of a multi-device project, one or more message box(es) are displayed in the Floorplan Editor to indicate these additional locations. To highlight locations in another chip, select a different chip from the Floorplan Editor’s Chip Name field and choose Locate All again.

The Message Processor initially searches for location(s) in the Last Compilation Floorplan (Layout menu).

This button is available only if the Locate in Floorplan Editor option is turned on, and the source of a message can be traced to a physical location in the Floorplan Editor.

See also:

Getting Help on a Message

Locating the Source of a Message


Help on Message Button (Message Processor)
Help on Message Button

Shortcut

Displays the cause and action of a selected message in MAX+PLUS II Help. Show me

If you select a message in the Message Processor window and choose Help on Message, the MAX+PLUS II Help window is opened or brought to the front, displaying the message, the likely cause of the message, and suggestions for corrective action.

See also:

Getting Help on a Message

MAX+PLUS II Messages


The Message Format panel is stored in mnmess because there are two panels that give the list of message prefixes (to make editing easier)


Message Text (Message Processor)
Message Text

Error, information, and warning messages for MAX+PLUS II applications and commands that run as background processes appear in Message Processor windows.

A Message Processor window opens automatically if any messages are generated when you run a background process. You can also open a window that contains the messages generated by another background process with Select Messages (File menu).

To get help on a specific message, select the message with the Message button or Button 1 and choose the Help on Message button, or use a shortcut.

You can print the messages in the Message Processor window or save them to a file for future reference.

See also:

Getting Help on a Message

Locating the Source of a Message

MAX+PLUS II Messages

Printing Messages

Saving Messages to a File

Selecting Messages to View


MAX+PLUS II Message File (.mmf) Description (Message Processor)
MAX+PLUS II Message File (.mmf)

A binary file (with the extension .mmf) containing messages and information that the Message Processor uses to display and locate errors in the current project.

The MMF contains error, information, and warning messages and message-locating data for all MAX+PLUS II applications and commands that can run as background processes. Each project has its own MMF.

You can save the messages that are displayed in the Message Processor window to a Message Text File.

See also:

Saving Messages to a File


Message Text File (.mtf) Description
Message Text File (.mtf)

An ASCII text file (with the extension .mtf) that contains a set of messages generated by a MAX+PLUS II background process.

In MAX+PLUS II for Windows, you can create an MTF with the Message Processor’s Save Messages As command (File menu). The messages saved in the file are identical to those displayed in the current Message Processor window.

In the workstation version MAX+PLUS II only, all MAX+PLUS II messages--both from the Compiler and the Timing Analyzer--are saved automatically to <project name>.mtf. If a <project name>.mtf already exists, MAX+PLUS II automatically saves the older file as <project name>.mtf.bak.

The file icon for an MTF with the same filename as the top-level design file in the current hierarchy tree appears in the Hierarchy Display window.

See also:

Saving Messages to a File


Message Processor Help Contents

Introduction

Basic Tools

Commands

Procedures

Golden Rules

Shortcuts

Messages


Message Processor Introduction
Introduction

The MAX+PLUS II Message Processor lists error, information, and warning messages that occur while MAX+PLUS II applications are running. Since the Message Processor interacts with all MAX+PLUS II applications, locating error and warning messages, obtaining on-line help, and correcting errors are a seamless operation. Show me

How Does the Message Processor Work?

The Message Processor interactively reports and locates errors that occur as you run MAX+PLUS II applications and/or background processes. Each set of messages is saved until you overwrite it by repeating a particular background process, regardless of whether you open and close MAX+PLUS II.

You can locate the source(s) of a message by simply double-clicking Button 1 on the message. MAX+PLUS II automatically opens the design file and/or ancillary file that contain the source of the message, regardless of their location in the project's hierarchy treeor the type of application that created them. In conjunction with the Timing Analyzer, the Message Processor also lists the timing delays between pairs of nodes and allows you to locate each portion of the signal paths between them.

From the Message Processor window, you have instant access to on-line help, with explanations of all message and descriptions of recommended corrective actions.

Where to Start

Altera offers a variety of information to help you use MAX+PLUS II and the Message Processor.

On-Line Help

On-Line Help supplies complete reference and how-to information.

Message Processor Help Contents provides access to all on-line Message Processor Help.

Message Processor Golden Rules describes essential guidelines and recommendations for using MAX+PLUS II and the Message Processor.

See also:

How to Use MAX+PLUS II Help


Message Processor Golden Rules
 Golden Rules

The following golden rules will help you use MAX+PLUS II and the Message Processor effectively.

When you start work on a new design file, name it as the current project with Project Name (File Menu) right away so that you can compile it easily. You can always change the project name later.

Use the built-in hierarchy traversal features in MAX+PLUS II to move between design files for the current hierarchy. To open a lower-level file in a hierarchy, open the top-level file and then use the Hierarchy Display window or Hierarchy Down (File menu) to open the lower-level files. If you choose Open or Retrieve (File menu) to open a lower-level file, it is considered to be the top of a different hierarchy tree, and resource, device, and probe assignments that you enter are saved only for that hierarchy, not for the project.

When you create an ancillary file for a project, the icon for the file will appear in the Hierarchy Display if you use the same filename as the project.

Don’t edit any MAX+PLUS II system files, including HIFs, maxplus2.idx,and the maxplus2.ini file.

Use the Save As command (File menu) if you wish to rename a design fileor an ancillary file. Don’t rename design files from outside of MAX+PLUS II system (e.g., from DOS or with the Windows File Manager).

When you have completed a project, use Project Archive (File menu) to ensure that you save a complete copy of all project files that will not be affected by future edits or deletions.


Message Processor--Context-Sensitive Help
Message Processor Context-Sensitive Help

Context-sensitive help is available for all Message Processor commands, dialog boxes, and messages, and the following basic tools:

Buttons & Options

Message Button

Locate Button

Locate in Floorplan Editor Option

Locate All Button

Help on Message Button

Messages

Toolbar

Status Bar

For information on other basic tools, see Message Processor Basic Tools.

See also:

Getting Context-Sensitive Help


Message Processor Shortcuts
Shortcuts

The following list provides shortcuts for Message Processor commands:

Command:	Shortcut:

Context-Sensitive Help	Shift+F1 or

Cascade	Shift+F5

Close	Alt+F4

Compiler

Exit MAX+PLUS II	Alt+F4 or double-click Button 1 on the Application Control Menu box

Floorplan Editor

Hierarchy Display

Hierarchy Project Top	Ctrl+T or

New

Next	Ctrl+F6

Open	Ctrl+O or

Locate button	Double-click Button 1 on a message

Print	Ctrl+P or

Programmer

Project Name	Ctrl+J or

Project Save & Compile	Ctrl+L or

Project Save & Check	Ctrl K or

Project Save & Simulate	Ctrl+Shift+L or

Save Messages As

Simulator

Switch To	Ctrl+Esc

Tile Horizontally	Shift+F4

Timing Analyzer

See also:

Guidelines for Workstation Help Users

Selecting Text


Message Processor Procedures
Procedures

Assignments & Compiler Configuration Settings

Assigning a Clique

Assigning a Device

Assigning a Pin, Location, or Chip

Assigning a Probe

Assigning an Individual Logic Option or Synthesis Style

Assigning Connected Pins

Assigning Individual Timing Requirements

Bank-Annotating Assignments for a Project

Clearing Assignments for a Project

Converting an Obsolete Assignment Format

Copying a Resource Assignment

Defining a Logic Synthesis Style

Deleting an Assignment

Guidelines for Working with Assignments

Ignoring Project Assignments during Compilation

Logic Synthesis Style & Logic Option Rules

Searching the Node Database

Specifying Devices for Automatic Device Selection

Specifying Global Project Classic & MAX Device Options

Specifying Global Project MAX 7000A Device Options

Specifying Global Project FLEX 8000 Device Options

Specifying Global Project FLEX 10K Device Options

Specifying Global Project Logic Synthesis Settings

Specifying Global Project Security Bit & Reserved Resource Settings

Specifying Global Project Timing Requirements

Specifying Individual Device Security & Turbo Bit Options

Specifying Individual Classic & MAX Device Options

Specifying Individual MAX 7000S Device Options

Specifying Individual FLEX 8000 Device Options

Specifying Individual FLEX 10K Device Options

File Management

Creating a New File

Deleting a file

Opening a File

Hierarchy

Navigating the Hierarchy

Updating the Hierarchy

MAX+PLUS II Management

Changing Colors in MAX+PLUS II

Closing a MAX+PLUS II Application

Creating & Using a Local Copy of the maxplus2.ini File

Exiting from MAX+PLUS II

Obtaining a Site License Authorization Code

Registering Your Software

Setting Up Your Authorization Code or Network License File

Setting MAX+PLUS II Preferences

Specifying a User Library

Starting MAX+PLUS II Applications

Switching between MAX+PLUS II Applications

Messages

Getting Help on a Message

Locating the Source of a Message

Printing Messages

Saving Messages to a File

Selecting Messages to View

Project Management

Archiving a Project

Changing the Project Name

Compiling a Project

Creating & Using a Local Copy of the maxplus2.ini File

Text

Selecting Text


Printing Messages (Message Processor)
Printing Messages

You can print the messages displayed in the Message Processor window.

To print messages:

1.	Open the Print dialog box by choosing Print (File menu) or using a shortcut.

2.	Enter the number of copies you want to print in the Copies box.

3.	If you wish to print a header on each page that includes the MAX+PLUS II version number, project name, date, and page number, turn on the Print Page Headers option.

4.	Choose OK.

To change the printer and printer options:

1.	Choose Printer Setup (File menu).The Printer Setup dialog box is displayed.

2.	Select the correct printer.

3.	If you wish, choose Setup to open a dialog box that controls options for your printer, change any desired options, and choose OK to return to the Printer Setup dialog box.

4.	Choose OK in the Printer Setup dialog box.

See also:

Saving Messages to a File


Saving Messages to a File (Message Processor)
Saving Messages to a File

You can save the messages that are displayed in the active Message Processor window to a Message Text File (.mtf).

To save messages to an MTF:

1.	Open the Save Message As dialog box by choosing Save Messages As (File menu) or using a shortcut.

2.	If necessary, select a different drive and/or directory.

3.	Select an existing filename in the Files box or type a filename in the File Name box. The filename may contain up to 32 name characters.  If you select the name of an existing file, it will be overwritten. If you type the name of a directory that does not exist, MAX+PLUS II will offer to create it for you.

4.	If you wish to save the file without a filename extension, type a period (.) after the filename. Otherwise, the extension .mtf is automatically appended to the filename.

5.	Choose OK.

See also:

Message Text File (.mtf)


Selecting Messages to View (Message Processor)
Selecting Messages to View

You can display the most recent set of messages generated by a MAX+PLUS II background process in the Message Processor window.

To select a set of messages to view:

1.	Choose Select Messages (File menu). The Select Messages dialog box is displayed.

2.	Select the name of an application or command in the Display Messages Generated By box.

3.	Choose OK.

If a Message Processor window containing the desired set of messages is already open, you can bring it to the front by choosing it from the Window menu. You can also choose Message Processor from the MAX+PLUS II menu to bring the most recently opened Message Processor window to the front.


---------------BEGINNING OF NON-TRANSLATED TEXT-------------------

These are MSGMSGS.MSG messages

-

--------------END OF NON-TRANSLATED TEXT-------------------


Can’t locate error-- project HIFs missing
Can’t locate node with information from existing HIF -- recompile the project to generate a new HIF

CAUSE:	The HIF for this project is damaged or was created by a previous version of MAX+PLUS II.

ACTION:	Recompile the project to generate a new HIF.

See also:

MAX+PLUS II Messages

Message Format


No messages exist for this project

CAUSE:	You chose the Select Messages button in the Message Processor window but there are no messages for the project.

ACTION:	No action is neccessary.

See also:

MAX+PLUS II Messages

Message Format


Message Processor Commands
Commands

For Help, choose a command name or dialog box name from the following list. Menu names are not included on the list.

About MAX+PLUS II

Advanced Options

AHDL

Archive

Arrange Icons

Authorization Code

Auto Device Selection

Back-Annotate Project

Basic Tools

Cascade

Classic & MAX Global Project Device Options

Classic & MAX Individual Device Options

Clear Project Assignments

Clique

Close ( [image] and [image] menus)

Color Palette

Commands

Compiler

Connected Pins

Convert Obsolete Assignment Format

Define Synthesis Style

Delete File

Device

Devices & Adapters

ES Site License Authorization Request

Exit MAX+PLUS II

FLEX 10K Global Project Device Options

FLEX 10K Individual Device Options

FLEX 8000 Global Project Device Options

FLEX 8000 Individual Device Options

Floorplan Editor

Global Project Device Options

Global Project Logic Synthesis

Global Project Timing Requirements

Glossary

Golden Rules

Graphic Editor

Help Menu

Hierarchy Display

Hierarchy Project Top

How to Use Help

How to Use MAX+PLUS II Help

Ignore Project Assignments

Individual Logic Options

Introduction

Logic Options

Macrofunctions

MAX 7000S Global Project Device Options

MAX 7000S Individual Device Options

MAX+PLUS II Registration

MAX+PLUS II Table of Contents

Maximize

Message Processor Help Basic Tools

Message Processor Help Commands

Message Processor Help Golden Rules

Message Processor Help Introduction

Message Processor Help Procedures

Message Processor Help Shortcuts

Message Processor Help Table of Contents

Message Processor

Messages

Minimize

More Windows

Move

Name

New Features in This Release

New Window

New

Next

Open

Pin/Location/Chip

Preferences

Primitives

Print Setup

Print

Probe

Procedures

Programmer

Project 1, 2, 3, 4...

Project Archive

Project Name

Project Save & Check

Project Save & Compile

Project Save & Simulate

Project Save, Compile & Simulate

Project Set Project to Current File

READ.ME

Rename Chip

Restore

Save & Check

Save & Compile

Save & Simulate

Save Messages As

Save Style As

Save, Compile & Simulate

Search for Help on

Search Node Database

Select Messages

Set Project to Current File

Shortcuts

Show Status Bar

Show Toolbar

Simulator

Size

Switch To

Symbol Editor

Table of Contents

Text Editor

Tile Horizontally

Tile Vertically

Timing Analyzer

Timing Requirements

User Libraries

VHDL

Waveform Editor

Window Menu


Select Messages Command (Message Processor)
Select Messages Command (File Menu)

Selects a set of messages from an application or command that runs as a background process and displays them in a Message Processor window.

Click Button 1 on any item in this dialog box for information on that item:

A Message Processor window shows only the messages generated during the current or most recent run of the application or command. A particular set of messages can be displayed in only one window at a time.

See also:

Saving Messages to a File

Selecting Messages to View


Display Messages Generated By

Displays the existing sets of messages in the MMF for the current project.

The Display Messages Generated By box lists messages in groups based on the MAX+PLUS II application or command that generated them. Select an application or command name to display its most recently generated set of messages in a Message Processor window.

Whenever you open a Message Processor window using the Select Messages command (File Menu), (Restored) appears in the window’s title bar after the application or command name.


 Select Messages dialog box

Click Button 1 on any item in this dialog box for information on that item:


Save Messages As Command (Message Processor)
Save Messages As Command (File Menu)

Shortcut

Saves the messages currently displayed in the Message Processor window in a Message Text File (.mtf).

Click Button 1 on any item in this dialog box for information on that item:

See also:

Saving Messages to a File


 Save Messages As dialog box

Click Button 1 on any item in this dialog box for information on that item:


Print Command (Message Processor)
Print Command (File Menu)

Shortcut

Prints the messages currently displayed in the Message Processor window.

Click Button 1 on any item in this dialog box for information on that item:

MAX+PLUS II prints the file according to the settings for the current printer, which are specified with Print Setup (File menu).

See also:

Printing Messages

Saving Messages to a File


Print dialog box (Message Processor)
 Print dialog box

Click Button 1 on any item in this dialog box for information on that item:


Message Processor Window #1
 Message Processor Window


Message Processor Window #2
 Message Processor Window


MAX+PLUS II Manager Index
MAX+PLUS II Manager Help Contents

Introduction

Basic Tools

Commands

Procedures

Golden Rules

Shortcuts

Messages


MAX+PLUS II Manager--Context-Sensitive Help
MAX+PLUS II Manager Context-Sensitive Help

Context-sensitive help is available for all MAX+PLUS II Manager commands, dialog boxes, and messages, and the following basic tools:

Status Bar

Toolbar

For information on basic tools, see MAX+PLUS II Manager Basic Tools.

See also:

Getting Context-Sensitive Help

MAX+PLUS II Manager Help Contents


MAX+PLUS II Manager Basic Tools
Basic Tools

Input & Output Files

Assignment & Configuration File (.acf)

ACF Format

Probe, Resource & Device Assignments

Clique Assignments

Connected Pin Assignments

Device Assignments

Logic Option Assignments

Pin, Location & Chip Assignments

Probe Assignments

Timing Assignments

MAX+PLUS II Initialization & System Files

maxplus2.idx File

maxplus2.ini File

Status Bar & Toolbar

Status Bar

Toolbar


MAX+PLUS II Manager Commands
Commands

About MAX+PLUS II

Advanced Options

AHDL

Archive

Arrange Icons

Authorization Code

Auto Device Selection

Back-Annotate Project

Basic Tools

Cascade

Classic & MAX Global Project Device Options Dialog Box

Classic & MAX Individual Device Options Dialog Box

Clear Project Assignments

Clique

Close ( [image] and [image] menus)

Color Palette

Commands

Compiler

Connected Pins

Convert Obsolete Assignment Format

Define Synthesis Style

Delete File

Device

Devices & Adapters

ES Site License Authorization Request

Exit MAX+PLUS II

FLEX 10K Global Project Device Options Dialog Box

FLEX 10K Individual Device Options Dialog Box

FLEX 8000 Global Project Device Option Dialog Boxs

FLEX 8000 Individual Device Options

Floorplan Editor

Global Project Device Options

Global Project Logic Synthesis

Global Project Timing Requirements

Global Project Parameters

Glossary

Golden Rules

Graphic Editor

Hierarchy Display

Hierarchy Project Top

How to Use Help

How to Use MAX+PLUS II Help

Ignore Project Assignments

Individual Logic Options

Introduction

Logic Options

Macrofunctions

MAX 7000S Global Project Device Options Dialog Box

MAX 7000S Individual Device Options Dialog Box

MAX+PLUS II Manager Help Basic Tools

MAX+PLUS II Manager Help Commands

MAX+PLUS II Manager Help Golden Rules

MAX+PLUS II Manager Help Introduction

MAX+PLUS II Manager Help Procedures

MAX+PLUS II Manager Help Shortcuts

MAX+PLUS II Manager Help Table of Contents

MAX+PLUS II Registration

MAX+PLUS II Table of Contents

Maximize

Message Processor

Messages

Minimize

More Windows

Move

Name

New Features in This Release

New Window

New

Next

Open

Pin/Location/Chip

Preferences

Primitives

Probe

Procedures

Programmer

Project 1, 2, 3, 4...

Project Archive

Project Name

Project Save & Check

Project Save & Compile

Project Save & Simulate

Project Save, Compile & Simulate

Project Set Project to Current File

READ.ME

Rename Chip

Restore

Save & Check

Save & Compile

Save & Simulate

Save Style As

Save, Compile & Simulate

Search for Help on

Search Node Database

Set Project to Current File

Shortcuts

Show Status Bar

Show Toolbar

Simulator

Size

Switch To

Symbol Editor

Table of Contents

Text Editor

Tile Horizontally

Tile Vertically

Timing Analyzer

Timing Requirements

User Libraries

VHDL

Waveform Editor


MAX+PLUS II Manager Procedures
Procedures

Assignments & Compiler Configuration Settings

Assigning a Clique

Assigning a Device

Assigning a Pin, Location, or Chip

Assigning a Probe

Assigning an Individual Logic Option or Synthesis Style

Assigning Connected Pins

Assigning Individual Timing Requirements

Bank-Annotating Assignments for a Project

Clearing Assignments for a Project

Converting an Obsolete Assignment Format

Copying a Resource Assignment

Defining a Logic Synthesis Style

Deleting an Assignment

Guidelines for Working with Assignments

Ignoring Project Assignments during Compilation

Logic Synthesis Style & Logic Option Rules

Searching the Node Database

Specifying Devices for Automatic Device Selection

Specifying Global Project Classic & MAX Device Options

Specifying Global Project FLEX 8000 Device Options

Specifying Global Project FLEX 10K Device Options

Specifying Global Project Logic Synthesis Settings

Specifying Global Project MAX 7000S Device Options

Specifying Global Project Parameters

Specifying Global Project Security Bit & Reserved Resource Settings

Specifying Global Project Timing Requirements

Specifying Individual Classic & Max Device Options

Specifying Individual Device Security & Turbo Bit Options

Specifying Individual FLEX 8000 Device Options

Specifying Individual FLEX 10K Device Options

Specifying Individual MAX 7000S Device Options

File Management

Creating a New File

Opening a File

Deleting a File

Hierarchy

Navigating the Hierarchy

Updating the Hierarchy

MAX+PLUS II Management

Changing Colors in MAX+PLUS II

Closing a MAX+PLUS II Application

Creating & Using a Local Copy of the maxplus2.ini File

Exiting from MAX+PLUS II

Obtaining a Site License Authorization Code

Registering Your Software

Setting MAX+PLUS II Preferences

Setting Up Your Authorization Code or Network License File

Specifying a User Library

Starting MAX+PLUS II Applications

Switching Between MAX+PLUS II Applications

Messages

Getting Help on a Message

Locating the Source of a Message

Project Management

Archiving a Project

Changing the Project Name

Compiling a Project

Text

Selecting Text


MAX+PLUS II Manager Shortcuts
Shortcuts

The following list provides shortcuts for MAX+PLUS II Manager commands:

Command:	Shortcut:

Context-Sensitive Help

Close	Alt+F4

Compiler

Exit MAX+PLUS II	Alt+F4 or double-click Button 1 on the Application Control Menu box

Floorplan Editor

Hierarchy Display

Hierarchy Project Top	Ctrl+T or

New

Next	Ctrl+F6

Open	Ctrl+O or

Programmer

Project Name	Ctrl+J or

Project Save & Check	Ctrl+K or

Project Save & Compile	Ctrl+L or

Project Save & Simulate	Ctrl+Shift+L or

Simulator

Switch To	Ctrl+Esc

Timing Analyzer

See also:

Guidelines for Workstation Help Users

Selecting Text

Showing the Toolbar


MAX+PLUS II Manager Introduction
Introduction

The MAX+PLUS II Manager provides a framework that controls and integrates MAX+PLUS II applications. It is the first window that opens when you start MAX+PLUS II. From the MAX+PLUS II Manager, you can open all other MAX+PLUS II applications. Show me

How Does the MAX+PLUS II Manager Work?

The MAX+PLUS II Manager provides functions that are common to all MAX+PLUS II applications. When you create a new file or open an existing file, a window for the appropriate application opens automatically. You can enter all types of probe, resource, and device assignments, as well as Compiler processing settings, for the current project. You can also start compiling or simulating the current project or change the project name. In addition, you can change the authorization code to enable new MAX+PLUS II features.

In the MAX+PLUS II Manager, you can turn on the toolbar and status bar, and specify libraries that contain Symbol Files and design files for your own macrofunctions, as well as AHDL Include Files. You can also archive all files of a project, so that subsequent edits to the project do not affect the archived files.

Where to Start

Altera offers a variety of information on the MAX+PLUS II Manager.

On-Line Help

On-line help supplies complete reference and how-to information.

MAX+PLUS II Manager Help Contents provides access to all on-line MAX+PLUS II Manager Help.

MAX+PLUS II Manager Golden Rules summarizes essential rules and guidelines for designing with MAX+PLUS II.

See also:

How to Use MAX+PLUS II Help


MAX+PLUS II Manager Window


MAX+PLUS II Manager Golden Rules
Golden Rules

The following golden rules will help you use MAX+PLUS II and the MAX+PLUS II Manager effectively.

When you start work on a new design file, name it as the current project with Project Name right away so that you can compile it easily. You can always change the project name later.

Use the built-in hierarchy traversal features in MAX+PLUS II to move between design files for the current hierarchy tree. To open a lower-level file in a hierarchy, open the top-level file and then use the Hierarchy Display window or Hierarchy Down to open the lower-level files. If you choose Open or Retrieve to open a lower-level file, it is considered to be the top of a different hierarchy tree, and resource, device, and probe assignments that you enter are saved only for that hierarchy, not for the project.

When you create an ancillary file for a project, the icon for the file will appear in the Hierarchy Display if you use the same filename as the project.

Don’t edit any MAX+PLUS II system files, including HIFs, maxplus2.idx files, or the maxplus2.ini file.

Use the Save As command if you wish to rename a design file or an ancillary file. Don’t rename design files from outside of the MAX+PLUS II system (e.g., from DOS or with the Windows File Manager).

When you have completed a project, use Project Archive to ensure that you save a complete backup copy of all project files that will not be affected by future edits or deletions.


----------------------BEGINNING OF NON-TRANSLATED TEXT--------------------------

The errmess style is redefined as not bold in this file only. In all other aspects the style sheet is as usual.

Anyone who redefines the errmess style to have double underlines in it will be dealt with severely! Don't even THINK of doing it.

----------------------END OF NON-TRANSLATED TEXT--------------------------


MAX+PLUS II Messages
Messages

MAX+PLUS II messages appear both in pop-up message boxes and in the Message Processor window. The Message Processor can also save messages in a Message Text File.

All messages are listed here in alphabetical order, without prefixes. Click Button 1 on the first letter(s) of a message (without the prefix) to jump to the section of the list starting with that letter, then choose a message for information on its possible causes and suggested appropriate actions.

A B C D E F G H I J L M N O P R S T U V W X Y

VHDL messages are not included in this list. See VHDL Messages for a complete list of all VHDL messages.

See also:

Getting Help on a Message

Internal Errors

Locating the Source of a Message

Message Format

Saving Messages to a File

Messages:

A

Absolute time <time> came after <time> in Pattern Section

Adapter <name> is incompatible with this version of device <name>. Contact Altera Applications for up-to-date adapter information.

ACF contains syntax errors. You must either correct the ACF or overwrite it with system defaults before completing this action. To save the existing ACF and obtain a list of errors, choose Cancel, then open and save the file in the Text Editor. To overwrite the existing ACF with system defaults, choose OK.

ACF syntax error on or before <text>

ADF syntax error: [<text>]

Address line <number> (<name>) changed during write at <time> on memory <name> -- information written by Simulator may be incorrect

All old-style assignments have been successfully converted to new format

Append a period (.) and a pinstub name to the node name to specify the location of the probe

Archive failed

Archive has been canceled

Archiving <project name>

Authorization code is not valid

B

Baud rate not supported by <COM port>

BIDIR pin <name> cannot be assigned more than one value

BIDIR pin <name> cannot feed global <text>

BIDIR pin <name> must be driven by TRI buffer, but is driven by primitive <net ID number>

BIDIR pin <name> must have same pin assignments

Binary number B"1" was expanded differently before MAX+PLUS II version 5.0

BitBlaster is not <text> -- check <text>

BitBlaster is not connected to a device

Blank-Check successful: <number> devices blank-checked

Both Preset and Clear inputs are connected to GND in flipflop <net ID number>

Bus name is allowed only on bus line -- <bus name> (ID <net ID number>)

Buses on output pinstubs [<node name>] ID <net ID number> and [<node name>] ID <net ID number> are tied together

C

Calculated frequency may not be accurate -- project uses multiple Clocks from one or more pins

Can't access device driver for Altera Programmer

Can't access the <hardware type> hardware

Can't add <text> information to SNF -- out of space for symbols

Can't add group and state information for <filename>

Can't add group or state name <name> to the linked SNF

Can't add group/state machine <name> to SNF -- too many <text>

Can't add state <name> to SNF -- too many states or don’t care state bits

Can't analyze timing -- no timing SNF exists for the project

Can't archive file <name>: file does not exist

Can't assign a pin to pin <name> [and pin <name>] because one or more pins have the same name

Can’t assign a probe to a bus or primitive array

Can't assign combinatorial logic <node name> to an I/O pin

Can’t assign input register <name> to an I/O cell because the tri-stated node <name> is always enabled

Can't assign node to two pins on the same chip -- specify the name of another chip

Can't assign register <node name> to the periphery because it uses an asynchronous Preset

Can’t assign two registers (<name>, <name>) to the same I/O cell

Can't change an existing node into a group

Can't change the JTAG attributes of device <name>

Can't combine more than <number> files for bit-slice configuration

Can't combine programming files from different device families

Can't compare file

Can't continue hardware tests -- programming adapter is installed on the <name> unit

Can't convert old-style assignments in <filename> to new format

Can't copy file <name> onto itself

Can't create directory <name>

Can't create file <filename>

Can't create fonts -- reinstall Windows fonts

Can't create linked SNF -- no macrofunctions in project represent SNFs

Can't create linked SNF -- top-level design file contains state machine logic (net ID <net ID number>)

Can't create project directory <name>

Can't delete style name <name>

Can't delete text

Can't detect a software guard or a valid authorization code. However, you are authorized to use the MAX+PLUS II PLS-ES feature set until <time>. Press F1 for Help and info on obtaining an authorization code

Can't display OrCAD part <name> as a primitive -- creating it as a macrofunction instead

Can't divide an expression by zero

Can't edit MAX+PLUS II *.<extension> system files

Can’t edit memory -- memory width exceeds 256 bits

Can't enter <name> clique -- already exists

Can't enter <name> connected pin -- already exists

Can't enter <name> device -- already exists

Can't enter <name> logic option -- already exists

Can't enter <name> pin/location/chip -- already exists

Can't enter <name> probe -- already exists

Can't enter <name> timing requirement -- already exists

Can't enter <text> -- name <name> has already been used

Can't enter macrofunction -- it would make the hierarchy tree recursive

Can't feed an inverted input pin to input register <node name>

Can't find a fit for this project, though one may exist

Can't find a partition with clique assignments

Can't find a pin that corresponds to [macrofunction <name>] pinstub/port <name> [in <filename>.snf]

Can't find anything that matches text pattern <text>

Can't find clique <name>

Can't find connected pin <name>

Can’t find data in initial memory content (MIF/HEX) file

Can't find design file <name>

Can't find device <name>

Can't find directory <name>

Can't find file <name> [<text>]

Can't find last edit

Can't find legal LAB for <node name>

Can't find legal pin or logic cell for <node name>

Can't find logic option <name>

Can't find master Reset pin [-- using pin <name>]

Can’t find matching section delimiter for <text>

Can't find node <name> in this floorplan

Can't find node <name> that is used in a breakpoint condition

Can't find node destination

Can't find node or symbol <text>

Can't find node source

Can't find OrCAD part: <name>

Can't find pin/location/chip <name>

Can't find probe <name>

Can't find programming card <programming card> at I/O address <I/O address>

Can't find programming file <name> for the current project

Can't find programming hardware -- use Hardware Setup command to set up hardware

Can't find programming unit <name>

Can't find symbol <name> -- symbol is not on a library path

Can't find text <text> in matrix

Can't find text: <text>

Can't find timing requirement <name>

Can't generate SCF from Vector File <filename>

Can't implement illegal resource number/name entered in the Pin, Logic Cell, LAB, Row, or Column drop-down list box

Can't import state machine <node name> -- it is not an output

Can't include a machine node in a group

Can't include macrofunction <name> in linked SNF -- it has no inputs

Can't list more than <number> Clock signals -- others are ignored

Can't list nodes -- no SNF exists for the project

Can't load JEDEC File <filename> -- device <device name> is not supported

Can't locate error -- project HIFs are missing

Can't make equation

Can't merge logic fed by CARRY primitive <net ID> into a single logic cell <node name> -- LCELL inserted automatically

Can't minimize <node name> completely

Can’t open encrypted file <name>

Can't open file <filename>

Can't open the <name> dialog box until <text>

Can't override existing external pin connections -- macrofunction <name> contains input pin <name> that is already externally connected to pin <name>

Can't overwrite file <filename>

Can't partition project into rows <text>

Can't partition row <letter> into LABs

Can't paste a machine node from a WDF into an SCF

Can't paste

Can’t paste -- Clipboard data <text> does not match the current <text>

Can't perform this action -- it edits the ACF for the project, which is already open in a Text Editor window and contains unsaved changes. You must save the changes or close the file without saving before you can perform this action.

Can't perform this action -- the database of project node names is being updated by the Compiler and is locked

Can't print: <text>

Can't program or configure device <name> in a multi-device JTAG chain -- delete programming file from device information

Can't provide <timing assignment> of <time> from <name> to <name>. Current <timing assignment> is <time>.

Can't provide fmax of <time> on <text> <name>. Current fmax is <time>.

Can't provide tsu of <time> from <name> to register <name> using Clock pin <name>. Current <timing assignment> is <time>.

Can't put both <pin name> and <pin name> on <text> <number>

Can't put pin <name> on dedicated global Clock input pin <number>

Can't read file <filename>

Can’t read line <number> of Report File Equations Section -- recompile the project to create a new Report File

Can't recognize symbol <name> (ID <net ID number>)

Can't rename chip(s) in ACF for this hierarchy tree to agree with the new filename

Can't replace node that is part of a group with a machine node

Can’t run <text>: all network licenses are in use

Can’t save & check <filename> -- its extension conflicts with the top-level design file of the current project. Use the Hierarchy Display’s Change File Type command to change the extension of the top-level design file

Can't save edits to a file that was not created by the Graphic Editor

Can't save edits to a Symbol File for a primitive

Can't save file <filename> [<text>]

Can't save file to <name> -- filename is reserved for Clipboard operations

Can't save hierarchy for <name>

Can't save JEDEC File for device: <device name>

Can't search -- project has not been compiled, so no database of node names is available

Can't select file <filename> -- it is not part of the current project. MAX+PLUS II is running a background process and cannot change the project name while this process is running.

Can't simulate -- input node names in <filename> are completely different from those in <filename>

Can't simulate -- no SCF is loaded for the project

Can't simulate -- no SNF exists for the project

Can't simulate -- optimized timing SNF <name> was generated with 16-bit Windows. Recompile the project before simulating with 32-bit Windows

Can't simulate a project with connected output and/or bidirectional pins

Can't simulate with a device -- project requires multiple devices

Can't test -- node names in file <filename> do not match pin names for the current project

Can't test -- project contains externally connected output or bidirectional pins

Can't test -- project requires multiple devices

Can't test <hardware type> hardware

Can't tie output to <text>

Can't tie primitive outputs together (node: <name>)

Can't update Report File <filename> with information from "smart" recompile --restart the compilation to re-create the Report File

Can't update ACF for this project before archiving -- archived file may be out of date

Can't update symbol <name> -- symbol is not on a library path

Can't use both <equation name> and <equation name> in flipflop <node name>

Can't use Case Statement in Outputs Subsection: <state machine name>

Can't use device <name> to configure <text> family devices

Can't use port <name> with port <name>

Can't use state name in expression: <state machine name>

Can't use state output names in Inputs Section: <state machine name>

Can't use state output names in Outputs Section: <state machine name>

Can't use state variable names in Outputs Subsection: <state machine name>

Can’t view equations while Report File is being written

Can’t view floorplan for last compilation -- no Fit File is available for this device

CARRY primitive <net ID> and CASCADE primitive <net ID> cannot both feed logic cell <node name> -- LCELL inserted automatically

CARRY primitive <net ID> cannot fan out to more than one non-CARRY primitive -- LCELL inserted automatically

CARRY primitive <net ID> cannot fan out to more than one other CARRY primitive -- LCELL inserted automatically

CARRY primitive <net ID> ignored

CARRY primitive <net ID> must feed an LCELL primitive -- LCELL inserted automatically

CASCADE primitive <name> cannot feed primitive <name> because it already feeds primitive <name>

CASCADE primitive <name> cannot feed primitive <name>

Cell width must be between <number> and <number>

CellRef must include libraryRef when used in design definition

Changes made with this dialog box will be lost. OK to discard changes and close this dialog box?

Checkout of <application name> failed

Chip <name> already exists in the ACF

Chip <name> already declared

Chip <name> did not fit into AUTO device <device>

Chip <name> has pin/location/chip assignments. OK to delete chip and all of its assignments?

Chip <name> in device <name> has less than <number>% of <text> available for future logic changes -- if your project is likely to change, Altera recommends using a larger device

Chip <name> is not used

Chip <name> successfully fit into AUTO device <device>

Chip assignment for <node name> conflicts with chip assignment for node <node name>

Chip assignment for <node name> conflicts with clique assignments for clique <name>

Clear and Preset for <node name> reduce to the same signal

Clique <name> is too large -- it has <number> members

Clock pin cannot be used as an I/O pin [<text>]

Clock signal <net ID number> is driven by state machine <name>

COM port <COM port> is busy

COM port <COM port> is not available

Command <name> is not supported

Command File <name> calls itself -- file processing halted

Compiling empty design file or file has no output pins

Compiling project with user-specified timing assignments

Complex combinatorial logic drives <text> node (ID <net ID number>) -- <text> should be driven by a pin or a single logic primitive

Configuration complete: [<text>]

Configuration failure: SRAM load unsuccessful

Conflicting Clock -- globally clocked register <name> conflicts with Clock input <name> that feeds the LAB

Conflicting Slow Slew Rate settings for node <name> -- using SLOW_SLEW_RATE=ON

Conflicting Turbo Bit settings for node <name> -- using TURBO=ON

Conflicting vector exists for <I/O type> node <name> at <time> -- ignoring earlier vector

Connect input pin <name> and output pin <name> to support inversion of active-low Output Enable signal <name>

Connect input pin <name> and output pin <name> to support logic on the Output Enable signal

Connected pin <name> (ID <net ID number>) can’t drive logic

Constant <name> may not be assigned a value

Constant too large

Constant truncated

Copied file <filename>

Creating chip <chip name> from <family name> device family

Currently selected version of device <name> cannot be programmed with the Security Bit turned on. Please turn off the Security Bit or use a later device version.

D

Defaults Statement must be first in Logic Section

Delay chain starting at primitive <net ID number> feeds primitive <net ID number>

Delay path [for <text>] from <node name> to <node name>: <delay time> [Clock period <time>]

Delay path from <node name> to <node name>: <delay time> [Clock period <time>]

Design Doctor has given the project a clean bill of health based on the <name> Rules set

Design Doctor has not examined the project

Design Doctor is currently examining the project

Design Doctor issued <number> warnings with <name> Rules [during project compilation]

Design name <name> must be the same as the filename <filename>

Device <name> already has JTAG attribute information. OK to overwrite the existing information with new information?

Device <name> assigned <number> <text>, but has room for <number>

Device <name> assigned too many parallel expanders

Device <name> does not have JTAG attribute information

Device <name> does not have JTAG attribute information. [OK to add new information for this device?]

Device <name> is not compatible with programming file <name>

Device <text> canceled

Device assignment(s) in Chip to Device dialog box have a different device family. Update these assignments before compiling the project

Device does not support array <text>

Device family was changed from <name> to <name> to agree with Device command setting

Device in adapter is incompatible with current programming file -- load SOF to test a FLEX 8000 device

Device is backwards in socket

Device is erased

Device is not erased

Device is not erased. Do you wish to program the Security Bit?

Device is not in socket

Device pin continuity check failed at pin <number> [(node <name>)]

Device requires opposite polarity of global signal for this port -- invert INPUT pin <name> that feeds the secondary input of primitive <name>

Device requires too many (<number>/<number>) global <text> signals

Device requires too many (<number>/<number>)<text> signals

Device uses inverted global signal for this port -- a NOT gate is required between INPUT pin <name> and the secondary input of primitive <name>

Device uses too many (<number>/<number>) I/O cell <text> signals

Device version is not enabled -- install a newer version of MAX+PLUS II software or enter a new device password

Devices from more than one family specified

Directory <name> already exists [<text>]

Directory <name> does not exist. OK to create it?

Don't care value <text> detected in comparison

Duplicate input or output pin name: <name>

Duplicate name <name> for two or more primitives

Duplicate node [or pin] name: <node/pin name> [(ID <net ID number> and <net ID number>)]

Duplicate port name: <name>

Duplicate state name: <name>

Duplicate state variable assignment: (<text>)

Duplicate state variable name: <name>

E

ECHO command output is too long (max. = 255 characters)

EDIF cell <name> already has LMF mapping so contents construct has been ignored

EDIF cell <name> differs from LMF declaration

EDIF cell <name> has LMF mapping

EDIF cell <name> has multiple mappings -- only the first mapping is accepted (others are ignored)

EDIF GND signal name not specified -- defaulting to <text>

EDIF GND VCC signal name not specified -- defaulting to <text>

EDIF Input File is too large to be processed

EDIF port <name> has LMF mapping

EDIF VCC signal name not specified -- defaulting to <text>

Empty truth table: no statements

End of comment character (%) is missing -- rest of file is treated as a comment

Enter or choose a text size between 6 and 96

Enter or choose a text size of 7, 10, or 12 -- Altera font is not available in other sizes

Equation for <text> input of <register name> can only be VCC or GND [or Q or NQ]

Equation too long

Error getting license file data

Examined device contains programming data that cannot be loaded

Existing files in archive directory <name> may be overwritten. OK to overwrite existing files?

Existing pin assignments may not be valid for the new device

Expander flipflop detected at primitive <net ID number>

Expander latch detected at primitive <net ID number>

Expected <text> but found <text>

Expression must be a machine variable, machine input, or machine output

Expression passed to LOG2 is negative or zero

Expressions to left of period (.) may be macrofunction or primitive variables only

External pin connections ignored for <project name>

Externally connect global Clock signal <name> to pins <text>

Externally connect pins to emulate internal tri-state bus

F

File <name> already exists. OK to overwrite?

File <name> contains a logic configuration that is not supported for this version of device <device name>. Please edit the project or use a later device version.

File <name> has already been selected. OK to add it again?

File <name> on disk is newer than file being edited. Close all windows of older file without saving before opening the newer file from disk.

File <name> on disk is newer than file being edited. OK to open newer file without saving current file?

File <name> was not generated by the LCA2XNF utility [or has no outputs or inputs]

File <name> will be overwritten by the new information. OK to overwrite the file?

File contains multiple <text>

File is read-only but <text>

File with old-style assignments contains a syntax error

Finished listing [longest] delay path[s]

Finished reading data from device

Finished searching the selection. <number> replacements were made. Do you want to search the remainder of the file?

Fit File syntax error: [<text>]

Fitting attempt <number> ended at <time> with <number> unplaced pins or logic cells

Flattened project hierarchy reveals a node loop near node <name>

Flipflop <net ID number> receives data that is synchronized by another Clock at flipflop <net ID number>

Flipflop <net ID number> stuck at <text>

Flipflop(s) and logic drive <text> node (ID <net ID number>)

Font <name> is not supported

Found a total of <number> timing assignments that were not implemented

Found Clock <text> time violation at <time> on node <name>

Found glitch at <time> on node <name>

Found hold time violation at <time> on register <node name>

Found hold time violation at <time> on <text>

Found logic contention at <time> on node <name>

Found NETLIST command -- terminating Command File

Found nil-period oscillation at <time>. Continue simulating with these inputs, or cancel simulation?

Found node <name> in chip <name> -- select this chip in Floorplan Editor and repeat the find/locate action

Found oscillation at <time> on node[s] <name(s)>

Found possible source of logic contention: <text> pin <name>, which is always enabled, is tied to output/bidirectional pin <name>

Found ripple clock -- warning messages and Report File information on tco, tsu, and fmax may be incorrect

Found setup and/or hold time violation at <time> in input data for memory <name>

Found setup time violation at <time> on register <node name>

Found setup time violation at <time> on <text>

Found <text> violation at <time> on memory <name>

G

GLOBAL (or SCLK) buffer <net ID number> must be driven by an INPUT pin or a GLOBAL (or SCLK) buffer

GLOBAL primitive on node <name> feeds logic -- non-global signal usage may result

Global <text> input cannot be used for another global input

Global Clock <name> can be assigned only to dedicated Clock pin <number>

Global Clock conflict: <node name> versus <node name>

Global Output Enable input cannot be used for another global input

Global signal <name> is assigned to local pin <number> in LAB <name>

Group <name> already exists

Group <name> contains input nodes -- COMB or REGISTER node type is not possible

Group <name> has already been created [ignoring second definition]

Group <name> is missing brackets [ ]

Group <name> was created but never used

Group <name> was redeclared with a different range

Group LSB will be <name>, overrides BIT0 = MSB in Options Statement

Group MSB will be <name>, overrides default order of bits or BIT0 = LSB in Options Statement

Group range <name><range> differs from declaration <name><range>

Group range expression cannot be negative

Group range of <name> must be specified when using comma placeholders to left of period (.)

Group range too large: <name><range>

Groups may not be assigned to nodes

Groups must be of equal size, but one has <number> members and the other has <number>

Guideline spacing value must be an integer between 1 and 999

H

Hex File contains invalid checksum <number> -- sum of bytes must be 0

Hex File record error: <text>

High fan-in [<text>] prevents node <name> from fitting into one logic cell

Hit breakpoint <name> at <time>

I

I/O error -- <text>

I/O pin <name> has no source or destination

I/O pin cannot be used as <signal name> input

IF keyword that is paired with substituted text <text> of previous message is at line <number>

Ignored ACF for this project because it contains syntax errors. To obtain a list of errors, open and save this ACF in the Text Editor. You should correct errors in the ACF before continuing work on the project.

Ignored all <assignment type> assignments by request of the user

Ignored all options except BIT0 in Options Statement -- other options are not supported

Ignored assignment on <text> node <name> to <pin or LC number> -- assignment on <text> node <name> to <pin or LC number> has precedence

Ignored assignment of node <name> to <row or LAB> -- <row or LAB name> is full

Ignored assignment of node <name> to column -- buried nodes cannot have column assignments in the current version of MAX+PLUS II

Ignored assignment on pin <name> to clique <name>

Ignored buried assignment for <node name>

Ignored CARRY [or CASCADE] primitives (total = <number>) as requested in logic option or logic synthesis style setting

Ignored conflicting assignment [for node <name>] to variable <variable> with value <value> -- using last value found in file

Ignored definition of <construct name> <construct>

Ignored Design Section -- it is not supported

Ignored duplicate assignment [for node <name>] to variable <variable> with value <value>

Ignored I/O Cell Register logic option for register <name>

Ignored I/O Cell Register logic option setting for node <name>

Ignored illegal .ini file variable: <variable> = <value>

Ignored illegal alias -- <alias>

Ignored illegal assignment for node <name>

Ignored illegal command: <command>

Ignored illegal name <name> in instance rename construct -- using identifier <name>

Ignored illegal name <name> in net rename construct -- using identifier <name>

Ignored illegal port <name>

Ignored illegal property <name>

Ignored illegal timing assignment <text>

Ignored initial memory content (MIF/HEX) file data -- address location is greater than the number of words

Ignored input node <name> -- it is an alias for input node <name>

Ignored macrofunction symbol <symbol> (ID <net ID number>) -- it has no output

Ignored missing or illegal EDIF <text> [defaulting to <text>]

Ignored pin assignment for node <name>

Ignored power-on preset for flipflop <name>

Ignored primitive symbol <symbol> (ID <net ID number>) -- it has no output

Ignored redefinition of <construct name> [<construct>] [property]

Ignored redefinition of resource assignment (<resource> assignment) for node <name>

Ignored redefinition of Security [or Turbo] Bit setting for device [or node] <name>

Ignored redundant portRef

Ignored state <name> -- it duplicates value of <text>

Ignored symbol <name>

Ignored TDF <text> -- it contains no design information

Ignored timing assignment for <timing assignment> on <text> <name>

Ignored timing assignment on node <name> -- it does not exist in the current SNF

Ignored timing assignments -- these assignments are available only for the FLEX 8000 device family

Ignored unnecessary INPUT pin <name>

Illegal assignment -- <name> on pin [or logic cell] <number>

Illegal assignment of global cell <name> and input <name> on logic cell <name>

Illegal assignment on non-dual I/O feedback logic cell -- <name> and <name> on logic cell <number>

Illegal assignment to <name> on node <name>

Illegal based number format: <text>

Illegal bus connection to pinstub <name> (ID <net ID number>)--bus should be named

Illegal bus range in <bus name> (ID <net ID number>)

Illegal character in name [<name>]

Illegal character in parameter declaration: <parameter name> = <parameter value>

Illegal character in <section name>

Illegal combinatorial feedback for <node name>

Illegal connection between port <name> and pin <name>

Illegal count <text> (min. = -32000, max. = 32000)

Illegal device name <text>

Illegal digit <character> in numeric constant: <number>

Illegal don’t-care value at <time> on <text> of memory segment <name>

Illegal don't care value <text> in add operation

Illegal extension (.<extension>) for the current editor

Illegal extension [<extension>] -- use only <extension>

Illegal file name or path: <text>

Illegal file path or path too long: <pathname>

Illegal filename <text> in Include Statement

Illegal filename: <name>

Illegal global <text> specification (<text>)

Illegal GND signal name <name> -- defaulting to <signal name>

Illegal group name: <text>

Illegal group value: <value>

Illegal horizontal page scale (min. = <number>, max. = <number>)

Illegal line or column number

Illegal logic cell number <number> for node <name>

Illegal logic cell or [or pin] syntax <text> [for node <name>]

Illegal machine output pin <name>

Illegal macrofunction name <macrofunction name>

Illegal node name character in <node name>

Illegal node name: <text>

Illegal node or pin name <name> (ID <net ID number>)[<text>]

Illegal node value: <value>

Illegal non-hexadecimal character(s) in port inversion pattern: <character(s)>

Illegal numerical index <number> in port <name> -- min = 0, max = <number>

Illegal option <text> [for node <name>]

Illegal or missing resource assignment <name> for node <name>

Illegal Outputs Subsection in <state machine name>

Illegal parameterized module type <name>

Illegal path time value <text>

Illegal pin (ID<net ID number>) default value -- <text>

Illegal pin assignment -- node <name> is on pin <number>, which is <text>

Illegal pin assignment -- pin <number> reserved for automatic global Clock signal <name>

Illegal pin assignment -- pin <number> reserved for global Clock signal <name>

Illegal pin assignment: (<assignment>, <pin name>)

Illegal pin assignments for logic cell <text> and pin <text>

Illegal pin number <number> for node <name>

Illegal port direction -- mapping is ignored

Illegal port direction <direction> -- defaulting to INPUT

Illegal port name format in <name>

Illegal product term on the <text> input equation of <register name>

Illegal repeat value (min. = 1, max. = 10000)

Illegal section name <section name>

Illegal setting in maxplus2.ini file: <option>=<setting> -- setting must be ON or OFF

Illegal start and/or end times. Start time = <number>, end time = <number>

Illegal state machine <text> name: (<code>, <node name>)

Illegal state machine name

Illegal state name: <text>

Illegal tab stop value (min. = 1; max. = 16)

Illegal text <text> after section keyword <keyword>

Illegal time and unit: <number> and <unit>

Illegal time value: glitch/oscillation = <time>

Illegal timing assignment [name or] value [<text>]

Illegal Transition Statement in <state machine name>

Illegal use of state machine variable <name>

Illegal value string <text> for radix <radix type>

Illegal value <value> for property <name> [-- max/min = <value>]

Illegal value <value> for <variable> variable

Illegal variable <name> for <section name> Section

Illegal VCC signal name <name> -- defaulting to <signal name>

In-system programming is not supported for this device version. [Continue anyway?]

Include File contains information other than Constant and Function Prototype Statements

Include File generation canceled: <number> errors; <number> warnings

Include File generation was successful: <number> errors; <number> warnings

Include File generation was unsuccessful: <number> errors; <number> warnings

Include Files may not be nested

Incomplete assignment information -- you must specify a <text>

Incomplete pattern found in Pattern Section

Incorrect adapter or hardware error

Incorrect address range <number> in initial memory content (MIF/HEX) file

Incorrect hardware type -- doesn’t match installed hardware

Information on instance-specific ports and parameters will be lost if this file is saved as an OrCAD Schematic file. OK to save the file anyway?

Input or bidirectional pin <name> has a <timing assignment> assignment but does not feed any <text>

Input pin <name> asynchronously drives multiple flipflops that are synchronized to Clock <net ID number> -- synchronize the input to Clock <net ID number>

Input pin <name> has two statements in Network Section

Input pin <name> may not be assigned a value

Input pin <name> missing primitive in Network Section

Input pinstub/port <name> is not connected and has no default value

Input port <instance name>.<port name> may not be used as a value

Input register <node name> and input pin <name> cannot both fan out

Input removed by mapping

Inputs Section contains node/group <name> but no pattern exists for it

Insertion point is not defined. OK to enter in center of window?

Installed hardware does not support device type <name>

Installed hardware does not support Use Device option

Insufficient memory or I/O error <text>

Internal error: <text>

Invalid absolute time <time> -- needs '>' character

Invalid address for <hardware type> hardware

Invalid JTAG user code -- value must be 1-byte hex number between 0 and 7F

Inverting delay chain detected starting at primitive <net ID number> feeds primitive <net ID number>

J

JEDEC File <filename> has incorrect transmission checksum (file value = <value>, calculated value = <value>). OK to ignore error?

JEDEC Files cannot be created for <device name> devices

JTAG boundary-scan testing not supported in <device name>

JTAG chain information confirmed by hardware check

JTAG chain information specified in this dialog box does not match the information detected in hardware -- <text>

JTAG ID code expected for device <number> <text> does not match ID code detected in hardware -- <text>

L

LATCH <net ID number> is permanently disabled

LATCH <net ID number> is permanently enabled

Left side of equation may not contain <text>

Line <number> truncated

Line is too long -- has more than 2000 characters

Line is too long -- has over <number> characters

Logic Array Block <LAB name> cannot be reached by pin

Logic Array Block <LAB name> cannot reach I/O cell signal

Logic Array Block <LAB name> cannot reach pin

Logic Array Block <LAB name> receives illegal logic cell feedback from logic cell <name>

Logic Array Block <LAB name> requires too many [(<number>/<number>)] <resource> [as a result of user assignments]

Logic cell <name> can’t feed <destination> [as a result of user assignments]

Logic cell <name> in device <name> requires too many (<number>/<number>) shareable expanders

Logic cell <name> must be global

Logic cell <name> requires too many (<number>/<number>) [<text>]

Logic cell <name> uses illegal <text> architecture

Logic contains an internal <text>: connect external <text> to pin <name>

Logic option assignments are not allowed in Pin Connection Statements

Logic that drives Clear signal <net ID number> should enable master Reset <pin name>, not pin <name>

Logic that drives primitive <net ID number> contains a static <1 or 0> hazard when <text> and primitive <net ID number> changes -- hazard found <text> logic synthesis

Logic that drives primitive <net ID number> is too complex to analyze for static hazards

Logic too complex for <node name> -- <text>

[Conditions: <text>]

M

Machine node <name> may only be assigned to a machine

Macrofunction instance <text> requires an output port

Output ports: <text>

MAX+PLUS II cell <name> differs from previous declaration -- only the first mapping is accepted (others are ignored)

MAX+PLUS II is currently <text>. OK to stop the <application name>?

MAX+PLUS II primitive port <name> does not exist -- mapping is ignored

MAX+PLUS II symbol <name> (ID <net ID number>) contains pinstubs(s) that cannot be placed on OrCAD grid units--come connectivity will be lost

MAX+PLUS II system software problem: <text>

MAX+PLUS II system software problem: can’t read file <name>

MAX+PLUS II system software problem: <name> is missing, so syntax coloring and section delimiter matching in the Text Editor will be disabled

Member node names and/or state names of one or more SCF groups that represent state machines (<group name(s)>) have changed -- updating SCF

Memory <text> differs from MIF <text> -- ignoring MIF value

Merging cliques <name> and <name>

MIF syntax error: <text>

Mismatched number of ports in LMF mapping and EDIF cell -- mapping is ignored

Mismatched parentheses in <state machine name>

Mismatched pin assignments for bidirectional pin: <name>

Mismatched table -- heading has more/less items than table row(s)

Missing a resource assignment for node <name>

Missing destination state in <state machine name>

Missing expression in <state machine name>

Missing identifier after section keyword <keyword>

Missing node name for variable <variable>

Missing node name in <state machine name>

Missing operator in <state machine name>

Missing or illegal <construct>Ref <name> <construct> definition

Missing or illegal Clock Subsection: (<code>, <text>)

Missing or illegal States Subsection

Missing port direction -- defaulting to INPUT

Missing <section name>

Missing state variable assignment

Missing state variable name

Move or copy canceled -- assignment must be attached to a symbol

Move or paste canceled -- it would create illegal assignment(s)

Multi-device JTAG chain mode, which disables the functions of this dialog box, is on. Do you want to switch to the single device mode?

Multi-device JTAG chain mode, which is needed to use the information entered in this dialog box, is off. Do you want to switch to the multi-device JTAG chain mode?

Multi-level logic drives <text> node (ID <net ID number>)

Multiple assignments to machine node <name>

Multiple CARRY primitives feed <net ID> -- LCELL inserted automatically after CARRY primitive <net ID>

Multiple devices are in the adapter

Multiple flipflops drive <text> node (ID <net ID number>)

Multiple OrCAD part mappings: both OrCAD parts <name> and <name> mapped to MAX+PLUS II symbol <name>, but the Graphic Editor can display only one version of this symbol

N

Name is not a macrofunction name

Nesting too deep

Net has <text>

Network Section line too long

Network too complex in <filename>

New group must have a radix

New interval must include part of original interval

New pin and/or logic cell assignments differ from those in the design file(s)

No Clock transition on flipflop <net ID number>

No dual I/O feedback available in logic cells in this device

No exit from state: (<state name>) in <state machine name>

No fit found, generating Report File

No fit possible because there are no dual I/O feedback logic cells in selected devices

No fit possible because too many shareable expanders feed one logic cell

No fit possible for <name> family because there is an array Clock and Output Enable equation on the same logic cell

No fit possible for <name> family because there is an illegal equation on <text>

No fit possible with the current device

No Function Prototype for <macrofunction>

No Inputs Section exists for this pattern

No messages exist for this project

No new information has been entered

No Outputs or Buried Section exists for this pattern

No partition possible because logic cell <name> requires too many (<number>/<number>) inputs from PIA

No register-to-register paths exist for this project -- Clock period represents the maximum toggle frequency of an individual register

No SNF exists for the project -- can’t create default SCF <filename>

No source nodes feed Clock inputs of registers

No superset bus at connection -- <bus name>

No valid assignment remains for selected node(s). OK to delete assignment(s) for current selected node(s)?

No valid <node type> nodes are tagged for the current timing analysis mode

Node <name> already exists

Node <name> assigned to <text> and <text>

Node <name> assigned to a VCC or GND pin

Node <name> assigned to more than one device

Node <name> assigned to multiple output pins

Node <name> assigned to pin <name> will not be tri-stated during device configuration

Node <name> assigned to row <letter>, but feeds pin <name> assigned to row <letter>

Node <name> assigned to row <letter>, but is fed by pin <name> assigned to row <letter>

Node <name> can’t use the global I/O feedback because Output Enable is not VCC

Node <name> carries into <node name>, which is assigned to a non-adjacent location

Node <name> cascades into <node name>, which is assigned to a non-adjacent location

Node <name> converted to <node name> [(same name as input pin)]

Node <name> has an input assignment to chip <name> but is not used as an input on this chip

Node <name> has assignments but doesn't exist or is a primitive array

Node <name> has both combinatorial output and combinatorial feedback, which are not supported on this device

Node <name> has both register output and I/O feedback, which are not supported on this device

Node <name> has conflicting assignments for Turbo Bit and Slow Slew Rate options -- ignoring Turbo Bit assignment

Node <name> has global logic cell feedback -- EP1810 devices support only local logic cell feedbacks

Node <name> has no Clock input

Node <name> has not been created [as an output or buried node]

Node <name> has same set of inputs but different values at <time> and <time>

Node <name> in SIF does not exist in the current SNF

Node <name> is assigned to row <letter> as a result of input/output pin assignments, but is part of a Carry or Cascade chain with logic cells that must be in row <letter>

Node <name> is fed by both pin <name> in row <letter> and pin <name> in row <letter>

Node <name> is fed by pin <name> in row <letter>, but also feeds pin <name> in row <letter>

Node <name> is in a loop of CARRY or CASCADE primitives

Node <name> is not a pin name for the current project -- node is ignored

Node <name> is not clocked by the Clock input <node name> at <time>

Node <name> is not preset by the Preset input <node name> at <time>

Node <name> is not reset by the Reset input <node name> at <time>

Node <name> missing source

Node name should not be specified for variable <variable>

Node <name> that feeds output pin <name> assigned to pin <name> also feeds an I/O cell signal. No logic cell can reach both locations simultaneously

Node <name> [(ID <net ID number>)] missing source

Node characteristics in current file will be overwritten with information in Clipboard. OK to paste?

Node for pin <name> (ID <net ID number>) must have the same name as the pin

Node has more than one name -- <node name>

Node name <name> has too many characters

Node or bus lines overlap if drawn with orthogonal lines. OK to replace orthogonal lines with diagonal lines?

Node or group must have a name

Nodes may not be used as <text>

Nodes <name> and <name> are assigned to the same location -- can't implement register packing because both feed I/O cells

Nodes <name> and <name> are assigned to the same location -- can’t implement register packing because it would require too many (<number>/<number>) signals to feed the same LAB

Nodes <name> and <name> are assigned to the same location -- can't implement register packing because node <name> must be in the same LAB, but is currently assigned to <text>

Nodes <name> and <name> are assigned to the same location -- can’t implement register packing because nodes are not compatible

Nodes <name> and <name> are assigned to the same location -- can't implement register packing because they require too many (<number>/<number>) product terms

Nodes <name> and <name> are assigned to the same location -- can't implement register packing because it would require too many (<number>/<number>) nodes to be in the same Logic Array Block

Non-existent node <name> specified as secondary input of node <name>

Non-input node <name> assigned to dedicated input

Not all MAX+PLUS II primitive ports are mapped -- mapping is ignored

Number must be an integer [<text>]

Number must be an integer in Number of Paths per Clock to List box: <number>

Number of bits in group on left side of equation must be evenly divisible by the number of bits in the group on the right, but one has <number> and the other has <number>

Number of copies must be an integer between <number> and <number>

Number of nodes or waveforms to be pasted is different from the number in the selected area. OK to paste?

Numbers may not be assigned to nodes

O

OK to change project device family to <name>?

OK to change project to <project name>?

OK to convert old-style assignments in <filename> into new format and change old assignments into comments? Choose No to prevent conversion (but assignments will be ignored during compilation).

OK to create a default channel with no nodes or groups?

OK to delete assignment(s) for current selected node(s)

OK to delete style <name>?

OK to overwrite old version of file format?

One or more files in archive directory have the same name as the project. OK to overwrite these files?

Only EDIF level 0 is allowed -- ignored <text> definition

Only EDIF Version 2 0 0 or 2 9 0 is allowed -- ignored <text> definition

Only GENERIC cellType is allowed -- ignored <cell name> cell definition

Only INPUT and BIDIR ports may have default values

Only NETLIST ViewType is allowed -- ignored <view name> view definition

Only one probe is allowed per pinstub--use the Change button to change the probe name

Options Statements are not allowed in Pin Connection Statements

Out of MAX+PLUS II system resources. Terminating...

Out of memory <text>

Output Enable input to <primitive name> is VCC -- converted primitive to <primitive name>

Output Enable source <node name> cannot feed both inverted or non-inverted signals to TRI buffers

Output logic level <logic level> does not match SCF logic level <logic level> for node <name> at <time>

Output or bidirectional pin <name> has a <timing assignment> assignment but is not driven by any <text>

Output pin <name> has two statements in Network Section

Output pin <name> missing primitive in Network Section

Output pinstub <node name> (ID <net ID number>) and <node name> (ID <net ID number>) are tied together

Output port <instance name>.<port name> may not be assigned a value

Output register <node name> and TRI buffer <name> cannot both fan out

Output register <node name> cannot feed output pin <name> through an inverter

Output tied to VCC/GND for <signal name> -- mapping is ignored

Output(s) change at <time>, but no input transitions cause the change

Outputs of primitive <net ID number> are active high and active low -- all will power up at GND

P

Parallel Expanders conflict -- node <name> on <pin or LC number> cannot borrow parallel expanders

Parallel Expanders conflict -- node <name> on <pin or LC number> conflicts with node <name> on <pin or LC number>

Parameterized module of type <name> is not supported in MAX+PLUS II

Parameterized module requires <name> property to define port width

Parameterized module requires one or more of these ports: <names>

Parameterized module with value <value> for property <name> is not supported in MAX+PLUS II

Parser error: <text>

Partitioner device limit exceeded

Partitioning support is not yet available for the <device family name> family in the current version of MAX+PLUS II

Partitioning will result in utilization less than <number>%

Password is not valid: <password>

Pasting will cause memory data to be truncated. OK to paste?

Pasting will edit only part of the group. OK to paste?

Pathname <name> does not exist [or contains an illegal character]

Pattern Section exists, but Inputs, Outputs, and Buried Sections are missing

Percentage specified for the Logic Cells per Row option in the Compiler’s Fitter Settings dialog box is too low (<percentage>) -- it must be <text>

Periods (.) in node names have been converted to underscores (_)

Pin and logic cell assignments are not allowed in <text>

Pin assignment ignored for node <name>

Pin name <name> has too many characters

Pin name truncated to <name>

Pin or logic cell <text> can’t drive an Output Enable signal

Pin or logic cell assignment ignored for chip assigned to AUTO

Pin or logic cell assignment ignored for node <name> -- logic is implemented in a different pin or logic cell

Pin symbol <name> (ID <net ID number>) has more than one line connected to it

Pin [or logic cell] <name> can’t feed <destination> [as a result of user assignments]

Pinstub name <name> is in a misleading location. OK to save the file anyway?

Pinstub/port name <name> is missing from symbol or Function Prototype that represents <filename>.snf

Port <name> declared as an <text> when it should be an <text> for <name> primitive

Port <name> is declared more than once in Function Prototype <name>

Port <name> is tied to <default value>

Port <name> requires the use of port <name>, which is missing

Port <name> should have the direction <direction>

Port count for instance of <macrofunction> (<number>) does not agree with Function Prototype port count (<number>)

Preset and Clear are both active at <time> on register <node name>

Presettable registers will power up high

Previous device and new device have similar pin-outs. OK to convert pin assignments from the previous to the new device?

Primitive <name> cannot be fed by CASCADE primitive <name> because it is already fed by CASCADE primitive <name>

Primitive <name> cannot cascade into primitive <name> -- CASCADE primitive ignored

Primitive <name> cannot feed CASCADE primitive <name>

Primitive <net ID number> is stuck at <text>

Primitive <node name> is stuck at GND

Printer or plotter problem: <text>

Probe <name> already exists -- enter a different probe name

Processing EDIF Input File <filename>...

Processing Library Mapping File <filename>...

Program failure: <text>

Program failure: FLASH bulk erase unsuccessful -- [check device Vpp supply voltage]

Program failure: FLASH bulk programming unsuccessful -- [check device Vpp supply voltage]

Programming complete: [<text>]

Programming hardware error -- voltage for <programming hardware> is out of tolerance

Programming hardware is busy

Programming hardware is not installed

Programming hardware tests failed on <hardware type>

Programming hardware tests were successful

Programming unit <name> is incompatible with this version of device <name>. Contact Altera Applications for up-to-date programming information.

Project archived successfully

Project cannot be simulated -- <filename> contains the network of only one of the project devices

Project compilation canceled: <number> errors; <number> warnings

Project compilation was successful: <number> errors; <number> warnings

Project compilation was unsuccessful: <number> errors; <number> warnings

Project directory <name> does not exist. OK to create it?

Project does not fit in specified device(s)

Project doesn’t fit -- No more AUTO devices allowed for <project name>

Project doesn’t fit. Do you wish to override some existing settings and/or assignments? Choosing No will end compilation and generate a Report File.

Project fit with the following "Advanced Try Harder/Longer Compilation" Fitter Settings. To preserve the fit in future compilations, change to "Custom" in the Fitter Settings dialog box <text>

Project has conflicting default assignments for Turbo Bit and Slow Slew Rate options -- ignoring default Turbo Bit assignment on output pins

Project has multiple devices -- <resource> assignment for <pin/node name> must be associated with a chip

Project has no SNF -- can’t analyze timing

Project has not changed since last compilation

Project has too many symbols in <filename>

Project has user pin or logic cell assignments, but has never been compiled before. For best fitting results, let the Compiler choose the first set of assignments instead

Project requires too many (<number>/<number>) <text> logic cells

Project requires too many (<number>/<number>) <text> pins [<text>]

Project requires too many (<number>/<number>) expanders

Project requires too many (<number>/<number>) output pins, including <number> Output Enable signals implemented on logic cells

Project requires too many (<number>/<number>) shareable expanders

Project simulation canceled: Simulation ended at <time>; Simulation coverage: <number> %; <number> errors; <number> warnings

Project simulation was successful: Circuit stabilized at <time>; Simulation ended at <time>; Simulation coverage: <number> %; <number> errors; <number> warnings

Project simulation was unsuccessful: Circuit stabilized at <time>; Simulation ended at <time>; Simulation coverage: <number> %; <number> errors; <number> warnings

Project SNF does not contain [<I/O type>] node/group <name>

Project too complex [<text>]

Project won’t fit with current constraints for <device name>

Property <name> has multiple definitions -- only the first is accepted (others are ignored)

Property <name> requires a[n] <text> value

R

Race condition exists for flipflop <net ID number> on <node name> -- driven by primitive <net ID number>

Reached beginning of file. Continue search at end?

Reached end of file. Continue search at beginning?

Register <name> and node <name> are assigned to the same location -- can’t implement register packing because the register has 2 or more product terms on its data input

Register <node name> has an fmax assignment but does not feed any other registers

Relative vector pattern is missing a valid stop time

Report File contains advance information

Specifications for <device name> are subject to change

Contact Altera Marketing for information on availability

[<text>]

Reserved resource percentage for <text>: <number>

Reserved unused pin <name> for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board

Reset state is <state name> in machine <name>

Right side of equation may not contain <text>

Ripple Clock detected starting with flipflop <net ID number>

Ripple-clocked logic drives primitive <net ID number>

Rounded non-integer result of LOG2 up to next whole number

S

Save & Check canceled: <number> errors; <number> warnings

Save & Check was successful: <number> errors; <number> warnings

Save & Check was unsuccessful: <number> errors; <number> warnings

Save all changes before compiling the project?

Save all changes to <filename>?

Save changes before opening Enter Assignments dialog box?

Save changes to <filename>?

Save changes to assignments in <filename>?

Save changes to probe, resource, and device assignments for the project?

Saved file, but can’t check non-design file <filename>

SCF <filename> is being used by another application and is locked

SCF successfully generated from <filename>

Search complete

Search text contains illegal character after ^

Search text contains too many wildcard characters

Secondary input <name> is defined twice

Security Bit can only be set for devices -- ignored Security Bit setting for node <name>

Security Bit programming complete

Selected configuration scheme forces 'Disable Start-Up Time-Out' device option for all devices

Selected item(s) <text> assignment. This command edits single assignments only, and will delete <text> assignments. Choose OK to replace <text> assignments with <text> assignment.

Selected text must be a section delimiter

Selecting a device from <device family> family for AUTO device <chip name>

Sheet size <name>:<dimensions> selected for file

Sheet size too small for drawing

Simulator is loading or converting a file. OK to stop the Simulator?

Size of WHEN group different than CASE group

Smart recompilation skipped the <module name> because it is not required

SMF syntax error: [<text>]

SNF <filename> is being used by another application and is locked

SNF for project does not contain node <name>

Some clearable/presettable registers will power up high

Source removed by mapping

Start time <time> is after SCF end time <time> -- changing start time to 0.0ns

State <name> already exists

State <name> in state machine <name> is never exited

State <name> of state machine <name> has no transitions

State bit <name> of state machine <name> may not be assigned a value

State bit assignments are not unique for state machine <name>

State machine <name> feeds logic

State machine <name> must be reset to guarantee proper operation

State machine Case Statements may not have groups in their WHEN clauses

State name <name> has no corresponding definition in state machine <name>

State value <value> has more significant bits than declared state bits

State variable definition must begin with left bracket ([): (<code>, <text>)

State variable definition must end with right bracket (])

States of input state machines may not be assigned a value

States Subsection terminated incorrectly

Stopping after current fitting attempt by request of the user

Stopping after generating Report File by request of the user

Style name <name> already exists. OK to overwrite?

Style name <name> has been edited. Do you want to save the edits?

Subdesign already specified in another design file

Subdesign and Logic Sections missing from design file

Subdesign name <name> must be the same as the filename <filename>

Substituted <text> for <text>

Successfully generated Table File <filename>

Successfully implemented all timing assignments

Switching from "smart" recompile to normal compile -- can’t <text> file <filename>

Symbol <name> (ID <net ID number>) has no <text>

Symbol <name> (ID <net ID number>) overlaps another symbol

Symbol <name> is not on a library path

Symbol <net ID number> has more than one name -- <symbol name>

Symbol <net ID number> has no name

Symbol corrupted

Symbol generation canceled: <number> errors; <number> warnings

Symbol generation was successful: <number> errors; <number> warnings

Symbol generation was unsuccessful: <number> errors; <number> warnings

Symbol or Function Prototype <net ID number> does not match its design file: it has <number> pinstubs/ports, but the design file has <number> pins

Symbol or Function Prototype for macrofunction <name> contains pinstub/port <name> with I/O type <text>, but its I/O type is different in <filename>.snf

Symbol too long in <state machine name>

Symbolic name <name> already declared [<text>]

Symbolic name <name> does not have ports

Symbolic name <name> is not a port of <name>

[Input ports: <names>]

[Output ports: <names>]

Symbolic name <name> is not a state of state machine <name>

Symbolic name <name> was declared as a Function Prototype, not a variable

Symbolic name <name> was declared but never used

Symbolic name <name> was not <text>

Syntax error: [<text>]

T

TDF syntax error: [<text>]

Test failure: <text>

Test inconclusive -- no outputs were compared

Test successful: no errors

Testing hardware is not installed

Text on the current line does not contain a section delimiter

Text size <number> is not available in the <name> font

This project was originally created for a Xilinx device. To achieve the best device performance and utilization, Altera recommends switching to an Altera design entry method.

Timing analysis canceled

Timing analysis completed

Timing Analyzer is running -- command ignored

Too many characters in <node/pin name> (max = 32)

Too many clocks or timers

Too many destination nodes (<number>) are tagged

Too many inputs or buried logic cells assigned to I/O pins

Too many inputs to logic primitive

Too many members in group <name> (max. = 256)

Too many nodes in file

Too many nodes/groups in Vector File (max. = 4096)

Too many nodes/groups to list: out of memory

Too many or few inputs on right-hand side of primitive statement

Too many or few signals on left-hand side of primitive statement

Too many source nodes (<number>) are tagged

Too many state variables (max. = 16)

Too many subdesigns -- only 200 are allowed

Too many timing assignment <text> nodes (<number>) in design file(s) to report whether timing assignments have been implemented successfully

Too many transitions in Pattern Section

Too many user libraries

Too many/few <text> ports (<number>) -- expected <number>

Too many/few arguments for command: <command>

Too many/few numerical indexes in port -- expected <number>

Too many/few state variable values

TRI buffer <net ID number> already drives OUTPUT pin; it cannot also drive other types of primitives

TRI buffer <net ID number> already feeds a BIDIR pin; it cannot also drive pin <name>

TRI buffer <net ID number> and primitive <net ID number> cannot be assigned to different devices

TRI buffer <net ID number> can only drive logic [(<net ID>)] if connected to a BIDIR pin

TRI buffer <net ID number> has a tpd or tco timing assignment but does not feed any bidirectional pins

TRI buffer <net ID number> is permanently disabled

Tried to compare Vector File to <filename>, but SNF is <text>

Truncated result of division with non-zero remainder

Truth table: missing <text> declarations

Truth table: too many/few <text> arguments

Trying to find new partition/fit after discarding assignments by request of the user

Turbo Bit logic option turned on automatically for <name> because pin assignments require <name> to borrow and lend parallel expanders

U

Undeclared input or output pin name <name>

Undeclared input: <pin name>

Undefined state: (<state name>) in <state machine name>

Unexpected EOF in <section name>

Unknown combinatorial feedback structure detected at primitive <net ID number>

Unknown combinatorial flipflop detected at primitive <net ID number>

Unknown combinatorial latch detected at primitive <net ID number>

Unknown device <device name> [in Fit File]

Unreachable <text> Statement: (<state name>) in <state machine name>

Unreachable conditional statement: (<state name>) in <state machine name>

Unreachable state <name> in state machine <name>

Unreachable unconditional statement: (<state name>) in <state machine name>

Unrecognized device or socket is empty

Unrecognized section

Unrecognized symbol in state assignment

V

Value <number> is not a <text> time value

Value of <parameter name> parameter is unresolved or illegal (<value>)

Variable <name> in ACF is obsolete -- delete variable and respecify setting with the Compiler’s Fitter Settings command

Variable <name> is set to <setting>

VCC/GND must be specified for <node name> -- mapping is ignored

Verify failure: <text>

Verify successful: [<text>]

Vertical page scale must be an integer between <number> and <number>

W

WDF <filename> is being used by another application and is locked

Width mismatch in pinstub <name> (ID <net ID number>)

Windows system error

X

XNF symbol <name> (named <name>) is not supported by Altera devices

Y

You have assigned chips to devices from multiple families. OK to convert all devices not from the current family to AUTO?

You have purchased an Altera development system that includes a site license to install an unlimited number of copies of MAX+PLUS II with the PLS-ES feature set

Your project’s ACF contains syntax errors -- Altera recommends correcting these syntax errors before continuing work on the project

Your version of MAX+PLUS II does not include an application that can edit *.<extension> files

Your version of MAX+PLUS II does not include <device/family name> compilation support -- projects created with this device will not compile

Your version of MAX+PLUS II does not include the <name> application or feature


----------------------BEGINNING OF NON-TRANSLATED TEXT--------------------------

The following panel is a Message Processor basic tool. Both of the following 2 panels give the list of message prefixes so both panels are kept here to make editing easier

----------------------END OF NON-TRANSLATED TEXT--------------------------


Message Format (Message Processor)
Message Format

A MAX+PLUS II message consists of descriptive message text, which is sometimes preceded by one or more of the following prefixes:

Error:

Info:

Warning:

Design Doctor Warning:

<filename abbreviation> File <filename>:

File <filename>:

Line <number>:

Column <number>:

Parameterized module <name>:

The descriptive message text in MAX+PLUS II Messages is written in BNF format. All messages are listed in alphabetical order, without the prefixes listed above.


message prefixes glossary definition
message prefixes

Message prefixes consist of one or more of the following strings of text:

Error:

Info:

Warning:

Design Doctor Warning:

<filename abbreviation> File <filename>:

File <filename>:

Line <number>:

Column <number>:

Parameterized module <name>:


VHDL Messages

MAX+PLUS II messages appear both in pop-up message boxes and in the Message Processor window. The Message Processor can also save messages in a Message Text File.

All messages are listed here in alphabetical order, without prefixes. Click Button 1 on the first letter(s) of a message (without the prefix) to jump to the section of the list starting with that letter, then choose a message for information on its possible causes and suggested appropriate actions.

A B C D E F G H I L M N O P Q R S T U V W

See also:

Getting Help on a Message

Internal Errors

Locating the Source of a Message

Message Format

Saving Messages to a File

<name> denotes the configuration being defined

"<name>" does not denote a label

"<name>" may not be <text>

<name> Statements are allowed only within a loop

<name> Statements must be labelled

A

Absolute value of universal expression is too large for implementation

Actual error: Literals can’t be written or passed as actuals to formals of mode out

Actual signal must have a static signal name

Aggregate error: A non-locally static OTHERS must be the only formal in the aggregate

Aggregate error: Choice OTHERS can’t appear in an aggregate of Unconstrained Array type

Aggregate error: Element associations in Array aggregates must be all named or all positional

Aggregate error: Elements associated by an OTHERS association in a Record aggregate must all have the same type

Aggregate error: No associations may follow an OTHERS association

Aggregate error: Null range or non-locally static choice must be the only choice in the aggregate

Aggregate error: Only one OTHERS association is allowed per aggregate

Aggregate error: OTHERS associations in Record aggregates must associate at least one element

Aggregate error: Type of this aggregate must be Array or Record

Alias Declaration error: Can't use name with a multi-dimensional array type

Alias Declaration error: Name must denote an object

ALL has no meaning with this prefix

All subelements of resolved signal <name> have not been <text>

Allocator requires either a subtype indication or a Qualified Expression

Analysis order error: Architecture <name> of entity <name> in library <name> is out of date and must be reanalyzed

Analysis order error: Primary unit <name> in library <name> is out of date and must be reanalyzed

Analysis order warning: Primary unit <name> in library <name> depends on a modified unit

Any previous unit in this file that depends on this unit is now out of date

Architecture <name> of entity <name> in library <name> depends on a modified unit

Array error: Array contains the wrong number of elements

Array error: Array value index constraint is incompatible with the specified type

Array error: Constraints on the "<name>" return type must match those on the "<name>" parameter type

Array error: Discrete range direction does not match the prefix direction

Array error: Index expression range does not intersect the range specified by the corresponding array index subtype

Array error: Index value is not within the range specified by the corresponding array index subtype

Array error: Number of constraints supplied does not equal the number of indices

Array error: Number of elements in array value is not equal to the number of elements specified by the type

Array error: Prefix of the <name> attribute must be constrained

Array error: Range specified in slice is incompatible with the corresponding array index constraint

Array error: Variable index range greater than the range specified by the corresponding array index subtype

Assignment error: <name> must be a locally static name

Assignment error: A <text> appears more than once in the target of this assignment

Assignment error: Can’t determine the type of the <text> of this assignment

Assignment error: Number of elements in this expression does not equal number of elements in the target of this assignment

Assignment error: Range of expression does not intersect the range specified by the type of the target of this assignment

Assignment error: Source-target type mismatch

Assignment error: Target of this assignment is not <text>

Assignment error: Value does not lie within the range specified by the type of the target of this assignment

Association list error: Actual does not correspond to any formal

Association list error: Actual is associated with a previously associated formal

Association list error: Association element subtype is incompatible with the associated element subtype

Association list error: Association element type is incompatible with the associated element type

Association list error: Can't determine the formal designator's type

Association list error: Can't use positional association after named association

Association list error: Can't use positional association after named association

Association list error: Formal "<name>" must be associated with an actual <text>

Association list error: Formal part of association is in the form of a type conversion, but is invalid

Association list error: Formal part of association is not a name or a type converted name

Association list error: Illegal formal part in named association

Association list error: Illegal formal type

Association list error: Independent formal subelement association is not allowed on formals of type <type name>

Association list error: Invalid formal in association element

Association list error: Non-defaultable formal "<name>" is not associated

Association list error: Subelement of <name> is not associated

Attribute <name> must <text>

Attribute error: <name> attribute is applicable only to <name>

Attribute error: "<name>" does not denote an attribute

Attribute error: Attribute <name> does not yield a value

Attribute error: Attribute <name> is already specified for entity <name>

Attribute error: Attribute "<name>" is not a user-defined attribute

Attribute error: Can't read attribute <name> of signal within a subprogram

Attribute error: Illegal reference to predefined attribute <name>

Attribute Specification error: Attribute Specification for design unit is for wrong class of design unit or not in the design unit's declarative part

Attribute Specification error: Can't associate entity with <name> -- it is not an attribute

Attribute Specification error: Entity does not have an attribute named "<name>"

Attribute Specification error: Illegal declaration of <name> following Attribute Specification that applies to it

Attribute Specification warning: OTHERS used without previous Attribute Specification of same class

B

Bad encoding string <text>

Bad form for attribute <text> value; expecting string literal

Bad meaning for attribute <text>

Bad meaning for name <text>

Based Literal error: Base of numbers must be between 2 and 16

Based Literal error: Illegal digit

Bit String Literal error: Binary digits are limited to '0' and '1'

Bit String Literal error: Bit String Literal can only represent arrays of element type BIT

Bit String Literal error: Octal digits are limited to '0' through '7'

Block configuration error: Block configuration in a component configuration requires an implied entity

Block configuration error: Block Specification may contain only one name

Block configuration error: Block specification must be an architecture name, a block statement label, or a generate statement label

Block configuration error: Index specification can be applied only to a label denoting a "FOR GENERATE" statement

Block configuration error: index specification must be either an expression or a range

Block Statement error: Implicit signal GUARD must not have a source

Block Statement error: No signal called "GUARD" exists

C

Can't apply a range constraint to an access type

Can't associate port "<name>" with OPEN

Can't continue -- one or more library logical names have no translation

Can't determine association type

Can't find STANDARD package

Can't find STD library

Can't find the corresponding <text> declaration for this <text>

Can’t locate node with information from existing HIF -- recompile the project to generate a new HIF

Can't process this configuration -- no corresponding entity exists in the working library

Can’t provide tsu of <time> from <name> to memory <name> using Write Enable pin <name>. Current tsu is <time>.

Cannot attribute from within a secondary unit any entity declared in the corresponding primary unit

Case Statement error: One or more case alternatives are missing

Case Statement error: OTHERS choice is required in this Case Statement

Case Statement or Selected Signal Assignment error: Alternative does not belong to the selector's type or subtype

Case Statement or Selected Signal Assignment error: Alternative is not locally static

Case Statement or Selected Signal Assignment error: Alternative repeats a previous choice

Case Statement or Selected Signal Assignment error: OTHERS choice must be the last alternative

Case Statement warning: Case Statement has too many possibilities for coverage and overlap checking

Compiling package <name>

Component <name> does not have a <text> clause

Component does not exist

Component Instantiation error: <name> is not an instance of component <name>

Component Instantiation error: Illegal Component Instantiation Statement

Concurrent Signal Assignment Statement error: Concurrent signal assignment target is neither guarded nor unguarded

Concurrent signal assignment error: Null waveform element can’t appear in a concurrent signal assignment

Concurrent signal assignment error: Target of this signal assignment is guarded, but assignment is not a guarded signal assignment

Configuration Specification error: Component has not been bound

Configuration Specification error: Component is bound more than once

Configuration Specification error: Components must be fully bound to <name> (<name>)

Configuration Specification error: Generic map or port map in binding indication does not imply a design entity

Configuration Specification error: Local generic "<name>" cannot be bound to any formal

Configuration Specification error: Local port "<name>" cannot be bound to any formal

Configuration Specification error: More than one configuration affects instance of component <name>

Configuration Specification error: "Open" can only be used as the actual of a port or a generic map

Configuration warning: OTHERS used without previous configuration of same component

Constant Declaration error: Deferred constant "<name>" must be completed before it is referenced here

Constant Declaration error: Deferred constant can be completed only in a package body

Constant Declaration error: Deferred constant can be declared only within a package declaration

Constant Declaration error: Found duplicate full declaration of constant "<name>"

Constants cannot be written

D

Design library error: Can’t locate the working library

Design library error: Library <name> (translation: "<name>") referenced in <name> cannot be opened

Design library error: Library name <name> has multiple definitions; none are used

Design library error: Library unit is inaccessible

Design library error: No library <name> exists (translation: <name>) or it cannot be read

Design library error: Primary unit <name> in library <name> can't be opened

Detected unresolved overloaded name

Disconnection Specification error: <text> expression in a <text> must be static

Disconnection Specification error: Disconnection Specification of type <name> is illegal following Disconnection Specification for ALL or OTHERS

Disconnection Specification error: More than one Disconnection Specification affects signal of type <type name>

Disconnection Specification warning: OTHERS used without previous Disconnection Specification of same type

Duplicate pin name <text>

Duplicate state name <name>

E

Each scalar subelement of signal <name> has not been <text>

Element "<name>" is unassociated in the aggregate

ELSE clause following Clock edge must hold the state of signal <name>

Entity Declaration error: <text> is not passive

Entity error: No corresponding entity exists in the working library

Entity error: No matching entity of this class exists in the current declarative part

Entity <name> does not have an Architecture Body

Errors in <name> prevent further processing

Exponentiation error: Negative exponent is allowed only for a left operand of a Floating Point type

Expression must be of type STD.STANDARD.Time

Expression type error: Expression is not of type <name>

Expression type error: Type of this expression cannot be determined

Expression type error: Type of this expression is not unique

Expression type error: Value of expression is not within the bounds of the type of the expression

Expression value is not within the range specified by the type

F

File <name> does not contain an Architecture Body. Stopping Compilation.

File <name> does not contain an Architecture Body. No <text> created.

File declaration subtype must denote a file type

Flipflops must be implemented with If Statements

Formal parameter error: Constant parameters must be of mode IN

Formal parameter error: Formal function parameters must be of mode IN

Formal parameter error: Formal function parameters must have an object class of CONSTANT or SIGNAL

Found duplicate body of subprogram "<name>"

Found extraneous attribute parameter

Found multiple assignments to the same signal or signal bit <name> in a Process Statement -- only the last assignment will take effect

Found multiple sources for signal <name>, which is associated with a BUFFER port

Found multiple sources for unresolved <text>

G

Generic declarations must be constants (generics are supported only in scalar type and subtype declarations in MAX+PLUS II)

Generic declarations must be of mode IN

H

High-impedance (Z) value(s) of constant <text> can’t be processed as tri-state buffer(s)

I

Ignored attribute <text>

Ignored construct: <text>

Ignored Resolution Function in <text>

Illegal Concurrent Procedure Call Statement

Illegal guarded signal declaration of type <name> following disconnection specification

Illegal reference to an incomplete type

Illegal use of keyword ALL

Implementation limit: <text>

Incorrect number of elements for conversion to type "<name>"

Index value <number> is out of bounds for VHDL Object <text>

Interface Declaration error: BUS keyword is not allowed in a non-signal declaration

Interface Declaration error: Ports of mode LINKAGE cannot have a default expression

Interface files cannot have a default expression

Interpreting as <text>

Invalid attribute prefix

L

Last association in list must be OTHERS

Library logical name <name> has changed since <name> was analyzed

Library name "<name>" does not translate to a logical name

Literal error: Exponent of integers must not be negative

Literal error: Literals can’t be passed as actuals to <text>

Literal error: Literals can’t serve as type marks

Literal error: String contains the wrong number of characters

Local <text> is not associated as a whole with a formal <text>

Loop error: Labeled <text> Statements are allowed only within the named loop

Loop Statement error: Range in a "FOR" iteration scheme is not of a discrete type

M

Math overflow while processing <number>

More than one If and/or Case Statements in a process assign values to signal <name>

Multiple nodes assigned to same location <name>

N

Name <name> is <text>

Name error: <text> must be a static name

Name error: Ending name does not match beginning name

Name error: Last part of name has no meaning with prefix

Name error: Library name is not valid in this context

Name error: Name "<name>" is already declared

Name error: Name "<name>" is ambiguous

Name error: Name "<name>" is undefined

Name error: Name must a package in library <name>

Name error: Name must be a package in the working library

Name error: Name must be a primary unit in the working library

Name error: Name must be a simple or selected name

Name error: Name must be the name of a library

Name error: Prefix of attribute name is ambiguous

Name error: Prefix of name is ambiguous

Name error: Prefix of name is invalid

Name error: Prefix of slice name must denote a one-dimensional array type

Name error: Prefix of this name must be the working library

Name error: Suffix of name must be a selector

Name error: Suffix of name must be an identifier

Named association is not allowed in this context

Need to update <text>

No corresponding package exists in the working library

No guarded signal called "<name>" exists in the current declarative region

Node <name> missing source

Nonportable extension: Choice OTHERS in an aggregate of unconstrained array type is not supported by IEEE Std 1076-1987

O

Only one <text> signal can be defined for a flipflop

Only one formal is allowed in this context

Only signals may be passed to ports of mode LINKAGE

Operation arguments must have the same length

OTHERS choice can’t appear in a list of choices

OUT and INOUT procedure call arguments in procedures not declared within processes must be formals of the procedure or one of its parents

Output file name is too long and will be truncated

Overloading error: Illegal designator on overloaded operator

Overloading error: Operator "<name>" must have <text>

P

Package body does not provide a completion for the deferred constant <name>

Package STD.STANDARD has an obsolete format, processing continuing

Parameter is required for <name> attribute

Parameter to the <name> attribute does not refer to one of the bounds of the array type <type name>

Parameter to the <name> attribute must be of <type name> type

Parameter to the <name> attribute must not be negative

Physical literal value overflowed implementation limit

Port <name> declared as an <text> when it should be an <text>

Port <name> is not the correct width for <text> primitive

Port error: Found multiple sources for a BUFFER port

Port error: Port declarations must be signals

Predefined attribute error: "<name>" already has a predefined attribute named "<name>"

Predefined attribute error: BASE attribute is allowed only as the prefix of another attribute

Predefined attribute error: Parameter to the <name> attribute must be a static expression

Predefined attribute error: Predefined attributes have at most one parameter

Predefined attribute error: Prefix of <name> attribute must be a static name

Process clocking is too complex

Process Statement warning: Process may run forever

Q

Qualified Expression error: Operand of this Qualified Expression contains the wrong number of elements

Qualified Expression error: Prefix of a Qualified Expression must be a type mark

Qualified Expression error: Type mark of this Qualified Expression can’t uniquely type the operand

Qualified Expression error: Type mark of this Qualified Expression permits no valid interpretations of the operand

Qualified expression error: Qualifier of this expression must be a type mark

R

Range error: Expression range does not intersect the range specified by the type

Range error: Illegal discrete range

Range error: Index constraints are applied to an array type whose designated type is not an array type or to an unsupported access type

Range error: Only one range bound is of integer type or range bound has an unsupported floating point type

Range error: Range bounds defining this type must be locally static

Range error: Range does not yield a value

Range error: Type bounds are not all of an integer type or type bounds have an unsupported floating-point type

Relational expression with meta-logic is evaluated to FALSE

Resolution Function error: Can't constrain the parameter of a Resolution Function (Resolution Functions can only describe wired-OR, wired-AND, or tri-state behavior in MAX+PLUS II)

Resolution Function error: Can't use SIGNAL as the object class of the parameter to a resolution function

Resolution Function error: No resolution function exists with this name

Return Statement error: Base type of Return Expression must be base type of return type mark given in the Function Specification

Return Statement error: Return Statements appearing within functions must return a value

Return Statement error: Return Statements appearing within procedures must not return a value

Return Statement error: Return Statements can only appear in subprogram bodies

Right operand of <name> operator must be a power of 2

S

Selector expression must be of a discrete type or of a one-dimensional character array type

Selector expressions of one-dimensional array type must <text>

Semicolon is extraneous

Sensitivity list error: Name in this sensitivity list does not denote a signal

Signal <name> has multiple sources

Signal <name> is not a guarded signal

Signal <name> was <text> extended

Signal assignment error: Null waveform elements can only be assigned to guarded signals

Signal assignment error: Time expression in a waveform element can’t be negative

Signal assignment error: Times in this waveform are not in ascending order

Signal assignment targets in procedures not declared within processes must be formals of the procedure or one of its parents

Signal Declaration error: Can't declare implicit signal "GUARD"

Signal Declaration error: Guarded signal "<name>" must also be resolved

Signal Declaration error: Signal <name> is not of type <name>

Signal is driven by illegal value -- Asynchronous Control for DFF is initializing the DFF to a value other than logic '0' or logic '1'

Signal name may not appear as a primary in this context

Space required between abstract literal and unit name

Static Expression error: Expression must be locally static

Static expression error: Expression must be globally static

Static expression error: Found arithmetic overflow when evaluating this locally static expression

Subprogram Body error: Function does not contain a Return Statement

Subprogram error: <text> declared outside this function may not be referenced within the function

Subprogram error: <text> has a declaration but no body

Subprogram error: Constraints can’t be specified in a Function Declaration

Subprogram invocation error: Can’t find a function named "<name>" with these parameters

Subprogram invocation error: Name must be a procedure

Subprogram invocation error: Procedure <name> is ambiguous

Subprogram invocation error: Procedure call is inconsistent with all visible procedures having this name

Subtype indication in an allocator must either denote a constrained subtype or include an explicit constraint

Suggested correction: <text>

Symbol has a homograph with non-conforming declaration

Symbolic name <name> is not a port of <name>

T

Type conversion error: <text> of this Type Conversion Function must be constrained

Type conversion error: Invalid use of a Type Conversion Function

Type conversion error: On formals of mode <text>, if formal or actual is type converted, both must be

Type conversion error: Operand of a Type Conversion Function cannot be <text>

Type conversion error: Parameter to Type Conversion Function "<name>" does not have the correct number of elements

Type conversion error: Result type of type conversion is not closely related to the type of its operand

Type conversion error: Type Conversion Function does not return the correct number of elements

Type conversion error: Type Conversion Function does not return type <name>

Type conversion error: Type Conversion Functions are not allowed on actuals for formals of mode <text>

Type conversion error: Type Conversion Functions are not allowed on formals of mode IN

Type conversion error: Type Conversion Functions can’t include File types

Type conversion error: Type Conversion Functions must be declared with a single argument

Type conversion error: Type conversion is not allowed on signal parameters

Type conversion error: Type of operand in type conversion cannot be determined independent of its context

Type conversion functions are not allowed on actuals for formals of mode BUFFER

Type Declaration error: Incomplete type declaration must be completed

Type error: "<name>" does not denote a type or subtype

Type error: <text> must be of a constrained array subtype

Type error: <text> range bound type is incompatible with the range type

Type error: Bounds defining a physical type must be of some integer type

Type error: Can't determine the parameter type

Type error: Can't uniquely determine the range type

Type error: Can't use type mark as a constraint

Type error: Cannot further constrain a constrained array type

Type error: Constraint is inconsistent with the range type

Type error: Constraint specified on subtype indication is incompatible with the constraint on the specified type or subtype

Type error: Expression must denote a physical type

Type error: Formal is not an element of the record type

Type error: Index constraint is not of a discrete type

Type error: Index constraint type mark does not denote a discrete type

Type error: Invalid constraint in subtype indication

Type error: Must be a physical unit

Type error: Must be an integer physical literal of the current type

Type error: Range bound is not of a discrete type

Type error: Range bound types are incompatible with the range type

Type error: Range bounds have incompatible types

Type error: Range values must belong to a scalar type

Type error: Record type <type name> does not have an element numbered <element number>

Type error: Return type mark index ranges and the returned expression type must have the same direction

Type error: Subtype of the selector expression must be constrained

Type is an access to itself

U

Undefined (X) values of constant <value> are interpreted as 0

Unit <name> is not a VHDL design unit; ignoring it

Unknown problem in file <name> <text>

Unlabeled statement can't have ending label

Unsupported arithmetic operation encountered <text>

Unsupported feature: <text>

Unsupported feature: Combinatorial feedback exists inside a Process Statement. Signal(s)/variable(s): <name(s)>

V

Variable Declaration error: Procedure parameters must be of mode IN, OUT, or INOUT

VHDL Design File <name> must contain entity of the same name

VHDL Netlist Reader limitation: <text> during static expression evaluation

VHDL Netlist Reader limitation: <text>

VHDL Netlist Reader limitation: <text>

VHDL Netlist Reader limitation: Can't determine validity of string literal's characters

VHDL syntax error: Expected a block, but this is not a block

VHDL syntax error: Expected a component, but this is not a component

VHDL syntax error: Expected a configuration, but this is not a configuration

VHDL syntax error: Expected a package name

VHDL syntax error: Expected an architecture, but this is not an architecture

VHDL syntax error: Expected an entity, but this is not an entity

VHDL syntax error: Expected a type or subtype name, but this is neither

VHDL syntax error: Expected Component Instantiation, but this is not a Component Instantiation

VHDL syntax error: OTHERS is not allowed in this context

W

Wait Statement error: Value of timeout expression cannot be negative

Wait Statement error: Wait Statements cannot appear in <text> or in procedures called from <text>

Width of flipflop control signals must be a single bit

Width of logical operand <name> does not match width of result

Width of operand <name> is greater than width of result


-----BEGINNING OF NON-TRANSLATED TEXT-----

The following LS_MSGS.MSG and MLSMSGS.MSG messages are not documented in this file:

FLS_ILLEGAL_COMB_FEEDBACK	COMESS.MAC

FLS_OUT_OF_MEMORY	GLMESS.MAC

WLS_PRIM_STUCK_AT_GND	COMESS.MAC

emls_cant_separate_tri	PRIMMESS.MAC

EMLS_ILLEGAL_USE_OF_REG	PRIMMESS.MAC

EMLS_ILL_OBJ_DRIVING_IOPIN	PRIMMESS.MAC

emls_sclk_bad_source	PRIMMESS.MAC

EMLS_TRI_FEEDS_BIDIR	PRIMMESS.MAC

wmls_warn_ignore_ipin	PRIMMESS.MAC

wmls_warn_latch_disabled	PRIMMESS.MAC

wmls_warn_no_clock_transition	PRIMMESS.MAC

wmls_warn_tristate_disabled	PRIMMESS.MAC

wmls_warn_trivial_reg_gnd	PRIMMESS.MAC

wmls_warn_trivial_reg_vcc	PRIMMESS.MAC

wmls_warn_trivial_use_latch	PRIMMESS.MAC

-----END OF NON-TRANSLATED TEXT-----


Can’t assign combinatorial logic <node name> to an I/O pin

CAUSE:	The specified combinatorial logic node has been assigned to an I/O cell register, but the only type of logic function that can be assigned to an I/O cell register is a DFF primitive. This message may occur if you may have inadvertently placed a pin assignment on a register rather than on the pin that the register feeds.

ACTION:	Delete the pin assignment or turn off the I/O Cell Register logic option on the register.

See also:

Assigning a Logic Option

Assigning a Pin, Location, or Chip

Deleting an Assignment

MAX+PLUS II Messages

Message Format


Can’t assign register <node name> to the periphery because it uses an asynchronous Preset

CAUSE:	The specified register, which uses an asynchronous Preset signal, has been assigned to an I/O cell register. This logic configuration is not available in FLEX 8000 and MAX 9000 devices.

ACTION:	Make pin assignments to input, output, and bidirectional pins only; do not assign a register to a pin. Change the logic in the design file to remove the asynchronous Preset signal on the register, or turn off the I/O Cell Register logic option on the register.

See also:

Assigning a Logic Option

Assigning a Pin, Location, or Chip

Deleting an Assignment

MAX+PLUS II Messages

Message Format


Can’t feed an inverted input pin to input register <node name>

CAUSE:	You have assigned a register to an I/O cell register, but it is fed by an inverted input pin, i.e., a signal from an input pin that passes through a NOT gate. This logic configuration is not available in MAX7000E, FLEX 8000, and MAX 9000 devices.

ACTION:	Make pin assignments to input, output, and bidirectional pins only; do not assign a register to a pin. Change the logic in the design file to remove the inversion on the input signal to the register, or turn off the I/O Cell Register logic option on the register.

See also:

Assigning a Logic Option

Assigning a Pin, Location, or Chip

Deleting an Assignment

MAX+PLUS II Messages

Message Format


Can't merge logic fed by CARRY primitive <net ID> into a single logic cell
Can’t merge logic fed by CARRY primitive <net ID> into a single logic cell

CAUSE:	The Logic Synthesizer cannot merge the logic that is fed by the specified CARRY primitive into a single logic cell.

ACTION:	No action is required. The Logic Synthesizer either ignores the CARRY primitive or automatically inserts an LCELL primitive on the output of the specified CARRY primitive to allow it to feed the logic that could not be implemented in a logic cell as a non-CARRY input. However, if you wish to avoid receiving this warning message in the future, insert an LCELL primitive on the output of the CARRY primitive, or insert LCELL primitives in the logic that feeds the CARRY primitive.

See also:

MAX+PLUS II Messages

Message Format


Can’t minimize <node name> completely

CAUSE:	The logic associated with the specified node(s) name was too complex to be minimized by the Logic Synthesizer, so it has been only partially minimized. In some cases, the project will fit anyway.

ACTION:	If your project does not fit, try to simplify it by inserting LCELL or SOFT primitives. It may also help to turn on the SOFT Buffer Insertion logic option in the default logic synthesis style that is specified for the project as a whole.

See also:

Defining a Logic Synthesis Style

MAX+PLUS II Messages

Message Format

Specifying Global Project Logic Synthesis Settings


CARRY primitive <net ID> and CASCADE primitive <net ID> cannot both feed logic cell <node name> -- etc
CARRY primitive <net ID> and CASCADE primitive <net ID> cannot both feed logic cell <node name> -- LCELL inserted automatically

CAUSE:	The specified CARRY and CASCADE primitives cannot both feed the specified logic cell, so the Logic Synthesizer has automatically inserted an LCELL primitive on the output of the specified CARRY primitive to implement the logic.

ACTION:	No action is required. However, if you wish to avoid receiving this warning message in the future, insert an LCELL primitive on the output of the CARRY primitive, or remove the specified CASCADE and/or CARRY primitive.

See also:

MAX+PLUS II Messages

Message Format


CARRY primitive <net ID> cannot fan out to more than one non-CARRY primitive

CAUSE:	The specified CARRY primitive feeds more than one other non-CARRY primitive. This logic configuration is not allowed.

ACTION:	No action is required. The Logic Synthesizer either ignores the CARRY primitive or automatically inserts an LCELL primitive on the output of the CARRY primitive to allow it to feed the non-CARRY primitive(s) only as a non-CARRY input. However, if you wish to avoid receiving this warning message in the future, redesign your logic or insert an LCELL primitive between the output of the CARRY primitive and all but one of the other non-CARRY primitives that it feeds. A CARRY primitive can feed only one other CARRY primitive and one non-CARRY primitive.

See also:

MAX+PLUS II Messages

Message Format

Primitive Interconnections


CARRY primitive <net ID> cannot fan out to more than one other CARRY primitive

CAUSE:	The specified CARRY primitive feeds more than one other CARRY primitive. This logic configuration is not allowed.

ACTION:	No action is required. The Logic Synthesizer either ignores the CARRY primitive or automatically inserts an LCELL primitive on the output of the CARRY primitive to allow it to feed all but one of the CARRY primitives as a non-CARRY input. However, if you wish to avoid receiving this warning message in the future, redesign your logic or insert an LCELL primitive between the output of the CARRY primitive and all but one of the other CARRY primitives that it feeds. A CARRY primitive can feed only one other CARRY primitive and one non-CARRY primitive.

See also:

MAX+PLUS II Messages

Message Format

Primitive Interconnections


CARRY primitive <net ID> ignored

CAUSE:	The Logic Synthesizer cannot could not implement the carry logic from the specified CARRY primitive in any logic cell. This message may occur if the CARRY primitive feeds more than one non-CARRY primitive but doesn’t feed any other CARRY primitives.

ACTION:	No action is required. However, if you wish to avoid receiving this warning message in the future, you can remove the CARRY primitive, or insert an LCELL primitive between the output of the CARRY primitive and all but one of the other non-CARRY primitives that it feeds. A CARRY primitive can feed only one other CARRY primitive and one non-CARRY primitive.

See also:

MAX+PLUS II Messages

Message Format


CARRY primitive <net ID> must feed an LCELL primitive

CAUSE:	The specified CARRY primitive feeds the Clock, Clear, Preset, Clock Enable, or Output Enable input of another primitive, or it feeds an OUTPUT, OUTPUTC, BIDIR, or BIDIRC primitive, but this logic configuration is not allowed.

ACTION:	No action is required. The Logic Synthesizer either ignores the CARRY primitive or automatically inserts an LCELL primitive on the output of the CARRY primitive to allow it to feed the primitive(s) as a non-CARRY input. However, if you wish to avoid receiving this warning message in the future, insert an LCELL primitive on the output of the CARRY primitive (between the CARRY and the pin primitive).

See also:

MAX+PLUS II Messages

Message Format

Primitive Interconnections


CASCADE primitive <node name> cannot feed primitive <name>

CAUSE:	The specified CASCADE primitive feeds a primitive other than an AND or OR gate. CASCADE primitives can only feed AND and OR gates. (An inverted OR gate is treated as an AND gate and vice-versa. Logical equivalents of AND gates are BAND, BNAND, and NOR. Logical equivalents of OR gates are BOR, BNOR, and NAND.)

ACTION:	No action is required. The CASCADE primitive will be ignored. Change the logic or remove the CASCADE primitive to avoid receiving the warning again.

See also:

MAX+PLUS II Messages

Message Format


CASCADE primitive <name> cannot feed primitive <name> because it already feeds primitive <name>

CAUSE:	The specified CASCADE primitive cannot feed the specified primitive because a CASCADE primitive is allowed to feed only a single AND or OR gate. (An inverted OR gate is treated as an AND gate and vice-versa. Logical equivalents of AND gates are BAND, BNAND, and NOR. Logical equivalents of OR gates are BOR, BNOR, and NAND.)

ACTION:	No action is required. The CASCADE primitive will be ignored. Create a separate CASCADE primitive and duplicate the AND or OR logic that feeds each CASCADE primitive for every fan-out destination to avoid receiving the warning again.

See also:

MAX+PLUS II Messages

Message Format


Clear and Preset for <name> reduce to the same signal
Clear and Preset for <node name>  reduce to the same signal

CAUSE:	The Clear and Preset inputs to a register are tied to (or reduce to) the same signal. This condition causes both Clear and Preset to be active at the same time and can create incorrect results.

ACTION:	Ensure that the Clear and Preset signals do not reduce to the same signal.

See also:

MAX+PLUS II Messages

Message Format


GLOBAL primitive on node <name> feeds logic -- non-global signal usage may result

CAUSE:	A GLOBAL primitive feeds some complex logic.

ACTION:	If you intend for the global signal to feed logic, then no action is required. If you intend the signal to be used only as a global signal, then your project has an error. To eliminate this warning, you should either delete the GLOBAL primitive or move the connection of the input signal that feeds the logic to occur before the GLOBAL primitive.

See also:

MAX+PLUS II Messages

Message Format

Primitive Interconnections

Specifying Global Project Logic Synthesis Settings


Ignored CARRY [or CASCADE] primitives (total = <number>) as requested in logic option or logic synthesis style setting

CAUSE:	You specified the IGNORE setting for the Carry Chain or Cascade Chain in a logic option or logic synthesis style assignment. Therefore, the Compiler has ignored the specified number of CARRY or CASCADE primitives in the project.

ACTION:	No action is required. The CARRY or CASCADE primitives will be ignored. If you do not wish the Compiler to ignore these primitives, change the logic option or logic synthesis style setting.

See also:

Assigning a Logic Option

MAX+PLUS II Messages

Message Format

Specifying Global Project Logic Synthesis Settings


Input register <node name> and input pin <name> cannot both fan out

CAUSE:	The specified register assigned to an I/O cell register and the specified input pin that feeds this register both feed other logic in the device. This message may occur if you may have inadvertently placed a pin assignment on a register rather than on the input pin that feeds the register.

ACTION:	Delete the pin assignment or turn off the I/O Cell Register logic option on the register.

See also:

Assigning a Logic Option

Assigning a Pin, Location, or Chip

Deleting an Assignment

MAX+PLUS II Messages

Message Format


High fan-in [<text>] prevents node <name> from fitting into one logic cell

CAUSE:	You have compiled a project with  the SOFT Buffer Insertion logic option turned on. However, high fan-in prevents the specified node from fitting in one logic cell. This error may also occur if you have specified a percentage for the Logic Cells per Row option in the expanded Fitter Settings dialog box (Processing menu) and the specified percentage is too small for the project to fit into the selected device.

ACTION:	Turn on the SOFT Buffer Insertion logic option in the default logic synthesis style that is specified for the project as a whole. You can also specify a higher percentage for the Logic Cells per Row option in the expanded Fitter Settings dialog box.

See also:

Assigning a Logic Option

MAX+PLUS II Messages

Message Format


Logic too complex for <node name> -- <text>

CAUSE:	The logic that feeds the specified node(s) requires more expander product terms than are available in the actual device, or in some other way is too complex to be compiled.

ACTION:	If the message indicates that the node(s) require too many expanders, try to simplify the project’s logic by inserting LCELL or SOFT primitives. During project processing, these buffers may allow the Compiler to reduce the number of unique inputs that feed the node. It may also help to turn on the SOFT Buffer Insertion logic option in the default logic synthesis style that is specified for the project as a whole.

See also:

Defining a Logic Synthesis Style

Implementing LCELL & SOFT Primitives (AHDL)

Guiding the Partitioner

MAX+PLUS II Messages

Message Format

Specifying Global Project Logic Synthesis Settings


Multiple CARRY primitives feed <node name>
Multiple CARRY primitives feed <net ID>

CAUSE:	The specified node is fed by multiple CARRY primitives. This logic configuration is not allowed.

ACTION:	No action is required. The Logic Synthesizer either ignores the CARRY primitive or automatically inserts an LCELL primitive on the outputs of all but one of the CARRY primitives to allow them to feed the specified node only as non-CARRY inputs. However, if you wish to avoid receiving this warning message in the future, insert an LCELL primitive on the output of all but one of the CARRY primitives that feed the specified node.

See also:

MAX+PLUS II Messages

Message Format

Primitive Interconnections


Output register <node name> and TRI buffer <name> may not both fanout
Output register <node name> and TRI buffer <name> cannot both fan out

CAUSE:	A register that is assigned to an I/O cell register and its output pin use dual I/O feedback, i.e., both the register and the TRI buffer feed back into the device. This message may occur if you may have inadvertently placed a pin assignment on a register rather than on the pin that the register feeds. This message may also occur if you have assigned a register that is not a DFF to an I/O cell register: the device architecture is such that the I/O cells in the device can only implement D flipflops.

ACTION:	Delete the pin assignment or turn off the I/O Cell Register logic option on the register.

See also:

Assigning a Logic Option

Assigning a Pin, Location, or Chip

Deleting an Assignment

MAX+PLUS II Messages

Message Format


Output register <node name> cannot feed output pin <name> through an inverter

CAUSE:	The specified output register, which is assigned to an I/O cell register, feeds the specified output pin through an inverter (i.e., a NOT gate). This message may occur if you may have inadvertently placed a pin assignment on a register rather than on the pin that is fed by the register.

ACTION:	Delete the pin assignment or turn off the I/O Cell Register logic option on the register.

See also:

Assigning a Logic Option

Assigning a Pin, Location, or Chip

Deleting an Assignment

MAX+PLUS II Messages

Message Format


Node <name> is in a loop of CARRY or CASCADE primitives

CAUSE:	The specified node is part of a loop of CARRY or CASCADE primitives, a logic configuration that is not available in FLEX 8000 devices.

ACTION:	No action is required. The CARRY or CASCADE primitives will be ignored. Remove the specified CARRY or CASCADE primitive or insert an LCELL buffer to break the loop to avoid receiving the warning again.

See also:

MAX+PLUS II Messages

Message Format


Presettable registers will power up high

CAUSE:	Your project contains registers that are fed by a Preset signal but not by a Clear signal. These registers will power up high.

ACTION:	No action is required. However, if you want these registers to power up low, turn off the NOT Gate Push-Back logic option on the registers and recompile the project.

See also:

Assigning a Logic Option

Deleting an Assignment

MAX+PLUS II Messages

Message Format


Primitive <name> cannot be fed by CASCADE primitive <name> because it is already fed by CASCADE primitive <name>

CAUSE:	The specified primitive is fed by more than one or CASCADE primitive. A logic cell can only be fed by one CASCADE primitive.

ACTION:	No action is required. The CASCADE primitive will be ignored. Remove all but one of the CASCADE primitives to avoid receiving the warning again.

See also:

MAX+PLUS II Messages

Message Format


Primitive <name> cannot cascade into primitive <name> -- CASCADE primitive ignored

CAUSE:	The first primitive specified in the message feeds a CASCADE primitive, which in turn feeds the second primitive specified in the message. However, these two primitives have different types of logic. The De Morgan’s inversion theorem implementation of cascaded AND and OR gates requires all primitives in a cascaded chain to be of the same type, i.e., both must be AND gates or both must be OR gates. A cascaded AND gate cannot feed a cascaded OR gate, and vice-versa. (An inverted OR gate is treated as an AND gate and vice-versa. Logical equivalents of AND gates are BAND, BNAND, and NOR. Logical equivalents of OR gates are BOR, BNOR, and NAND.)

ACTION:	No action is required. The CASCADE primitive will be ignored. Delete the CASCADE primitive to avoid receiving the warning again.

See also:

MAX+PLUS II Messages

Message Format


Primitive <name> cannot feed CASCADE primitive <name>

CAUSE:	The specifed primitive feeds a CASCADE primitive, but it is not an AND or OR gate. CASCADE primitives can only be fed by AND and OR gates. (An inverted OR gate is treated as an AND gate and vice-versa. Logical equivalents of AND gates are BAND, BNAND, and NOR. Logical equivalents of OR gates are BOR, BNOR, and NAND.)

ACTION:	No action is required. The CASCADE primitive will be ignored. Change the logic or remove the CASCADE primitive to avoid receiving the warning again.

See also:

MAX+PLUS II Messages

Message Format


Some clearable/presettable registers will power up high

CAUSE:	Your project contains some register that are fed by a Preset signal but not by a Clear signal. These registers will power up active-high.

ACTION:	No action is required. However, if you want these registers to power up active-low, turn off the NOT Gate Push-Back logic option on the registers and recompile the project.

See also:

Assigning a Logic Option

Deleting an Assignment

MAX+PLUS II Messages

Message Format


The following messages must be re-checked after 6.0


Ignored <number> superfluous or non-implementable CARRY or CASCADE primitives

CAUSE:	You have entered CARRY or CASCADE primitives, either manually or through the instantiation of a macrofunction or LPM primitive, which were not implemented either because they could be ignored without affecting the design performance, or because they could not be implemented, such as a cascaded OR that feeds a cascaded AND.

ACTION:	No action is required. However, if you wish to avoid receiving this warming message in the future, remove the unnecessary CARRY or CASCADE primitives from your design. To prevent LPM primitives from instantiating CARRY primitives, set the CARRY parameter to OFF. You can remove some or all unnecessary CARRY primitives by setting the Carry Chain option to IGNORE in Logic Options (Assign menu).

See also:

Assigning a Logic Option

MAX+PLUS II Messages

Message Format


Ignored unnecessary memory segment <name> -- no project outputs depend on it

CAUSE:	The Logic Synthesizer has ignored a RAM segment because either there are no outputs connected to it or the RAM segment was not necessary to implement the design.

ACTION:	No action required. However, if you did not intend for this RAM segment to be ignored, you should redesign your project using smaller RAM (i.e., less width).

See also:

MAX+PLUS II Messages

Message Format


Memory <name> has no <input/output> Clock transition

CAUSE:	The specified memory block has an input or output Clock that is stuck at VCC or GND; therefore the memory will not function. This error may occur if logic synthesis reduced the logic feeding the Clock to VCC or GND, if you failed to connect the Clock to another signal, or if you explicitly connected the Clock to VCC or GND

ACTION:	Connect the Clock to logic that does not reduce to VCC or GND.

See also:

MAX+PLUS II Messages

Message Format


Memory segment <name> has no <input/output> Clock transition

CAUSE:	The specified memory segment has an input or output Clock that is stuck at VCC or GND; therefore that memory segment will not function, and the memory will not be implemented as a block. This error may occur if you have assigned Clocks to individual memory segments separately and one or more Clocks are connected to VCC or GND.

ACTION:	Use separate instances of the memory megafunction if separate Clocks are required.

See also:

MAX+PLUS II Messages

Message Format


 Can’t use port <name> with port <name>

CAUSE:	The two specified ports are both used in the parameterized module definition. However, these ports are mutually exclusive: both cannot appear in the definition of this type of parameterized module.

ACTION:	Delete one of the ports. In general, it is better to correct the source design file rather than the EDIF Input File generated from it. If you choose to edit the EDIF Input file, make sure that it conforms to the format for EDIF version 2 0 0 or 3 0 0. Refer to your EDIF or LPM manual for more information.

See also:

Library of Parameterized Modules Support

MAX+PLUS II Messages

Message Format


 Duplicate port name: <name>

CAUSE:	The specified parameterized module definition has multiple ports with the same name.

ACTION:	Remove duplicate ports from the parameterized module definition. In general, it is better to correct the source design file rather than the EDIF Input File generated from it. If you choose to edit the EDIF Input file, make sure that it conforms to the format for EDIF version 2 0 0 or 300. Refer to your EDIF or LPM manual for more information.

See also:

Library of Parameterized Modules Support

MAX+PLUS II Messages

Message Format


 Ignored illegal port <name>

CAUSE:	The specified port is not a legal port for the parameterized module, so the Compiler has ignored it.

ACTION:	No action is required. If you do not wish to receive this message during future compilations, delete the illegal port from the parameterized module definition. In general, it is better to correct the source design file rather than the EDIF Input File generated from it. If you choose to edit the EDIF Input file, make sure that it conforms to the format for EDIF version 2 0 0 or 3 0 0. Refer to your EDIF or LPM manual for more information.

See also:

Library of Parameterized Modules Support

MAX+PLUS II Messages

Message Format


 Ignored illegal property <name>

CAUSE:	The specified property is not a legal property for the parameterized module, so the Compiler has ignored it.

ACTION:	No action is required. If you do not wish to receive this message during future compilations, delete the illegal property from the parameterized module definition. In general, it is better to correct the source design file rather than the EDIF Input File generated from it. If you choose to edit the EDIF Input file, make sure that it conforms to the format for EDIF version 2 0 0 or 3 0 0. Refer to your EDIF or LPM manual for more information.

See also:

Library of Parameterized Modules Support

MAX+PLUS II Messages

Message Format


 Illegal numerical index <number> in port <name> -- min = 0, max = <number>

CAUSE:	The numerical index (i.e., the decimal number) in the specified port name of a parameterized module is outside of the legal range that is defined by the parameterized module type or its properties.

ACTION:	Use a numerical index within the specified range in the port name or change the parameterized module’s property. See the individual parameterized module descriptions listed in Library of Parameterized Modules Support for information on ports and properties. In general, it is better to correct the source design file rather than the EDIF Input File generated from it. If you choose to edit the EDIF Input file, make sure that it conforms to the format for EDIF version 2 0 0 or 3 0 0. Refer to your EDIF or LPM manual for more information.

See also:

MAX+PLUS II Messages

Message Format


 Illegal parameterized module type <name>

CAUSE:	The specified name is not a legal parameterized module type, i.e., the parameterized module definition has an illegal value for the LPM_TYPE property.

ACTION:	Edit the LPM_TYPE property value. See Library of Parameterized Modules Support for a list of legal, supported parameterized module types. In general, it is better to correct the source design file rather than the EDIF Input File generated from it. If you choose to edit the EDIF Input file, make sure that it conforms to the format for EDIF version 2 0 0 or 3 0 0. Refer to your EDIF or LPM manual for more information.

See also:

MAX+PLUS II Messages

Message Format


 Illegal port name format in <name>

CAUSE:	The specified port name of a parameterized module has an illegal format.

ACTION:	Edit the port name. Refer to your LPM manual for information on legal port name formats. In general, it is better to correct the source design file rather than the EDIF Input File generated from it. If you choose to edit the EDIF Input file, make sure that it conforms to the format for EDIF version 2 0 0 or 3 0 0. Refer to your EDIF manual for more information.

See also:

Library of Parameterized Modules Support

MAX+PLUS II Messages

Message Format


 Illegal value <value> for property <name> [-- max/min = <value>]

CAUSE:	The property of the specified parameterized module definition has an illegal string or integer value.

ACTION:	Change the string or integer value to one of the legal values for the specified property type. See the individual parameterized module descriptions listed in Library of Parameterized Modules Support for information on legal property values. In general, it is better to correct the source design file rather than the EDIF Input File generated from it. If you choose to edit the EDIF Input file, make sure that it conforms to the format for EDIF version 2 0 0 or 3 0 0. Refer to your EDIF or LPM manual for more information.

See also:

MAX+PLUS II Messages

Message Format


 Parameterized module of type <name> is not supported in MAX+PLUS II

CAUSE:	The specified parameterized module name is not supported in the current version of MAX+PLUS II.

ACTION:	Edit the LPM_TYPE property value to use a different parameterized module or implement the function in another way. See Library of Parameterized Modules Support for a list of supported parameterized module types. In general, it is better to correct the source design file rather than the EDIF Input File generated from it. If you choose to edit the EDIF Input file, make sure that it conforms to the format for EDIF version 2 0 0 or 3 0 0. Refer to your EDIF or LPM manual for more information.

See also:

MAX+PLUS II Messages

Message Format


 Parameterized module requires one or more of these ports: <names>

CAUSE:	The specified parameterized module requires at least one of the listed ports.

ACTION:	Add at least one of the listed ports to the definition of the parameterized module. In general, it is better to correct the source design file rather than the EDIF Input File generated from it. If you choose to edit the EDIF Input file, make sure that it conforms to the format for EDIF version 2 0 0 or 3 0 0. Refer to your EDIF or LPM manual for more information.

See also:

Library of Parameterized Modules Support

MAX+PLUS II Messages

Message Format


 Parameterized module requires <name> property to define port width

CAUSE:	The parameterized module requires the specified property, which determines the width of a port.

ACTION:	Add the property to the definition of the parameterized module. In general, it is better to correct the source design file rather than the EDIF Input File generated from it. If you choose to edit the EDIF Input file, make sure that it conforms to the format for EDIF version 2 0 0 or 3 0 0. Refer to your EDIF or LPM manual for more information.

See also:

Library of Parameterized Modules Support

MAX+PLUS II Messages

Message Format


 Parameterized module with value <value> for property <name> is not supported in MAX+PLUS II

CAUSE:	The specified value for the specified property of the parameterized module is not supported in the current version of MAX+PLUS II.

ACTION:	Use a different property value. See the individual parameterized module descriptions listed in Library of Parameterized Modules Support for information on supported parameterized module properties. In general, it is better to correct the source design file rather than the EDIF Input File generated from it. If you choose to edit the EDIF Input file, make sure that it conforms to the format for EDIF version 2 0 0 or 3 0 0. Refer to your EDIF or LPM manual for more information.

See also:

MAX+PLUS II Messages

Message Format


 Port <name> requires the use of port <name>, which is missing

CAUSE:	The two specified ports must both appear in the definition of the specified parameterized module, but only the first port name is present.

ACTION:	Use both or neither of the ports. In general, it is better to correct the source design file rather than the EDIF Input File generated from it. If you choose to edit the EDIF Input file, make sure that it conforms to the format for EDIF version 2 0 0 or 3 0 0. Refer to your EDIF or LPM manual for more information.

See also:

Library of Parameterized Modules Support

MAX+PLUS II Messages

Message Format


 Port <name> should have the direction <direction>

CAUSE:	The specified port of a parameterized module has the wrong direction. The message indicates the correct port direction.

ACTION:	Change the direction of the port name as specified in the message. In general, it is better to correct the source design file rather than the EDIF Input File generated from it. If you choose to edit the EDIF Input file, make sure that it conforms to the format for EDIF version 2 0 0 or 3 0 0. Refer to your EDIF or LPM manual for more information.

See also:

Library of Parameterized Modules Support

MAX+PLUS II Messages

Message Format


 Property <name> has multiple definitions -- only the first is accepted (others are ignored)

CAUSE:	The specified property is defined more than once for the same parameterized module.

ACTION:	No action is required. If you do not wish to receive this message during future compilations, define each property only once. In general, it is better to correct the source design file rather than the EDIF Input File generated from it. If you choose to edit the EDIF Input file, make sure that it conforms to the format for EDIF version 2 0 0 or 3 0 0. Refer to your EDIF or LPM manual for more information.

See also:

Library of Parameterized Modules Support

MAX+PLUS II Messages

Message Format


 Property <name> requires a[n] <text> value

CAUSE:	The specified parameterized module property requires a string (or integer) value, but has a non-string (or non-integer) value.

ACTION:	Edit the property value to contain a legal EDIF string (or integer) value. In general, it is better to correct the source design file rather than the EDIF Input File generated from it. If you choose to edit the EDIF Input file, make sure that it conforms to the format for EDIF version 2 0 0 or 3 0 0. Refer to your EDIF or LPM manual for more information.

See also:

Library of Parameterized Modules Support

MAX+PLUS II Messages

Message Format


 Too many/few numerical indexes in port -- expected <number>

CAUSE:	The parameterized module requires the specified number of numerical indexes (i.e., decimal numbers) in a port, but the port name contains either too few or too many numerical indexes.

ACTION:	Edit the port name to contain the correct number of numerical indexes. See the individual parameterized module descriptions listed in the Library of Parameterized Modules Support for information on supported index name format. In general, it is better to correct the source design file rather than the EDIF Input File generated from it. If you choose to edit the EDIF Input file, make sure that it conforms to the format for EDIF version 2 0 0 or 3 0 0. Refer to your EDIF or LPM manual for more information.

See also:

MAX+PLUS II Messages

Message Format


 Too many/few <text> ports (<number>) -- expected <number>

CAUSE:	The parameterized module has more or less than the expected number of ports, which are determined by a width property. If no width property is specified, the number of ports does not match the default width property value.

ACTION:	Add or delete the appropriate number of ports to match the width property value, or change the width property value to match the number of ports. See the individual parameterized module descriptions listed in the Library of Parameterized Modules Support for information on width properties. In general, it is better to correct the source design file rather than the EDIF Input File generated from it. If you choose to edit the EDIF Input file, make sure that it conforms to the format for EDIF version 2 0 0 or 3 0 0. Refer to your EDIF or LPM manual for more information.

See also:

MAX+PLUS II Messages

Message Format


-------------------------------BEGINNING OF NON-TRANSLATED TEXT-----------------------------------

This file documents AHDL Assert Statement messages that are embedded in files in the lpmlib directory and one file (expdff.tdf) in the macrolib directory.

-------------------------------END OF NON-TRANSLATED TEXT-----------------------------------


Can’t create synchronous RAM from a DFFE array unless all inputs are registered

CAUSE:	You have requested synchronous RAM functionality in your project, and the current device family can implement synchronous RAM only as an array of DFFE primitives. However, not all of the inputs to the array are registered, which is required to implement the requested functionality.

ACTION:	Register all inputs by assigning a value of ALL or DEFAULT to the REGISTERINPUTMODE parameter, or change the device family to a family that implements asynchronous RAM in a different way (e.g., FLEX 10K).

See also:

MAX+PLUS II Messages

Megafunctions/LPM

Message Format


Can’t use <port name> port if <port name> [or <port name>] port is used

CAUSE:	The specified port is used at the same time as one or more other ports which are mutually exclusive with it.

ACTION:	Delete one of the conflicting ports.

See also:

MAX+PLUS II Messages

Megafunctions/LPM

Message Format


Can’t use LPM_DIRECTION parameter if UPDOWN port is used

CAUSE:	In an instance of the lpm_counter megafunction, the LPM_DIRECTION parameter is used at the same time as the updown port, which is mutually exclusive with it.

ACTION:	Delete either the port or the parameter.

See also:

MAX+PLUS II Messages

Megafunctions/LPM

Message Format


Current device family does not support <text>
Current device family (<device family>) does not support <text>

CAUSE:	The architecture of the current device family does not support the feature (e.g., RAM, ROM, the Implement in EAB logic option) used in a megafunction in your project. In some cases, the message also describes an alternative implementation of the logic you requested.

ACTION:	If you did not intend to implement the project in the current device family, change the family or delete the megafunction that caused the error or warning. RAM, ROM, and the Implement in EAB logic option are available only in the FLEX 10K device family.

See also:

Assigning a Device

MAX+PLUS II Messages

Megafunctions/LPM

Message Format


Ignored FILE parameter -- the <family name> device family does not support RAM initialization

CAUSE:	The FILE parameter has been ignored because the current device family does not support RAM initialization via a MIF or Hex File.

ACTION:	Delete the parameter or change the device family to a family that implements asynchronous RAM in a different way (e.g., FLEX 10K).

See also:

MAX+PLUS II Messages

Megafunctions/LPM

Message Format


Ignored request for carry chain -- chain length setting is too low (<3) to create useful carry chains
Ignored request for carry chain -- chain length setting is too low (<4) to create useful carry chains

CAUSE:	The length specified for the Carry Chain logic option, which can also be used as a parameter, is too low to create useful carry chains, so the Compiler has ignored the logic option/parameter

ACTION:	Assign a higher value to the carry chain length, either as a parameter value or a logic option setting. During compilation, the Compiler searches for parameter values in parameter value search order.

See also:

Assigning a Logic Option???

Customizing a ???

MAX+PLUS II Messages

Megafunctions/LPM

Message Format


Illegal value for <parameter name> parameter (<value>) -- value must be <text>

CAUSE:	You assigned an illegal value to the specified parameter.

ACTION:	Change the parameter value to one of the specified legal values or allow it to default to the default value specified in the message. During compilation, the Compiler searches for parameter values in parameter value search order.

See also:

MAX+PLUS II Messages

Megafunctions/LPM

Message Format


Macrofunction <name> is not recommended for the <device family> device family -- use <text> instead

CAUSE:	The specified macrofunction is not optimized for the architecture of the current device family, so MAX+PLUS II is suggesting a better implementation of the logic you requested. For example, this message can occur if you are using an expdff macrofunction in project that is targeted for a MAX 7000 or MAX 9000 device.

ACTION:	To ensure efficient use of device resources, use the suggested logic function or change the device family used for the project.

See also:

Assigning a Device

MAX+PLUS II Messages

Message Format

Old-Style Macrofunctions


Too few <text> inputs for the requested <text>

CAUSE:	You have implemented too few inputs of the specified type to generate the megafunction outputs of the specified size.

ACTION:	Increase the number of inputs or decrease the number of outputs of the megafunction. For example, if there are too few select inputs to lpm_mux, you must increase the LPM_WIDTHS value to create more select inputs or decrease the LPM_SIZE value to reduce the multiplexer size. During compilation, the Compiler searches for parameter values in parameter value search order.

See also:

MAX+PLUS II Messages

Megafunctions/LPM

Message Format


Too many distance inputs for the requested I/O vector width (max. = CEIL(LOG2(LPM_WIDTH)))
Too many distance inputs for the requested I/O vector width of <number> (max. = CEIL(LOG2(LPM_WIDTH)))

CAUSE:	You have implemented too many distance inputs of the specified type to generate the lpm_clshift megafunction outputs of the specified size.

ACTION:	Either decrease the LPM_WIDTHDIST value to create fewer distance inputs or increase the LPM_WIDTH value to increase the I/O vector width (number of outputs). During compilation, the Compiler searches for parameter values in parameter value search order.

See also:

MAX+PLUS II Messages

Megafunctions/LPM

Message Format


Value of <parameter name> parameter must be greater than [or equal to] <value>

CAUSE:	The specified parameter must have a value greater than the specified <value> or greater than or equal to the specified <value>.

ACTION:	Assign a meaningful value to the parameter. For some parameters, a legal default value also exists. During compilation, the Compiler searches for parameter values in parameter value search order.

See also:

MAX+PLUS II Messages

Megafunctions/LPM

Message Format


Value of <parameter name> parameter must be greater than <value> if <text> is used [<text>]

CAUSE:	The specified parameter must have a value greater than the specified <value> if the specified feature or port is used in the megafunction.

ACTION:	Assign a meaningful value to the parameter or do not use the feature or port that requires the specified parameter value. During compilation, the Compiler searches for parameter values in parameter value search order.

See also:

MAX+PLUS II Messages

Megafunctions/LPM

Message Format


Value of LATENCY parameter (<number>) should be lower -- use  <number> for best performance/utilization

CAUSE:	You assigned non-optimal value to the specified parameter.

ACTION:	To increase the performance and/or utilization of the megafunction, assign a lower value to the parameter. During compilation, the Compiler searches for parameter values in parameter value search order.

See also:

MAX+PLUS II Messages

Megafunctions/LPM

Message Format


Value of LPM_MODULUS parameter (<number>) is too large for a <number>-bit counter

CAUSE:	The value of the LPM_MODULUS parameter is too large for the counter.

ACTION:	Eitehr make the counter wider or reduce the value of the parameter so that it is less than or equal to 2^LPM_WIDTH. During compilation, the Compiler searches for parameter values in parameter value search order.

See also:

MAX+PLUS II Messages

Megafunctions/LPM

Message Format


Value of LPM_WIDTHR parameter is too low --  <number> least significant bits of the result have been discarded

CAUSE:	The Compiler has discarded the specified number of bits from the result because the value of the lpm_mult megafunction’s LPM_WIDTHR parameter is too low.

ACTION:	Assign a higher value to the parameter. During compilation, the Compiler searches for parameter values in parameter value search order.

See also:

MAX+PLUS II Messages

Megafunctions/LPM

Message Format


Values of LPM_INDATA (<value>) and/or LPM_ADDRESS_CONTROL (<value>) parameters are not consistent with the use of the inclock po
Values of LPM_INDATA (<value>) and/or LPM_ADDRESS_CONTROL (<value>) parameters are not consistent with the use of the inclock port

CAUSE:	The LPM_INDATA and/or the LPM_ADDRESS_CONTROL parameters must have different values if you wish to use or not use the inclock port. This error can occur in the lpm_ram_io or lpm_ram_dq megafunction if neither the LPM_ADDRESS_CONTROL nor the LPM_INDATA parameter is assigned a value of REGISTERED but the inclock port is used.

ACTION:	If you wish to use the inclock port, change the value of at least one of the parameters to REGISTERED. If you do not wish to use the inclock port, make sure both parameters have a value of UNREGISTERED and do not use the inclock port.

See also:

MAX+PLUS II Messages

Megafunctions/LPM

Message Format


-------------------------------BEGINNING OF NON-TRANSLATED TEXT-----------------------------------

The following 3 messages should be listed twice each in messlist with the following text filled in for the first two variables:

LPM_AVALUE and aconst

LPM_SVALUE and sconst

-------------------------------END OF NON-TRANSLATED TEXT-----------------------------------


Ignored <parameter name> parameter because <port name> port is not used

CAUSE:	The specified parameter has been ignored because the specified port is not used in the megafunction.

ACTION:	Delete the parameter or use the port specified in the message.

See also:

MAX+PLUS II Messages

Megafunctions/LPM

Message Format


Value of <parameter name> parameter must be assigned if <port name> port is used

CAUSE:	The specified parameter must have a value because the specified port is used in the megafunction.

ACTION:	Assign a meaningful value to the parameter or delete the specified port. During compilation, the Compiler searches for parameter values in parameter value search order.

See also:

MAX+PLUS II Messages

Megafunctions/LPM

Message Format


Value of <parameter name> parameter must be less than 2^LPM_WIDTH if <port name> port is used -- using <value> instead

CAUSE:	The specified parameter must have a value less than the specified <value> if the specified port is used in the megafunction. Because you specified a higher value, the Compiler has defaulted to the value shown in the message.

ACTION:	Assign a value in the correct range to the parameter. During compilation, the Compiler searches for parameter values in parameter value search order.

See also:

MAX+PLUS II Messages

Megafunctions/LPM

Message Format


-------------------------------BEGINNING OF NON-TRANSLATED TEXT-----------------------------------

The following 2 messages should be listed twice each in messlist with the following text filled in for the first two variables:

LPM_NUMWORDS and LPM_WIDTHAD

NUMWORDS and AD_WIDTH

-------------------------------END OF NON-TRANSLATED TEXT-----------------------------------


Value of <parameter name> parameter requires <number> address lines, but <parameter name> value, which defines the number of add
Value of <parameter name> parameter requires <number> address lines, but <parameter name> value, which defines the number of address lines, is <number>

CAUSE:	The first specified parameter requires the specified number of address lines, but the value of the second parameter, which constrains the value of the first, is inapproriate. For example, the LPM_NUMWORDS parameter must have a value in the range 2^(LPM_WIDTHAD-1)+1 and 2^LPM_WIDTHAD.

ACTION:	Assign a value in the correct range to the first specified parameter or delete the assigned value to allow the parameter to assume a sensible default value. Or, change the value of the second specified parameter so that the value of the first parameter is sensible. During compilation, the Compiler searches for parameter values in parameter value search order.

See also:

MAX+PLUS II Messages

Megafunctions/LPM

Message Format


Value of <parameter name> parameter is not consistent with the use of the <port name> port
Value of <parameter name> parameter (<value>) is not consistent with the use of the <port name> port

CAUSE:	The specified parameter must have a different value if you wish to use or not use the specified port. For example, this error can occur in the lpm_ram_io megafunction if the LPM_OUTDATA parameter is assigned a value of REGISTERED but the outclock port is used.

ACTION:	Change the value of the specified parameter or delete the parameter so that it supports the use or non-use of the specified port, or change the USED/UNUSED status of the port to the opposite status and connect a signal to it, if necessary.

See also:

MAX+PLUS II Messages

Megafunctions/LPM

Message Format


--------------------BEGINNING OF NON-TRANSLATED TEXT-----------------------------------------------

This file contains "fixit" panels that are used as intermediate destinations for links that can't go directly to a panel because the link source cannot specify a particular application.

--------------------END OF NON-TRANSLATED TEXT-----------------------------------------------


Select the Appropriate Compiler Module

Choose one of the following module names for information:

EDIF Netlist Writer

Verilog Netlist Writer

VHDL Netlist Writer

See also:

Module Boxes


Select the Appropriate Cut Command

Choose one of the following applications for information on its Cut command:

Graphic & Symbol Editor

Text Editor

Waveform Editor

Floorplan Editor


Select the Appropriate Copy Command

Choose one of the following applications for information on its Copy command:

Graphic & Symbol Editor

Text Editor

Waveform Editor

Floorplan Editor


Select the Appropriate Paste Command

Choose one of the following applications for information on its Paste command:

Graphic & Symbol Editor

Text Editor

Waveform Editor

Floorplan Editor


Select the Appropriate Inputs/Outputs Command

Choose one of the following applications for information on its Inputs/Outputs command:

Programmer

Simulator


Select the Appropriate Print Command

Choose one of the following applications for information on its Print command:

Graphic Editor

Message Processor

Symbol Editor

Timing Analyzerr

Text Editor

Waveform Editor


Select the Appropriate Printing Procedure

Choose one of the following applications for information on printing:

Graphic Editor

Message Processor

Symbol Editor

Timing Analyzerr

Text Editor

Waveform Editor


Select the Appropriate Save As Command

Choose one of the following applications for information on its Save As command:

Graphic & Symbol Editor

Text Editor

Waveform Editor


Select the Appropriate Search & Replace Command

Choose one of the following applications for information on its Search & Replace command:

Graphic Editor

Symbol Editor

Text Editor

Waveform Editor


Select the Appropriate Find Text Command

Choose one of the following applications for information on its Find Text command:

Graphic Editor

Symbol Editor

Text Editor

Timing Analyzer

Waveform Editor

Floorplan Editor


Select the Appropriate Finding Text Procedure

Choose one of the following applications for information on how to find text:

Graphic & Symbol Editors

Text Editor

Timing Analyzer

Waveform Editor

Floorplan Editor


Select the Appropriate Finding & Replacing Text Procedure

Choose one of the following applications for information on how to find and replace text:

Graphic & Symbol Editors

Text Editor

Waveform Editor


Select the Appropriate Shortcuts

Choose one of the following applications for information on its shortcuts:

MAX+PLUS II Mananger

Hierarchy Display

Graphic & Symbol Editors

Text Editor

Waveform Editor

Floorplan Editor

Compiler

Simulator

Timing Analyzer

Programmer

Message Processor


Select the Appropriate Toolbar

Choose one of the following applications for information on its toolbar:

MAX+PLUS II Mananger

Hierarchy Display

Graphic & Symbol Editors

Text Editor

Waveform Editor

Floorplan Editor

Compiler

Simulator

Timing Analyzerr

Programmer

Message Processor


--------------------BEGINNING OF NON-TRANSLATED TEXT-----------------------------------------------

The following panel is used if you click on a dimmed button in MAX+PLUS II with the context-sensitive Help pointer. The popup that appears when you are in Help and click on a dimmed button in the segmented hypergraphic of the toolbar is similar, but is duplicated for each application. That panel is stored in the file duptool.mac/rtf.

note: in 4.0 the Save & Check button stuff is hosed for c-s help. For now, the MAX File Save & Check keyword cant go here, it has to go to the fs&c command panel instead

--------------------END OF NON-TRANSLATED TEXT-----------------------------------------------


Unavailable Toolbar Button

This button is not available (and is always dimmed) on the toolbar of the current application.


Third-Party Logic Function
Third-Party Logic Functions

The logic function that you selected has been created for mapping third-party functions to MAX+PLUS II logic functions.

Altera does not recommend using this function in projects created with MAX+PLUS II design entry methods. No help is currently available on this logic function.

For information on supported third-party interfaces, go to Third-Party Interfaces Help Contents.


***************************** BEGINNING OF NON-TRANSLATED TEXT ******************************

8/20: Took out glossary entry for function name (def_func_name) and put panel in hrkeys (in zold files folder).

******************************* END OF NON-TRANSLATED TEXT ************************************


Hierarchy Display Basic Tools
Basic Tools

Hierarchical Node & Symbol Names

Input & Output Files

Assignment & Configuration File (.acf)

ACF Format

MAX+PLUS II Initialization & System Files

maxplus2.idx file

maxplus2.ini File

Probe, Resource & Device Assignments

Clique Assignments

Connected Pins

Device Assignments

Guidelines for Timing Assignments

Logic Option Assignments

Pin, Location & Chip Assignments

Probe Assignments

Timing Assignments

Project & File Hierarchies

Branch Buttons

Connection Arrows

File Icons

Filenames

Filename Extensions

Hierarchy Tree

Status Bar & Toolbar

Status Bar

Toolbar


Hierarchical Node & Symbol Names Description (Hierarchy Display)
Hierarchical Node & Symbol Names

Uniquely identify each node or symbol in a lower-level file of a hierarchical project on the basis of its position in the hierarchy tree.

A hierarchical node name exists for every node and symbol in the design files and functional SNF for a project. When you create a timing SNF for a project, the Compiler’s Logic Synthesizer module eliminates unnecessary nodes and logic, so a timing SNF contains only the hierarchical node names that have "survived" logic synthesis.

Hierarchical node and symbol names are used to specify buried nodes in TDFs, ACFs, Vector Files, SCFs, and Command Files, and to find nodes and symbols in design files.

The hierarchical name consists of two parts: a hierarchy path and a node name. Show me

A hierarchy path traces the node name along a path through multiple levels of hierarchy. This path includes the <macrofunction name> followed by the <net ID> or <user function name> of each design file (macrofunction) that is higher up in the hierarchy. The <macrofunction name> and the <net ID> or <user function name> are repeated for each hierarchy level. A <macrofunction> name is the name of a macrofunction; a <user function name> is a user-defined name of a macrofunction instance in an ADHL TDF. The <net ID> or <user function name> distinguishes between multiple occurrences of the same item in the same level of hierarchy.

A node or symbol name is appended to the hierarchy path. For a symbol, this name consists of the symbol ID number (or symbol name plus ID number). For a node, this name is a user-assigned node name or a name that is based on the symbol ID number and pinstub name (called a port in a TDF) of the primitive or macrofunction that feeds the node.

A full hierarchical node name can be replaced with a single user-defined probe in a design file. Since a probe name is always unique, you can use the probe name instead of the node name wherever the node name is needed.

Various different hierarchical names may exists for the same source node that feeds a particular destination node. MAX+PLUS II accepts all different versions of hierarchical node names as synonyms for the source node. Example

If you assign a name to a node, the hierarchical path that leads to that name is part of the hierarchical node name.

See also:

Assigning a Probe

Hierarchical Node & Symbol Name Examples

Hierarchical Node & Symbol Name Syntax


Hierarchical Node & Symbol Name Syntax (Hierarchy Display)
Hierarchical Node & Symbol Name Syntax

A hierarchical node name has the following BNF syntax:

<hierarchical node name>::= 	[|] <probe name> [ .<pinstub name> ]

|	[|] { <macrofunction path>  }  <node name>

|	[|] { <macrofunction path>  }  <function> [ .<pinstub name> ]

<macrofunction path>::= 	[ <macrofunction> ] : <user function name> |

|	[ <macrofunction> ] : <net ID> |

<function>::= 	[ <macrofunction> ] : <user function name>

|	[ <macrofunction> ] : <net ID>

|	[ <primitive> ] : <net ID>

|	Separates different hierarchical levels in a hierarchical name. If a hierarchical node name begins with a vertical bar (|), it is an absolute path. The first | in a hierarchical name is not used if you wish to specify a relative path.

<probe name>	Indicates the name of the probe that you attach to the input or output pinstub (or port) of a primitive or macrofunction. If you use the probe name, you do not need to specify a hierarchical node name. The <probe name> consists of up to 32 name characters.

.<pinstub name>	Represents the pinstub of an input or output of a primitive or macrofunction. Pinstub names are visible in the symbol in the Symbol Editor (and sometimes the Graphic Editor) window; port names for primitives used in AHDL TDFs are given in the Function Prototype. Example

The <pinstub name> consists of up to 32 name characters. On a primitive with only one output, the output pinstub name is optional. Example

A macrofunction can also have a .<pinstub name> in a design file. However, a <probe name>.<pinstub name> for a macrofunction is always removed during compilation and does not appear in a functional, timing, or linked SNF.

<macrofunction path> 	Represents the name and symbol (net) ID number of a macrofunction file that is higher in the project hierarchy than the <node name> or <function>. The <macrofunction path> is repeated for each file in the hierarchy, from the top of the hierarchy down to the hierarchical node name. It does not appear for nodes in the current file. It is also not required to specify nodes and symbols in the top-level file of a hierarchy. The <macrofunction path> is always followed by <node name> or <function>[ .<pinstub name>].

<user function name>	Represents the user-defined name given to a particular instance of a macrofunction in the Variable Section of a TDF. The <user function name> consists of up to 32 name characters.

<macrofunction>	Represents the name of a macrofunction, which is a filename with up to eight name characters. No filename extension is included.

:<net ID>	Represents the symbol (net) ID number for the preceding macrofunction. The <net ID> consists of up to five digits.

<node name>	Represents the name of a node (in a TDF, a node declared in the Variable Section). The <node name> consists of up to 32 name characters. A tilde (~) at the beginning of a name indicates a pin or a buried node created by the Compiler.

<function>	Represents a <user function name>, <macrofunction>, or <primitive>, which is a filename with up to eight name characters. No filename extension is included. A <probe name> can also be substituted for a <function>.

See also:

Assigning a Probe

Hierarchical Node & Symbol Names

Hierarchical Node & Symbol Name Examples

Macrofunctions

Primitives

Recommended reading:

AB92 (Simulating Internal Nodes with MAX+PLUS II Software)


Example: hierarchical node & symbol names 1
The pinstub/port names of the DFF primitive are .Q, .D, .CLK, .CLRN, and .PRN.


Example: hierarchical node & symbol names 2
DFF is equivalent to DFF.Q.


Hierarchical Node & Symbol Name Examples (Hierarchy Display)
Hierarchical Node & Symbol Name Examples

The hierarchy of the chiptrip project, which is copied onto your hard disk during installation, is shown below:

The TICK_CNT function (i.e., the file tick_cnt.gdf) in the file chiptrip.gdf incorporates the 8COUNT function. The TICK_CNT function has a net ID number of 3; the 8COUNT function within the TICK_CNT function has a net ID number of 1. The output pinstubs of the 8COUNT function are called QA, QB, QC, QD, QE, QF, QG, QH, and COUT.

Example 1:

Within chiptrip.gdf, the hierarchical symbol name of the TICK_CNT macrofunction can take any of the following formats:

|tick_cnt:3	(absolute path notation)

tick_cnt:3	(relative path notation)

:3	(relative path notation)

The vertical bar (|) is optional because the TICK_CNT macrofunction appears in the top-level file of the project hierarchy. The name of the primitive or macrofunction is always optional because the net ID number uniquely identifies each instance of a function.

Example 2:

Within chiptrip.gdf, the hierarchical node names of the nodes connected to the outputs (pinstubs) of TICK_CNT:3 are:

|tick_cnt:3.ticket3

|tick_cnt:3.ticket2

|tick_cnt:3.ticket1

|tick_cnt:3.ticket0

Example 3:

The chiptrip.gdf file contains an instance of TICK_CNT, which in turn contains an instance of 8COUNT. The hierarchical node name of the COUT output port of the instance of 8COUNT that is used in TICK_CNT:3 can be expressed in one of the following forms:

|tick_cnt:3|8count:1.cout

|:3|8count:1.cout

|tick_cnt:3|:1.cout

:3|:1.cout

Note that the filename is always optional.

Example 4:

If you go down the project hierarchy into the file TICK_CNT:3, the hierarchical node name of the COUT output port of the 8COUNT function can be expressed relative to the current file or to the top-level file:

|tick_cnt:3|8count.cout	(absolute path notation)

8count:1.cout	(relative path notation)

Example 5:

If you were to change the implementation of TICK_CNT:3 from a GDF to an AHDL TDF, you could use the Variable Section of tick_cnt.tdf to create the instance of 8COUNT and to give it a user-defined function name. For example:

VARIABLE

   my8count : 8count ;

The hierarchical node name of the COUT output of the function can then be expressed as:

|tick_cnt:3|my8count.cout	(absolute path notation)

See also:

Hierarchical Node & Symbol Names Description

Recommended reading:

AB92 (Simulating Internal Nodes with MAX+PLUS II Software)


Branch Buttons (Hierarchy Display)
Branch Buttons

Hides lower-level branches of the hierarchy tree in the Hierarchy Display window.

Displays lower-level branches that were previously hidden in the Hierarchy Display window.

Branch buttons appear at the intersections of the hierarchy tree branches. Show me

You can redisplay all levels of the hierarchy with Show All Hierarchy Branches.

See also:

Showing & Hiding Hierarchy Branches


Connection Arrows (Hierarchy Display)
Connection Arrows

Connect a higher-level design file to a lower-level design file in a hierarchy tree. Show me

A hierarchy of design files can be displayed in either vertical or horizontal orientation. The top-level filename is on the top or left, and all instances of lower-level design files are shown below or to the right of it. Arrows lead from each higher-level design file to the design file(s) one level lower in the hierarchy. Branch buttons can be used to hide or redisplay each lower-level design file.

See also:

Changing the Hierarchy Orientation

Navigating the Hierarchy

Showing & Hiding Hierarchy Branches


File Icons (Hierarchy Display)
File Icons

Represents a design file or ancillary file in the current hierarchy tree. Show me

The file icon, along with the filename and the filename extension, represents a file in the current hierarchy opened with Open and shows which MAX+PLUS II editor can open the file:

File Icon:	Editor:

Represents a Graphic Editor file

Represents a Symbol Editor file

Represents a Text Editor file

Represents a Waveform Editor file

When you change the project name or open a file with Open, Retrieve, or Edit Symbol, icons for the files in the hierarchy are displayed in the hierarchy tree.

When you open a file in MAX+PLUS II, an icon appears in the hierarchy tree if it is not already displayed. The icons for ancillary files also appear at the top level of the hierarchy tree. A bar is displayed at the top of the icon when a file is open and disappears when it is closed. Show me

You can open one or more files in a hierarchy or bring open files to the front by selecting their icons or names and choosing Open Editor or by double-clicking Button 1 on a single icon or filename. You can also close one or more files by selecting their icons or filenames and choosing Close Editor.

If you create two or more design files with the same filename but with different filename extensions, you may need to change the filename extension and file icon shown in the hierarchy tree with Change File Type before you compile a project.

See also:

Changing the File Type

Closing a File

Creating a New File

Navigating the Hierarchy

Opening a File

Selecting a File Icon or Name

Showing & Hiding Hierarchy Branches


File Icon:	Editor:

Represents an open Graphic Editor file

Represents an open Symbol Editor file

Represents an open Text Editor file

Represents an open Waveform Editor file


Filenames (Hierarchy Display)
Filenames

Names of files in the current hierarchy tree. Show me

In the hierarchy of the current project, all filenames are the names of design files. In the hierarchy of a file opened with Open, Retrieve, or Edit Symbol, the filenames may be design file names, a single ancillary file name, or another non-MAX+PLUS II filename.

The filename, along with the file icon and the filename extension, represents a file that is part of the current hierarchy tree. All design file names except for the top-level file include a unique net ID number.

A filename that is followed by a ? (question mark) indicates that the file has not yet been incorporated into the HIF for the current hierarchy. Updating the hierarchy removes the ? from the filename.

Connection Arrows in a hierarchy tree connect design files to lower-level design files. Branch buttons that allow you to hide or redisplay hierarchy branches appear at the intersection of a higher-level design file and each of its lower-level design files.

You can open one or more files in a hierarchy or bring open files to the front by selecting their names or icons and choosing Open Editor or by double-clicking Button 1 on a single filename or icon. You can also close one or more files by selecting their filenames or icons and choosing Close Editor.

See also:

Closing a File

Navigating the Hierarchy

Opening a File

Selecting a File Icon or Name

Updating the Hierarchy


Filename Extensions (Hierarchy Display)
Filename Extensions

The three-letter extensions of filenames that appear under associated file icons.

The filename extension, along with the filename and the file icon, represents a file in the current hierarchy tree. A file icon and filename extension for one or more ancillary files are displayed next to the top-level design file in the hierarchy tree. In other levels of the hierarchy tree, ancillary file icons and filename extensions are displayed only if the files are open.

You can open files with the following extensions with MAX+PLUS II editors:

Editor:	Extensions:

Graphic Editor	.gdf, .sch

Symbol Editor	.sym

Text Editor	.acf, .aco, .adf, .cmd, .edc, .edf, .fit, .hst, .lmf, .log, .mtf, .plf, .rpt, .smf, .tao, .tbl, .tdf, .tdo, .tdx, .ttf, .vec, .vhd, .vho, .vo, .xnf, or any other ASCII text file

Waveform Editor	.scf, .wdf

A file icon with no extension indicates that you have entered a symbol in a GDF but there is no design file associated with it, i.e., the design file is missing.

1.	If you create two or more design files with the same filename but with different filename extensions, you may need to change the filename extension and file icon shown in the hierarchy tree with Change File Type before you compile a project. If the design file is at the top of a project hierarchy, you can specify the extension when you change the project name with Project Name.

2.	If you double-click Button 1 on the file icon with the .acf extension, it opens the ACF in a Text Editor window. You must choose the Floorplan Editor if you wish to edit ACF assignments in the Floorplan Editor.

See also:

Changing the File Type

Changing the Project Name

Opening a File


Hierarchy Tree (Hierarchy Display)
Hierarchy Tree

The representation of design files and/or ancillary files in the current hierarchy. Show me

The hierarchy tree represents all files associated with the current hierarchy. The current hierarchy can be that of the current project, or a separate hierarchy associated with a file that has been opened with the Open or Retrieve command. Choosing Edit Symbol from a lower-level file in any hierarchy also opens a separate hierarchy tree.

The hierarchy tree consists of filenames, file icons, filename extensions, branch buttons and connection arrows.


Hierarchy Display Table of Contents
Hierarchy Display Help Contents

Introduction

Basic Tools

Commands

Procedures

Golden Rules

Shortcuts

Messages


Hierarchy Display--Context-Sensitive Help
Hierarchy Display Context-Sensitive Help

Context-sensitive help is available for all Hierarchy Display commands, dialog boxes, and messages, and the following basic tools:

Branch Buttons

File Icons

Filename Extensions

Filenames

Status Bar

Toolbar

For information on other basic tools, see Hierarchy Display Basic Tools.

See also:

Getting Context-Sensitive Help


Hierarchy Display Introduction
Introduction

The MAX+PLUS II Hierarchy Display shows the current design hierarchy and allows you to open and close files in the hierarchy. Show me

How Does the Hierarchy Display Work?

The Hierarchy Display shows a hierarchy tree that represents the current hierarchy. The current hierarchy is either the hierarchy of the current project or the hierarchy of a design file that has been opened with the Open command (File menu). The hierarchy tree branches show a filename and file icon for each subdesign in the hierarchy. The Hierarchy Display also shows ancillary files associated with the current hierarchy.

The Hierarchy Display allows you to easily traverse the hierarchy of a design, automatically opening the appropriate editor for each subdesign or ancillary file. A bar over the file icon indicates that the file is currently open.

To get a better perspective on your project, you can zoom in and out to different display scales or switch between vertical or horizontal orientation. You can also hide a subdesign branch from view or redisplay branches that were previously hidden. In addition, you can select a design file icon and locate all logic functions within that design file in the Floorplan Editor.

Where to Start

Altera offers a variety of information to help you use MAX+PLUS II and the Hierarchy Display.

On-Line Help

On-line help supplies complete reference and how-to information on using the Hierarchy Display.

Hierarchy Display Help Contents provides access to all on-line Hierarchy Display Help.

Hierarchy Display Golden Rules summarizes essential rules and guidelines for using MAX+PLUS II and the Hierarchy Display.

See also:

How to Use MAX+PLUS II Help


Hierarchy Display Golden Rules
Golden Rules

The following golden rules will help you use MAX+PLUS II and the Hierarchy Display effectively.

When you start work on a new design file, name it as the current project with Project Name or Project Set Project to Current File (File menu) right away so that you can compile it easily. You can always change the name later.

Use the built-in hierarchy traversal features in MAX+PLUS II to move between design files for the current hierarchy. To open a lower-level file in a hierarchy, open the top-level file and then use the Hierarchy Display window or Hierarchy Down (File menu) to open the lower-level files. If you choose Open or Retrieve (File menu) to open a lower-level file, it is considered to be the top of a different hierarchy tree, and resource, device, and probe assignments that you enter are saved only for that hierarchy, not for the project.

When you create an ancillary file for a project, the icon for the file will appear in the Hierarchy Display if you use the same filename as the project.

Don’t edit any MAX+PLUS II system files, including HIFs, maxplus2.idx, or the maxplus2.ini file.

Use the Save As command (File menu) if you wish to rename a design file or an ancillary file. Don’t rename design files from outside of the MAX+PLUS II system (e.g., from DOS or with the Windows File Manager).

When you have completed a project, use Project Archive (File menu) to ensure that you save a complete copy of all project files that will not be affected by future edits or deletions.


Hierarchy Display Shortcuts
 Shortcuts

The following list provides shortcuts for Hierarchy Display commands:

Command:	Shortcut:

Context-Sensitive Help	Shift+F1 or

Cascade	Shift+F5

Close	Alt+F4

Compiler

Exit MAX+PLUS II	Alt+F4 or double-click Button 1 on the Application Control Menu box

Find Node in Floorplan

Fit in Window	Ctrl+W or

Floorplan Editor

Hierarchy Display

Hierarchy Project Top	Ctrl+T or

New

Next	Ctrl+F6

Normal Size	Ctrl+1

Open	Ctrl+O or

Open Editor	Double-click Button 1 on a file icon or filename

Print 	Ctrl+P or

Programmer

Project Name	Ctrl+J or

Project Save & Check	Ctrl+??? or

Project Save & Compile	Ctrl+L or

Project Save & Simulate	Ctrl+Shift+L or

Project Set Project to Current File	??? or

Show All Hierarchy Branches

Simulator

Switch To	Ctrl+Esc

Timing Analyzer

Tile Horizontally	Shift+F4

Zoom In	Ctrl+Space or ???

Zoom Out	Ctrl+Shift+Space or ???

See also:

Selecting Text


Hierarchy Display Procedures
Procedures

Assignments & Compiler Configuration Settings

Assigning a Clique

Assigning a Device

Assigning a Pin, Location, or Chip

Assigning a Probe

Assigning an Individual Logic Option or Synthesis Style

Assigning Connected Pins

Assigning Individual Timing Requirements

Bank-Annotating Assignments for a Project

Clearing Assignments for a Project

Converting an Obsolete Assignment Format

Copying a Resource Assignment

Defining a Logic Synthesis Style

Deleting an Assignment

Guidelines for Working with Assignments

Ignoring Project Assignments during Compilation

Logic Synthesis Style & Logic Option Rules

Searching the Node Database

Specifying Devices for Automatic Device Selection

Specifying Global Project FLEX 8000 Device & Pin Options

Specifying Global Project Logic Synthesis Settings

Specifying Global Project Security Bit & Reserved Resource Settings

Specifying Global Project Timing Requirements

Specifying Individual Device Security & Turbo Bit Options

Specifying Individual FLEX 8000 Device & Pin Options

File Management

Closing a File

Creating a New File

Opening a File

Hierarchy

Changing the File Type

Changing the Hierarchy Orientation

Fitting the Hierarchy into the Window

Navigating the Hierarchy

Printing the Hierarchy

Selecting a File Icon or Name

Selecting a Hierarchy to View

Showing & Hiding Hierarchy Branches

Turning Compact Display On or Off

Updating the Hierarchy

Zooming In & Out

MAX+PLUS II Management

Changing Colors in MAX+PLUS II

Closing a MAX+PLUS II Application

Creating & Using a Local Copy of the maxplus2.ini File

Entering an Authorization Code

Exiting from MAX+PLUS II

Specifying a User Library

Starting MAX+PLUS II Applications

Switching Between MAX+PLUS II Applications

Messages

Getting Help on a Message

Locating the Source of a Message

Nodes & Symbols

Finding Nodes & Pins in the Floorplan Editor

Project Management

Archiving a Project

Changing the Project Name

Compiling a Project

Status Bar & Toolbar

Showing the Toolbar

Showing the Status Bar

Text

Selecting Text


Changing the File Type (Hierarchy Display)
Changing the File Type

If you change the type of a design file in the current hierarchy (for example, if you decide to implement part of the project in a GDF instead of a TDF), the Hierarchy Display must be updated to show the new file type before you compile the project. The first file icon shown after a filename in the Hierarchy Display window represents the type of design file. You only need to update the Hierarchy Display if both the old and new versions of the file have the same filename. Until you change the file type, the filename extension and file icon continue to show the older version of the file.

If you have changed the top-level design file in the current hierarchy tree to use a different type of design file, you can simply specify the new file as the project name, as described in Changing the Project Name.

To change the file type for a lower-level file in the current hierarchy tree:

1.	Select the filename or file icon that represents the file.

2.	Choose Change File Type (File menu). The Change File Type dialog box is displayed.

3.	Select the new file type in the File Type box.

4.	Choose OK. The filename extension and file icon are updated in the Hierarchy Display to reflect the new file type.

5.	Recompile the project with the Compiler’s Total Recompile command (Processing menu) turned on.

See also:

Selecting a File Icon or Name

Totally Recompiling a Project


Changing the Hierarchy Orientation (Hierarchy Display)
Changing the Hierarchy Orientation

You can change the orientation of the hierarchy tree to either vertical or horizontal (default). In vertical orientation, filenames are listed from top to bottom. In horizontal orientation, filenames are listed from left to right.

To change the hierarchy orientation:

Choose Orientation Vertical or Orientation Horizontal (Options menu).


Fitting the Hierarchy into the Window (Hierarchy Display)
Fitting the Hierarchy into the Window

You can show an entire hierarchy tree in the Hierarchy Display window.

To view the entire hierarchy tree:

Choose Fit in Window (View menu) or use a shortcut.

To set the view so that the complete hierarchy tree is automatically displayed at all times:

Choose Auto Fit in Window (View menu).

See also:

Showing & Hiding Hierarchy Branches

Turning Compact Display On & Off

Zooming In & Out


Printing the Hierarchy (Hierarchy Display)
Printing the Hierarchy

You can print the hierarchy tree at the size currently shown in the Hierarchy Display window.

To print the hierarchy tree:

1.	Open the Print dialog box by choosing Print (File menu) or using a shortcut.

2.	Enter the number of copies to print in the Copies box.

3.	If you wish to print the MAX+PLUS II version number, project name, date, and page number at the top of each page, turn on the Print Page Headers option.

4.	Choose OK.

To change the printer and printer options:

1.	Choose Printer Setup (File menu). The Printer Setup dialog box is displayed.

2.	Select the correct printer.

3.	If you wish to change any of your printer options, choose Setup to open a dialog box that controls options for your printer. Make any necessary changes, and then choose OK to return to the Printer Setup dialog box.

4.	Choose OK in the Printer Setup dialog box.


Selecting a File Icon or Name (Hierarchy Display)
Selecting a File Icon or Name

In the Hierarchy Display, two types of selections are available: area selection and object-by-object selection. File icons and filenames are selected with Button 1 and additional keys.

To select a single object:

Click Button 1 on the object.

To select an area, use one of the following mouse/key combinations:

Mouse/Key:	Action:

Press, Drag, Release	Selects all objects from the point where Button 1 is pressed to the point where it is released. This type of selection works only if you start by pressing Button 1 over a blank space in the window.

Click, Move, Shift+Click	Selects all objects between the first click and the Shift+Click. This type of selection works only if you start by pressing Button 1 over a blank space in the window.???spr30310

The area is denoted by the area marquee that surrounds it as you drag the mouse. The area marquee is not visible after objects are selected. Only objects that are fully within the marquee are selected.

To select more than one discontinuous object, use one of the following mouse/key combinations:

Mouse/Key:	Action:

Shift+Click	Selects a single object and adds it to a previous selection.

Shift+Press, Drag, Release	Selects all objects from the point where Button 1 is pressed to the point where it is released, adding the objects to a previous selection. This type of selection works only if you start by pressing Button 1 over a blank space in the window.

You can mix area and object-by-object selection. However, adding additional objects to an area selection will change it to a object-by-object selection.


Selecting a Hierarchy to View (Hierarchy Display)
Selecting a Hierarchy to View

You can view the hierarchy of the current project or of any file opened with Open, Retrieve, or Edit Symbol (File menu) in the Hierarchy Display window. You can also switch between different hierarchies of design files by displaying a different hierarchy.

To select a hierarchy to view:

1.	Choose Select Hierarchy (File menu). The Select Hierarchy dialog box is displayed.

2.	Select the name of the top-level file in the hierarchy from the Files box.

3.	Choose OK.

The selected hierarchy is displayed.


Showing & Hiding Hierarchy Branches (Hierarchy Display)
Showing & Hiding Hierarchy Branches

To hide a hierarchy branch in the Hierarchy Display window:

Click Button 1 on the branch button that is associated with (i.e., either to the left of or above) the lower-level branch you wish to hide. When the lower-level branches are not hidden, the branch button has a minus sign (-).

All the lower-level hierarchy branches associated with the branch button are hidden from view. The branch button has a plus sign (+) when its lower-level branches are hidden.

To show a hierarchy branch that was previously hidden:

Click Button 1 on a branch button with a plus sign (+).

All lower-level hierarchy branches associated with the branch button are redisplayed.

To show all hierarchy branches:

Choose Show All Hierarchy Branches (Options menu) or use a shortcut. ???no shortcut exists yet

The entire hierarchy tree is displayed in the Hierarchy Display window.

See also:

Fitting the Hierarchy into the Window

Turning Compact Display On or Off


Turning Compact Display On or Off (Hierarchy Display)
Turning Compact Display On or Off

When Compact Display (Options menu).is turned on, the items in the Hierarchy Display window are arranged so that they fit closer together and show a larger portion of the hierarchy tree without changing the display scale.

To turn the compact display feature on or off:

Choose Compact Display.

See also:

Changing the Hierarchy Orientation


Zooming In & Out (Hierarchy Display)
Zooming In & Out

To change the view of the hierarchy tree, choose one of the following View menu commands:

Command:	Action:

Fit in Window	Changes the display scale to fit the entire hierarchy tree in the current window. Shortcut

Zoom In	Increases the scale of the hierarchy tree, showing a smaller portion of the tree. Shortcut

Zoom Out	Reduces the scale of the hierarchy tree, showing a larger portion of the tree. Shortcut

Normal Size	Zooms in or out to display the hierarchy tree at the normal (default) size. Shortcut

Auto Fit in Window	Forces the Hierarchy Display to automatically display the entire hierarchy tree at all times. This command remains on until you turn it off.

See also:

Fitting the Hierarchy into the Window

Turning Compact Display On or Off

Showing & Hiding Hierarchy Branches


******************** BEGINNING OF NON-TRANSLATED TEXT *************************************

The following HRWMSGS.MSG messages are not documented in this file:

FHRW_FET_BAD_FILE_PATH	edifmess.mac (note: make note in hrwmsgs)

FHRW_FET_CANT_OPEN_FILE	glmess.mac (note: make note in hrwmsgs)

FHRW_FET_CANT_WRITE_FILE	glmess.mac (note: make note in hrwmsgs)

FHRW_FET_OUT_OF_MEMORY	glmess.mac (note: make note in hrwmsgs)

FHRW_FET_PGM_LIMIT_REACHED	glmess.mac (note: make note in hrwmsgs)

SHRW_FILE_DOES_NOT_EXIST	glmess.mac

SHRW_CANT_FIND_NODE	EDMESS.MAC

SHRW_WT_CANT_OPEN_FILE	glmess.mac

SHRW_WT_HIF_CORRUPT	glmess

Messages from other modules that are documented in this file:

PGE_SAVE_EDITS	ge_msgs.msg (genlib)

EG2C_ILL_MACROFUNC_NAME	gdfmess.mac

**************************** END OF NON-TRANSLATED TEXT **************************************


Append a period (.) and a pinstub name to the node name to specify the location of the probe

CAUSE:	You chose the Probe command (Assign menu) and have specified a probe without specifying a pinstub in the node name.

ACTION:	Append a period (.) and a pinstub name to the node name to specify the location of the probe. If you do not specify a pinstub name, MAX+PLUS II automatically selects a pinstub name and appends it to the node name.

See also:

Assigning a Probe

MAX+PLUS II Messages

Message Format


Can’t assign node to two pins on the same chip -- specify the name of another chip

CAUSE:	You tried to assign a node to two pins on the same chip in the Pin/Location/Chip (Assign menu) dialog box.

ACTION:	Specify the name of another chip or choose Cancel to cancel the command.

See also:

Assigning a Pin, Location, or Chip

MAX+PLUS II Messages

Message Format


Can't enter <name> <text> -- already exists
Can’t enter <name> <text> -- already exists

CAUSE:	You are trying to enter a probe, clique, connected pin, logic option, timing assignment, chip, or device that already exists.

ACTION:	No action is required.

See also:

MAX+PLUS II Messages

Message Format


Can't enter <text> -- name <name> has already been used
Can’t enter <text> -- name <name> has already been used

CAUSE:	You are trying to define a probe or assignment name that is already in use in this design file.

ACTION:	Enter a unique probe or assignment name with up to 32 name characters.

See also:

MAX+PLUS II Messages

Message Format


Can't enter macrofunction--it would make the hierarchy tree recursive
Can’t enter macrofunction--it would make the hierarchy tree recursive

CAUSE:	You tried to enter a macrofunction symbol that represents the current design file or a higher-level file in the current hierarchy. This type of recursive logic definition is not allowed in MAX+PLUS II. This message may also occur if you open a design file after creating recursive logic in another file within the hierarchy.

ACTION:	Use a different macrofunction.

See also:

MAX+PLUS II Messages

Message Format


Can't find <text> <name>
Can’t find <text> <name>

CAUSE:	You tried to delete a probe, clique, connected pin, logic option, timing assignment, chip, or device assignment that hasn’t been assigned yet.

ACTION:	No action is required.

See also:

MAX+PLUS II Messages

Message Format


Can't rename chip(s) in ACF for this hierarchy tree to agree with the new filename
Can’t rename chip(s) in ACF for this hierarchy tree to agree with the new filename

CAUSE:	You saved a top-level design file to a new filename. As part of this process, MAX+PLUS II automatically saves a copy of the ACF for the hierarchy tree to the new name, and attempts to update any chip names in the ACF that are based on the old filename to names that are based on the new filename. However, in this case, MAX+PLUS II could not change the chip names because one of the new chip names is the same as an old chip name or the new filename. Therefore, none of the old chip names in the ACF have been updated. This message could occur, for example, if you saved a top-level design file called multiple.gdf as multiple1.gdf, but the ACF for multiple.gdf already had chips called multiple1 and multiple2.

ACTION:	Manually edit the Physical Chip Assignments Section(s) of the ACF ACF to change the chip name(s). It is especially important to rename the chips if you have not saved the new file to a different directory: when you compile the new project, you may overwrite programming files that are based on the chip names in the ACF.

See also:

Assigning a Pin, Location, or Chip

MAX+PLUS II Messages

Message Format


Device assignment(s) in Chip to Device dialog box have a different device family.....
Device assignment(s) in Device dialog box have a different device family. Update these assignments before compiling the project.

CAUSE:	You have changed the device family for the project with the Device command Assign menu), but one or more chips in the project are assigned to a device in a different device family. All device assignments must have the same family as the current family when you compile the project; otherwise errors will occur.

ACTION:	Change all conflicting device assignments in the Device dialog box before compiling the project.

See also:

Assigning a Device

MAX+PLUS II Messages

Message Format


Illegal macrofunction name: [macrofunction]
Illegal macrofunction name: <macrofunction>

CAUSE:	You have opened or compiled a project with a corrupted HIF with an illegal macrofunction name, or you have opened or compiled a MAX+PLUS DOS design file with a macrofunction name that is not supported by MAX+PLUS II, or you have compiled an EDIF Input File that contains an EDIF cell name that is illegal in MAX+PLUS II. .

ACTION:	Delete the old macrofunction name or symbol and type a new macrofunction name, using only legal name characters. If this message occurs during compilation, you must correct the design file, then recompile the project.

If the error occurs in an EDIF Input File, it is generally better to correct only the source design file rather than the EDIF Input File. If you really want to edit the EDIF Input File, make sure that the EDIF cell name contains no more than 32 name characters. If necessary, consult your EDIF manual.

See also:

MAX+PLUS II Messages

Message Format


OK to change project device family to <name> ?

CAUSE:	You have changed the device family and device assignment in the Device dialog box (Assign menu), and the device family and assignment specified are different from the family currently specified for the project.

ACTION:	Choose OK to change the device family for the project to the specified device famliy name or choose Cancel to cancel the command.

See also:

Assigning a Device

MAX+PLUS II Messages

Message Format


[No valid assignment remains for selected node(s).] OK to delete assignment(s) for current selected node(s)?

CAUSE:	You selected one or more nodes, symbols, and or probes, chose an Assign menu command, deleted text from one or more fields in the dialog box , and chose OK. Since the existing assignment(s) for the selected item(s) are no longer complete, MAX+PLUSII is asking whether you wish to delete the assignment(s).

ACTION:	Choose OK to delete assignment(s) or Cancel to return to the dialog box.

See also:

Deleting an Assignment

MAX+PLUS II Messages

Message Format


Only one probe is allowed per pinstub -- use the Change button to change the probe name

CAUSE:	You tried to assign more than one probe to a pinstub in the Probe dialog box (Assign menu). Only one probe is allowed per pinstub.

ACTION:	Enter a different probe name or choose Cancel to cancel the command.

See also:

Assigning a Probe

MAX+PLUS II Messages

Message Format


Probe <probe name> already exists -- <text>
Probe <probe name> already exists -- enter a different probe name

CAUSE:	The specified probe name has been used elsewhere in the project or in the design file.

ACTION:	Use a unique name with up to 32 name characters for each probe in the project. You can move a probe in the Graphic Editor by dragging it to a different pinstub and/or symbol.

See also:

Assigning a Probe

Deleting an Assignment

MAX+PLUS II Messages

Message Format

Selecting a Probe or Resource Assignment


Hierarchy Display Commands
Commands

For Help, choose a command name or dialog box name from the following list. Menu names are not included on the list.

About MAX+PLUS II	Message Processor

Advanced Options	Messages

AHDL	Minimize

Archive	More Windows

Arrange Icons	Move

Authorization Code	Name

Auto Device Selection	New

Auto Fit in Window	New Features in This Release

Back-Annotate Project	New Window

Basic Tools	Next

Cascade	Normal Size

Change File Type	Open

Classic & MAX Global Project Device Options	Open Editor

Classic & MAX Individual Device Options	Orientation Horizontal

Clear Project Assignments	Orientation Vertical

Clique	Pin/Location/Chip

Close ({bmc app_menu.bmp} and {bmc doc_menu.bmp} menus)	Primitives

Close Editor	Print

Color Palette	Printer Setup

Commands	Probe

Compact Display	Procedures

Compiler	Programmer

Connected Pins	Project 1, 2, 3, 4...

Convert Obsolete Assignment Format	Project Archive

Define Synthesis Style	Project Name

Device	Project Save & Check

Devices & Adapters	Project Save & Compile

Exit MAX+PLUS II	Project Save & Simulate

Find Node in Floorplan	Project Save, Compile & Simulate

Fit in Window	Project Set Project to Current File

FLEX 10K Global Project Device Options	READ.ME

FLEX 10K Individual Device Options	Rename Chip

FLEX 8000 Global Project Device Options	Restore

FLEX 8000 Individual Device Options	Save & Check

Floorplan Editor	Save & Compile

Global Project Device Options	Save & Simulate

Global Project Logic Synthesis 	Save Style As

Global Project Timing Requirements	Save, Compile & Simulate

Glossary	Search for Help on

Golden Rules	Search Node Database

Graphic Editor	Select Hierarchy

Hierarchy Display	Set Project to Current File

Hierarchy Display Help Basic Tools	Shortcuts

Hierarchy Display Help Commands	Show All Hierarchy Branches

Hierarchy Display Help Golden Rules	Show Status Bar

Hierarchy Display Help Introduction	Show Toolbar

Hierarchy Display Help Procedures	Simulator

Hierarchy Display Help Shortcuts	Size

Hierarchy Display Help Table of Contents	Switch To

Hierarchy Project Top	Symbol Editor

Horizontal	Table of Contents

How to Use Help	Text Editor

How to Use MAX+PLUS II Help	Tile

Ignore Project Assignments	Timing Analyzer

Individual Logic Options	Timing Requirements

Introduction	User Libraries

Logic Options	Vertical

Macrofunctions	VHDL

MAX 7000S Global Project Device Options	Waveform Editor

MAX 7000S Individual Device Options	Zoom In

MAX+PLUS II Table of Contents	Zoom Out

Maximize


test shortcut !!!
Test shortcut topic

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Select Hierarchy Command (Hierarchy Display)
Select Hierarchy Command (File Menu)

Selects a hierarchy of files to display in the Hierarchy Display window.

Click Button 1 on any item in this dialog box for information on that item:

See also:

Selecting a Hierarchy to View


Files

Specifies the hierarchy of files to display. The current hierarchy is selected as the default.

The Files box lists available hierarchy names, including the current project and the names of all hierarchies of files opened with the Open, Retrieve, and Edit Symbol commands (File menu) during the current MAX+PLUS II session (if any).


Select Hierarchy dialog box

Click Button 1 on any item in this dialog box for information on that item:


Open Editor Command (Hierarchy Display)
Open Editor Command (File Menu)

Shortcut

Opens one or more selected files in the Hierarchy Display with the appropriate editor (Graphic, Symbol, Text, or Waveform Editor).

You can open one or more files in the current hierarchy tree by selecting one or more filenames or file icons and choosing Open Editor. If the file is already open, this command brings the file to the front.

When you open a file in MAX+PLUS II, an icon for it appears in the hierarchy tree if it is not already shown, and a bar is displayed at the top of the icon.

See also:

Navigating the Hierarchy

Opening a File

Selecting a File Icon or Name


Open Editor Command Shortcuts

Button 1 	Double-click Button 1 on a filename or file icon.


Close Editor Command (Hierarchy Display)
Close Editor Command (File Menu)

Closes one or more selected files in the Hierarchy Display.

You can close one or more files in the current hierarchy tree by selecting one or more filenames (for design files) or file icons (for design files and/or ancillary files) and choosing Close Editor.

See also:

Closing a File

Selecting a File Icon or Name


Change File Type Command (Hierarchy Display)
Change File Type Command (File Menu)

Changes the type of a selected design file (e.g., from TDF to GDF) in the current hierarchy tree.

Click Button 1 on any item in this dialog box for information on that item:

The first file icon shown after a filename in the Hierarchy Display window represents the type of design file. Change File Type is required if you change the type of design file that you use to implement part of the logic in a project and if both the old and new versions of the file have the same filename. Until you change the file type, the filename extension and file icon continue to show the older version of the file. You must update the file type before compiling the project before the Compiler will use the newer version of the file.

A question mark may be displayed after the filename if no HIF exists for the new file. Therefore, when you recompile the project, be sure to turn on the Compiler’s Total Recompile (Processing menu) to create new HIFs.

Change File Type is available only if you have selected a single icon that represents a design file. It is not available if the selected file is open.

See also:

Changing the File Type

Selecting a File Icon or Name

Totally Recompiling a Project


File Name

Displays the name of the file that is currently selected in the Hierarchy Display window.


File Type

Lists the different types of design files with the same filename as the selected File Name. The current type of the selected file is highlighted.

Select a different design file type in the File Type box to incorporate the file of that type into the current hierarchy. The filename extension and file icon will change to match the specified file type.


Change File Type dialog Box (Hierarchy Display)
Change File Type dialog box

Click Button 1 on any item in this dialog box for information on that item:


Print Command (Hierarchy Display)
Print Command (File Menu)

Shortcuts

Prints the hierarchy tree at the size currently shown in the Hierarchy Display window.

Click Button 1 on any item in this dialog box for information on that item:

MAX+PLUS II prints the file according to the settings for the current printer, which is specified with Printer Setup.

See also:

Printing the Hierarchy


Print dialog Box (Hierarchy Display)
Print dialog box

Click Button 1 on any item in this dialog box for information on that item:


View Commands (Hierarchy Display)
View Commands (View Menu)

Change the display scale of the hierarchy tree in the current window.

Command:	Action:

Fit in Window	Changes the display scale to fit the entire hierarchy tree in the current window. Shortcuts

Zoom In	Increases the scale of the hierarchy tree, showing a smaller portion of the tree. Shortcuts

Zoom Out	Reduces the scale of the hierarchy tree, showing a larger portion of the tree. Shortcuts

Normal Size	Zooms in or out to display the hierarchy tree at the normal (default) size. Shortcuts

Auto Fit in Window	Forces the Hierarchy Display to automatically display the entire hierarchy tree at all times.

Other commands on the View menu are not available if Auto Fit in Window is turned on.

See also:

Changing the Hierarchy Orientation

Fitting the Hierarchy into the Window

Showing & Hiding Hierarchy Branches

Turning Compact Display On or Off


Orientation Commands (Hierarchy Display)
Orientation Commands (Options Menu)

Change the orientation of the hierarchy tree to vertical or horizontal.

Command:	Action:

Orientation Vertical	Changes the orientation of the hierarchy tree so that filenames are listed from top to bottom.

Orientation Horizontal	Changes the orientation of the hierarchy tree so that filenames are listed from left to right.

See also:

Changing the Hierarchy Orientation


Compact Display Command (Options Menu)

Rearranges the items in the Hierarchy Display window so that they fit closer together and show a larger portion of the hierarchy tree without changing the display scale.

See also:

Changing the Hierarchy Orientation

Fitting the Hierarchy into the Window

Showing & Hiding Hierarchy Branches

Turning Compact Display On or Off

Zooming In & Out


Show All Hierarchy Branches Command (Hierarchy Display)
Show All Hierarchy Branches Command (Options Menu)

Displays all branches of the hierarchy tree in the Hierarchy Display window.

Show All Hierarchy Branches redisplays all hierarchy branches that were previously hidden with branch buttons. This command is a shortcut for individually redisplaying each hierarchy branch.

Shortcut:

See also:

Showing & Hiding Hierarchy Branches


Hierarchical Node Name Synonyms


Change File Type dialog box (Hierarchy Display)
Hierarchical Node Name


Hierarchy Display Window (1)
Hierarchy Display Window


Hierarchy Display Window (2)
Hierarchy Display Window


branch buttons


---------------------BEGINNING OF NON-TRANSLATED TEXT---------------------------------

The following panels have been moved to 3rdparty.mac:

Guidelines for Workstation Help UsersWS_HELP

------------------------------END OF NON-TRANSLATED TEXT------------------------------------


How to Use MAX+PLUS II Help

MAX+PLUS II Help provides comprehensive, platform-independent documentation for MAX+PLUS II software. This help panel tells you how to get the most out of MAX+PLUS II Help. If you have never used Help before, choose How to Use Help from the Help menu to learn about the mechanics of using the Help application.

To learn about MAX+PLUS II Help, choose one of the following topics:

Copying Examples from Help

Customizing the Color of Help Topic Jumps

Getting Context-Sensitive Help

Maximizing the MAX+PLUS II Help Window

Opening the read.me File

Searching for a Help Topic

Understanding MAX+PLUS II Help Categories

Workstation users should also refer to Guidelines for Workstation Help Users.

MAX+PLUS II Help uses consistent documentation conventions to make it easy for you to find and interpret information:

Backus-Naur Form (BNF)

Key Combinations

Terminology

Typographic Conventions


Copying Examples from Help (How to Use MAX+PLUS II Help)
Copying Examples from Help

MAX+PLUS II Help contains many examples that you can use when creating text-based design files and/or ancillary files. These examples can be copied to the Clipboard and pasted directly into a TDF, VHDL Design File, or another text file.

To copy an example from MAX+PLUS II Help:

1.	Open a Help topic that contains an example.

2.	Choose Copy (Edit menu). The Copy dialog box is displayed.

 	Click Button 1 on any item in this dialog box for information on that item:

3.	(Optional) Select the text you wish to copy. If you do not select any text, all text in the Help topic is copied to the Clipboard.

4.	Choose the Copy button.

5.	Open or switch to an existing Text Editor file or create a new file.

6.	Move the cursor to the desired insertion point or select the text to be replaced.

7.	Choose Paste (Edit menu).

The text you copied is pasted into the file at the current insertion point.

You cannot copy the graphics from a Help topic onto the Clipboard.

See also:

Creating a New File

Customizing the Color of Help Topic Jumps

Getting Context-Sensitive Help

How to Use MAX+PLUS II Help

Opening a File

Opening the read.me File

Starting MAX+PLUS II Applications

Switching Between MAX+PLUS II Applications


Select Files
Select text to copy to the Clipboard

Displays all text in the current Help topic.

You can select the text in this box and choose the Copy button to copy the selected text to the Clipboard. If you do not select any text, all text in the Help topic is copied to the Clipboard.


Copy button (Help application)
Copy

Copies selected text in the Select text to copy to the Clipboard box to the Clipboard. If you do not select any text, all text in the current Help topic is copied to the Clipboard.


Customizing the Color of Help Topic Jumps (How to Use MAX+PLUS II Help)
Customizing the Color of Help Topic Jumps

Each Help topic contains one or more underlined words, called jumps, that provide links to other Help topics or to additional information on the current topic. A green dotted underline jump links to a glossary entry or an example that pops up on top of the current Help topic. A green solid underline jump takes you to a different Help topic. A blue solid underline* jump is specially coded to provide a shortcut or example that pops up on top of the current Help topic.

In MAX+PLUS II Help, most topics use the green default color for jumps. You can change the color of the green dotted underline and/or solid underlined jumps to more easily distinguish between the two types of jumps. (The color of blue jumps cannot be changed.)

To customize the color of the green jumps that appear in the Help window:

Add one or both of the following two parameters to the [Windows Help] section of your win.ini file:

PopupColor = <red> <green> <blue>

JumpColor = <red> <green> <blue>

The variables <red> <green> <blue> are numbers from 0 to 255 that control the color intensity. For example, to change the jump text (solid underline) to red, add the following line to your win.ini file:

JumpColor = 255 0 0

See also:

Appendix C: Additional Workstation Configuration Information in the MAX+PLUS II Getting Started manual


Getting Context-Sensitive Help (How to Use MAX+PLUS II Help)
Getting Context-Sensitive Help

Context-sensitive help gives you instant help when you need it. MAX+PLUS II provides context-sensitive help on the following items:

Menu commands

Dialog boxes

Messages, including messages that pop up and messages that are displayed in the Message Processor window

Basic tools that are visible in individual application windows, such as primitive and macrofunction symbols, palette tools, buttons, fields, icons, waveforms, module boxes, etc.

Any MAX+PLUS II text file. In addition, context-sensitive help is available for individual syntax elements (e.g., keywords and punctuation) in the following text files, provided that you have saved the file with the correct filename extension:

-	ACFs

-	AHDL TDFs (including primitive, megafunction, and macrofunction names)

-	EDIF Command Files

-	Vector Files

-	Command Files

-	Report Files

-	VHDL Design Files (primitive, megafunction, and macrofunction names only)

You can access context-sensitive help in three ways:

Choose the [image] context-sensitive help button from the toolbar

or:

Press Shift+F1

The pointer turns into a Help pointer, and you can then point to an item on the screen or a menu command and click Button 1 on it to obtain context-sensitive help. (Shift+F1 and the toolbar buttons are not available in MAX+PLUS II for workstations).

When a menu command is highlighted, a dialog box is open, or a pop-up message box is displayed, press F1. You can also press F1 when the current application window is displayed to obtain general help.

In the Message Processor window, you can select a message with Button 1 and choose the Help on Message button to display help on that message.

If you select an item for which no context-sensitive help is available, MAX+PLUS II displays information on the types of context-sensitive help that you can find for the current application or text file.

See also:

Customizing the Color of Help Topic Jumps

Getting Help on a Message

Opening the read.me File

Maximizing the MAX+PLUS II Help Window

Searching for a Help Topic

Understanding MAX+PLUS II Help Categories


Maximizing the MAX+PLUS II Help Window (How to Use MAX+PLUS II Help)
Maximizing the MAX+PLUS II Help Window

A dotted underline jump links to a glossary entry or an example that pops up on top of the current Help topic. Since the size of a pop-up window is proportional to the size of the main Help window, Altera recommends maximizing the Help window to ensure that you can see all of each pop-up window. You can maximize the Help window by choosing Maximize (Application Control Menu) or by clicking Button 1 on the Maximize button in the top right corner of the Help window.

See also:

Customizing the Color of Help Topic Jumps

Getting Context-Sensitive Help

How to Use MAX+PLUS II Help

Opening the read.me File

Searching for a Help Topic

Understanding MAX+PLUS II Help Categories


Opening the read.me File (How to Use MAX+PLUS II Help)
Opening the read.me File

MAX+PLUS II includes a read.me file that contains information about changes to the software since the release of the printed documentation. This file also includes information that is not incorporated into the main Help system.

The read.me file is available in ASCII format on the diskettes or CD-ROM that contains the MAX+PLUS II software. You can also read this file from the Help application.

To open the read.me file, you can choose the READ.ME command from the Help menu in MAX+PLUS II, or open the ASCII file with any text editor. In addition, from within the Help application only, you can use the Open command (File menu) to open the file readme.hlp.

See also:

Customizing the Color of Help Topic Jumps

Getting Context-Sensitive Help

Maximizing the MAX+PLUS II Help Window

Searching for a Help Topic

Understanding MAX+PLUS II Help Categories


Searching for a Help Topic (How to Use MAX+PLUS II Help)
Searching for a Help Topic

MAX+PLUS II Help includes an extensive on-line index to help you find information fast.

To search for a Help topic:

1.	Choose the Search for Help on command on the MAX+PLUS II Help menu or the Search button in the Help window’s button bar to open the Search dialog box.

 Click Button 1 on any item in this dialog box for information on that item:

2.	Type a keyword or phrase of interest. The keyword list scrolls to display the keywords that match what you type.

3.	Choose the Show Topics button or double-click Button 1 on a keyword to list all topics associated with that word.

4.	Select any topic name from the list and choose the Go To button, or double-click Button 1 on a topic name to view the topics.

See also:

Customizing the Color of Help Topic Jumps

Getting Context-Sensitive Help

Maximizing the MAX+PLUS II Help Window

Opening the read.me File

Understanding MAX+PLUS II Help Categories


Keyword

Specifies the keyword or phrase about which you want to find information. You can type a keyword or phrase or select a keyword or phrase from the list. The keyword list scrolls to display the keywords that match what you type.


Keyword List

Lists all the keywords available in MAX+PLUS II Help. You can type a keyword or phrase in the Keyword box or select a keyword or phrase from the list. The keyword list scrolls to display the keywords that match what you type. You can then display a list of Help topics associated with the selected keyword by choosing the Show Topics button.


Topic List

Lists all the Help topics available for the keyword(s) shown in the Keyword box. You must choose the Show Topics button to display topics in the Topic List box.

You can select any topic from the list and choose the Go To button to view the topic. Double-clicking Button 1 on a topic is a shortcut for choosing the Go To button.


Close or Cancel

Closes the dialog box without saving any changes.


Show Topics

Displays a list of Help topics that are associated with the keyword(s) shown in the Keyword box. You can also double-click Button 1 on a keyword in the Keyword List box to display a list of topics.


Go To

Displays the selected Help topic in the Help window. You can also double-click Button 1 on a topic in the Topic List box to view that topic.


Understanding MAX+PLUS II Help Categories (How to Use MAX+PLUS II Help)
Understanding MAX+PLUS II Help Categories

MAX+PLUS II includes several different categories of help. Since many help topics are interrelated, each topic contains jumps that provide links to other relevant help topics. Two basic types of help are available: information on individual MAX+PLUS II applications, and information that helps you use MAX+PLUS II as a whole.

MAX+PLUS II Help includes the help categories listed below. You can reach some types of help directly with a Help menu command. Other types of help are available from the overall table of contents for MAX+PLUS II Help, which you open by choosing MAX+PLUS II Contents (Help menu). (You can also reach the MAX+PLUS II Help Contents by choosing the Contents button from the button bar at the top of the Help window.)

Help Category:	Description:

Introduction to MAX+PLUS II	An introduction to the MAX+PLUS II development system.

Search for Help on	Provides access to the on-line index for all of MAX+PLUS II Help and allows you to search for help topics by specifying a keyword or phrase.

MAX+PLUS II Table of Contents	A list of all major categories in MAX+PLUS II Help.

<Application Name> Contents	Help on each individual MAX+PLUS II application. The following help categories are available for each MAX+PLUS II application:

Category:	Description:

Introduction	Provides an overview of the application.

Basic Tools	Describes items visible in the application window, input and output files, and text file formats. This help category gives you access to information on primitives, megafunctions, macrofunctions, buttons, fields, icons, waveforms, module boxes, etc.

Commands	Supplies complete descriptions of all menu commands and command dialog boxes.

Procedures	Gives step-by-step instructions on how to perform specific tasks.

Golden Rules	Summarizes essential guidelines and recommendations for using the application.

Shortcuts	Lists keyboard and mouse shortcuts for commands and procedures.

AHDL	Help on AHDL, including an introduction; descriptions of basic elements, design structure, and syntax; golden rules; how-to’s; and a style guide.

VHDL	Help on VHDL, including an introduction; descriptions of syntax and support; golden rules; how-to’s; and a style guide.

Megafunctions/LPM	Help on all Altera-provided megafunctions, including LPM functions. LPM and megafunction help includes AHDL Function Prototypes and information on ports, parameters, function tables, and resource usage.

Old-Style Macrofunctions	Help on all Altera-provided old-style macrofunctions, including function tables and AHDL Function Prototypes.

Primitives	Help on all Altera-provided primitives, including AHDL Function Prototypes.

Devices & Adapters	Information on all Altera devices and adapters, including device descriptions, pin-outs, and logic cell interconnections.

Third-Party Interfaces	Information on using other industry-standard CAE tools with the MAX+PLUS II, including basic tools, commands, and procedures for importing EDIF files, OrCAD Schematic Files, VHDL Design Files and XNF Files and exporting EDIF Output Files, Verilog Output Files, and VHDL Output Files.

Messages	A list of all messages generated by MAX+PLUS II, including detailed explanations of their probable causes and suggested recommended actions.

Glossary	A comprehensive glossary of terms used in MAX+PLUS II software and documentation.

Design Doctor	Information on the Compiler’s Design Doctor utility, which checks your projects for potentially unreliable logic.

How to Use Help	Explains the mechanics of using the Help application.

How to Use MAX+PLUS II Help	Describes how to get the most out of the help information supplied with MAX+PLUS II.

Recommended Reading	A list of other Altera publications that contain related information.

New Features in This Release	Descriptions of all new features in the current version of MAX+PLUS II, including jumps that provide links to new and updated Help topics.

Regardless of how you first enter the Help window, you can go to any topic at any time. For example, you can choose the Contents button to go to the overall table of contents for MAX+PLUS II Help, or choose the Search button to search for a topic that matches a particular keyword or phrase.

See also:

Customizing the Color of Help Topic Jumps

Getting Context-Sensitive Help

Guidelines for Workstation Help Users

Maximizing the MAX+PLUS II Help Window

Opening the read.me File

Searching for a Help Topic


How to Use Help (MAX+PLUS II)
How to Use Help

MAX+PLUS II Help consists of topics that help you find information on items such as commands, procedures, and the basic tools used in MAX+PLUS II.

Each Help topic contains one or more underlined words, called jumps, that provide links to other Help topics or to additional information on the current topic. To view a topic, point to the jump and click Button 1. The pointer changes to a hand when it is over a jump.

A dotted underline jump links to a glossary entry or an example that pops up on top of the current Help topic. A solid underline jump takes you to a different Help topic.

The size of a pop-up window is proportional to the size of the main Help window. You must increase the size of the Help window if you want the pop-up window to be larger. Altera recommends maximizing the Help window to ensure that you can see all of each pop-up window. See Maximizing the MAX+PLUS II Help Window.

The top of the Help window contains a bar with the following buttons. You can click Button 1 on one of these buttons to move around in MAX+PLUS II Help:

Button:	Action:

Contents	Displays the MAX+PLUS II Help Contents, a table of contents for all MAX+PLUS II Help.

Search	Opens the Search dialog box, which allows you to select or type a word or phrase of interest, list all Help topics that are associated with that word, and then go to a Help topic from the list.

Back	Goes back through the Help topics you have already reviewed. This button is dimmed if there is no previous topic to view.

History	Shows the last 40 topics you have viewed. You can reread a topic by double-clicking Button 1 on it.

Glossary	Shows a comprehensive glossary of terms used in MAX+PLUS II software and documentation.

Print	Prints the current Help topic. You can specify the number of copies and a Postscript printer. Refer to the documentation for your printer for information about printer setup. Workstation users may also wish to refer to Appendix C: Additional Workstation Configuration Information in the MAX+PLUS II Getting Started manual.

Close	Closes MAX+PLUS II Help.

For special information on Help for workstation-based MAX+PLUS II software, see Guidelines for Workstation Help Users. See How to Use MAX+PLUS II Help for a description of the specific features of MAX+PLUS II Help.


Backus-Naur Form (BNF)

MAX+PLUS II Help uses the Backus-Naur Form (BNF) to define the syntax of the text file formats and message variables. BNF uses the following notation:

Characters:	Meaning:

::= 	"Is defined as"

<...>	Identifiers (i.e., variables)

[...]	Optional items

{ ... }	Repeated items (zero or more times)

...|...	Indicates a choice between items

:n:n	Suffix indicates a range (e.g., <name char>:1:8 means "from 1 to 8 name characters")

italics	Variables in syntax descriptions

Courier font	Literal text in syntax descriptions. Bold Courier font is also sometimes used to help distinguish literal text from italic variables in syntax descriptions.

See also:

Key Combinations

Terminology

Typographic Conventions


Key Combinations

Key combinations and sequences in MAX+PLUS II Help and manuals appear in the following format:

Format Cue:	Meaning:

Key1+Key2	A plus (+) symbol indicates that you must hold down the first key when you press the second key. Example: Ctrl+L means that you must hold down Ctrl while pressing L, then release both keys.

Key1,Key2	A comma (,) indicates that you must press the keys sequentially. Example: Alt,F1 means that you must press Alt and release it, then press F1 and release it.

See also:

Backus-Naur Form (BNF)

Guidelines for Workstation Help Users

Terminology

Typographic Conventions


Terminology

The following terminology is used throughout MAX+PLUS II Help and manuals:

Term:	Meaning:

Button 1	Left mouse button.

Button 2	Right button on a two-button mouse or the middle or right button on a three-button mouse.

"point to"	Indicates that you should move the mouse so that the pointer is over the specified item.

"choose"	Indicates that you need to use a mouse or key combination to start an action. For example, when you use the mouse to choose a button, you point to the button and click Button 1. When you use the keyboard to choose a command, you type Alt and then type letters that are underlined in the menu bar and menu. (In workstation-based MAX+PLUS II, you must use Ctrl instead of Alt.)

"select"	Indicates that you need to highlight text and/or objects or an option in a dialog box with a key combination or the mouse. A selection does not start an action. Example: Select the AND2 primitive, then choose Delete from the Edit menu.

"press"	Indicates that you must hold down a mouse button or key.

"turn on"/"turn off"	Indicates that you must click Button 1 on a checkbox or choose a menu command to turn a function on or off.

"click"	Indicates a quick press and release of a mouse button.

"double-click"	Indicates two clicks in rapid succession.

See also:

Backus-Naur Form (BNF)

Guidelines for Workstation Help Users

Key Combinations

Typographic Conventions


Typographic Conventions

MAX+PLUS II Help and manuals use the following typographic conventions:

Visual Cue:	Meaning:

Bold Initial Capitals	Command names, dialog box titles, button names, and diskette names are shown in bold, with initial capital letters. Examples: Find Text command, Save As dialog box, Start button, and Install diskette.

bold	Directory names, project names, disk drive names, filenames, filename extensions, and software utility names are shown in bold. Examples: \maxplus2 directory, d: drive, chiptrip.gdf file. These items are not case-sensitive in the Windows environment; however, they are case-sensitive in the workstation environment. MAX+PLUS II Help shows these items in the case appropriate to the workstation environment.

Initial Capitals	Keyboard keys, user-editable application window fields, and menu names are shown with initial capital letters. Examples: Delete key, the Start Time field, the Options menu.

"Subheading Title"	Subheadings within a manual section are enclosed in quotation marks. In manuals, titles of help topics are also shown in quotation marks.

Italic Initial Capitals	Help categories, section titles in manuals, application note and brief names, checkbox options, and options in dialog boxes are shown in italics with initial capital letters. Examples: Text Editor Procedures, the Check Outputs option, the Directories box in the Open dialog box.

italics	Variables are enclosed in angle brackets (< >) and shown in italics. Example: <filename>, <project name>.acf file.

Bold Italics	Manual titles are shown in bold italics with initial capital letters. Example: MAX+PLUS II Getting Started.

Courier font	Anything that must be typed exactly as it appears in Help is shown in Courier. For example: c:\max2work\tutorial\chiptrip.gdf. Also, sections of an actual file, such as a Report File, references to parts of files (e.g., the AHDL keyword SUBDESIGN), and primitive and macrofunction names (e.g., DFF and 16CUDSLR) are shown in Courier.

Bold Courier font	In syntax descriptions, bold Courier may be used to help distinguish literal text from variables.

1., 2., 3., and a., b., c.,...	Numbered steps are used in a list of items when the sequence of the items is important, such as the steps listed in a procedure.

Bullets are used in a list of items when the sequence of the items is not important.

The checkmark indicates a procedure that consists of one step only.

The hand points to information that requires special attention.

In MAX+PLUS II manuals, the feet show you where to go for more information on a particular topic.

The upward-pointing hand indicates that you can click Button 1 on any portion of the illustration that follows it to get help on that item. The mouse pointer changes to an upward-pointing hand when it is over a picture or word for which help is available.

See also:

Backus-Naur Form (BNF)

Guidelines for Workstation Help Users

Key Combinations

Terminology


pop-up window

This is an example of a pop-up window. Click Button 1 anywhere on the screen to make it go away.


Sample Help Topic

This is a sample Help topic. You can click Button 1 on the underlined text or choose the Back button in the Help button bar to return to How to Use Help.


Search dialog box popup
 Search dialog box


Devices & Adapters

Adapters

Configuration EPROM Devices

EPC1

EPC1064/EPC1064V

EPC1213

FLEX 10K Devices

EPF10K50

Selection Guide

FLEX 8000 Devices

EPF8282/EPF8282A

EPF8282V

EPF8452/EPF8452A

EPF8636A

EPF8820/EPF8820A

EPF81188/EPF81188A

EPF81500/EPF81500A

Selection Guide

MAX 9000 EPLDs

EPM9320

EPM9400

EPM9480

EPM9560

Selection Guide

MAX 7000 EPLDs

EPM7032

EPM7032V

EPM7064

EPM7096

EPM7128E

EPM7160E

EPM7192E

EPM7256E

Selection Guide

MAX 5000 EPLDs

EPM5016

EPM5032

EPS464

EPM5064

EPM5128/EPM5128A

EPM5130

EPM5192

Selection Guide

Classic EPLDs

EP330/EP320I/EP220

EP610/EP610I/EP600I

EP910/EP910I/EP900I

EP1810/EP1800I

Selection Guide

FLASHlogic Devices

EPX740

EPX780/EPX880

EPX8160

Selection Guide

MPLDs

See also:

Programming-Only Support for Altera Devices


Adapters

The following table contains information on supported Altera device programming hardware. You should always use the latest version of programming software to ensure correct programming.

For up-to-date information on adapter availability, contact Altera Marketing.

EPLD  Note (1)	Package	Adapter   Note (2)	Notes

EP330/EP320I/EP220	DIP	None required

J-Lead	PLEJ330	(4)

SOIC	PLES330	(4)

EP610/610I/600I	DIP	PLED610	(4)

J-lead	PLEJ610	(4)

SOIC	PLES610	(4)

EP910/910I/900I	DIP	PLED910	(4)

J-lead	PLEJ910	(4)

EP1810/1800I	J-lead	PLEJ1810	(4)

J-lead	PLMJ1810

PGA	PLEG1810	(4)

EPC1	J-lead	PLMJ1213	(5)

DIP	PLMJ1213	(5)

EPC1064/EPC1064V	J-lead	PLMJ1213	(5)

DIP	PLMJ1213	(5)

TQFP	PLMT1064	(5)

EPC1213	J-lead	PLMJ1213	(5)

DIP	PLMJ1213	(5)

EPM5016	DIP	PLED5016	(4)

J-lead	PLEJ5016	(4)

SOIC	PLES5016	(4)

EPM5032	DIP	PLMD5032A	(4)

J-lead	PLMJ5032A	(4)

SOIC	PLMS5032A	(4)

EPM5064	J-lead	PLMJ5064A	(4)

EPM5128/EPM5128A	J-lead	PLMJ5128A

PGA	PLMG5128A

EPM5130	J-lead	PLMJ5130A	(4)

PGA	PLMG5130A	(4)

CQFP	PLMQ5130A

PQFP	PLMQ5130A

EPM5192	J-lead	PLMJ5192A

PGA	PLMJ5192A

EPLD  Note (1)	Package	Adapter   Note (2)	Notes

EPM7032	J-lead	PLMJ7000-44, PLMJ7032-44

PQFP	PLMQ7000-44, PLMQ7032-44

TQFP	PLMT7000-44, PLMT7032-44

EPM7032V	J-lead	PLMJ7000-44, PLMJ7032-44

TQFP	PLMT7000-44, PLMT7032-44

EPM7064	J-lead (44-pin)	PLMJ7000-44

TQFP (44-pin)	PLMT7000-44

J-lead (68-pin)	PLMJ7000-68

J-lead (84-pin)	PLMJ7000-84

PQFP (100-pin)	PLMQ7000-100

EPM7096	J-lead (68-pin)	PLMJ7000-68, PLMJ7096-68

J-lead (84-pin)	PLMJ7000-84, PLMJ7096-84

PQFP (100-pin)	PLMQ7000-100, PLMQ7096-100

EPM7128E	J-lead (84-pin)	PLMJ7000-84, PLMJ7128-84

PQFP (100-pin)	PLMQ7000-100

PQFP (160-pin)	PLMQ7128/7160-160, PLMQ7128-160

EPM7160E	J-lead (84-pin)	PLMJ7000-84, PLMJ7160-84

PQFP (100-pin)	PLMQ7000-100

PQFP (160-pin)	PLMQ7128/7160-160, PLMQ7160-160

EPM7192E	PGA	PLMG7192-160

PQFP	PLMQ7192/7256-160, PLMQ7192-160

EPM7256E/EPM7256	PQFP (160-pin)	PLMQ7192/7256-160

PGA (192-pin)	PLMG7256-192

RQFP (208-pin)	PLMR7256-208

EPM9320	J-lead (84-pin)	PLMJ9320-84, PL-BITBLASTER	(6)

RQFP (208-pin)	PLMR9000-208, PL-BITBLASTER	(6)

PGA (280-pin)	PLMG9000-280, PL-BITBLASTER	(6)

EPM9400	RQFP (208-pin)	PLMR9000-208, PL-BITBLASTER	(6)

RQFP (240-pin)	PLMR9000-240, PL-BITBLASTER	(6)

EPM9480	RQFP (208-pin)	PLMR9000-208, PL-BITBLASTER	(6)

RQFP (240-pin)	PLMR9000-240, PL-BITBLASTER	(6)

EPM9560	RQFP (208-pin)	PLMR9000-208, PL-BITBLASTER	(6)

RQFP (240-pin)	PLMR9000-240, PL-BITBLASTER	(6)

PGA (280-pin)	PLMG9000-280, PL-BITBLASTER	(6)

RQFP (304-pin)	PLMR9000-304, PL-BITBLASTER	(6)

EPLD  Note (1)	Package	Adapter   Note (2)	Notes

EPS464	J-lead	PLEJ464	(4)

J-lead	PLMJ464

QFP	PLEQ464	(4)

QFP	PLMQ464

EPX740	J-lead (44-pin)	PLMJ740-44, PL-BITBLASTER	(6)

J-lead (68-pin)	PLMJ740-68, PL-BITBLASTER	(6)

EPX780	J-lead	PLMJ780-84, PL-BITBLASTER	(6)

QFP	PL-BITBLASTER	(6)

EPX880	QFP	PL-BITBLASTER	(6)

EPX8160	QFP	PL-BITBLASTER	(6)

All FLEX 10K Devices	All	PL-BITBLASTER	(3)

All FLEX 8000 Devices	All	PL-BITBLASTER	(3)


Adapters Note 1
Note (1)

All programmable Altera devices can be programmed with the PL-MPU Master Programming Unit. (FLEX 8000 and FLEX 10K devices are not programmable.) In addition, all Classic devices can be programmed with the older PLE3-12A programming unit. The LP6 Programmer Card can be used with all devices.


Adapters Note 2
 Note (2)

Refer to the Altera Programming Hardware Data Sheet in the current Altera Data Book for more information.


Adapters Note 3
 Note (3)

Configuration of FLEX 8000 and FLEX 10K devices is supported by Configuration EPROMs, the FLEX Download Cable, and the BitBlaster.


Adapters Note 4
 Note (4)

These adapters require the PLAD3-12 compatibility adapter and the PL-MPU Master Programming Unit.


Adapters Note 5
 Note (5)

In-circuit FLEX 8000  and FLEX 10K device configuration is supported by all Configuration EPROM adapters in conjunction with the FLEX Download Cable.


Adapters Note 6
 Note (6)

The BitBlaster can be used for in-system programming of MAX 9000 and FLASHlogic devices, and in-circuit configuration of FLEX 8000, FLEX 10K, and FLASHlogic devices.


Programming-Only Support for Altera Devices

MAX+PLUS II provides programming-only support for the following devices:

SAM EPS448

FLASHlogic devices and their corresponding Intel ordering codes:

EPX740LC44

EPX740LC68

EPX780LC84

EPX780QC132

EPX880QC132

EPX8160QC208

Classic devices with Intel ordering codes (full compilation support is available only for Altera device names):

EP320

EP600

EP900

EP1800

For information on Intel ordering codes, refer to the Intel-to-Altera Device Ordering Code Cross-Reference.


EP330/EP320I/EP220 EPLDs

The EP330, EP320I, and EP220 EPLDs provide high-speed, low-power, pin-compatible replacement for 20-pin programmable logic devices such as PALs and GALs. These EPLDs can accommodate up to 18 inputs and 8 outputs and have 8 logic cells, as shown in the table below. They are available in 20-pin DIP, J-lead, and SOIC packages. For complete information on EP330, EP320I, and EP220 EPLDs, refer to the current Altera Data Book.

MAX+PLUS II provides full compilation and programming support for the following programming-file-compatible EP330-equivalent devices. Only programming support is provided for the equivalent Intel device names (shown in parentheses):

EP320I	(5C032)

EP220	(5C220)

For information on Intel ordering codes, refer to the Intel-to-Altera Device Ordering Code Cross-Reference.

See also:

Classic EPLD Selection Guide

Recommended reading:

AN2 (Replacing 20-Pin PAL & GAL Devices with EP330 Classic EPLDs)

AN26 (EPLD/MPLD Design Guidelines)

AN42 (Metastability in Altera Devices)

AB9 (Asynchronous Latches in Classic, MAX & STG EPLDs)

AB60 (Estimating a Design Fit)

AB87 (Troubleshooting Functional Problems in EPLDs)

AB89 (Minimizing Output Switching Noise in Altera EPLDs)

AB91 (External Clock Sources for Altera EPLDs)

AB94 (Solutions to Design Timing Problems for Altera EPLDs)

AB100 (Understanding Classic, MAX 5000 & MAX 7000 Timing)

Altera Device Package Outlines Data Sheet

Operating Requirements for Altera Devices Data Sheet

Function	LCell	J-Lead	DIP	SOIC

Input/GCLK	-	1	1	1

Input	-	2	2	2

Input	-	3	3	3

Input	-	4	4	4

Input	-	5	5	5

Input	-	6	6	6

Input	-	7	7	7

Input	-	8	8	8

Input	-	9	9	9

Input	-	11	11	11

I/O or Buried	1	19	19	19

I/O or Buried	2	18	18	18

I/O or Buried	3	17	17	17

I/O or Buried	4	16	16	16

I/O or Buried	5	15	15	15

I/O or Buried	6	14	14	14

I/O or Buried	7	13	13	13

I/O or Buried	8	12	12	12

VCC	-	20	20	20

GND	-	10	10	10


EP610/EP610I/EP600I EPLDs

The high-performance EP610, EP610I, and EP600I EPLDs are high-density replacements for TTL and 74HC devices with up to 600 equivalent gates of SSI and MSI logic functions. These EPLDs can accommodate up to 20 inputs or 16 outputs and have 16 logic cells, as shown in the table below. They are available in 24-pin DIP and SOIC and 28-pin J-lead packages. For complete information on the EP610, EP610I, and EP600I EPLDs, refer to the current Altera Data Book.

MAX+PLUS II provides full compilation and programming support for the following programming-file-compatible EP610-equivalent devices. Only programming support is provided for the equivalent Intel device names (shown in parentheses):

EP600I	(5C060)

EP610I	(PLD610)

For information on Intel ordering codes, refer to the Intel-to-Altera Device Ordering Code Cross-Reference.

See also:

Classic EPLD Selection Guide

Recommended reading:

AN26 (EPLD/MPLD Design Guidelines)

AN42 (Metastability in Altera Devices)

AB9 (Asynchronous Latches in Classic, MAX & STG EPLDs)

AB60 (Estimating a Design Fit)

AB83 (Programmable Frequency Divider with the EP610 Classic EPLD)

AB87 (Troubleshooting Functional Problems in EPLDs)

AB89 (Minimizing Output Switching Noise in Altera EPLDs)

AB91 (External Clock Sources for Altera EPLDs)

AB94 (Solutions to Design Timing Problems for Altera EPLDs)

AB100 (Understanding Classic, MAX 5000 & MAX 7000 Timing)

Altera Device Package Outlines Data Sheet

Operating Requirements for Altera Devices Data Sheet

Function	LCell	LAB	J-Lead	DIP	SOIC

Input/GCLK	-	A	16	13	13

Input/GCLK	-	B	2	1	1

Input	-	-	3	2	2

Input	-	-	13	11	11

Input	-	-	17	14	14

Input	-	-	27	23	23

I/O or Buried	1	A	26	22	22

I/O or Buried	2	A	25	21	21

I/O or Buried	3	A	24	20	20

I/O or Buried	4	A	23	19	19

I/O or Buried	5	A	22	18	18

I/O or Buried	6	A	21	17	17

I/O or Buried	7	A	20	16	16

I/O or Buried	8	A	18	15	15

I/O or Buried	9	B	4	3	3

I/O or Buried	10	B	5	4	4

I/O or Buried	11	B	6	5	5

I/O or Buried	12	B	7	6	6

I/O or Buried	13	B	8	7	7

I/O or Buried	14	B	9	8	8

I/O or Buried	15	B	10	9	9

I/O or Buried	16	B	12	10	10

VCC	-	-	1	-	-

VCC	-	-	28	24	24

Function	LCell	LAB	J-Lead	DIP	SOIC

GND	-	-	14	-	-

GND	-	-	15	12	12

N.C.	-	-	11	-	-

N.C.	-	-	19	-	-


EP910/EP910I/EP900I EPLDs

The high-performance EP910, EP910I, and EP900I EPLDs are high-density replacements for TTL and 74HC devices with up to 900 equivalent gates of SSI and MSI logic functions. These EPLDs can accommodate up to 36 inputs or 24 outputs and have 24 logic cells, as shown in the table below. They available in 40-pin DIP and 44-pin J-lead packages. For complete information on EP910, EP910I, and EP900I EPLDs, refer to the current Altera Data Book.

MAX+PLUS II provides full compilation and programming support for the following programming-file-compatible EP910-equivalent devices. Only programming support is provided for the equivalent Intel device names (shown in parentheses):

EP900I	(5C090)

EP910I	(PLD910)

For information on Intel ordering codes, refer to the Intel-to-Altera Device Ordering Code Cross-Reference.

See also:

Classic EPLD Selection Guide

Recommended reading:

AN26 (EPLD/MPLD Design Guidelines)

AN42 (Metastability in Altera Devices)

AB9 (Asynchronous Latches in Classic, MAX & STG EPLDs)

AB60 (Estimating a Design Fit)

AB87 (Troubleshooting Functional Problems in EPLDs)

AB89 (Minimizing Output Switching Noise in Altera EPLDs)

AB91 (External Clock Sources for Altera EPLDs)

AB94 (Solutions to Design Timing Problems for Altera EPLDs)

AB100 (Understanding Classic, MAX 5000 & MAX 7000 Timing)

Altera Device Package Outlines Data Sheet

Operating Requirements for Altera Devices Data Sheet

Function	LCell	LAB	J-Lead	DIP

Input/GCLK	-	A	24	21

Input/GCLK	-	B	2	1

Input	-	-	3	2

Input	-	-	4	3

Input	-	-	5	4

Input	-	-	19	17

Input	-	-	20	18

Input	-	-	21	19

Input	-	-	25	22

Input	-	-	26	23

Input	-	-	27	24

Input	-	-	41	37

Input	-	-	42	38

Input	-	-	43	39

I/O or Buried	1	A	40	36

I/O or Buried	2	A	38	35

I/O or Buried	3	A	37	34

I/O or Buried	4	A	36	33

I/O or Buried	5	A	35	32

I/O or Buried	6	A	34	31

I/O or Buried	7	A	33	30

I/O or Buried	8	A	32	29

I/O or Buried	9	A	31	28

I/O or Buried	10	A	30	27

Function	LCell	LAB	J-Lead	DIP

I/O or Buried	11	A	29	26

I/O or Buried	12	A	28	25

I/O or Buried	13	B	6	5

I/O or Buried	14	B	7	6

I/O or Buried	15	B	8	7

I/O or Buried	16	B	9	8

I/O or Buried	17	B	10	9

I/O or Buried	18	B	11	10

I/O or Buried	19	B	12	11

I/O or Buried	20	B	13	12

I/O or Buried	21	B	14	13

I/O or Buried	22	B	15	14

I/O or Buried	23	B	16	15

I/O or Buried	24	B	18	16

VCC	-	-	1	-

VCC	-	-	44	40

GND	-	-	22	-

GND	-	-	23	20

N.C.	-	-	17	-

N.C.	-	-	39	-


EP1810/EP1800I EPLDs

The high-performance EP1810 and EP1800I EPLDs are high-density replacements for 20 to 30 SSI and MSI devices. These EPLDs can accommodate up to 64 inputs or 48 outputs and have 48 logic cells, as shown in the table below. They are available in 68-pin J-lead and PGA packages. For complete information on the EP1810 and EP1800I EPLDs, refer to the current Altera Data Book.

MAX+PLUS II provides full compilation and programming support for the following programming-file-compatible EP1810-equivalent devices. Only programming support is provided for the equivalent Intel device names (shown in parentheses):

EP1800I	(5C180)

For information on Intel ordering codes, refer to the Intel-to-Altera Device Ordering Code Cross-Reference.

See also:

Classic EPLD Selection Guide

Recommended reading:

AN26 (EPLD/MPLD Design Guidelines)

AN42 (Metastability in Altera Devices)

AB9 (Asynchronous Latches in Classic, MAX & STG EPLDs)

AB27 (EP1810 Classic EPLD as a Bar Code Decoder)

AB60 (Estimating a Design Fit)

AB87 (Troubleshooting Functional Problems in EPLDs)

AB89 (Minimizing Output Switching Noise in Altera EPLDs)

AB91 (External Clock Sources for Altera EPLDs)

AB94 (Solutions to Design Timing Problems for Altera EPLDs)

AB100 (Understanding Classic, MAX 5000 & MAX 7000 Timing)

Altera Device Package Outlines Data Sheet

Operating Requirements for Altera Devices Data Sheet

Function	LCell	LAB	J-Lead	PGA

Input/GCLK	-	A	17	L5

Input/GCLK	-	B	19	L6

Input/GCLK	-	C	51	A7

Input/GCLK	-	D	53	A6

Input	-	-	14	K4

Input	-	-	15	L4

Input	-	-	16	K5

Input	-	-	20	K7

Input	-	-	21	L7

Input	-	-	22	K8

Input	-	-	48	B8

Input	-	-	49	A8

Input	-	-	50	B7

Input	-	-	54	B5

Input	-	-	55	A5

Input	-	-	56	B4

I/O or Buried	1	A	2	F1

I/O or Buried	2	A	3	G2

I/O or Buried	3	A	4	G1

I/O or Buried	4	A	5	H2

I/O or Buried	5	A	6	H1

I/O or Buried	6	A	7	J2

I/O or Buried	7	A	8	J1

I/O or Buried	8	A	9	K1

Function	LCell	LAB	J-Lead	PGA

I/O or Buried	9	Note (1) 	A	10	K2

I/O or Buried	10	Note (1)	A	11	L2

I/O or Buried	11	Note (1)	A	12	K3

I/O or Buried	12	Note (1)	A	13	L3

I/O or Buried	13	Note (1)	B	23	L8

I/O or Buried	14	Note (1)	B	24	K9

I/O or Buried	15	Note (1)	B	25	L9

I/O or Buried	16	Note (1)	B	26	L10

I/O or Buried	17	B	27	K10

I/O or Buried	18	B	28	K11

I/O or Buried	19	B	29	J10

I/O or Buried	20	B	30	J11

I/O or Buried	21	B	31	H10

I/O or Buried	22	B	32	H11

I/O or Buried	23	B	33	G10

I/O or Buried	24	B	34	G11

I/O or Buried	25	C	36	F11

I/O or Buried	26	C	37	E10

I/O or Buried	27	C	38	E11

I/O or Buried	28	C	39	D10

I/O or Buried	29	C	40	D11

I/O or Buried	30	C	41	C10

I/O or Buried	31	C	42	C11

I/O or Buried	32	C	43	B11

I/O or Buried	33	Note (1)	C	44	B10

Function	LCell	LAB	J-Lead	PGA

I/O or Buried	34	Note (1)	C	45	A10

I/O or Buried	35	Note (1)	C	46	B9

I/O or Buried	36	Note (1)	C	47	A9

I/O or Buried	37	Note (1)	D	57	A4

I/O or Buried	38	Note (1)	D	58	B3

I/O or Buried	39	Note (1)	D	59	A3

I/O or Buried	40	Note (1)	D	60	A2

I/O or Buried	41	D	61	B2

I/O or Buried	42	D	62	B1

I/O or Buried	43	D	63	C2

I/O or Buried	44	D	64	C1

I/O or Buried	45	D	65	D2

I/O or Buried	46	D	66	D1

I/O or Buried	47	D	67	E2

I/O or Buried	48	D	68	E1

VCC	-	-	18	B6

VCC	-	-	52	K6

GND	-	-	1	F2

GND	-	-	35	F10


EP1810 Note 1
 Note (1)

This logic cell is global.


Classic EPLD Selection Guide

The following table provides information on the Classic family of general-purpose, zero-standby-power EPLDs. Classic EPLDs are suitable for random logic, and TTL and PAL integration.

1.	MAX+PLUS II provides programming-only support for Classic devices with Intel device names. Compilation support is available only for the equivalent Altera device names. For information on Intel ordering codes, refer to the Intel-to-Altera Device Ordering Code Cross-Reference.

2.	For up-to-date information on device availability, contact Altera Marketing. For more information on Classic devices, refer to the Altera Data Book or contact the Altera Literature Department for a copy of the appropriate data sheet.

EPLD	Package	Temp.	Speed	tPD1	fCNT	ICC3	ICC1	LCell	Ded.	I/O

Note (1)	Note (2)	Note (3)	Grade	(ns)	(MHz)	(mA)	(mA)	(Reg.)	Inputs

Active	Standby

EP220	20P, 20L	C	-7	7.5	100.0	75	-	8	10	8

EP220	20L	C	-7A	7.5	115.0	60	-	8	10	8

EP220	20P, 20L	C	-10	10	60.6	75	-	8	10	8

EP220	20P, 20L	C	-10A	10	100.0	35	0.05	8	10	8

EP220	20P, 20L	C	-12	12	83.3	35	0.05	8	10	8

EP220	20L	I	-12	12	83.3	35	0.05	8	10	8

EP320I	20D, 20P	C	-30	30	28.5	75	75	8	10	8

EP320I	20D, 20P	C	-35	35	25.0	75	75	8	10	8

EP320I	20P	I	-35	35	25.0	75	75	8	10	8

EP320I	20D, 20P	C	-40	40	21.7	75	75	8	10	8

EP320I	20P	I	-40	40	21.7	75	75	8	10	8

EP330	20S	C	-12	12	100.0	75	75	8	10	8

EP330	20S	C	-15	15	83.3	75	75	8	10	8

EP330	20P	I	-15	15	83.3	75	75	8	10	8

EP600I	24D,24P,28L	C	-45	43	22.2	-	0.10	16	4	16

EP600I	28L	I	-45	43	22.2	-	0.10	16	4	16

EP600I	24D,24P	C	-55	53	18.2	-	0.10	16	4	16

EP610	24P,28L,24S	C	-15	15	83.3	90	0.15	16	4	16

EP610	24P,28L	C	-15T	83.3	90	0.15	16	4	16

EP610	24P,24S	C	-20	20	62.5	90	0.15	16	4	16

EP610	28L	I	-20	20	62.5	90	0.15	16	4	16

EP610	24P	C	-20T	62.5	90	0.15	16	4	16

EP610	24D,24P,28L,24S	C	-25	25	40.0	60	0.15	16	4	16

EP610	24P	C	-25T	40.0	60	0.15	16	4	16

EP610	24D,24P	C	-30	30	33.3	60	0.15	16	4	16

EP610	24D,24P,28L	I	-30	30	33.3	60	0.15	16	4	16

EP610	24D,24P,28L	C	-35	35	28.6	60	0.15	16	4	16

EP610	28L	I	-35	35	28.6	60	0.15	16	4	16

EP610	24D	M	-35	35	28.5	60	0.15	16	4	16

EP610I	24D,24P,28L	C	-10	10	100.0	65	0.02	16	4	16

EP610I	28L	I	-12	12	83.3	65	0.02	16	4	16

EP610I	24D,24P,28L	C	-15	15	66.0	65	0.02	16	4	16

EP610I	24P,28L	C	-25	25	40.0	65	0.02	16	4	16

EP900I	40D,40P,44L	C	-50	45	20.0	80	0.15	24	12	24

EP900I	44L	I	-50	45	20.0	80	0.15	24	12	24

EP900I	44L	C	-60	55	16.7	80	0.15	24	12	24

EP900I	40P	C	-60	55	16.7	80	0.15	24	12	24

EP910	40D,40P,44L	C	-30	30	33.3	80	0.15	24	12	24

EP910	40P,44L	C	-30T	20	33.3	80	0.15	24	12	24

EP910	40D,40P,44L	C,I	-35	35	28.6	80	0.15	24	12	24

EP910	40D,44J	M	-40	40	25.0	80	0.15	24	12	24

EP910	40D,40P,44L	C	-40	40	25.0	80	0.15	24	12	24

EP910	44L	I	-40	40	25.0	80	0.15	24	12	24

EP910I	44L	C,I	-12	12	76.9	120	0.06	24	12	24

EP910I	44L	C,I	-15	15	66.6	120	0.06	24	12	24

EP910I	40D,40P	C	-15	15	66.6	120	0.06	24	12	24

EP910I	40P,44L	C	-25	25	40.0	120	0.06	24	12	24

EP1800I	68L	C	-70	65	16.1	225	0.15	48	16	48

EP1800I	68L	C,I	-75	70	15.1	225	0.15	48	16	48

EP1800I	68L	C,I	-90	85	12.2	225	0.15	48	16	48

EP1810	68L	C	-20	20	50.0	225	0.15	48	16	48

EP1810	68L	C	-20T	20	50.0	225	0.15	48	16	48

EP1810	68L	C,I	-25	25	40.0	225	0.15	48	16	48

EP1810	68L	C	-25T	25	40.0	225	0.15	48	16	48

EP1810	68J,68L,68G	C	-35	35	28.6	180	0.15	48	16	48

EP1810	68L	C	-35T	35	28.6	180	0.15	48	16	48

EP1810	68L,68G	I	-40	40	25.0	180	0.15	48	16	48

EP1810	68J,68L,68G	C,I,M	-45	45	22.2	180	0.15	48	16	48

Recommended reading:

AN26 (EPLD/MPLD Design Guidelines)

AN42 (Metastability in Altera Devices)

AB9 (Asynchronous Latches in Classic, MAX & STG EPLDs)

AB60 (Estimating a Design Fit)

AB87 (Troubleshooting Functional Problems in EPLDs)

AB89 (Minimizing Output Switching Noise in Altera EPLDs)

AB91 (External Clock Sources for Altera EPLDs)

AB94 (Solutions to Design Timing Problems for Altera EPLDs)

AB100 (Understanding Classic, MAX 5000 & MAX 7000 Timing)

Altera Device Package Outlines Data Sheet

Operating Requirements for Altera Devices Data Sheet


Device Note 1
Note (1)

Preliminary data is shown for some parameters. Consult individual device data sheets for complete information.


Device Note 2
Note (2)

Package codes:

D:	Windowed ceramic dual in-line package (CerDIP)

P:	Plastic dual in-line package (PDIP)

J:	Windowed ceramic J-lead chip carrier (JLCC)

L:	Plastic J-lead chip carrier (PLCC)

G:	Windowed ceramic pin-grid array (PGA)

B:	Ball-grid array (BGA)

S:	Plastic small-outline integrated circuit (SOIC)

Q:	Plastic quad flat pack (PQFP)

W:	Windowed ceramic quad flat pack (CQFP)

T:	Thin quad flat pack (TQFP)

R:	Power quad flat pack (RQFP)


Device Note 3
Note (3)

Operating temperature:

C :	Commercial	(0° C to 70° C)

I:	Industrial	(-40° C to 85° C)

M:	Military	(-55° C to 125° C)


Intel-to-Altera Device Ordering Code Cross-Reference

The following MAX+PLUS II-supported devices, formerly offered by Intel, are now offered by Altera through the ordering codes listed below. Only programming support is available for devices with Intel ordering codes. Full compilation and programming support is available for the corresponding Altera ordering codes.

For up-to-date information on device availability, contact Altera Marketing.

Intel Ordering Code:	Altera Ordering Code:

MG5C180-90	EP1800IGM883B-90

N5C180-70	EP1800ILC-70

N5C180-75	EP1800ILC-75

N5C180-90	EP1800ILC-90

TN5C180-90	EP1800ILI-90

D5C090-50	EP900IDC-50

D5C090-60	EP900IDC-60

MDPLD910-20	EP910IDM883B-20

MDPLD910-25	EP910IDM883B-25

MDPLD910-30	EP910IDM883B-30

N5C090-50	EP900ILC-50

N5C090-60	EP900ILC-60

P5C090-50	EP900IPC-50

P5C090-60	EP900IPC-60

TD5C090-60	EP900IDI-60

TN5C090-60	EP900ILI-60

TP5C090-60	EP900IPI-60

DPLD910-12	EP910IDC-12

DPLD910-15	EP910IDC-15

DPLD910-25	EP910IDC-25

NPLD910-12	EP910ILC-12

NPLD910-15	EP910ILC-15

NPLD910-25	EP910ILC-25

PPLD910-12	EP910IPC-12

PPLD910-15	EP910IPC-15

PPLD910-25	EP910IPC-25

TDPLD910-25	EP910IDI-25

TNPLD910-12	EP910ILI-12

TNPLD910-15	EP910ILI-15

TNPLD910-25	EP910ILI-25

Intel Ordering Code:	Altera Ordering Code:

D5C060-45	EP600IDC-45

D5C060-55	EP600IDC-55

MD5C060-55	EP600IDM883B-55

N5C060-45	EP600ILC-45

N5C060-55	EP600ILC-55

P5C060-45	EP600IPC-45

P5C060-55	EP600IPC-55

TD5C060-55	EP600IDI-55

TN5C060-55	EP600ILI-55

TP5C060-55	EP600IPI-55

DPLD610-10	EP610IDC-10

DPLD610-15	EP610IDC-15

DPLD610-25	EP610IDC-25

MDPLD610-15	EP610IDM883B-15

MDPLD610-25	EP610IDM883B-25

MDPLD610-35	EP610IDM883B-35

NPLD610-10	EP610ILC-10

NPLD610-15	EP610ILC-15

NPLD610-25	EP610ILC-25

PPLD610-10	EP610IPC-10

PPLD610-15	EP610IPC-15

PPLD610-25	EP610IPC-25

TNPLD610-12	EP610ILI-12

TNPLD610-15	EP610ILI-15

TNPLD610-25	EP610ILI-25

Intel Ordering Code:	Altera Ordering Code:

D5C032-30	EP320IDC-30

D5C032-35	EP320IDC-35

D5C032-40	EP320IDC-40

P5C032-30	EP320IPC-30

P5C032-35	EP320IPC-35

P5C032-40	EP320IPC-40

TD5C032-35	EP320IDI-35

TP5C032-35	EP320IPI-35

TP5C032-40	EP320IPI-40

D85C220-80	EP220DC-10A

D85C220-66	EP220DC-12

MD85C220-66	EP220DM883B-15

MD85C220-50	EP220DM883B-20

N85C220-100	EP220LC-7A

N85C220-80	EP220LC-10A

N85C220-7	EP220LC-7

N85C220-66	EP220LC-12

N85C220-10	EP220LC-10

P85C220-80	EP220PC-10A

P85C220-66	EP220PC-12

P85C220-7	EP220PC-7

P85C220-10	EP220PC-10

TN85C220-66	EP220LI-12

Intel Ordering Code:	Altera Ordering Code:

N44FX740-10	EPX740LC44-10

N44FX740-12	EPX740LC44-12

N44FX740-15	EPX740LC44-15

N44FX740Z-10	EPX740LC44-10Z

N44FX740Z-15	EPX740LC44-15Z

TN44FX740-12	EPX740LI44-12

N68FX740-10	EPX740LC68-10

N68FX740-12	EPX740LC68-12

N68FX740-15	EPX740LC68-15

N68FX740Z-10	EPX740LC68-10Z

N68FX740Z-15	EPX740LC68-15Z

TN68FX740-12	EPX740LI68-12

NFX780-10	EPX780LC84-10

NFX780-12	EPX780LC84-12

NFX780-15	EPX780LC84-15

NFX780Z-10	EPX780LC84-10Z

NFX780Z-15	EPX780LC84-15Z

KUFX780-10	EPX780QC132-10

KUFX780-12	EPX780QC132-12

KUFX780-15	EPX780QC132-15

KUFX780Z-10	EPX780QC132-10Z

KUFX780Z-15	EPX780QC132-15Z

TUFX780-15	EPX780QI132-15

SBFX8160-10	EPX8160QC208-10

SBFX8160-12	EPX8160QC208-12


EPM5016 EPLDs

The EPM5016 EPLD is a single-LAB MAX 5000 CMOS EPLD that is optimized for speed and high-output-current applications. It can integrate multiple SSI and MSI TTL and 74HC devices, and can replace any 20-pin PAL or PLA device. The EPM5016 EPLD has 8 bidirectional pins, 16 logic cells, and 32 expander product terms. It is available in 20-pin J-lead, DIP, and SOIC packages with 8 I/O pins.

See also:

MAX 5000 EPLD Selection Guide

Recommended reading:

AN20 (Fast Bus Controllers with the EPM5016 MAX EPLD)

AN26 (EPLD/MPLD Design Guidelines)

AN42 (Metastability in Altera Devices)

AB9 (Asynchronous Latches in Classic, MAX & STG EPLDs)

AB60 (Estimating a Design Fit)

AB77 (Fitting Complex Designs in MAX 5000 EPLDs)

AB87 (Troubleshooting Functional Problems in EPLDs)

AB89 (Minimizing Output Switching Noise in Altera EPLDs)

AB91 (External Clock Sources for Altera EPLDs)

AB94 (Solutions to Design Timing Problems for Altera EPLDs)

AB95 (Designing Phase-Locked Loops with Altera EPLDs)

AB100 (Understanding Classic, MAX 5000 & MAX 7000 Timing)

Altera Device Package Outlines Data Sheet

Operating Requirements for Altera Devices Data Sheet

Function	LCell	J-Lead	DIP	SOIC

Input/GCLK	-	7	2	2

Input	-	4	19	19

Input	-	5	20	20

Input	-	6	1	1

Input	-	14	9	9

Input	-	15	10	10

Input	-	16	11	11

Input	-	17	12	12

I/O or Buried	1	8	3	3

I/O or Buried	2	-	-	-

I/O or Buried	3	9	4	4

I/O or Buried	4	-	-	-

I/O or Buried	5	12	7	7

I/O or Buried	6	-	-	-

I/O or Buried	7	13	8	8

I/O or Buried	8	-	-	-

I/O or Buried	9	18	13	13

I/O or Buried	10	-	-	-

I/O or Buried	11	19	14	14

I/O or Buried	12	-	-	-

I/O or Buried	13	2	17	17

I/O or Buried	14	-	-	-

I/O or Buried	15	3	18	18

I/O or Buried	16	-	-	-

Function	LCell	J-Lead	DIP	SOIC

VCC	-	1	5	5

VCC	-	10	16	16

GND	-	11	6	6

GND	-	20	15	15


EPM5032 EPLDs

The EPM5032 EPLD is a single-LAB MAX 5000 CMOS EPLD that is optimized for speed. It can integrate multiple SSI and MSI TTL and 74HC devices, and can replace any 20-pin PAL or PLA device. The EPM5032 EPLD allows up to 24 inputs or 16 outputs, and has 32 logic cells and 64 expander product terms. It is available in 28-pin J-lead, DIP, and SOIC packages, as shown in the table below. For complete information on EPM5032 EPLDs, refer to the current Altera Data Book.

See also:

MAX 5000 EPLD Selection Guide

Recommended reading:

AN16 (Integrating PAL, GAL & PLA Devices with the EPM5032 MAX EPLD)

AN26 (EPLD/MPLD Design Guidelines)

AN42 (Metastability in Altera Devices)

AB9 (Asynchronous Latches in Classic, MAX & STG EPLDs)

AB60 (Estimating a Design Fit)

AB77 (Fitting Complex Designs in MAX 5000 EPLDs)

AB87 (Troubleshooting Functional Problems in EPLDs)

AB89 (Minimizing Output Switching Noise in Altera EPLDs)

AB91 (External Clock Sources for Altera EPLDs)

AB94 (Solutions to Design Timing Problems for Altera EPLDs)

AB95 (Designing Phase-Locked Loops with Altera EPLDs)

AB100 (Understanding Classic, MAX 5000 & MAX 7000 Timing)

Altera Device Package Outlines Data Sheet

Operating Requirements for Altera Devices Data Sheet

Function	LCell	J-Lead	DIP	SOIC

Input/GCLK	-	9	2	2

Input	-	6	27	27

Input	-	7	28	28

Input	-	8	1	1

Input	-	20	13	13

Input	-	21	14	14

Input	-	22	15	15

Input	-	23	16	16

I/O or Buried	1	10	3	3

I/O or Buried	2	-	-	-

I/O or Buried	3	11	4	4

I/O or Buried	4	-	-	-

I/O or Buried	5	12	5	5

I/O or Buried	6	-	-	-

I/O or Buried	7	13	6	6

I/O or Buried	8	-	-	-

I/O or Buried	9	16	9	9

I/O or Buried	10	-	-	-

I/O or Buried	11	17	10	10

I/O or Buried	12	-	-	-

I/O or Buried	13	18	11	11

I/O or Buried	14	-	-	-

I/O or Buried	15	19	12	12

I/O or Buried	16	-	-	-

Function	LCell	J-Lead	DIP	SOIC

I/O or Buried	17	24	17	17

I/O or Buried	18	-	-	-

I/O or Buried	19	25	18	18

I/O or Buried	20	-	-	-

I/O or Buried	21	26	19	19

I/O or Buried	22	-	-	-

I/O or Buried	23	27	20	20

I/O or Buried	24	-	-	-

I/O or Buried	25	2	23	23

I/O or Buried	26	-	-	-

I/O or Buried	27	3	24	24

I/O or Buried	28	-	-	-

I/O or Buried	29	4	25	25

I/O or Buried	30	-	-	-

I/O or Buried	31	5	26	26

I/O or Buried	32	-	-	-

VCC	-	1	7	7

VCC	-	14	22	22

GND	-	15	8	8

GND	-	28	21	21


EPS464 EPLDs

The high-performance EPS464 EPLD is ideal for custom waveform generation and state machine designs. The EPS464 EPLD has 32 I/O pins, 4 dedicated input pins, and 64 logic cells, as shown in the table below. It is available in 44-pin QFP and J-lead packages.

See also:

MAX 5000 EPLD Selection Guide

Recommended reading:

AN25 (Controlling Complex CCD Imaging Systems with the EPS464 STG EPLD)

AN26 (EPLD/MPLD Design Guidelines)

AN42 (Metastability in Altera Devices)

AB9 (Asynchronous Latches in Classic, MAX & STG EPLDs)

AB60 (Estimating a Design Fit)

AB87 (Troubleshooting Functional Problems in EPLDs)

AB89 (Minimizing Output Switching Noise in Altera EPLDs)

AB91 (External Clock Sources for Altera EPLDs)

AB94 (Solutions to Design Timing Problems for Altera EPLDs)

AB95 (Designing Phase-Locked Loops with Altera EPLDs)

AB100 (Understanding Classic, MAX 5000 & MAX 7000 Timing)

Altera Device Package Outlines Data Sheet

Operating Requirements for Altera Devices Data Sheet

QFP Carrier & Development Socket Data Sheet

Function	LCell	QFP	J-Lead

Input/GCLK	-	37	43

Input/GCLRn	-	39	1

Input/GPREn	-	38	44

Input/OEn	-	40	2

I/O or Buried	1	42	4

I/O or Buried	2	43	5

I/O or Buried	3	44	6

I/O or Buried	4	1	7

I/O or Buried	5	2	8

I/O or Buried	6	3	9

I/O or Buried	7	5	11

I/O or Buried	8	6	12

I/O or Buried	9	7	13

I/O or Buried	10	8	14

I/O or Buried	11	10	16

I/O or Buried	12	11	17

I/O or Buried	13	12	18

I/O or Buried	14	13	19

I/O or Buried	15	14	20

I/O or Buried	16	15	21

I/O or Buried	17	35	41

I/O or Buried	18	34	40

I/O or Buried	19	33	39

I/O or Buried	20	32	38

Function	LCell	QFP	J-Lead

I/O or Buried	21	31	37

I/O or Buried	22	30	36

I/O or Buried	23	28	34

I/O or Buried	24	27	33

I/O or Buried	25	26	32

I/O or Buried	26	25	31

I/O or Buried	27	23	29

I/O or Buried	28	22	28

I/O or Buried	29	21	27

I/O or Buried	30	20	26

I/O or Buried	31	19	25

I/O or Buried	32	18	24

I/O or Buried	33	-	-

I/O or Buried	34	-	-

I/O or Buried	35	-	-

I/O or Buried	36	-	-

I/O or Buried	37	-	-

I/O or Buried	38	-	-

I/O or Buried	39	-	-

I/O or Buried	40	-	-

I/O or Buried	41	-	-

I/O or Buried	42	-	-

I/O or Buried	43	-	-

I/O or Buried	44	-	-

I/O or Buried	45	-	-

Function	LCell	QFP	J-Lead

I/O or Buried	46	-	-

I/O or Buried	47	-	-

I/O or Buried	48	-	-

I/O or Buried	49	-	-

I/O or Buried	50	-	-

I/O or Buried	51	-	-

I/O or Buried	52	-	-

I/O or Buried	53	-	-

I/O or Buried	54	-	-

I/O or Buried	55	-	-

I/O or Buried	56	-	-

I/O or Buried	57	-	-

I/O or Buried	58	-	-

I/O or Buried	59	-	-

I/O or Buried	60	-	-

I/O or Buried	61	-	-

I/O or Buried	62	-	-

I/O or Buried	63	-	-

I/O or Buried	64	-	-

VCC	-	9	3

VCC	-	17	15

VCC	-	29	23

VCC	-	41	35

GND	-	4	10

GND	-	16	22

Function	LCell	QFP	J-Lead

GND	-	24	30

GND	-	36	42


EPM5064 EPLDs

The EPM5064 EPLD is a user-configurable, high-performance MAX 5000 EPLD that provides a high-density replacement for 74-series SSI and MSI TTL and CMOS logic. It can also integrate multiple 20- and 24-pin low-density PLDs. The EPM5064 EPLD allows up to 36 inputs or 28 outputs, and has 64 logic cells divided into 4 LABs. Each LAB also contains 32 expander product terms. The EPM5064 EPLD is available in 44-pin J-lead packages, as shown in the table below. For complete information on EPM5064 EPLDs, refer to the current Altera Data Book.

See also:

MAX 5000 EPLD Selection Guide

Recommended reading:

AN21 (Designing a FIFO Controller with an EPM5064 MAX EPLD)

AN26 (EPLD/MPLD Design Guidelines)

AN27 (Implementing EISA Interfaces with MAX EPLDs)

AN42 (Metastability in Altera Devices)

AB9 (Asynchronous Latches in Classic, MAX & STG EPLDs)

AB60 (Estimating a Design Fit)

AB77 (Fitting Complex Designs in MAX 5000 EPLDs)

AB84 (DMA Controller with the EPM5064 MAX EPLD)

AB87 (Troubleshooting Functional Problems in EPLDs)

AB89 (Minimizing Output Switching Noise in Altera EPLDs)

AB91 (External Clock Sources for Altera EPLDs)

AB94 (Solutions to Design Timing Problems for Altera EPLDs)

AB95 (Designing Phase-Locked Loops with Altera EPLDs)

AB100 (Understanding Classic, MAX 5000 & MAX 7000 Timing)

Altera Device Package Outlines Data Sheet

Operating Requirements for Altera Devices Data Sheet

Function	LCell	LAB	J-Lead

Input/GCLK	-	-	34

Input	-	-	9

Input	-	-	11

Input	-	-	12

Input	-	-	13

Input	-	-	31

Input	-	-	33

Input	-	-	35

I/O or Buried	1	A	2

I/O or Buried	2	A	4

I/O or Buried	3	A	5

I/O or Buried	4	A	6

I/O or Buried	5	A	7

I/O or Buried	6	A	8

I/O or Buried	7	A	-

I/O or Buried	8	A	-

I/O or Buried	9	A	-

I/O or Buried	10	A	-

I/O or Buried	11	A	-

I/O or Buried	12	A	-

I/O or Buried	13	A	-

I/O or Buried	14	A	-

I/O or Buried	15	A	-

I/O or Buried	16	A	-

Function	LCell	LAB	J-Lead

I/O or Buried	17	B	15

I/O or Buried	18	B	16

I/O or Buried	19	B	17

I/O or Buried	20	B	18

I/O or Buried	21	B	19

I/O or Buried	22	B	20

I/O or Buried	23	B	22

I/O or Buried	24	B	23

I/O or Buried	25	B	-

I/O or Buried	26	B	-

I/O or Buried	27	B	-

I/O or Buried	28	B	-

I/O or Buried	29	B	-

I/O or Buried	30	B	-

I/O or Buried	31	B	-

I/O or Buried	32	B	-

I/O or Buried	33	C	24

I/O or Buried	34	C	26

I/O or Buried	35	C	27

I/O or Buried	36	C	28

I/O or Buried	37	C	29

I/O or Buried	38	C	30

I/O or Buried	39	C	-

I/O or Buried	40	C	-

I/O or Buried	41	C	-

Function	LCell	LAB	J-Lead

I/O or Buried	42	C	-

I/O or Buried	43	C	-

I/O or Buried	44	C	-

I/O or Buried	45	C	-

I/O or Buried	46	C	-

I/O or Buried	47	C	-

I/O or Buried	48	C	-

I/O or Buried	49	D	37

I/O or Buried	50	D	38

I/O or Buried	51	D	39

I/O or Buried	52	D	40

I/O or Buried	53	D	41

I/O or Buried	54	D	42

I/O or Buried	55	D	44

I/O or Buried	56	D	1

I/O or Buried	57	D	-

I/O or Buried	58	D	-

I/O or Buried	59	D	-

I/O or Buried	60	D	-

I/O or Buried	61	D	-

I/O or Buried	62	D	-

I/O or Buried	63	D	-

I/O or Buried	64	D	-

VCC	-	-	3

VCC	-	-	14

Function	LCell	LAB	J-Lead

VCC	-	-	25

VCC	-	-	36

GND	-	-	10

GND	-	-	21

GND	-	-	32

GND	-	-	43


EPM5128 EPLDs
EPM5128/EPM5128A EPLDs

The EPM5128 and EPM5128A EPLDs are user-configurable, high-performance MAX 5000 EPLDs that can replace over 60 TTL MSI and SSI components and integrate multiple 20- and 24-pin low-density PLDs. EPM5128 and EPM5128A EPLDs allow up to 60 inputs or 52 outputs and have 128 logic cells divided into 8 LABs. Each LAB also contains 32 expander product terms. EPM5128 and EPM5128A EPLDs are available in 68-pin J-lead and PGA packages, as shown in the table below. For complete information on EPM5128 and 5128A EPLDs, refer to the current Altera Data Book.

See also:

MAX 5000 EPLD Selection Guide

Recommended reading:

AN26 (EPLD/MPLD Design Guidelines)

AN42 (Metastability in Altera Devices)

AB9 (Asynchronous Latches in Classic, MAX & STG EPLDs)

AB60 (Estimating a Design Fit)

AB77 (Fitting Complex Designs in MAX 5000 EPLDs)

AB87 (Troubleshooting Functional Problems in EPLDs)

AB89 (Minimizing Output Switching Noise in Altera EPLDs)

AB91 (External Clock Sources for Altera EPLDs)

AB94 (Solutions to Design Timing Problems for Altera EPLDs)

AB95 (Designing Phase-Locked Loops with Altera EPLDs)

AB100 (Understanding Classic, MAX 5000 & MAX 7000 Timing)

Altera Device Package Outlines Data Sheet

Operating Requirements for Altera Devices Data Sheet

Function	LCell	LAB	J-Lead	PGA

Input/GCLK	-	-	1	B6

Input	-	-	2	A6

Input	-	-	32	L4

Input	-	-	34	L5

Input	-	-	35	K6

Input	-	-	36	L6

Input	-	-	66	A8

Input	-	-	68	A7

I/O or Buried	1	A	4	A5

I/O or Buried	2	A	5	B4

I/O or Buried	3	A	6	A4

I/O or Buried	4	A	7	B3

I/O or Buried	5	A	8	A3

I/O or Buried	6	A	9	A2

I/O or Buried	7	A	10	B2

I/O or Buried	8	A	11	B1

I/O or Buried	9	A	-	-

I/O or Buried	10	A	-	-

I/O or Buried	11	A	-	-

I/O or Buried	12	A	-	-

I/O or Buried	13	A	-	-

I/O or Buried	14	A	-	-

I/O or Buried	15	A	-	-

I/O or Buried	16	A	-	-

Function	LCell	LAB	J-Lead	PGA

I/O or Buried	17	B	12	C2

I/O or Buried	18	B	13	C1

I/O or Buried	19	B	14	D2

I/O or Buried	20	B	15	D1

I/O or Buried	21	B	17	E1

I/O or Buried	22	B	-	-

I/O or Buried	23	B	-	-

I/O or Buried	24	B	-	-

I/O or Buried	25	B	-	-

I/O or Buried	26	B	-	-

I/O or Buried	27	B	-	-

I/O or Buried	28	B	-	-

I/O or Buried	29	B	-	-

I/O or Buried	30	B	-	-

I/O or Buried	31	B	-	-

I/O or Buried	32	B	-	-

I/O or Buried	33	C	18	F2

I/O or Buried	34	C	19	F1

I/O or Buried	35	C	21	G1

I/O or Buried	36	C	22	H2

I/O or Buried	37	C	23	H1

I/O or Buried	38	C	-	-

I/O or Buried	39	C	-	-

I/O or Buried	40	C	-	-

I/O or Buried	41	C	-	-

Function	LCell	LAB	J-Lead	PGA

I/O or Buried	42	C	-	-

I/O or Buried	43	C	-	-

I/O or Buried	44	C	-	-

I/O or Buried	45	C	-	-

I/O or Buried	46	C	-	-

I/O or Buried	47	C	-	-

I/O or Buried	48	C	-	-

I/O or Buried	49	D	24	J2

I/O or Buried	50	D	25	J1

I/O or Buried	51	D	26	K1

I/O or Buried	52	D	27	K2

I/O or Buried	53	D	28	L2

I/O or Buried	54	D	29	K3

I/O or Buried	55	D	30	L3

I/O or Buried	56	D	31	K4

I/O or Buried	57	D	-	-

I/O or Buried	58	D	-	-

I/O or Buried	59	D	-	-

I/O or Buried	60	D	-	-

I/O or Buried	61	D	-	-

I/O or Buried	62	D	-	-

I/O or Buried	63	D	-	-

I/O or Buried	64	D	-	-

I/O or Buried	65	E	38	L7

I/O or Buried	66	E	39	K8

Function	LCell	LAB	J-Lead	PGA

I/O or Buried	67	E	40	L8

I/O or Buried	68	E	41	K9

I/O or Buried	69	E	42	L9

I/O or Buried	70	E	43	L10

I/O or Buried	71	E	44	K10

I/O or Buried	72	E	45	K11

I/O or Buried	73	E	-	-

I/O or Buried	74	E	-	-

I/O or Buried	75	E	-	-

I/O or Buried	76	E	-	-

I/O or Buried	77	E	-	-

I/O or Buried	78	E	-	-

I/O or Buried	79	E	-	-

I/O or Buried	80	E	-	-

I/O or Buried	81	F	46	J10

I/O or Buried	82	F	47	J11

I/O or Buried	83	F	48	H10

I/O or Buried	84	F	49	H11

I/O or Buried	85	F	51	G11

I/O or Buried	86	F	-	-

I/O or Buried	87	F	-	-

I/O or Buried	88	F	-	-

I/O or Buried	89	F	-	-

I/O or Buried	90	F	-	-

I/O or Buried	91	F	-	-

Function	LCell	LAB	J-Lead	PGA

I/O or Buried	92	F	-	-

I/O or Buried	93	F	-	-

I/O or Buried	94	F	-	-

I/O or Buried	95	F	-	-

I/O or Buried	96	F	-	-

I/O or Buried	97	G	52	F10

I/O or Buried	98	G	53	F11

I/O or Buried	99	G	55	E11

I/O or Buried	100	G	56	D10

I/O or Buried	101	G	57	D11

I/O or Buried	102	G	-	-

I/O or Buried	103	G	-	-

I/O or Buried	104	G	-	-

I/O or Buried	105	G	-	-

I/O or Buried	106	G	-	-

I/O or Buried	107	G	-	-

I/O or Buried	108	G	-	-

I/O or Buried	109	G	-	-

I/O or Buried	110	G	-	-

I/O or Buried	111	G	-	-

I/O or Buried	112	G	-	-

I/O or Buried	113	H	58	C10

I/O or Buried	114	H	59	C11

I/O or Buried	115	H	60	B11

I/O or Buried	116	H	61	B10

Function	LCell	LAB	J-Lead	PGA

I/O or Buried	117	H	62	A10

I/O or Buried	118	H	63	B9

I/O or Buried	119	H	64	A9

I/O or Buried	120	H	65	B8

I/O or Buried	121	H	-	-

I/O or Buried	122	H	-	-

I/O or Buried	123	H	-	-

I/O or Buried	124	H	-	-

I/O or Buried	125	H	-	-

I/O or Buried	126	H	-	-

I/O or Buried	127	H	-	-

I/O or Buried	128	H	-	-

VCC	-	-	3	B5

VCC	-	-	20	E10

VCC	-	-	37	G2

VCC	-	-	54	K7

GND	-	-	16	B7

GND	-	-	33	E2

GND	-	-	50	G10

GND	-	-	67	K5


EPM5130 EPLDs

The EPM5130 EPLD is a user-configurable, high-performance MAX 5000 EPLD that is optimized for pin -intensive designs. It provides a high-density replacement for over 60 TTL MSI and SSI components. The EPM5130 EPLD is available in a 84-pin J-lead package that allows up to 68 inputs or 48 outputs; and in 100-pin QFP and PGA packages that allow up to 84 inputs or 64 outputs. The EPM5130 EPLD has 128 logic cells divided into 8 LABs. Each LAB also contains 32 expander product terms. For complete information on EPM5130 EPLDs, refer to the current Altera Data Book.

See also:

MAX 5000 EPLD Selection Guide

Recommended reading:

AN17 (Integrating an Intelligent I/O Subsystem with a Single EPM5130 EPLD)

AN26 (EPLD/MPLD Design Guidelines)

AN27 (Implementing EISA Interfaces with MAX EPLDs)

AN42 (Metastability in Altera Devices)

AB9 (Asynchronous Latches in Classic, MAX & STG EPLDs)

AB60 (Estimating a Design Fit)

AB77 (Fitting Complex Designs in MAX 5000 EPLDs)

AB87 (Troubleshooting Functional Problems in EPLDs)

AB89 (Minimizing Output Switching Noise in Altera EPLDs)

AB91 (External Clock Sources for Altera EPLDs)

AB94 (Solutions to Design Timing Problems for Altera EPLDs)

AB100 (Understanding Classic, MAX 5000 & MAX 7000 Timing)

Altera Device Package Outlines Data Sheet

Operating Requirements for Altera Devices Data Sheet

Function	LCell	LAB	QFP	J-Lead	PGA

Input/GCLK	-	-	16	1	C7

Input	-	-	9	2	A10

Input	-	-	10	5	B9

Input	-	-	11	6	A9

Input	-	-	14	7	A8

Input	-	-	15	36	B7

Input	-	-	17	37	A7

Input	-	-	20	38	C6

Input	-	-	21	41	A5

Input	-	-	22	42	B5

Input	-	-	59	43	N4

Input	-	-	60	44	M5

Input	-	-	61	47	N5

Input	-	-	64	48	N6

Input	-	-	65	49	M7

Input	-	-	66	78	L7

Input	-	-	67	79	N7

Input	-	-	70	80	L8

Input	-	-	71	83	N9

Input	-	-	72	84	M9

I/O or Buried	1	A	1	8	B13

I/O or Buried	2	A	2	9	C12

I/O or Buried	3	A	3	10	A13

I/O or Buried	4	A	4	11	B12

Function	LCell	LAB	QFP	J-Lead	PGA

I/O or Buried	5	A	5	12	A12

I/O or Buried	6	A	6	13	B11

I/O or Buried	7	A	7	-	A11

I/O or Buried	8	A	8	-	B10

I/O or Buried	9	A	-	-	-

I/O or Buried	10	A	-	-	-

I/O or Buried	11	A	-	-	-

I/O or Buried	12	A	-	-	-

I/O or Buried	13	A	-	-	-

I/O or Buried	14	A	-	-	-

I/O or Buried	15	A	-	-	-

I/O or Buried	16	A	-	-	-

I/O or Buried	17	B	23	14	A4

I/O or Buried	18	B	24	15	B4

I/O or Buried	19	B	25	16	A3

I/O or Buried	20	B	26	17	A2

I/O or Buried	21	B	27	18	B3

I/O or Buried	22	B	28	21	A1

I/O or Buried	23	B	29	-	B2

I/O or Buried	24	B	30	-	B1

I/O or Buried	25	B	-	-	-

I/O or Buried	26	B	-	-	-

I/O or Buried	27	B	-	-	-

I/O or Buried	28	B	-	-	-

I/O or Buried	29	B	-	-	-

Function	LCell	LAB	QFP	J-Lead	PGA

I/O or Buried	30	B	-	-	-

I/O or Buried	31	B	-	-	-

I/O or Buried	32	B	-	-	-

I/O or Buried	33	C	31	22	C2

I/O or Buried	34	C	32	25	C1

I/O or Buried	35	C	33	26	D2

I/O or Buried	36	C	34	27	D1

I/O or Buried	37	C	35	28	E2

I/O or Buried	38	C	36	29	E1

I/O or Buried	39	C	39	-	F1

I/O or Buried	40	C	40	-	G2

I/O or Buried	41	C	-	-	-

I/O or Buried	42	C	-	-	-

I/O or Buried	43	C	-	-	-

I/O or Buried	44	C	-	-	-

I/O or Buried	45	C	-	-	-

I/O or Buried	46	C	-	-	-

I/O or Buried	47	C	-	-	-

I/O or Buried	48	C	-	-	-

I/O or Buried	49	D	41	30	G3

I/O or Buried	50	D	42	31	G1

I/O or Buried	51	D	45	32	H3

I/O or Buried	52	D	46	33	J1

I/O or Buried	53	D	47	34	J2

I/O or Buried	54	D	48	35	K1

Function	LCell	LAB	QFP	J-Lead	PGA

I/O or Buried	55	D	49	-	K2

I/O or Buried	56	D	50	-	L1

I/O or Buried	57	D	-	-	-

I/O or Buried	58	D	-	-	-

I/O or Buried	59	D	-	-	-

I/O or Buried	60	D	-	-	-

I/O or Buried	61	D	-	-	-

I/O or Buried	62	D	-	-	-

I/O or Buried	63	D	-	-	-

I/O or Buried	64	D	-	-	-

I/O or Buried	65	E	51	50	M1

I/O or Buried	66	E	52	51	L2

I/O or Buried	67	E	53	52	N1

I/O or Buried	68	E	54	53	M2

I/O or Buried	69	E	55	54	N2

I/O or Buried	70	E	56	55	M3

I/O or Buried	71	E	57	-	N3

I/O or Buried	72	E	58	-	M4

I/O or Buried	73	E	-	-	-

I/O or Buried	74	E	-	-	-

I/O or Buried	75	E	-	-	-

I/O or Buried	76	E	-	-	-

I/O or Buried	77	E	-	-	-

I/O or Buried	78	E	-	-	-

I/O or Buried	79	E	-	-	-

Function	LCell	LAB	QFP	J-Lead	PGA

I/O or Buried	80	E	-	-	-

I/O or Buried	81	F	73	56	N10

I/O or Buried	82	F	74	57	M10

I/O or Buried	83	F	75	58	N11

I/O or Buried	84	F	76	59	N12

I/O or Buried	85	F	77	60	M11

I/O or Buried	86	F	78	63	N13

I/O or Buried	87	F	79	-	M12

I/O or Buried	88	F	80	-	M13

I/O or Buried	89	F	-	-	-

I/O or Buried	90	F	-	-	-

I/O or Buried	91	F	-	-	-

I/O or Buried	92	F	-	-	-

I/O or Buried	93	F	-	-	-

I/O or Buried	94	F	-	-	-

I/O or Buried	95	F	-	-	-

I/O or Buried	96	F	-	-	-

I/O or Buried	97	G	81	64	L12

I/O or Buried	98	G	82	67	L13

I/O or Buried	99	G	83	68	K12

I/O or Buried	100	G	84	69	K13

I/O or Buried	101	G	85	70	J12

I/O or Buried	102	G	86	71	J13

I/O or Buried	103	G	89	-	H13

I/O or Buried	104	G	90	-	G12

Function	LCell	LAB	QFP	J-Lead	PGA

I/O or Buried	105	G	-	-	-

I/O or Buried	106	G	-	-	-

I/O or Buried	107	G	-	-	-

I/O or Buried	108	G	-	-	-

I/O or Buried	109	G	-	-	-

I/O or Buried	110	G	-	-	-

I/O or Buried	111	G	-	-	-

I/O or Buried	112	G	-	-	-

I/O or Buried	113	H	91	72	G11

I/O or Buried	114	H	92	73	G13

I/O or Buried	115	H	95	74	F11

I/O or Buried	116	H	96	75	E13

I/O or Buried	117	H	97	76	E12

I/O or Buried	118	H	98	77	D13

I/O or Buried	119	H	99	-	D12

I/O or Buried	120	H	100	-	C13

I/O or Buried	121	H	-	-	-

I/O or Buried	122	H	-	-	-

I/O or Buried	123	H	-	-	-

I/O or Buried	124	H	-	-	-

I/O or Buried	125	H	-	-	-

I/O or Buried	126	H	-	-	-

I/O or Buried	127	H	-	-	-

I/O or Buried	128	H	-	-	-

VCC	-	-	18	3	A6

Function	LCell	LAB	QFP	J-Lead	PGA

VCC	-	-	19	4	B6

VCC	-	-	43	23	F12

VCC	-	-	44	24	F13

VCC	-	-	68	45	H1

VCC	-	-	69	46	H2

VCC	-	-	93	65	M8

VCC	-	-	94	66	N8

GND	-	-	12	19	B8

GND	-	-	13	20	C8

GND	-	-	37	39	F2

GND	-	-	38	40	F3

GND	-	-	62	61	H11

GND	-	-	63	62	H12

GND	-	-	87	81	L6

GND	-	-	88	82	M6


EPM5192 EPLDs

The EPM5192 EPLD is a user-configurable, high-performance MAX 5000 EPLD that provides a high-density replacement for over 100 TTL MSI and SSI components. The EPM5192 EPLD allows up to 72 inputs or 64 outputs, and has 192 logic cells divided into 12 LABs. Each LAB also contains 32 expander product terms. The EPM5192 EPLD is available in 84-pin J-lead and PGA packages, as shown in the table below. For complete information on EPM5192 EPLDs, refer to the current Altera Data Book.

See also:

MAX 5000 EPLD Selection Guide

Recommended reading:

AN26 (EPLD/MPLD Design Guidelines)

AN42 (Metastability in Altera Devices)

AB9 (Asynchronous Latches in Classic, MAX & STG EPLDs)

AB60 (Estimating a Design Fit)

AB77 (Fitting Complex Designs in MAX 5000 EPLDs)

AB87 (Troubleshooting Functional Problems in EPLDs)

AB89 (Minimizing Output Switching Noise in Altera EPLDs)

AB91 (External Clock Sources for Altera EPLDs)

AB94 (Solutions to Design Timing Problems for Altera EPLDs)

AB100 (Understanding Classic, MAX 5000 & MAX 7000 Timing)

Altera Device Package Outlines Data Sheet

Operating Requirements for Altera Devices Data Sheet

Function	LCell	LAB	J-Lead	PGA

Input/GCLK	-	-	1	A6

Input	-	-	2	A5

Input	-	-	41	K6

Input	-	-	42	J6

Input	-	-	43	J7

Input	-	-	44	L7

Input	-	-	83	C7

Input	-	-	84	C6

I/O or Buried	1	A	4	C5

I/O or Buried	2	A	5	A4

I/O or Buried	3	A	6	B4

I/O or Buried	4	A	7	A3

I/O or Buried	5	A	8	A2

I/O or Buried	6	A	9	B3

I/O or Buried	7	A	10	A1

I/O or Buried	8	A	11	B2

I/O or Buried	9	A	-	-

I/O or Buried	10	A	-	-

I/O or Buried	11	A	-	-

I/O or Buried	12	A	-	-

I/O or Buried	13	A	-	-

I/O or Buried	14	A	-	-

I/O or Buried	15	A	-	-

I/O or Buried	16	A	-	-

Function	LCell	LAB	J-Lead	PGA

I/O or Buried	17	B	12	C2

I/O or Buried	18	B	13	B1

I/O or Buried	19	B	14	C1

I/O or Buried	20	B	15	D2

I/O or Buried	21	B	-	-

I/O or Buried	22	B	-	-

I/O or Buried	23	B	-	-

I/O or Buried	24	B	-	-

I/O or Buried	25	B	-	-

I/O or Buried	26	B	-	-

I/O or Buried	27	B	-	-

I/O or Buried	28	B	-	-

I/O or Buried	29	B	-	-

I/O or Buried	30	B	-	-

I/O or Buried	31	B	-	-

I/O or Buried	32	B	-	-

I/O or Buried	33	C	16	D1

I/O or Buried	34	C	17	E3

I/O or Buried	35	C	20	F2

I/O or Buried	36	C	21	F3

I/O or Buried	37	C	-	-

I/O or Buried	38	C	-	-

I/O or Buried	39	C	-	-

I/O or Buried	40	C	-	-

I/O or Buried	41	C	-	-

Function	LCell	LAB	J-Lead	PGA

I/O or Buried	42	C	-	-

I/O or Buried	43	C	-	-

I/O or Buried	44	C	-	-

I/O or Buried	45	C	-	-

I/O or Buried	46	C	-	-

I/O or Buried	47	C	-	-

I/O or Buried	48	C	-	-

I/O or Buried	49	D	22	G3

I/O or Buried	50	D	23	G1

I/O or Buried	51	D	25	F1

I/O or Buried	52	D	26	H1

I/O or Buried	53	D	-	-

I/O or Buried	54	D	-	-

I/O or Buried	55	D	-	-

I/O or Buried	56	D	-	-

I/O or Buried	57	D	-	-

I/O or Buried	58	D	-	-

I/O or Buried	59	D	-	-

I/O or Buried	60	D	-	-

I/O or Buried	61	D	-	-

I/O or Buried	62	D	-	-

I/O or Buried	63	D	-	-

I/O or Buried	64	D	-	-

I/O or Buried	65	E	27	H2

I/O or Buried	66	E	28	J1

Function	LCell	LAB	J-Lead	PGA

I/O or Buried	67	E	29	K1

I/O or Buried	68	E	30	J2

I/O or Buried	69	E	-	-

I/O or Buried	70	E	-	-

I/O or Buried	71	E	-	-

I/O or Buried	72	E	-	-

I/O or Buried	73	E	-	-

I/O or Buried	74	E	-	-

I/O or Buried	75	E	-	-

I/O or Buried	76	E	-	-

I/O or Buried	77	E	-	-

I/O or Buried	78	E	-	-

I/O or Buried	79	E	-	-

I/O or Buried	80	E	-	-

I/O or Buried	81	F	31	L1

I/O or Buried	82	F	32	K2

I/O or Buried	83	F	33	K3

I/O or Buried	84	F	34	L2

I/O or Buried	85	F	35	L3

I/O or Buried	86	F	36	K4

I/O or Buried	87	F	37	L4

I/O or Buried	88	F	38	J5

I/O or Buried	89	F	-	-

I/O or Buried	90	F	-	-

I/O or Buried	91	F	-	-

Function	LCell	LAB	J-Lead	PGA

I/O or Buried	92	F	-	-

I/O or Buried	93	F	-	-

I/O or Buried	94	F	-	-

I/O or Buried	95	F	-	-

I/O or Buried	96	F	-	-

I/O or Buried	97	G	46	L6

I/O or Buried	98	G	47	L8

I/O or Buried	99	G	48	K8

I/O or Buried	100	G	49	L9

I/O or Buried	101	G	50	L10

I/O or Buried	102	G	51	K9

I/O or Buried	103	G	52	L11

I/O or Buried	104	G	53	K10

I/O or Buried	105	G	-	-

I/O or Buried	106	G	-	-

I/O or Buried	107	G	-	-

I/O or Buried	108	G	-	-

I/O or Buried	109	G	-	-

I/O or Buried	110	G	-	-

I/O or Buried	111	G	-	-

I/O or Buried	112	G	-	-

I/O or Buried	113	H	54	J10

I/O or Buried	114	H	55	K11

I/O or Buried	115	H	56	J11

I/O or Buried	116	H	57	H10

Function	LCell	LAB	J-Lead	PGA

I/O or Buried	117	H	-	-

I/O or Buried	118	H	-	-

I/O or Buried	119	H	-	-

I/O or Buried	120	H	-	-

I/O or Buried	121	H	-	-

I/O or Buried	122	H	-	-

I/O or Buried	123	H	-	-

I/O or Buried	124	H	-	-

I/O or Buried	125	H	-	-

I/O or Buried	126	H	-	-

I/O or Buried	127	H	-	-

I/O or Buried	128	H	-	-

I/O or Buried	129	I	58	H11

I/O or Buried	130	I	59	F10

I/O or Buried	131	I	62	G9

I/O or Buried	132	I	63	F9

I/O or Buried	133	I	-	-

I/O or Buried	134	I	-	-

I/O or Buried	135	I	-	-

I/O or Buried	136	I	-	-

I/O or Buried	137	I	-	-

I/O or Buried	138	I	-	-

I/O or Buried	139	I	-	-

I/O or Buried	140	I	-	-

I/O or Buried	141	I	-	-

Function	LCell	LAB	J-Lead	PGA

I/O or Buried	142	I	-	-

I/O or Buried	143	I	-	-

I/O or Buried	144	I	-	-

I/O or Buried	145	J	64	F11

I/O or Buried	146	J	65	E11

I/O or Buried	147	J	67	E9

I/O or Buried	148	J	68	D11

I/O or Buried	149	J	-	-

I/O or Buried	150	J	-	-

I/O or Buried	151	J	-	-

I/O or Buried	152	J	-	-

I/O or Buried	153	J	-	-

I/O or Buried	154	J	-	-

I/O or Buried	155	J	-	-

I/O or Buried	156	J	-	-

I/O or Buried	157	J	-	-

I/O or Buried	158	J	-	-

I/O or Buried	159	J	-	-

I/O or Buried	160	J	-	-

I/O or Buried	161	K	69	D10

I/O or Buried	162	K	70	C11

I/O or Buried	163	K	71	B11

I/O or Buried	164	K	72	C10

I/O or Buried	165	K	-	-

I/O or Buried	166	K	-	-

Function	LCell	LAB	J-Lead	PGA

I/O or Buried	167	K	-	-

I/O or Buried	168	K	-	-

I/O or Buried	169	K	-	-

I/O or Buried	170	K	-	-

I/O or Buried	171	K	-	-

I/O or Buried	172	K	-	-

I/O or Buried	173	K	-	-

I/O or Buried	174	K	-	-

I/O or Buried	175	K	-	-

I/O or Buried	176	K	-	-

I/O or Buried	177	L	73	A11

I/O or Buried	178	L	74	B10

I/O or Buried	179	L	75	B9

I/O or Buried	180	L	76	A10

I/O or Buried	181	L	77	A9

I/O or Buried	182	L	78	B8

I/O or Buried	183	L	79	A8

I/O or Buried	184	L	80	B6

I/O or Buried	185	L	-	-

I/O or Buried	186	L	-	-

I/O or Buried	187	L	-	-

I/O or Buried	188	L	-	-

I/O or Buried	189	L	-	-

I/O or Buried	190	L	-	-

I/O or Buried	191	L	-	-

Function	LCell	LAB	J-Lead	PGA

I/O or Buried	192	L	-	-

VCC	-	-	3	B5

VCC	-	-	24	E10

VCC	-	-	45	G2

VCC	-	-	66	K7

GND	-	-	18	A7

GND	-	-	19	B7

GND	-	-	39	E1

GND	-	-	40	E2

GND	-	-	60	G10

GND	-	-	61	G11

GND	-	-	81	K5

GND	-	-	82	L5


MAX 5000 EPLD Selection Guide

The following table provides information on the MAX 5000 family of general-purpose EPLDs. MAX 5000 EPLDs are suitable for register-intensive random logic, and TTL and PAL integration.

For up-to-date information on device availability, contact Altera Marketing. For more information on the MAX 5000 devices, refer to the Altera Data Book.

EPLD	Package	Temp.	Speed	tPD1	fCNT	ICC3	ICC1	LCells	Ded.	I/O

Note (1)	Note (2)	Note (3)	Grade	(ns)	(MHz)	(mA)	(mA)	(Reg.)	Inputs

Active	Standby

EPM5016	20D,20P,20L,20S	C	-15	15	100.0	115	110	16	8	8

EPM5016	20D,20P,20L,20S	C	-17	17	83.3	115	110	16	8	8

EPM5016	20D,20P,20L,20S	C,I,M	-20	20	62.5	115	110	16	8	8

EPM5032	28D,28P,28J,28L,28S	C	-15	15	76.9	155	150	32	8	16

EPM5032	28D,28P,28J,28L,28S	C	-17	17	71.4	155	150	32	8	16

EPM5032	28D,28P,28J,28L,28S	C,I	-20	20	62.5	155	150	32	8	16

EPM5032	28D,28P,28J,28L,28S	C,I,M	-25	25	50.0	155	150	32	8	16

EPM5064	44J,44L	C	-1	25	50.0	135	125	64	8	28

EPM5064	44J,44L	C	-2	30	40.0	135	125	64	8	28

EPM5064	44J,44L	C,I,M	35	33.3	135	125	64	8	28

EPS464	44J,44L,44Q	C	-20	20	66.7	125	120	64	4	32

EPS464	44J,44L,44Q	C	-25	25	50.0	125	120	64	4	32

EPM5128	68J,68L,68G	C	-1	25	50.0	250	225	128	8	52

EPM5128	68J,68L,68G	C,I	-2	30	40.0	250	225	128	8	52

EPM5128	68J,68L,68G	C,I,M	35	33.3	250	225	128	8	52

EPM5128A	68L	C	-15	15	83.3	250	225	128	8	52

EPM5128A	68L	C	-20	20	66.7	250	225	128	8	52

EPM5130	84J,84L,100G,100Q	C	-1	25	50.0	275	250	128	20	48; 64

EPM5130	100W	C	-1	25	50.0	275	250	128	20	48; 64

EPM5130	84J,84L,100G,100Q	C,I	-2	30	40.0	275	250	128	20	48; 64

EPM5130	100W	C	-2	30	40.0	275	250	128	20	48; 64

EPM5130	84J,84L,100G,100Q	C,I,M	35	33.3	275	250	128	20	48; 64

EPM5130	100W	C,I,M	35	33.3	275	250	128	20	48; 64

EPM5192	84J,84L,84G	C	-1	25	50.0	380	360	192	8	64

EPM5192	84J,84L,84G	C	-2	30	40.0	380	360	192	8	64

EPM5192	84J,84L,84G	C,I,M	35	33.3	380	360	192	8	64

Recommended reading:

AN26 (EPLD/MPLD Design Guidelines)

AN42 (Metastability in Altera Devices)

AB9 (Asynchronous Latches in Classic, MAX & STG EPLDs)

AB46 (Selecting Sockets for J-Lead Packages)

AB60 (Estimating a Design Fit)

AB77 (Fitting Complex Designs in MAX 5000 EPLDs)

AB87 (Troubleshooting Functional Problems in EPLDs)

AB89 (Minimizing Output Switching Noise in Altera EPLDs)

AB91 (External Clock Sources for Altera EPLDs)

AB94 (Solutions to Design Timing Problems for Altera EPLDs)

AB100 (Understanding Classic, MAX 5000 & MAX 7000 Timing)

Altera Device Package Outlines Data Sheet

Operating Requirements for Altera Devices Data Sheet

QFP Carrier & Development Socket Data Sheet


EPC1064/EPC1064V Configuration EPROMs

The EPC1064 is a serial memory device that stores configuration data for SRAM-based Altera FLEX 8000 family devices. Because FLEX 8000 devices use SRAM cells, the configuration data must be reloaded whenever the system initializes, or whenever new configuration data is desired. The EPC1064 is a convenient and cost-effective way to store this configuration data. With a capacity of over 64 Kbits of data, a single EPC1064 can configure one EPF8452 device or multiple smaller FLEX 8000 devices in an AS configuration scheme.

The EPC1064V is 3.3-V version of the EPC1064 device. The EPC1064V meets the low power and voltage requirements of 3.3-V applications ranging from notebook computers to battery-operated, hand-held equipment.

The EPC1064 and EPC1064V Configuration EPROM devices are available in plastic one-time-programmable 8-pin DIP, 20-pin J-lead, and 32-pin QFP packages. For complete information on the EPC1064, refer to the current Altera Data Book.

Recommended reading:

AN33 (Configuring FLEX 8000 Devices)

AN38 (Configuring Multiple FLEX 8000 Devices)

Function	DIP	J-Lead	QFP

DATA	1	2	31

DCLK	2	4	2

OE	3	8	7

nCS	4	9	10

GND	5	10	12

nCASC	6	12	15

VCC	7	18	23

VCC	8	20	27


EPC1213 Configuration EPROM

The EPC1213 is a serial memory device that stores configuration data for SRAM-based Altera FLEX 8000 family devices. Because FLEX 8000 devices use SRAM cells, the configuration data must be reloaded whenever the system initializes, or whenever new configuration data is desired. The EPC1213 is a convenient and cost-effective way to store this configuration data. With a capacity of over 200 Kbits of data, a single EPC1213 can configure one EPF81188 device or multiple smaller FLEX 8000 devices in an AS configuration scheme.

The EPC1213 Configuration EPROM is available in plastic one-time-programmable 8-pin DIP and 20-pin J-lead packages. For complete information on the EPC1213, refer to the current Altera Data Book.

Recommended reading:

AN33 (Configuring FLEX 8000 Devices)

AN38 (Configuring Multiple FLEX 8000 Devices)

Function	DIP	J-Lead

DOUT	1	2

DCLK	2	4

OE	3	8

nCS	4	9

GND	5	10

nCASC	6	12

VCC	7	18

VCC	8	20


EPC1 Configuration EPROM

The EPC1 is a serial memory device that stores configuration data for SRAM-based Altera FLEX 10K and FLEX 8000 family devices. In SRAM-based devices, the configuration data must be reloaded whenever the system initializes, or whenever new configuration data is desired. With a capacity of over 1,064 Kbits of data, a single EPC1 can configure one or more FLEX10K and FLEX 8000 devices in a PS or AS configuration scheme, respectively.

MAX+PLUS II automatically generates a POF for every EPC1 in a project. MAX+PLUS II can combine the programming files for multiple FLEX devices into one or more EPC1 devices.

The EPC1 Configuration EPROM devices are available in UV-erasable ceramic and plastic one-time-programmable 8-pin DIP, and 20-pin J-lead packages. For complete information on the EPC1, refer to the current EPC1 Configuration EPROM for FLEX Devices Data Sheet.

Recommended reading:

AN33 (Configuring FLEX 8000 Devices)

AN38 (Configuring Multiple FLEX 8000 Devices)

AN59 (Configuring FLEX 10K Devices)

Function	DIP	J-Lead

DATA	1	2

DCLK	2	4

OE	3	8

nCS	4	9

GND	5	10

nCASC	6	12

VCC	7	18

VCC	8	20


EPF8282/EPF8282A Devices

The EPF8282 and EPF8282A, members of the FLEX 8000 device family, provide 282 registers, and a large number of storage elements for complex circuit applications.

The EPF8282 and EPF8282A are available in 84-pin J-lead packages with 64 I/O pins and 100-pin QFP packages with 74 I/O pins. They have 208 logic cells grouped into 26 LABs. These LABs are arranged into 2 rows and 13 columns. Each I/O element contains a bidirectional I/O buffer and a flipflop that can be used as either an input or output register. They also contain 4 dedicated fast inputs for synchronous control signals with large fan-outs. When used as outputs, the I/O registers provide fast Clock-to-output times; as inputs, they provide quick setup times. For complete information on the EPF8282 and EPF8282A devices, refer to the current FLEX 8000 Programmable Logic Device Family Data Sheet.

Altera recommends using the EPF8282A rather than the EPF8282 for new designs.

See also:

EPC1 Configuration EPROM

EPC1064/EPC1064V Configuration EPROM

EPC1213 Configuration EPROM

FLEX 8000 Device Selection Guide

Recommended reading:

AN26 (EPLD/MPLD Design Guidelines)

AN33 (Configuring FLEX 8000 Devices)

AN36 (Designing with FLEX 8000 Devices)

AN38 (Configuring Multiple FLEX 8000 Devices)

AB143 (Understanding FLEX 8000 Timing)

Operating Requirements for Altera Devices Data Sheet

Function	Config. Pin	Row	Col	QFP	J-Lead

Ded. Config. Pin	CONF_DONE	-	-	1	11

Ded. Config. Pin	nSTATUS	-	-	24	32

Ded. Config. Pin	nCONFIG	-	-	25	33

Ded. Config. Pin	MSEL1	-	-	51	53

Ded. Config. Pin	MSEL0	-	-	74	74

Ded. Config. Pin	nSP	-	-	75	75

Ded. Config. Pin	DCLK	-	-	100	10

Ded. JTAG Pin	nTRST	-	-	50	52

Input	-	-	-	3	12

Input	-	-	-	23	31

Input	-	-	-	53	54

Input	-	-	-	73	73

I/O	DATA1	A	-	4	13

I/O	DATA0	A	-	5	14

I/O	-	A	-	7	15

I/O	-	A	-	8	16

I/O	-	A	-	9	18

I/O	-	A	-	10	19

I/O or JTAG	TMS	A	-	11	20

I/O	-	A	-	12	21

I/O	ADD8	A	-	64	64

I/O	ADD7	A	-	65	65

I/O	ADD6	A	-	66	66

I/O	ADD5	A	-	67	67

Function	Config. Pin	Row	Col	QFP	J-Lead

I/O	ADD4	A	-	68	69

I/O	ADD3	A	-	69	70

I/O	ADD2	A	-	71	71

I/O or JTAG	TCLK	A	-	72	72

I/O	-	B	-	14	22

I/O	-	B	-	15	23

I/O	-	B	-	16	24

I/O	-	B	-	17	25

I/O or JTAG	TDO	B	-	18	27

I/O	CS	B	-	19	28

I/O	nCS	B	-	21	29

I/O	nWS	B	-	22	30

I/O or JTAG	TDI	B	-	54	55

I/O	ADD15	B	-	55	56

I/O	ADD14	B	-	57	57

I/O	ADD13	B	-	58	58

I/O	ADD12	B	-	59	60

I/O	ADD11	B	-	60	61

I/O	ADD10	B	-	61	62

I/O	ADD9	B	-	62	63

I/O	-	-	1	26	34

I/O	-	-	1	98	-

I/O	DATA2	-	1	99	9

I/O	-	-	1	-	35

I/O	-	-	2	27	-

Function	Config. Pin	Row	Col	QFP	J-Lead

I/O	ADD16	-	2	28	36

I/O	-	-	2	96	-

I/O	DATA3	-	2	97	8

I/O	-	-	3	29	37

I/O	-	-	3	93	-

I/O	DATA4	-	3	95	7

I/O	-	-	3	-	39

I/O	-	-	4	31	-

I/O	-	-	4	32	40

I/O	DATA5	-	4	92	6

I/O	-	-	5	33	41

I/O	DATA7	-	5	90	-

I/O	DATA6	-	5	91	4

I/O	-	-	5	-	42

I/O	-	-	6	34	-

I/O	-	-	6	35	43

I/O	-	-	6	89	-

I/O	DATA7	-	6	-	3

I/O	-	-	7	36	-

I/O	-	-	7	86	-

I/O	-	-	7	88	2

I/O	-	-	7	-	44

I/O	-	-	8	38	-

I/O	-	-	8	39	45

I/O	-	-	8	85	1

Function	Config. Pin	Row	Col	QFP	J-Lead

I/O	-	-	9	40	-

I/O	-	-	9	83	83

I/O	-	-	9	84	84

I/O	-	-	9	-	46

I/O	-	-	10	41	-

I/O	nRS	-	10	42	48

I/O	-	-	10	82	82

I/O	-	-	11	43	-

I/O	RDCLK	-	11	45	49

I/O	SDOUT	-	11	79	79

I/O	-	-	11	81	81

I/O	-	-	12	46	-

I/O	CLKUSR	-	12	47	50

I/O	ADD0	-	12	78	78

I/O	-	-	13	48	-

I/O	ADD17	-	13	49	51

I/O	ADD1	-	13	76	76

I/O	RDYnBUSY	-	13	77	77

VCC	-	-	-	6	17

VCC	-	-	-	20	38

VCC	-	-	-	37	59

VCC	-	-	-	56	80

VCC	-	-	-	70	-

VCC	-	-	-	87	-

GND	-	-	-	2	5

Function	Config. Pin	Row	Col	QFP	J-Lead

GND	-	-	-	13	26

GND	-	-	-	30	47

GND	-	-	-	44	68

GND	-	-	-	52	-

GND	-	-	-	63	-

GND	-	-	-	80	-

GND	-	-	-	94	-


EPF8282V Devices

The EPF8282V, a member of the FLEX 8000 device family, provides 282 registers, and a large number of storage elements for complex circuit applications. The EPF8282V meets the low power and voltage requirements of 3.3-V applications ranging from notebook computers to battery-operated, hand-held equipment.

The EPF8282V is available in 84-pin J-lead packages with 64 I/O pins and 100-pin QFP package with 74 I/O pins. It has 208 logic cells grouped into 26 LABs. These LABs are arranged into 2 rows and 13 columns. Each I/O element contains a bidirectional I/O buffer and a flipflop that can be used as either an input or output register. It also contains 4 dedicated fast inputs for synchronous control signals with large fan-outs. When used as outputs, the I/O registers provide fast Clock-to-output times; as inputs, they provide quick setup times. For complete information on the EPF8282V device, refer to the current FLEX 8000 Programmable Logic Device Family Data Sheet.

See also:

EPC1 Configuration EPROM

EPC1064/EPC1064V Configuration EPROM

EPC1213 Configuration EPROM

FLEX 8000 Device Selection Guide

Recommended reading:

AN26 (EPLD/MPLD Design Guidelines)

AN33 (Configuring FLEX 8000 Devices)

AN36 (Designing with FLEX 8000 Devices)

AN38 (Configuring Multiple FLEX 8000 Devices)

AN42 (Metastability in Altera Devices)

AB143 (Understanding FLEX 8000 Timing)

Operating Requirements for Altera Devices Data Sheet

Function	Config. Pin	Row	Col	QFP	J-Lead

Ded. Config. Pin	CONF_DONE	-	-	1	11

Ded. Config. Pin	nSTATUS	-	-	24	32

Ded. Config. Pin	nCONFIG	-	-	25	33

Ded. Config. Pin	MSEL1	-	-	51	53

Ded. Config. Pin	MSEL0	-	-	74	74

Ded. Config. Pin	nSP	-	-	75	75

Ded. Config. Pin	DCLK	-	-	100	10

Ded. JTAG Pin	nTRST	-	-	50	52

Input	-	-	-	3	12

Input	-	-	-	23	31

Input	-	-	-	53	54

Input	-	-	-	73	73

I/O	DATA1	A	-	4	13

I/O	DATA0	A	-	5	14

I/O	-	A	-	7	15

I/O	-	A	-	8	16

I/O	-	A	-	9	18

I/O	-	A	-	10	19

I/O or JTAG	TMS	A	-	11	20

I/O	-	A	-	12	21

I/O	ADD8	A	-	64	64

I/O	ADD7	A	-	65	65

I/O	ADD6	A	-	66	66

I/O	ADD5	A	-	67	67

Function	Config. Pin	Row	Col	QFP	J-Lead

I/O	ADD4	A	-	68	69

I/O	ADD3	A	-	69	70

I/O	ADD2	A	-	71	71

I/O or JTAG	TCLK	A	-	72	72

I/O	-	B	-	14	22

I/O	-	B	-	15	23

I/O	-	B	-	16	24

I/O	-	B	-	17	25

I/O or JTAG	TDO	B	-	18	27

I/O	CS	B	-	19	28

I/O	nCS	B	-	21	29

I/O	nWS	B	-	22	30

I/O or JTAG	TDI	B	-	54	55

I/O	ADD15	B	-	55	56

I/O	ADD14	B	-	57	57

I/O	ADD13	B	-	58	58

I/O	ADD12	B	-	59	60

I/O	ADD11	B	-	60	61

I/O	ADD10	B	-	61	62

I/O	ADD9	B	-	62	63

I/O	-	-	1	26	34

I/O	-	-	1	98	-

I/O	DATA2	-	1	99	9

I/O	-	-	1	-	35

I/O	-	-	2	27	-

Function	Config. Pin	Row	Col	QFP	J-Lead

I/O	ADD16	-	2	28	36

I/O	-	-	2	96	-

I/O	DATA3	-	2	97	8

I/O	-	-	3	29	37

I/O	-	-	3	93	-

I/O	DATA4	-	3	95	7

I/O	-	-	3	-	39

I/O	-	-	4	31	-

I/O	-	-	4	32	40

I/O	DATA5	-	4	92	6

I/O	-	-	5	33	41

I/O	DATA7	-	5	90	-

I/O	DATA6	-	5	91	4

I/O	-	-	5	-	42

I/O	-	-	6	34	-

I/O	-	-	6	35	43

I/O	-	-	6	89	-

I/O	DATA7	-	6	-	3

I/O	-	-	7	36	-

I/O	-	-	7	86	-

I/O	-	-	7	88	2

I/O	-	-	7	-	44

I/O	-	-	8	38	-

I/O	-	-	8	39	45

I/O	-	-	8	85	1

Function	Config. Pin	Row	Col	QFP	J-Lead

I/O	-	-	9	40	-

I/O	-	-	9	83	83

I/O	-	-	9	84	84

I/O	-	-	9	-	46

I/O	-	-	10	41	-

I/O	nRS	-	10	42	48

I/O	-	-	10	82	82

I/O	-	-	11	43	-

I/O	RDCLK	-	11	45	49

I/O	SDOUT	-	11	79	79

I/O	-	-	11	81	81

I/O	-	-	12	46	-

I/O	CLKUSR	-	12	47	50

I/O	ADD0	-	12	78	78

I/O	-	-	13	48	-

I/O	ADD17	-	13	49	51

I/O	ADD1	-	13	76	76

I/O	RDYnBUSY	-	13	77	77

VCC	-	-	-	6	17

VCC	-	-	-	20	38

VCC	-	-	-	37	59

VCC	-	-	-	56	80

VCC	-	-	-	70	-

VCC	-	-	-	87	-

GND	-	-	-	2	5

Function	Config. Pin	Row	Col	QFP	J-Lead

GND	-	-	-	13	26

GND	-	-	-	30	47

GND	-	-	-	44	68

GND	-	-	-	52	-

GND	-	-	-	63	-

GND	-	-	-	80	-

GND	-	-	-	94	-


EPF8452/EPF8452A Devices

The EPF8452 and EPF8452A, members of the FLEX 8000 device family, provide 452 registers, and a large number of storage elements for applications such as digital signal processing, wide data-path manipulation, and data transformation. The high-pin-count EPF8452 and EPF8452A devices can integrate multiple 32-bit buses into a single device.

The EPF8452 and EPF8452A are available in 84-pin J-lead and 100-pin QFP packages with 64 I/O pins, and 160-pin PGA and QFP packages with 116 I/O pins. The devices have 336 logic cells grouped into 42 LABs. These LABs are arranged into 2 rows and 21 columns. Each I/O element contains a bidirectional I/O buffer and a flipflop that can be used as either an input or output register. The devices also contain 4 dedicated fast inputs for synchronous control signals with large fan-outs. When used as outputs, the I/O registers provide fast Clock-to-output times; as inputs, they provide quick setup times. For complete information on the EPF8452 and EPF8452A devices, refer to the current FLEX 8000 Programmable Logic Device Family Data Sheet.

Altera recommends using the EPF8452A rather than the EPF8452 for new designs.

See also:

EPC1 Configuration EPROM

EPC1064/EPC1064V Configuration EPROM

EPC1213 Configuration EPROM

FLEX 8000 Device Selection Guide

Recommended reading:

AN26 (EPLD/MPLD Design Guidelines)

AN33 (Configuring FLEX 8000 Devices)

AN36 (Designing with FLEX 8000 Devices)

AN38 (Configuring Multiple FLEX 8000 Devices)

AN42 (Metastability in Altera Devices)

AB143 (Understanding FLEX 8000 Timing)

Operating Requirements for Altera Devices Data Sheet

QFP	QFP

Function	Config. Pin	Row	Col	(160-pin)	(100-pin)	J-Lead	PGA

Ded. Config. Pin	DCLK	-	-	1	100	10	P14

Ded. Config. Pin	CONF_DONE	-	-	4	1	11	N13

Ded. Config. Pin	nSTATUS	-	-	37	25	32	C13

Ded. Config. Pin	nCONFIG	-	-	40	26	33	A15

Ded. Config. Pin	MSEL1	-	-	84	51	53	A1

Ded. Config. Pin	MSEL0	-	-	117	75	74	P2

Ded. Config. Pin	nSP	-	-	120	76	75	R1

Input	-	-	-	5	3	12	R15

Input	-	-	-	36	24	31	D14

Input	-	-	-	85	53	54	C3

Input	-	-	-	116	74	73	N2

I/O	DATA1	A	-	11	4	13	N15

I/O	DATA0	A	-	12	5	14	K13

I/O	-	A	-	15	7	15	L15

I/O	-	A	-	16	8	16	K14

I/O	-	A	-	17	10	18	J14

I/O	-	A	-	18	11	19	K15

I/O	-	A	-	19	12	20	H14

I/O	-	A	-	20	14	21	J15

I/O	ADD8	A	-	101	65	64	H1

I/O	ADD7	A	-	102	66	65	H2

I/O	ADD6	A	-	103	67	66	J1

I/O	ADD5	A	-	104	68	67	J2

I/O	ADD4	A	-	105	70	69	K2

QFP	QFP

Function	Config. Pin	Row	Col	(160-pin)	(100-pin)	J-Lead	PGA

I/O	ADD3	A	-	106	71	70	K1

I/O	ADD2	A	-	109	72	71	K3

I/O	ADD1	A	-	110	73	72	M1

I/O	-	B	-	22	15	22	G15

I/O	-	B	-	23	16	23	H15

I/O	-	B	-	24	17	24	F15

I/O	-	B	-	25	18	25	G14

I/O	-	B	-	26	20	27	F14

I/O	CS	B	-	27	21	28	E15

I/O	nCS	B	-	29	22	29	D15

I/O	nWS	B	-	30	23	30	F13

I/O	ADD16	B	-	91	54	55	E2

I/O	ADD15	B	-	92	55	56	D1

I/O	ADD14	B	-	94	57	57	E1

I/O	ADD13	B	-	95	58	58	F3

I/O	ADD12	B	-	96	60	60	F2

I/O	ADD11	B	-	97	61	61	F1

I/O	ADD10	B	-	98	62	62	G2

I/O	ADD9	B	-	99	64	63	G1

I/O	-	-	1	10	-	-	L14

I/O	-	-	1	31	-	-	C15

I/O	-	-	1	42	27	34	A14

I/O	DATA2	-	1	159	-	-	R14

I/O	-	-	2	32	-	-	E14

I/O	-	-	2	43	-	-	B14

QFP	QFP

Function	Config. Pin	Row	Col	(160-pin)	(100-pin)	J-Lead	PGA

I/O	DATA3	-	2	157	-	-	P13

I/O	-	-	2	158	-	-	P12

I/O	DATA2	-	2	-	98	9	-

I/O	-	-	3	33	-	-	B15

I/O	-	-	3	44	28	35	A13

I/O	DATA4	-	3	154	-	-	R13

I/O	-	-	3	156	-	-	N11

I/O	DATA3	-	3	-	97	8	-

I/O	-	-	4	9	-	-	M14

I/O	-	-	4	45	-	-	B13

I/O	-	-	4	47	29	36	A12

I/O	-	-	4	153	-	-	P11

I/O	DATA4	-	4	-	96	7	-

I/O	-	-	5	8	-	-	L13

I/O	-	-	5	48	-	-	B12

I/O	-	-	5	49	31	37	A11

I/O	DATA5	-	5	152	-	-	R12

I/O	-	-	6	34	-	-	E13

I/O	-	-	6	50	-	-	C11

I/O	DATA6	-	6	150	-	-	P10

I/O	-	-	6	151	-	-	N10

I/O	DATA5	-	6	-	95	6	-

I/O	-	-	7	35	-	-	C14

I/O	-	-	7	51	33	39	B11

I/O	-	-	7	146	-	-	N9

QFP	QFP

Function	Config. Pin	Row	Col	(160-pin)	(100-pin)	J-Lead	PGA

I/O	-	-	7	149	-	-	R11

I/O	DATA6	-	7	-	91	4	-

I/O	-	-	8	7	-	-	P15

I/O	-	-	8	52	-	-	B10

I/O	-	-	8	54	34	40	C10

I/O	-	-	8	145	90	3	R10

I/O	-	-	9	6	-	-	N14

I/O	-	-	9	55	-	-	A10

I/O	-	-	9	56	35	41	B9

I/O	DATA7	-	9	144	-	-	P8

I/O	-	-	10	57	-	-	A9

I/O	-	-	10	79	-	-	B3

I/O	-	-	10	142	-	-	N8

I/O	-	-	10	143	-	-	P9

I/O	DATA7	-	10	-	89	2	-

I/O	-	-	11	58	36	42	C9

I/O	-	-	11	86	-	-	B1

I/O	-	-	11	139	-	-	R8

I/O	-	-	11	141	88	1	R9

I/O	-	-	12	59	-	-	A8

I/O	-	-	12	61	38	43	A7

I/O	-	-	12	122	-	-	R2

I/O	-	-	12	138	86	84	P7

I/O	-	-	13	62	-	-	C8

I/O	-	-	13	63	39	44	B7

QFP	QFP

Function	Config. Pin	Row	Col	(160-pin)	(100-pin)	J-Lead	PGA

I/O	-	-	13	115	-	-	M2

I/O	-	-	13	137	-	-	R7

I/O	-	-	14	64	-	-	B8

I/O	-	-	14	87	-	-	C2

I/O	-	-	14	135	-	-	R6

I/O	-	-	14	136	85	83	N7

I/O	-	-	15	65	40	45	A6

I/O	-	-	15	88	-	-	D2

I/O	-	-	15	132	-	-	P6

I/O	-	-	15	134	84	82	N6

I/O	-	-	16	66	-	-	C7

I/O	-	-	16	68	41	46	A5

I/O	-	-	16	114	-	-	P1

I/O	-	-	16	131	83	81	P5

I/O	-	-	17	69	-	-	B6

I/O	nRS	-	17	71	45	48	C6

I/O	-	-	17	113	-	-	L3

I/O	-	-	17	130	-	-	N5

I/O	-	-	18	72	-	-	A4

I/O	-	-	18	89	-	-	E3

I/O	SDOUT	-	18	128	-	-	P4

I/O	-	-	18	129	81	79	R5

I/O	RDCLK	-	19	73	46	49	B5

I/O	-	-	19	90	-	-	C1

I/O	RDYnBUSY	-	19	125	-	-	P3

QFP	QFP

Function	Config. Pin	Row	Col	(160-pin)	(100-pin)	J-Lead	PGA

I/O	-	-	19	127	-	-	R4

I/O	SDOUT	-	19	-	79	78	-

I/O	-	-	20	74	-	-	A3

I/O	CLKUSR	-	20	76	47	50	C5

I/O	-	-	20	112	-	-	N1

I/O	-	-	20	124	-	-	R3

I/O	RDYnBUSY	-	20	-	78	77	-

I/O	-	-	21	77	-	-	A2

I/O	ADD17	-	21	78	48	51	B4

I/O	-	-	21	111	-	-	L2

I/O	ADD0	-	21	123	77	76	N3

VCC	-	-	-	-	9	17	B2

VCC	-	-	-	-	32	38	C4

VCC	-	-	-	-	49	52	D3

VCC	-	-	-	-	59	59	D8

VCC	-	-	-	-	82	80	D12

VCC	-	-	-	21	-	-	G3

VCC	-	-	-	41	-	-	G12

VCC	-	-	-	53	-	-	H4

VCC	-	-	-	67	-	-	H13

VCC	-	-	-	80	-	-	J3

VCC	-	-	-	81	-	-	J12

VCC	-	-	-	100	-	-	M4

VCC	-	-	-	121	-	-	M7

VCC	-	-	-	133	-	-	M9

QFP	QFP

Function	Config. Pin	Row	Col	(160-pin)	(100-pin)	J-Lead	PGA

VCC	-	-	-	147	-	-	M13

VCC	-	-	-	160	-	-	N12

GND	-	-	-	-	19	5	C12

GND	-	-	-	-	44	26	D4

GND	-	-	-	-	69	47	D7

GND	-	-	-	-	94	68	D9

GND	-	-	-	-	-	-	D13

GND	-	-	-	13	-	-	G4

GND	-	-	-	14	-	-	G13

GND	-	-	-	28	-	-	H3

GND	-	-	-	46	-	-	H12

GND	-	-	-	60	-	-	J4

GND	-	-	-	75	-	-	J13

GND	-	-	-	93	-	-	L1

GND	-	-	-	107	-	-	M3

GND	-	-	-	108	-	-	M8

GND	-	-	-	126	-	-	M12

GND	-	-	-	140	-	-	M15

GND	-	-	-	155	-	-	N4

N.C.	-	-	-	2	2	-	-

N.C.	-	-	-	3	6	-	-

N.C.	-	-	-	38	13	-	-

N.C.	-	-	-	39	30	-	-

N.C.	-	-	-	70	37	-	-

N.C.	-	-	-	82	42	-	-

QFP	QFP

Function	Config. Pin	Row	Col	(160-pin)	(100-pin)	J-Lead	PGA

N.C.	-	-	-	83	43	-	-

N.C.	-	-	-	118	50	-	-

N.C.	-	-	-	119	52	-	-

N.C.	-	-	-	148	56	-	-

N.C.	-	-	-	-	63	-	-

N.C.	-	-	-	-	80	-	-

N.C.	-	-	-	-	87	-	-

N.C.	-	-	-	-	92	-	-

N.C.	-	-	-	-	93	-	-

N.C.	-	-	-	-	99	-	-


EPF8636A Devices

The EPF8636A, a member of the FLEX 8000 device family, provides 636 registers, and a large number of storage elements for applications such as digital signal processing, wide data-path manipulation, and data transformation. The high-pin-count EPF8636A devices can integrate multiple 32-bit buses into a single device.

The EPF8636A is available in 84-pin J-lead packages with 64 I/O pins, 160-pin QFP packages with 114 I/O pins, and 192-pin PGA and 208-pin QFP packages with 132 I/O pins. It has 504 logic cells grouped into 63 LABs. These LABs are arranged into 3 rows and 21 columns. Each I/O element contains a bidirectional I/O buffer and a flipflop that can be used as either an input or output register. It also contains 4 dedicated fast inputs for synchronous control signals with large fan-outs. When used as outputs, the I/O registers provide fast Clock-to-output times; as inputs, they provide quick setup times. For complete information on the EPF8636A device, refer to the current FLEX 8000 Programmable Logic Device Family Data Sheet.

See also:

EPC1 Configuration EPROM

EPC1064/EPC1064V Configuration EPROM

EPC1213 Configuration EPROM

FLEX 8000 Device Selection Guide

Recommended reading:

AN26 (EPLD/MPLD Design Guidelines)

AN33 (Configuring FLEX 8000 Devices)

AN36 (Designing with FLEX 8000 Devices)

AN38 (Configuring Multiple FLEX 8000 Devices)

AN42 (Metastability in Altera Devices)

AB143 (Understanding FLEX 8000 Timing)

Operating Requirements for Altera Devices Data Sheet

QFP	QFP

Function	Config. Pin	Row	Col	(208-pin)	(160-pin)	J-Lead	PGA

Ded. Config. Pin	MSEL0	-	-	4	3	74	T15

Ded. Config. Pin	MSEL1	-	-	49	38	53	T3

Ded. Config. Pin	nCONFIG	-	-	103	81	33	C3

Ded. Config. Pin	nSTATUS	-	-	108	83	32	B3

Ded. Config. Pin	CONF_DONE	-	-	153	118	11	B15

Ded. Config. Pin	DCLK	-	-	158	120	10	C15

Ded. Config. Pin	nSP	-	-	207	1	75	R15

Ded. JTAG Pin	nTRST	-	-	54	40	52	R3

Input	-	-	-	7	6	73	U13

Input	-	-	-	45	35	54	U5

Input	-	-	-	112	87	31	A5

Input	-	-	-	150	116	12	A13

I/O	ADD1	A	-	8	7	72	R13

I/O	-	A	-	9	8	-	T11

I/O	ADD2	A	-	10	9	71	U15

I/O	-	A	-	11	10	-	T10

I/O	ADD3	A	-	12	11	70	U14

I/O	-	A	-	13	12	-	T9

I/O	ADD4	A	-	14	13	69	R12

I/O	-	A	-	15	14	-	U6

I/O	-	A	-	142	108	-	A11

I/O	-	A	-	143	109	16	A12

I/O	-	A	-	144	110	-	B12

I/O	-	A	-	145	111	15	A14

I/O	-	A	-	146	112	-	A15

QFP	QFP

Function	Config. Pin	Row	Col	(208-pin)	(160-pin)	J-Lead	PGA

I/O	DATA0	A	-	147	113	14	C16

I/O	-	A	-	148	114	-	B14

I/O	DATA1	A	-	149	115	13	E16

I/O	ADD5	B	-	21	17	67	U12

I/O	ADD6	B	-	22	18	66	U11

I/O	ADD7	B	-	23	19	65	U10

I/O	ADD8	B	-	24	20	64	U9

I/O	ADD9	B	-	28	21	63	T8

I/O	ADD10	B	-	29	22	62	T7

I/O	ADD11	B	-	30	23	61	R7

I/O	ADD12	B	-	31	24	60	T6

I/O	-	B	-	126	98	25	B6

I/O	-	B	-	127	99	24	A6

I/O	-	B	-	128	100	23	A7

I/O	-	B	-	129	101	22	B7

I/O	-	B	-	133	102	21	B8

I/O	-	B	-	134	103	20	A9

I/O	-	B	-	135	104	19	B10

I/O	-	B	-	136	105	18	B11

I/O	ADD13	C	-	37	27	58	R6

I/O	-	C	-	38	28	-	U2

I/O	ADD14	C	-	39	29	57	U4

I/O	-	C	-	40	30	-	T4

I/O	ADD15	C	-	41	31	56	T5

I/O	-	C	-	42	32	-	T2

QFP	QFP

Function	Config. Pin	Row	Col	(208-pin)	(160-pin)	J-Lead	PGA

I/O	ADD16	C	-	43	33	55	U3

I/O	-	C	-	44	34	-	U1

I/O	-	C	-	113	88	-	B4

I/O	nWS	C	-	114	89	30	C5

I/O	-	C	-	115	90	-	A2

I/O	nCS	C	-	116	91	29	B13

I/O	-	C	-	117	92	-	A3

I/O	CS	C	-	118	93	28	A16

I/O	-	C	-	119	94	-	A4

I/O or JTAG	TDO	C	-	120	95	27	B9

I/O	-	-	1	100	78	-	D2

I/O	-	-	1	101	79	34	B2

I/O	-	-	1	152	-	-	B16

I/O	DATA2	-	1	160	122	-	F15

I/O	-	-	2	98	-	-	C2

I/O	-	-	2	99	77	35	A1

I/O	-	-	2	161	123	-	A17

I/O	DATA3	-	2	162	124	-	G15

I/O	DATA2	-	2	-	-	9	-

I/O	-	-	3	95	74	-	B1

I/O	-	-	3	97	76	-	E2

I/O	-	-	3	163	125	-	D16

I/O	DATA4	-	3	165	-	-	E17

I/O	DATA3	-	3	-	-	8	-

I/O	-	-	4	93	72	-	C1

QFP	QFP

Function	Config. Pin	Row	Col	(208-pin)	(160-pin)	J-Lead	PGA

I/O	-	-	4	94	73	36	F2

I/O	-	-	4	166	-	-	B17

I/O	-	-	4	167	-	-	C17

I/O	DATA4	-	4	-	127	7	-

I/O	-	-	5	90	69	-	D1

I/O	-	-	5	92	71	37	G3

I/O	-	-	5	168	128	-	F16

I/O	DATA5	-	5	169	129	-	F17

I/O	-	-	6	88	-	-	E1

I/O	-	-	6	89	68	39	G2

I/O	-	-	6	170	130	-	D17

I/O	DATA6	-	6	172	132	-	G17

I/O	DATA5	-	6	-	-	6	-

I/O	-	-	7	86	-	-	H3

I/O	-	-	7	87	67	-	F1

I/O	-	-	7	173	133	-	G16

I/O	-	-	7	174	134	-	H15

I/O	DATA6	-	7	-	-	4	-

I/O	-	-	8	84	65	-	H2

I/O	-	-	8	85	66	40	G1

I/O	-	-	8	175	135	3	H16

I/O	-	-	8	176	-	-	J16

I/O	-	-	9	82	63	-	J2

I/O	-	-	9	83	64	41	H1

I/O	-	-	9	177	136	-	J17

QFP	QFP

Function	Config. Pin	Row	Col	(208-pin)	(160-pin)	J-Lead	PGA

I/O	DATA7	-	9	178	-	-	H17

I/O	-	-	10	80	-	-	J1

I/O	-	-	10	81	62	42	K2

I/O	-	-	10	179	-	-	K16

I/O	-	-	10	180	138	-	K17

I/O	DATA7	-	10	-	137	2	-

I/O	-	-	11	77	-	-	K1

I/O	-	-	11	79	61	-	K3

I/O	-	-	11	181	139	1	K15

I/O	-	-	11	183	141	-	L17

I/O	-	-	12	75	58	-	L2

I/O or JTAG	TMS	-	12	76	59	43	U7

I/O	-	-	12	184	142	84	L16

I/O	-	-	12	185	-	-	M17

I/O	-	-	13	73	56	-	L1

I/O or JTAG	TCLK	-	13	74	57	44	U8

I/O	-	-	13	186	143	-	N17

I/O	-	-	13	187	-	-	L15

I/O	-	-	14	71	54	-	L3

I/O or JTAG	TDI	-	14	72	55	45	R11

I/O	-	-	14	188	144	83	P17

I/O	-	-	14	189	145	-	M16

I/O	-	-	15	69	-	-	N1

I/O	-	-	15	70	53	-	M1

I/O	-	-	15	190	146	82	R17

QFP	QFP

Function	Config. Pin	Row	Col	(208-pin)	(160-pin)	J-Lead	PGA

I/O	-	-	15	191	147	-	M15

I/O	nRS	-	16	66	50	-	B5

I/O	-	-	16	68	52	46	M2

I/O	-	-	16	192	148	81	T17

I/O	-	-	16	194	-	-	N16

I/O	RDCLK	-	17	64	48	-	C11

I/O	-	-	17	65	49	-	P1

I/O	-	-	17	195	150	-	R16

I/O	-	-	17	196	-	-	P16

I/O	nRS	-	17	-	-	48	-

I/O	-	-	18	62	-	-	R1

I/O	-	-	18	63	47	-	M3

I/O	-	-	18	197	151	79	U17

I/O	SDOUT	-	18	198	152	-	C7

I/O	RDCLK	-	18	-	-	49	-

I/O	CLKUSR	-	19	59	-	-	A10

I/O	-	-	19	61	46	-	N2

I/O	-	-	19	199	153	-	T16

I/O	RDYnBUSY	-	19	201	155	-	A8

I/O	SDOUT	-	19	-	-	78	-

I/O	ADD17	-	20	57	43	-	R5

I/O	-	-	20	58	-	-	T1

I/O	-	-	20	202	156	-	T14

I/O	ADD0	-	20	203	157	-	U16

I/O	CLKUSR	-	20	-	44	50	-

QFP	QFP

Function	Config. Pin	Row	Col	(208-pin)	(160-pin)	J-Lead	PGA

I/O	RDYnBUSY	-	20	-	-	77	-

I/O	-	-	21	48	-	-	R2

I/O	-	-	21	56	42	-	P2

I/O	-	-	21	204	158	-	T13

I/O	-	-	21	205	159	-	T12

I/O	ADD17	-	21	-	-	51	-

I/O	ADD0	-	21	-	-	76	-

VCC	-	-	-	-	4	17	C8

VCC	-	-	-	-	5	38	C9

VCC	-	-	-	-	25	59	C10

VCC	-	-	-	-	26	80	D3

VCC	-	-	-	5	41	-	D4

VCC	-	-	-	6	60	-	D9

VCC	-	-	-	32	70	-	D14

VCC	-	-	-	33	80	-	D15

VCC	-	-	-	55	85	-	G4

VCC	-	-	-	78	106	-	G14

VCC	-	-	-	91	107	-	L4

VCC	-	-	-	102	121	-	L14

VCC	-	-	-	110	140	-	P4

VCC	-	-	-	137	149	-	P9

VCC	-	-	-	138	160	-	P14

VCC	-	-	-	159	-	-	R8

VCC	-	-	-	182	-	-	R9

VCC	-	-	-	193	-	-	R10

QFP	QFP

Function	Config. Pin	Row	Col	(208-pin)	(160-pin)	J-Lead	PGA

VCC	-	-	-	206	-	-	R14

GND	-	-	-	19	15	5	-

GND	-	-	-	20	16	26	-

GND	-	-	-	46	36	47	C4

GND	-	-	-	47	37	68	D7

GND	-	-	-	60	45	-	D8

GND	-	-	-	67	51	-	D10

GND	-	-	-	96	75	-	D11

GND	-	-	-	109	84	-	H4

GND	-	-	-	111	86	-	H14

GND	-	-	-	124	96	-	K4

GND	-	-	-	125	97	-	K14

GND	-	-	-	151	117	-	P7

GND	-	-	-	164	126	-	P8

GND	-	-	-	171	131	-	P10

GND	-	-	-	200	154	-	P11

N.C.	-	-	-	1	2	-	-

N.C.	-	-	-	2	39	-	-

N.C.	-	-	-	3	82	-	-

N.C.	-	-	-	16	119	-	-

N.C.	-	-	-	17	-	-	-

N.C.	-	-	-	18	-	-	-

N.C.	-	-	-	25	-	-	-

N.C.	-	-	-	26	-	-	-

N.C.	-	-	-	27	-	-	-

QFP	QFP

Function	Config. Pin	Row	Col	(208-pin)	(160-pin)	J-Lead	PGA

N.C.	-	-	-	34	-	-	-

N.C.	-	-	-	35	-	-	-

N.C.	-	-	-	36	-	-	-

N.C.	-	-	-	50	-	-	-

N.C.	-	-	-	51	-	-	-

N.C.	-	-	-	52	-	-	-

N.C.	-	-	-	53	-	-	-

N.C.	-	-	-	104	-	-	-

N.C.	-	-	-	105	-	-	-

N.C.	-	-	-	106	-	-	C6

N.C.	-	-	-	107	-	-	C12

N.C.	-	-	-	121	-	-	C13

N.C.	-	-	-	122	-	-	C14

N.C.	-	-	-	123	-	-	E3

N.C.	-	-	-	130	-	-	E15

N.C.	-	-	-	131	-	-	F3

N.C.	-	-	-	132	-	-	J3

N.C.	-	-	-	139	-	-	J4

N.C.	-	-	-	140	-	-	J14

N.C.	-	-	-	141	-	-	J15

N.C.	-	-	-	154	-	-	N3

N.C.	-	-	-	155	-	-	N15

N.C.	-	-	-	156	-	-	P3

N.C.	-	-	-	157	-	-	P15

N.C.	-	-	-	208	-	-	R4


EPF8820/EPF8820A Devices

The EPF8820 and EPF8820A, members of the FLEX 8000 device family, provide 820 registers and a large number of storage elements for applications such as digital signal processing, wide data-path manipulation, and data transformation. The high-pin -count EPF8820 and EPF8820A devices can integrate multiple 32-bit buses into a single device.

The EPF8820 and EPF8820A are available in 160-pin QFP packages with 116 I/O pins, and 192-pin PGA, 208-pin QFP, and 225-pin BGA packages with 148 I/O pins. They have 672 logic cells grouped into 84 LABs. These LABs are arranged into 4 rows and 21 columns. Each I/O element contains a bidirectional I/O buffer and a flipflop that can be used as either an input or output register. They also contain 4 dedicated fast inputs for synchronous control signals with large fan-outs. When used as outputs, the I/O registers provide fast Clock-to-output times; as inputs, they provide quick setup times. For complete information on the EPF8820 and EPF8820A devices, refer to the current FLEX 8000 Programmable Logic Device Family Data Sheet.

Altera recommends using the EPF8820A rather than the EPF8820 for new designs.

See also:

EPC1 Configuration EPROM

EPC1064/EPC1064V Configuration EPROM

EPC1213 Configuration EPROM

FLEX 8000 Device Selection Guide

Recommended reading:

AN26 (EPLD/MPLD Design Guidelines)

AN33 (Configuring FLEX 8000 Devices)

AN36 (Designing with FLEX 8000 Devices)

AN38 (Configuring Multiple FLEX 8000 Devices)

AN42 (Metastability in Altera Devices)

AB143 (Understanding FLEX 8000 Timing)

Operating Requirements for Altera Devices Data Sheet

QFP	QFP

Function	Config. Pin	Row	Col	(208-pin)	(160-pin)	PGA	BGA

Ded. Config. Pin	MSEL0	-	-	4	2	T15	B14

Ded. Config. Pin	MSEL1	-	-	49	44	T3	R15

Ded. Config. Pin	nCONFIG	-	-	103	81	C3	R1

Ded. Config. Pin	nSTATUS	-	-	108	82	B3	P2

Ded. Config. Pin	CONF_DONE	-	-	153	124	B15	A1

Ded. Config. Pin	DCLK	-	-	158	125	C15	B2

Ded. Config. Pin	nSP	-	-	207	1	R15	A15

Ded. JTAG Pin	nTRST	-	-	54	45	R3	P14

Input	-	-	-	17	14	U13	E15

Input	-	-	-	36	33	U5	K12

Input	-	-	-	121	94	A5	L1

Input	-	-	-	140	113	A13	F4

I/O	-	A	-	7	4	T16	C14

I/O	-	A	-	8	5	T14	D13

I/O	ADD0	A	-	9	6	U16	C15

I/O	ADD1	A	-	10	7	R13	E12

I/O	ADD2	A	-	11	8	U15	D14

I/O	-	A	-	12	9	T13	F11

I/O	ADD3	A	-	13	10	U14	D15

I/O	ADD4	A	-	14	11	R12	E13

I/O	-	A	-	143	116	C12	E2

I/O	-	A	-	144	117	A14	E3

I/O	nCS	A	-	145	118	B13	D1

I/O	-	A	-	146	119	A15	E4

I/O	-	A	-	147	120	C13	D2

QFP	QFP

Function	Config. Pin	Row	Col	(208-pin)	(160-pin)	PGA	BGA

I/O	CS	A	-	148	121	A16	C1

I/O	-	A	-	149	122	B14	D3

I/O	-	A	-	150	123	B16	E5

I/O	-	B	-	18	15	T12	F13

I/O	ADD5	B	-	19	16	U12	F14

I/O or JTAG	TDI	B	-	20	17	R11	F15

I/O	ADD6	B	-	21	18	U11	G11

I/O	-	B	-	22	19	T11	G12

I/O	ADD7	B	-	23	20	U10	G13

I/O	-	B	-	24	21	T10	G15

I/O	ADD8	B	-	25	22	U9	G14

I/O	-	B	-	132	105	A9	G5

I/O	-	B	-	133	106	B10	G1

I/O	CLKUSR	B	-	134	107	A10	G2

I/O	-	B	-	135	108	B11	G3

I/O	-	B	-	136	109	A11	G4

I/O	RDCLK	B	-	137	110	C11	F1

I/O	-	B	-	138	111	A12	F2

I/O	-	B	-	139	112	B12	F3

I/O	-	C	-	28	25	T9	J11

I/O	ADD9	C	-	29	26	T8	J15

I/O or JTAG	TCLK	C	-	30	27	U8	J14

I/O	ADD10	C	-	31	28	T7	J13

I/O or JTAG	TMS	C	-	32	29	U7	J12

I/O	ADD11	C	-	33	30	R7	K15

QFP	QFP

Function	Config. Pin	Row	Col	(208-pin)	(160-pin)	PGA	BGA

I/O	-	C	-	34	31	U6	K14

I/O	ADD12	C	-	35	32	T6	K13

I/O	-	C	-	122	95	B6	K3

I/O	-	C	-	123	96	A6	K2

I/O	SDOUT	C	-	124	97	C7	K1

I/O	-	C	-	125	98	A7	J5

I/O	-	C	-	126	99	B7	J4

I/O	RDYnBUSY	C	-	127	100	A8	J3

I/O	-	C	-	128	101	B8	J1

I/O or JTAG	TDO	C	-	129	102	B9	J2

I/O	ADD13	D	-	39	36	R6	L14

I/O	ADD14	D	-	40	37	U4	L13

I/O	ADD15	D	-	41	38	T5	M15

I/O	ADD16	D	-	42	39	U3	L12

I/O	ADD17	D	-	43	40	R5	M14

I/O	-	D	-	44	41	U2	N15

I/O	-	D	-	45	42	T4	M13

I/O	-	D	-	46	43	T2	L11

I/O	-	D	-	111	84	B2	N2

I/O	-	D	-	112	85	B4	M3

I/O	-	D	-	113	86	A2	N1

I/O	nWS	D	-	114	87	C5	L4

I/O	-	D	-	115	88	A3	M2

I/O	nRS	D	-	116	89	B5	K5

I/O	-	D	-	117	90	A4	M1

QFP	QFP

Function	Config. Pin	Row	Col	(208-pin)	(160-pin)	PGA	BGA

I/O	-	D	-	118	91	C6	L3

I/O	-	-	1	100	-	A1	L5

I/O	-	-	1	101	78	D2	P3

I/O	-	-	1	151	-	C14	C2

I/O	-	-	1	160	128	A17	F6

I/O	-	-	2	98	-	C2	R3

I/O	-	-	2	99	77	E3	N4

I/O	-	-	2	161	-	D16	B3

I/O	DATA0	-	2	162	129	C16	C4

I/O	-	-	3	95	-	F3	M5

I/O	-	-	3	97	76	E2	P4

I/O	-	-	3	163	130	E15	A3

I/O	DATA1	-	3	165	-	E16	D5

I/O	-	-	4	93	73	F2	N5

I/O	-	-	4	94	74	B1	R4

I/O	-	-	4	166	-	B17	B4

I/O	DATA2	-	4	167	-	F15	E6

I/O	DATA1	-	4	-	132	-	-

I/O	-	-	5	91	-	G3	L6

I/O	-	-	5	92	72	C1	P5

I/O	-	-	5	168	-	C17	A4

I/O	-	-	5	169	-	F16	C5

I/O	DATA2	-	5	-	133	-	-

I/O	-	-	6	89	-	G2	M6

I/O	-	-	6	90	71	D1	R5

QFP	QFP

Function	Config. Pin	Row	Col	(208-pin)	(160-pin)	PGA	BGA

I/O	-	-	6	170	134	D17	D6

I/O	DATA3	-	6	171	135	G15	B5

I/O	-	-	7	86	-	F1	M7

I/O	-	-	7	88	70	E1	N6

I/O	DATA4	-	7	172	136	E17	A5

I/O	DATA5	-	7	174	-	F17	A6

I/O	-	-	8	84	67	G1	P7

I/O	-	-	8	85	68	H3	N7

I/O	-	-	8	175	-	G16	E7

I/O	DATA6	-	8	176	-	G17	D7

I/O	DATA5	-	8	-	138	-	-

I/O	-	-	9	82	-	H1	L7

I/O	-	-	9	83	66	H2	R7

I/O	-	-	9	177	-	H15	C7

I/O	DATA7	-	9	178	-	H17	A7

I/O	DATA6	-	9	-	139	-	-

I/O	-	-	10	80	-	J2	P8

I/O	-	-	10	81	65	J3	N8

I/O	-	-	10	179	-	H16	B7

I/O	-	-	10	180	141	J16	E8

I/O	DATA7	-	10	-	140	-	-

I/O	-	-	11	77	-	K2	M8

I/O	-	-	11	79	64	J4	R8

I/O	-	-	11	181	142	J14	D8

I/O	-	-	11	183	-	J15	A8

QFP	QFP

Function	Config. Pin	Row	Col	(208-pin)	(160-pin)	PGA	BGA

I/O	-	-	12	75	61	K3	P9

I/O	-	-	12	76	62	J1	L8

I/O	-	-	12	184	144	J17	B8

I/O	-	-	12	185	-	K16	C8

I/O	-	-	13	73	-	L2	N9

I/O	-	-	13	74	60	K1	R9

I/O	-	-	13	186	145	K17	E9

I/O	-	-	13	187	-	K15	A9

I/O	-	-	14	71	-	L3	L9

I/O	-	-	14	72	59	L1	M9

I/O	-	-	14	188	146	L17	B9

I/O	-	-	14	189	147	L16	C9

I/O	-	-	15	68	-	N1	R11

I/O	-	-	15	70	58	M1	R10

I/O	-	-	15	190	148	M17	D9

I/O	-	-	15	192	-	N17	C10

I/O	-	-	16	66	55	P1	M10

I/O	-	-	16	67	56	M2	P11

I/O	-	-	16	193	150	L15	D10

I/O	-	-	16	194	-	P17	A11

I/O	-	-	17	64	-	R1	R12

I/O	-	-	17	65	54	M3	N11

I/O	-	-	17	195	151	M16	E10

I/O	-	-	17	196	-	R17	B11

I/O	-	-	18	62	-	T1	P12

QFP	QFP

Function	Config. Pin	Row	Col	(208-pin)	(160-pin)	PGA	BGA

I/O	-	-	18	63	53	N2	L10

I/O	-	-	18	197	152	M15	C11

I/O	-	-	18	198	153	T17	A12

I/O	-	-	19	59	-	P2	R13

I/O	-	-	19	61	52	N3	M11

I/O	-	-	19	199	154	N16	D11

I/O	-	-	19	201	-	N15	B12

I/O	-	-	20	57	49	P3	P13

I/O	-	-	20	58	50	R2	N12

I/O	-	-	20	202	156	R16	A13

I/O	-	-	20	203	-	P16	C12

I/O	-	-	21	47	-	R4	N14

I/O	-	-	21	56	48	U1	K10

I/O	-	-	21	204	157	U17	E11

I/O	-	-	21	205	158	P15	B13

VCC	-	-	-	-	-	-	A2

VCC	-	-	-	-	-	-	A10

VCC	-	-	-	-	-	-	A14

VCC	-	-	-	-	-	-	B6

VCC	-	-	-	-	-	-	B10

VCC	-	-	-	-	-	-	B15

VCC	-	-	-	-	-	-	C3

VCC	-	-	-	-	-	-	C6

VCC	-	-	-	-	-	-	C13

VCC	-	-	-	-	-	-	D12

QFP	QFP

Function	Config. Pin	Row	Col	(208-pin)	(160-pin)	PGA	BGA

VCC	-	-	-	-	-	-	E1

VCC	-	-	-	-	-	-	F5

VCC	-	-	-	-	-	C8	F10

VCC	-	-	-	-	-	C9	H2

VCC	-	-	-	-	-	C10	H3

VCC	-	-	-	5	3	D3	H12

VCC	-	-	-	6	23	D4	H13

VCC	-	-	-	26	24	D9	H14

VCC	-	-	-	27	46	D14	H15

VCC	-	-	-	48	47	D15	K4

VCC	-	-	-	55	57	G4	L2

VCC	-	-	-	69	69	G14	M4

VCC	-	-	-	87	79	L4	M12

VCC	-	-	-	102	92	L14	N10

VCC	-	-	-	119	104	P4	N13

VCC	-	-	-	131	114	P9	P6

VCC	-	-	-	141	127	P14	P10

VCC	-	-	-	159	137	R8	P15

VCC	-	-	-	173	149	R9	R2

VCC	-	-	-	191	159	R10	R6

VCC	-	-	-	206	160	R14	R14

GND	-	-	-	-	-	-	B1

GND	-	-	-	-	-	-	D4

GND	-	-	-	-	-	-	E14

GND	-	-	-	-	-	-	F7

QFP	QFP

Function	Config. Pin	Row	Col	(208-pin)	(160-pin)	PGA	BGA

GND	-	-	-	-	-	-	F8

GND	-	-	-	-	-	-	F9

GND	-	-	-	-	-	-	F12

GND	-	-	-	-	-	-	G6

GND	-	-	-	-	-	-	G7

GND	-	-	-	-	-	-	G8

GND	-	-	-	-	-	-	G9

GND	-	-	-	-	-	-	G10

GND	-	-	-	-	-	-	H1

GND	-	-	-	-	-	-	H4

GND	-	-	-	-	-	-	H5

GND	-	-	-	-	-	-	H6

GND	-	-	-	-	-	-	H7

GND	-	-	-	-	-	-	H8

GND	-	-	-	15	12	-	H9

GND	-	-	-	16	13	-	H10

GND	-	-	-	37	34	-	H11

GND	-	-	-	38	35	C4	J6

GND	-	-	-	60	51	D7	J7

GND	-	-	-	78	63	D8	J8

GND	-	-	-	96	75	D10	J9

GND	-	-	-	109	80	D11	J10

GND	-	-	-	110	83	H4	K6

GND	-	-	-	120	93	H14	K7

GND	-	-	-	130	103	K4	K8

QFP	QFP

Function	Config. Pin	Row	Col	(208-pin)	(160-pin)	PGA	BGA

GND	-	-	-	142	115	K14	K9

GND	-	-	-	152	126	P7	K11

GND	-	-	-	164	131	P8	L15

GND	-	-	-	182	143	P10	N3

GND	-	-	-	200	155	P11	P1

N.C.	-	-	-	1	-	-	-

N.C.	-	-	-	2	-	-	-

N.C.	-	-	-	3	-	-	-

N.C.	-	-	-	50	-	-	-

N.C.	-	-	-	51	-	-	-

N.C.	-	-	-	52	-	-	-

N.C.	-	-	-	53	-	-	-

N.C.	-	-	-	104	-	-	-

N.C.	-	-	-	105	-	-	-

N.C.	-	-	-	106	-	-	-

N.C.	-	-	-	107	-	-	-

N.C.	-	-	-	154	-	-	-

N.C.	-	-	-	155	-	-	-

N.C.	-	-	-	156	-	-	-

N.C.	-	-	-	157	-	-	-

N.C.	-	-	-	208	-	-	-


EPF81188/EPF81188A Devices

The EPF81188 and EPF81188A, members of the FLEX 8000 device family, provide 1,188 registers and a large number of storage elements for applications such as digital signal processing, wide data-path manipulation, and data transformation. The high-pin-count EPF81188 and EPF81188A devices can integrate multiple 32-bit buses into a single device.

The EPF81188 and EPF81188A are available in 208-pin QFP packages with 144 I/O pins, and 232-pin PGA and 240-pin QFP packages with 180 I/O pins. These devices have 1,008 logic cells grouped into 126 LABs, which are arranged into 6 rows and 21 columns. Each I/O element contains a bidirectional I/O buffer and a flipflop that can be used as either an input or output register. These devices also contain 4 dedicated fast inputs for synchronous control signals with large fan-outs. When used as outputs, the I/O registers provide fast Clock-to-output times; as inputs, they provide quick setup times. For complete information on the EPF81188 and EPF81188A devices, refer to the current FLEX 8000 Programmable Logic Device Family Data Sheet.

Altera recommends using the EPF81188A rather than the EPF81188 for new designs.

See also:

EPC1 Configuration EPROM

EPC1064/EPC1064V Configuration EPROM

EPC1213 Configuration EPROM

FLEX 8000 Device Selection Guide

Recommended reading:

AN26 (EPLD/MPLD Design Guidelines)

AN33 (Configuring FLEX 8000 Devices)

AN36 (Designing with FLEX 8000 Devices)

AN38 (Configuring Multiple FLEX 8000 Devices)

AN42 (Metastability in Altera Devices)

AB143 (Understanding FLEX 8000 Timing)

Operating Requirements for Altera Devices Data Sheet

QFP	QFP

Function	Config. Pin	Row	Col	(240-pin)	(208-pin)	PGA	BGA

Ded. Config. Pin	MSEL0	-	-	21	21	G15	B14

Ded. Config. Pin	MSEL1	-	-	40	33	L15	R15

Ded. Config. Pin	nCONFIG	-	-	117	107	R4	R1

Ded. Config. Pin	nSTATUS	-	-	141	124	L3	P2

Ded. Config. Pin	CONF_DONE	-	-	160	138	G3	A1

Ded. Config. Pin	DCLK	-	-	184	154	C4	B2

Ded. Config. Pin	nSP	-	-	237	5	C14	A15

Input	-	-	-	10	13	C17	E15

Input	-	-	-	51	41	R17	K12

Input	-	-	-	130	116	R1	L1

Input	-	-	-	171	146	C1	F4

I/O	-	A	-	238	6	D13	A14

I/O	-	A	-	1	-	B15	A13

I/O	-	A	-	2	7	B16	C12

I/O	ADD0	A	-	3	8	C15	C15

I/O	-	A	-	4	-	D14	B13

I/O	ADD1	A	-	5	9	B17	E12

I/O	-	A	-	6	-	C16	F11

I/O	ADD2	A	-	7	10	D15	D14

I/O	-	A	-	174	-	D3	C2

I/O	-	A	-	175	149	C2	E4

I/O	-	A	-	176	-	B1	G3

I/O	-	A	-	177	150	D4	H6

I/O	-	A	-	178	151	C3	J5

I/O	-	A	-	179	-	B2	C3

QFP	QFP

Function	Config. Pin	Row	Col	(240-pin)	(208-pin)	PGA	BGA

I/O	-	A	-	180	152	B3	B3

I/O	-	A	-	183	153	D5	A2

I/O	-	B	-	11	14	D16	C14

I/O	-	B	-	12	-	E15	C13

I/O	-	B	-	13	15	D17	D13

I/O	ADD3	B	-	14	16	F14	D15

I/O	-	B	-	15	-	E16	G10

I/O	ADD4	B	-	16	17	F15	E13

I/O	-	B	-	17	-	E17	F13

I/O	ADD5	B	-	18	18	F16	F14

I/O	-	B	-	163	-	F2	E2

I/O	-	B	-	164	141	E1	G5

I/O	-	B	-	165	-	F3	F3

I/O	nCS	B	-	166	142	E2	D1

I/O	-	B	-	167	143	F4	E3

I/O	-	B	-	168	-	D1	D2

I/O	CS	B	-	169	144	E3	C1

I/O	-	B	-	170	145	D2	D3

I/O	-	C	-	22	22	F17	F12

I/O	-	C	-	23	-	G16	F15

I/O	-	C	-	24	23	G17	G15

I/O	ADD6	C	-	25	24	H15	G11

I/O	-	C	-	26	-	H16	G12

I/O	ADD7	C	-	27	25	H17	G13

I/O	-	C	-	28	-	J17	H15

QFP	QFP

Function	Config. Pin	Row	Col	(240-pin)	(208-pin)	PGA	BGA

I/O	ADD8	C	-	29	26	J15	G14

I/O	-	C	-	152	-	J3	H1

I/O	-	C	-	153	133	J1	G1

I/O	-	C	-	154	-	H1	H5

I/O	CLKUSR	C	-	155	134	H2	G2

I/O	-	C	-	156	135	H3	G6

I/O	-	C	-	157	136	G1	G4

I/O	RDCLK	C	-	158	137	G2	F1

I/O	-	C	-	159	-	F1	F2

I/O	ADD9	D	-	32	29	J14	J15

I/O	-	D	-	33	-	J16	J12

I/O	ADD10	D	-	34	30	K17	J13

I/O	-	D	-	35	-	K16	J14

I/O	ADD11	D	-	36	31	K15	K15

I/O	-	D	-	37	-	L17	J11

I/O	-	D	-	38	32	L16	G9

I/O	-	D	-	39	-	M17	K14

I/O	-	D	-	142	125	M1	K2

I/O	-	D	-	143	126	L2	K1

I/O	-	D	-	144	-	L1	J2

I/O	-	D	-	145	127	K3	J1

I/O	RDYnBUSY	D	-	146	128	K2	J3

I/O	-	D	-	147	129	K1	J4

I/O	-	D	-	148	-	J2	J6

I/O	-	D	-	149	130	J4	H4

QFP	QFP

Function	Config. Pin	Row	Col	(240-pin)	(208-pin)	PGA	BGA

I/O	ADD12	E	-	43	36	M16	K13

I/O	-	E	-	44	-	N17	M13

I/O	ADD13	E	-	45	37	M15	L14

I/O	-	E	-	46	38	N16	P12

I/O	ADD14	E	-	47	39	M14	L13

I/O	-	E	-	48	-	P17	N12

I/O	-	E	-	49	40	N15	N15

I/O	-	E	-	50	-	P16	H11

I/O	-	E	-	131	-	P2	M1

I/O	-	E	-	132	117	N3	M2

I/O	nWS	E	-	133	118	P1	L4

I/O	-	E	-	134	-	M4	M3

I/O	SDOUT	E	-	135	119	N2	L6

I/O	-	E	-	136	120	M3	L3

I/O	nRS	E	-	137	121	N1	K5

I/O	-	E	-	138	-	M2	K3

I/O	ADD15	F	-	54	44	P15	M15

I/O	-	F	-	55	-	R16	N14

I/O	ADD16	F	-	56	45	T17	L12

I/O	-	F	-	57	-	P14	P14

I/O	ADD17	F	-	58	46	R15	M14

I/O	-	F	-	59	-	T16	P13

I/O	-	F	-	60	47	T15	R14

I/O	-	F	-	63	-	P13	R13

I/O	-	F	-	118	108	P5	R2

QFP	QFP

Function	Config. Pin	Row	Col	(240-pin)	(208-pin)	PGA	BGA

I/O	-	F	-	121	109	T3	P4

I/O	-	F	-	122	-	T2	R3

I/O	-	F	-	123	110	R3	P3

I/O	-	F	-	124	111	P4	N4

I/O	-	F	-	125	112	T1	N1

I/O	-	F	-	126	-	R2	M4

I/O	-	F	-	127	113	P3	N2

I/O	-	-	1	112	100	P6	M5

I/O	-	-	1	113	101	R5	L5

I/O	-	-	1	188	160	C5	A3

I/O	DATA0	-	1	189	161	A2	C4

I/O	-	-	2	110	98	T4	N5

I/O	-	-	2	111	99	U2	R4

I/O	-	-	2	190	162	B4	B4

I/O	DATA1	-	2	191	163	A3	D5

I/O	-	-	3	107	95	R6	G7

I/O	-	-	3	109	97	U3	P5

I/O	-	-	3	192	164	C6	A4

I/O	DATA2	-	3	194	166	B5	E6

I/O	-	-	4	105	93	P7	M6

I/O	-	-	4	106	94	T5	R5

I/O	-	-	4	195	167	A4	C5

I/O	DATA3	-	4	196	168	D7	B5

I/O	-	-	5	103	91	T6	P6

I/O	-	-	5	104	92	U4	N6

QFP	QFP

Function	Config. Pin	Row	Col	(240-pin)	(208-pin)	PGA	BGA

I/O	-	-	5	197	169	B6	E5

I/O	DATA4	-	5	198	170	C7	A5

I/O	-	-	6	101	89	U5	J7

I/O	-	-	6	102	90	R7	R6

I/O	-	-	6	199	171	A5	B6

I/O	DATA5	-	6	200	172	B7	A6

I/O	-	-	7	98	86	P8	N7

I/O	-	-	7	100	88	T7	L7

I/O	-	-	7	201	173	A6	D6

I/O	DATA6	-	7	203	175	D8	D7

I/O	-	-	8	96	84	R8	R7

I/O	-	-	8	97	85	U6	P7

I/O	-	-	8	204	176	C8	C7

I/O	DATA7	-	8	205	177	A7	A7

I/O	-	-	9	94	82	T8	H8

I/O	-	-	9	95	83	U7	M7

I/O	-	-	9	206	178	B8	B7

I/O	-	-	9	207	179	A8	D8

I/O	-	-	10	92	80	U9	P8

I/O	-	-	10	93	81	U8	N8

I/O	-	-	10	208	180	B9	C8

I/O	-	-	10	209	181	C9	B8

I/O	-	-	11	89	77	P9	M8

I/O	-	-	11	91	79	R9	R8

I/O	-	-	11	210	182	D9	A8

QFP	QFP

Function	Config. Pin	Row	Col	(240-pin)	(208-pin)	PGA	BGA

I/O	-	-	11	212	184	A9	E8

I/O	-	-	12	87	75	U10	L9

I/O	-	-	12	88	76	T9	L8

I/O	-	-	12	213	185	A10	E9

I/O	-	-	12	214	186	B10	D9

I/O	-	-	13	85	73	U11	R9

I/O	-	-	13	86	74	T10	P9

I/O	-	-	13	215	187	A11	C9

I/O	-	-	13	216	188	C10	A9

I/O	-	-	14	83	71	U12	N9

I/O	-	-	14	84	72	R10	J9

I/O	-	-	14	217	189	A12	F6

I/O	-	-	14	218	190	B11	B9

I/O	-	-	15	80	68	T11	H10

I/O	-	-	15	82	70	P10	M9

I/O	-	-	15	219	191	D10	E7

I/O	-	-	15	221	193	A13	D10

I/O	-	-	16	78	66	R11	M10

I/O	-	-	16	79	67	U13	R10

I/O	-	-	16	222	194	C11	A10

I/O	-	-	16	223	195	B12	B10

I/O	-	-	17	76	64	U14	K10

I/O	-	-	17	77	65	T12	L10

I/O	-	-	17	224	196	A14	C10

I/O	-	-	17	225	197	B13	E10

QFP	QFP

Function	Config. Pin	Row	Col	(240-pin)	(208-pin)	PGA	BGA

I/O	-	-	18	74	62	T13	R11

I/O	-	-	18	75	63	P11	J10

I/O	-	-	18	226	198	D11	C11

I/O	-	-	18	227	199	C12	A11

I/O	-	-	19	71	59	U15	N11

I/O	-	-	19	73	61	R12	P11

I/O	-	-	19	228	200	A15	B11

I/O	-	-	19	230	202	B14	D11

I/O	-	-	20	69	57	U16	L11

I/O	-	-	20	70	58	T14	M11

I/O	-	-	20	231	203	A16	E11

I/O	-	-	20	232	204	C13	D12

I/O	-	-	21	67	55	U17	M12

I/O	-	-	21	68	56	R13	R12

I/O	-	-	21	233	205	D12	A12

I/O	-	-	21	234	206	A17	B12

VCC	-	-	-	19	3	E4	-

VCC	-	-	-	20	4	E8	-

VCC	-	-	-	41	19	E10	-

VCC	-	-	-	42	20	E14	-

VCC	-	-	-	64	34	F5	-

VCC	-	-	-	65	35	F13	B15

VCC	-	-	-	66	48	H4	C6

VCC	-	-	-	81	49	H5	E1

VCC	-	-	-	99	50	H13	F5

QFP	QFP

Function	Config. Pin	Row	Col	(240-pin)	(208-pin)	PGA	BGA

VCC	-	-	-	114	69	H14	F10

VCC	-	-	-	116	87	K5	H2

VCC	-	-	-	128	102	K13	H3

VCC	-	-	-	140	106	L4	H12

VCC	-	-	-	150	114	L14	H13

VCC	-	-	-	162	123	M5	H14

VCC	-	-	-	172	131	M13	K4

VCC	-	-	-	186	140	N8	L2

VCC	-	-	-	202	147	N10	N10

VCC	-	-	-	220	156	P12	N13

VCC	-	-	-	235	174	R14	P10

VCC	-	-	-	236	192	U1	P15

GND	-	-	-	8	11	A1	-

GND	-	-	-	9	12	D6	-

GND	-	-	-	30	27	E7	B1

GND	-	-	-	31	28	E9	D4

GND	-	-	-	52	42	E11	E14

GND	-	-	-	53	43	G4	F7

GND	-	-	-	72	60	G5	F8

GND	-	-	-	90	78	G13	F9

GND	-	-	-	108	96	G14	G8

GND	-	-	-	115	105	J5	H7

GND	-	-	-	129	115	J13	H9

GND	-	-	-	139	122	K4	J8

GND	-	-	-	151	132	K14	K6

QFP	QFP

Function	Config. Pin	Row	Col	(240-pin)	(208-pin)	PGA	BGA

GND	-	-	-	161	139	L5	K7

GND	-	-	-	173	148	L13	K8

GND	-	-	-	185	155	N4	K9

GND	-	-	-	187	159	N7	K11

GND	-	-	-	193	165	N9	L15

GND	-	-	-	211	183	N11	N3

GND	-	-	-	229	201	N14	P1

N.C.	-	-	-	61	1	-	-

N.C.	-	-	-	62	2	-	-

N.C.	-	-	-	119	51	-	-

N.C.	-	-	-	120	52	-	-

N.C.	-	-	-	181	53	-	-

N.C.	-	-	-	182	54	-	-

N.C.	-	-	-	239	103	-	-

N.C.	-	-	-	240	104	-	-

N.C.	-	-	-	-	157	-	-

N.C.	-	-	-	-	158	-	-

N.C.	-	-	-	-	207	-	-

N.C.	-	-	-	-	208	-	-


EPF81500/EPF81500A Devices

The EPF81500 and EPF81500A, members of the FLEX 8000 device family, provide 1,500 registers and are well-suited for applications such as digital signal processing, wide data-path manipulation, and data transformation. The high-pin-count EPF81500 and EPF81500A devices can integrate multiple wide buses into a single device.

The EPF81500 and EPF81500A are available in 240-pin QFP packages with 177 I/O pins and 280-pin PGA and 304-pin QFP packages with 204 I/O pins. The devices have 1,296 logic cells grouped into 162 LABs. These LABs are arranged into 6 rows and 27 columns. Each I/O element contains a bidirectional I/O buffer and a flipflop that can be used as either an input or output register. The devices also contain 4 dedicated fast inputs for synchronous control signals with large fan-outs. When used as outputs, the I/O registers provide fast Clock-to-output times; as inputs, they provide quick setup times. For complete information on the EPF81500 and EPF81500A devices, refer to the current FLEX 8000 Programmable Logic Device Family Data Sheet.

Altera recommends using the EPF81500A rather than the EPF81500 for new designs.

See also:

EPC1 Configuration EPROM

EPC1064/EPC1064V Configuration EPROM

EPC1213 Configuration EPROM

FLEX 8000 Device Selection Guide

Recommended reading:

AN33 (Configuring FLEX 8000 Devices)

AN36 (Designing with FLEX 8000 Devices)

AN38 (Configuring Multiple FLEX 8000 Devices)

AN42 (Metastability in Altera Devices)

AB143 (Understanding FLEX 8000 Timing)

Operating Requirements for Altera Devices Data Sheet

QFP	QFP

Function	Config. Pin	Row	Col	(304-pin)	(240-pin)	PGA

Ded. Config. Pin	MSEL0	-	-	26	19	N1

Ded. Config. Pin	MSEL1	-	-	51	38	H3

Ded. Config. Pin	nCONFIG	-	-	152	120	B18

Ded. Config. Pin	nSTATUS	-	-	178	142	G19

Ded. Config. Pin	CONF_DONE	-	-	204	161	M16

Ded. Config. Pin	DCLK	-	-	230	183	U18

Ded. Config. Pin	nSP	-	-	304	237	W1

Ded. JTAG Pin	TDI	-	-	80	63	B1

Ded. JTAG Pin	TMS	-	-	81	64	C2

Ded. JTAG Pin	nTRST	-	-	145	115	A18

Ded. JTAG Pin	TCLK	-	-	148	116	A19

Ded. JTAG Pin	TDO	-	-	149	117	C17

Input	-	-	-	12	8	P3

Input	-	-	-	64	49	F1

Input	-	-	-	164	131	F16

Input	-	-	-	217	172	P19

I/O	-	A	-	1	238	U3

I/O	-	A	-	2	239	V2

I/O	-	A	-	3	240	T3

I/O	ADD0	A	-	4	1	V1

I/O	-	A	-	5	2	R3

I/O	ADD1	A	-	6	3	U2

I/O	-	A	-	7	4	R2

I/O	ADD2	A	-	8	5	U1

QFP	QFP

Function	Config. Pin	Row	Col	(304-pin)	(240-pin)	PGA

I/O	-	A	-	222	175	R18

I/O	-	A	-	223	176	R19

I/O	-	A	-	224	177	R17

I/O	-	A	-	225	178	T19

I/O	-	A	-	226	179	T18

I/O	-	A	-	227	180	U19

I/O	-	A	-	228	181	T17

I/O	-	A	-	229	182	V19

I/O	-	B	-	13	9	T2

I/O	-	B	-	14	10	P2

I/O	-	B	-	15	11	T1

I/O	ADD3	B	-	16	12	N4

I/O	-	B	-	17	13	R1

I/O	ADD4	B	-	18	14	N3

I/O	-	B	-	19	15	P1

I/O	ADD5	B	-	20	16	N2

I/O	-	B	-	209	164	M19

I/O	-	B	-	210	165	N17

I/O	-	B	-	211	166	M18

I/O	nCS	B	-	212	167	N16

I/O	-	B	-	213	168	N19

I/O	-	B	-	214	169	P18

I/O	CS	B	-	215	170	N18

I/O	-	B	-	216	171	P17

I/O	-	C	-	27	20	M4

QFP	QFP

Function	Config. Pin	Row	Col	(304-pin)	(240-pin)	PGA

I/O	-	C	-	28	21	M2

I/O	-	C	-	29	22	M3

I/O	ADD6	C	-	30	23	M1

I/O	-	C	-	31	24	L4

I/O	ADD7	C	-	32	25	L2

I/O	-	C	-	33	26	L3

I/O	ADD8	C	-	34	27	L1

I/O	-	C	-	196	153	K17

I/O	-	C	-	197	154	K18

I/O	-	C	-	198	155	L17

I/O	CLKUSR	C	-	199	156	K19

I/O	-	C	-	200	157	L16

I/O	-	C	-	201	158	L19

I/O	RDCLK	C	-	202	159	M17

I/O	-	C	-	203	160	L18

I/O	ADD9	D	-	43	30	K4

I/O	-	D	-	44	31	K2

I/O	ADD10	D	-	45	32	K3

I/O	-	D	-	46	33	K1

I/O	ADD11	D	-	47	34	J3

I/O	-	D	-	48	35	J1

I/O	-	D	-	49	36	J4

I/O	-	D	-	50	37	J2

I/O	-	D	-	179	143	H17

I/O	-	D	-	180	144	H18

QFP	QFP

Function	Config. Pin	Row	Col	(304-pin)	(240-pin)	PGA

I/O	-	D	-	181	145	J16

I/O	-	D	-	182	146	H19

I/O	RDYnBUSY	D	-	183	147	J17

I/O	-	D	-	184	148	J18

I/O	-	D	-	185	149	K16

I/O	-	D	-	186	150	J19

I/O	ADD12	E	-	56	41	H1

I/O	-	E	-	57	42	H4

I/O	ADD13	E	-	58	43	H2

I/O	-	E	-	59	44	G3

I/O	ADD14	E	-	60	45	G1

I/O	-	E	-	61	46	G4

I/O	-	E	-	62	47	G2

I/O	-	E	-	63	48	F3

I/O	-	E	-	165	132	E19

I/O	-	E	-	166	133	F17

I/O	nWS	E	-	167	134	F18

I/O	-	E	-	168	135	G16

I/O	SDOUT	E	-	169	136	F19

I/O	-	E	-	170	137	G17

I/O	nRS	E	-	171	138	G18

I/O	-	E	-	172	139	H16

I/O	ADD15	F	-	69	52	F4

I/O	-	F	-	70	53	F2

I/O	ADD16	F	-	71	54	E2

QFP	QFP

Function	Config. Pin	Row	Col	(304-pin)	(240-pin)	PGA

I/O	-	F	-	72	55	E1

I/O	ADD17	F	-	73	56	E3

I/O	-	F	-	74	57	D1

I/O	-	F	-	75	58	D2

I/O	-	F	-	76	59	C1

I/O	-	F	-	153	121	C18

I/O	-	F	-	154	122	B19

I/O	-	F	-	155	123	D17

I/O	-	F	-	156	124	C19

I/O	-	F	-	157	125	D18

I/O	-	F	-	158	126	D19

I/O	-	F	-	159	127	E17

I/O	-	F	-	160	128	E18

I/O	-	-	1	142	112	C16

I/O	-	-	1	143	113	A17

I/O	-	-	1	238	-	W19

I/O	DATA0	-	1	239	187	V17

I/O	-	-	2	140	111	B16

I/O	-	-	2	141	-	A16

I/O	-	-	2	240	188	V18

I/O	DATA1	-	2	241	189	U16

I/O	-	-	3	138	109	C15

I/O	-	-	3	139	110	A15

I/O	-	-	3	242	-	W18

I/O	DATA2	-	3	243	190	V16

QFP	QFP

Function	Config. Pin	Row	Col	(304-pin)	(240-pin)	PGA

I/O	-	-	4	135	107	B14

I/O	-	-	4	136	-	B15

I/O	-	-	4	245	192	U15

I/O	DATA3	-	4	246	193	W17

I/O	-	-	5	133	105	A14

I/O	-	-	5	134	106	C14

I/O	-	-	5	247	-	V15

I/O	DATA4	-	5	248	194	W16

I/O	-	-	6	131	104	B13

I/O	-	-	6	132	-	D13

I/O	-	-	6	249	195	U14

I/O	DATA5	-	6	250	196	W15

I/O	-	-	7	129	102	A13

I/O	-	-	7	130	103	D12

I/O	-	-	7	251	-	V14

I/O	DATA6	-	7	252	197	W14

I/O	-	-	8	126	100	C13

I/O	-	-	8	127	-	B12

I/O	DATA7	-	8	254	199	W13

I/O	-	-	8	255	200	T12

I/O	-	-	9	124	98	C12

I/O	-	-	9	125	99	A12

I/O	-	-	9	256	-	V12

I/O	-	-	9	257	201	U13

I/O	-	-	10	122	97	D11

QFP	QFP

Function	Config. Pin	Row	Col	(304-pin)	(240-pin)	PGA

I/O	-	-	10	123	-	B11

I/O	-	-	10	258	202	W12

I/O	-	-	10	259	203	T11

I/O	-	-	11	120	95	C11

I/O	-	-	11	121	96	A11

I/O	-	-	11	260	-	V11

I/O	-	-	11	261	204	U12

I/O	-	-	12	117	93	A10

I/O	-	-	12	118	-	C10

I/O	-	-	12	263	206	V13

I/O	-	-	12	264	207	W11

I/O	-	-	13	113	89	B10

I/O	-	-	13	114	90	D10

I/O	-	-	13	267	-	T10

I/O	-	-	13	268	210	V10

I/O	-	-	14	111	88	A9

I/O	-	-	14	112	-	B9

I/O	-	-	14	269	211	U11

I/O	-	-	14	270	212	W10

I/O	-	-	15	109	86	A8

I/O	-	-	15	110	87	B8

I/O	-	-	15	271	-	U10

I/O	-	-	15	272	213	W9

I/O	-	-	16	106	84	C9

I/O	-	-	16	107	-	A7

QFP	QFP

Function	Config. Pin	Row	Col	(304-pin)	(240-pin)	PGA

I/O	-	-	16	274	215	V9

I/O	-	-	16	275	216	U9

I/O	-	-	17	104	82	D9

I/O	-	-	17	105	83	A6

I/O	-	-	17	276	-	W8

I/O	-	-	17	277	217	T9

I/O	-	-	18	102	81	C8

I/O	-	-	18	103	-	A5

I/O	-	-	18	278	218	W7

I/O	-	-	18	279	219	V8

I/O	-	-	19	100	79	B7

I/O	-	-	19	101	80	B6

I/O	-	-	19	280	-	W6

I/O	-	-	19	281	220	U8

I/O	-	-	20	97	77	A4

I/O	-	-	20	98	-	C7

I/O	-	-	20	283	222	V7

I/O	-	-	20	284	223	V6

I/O	-	-	21	95	75	B5

I/O	-	-	21	96	76	D8

I/O	-	-	21	285	-	T8

I/O	-	-	21	286	224	W5

I/O	-	-	22	93	74	A3

I/O	-	-	22	94	-	D7

I/O	-	-	22	287	225	U7

QFP	QFP

Function	Config. Pin	Row	Col	(304-pin)	(240-pin)	PGA

I/O	-	-	22	288	226	V5

I/O	-	-	23	91	72	B4

I/O	-	-	23	92	73	C6

I/O	-	-	23	289	-	T7

I/O	-	-	23	290	227	W4

I/O	-	-	24	88	70	C5

I/O	-	-	24	89	-	A2

I/O	-	-	24	292	229	V4

I/O	-	-	24	293	230	U6

I/O	-	-	25	86	68	C4

I/O	-	-	25	87	69	B3

I/O	-	-	25	294	-	W3

I/O	-	-	25	295	231	U5

I/O	-	-	26	84	67	D6

I/O	-	-	26	85	-	A1

I/O	-	-	26	296	232	V3

I/O	-	-	26	297	233	T6

I/O	-	-	27	82	65	C3

I/O	-	-	27	83	66	B2

I/O	-	-	27	298	-	W2

I/O	-	-	27	299	234	U4

VCC	-	-	-	22	17	B17

VCC	-	-	-	24	18	D3

VCC	-	-	-	53	39	D14

VCC	-	-	-	54	40	D15

QFP	QFP

Function	Config. Pin	Row	Col	(304-pin)	(240-pin)	PGA

VCC	-	-	-	77	60	E7

VCC	-	-	-	78	61	E8

VCC	-	-	-	79	62	E9

VCC	-	-	-	99	78	E10

VCC	-	-	-	115	91	E11

VCC	-	-	-	119	94	E12

VCC	-	-	-	137	108	E13

VCC	-	-	-	144	114	E14

VCC	-	-	-	162	129	R6

VCC	-	-	-	163	130	R7

VCC	-	-	-	191	151	R8

VCC	-	-	-	193	152	R9

VCC	-	-	-	218	173	R10

VCC	-	-	-	220	174	R11

VCC	-	-	-	244	191	R12

VCC	-	-	-	262	205	R13

VCC	-	-	-	266	209	R14

VCC	-	-	-	282	221	T13

VCC	-	-	-	300	235	T14

VCC	-	-	-	301	236	T15

GND	-	-	-	-	6	D4

GND	-	-	-	-	7	D5

GND	-	-	-	-	28	D16

GND	-	-	-	-	29	E4

GND	-	-	-	-	50	E5

QFP	QFP

Function	Config. Pin	Row	Col	(304-pin)	(240-pin)	PGA

GND	-	-	-	-	51	E6

GND	-	-	-	-	71	E15

GND	-	-	-	-	85	E16

GND	-	-	-	-	92	F5

GND	-	-	-	-	101	F15

GND	-	-	-	-	118	G5

GND	-	-	-	-	119	G15

GND	-	-	-	-	140	H5

GND	-	-	-	9	141	H15

GND	-	-	-	11	162	J5

GND	-	-	-	36	163	J15

GND	-	-	-	38	184	K5

GND	-	-	-	65	185	K15

GND	-	-	-	67	186	L5

GND	-	-	-	90	198	L15

GND	-	-	-	108	208	M5

GND	-	-	-	116	214	M15

GND	-	-	-	128	228	N5

GND	-	-	-	150	-	N15

GND	-	-	-	151	-	P4

GND	-	-	-	175	-	P5

GND	-	-	-	177	-	P15

GND	-	-	-	206	-	P16

GND	-	-	-	208	-	R4

GND	-	-	-	231	-	R5

QFP	QFP

Function	Config. Pin	Row	Col	(304-pin)	(240-pin)	PGA

GND	-	-	-	232	-	R15

GND	-	-	-	237	-	R16

GND	-	-	-	253	-	T4

GND	-	-	-	265	-	T5

GND	-	-	-	273	-	T16

GND	-	-	-	291	-	U17

N.C.	-	-	-	10	-	-

N.C.	-	-	-	21	-	-

N.C.	-	-	-	23	-	-

N.C.	-	-	-	25	-	-

N.C.	-	-	-	35	-	-

N.C.	-	-	-	37	-	-

N.C.	-	-	-	39	-	-

N.C.	-	-	-	40	-	-

N.C.	-	-	-	41	-	-

N.C.	-	-	-	42	-	-

N.C.	-	-	-	52	-	-

N.C.	-	-	-	55	-	-

N.C.	-	-	-	66	-	-

N.C.	-	-	-	68	-	-

N.C.	-	-	-	146	-	-

N.C.	-	-	-	147	-	-

N.C.	-	-	-	161	-	-

N.C.	-	-	-	173	-	-

N.C.	-	-	-	174	-	-

QFP	QFP

Function	Config. Pin	Row	Col	(304-pin)	(240-pin)	PGA

N.C.	-	-	-	176	-	-

N.C.	-	-	-	187	-	-

N.C.	-	-	-	188	-	-

N.C.	-	-	-	189	-	-

N.C.	-	-	-	190	-	-

N.C.	-	-	-	192	-	-

N.C.	-	-	-	194	-	-

N.C.	-	-	-	195	-	-

N.C.	-	-	-	205	-	-

N.C.	-	-	-	207	-	-

N.C.	-	-	-	219	-	-

N.C.	-	-	-	221	-	-

N.C.	-	-	-	233	-	-

N.C.	-	-	-	234	-	-

N.C.	-	-	-	235	-	-

N.C.	-	-	-	236	-	-

N.C.	-	-	-	302	-	-

N.C.	-	-	-	303	-	-


FLEX 8000 Device Selection Guide

The following table provides information on the FLEX 8000 family of programmable logic devices.

For up-to-date information on device availability, contact Altera Marketing. For more information on the FLEX 8000 devices, refer to the Altera Data Book, or contact the Altera Literature Department for a copy of the FLEX 8000 Programmable Logic Device Family Data Sheet.

Device	Package	Temp.	Speed	LCell	Flipflops	Ded.	I/O	Configuration

Note (1)	Note (2)	Note (3)	Grade	Inputs	EPROM

EPF8282A	84L,100T	C	-4,-3,-2	208	282	4	64,74	EPC1064

EPF8282A	84L	I	-4	208	282	4	64,74	EPC1064

EPF8282	84L,100T	C	-2,-3	208	282	4	64,74	EPC1064

EPF8282	84L	I	-3	208	282	4	64	EPC1064

EPF8282V	84L,100T	C	-3,-4	208	282	4	64,74	EPC1064V

EPF8452A	84L,100T,160G,160Q	C	-6,-5,-4,-3	336	452	4	64,64,116,116	EPC1064

EPF8452A	84L	I	-4	336	452	4	64	EPC1064

EPF8452	84L,160Q	C	-2,-3	336	452	4	64,116	EPC1064

EPF8636A	84L,160Q,192G,208R	C	-5,-4,-3	504	636	4	64,116,132,132	EPC1213

EPF8636A	84L	I	-4	504	636	4	64	EPC1213

EPF8820A	160Q,192G,208R	C	-4,-3,-2	672	820	4	116,148,148	EPC1213

EPF8820A	225B	C	-4,-3	672	820	4	148	EPC1213

EPF8820A	208R	I	-4	672	820	4	148	EPC1213

EPF8820	208R	C	-2,-3	672	820	4	148	EPC1213

EPF8820	192G,208R	I	-3	672	820	4	148,148	EPC1213

EPF8820	192G,208W	M	-3	672	820	4	148,148	EPC1213

EPF81188A	232G,240R	C	-6,-5,-4,-3,-2	1,008	1,188	4	180,180	EPC1213

EPF81188A	208Q	C	-4,-3,-2	1,008	1,188	4	148	EPC1213

EPF81188A	208Q,240R	I	-4	1,008	1,188	4	180	EPC1213

EPF81188	232G,240R	C	-2,-3	1,008	1,188	4	180,180	EPC1213

EPF81188	232G,240R	I	-3	1,008	1,188	4	180,180	EPC1213

EPF81188	232G	M	-3	1,008	1,188	4	180	EPC1213

EPF81500A	240R,280G,304R	C	-4,-3,-2	1,296	1,500	4	180,204,204	EPC1213

EPF81500	280G,304R	C	-2,-3	1,296	1,500	4	204,204	EPC1213

Recommended reading:

AN33 (Configuring FLEX 8000 Devices)

AN36 (Designing with FLEX 8000 Devices)

AN38 (Configuring Multiple FLEX 8000 Devices)

AN39 (JTAG Boundary-Scan Testing in Altera Devices)

AN42 (Metastability in Altera Devices)

AB46 (Selecting Sockets for J-Lead Packages)

AB60 (Estimating a Design Fit)

AB143 (Understanding FLEX 8000 Timing)

Altera Device Package Outlines Data Sheet

Operating Requirements for Altera Devices Data Sheet

QFP Carrier & Development Socket Data Sheet


EPF10K50 Devices

The EPF10K50, a member of the FLEX 10K device family, provides 3,184 registers, 20,480 memory bits, and 36,000 to 116,000 usable gates. It is suitable for memory functions and complex logic functions such as digital signal processing, wide data-path manipulation, data transformation, and microcontrollers. The high-pin-count EPF10K50 device contains an embedded array to implement memory functions and a logic array to implement general logic functions. You can integrate entire systems, including 32-bit buses, into a single EPF10K50 device.

The EPF10K50 is available in 403-pin PGA packages with 310 I/O pins. The device has 2,880 logic cells grouped into 360 LABs. These LABs are arranged into 10 rows and 36 columns. The embedded array consists of a series of EABs, each of which provides 2,048 bits which can be used to create RAM or ROM or to contribute 100 to 300 gates towards complex logic functions. Each I/O cell contains a bidirectional I/O buffer and a flipflop that can be used as either an input or output register. The EPF10K50 also contains 6 dedicated fast inputs for synchronous control signals with large fan-outs. When used as outputs, the I/O registers provide fast Clock-to-output times; as inputs, they provide quick setup times. For complete information on the EPF10K50 device, refer to the current FLEX 10K Programmable Logic Device Family Data Sheet or the Altera Data Book.

See also:

EPC1 Configuration EPROM

FLEX 10K Device Selection Guide

Recommended reading:

AN39 (JTAG Boundary-Scan Testing in Altera Devices)

AN42 (Metastability in Altera Devices)

AN59 (Configuring FLEX 10K Devices)

Operating Requirements for Altera Devices Data Sheet

Function	Config. Pin	Row	Col	PGA

Ded. Config. Pin	MSEL0	-	-	AN1

Ded. Config. Pin	MSEL1	-	-	AR1

Ded. Config. Pin	nCONFIG	-	-	AU1

Ded. Config. Pin	nSTATUS	-	-	AU37

Ded. Config. Pin	DATA0	-	-	C1

Ded. Config. Pin	CONF_DONE	-	-	C37

Ded. Config. Pin	DCLK	-	-	E1

Ded. Config. Pin	nCEO	-	-	E37

Ded. Config. Pin	nCE	-	-	G1

Ded. JTAG Pin	TMS	-	-	AN37

Ded. JTAG Pin	nTRST	-	-	AR37

Ded. JTAG Pin	TCLK	-	-	A37

Ded. JTAG Pin	TDO	-	-	G37

Ded. JTAG Pin	TDI	-	-	J1

Input	-	-	-	AU17

Input	-	-	-	AU21

Input	-	-	-	A17

Input	-	-	-	A21

Input/GCLK	-	-	-	AU19

Input/GCLK	-	-	-	A19

I/O	-	A	-	A3

I/O	-	A	-	B4

I/O	-	A	-	B34

I/O	-	A	-	C3

I/O	-	A	-	C35

Function	Config. Pin	Row	Col	PGA

 I/O	-	A	-	D2

I/O	-	A	-	D32

I/O	-	A	-	D36

I/O	-	A	-	E35

I/O	-	A	-	F4

I/O	-	A	-	F34

I/O	-	A	-	G5

I/O	-	A	-	G7

I/O	-	A	-	G31

I/O	-	A	-	H6

I/O	-	A	-	H32

I/O	-	B	-	E3

I/O	-	B	-	F2

I/O	-	B	-	F36

I/O	-	B	-	G3

I/O	CLKUSR	B	-	G35

I/O	-	B	-	H2

I/O	-	B	-	H4

I/O	-	B	-	H34

I/O	-	B	-	H36

I/O	-	B	-	J3

I/O	-	B	-	J5

I/O	-	B	-	J33

I/O	-	B	-	J35

I/O	-	B	-	K6

Function	Config. Pin	Row	Col	PGA

 I/O	-	B	-	K32

I/O	-	B	-	K34

I/O	-	C	-	J37

I/O	-	C	-	K4

I/O	-	C	-	L1

I/O	-	C	-	L3

I/O	-	C	-	L35

I/O	-	C	-	L37

I/O	-	C	-	M2

I/O	-	C	-	M4

I/O	-	C	-	M6

I/O	-	C	-	M32

I/O	-	C	-	M34

I/O	-	C	-	M36

I/O	-	C	-	N5

I/O	-	C	-	N7

I/O	-	C	-	N31

I/O	-	C	-	N33

I/O	-	D	-	N1

I/O	-	D	-	N3

I/O	RDYnBUSY	D	-	N35

I/O	-	D	-	N37

I/O	-	D	-	P2

I/O	-	D	-	P6

I/O	-	D	-	P32

Function	Config. Pin	Row	Col	PGA

I/O	-	D	-	P36

I/O	-	D	-	R3

I/O	-	D	-	R5

I/O	-	D	-	R7

I/O	-	D	-	R31

I/O	-	D	-	R33

I/O	INIT_DONE	D	-	R35

I/O	-	D	-	T4

I/O	-	D	-	T34

I/O	-	E	-	R1

I/O	-	E	-	R37

I/O	-	E	-	U1

I/O	-	E	-	U3

I/O	-	E	-	U7

I/O	-	E	-	U31

I/O	-	E	-	U33

I/O	-	E	-	U35

I/O	-	E	-	U37

I/O	-	E	-	V2

I/O	-	E	-	V4

I/O	-	E	-	V34

I/O	-	E	-	V36

I/O	-	E	-	W3

I/O	-	E	-	W7

I/O	-	E	-	W37

Function	Config. Pin	Row	Col	PGA

I/O	-	F	-	AA1

I/O	-	F	-	AA3

I/O	-	F	-	AA5

I/O	-	F	-	AA7

I/O	-	F	-	AA31

I/O	-	F	-	AA35

I/O	-	F	-	AA37

I/O	-	F	-	AB34

I/O	-	F	-	AC1

I/O	-	F	-	W1

I/O	-	F	-	W31

I/O	-	F	-	W35

I/O	-	F	-	Y2

I/O	-	F	-	Y4

I/O	-	F	-	Y34

I/O	-	F	-	Y36

I/O	-	G	-	AB4

I/O	-	G	-	AC3

I/O	-	G	-	AC5

I/O	-	G	-	AC7

I/O	-	G	-	AC31

I/O	-	G	-	AC33

I/O	-	G	-	AC35

I/O	-	G	-	AC37

I/O	-	G	-	AD2

Function	Config. Pin	Row	Col	PGA

I/O	-	G	-	AD6

I/O	-	G	-	AD32

I/O	-	G	-	AD36

I/O	-	G	-	AE1

I/O	-	G	-	AE3

I/O	-	G	-	AE35

I/O	-	G	-	AE37

I/O	-	H	-	AE7

I/O	-	H	-	AE31

I/O	-	H	-	AE33

I/O	-	H	-	AF2

I/O	-	H	-	AF4

I/O	-	H	-	AF6

I/O	-	H	-	AF32

I/O	-	H	-	AF34

I/O	-	H	-	AF36

I/O	-	H	-	AG1

I/O	-	H	-	AG3

I/O	-	H	-	AG35

I/O	-	H	-	AG37

I/O	-	H	-	AH4

I/O	-	H	-	AJ1

I/O	-	H	-	AJ37

I/O	-	I	-	AH6

I/O	-	I	-	AH32

Function	Config. Pin	Row	Col	PGA

I/O	-	I	-	AH34

I/O	-	I	-	AJ3

I/O	-	I	-	AJ5

I/O	-	I	-	AJ33

I/O	-	I	-	AJ35

I/O	-	I	-	AK2

I/O	-	I	-	AK4

I/O	-	I	-	AK34

I/O	-	I	-	AK36

I/O	-	I	-	AL1

I/O	-	I	-	AL3

I/O	-	I	-	AL35

I/O	-	I	-	AL37

I/O	-	I	-	AM2

I/O	-	J	-	AK6

I/O	-	J	-	AK32

I/O	-	J	-	AL7

I/O	-	J	-	AL31

I/O	-	J	-	AL33

I/O	-	J	-	AM4

I/O	-	J	-	AM34

I/O	-	J	-	AM36

I/O	-	J	-	AN3

I/O	-	J	-	AN35

I/O	-	J	-	AP2

Function	Config. Pin	Row	Col	PGA

I/O	-	J	-	AP36

I/O	-	J	-	AR3

I/O	-	J	-	AR35

I/O	-	J	-	AT4

I/O	-	J	-	AU3

I/O	-	-	1	AP6

I/O	-	-	1	AR5

I/O	DATA1	-	1	C5

I/O	-	-	1	D6

I/O	-	-	2	AM8

I/O	-	-	2	AN7

I/O	DATA2	-	2	E7

I/O	-	-	2	F8

I/O	-	-	3	AT6

I/O	-	-	3	AU5

I/O	DATA3	-	3	A5

I/O	-	-	3	B6

I/O	-	-	4	AP8

I/O	-	-	4	AR7

I/O	DATA4	-	4	C7

I/O	-	-	4	D8

I/O	-	-	5	AM10

I/O	-	-	5	AN9

I/O	DATA5	-	5	E9

I/O	-	-	5	F10

Function	Config. Pin	Row	Col	PGA

I/O	-	-	6	AT8

I/O	-	-	6	AU7

I/O	DATA6	-	6	A7

I/O	-	-	6	B8

I/O	-	-	7	AP10

I/O	-	-	7	AR9

I/O	DATA7	-	7	C9

I/O	-	-	7	D10

I/O	-	-	8	AM12

I/O	-	-	8	AU9

I/O	-	-	8	A9

I/O	-	-	8	F12

I/O	-	-	9	AL13

I/O	-	-	9	AR11

I/O	-	-	9	C11

I/O	-	-	9	G13

I/O	-	-	10	AP12

I/O	-	-	10	AU11

I/O	-	-	10	A11

I/O	-	-	10	D12

I/O	-	-	11	AN13

I/O	-	-	11	AT12

I/O	-	-	11	B12

I/O	-	-	11	E13

I/O	-	-	12	AM14

Function	Config. Pin	Row	Col	PGA

I/O	-	-	12	AR13

I/O	-	-	12	C13

I/O	-	-	12	F14

I/O	-	-	13	AL15

I/O	-	-	13	AU13

I/O	-	-	13	A13

I/O	-	-	13	G15

I/O	-	-	14	AN15

I/O	-	-	14	AT14

I/O	-	-	14	B14

I/O	-	-	14	E15

I/O	-	-	15	AL17

I/O	-	-	15	AP16

I/O	-	-	15	C15

I/O	-	-	15	D16

I/O	-	-	16	AP18

I/O	-	-	16	AR15

I/O	-	-	16	A15

I/O	-	-	16	G17

I/O	-	-	17	AR17

I/O	-	-	17	AT18

I/O	-	-	17	D18

I/O	-	-	17	E17

I/O	-	-	18	AL19

I/O	-	-	18	AU15

Function	Config. Pin	Row	Col	PGA

I/O	-	-	18	B18

I/O	DEV_CLRn	-	18	C17

I/O	-	-	19	AR19

I/O	-	-	19	AT20

I/O	DEV_OE	-	19	C19

I/O	-	-	19	G19

I/O	-	-	20	AP20

I/O	-	-	20	AR21

I/O	-	-	20	B20

I/O	-	-	20	C21

I/O	-	-	21	AL21

I/O	-	-	21	AU23

I/O	-	-	21	A23

I/O	-	-	21	D20

I/O	-	-	22	AP22

I/O	-	-	22	AR23

I/O	-	-	22	C23

I/O	-	-	22	G21

I/O	-	-	23	AN23

I/O	-	-	23	AT24

I/O	-	-	23	D22

I/O	-	-	23	E23

I/O	-	-	24	AL23

I/O	-	-	24	AU25

I/O	-	-	24	A25

Function	Config. Pin	Row	Col	PGA

I/O	-	-	24	B24

I/O	-	-	25	AM24

I/O	-	-	25	AR25

I/O	-	-	25	C25

I/O	-	-	25	G23

I/O	-	-	26	AT26

I/O	-	-	26	AU27

I/O	-	-	26	A27

I/O	-	-	26	F24

I/O	-	-	27	AL25

I/O	-	-	27	AP26

I/O	-	-	27	B26

I/O	-	-	27	C27

I/O	-	-	28	AM26

I/O	-	-	28	AR27

I/O	-	-	28	A29

I/O	-	-	28	D26

I/O	-	-	29	AP28

I/O	-	-	29	AU29

I/O	-	-	29	C29

I/O	-	-	29	G25

I/O	-	-	30	AR29

I/O	-	-	30	AT30

I/O	-	-	30	A31

I/O	-	-	30	F26

Function	Config. Pin	Row	Col	PGA

I/O	-	-	31	AM28

I/O	-	-	31	AU31

I/O	-	-	31	D28

I/O	-	-	31	E29

I/O	-	-	32	AP30

I/O	-	-	32	AR31

I/O	-	-	32	B30

I/O	-	-	32	C31

I/O	-	-	33	AT32

I/O	-	-	33	AU33

I/O	nRS	-	33	A33

I/O	-	-	33	F28

I/O	-	-	34	AM30

I/O	-	-	34	AN31

I/O	-	-	34	D30

I/O	nWS	-	34	E31

I/O	-	-	35	AP32

I/O	-	-	35	AR33

I/O	-	-	35	B32

I/O	CS	-	35	C33

I/O	-	-	36	AT34

I/O	-	-	36	AU35

I/O	nCS	-	36	A35

I/O	-	-	36	F30

VCC	-	-	-	AB36

Function	Config. Pin	Row	Col	PGA

VCC	-	-	-	AD34

VCC	-	-	-	AE5

VCC	-	-	-	AG5

VCC	-	-	-	AG33

VCC	-	-	-	AH2

VCC	-	-	-	AL5

VCC	-	-	-	AM6

VCC	-	-	-	AM18

VCC	-	-	-	AM20

VCC	-	-	-	AM32

VCC	-	-	-	AN11

VCC	-	-	-	AN25

VCC	-	-	-	AN27

VCC	-	-	-	AN29

VCC	-	-	-	AP4

VCC	-	-	-	AP24

VCC	-	-	-	AT16

VCC	-	-	-	AT22

VCC	-	-	-	AT36

VCC	-	-	-	B2

VCC	-	-	-	B22

VCC	-	-	-	D14

VCC	-	-	-	D34

VCC	-	-	-	E11

VCC	-	-	-	E25

Function	Config. Pin	Row	Col	PGA

VCC	-	-	-	E27

VCC	-	-	-	F16

VCC	-	-	-	F22

VCC	-	-	-	K36

VCC	-	-	-	L5

VCC	-	-	-	L33

VCC	-	-	-	P4

VCC	-	-	-	T2

VCC	-	-	-	T6

VCC	-	-	-	T32

VCC	-	-	-	T36

VCC	-	-	-	V6

VCC	-	-	-	V32

GND	-	-	-	AA33

GND	-	-	-	AB2

GND	-	-	-	AB6

GND	-	-	-	AB32

GND	-	-	-	AD4

GND	-	-	-	AH36

GND	-	-	-	AM16

GND	-	-	-	AM22

GND	-	-	-	AN5

GND	-	-	-	AN17

GND	-	-	-	AN19

GND	-	-	-	AN21

Function	Config. Pin	Row	Col	PGA

GND	-	-	-	AN33

GND	-	-	-	AP14

GND	-	-	-	AP34

GND	-	-	-	AT2

GND	-	-	-	AT10

GND	-	-	-	AT28

GND	-	-	-	B10

GND	-	-	-	B16

GND	-	-	-	B28

GND	-	-	-	B36

GND	-	-	-	D4

GND	-	-	-	D24

GND	-	-	-	E5

GND	-	-	-	E19

GND	-	-	-	E21

GND	-	-	-	E33

GND	-	-	-	F6

GND	-	-	-	F18

GND	-	-	-	F20

GND	-	-	-	F32

GND	-	-	-	G33

GND	-	-	-	K2

GND	-	-	-	P34

GND	-	-	-	U5

GND	-	-	-	W5

Function	Config. Pin	Row	Col	PGA

GND	-	-	-	W33

GND	-	-	-	Y6

GND	-	-	-	Y32


FLEX 10K Device Selection Guide

The following table provides information on the FLEX 10K family of programmable logic devices.

For up-to-date information on device availability, contact Altera Marketing. For more information on FLEX 10K devices, refer to the Altera Data Book or contact the Altera Literature Department for a copy of the FLEX 10K Programmable Logic Device Family Data Sheet.

Device	Package	Temp.	Speed	LCells	Flipflops	Memory	Ded.	I/O	Configuration

Note (1)	Note (2)	Note (3)	Grade	Bits	Inputs	EPROM

EPF10K50	403G	C	-4	2,880	3,184	20,480	6	310	EPC1

EPF10K50	403G	C,I	-5	2,880	3,184	20,480	6	310	EPC1

Recommended reading:

AN39 (JTAG Boundary-Scan Testing in Altera Devices)

AN42 (Metastability in Altera Devices)

AN59 (Configuring FLEX 10K Devices)

AB60 (Estimating a Design Fit)

Altera Device Package Outlines Data Sheet

Operating Requirements for Altera Devices Data Sheet


EPM7032 EPLDs

The high-density EPM7032 EPLD, a member of the MAX 7000 family, is based on second-generation MAX architecture and has 625 usable gates. The EPM7032 EPLD can accommodate up to 36 inputs or 32 outputs, and has 32 logic cells divided into 2 LABs. Configurable expander product-term distribution allows up to 32 product terms per logic cell. The EPM7032 is available in reprogrammable plastic 44-pin QFP and J-lead packages, as shown in the table below. For complete information on EPM7032 EPLDs, refer to the current MAX 7000 Programmable Logic Device Family Data Sheet.

See also:

MAX 7000 EPLD Selection Guide

Recommended reading:

AN26 (EPLD/MPLD Design Guidelines)

AN31 (Fitting Designs in MAX 7000 EPLDs)

AB9 (Asynchronous Latches in Classic, MAX & STG EPLDs)

AB60 (Estimating a Design Fit)

AB87 (Troubleshooting Functional Problems in EPLDs)

AB89 (Minimizing Output Switching Noise in Altera EPLDs)

AB91 (External Clock Sources for Altera EPLDs)

AB94 (Solutions to Design Timing Problems for Altera EPLDs)

AB100 (Understanding Classic, MAX 5000 & MAX 7000 Timing)

Altera Device Package Outlines Data Sheet

Operating Requirements for Altera Devices Data Sheet

Function	LCell	LAB	QFP	J-Lead

Input/GCLK	-	-	37	43

Input/GCLRn	-	-	39	1

Input/OE1n	-	-	38	44

Input/OE2n	-	-	40	2

I/O or Buried	1	A	42	4

I/O or Buried	2	A	43	5

I/O or Buried	3	A	44	6

I/O or Buried	4	A	1	7

I/O or Buried	5	A	2	8

I/O or Buried	6	A	3	9

I/O or Buried	7	A	5	11

I/O or Buried	8	A	6	12

I/O or Buried	9	A	7	13

I/O or Buried	10	A	8	14

I/O or Buried	11	A	10	16

I/O or Buried	12	A	11	17

I/O or Buried	13	A	12	18

I/O or Buried	14	A	13	19

I/O or Buried	15	A	14	20

I/O or Buried	16	A	15	21

I/O or Buried	17	B	35	41

I/O or Buried	18	B	34	40

I/O or Buried	19	B	33	39

I/O or Buried	20	B	32	38

Function	LCell	LAB	QFP	J-Lead

I/O or Buried	21	B	31	37

I/O or Buried	22	B	30	36

I/O or Buried	23	B	28	34

I/O or Buried	24	B	27	33

I/O or Buried	25	B	26	32

I/O or Buried	26	B	25	31

I/O or Buried	27	B	23	29

I/O or Buried	28	B	22	28

I/O or Buried	29	B	21	27

I/O or Buried	30	B	20	26

I/O or Buried	31	B	19	25

I/O or Buried	32	B	18	24

VCC	-	-	9	3

VCC	-	-	17	15

VCC	-	-	29	23

VCC	-	-	41	35

GND	-	-	4	10

GND	-	-	16	22

GND	-	-	24	30

GND	-	-	36	42


EPM7032V EPLDs

The high-density EPM7032V EPLD, a member of the MAX 7000 family, is a high-performance MAX 7000 EPLD that meets the low power and voltage requirements of 3.3-V applications ranging from notebook computers to battery-operated, hand-held equipment. The EPM7032V EPLD can accommodate up to 36 inputs or 32 outputs, and has 32 logic cells divided into 2 LABs. Configurable expander product-term distribution allows up to 32 product terms per logic cell. The EPM7032V provides a unique power-down mode that is ideal for power-sensitive applications.

The EPM7032V is available in reprogrammable plastic 44-pin QFP and J-lead packages, as shown in the table below. For complete information on EPM7032V EPLDs, refer to the current MAX 7000 Programmable Logic Device Family Data Sheet.

See also:

MAX 7000 EPLD Selection Guide

Recommended reading:

AN26 (EPLD/MPLD Design Guidelines)

AN31 (Fitting Designs in MAX 7000 EPLDs)

AN42 (Metastability in Altera Devices)

AB9 (Asynchronous Latches in Classic, MAX & STG EPLDs)

AB60 (Estimating a Design Fit)

AB87 (Troubleshooting Functional Problems in EPLDs)

AB89 (Minimizing Output Switching Noise in Altera EPLDs)

AB91 (External Clock Sources for Altera EPLDs)

AB94 (Solutions to Design Timing Problems for Altera EPLDs)

AB100 (Understanding Classic, MAX 5000 & MAX 7000 Timing)

Altera Device Package Outlines Data Sheet

Operating Requirements for Altera Devices Data Sheet

Function	LCell	LAB	QFP	J-Lead

Input/GCLK	-	-	37	43

Input/GCLRn	-	-	39	1

Input/OE1n	-	-	38	44

Input/OE2n	-	-	40	2

I/O or Buried	1	A	42	4

I/O or Buried	2	A	43	5

I/O or Buried	3	A	44	6

I/O or Buried	4	A	1	7

I/O or Buried	5	A	2	8

I/O or Buried	6	A	3	9

I/O or Buried	7	A	5	11

I/O or Buried	8	A	6	12

I/O or Buried	9	A	7	13

I/O or Buried	10	A	8	14

I/O or Buried	11	A	10	16

I/O or Buried	12	A	11	17

I/O or Buried	13	A	12	18

I/O or Buried	14	A	13	19

I/O or Buried	15	A	14	20

I/O or Buried	16	A	15	21

I/O or Buried	17	B	35	41

I/O or Buried	18	B	34	40

I/O or Buried	19	B	33	39

I/O or Buried	20	B	32	38

Function	LCell	LAB	QFP	J-Lead

I/O or Buried	21	B	31	37

I/O or Buried	22	B	30	36

I/O or Buried	23	B	28	34

I/O or Buried	24	B	27	33

I/O or Buried	25	B	26	32

I/O or Buried	26	B	25	31

I/O or Buried	27	B	23	29

I/O or Buried	28	B	22	28

I/O or Buried	29	B	21	27

I/O or Buried	30	B	20	26

I/O or Buried	31	B	19	25

I/O or Buried	32	B	18	24

PDn  Note (1)	-	-	41	3

VCC	-	-	17	15

VCC	-	-	29	23

VCC	-	-	9	35

GND	-	-	4	10

GND	-	-	16	22

GND	-	-	24	30

GND	-	-	36	42


Note 1
Note (1)

When PDn is asserted (i.e., brought to ground), the power-down sequence latches all inputs, internal logic, and output pins of the EPM7032V, preserving their present state. In this mode, the device consumes near-zero power (typically 50 µA).


EPM7064 EPLDs

The high-density EPM7064 EPLD, a member of the MAX 7000 family, is based on second-generation MAX architecture and has 1,200 usable gates. The EPM7064 EPLD can accommodate up to 68 inputs or 64 outputs, and has 64 logic cells divided into 4 LABs. Configurable expander product-term distribution allows up to 32 product terms per logic cell. The EPM7064 is available in 44-, 68-, and 84-pin plastic J-lead packages and 44- and 100-pin QFP packages. For complete information on EPM7064 EPLDs, refer to the current MAX 7000 Programmable Logic Device Family Data Sheet.

See also:

MAX 7000 EPLD Selection Guide

Recommended reading:

AN26 (EPLD/MPLD Design Guidelines)

AN31 (Fitting Designs in MAX 7000 EPLDs)

AN42 (Metastability in Altera Devices)

AB9 (Asynchronous Latches in Classic, MAX & STG EPLDs)

AB60 (Estimating a Design Fit)

AB87 (Troubleshooting Functional Problems in EPLDs)

AB89 (Minimizing Output Switching Noise in Altera EPLDs)

AB91 (External Clock Sources for Altera EPLDs)

AB94 (Solutions to Design Timing Problems for Altera EPLDs)

AB100 (Understanding Classic, MAX 5000 & MAX 7000 Timing)

Altera Device Package Outlines Data Sheet

Operating Requirements for Altera Devices Data Sheet

QFP	QFP	J-Lead	J-Lead	J-Lead

Function	LCell	LAB	(100-pin)	(44-pin)	(84-pin)	(68-pin)	(44-pin)

Input/GCLK	-	-	89	37	83	67	43

Input/GCLRn	-	-	91	39	1	1	1

Input/OE1n	-	-	90	38	84	68	44

Input/OE2n	-	-	92	40	2	2	2

I/O or Buried	1	A	16	6	22	18	12

I/O or Buried	2	A	15	-	21	-	-

I/O or Buried	3	A	14	5	20	17	11

I/O or Buried	4	A	12	3	18	15	9

I/O or Buried	5	A	11	2	17	14	8

I/O or Buried	6	A	10	-	16	13	-

I/O or Buried	7	A	8	-	15	-	-

I/O or Buried	8	A	6	1	14	12	7

I/O or Buried	9	A	4	-	12	10	-

I/O or Buried	10	A	3	-	11	-	-

I/O or Buried	11	A	100	44	10	9	6

I/O or Buried	12	A	99	-	9	8	-

I/O or Buried	13	A	98	-	8	7	-

I/O or Buried	14	A	96	43	6	5	5

I/O or Buried	15	A	95	-	5	-	-

I/O or Buried	16	A	94	42	4	4	4

I/O or Buried	17	B	39	15	41	33	21

I/O or Buried	18	B	38	-	40	-	-

I/O or Buried	19	B	37	14	39	32	20

I/O or Buried	20	B	35	13	37	30	19

I/O or Buried	21	B	34	12	36	29	18

QFP	QFP	J-Lead	J-Lead	J-Lead

Function	LCell	LAB	(100-pin)	(44-pin)	(84-pin)	(68-pin)	(44-pin)

I/O or Buried	22	B	33	-	35	28	-

I/O or Buried	23	B	32	-	34	-	-

I/O or Buried	24	B	31	11	33	27	17

I/O or Buried	25	B	27	10	31	25	16

I/O or Buried	26	B	25	-	30	-	-

I/O or Buried	27	B	23	-	29	24	-

I/O or Buried	28	B	22	-	28	23	-

I/O or Buried	29	B	21	-	27	22	-

I/O or Buried	30	B	19	8	25	20	14

I/O or Buried	31	B	18	-	24	-	-

I/O or Buried	32	B	17	7	23	19	13

I/O or Buried	33	C	42	18	44	36	24

I/O or Buried	34	C	43	-	45	-	-

I/O or Buried	35	C	44	19	46	37	25

I/O or Buried	36	C	46	20	48	39	26

I/O or Buried	37	C	47	21	49	40	27

I/O or Buried	38	C	48	-	50	41	-

I/O or Buried	39	C	49	-	51	-	-

I/O or Buried	40	C	50	22	52	42	28

I/O or Buried	41	C	54	23	54	44	29

I/O or Buried	42	C	56	-	55	-	-

I/O or Buried	43	C	58	-	56	45	-

I/O or Buried	44	C	59	-	57	46	-

I/O or Buried	45	C	60	-	58	47	-

I/O or Buried	46	C	62	25	60	49	31

QFP	QFP	J-Lead	J-Lead	J-Lead

Function	LCell	LAB	(100-pin)	(44-pin)	(84-pin)	(68-pin)	(44-pin)

I/O or Buried	47	C	63	-	61	-	-

I/O or Buried	48	C	64	26	62	50	32

I/O or Buried	49	D	65	27	63	51	33

I/O or Buried	50	D	66	-	64	-	-

I/O or Buried	51	D	67	28	65	52	34

I/O or Buried	52	D	69	30	67	54	36

I/O or Buried	53	D	70	31	68	55	37

I/O or Buried	54	D	71	-	69	56	-

I/O or Buried	55	D	73	-	70	-	-

I/O or Buried	56	D	75	32	71	57	38

I/O or Buried	57	D	77	33	73	59	39

I/O or Buried	58	D	78	-	74	-	-

I/O or Buried	59	D	81	-	75	60	-

I/O or Buried	60	D	82	-	76	61	-

I/O or Buried	61	D	83	-	77	62	-

I/O or Buried	62	D	85	34	79	64	40

I/O or Buried	63	D	86	-	80	-	-

I/O or Buried	64	D	87	35	81	65	41

VCC	-	-	5	9	3	3	3

VCC	-	-	20	17	13	11	15

VCC	-	-	36	29	26	21	23

VCC	-	-	41	41	38	31	35

VCC	-	-	53	-	43	35	-

VCC	-	-	68	-	53	43	-

VCC	-	-	84	-	66	53	-

QFP	QFP	J-Lead	J-Lead	J-Lead

Function	LCell	LAB	(100-pin)	(44-pin)	(84-pin)	(68-pin)	(44-pin)

VCC	-	-	93	-	78	63	-

GND	-	-	13	4	7	6	10

GND	-	-	28	16	19	16	22

GND	-	-	40	24	32	26	30

GND	-	-	45	36	42	34	42

GND	-	-	61	-	47	38	-

GND	-	-	76	-	59	48	-

GND	-	-	88	-	72	58	-

GND	-	-	97	-	82	66	-

N.C.	-	-	1	-	-	-	-

N.C.	-	-	2	-	-	-	-

N.C.	-	-	7	-	-	-	-

N.C.	-	-	9	-	-	-	-

N.C.	-	-	24	-	-	-	-

N.C.	-	-	26	-	-	-	-

N.C.	-	-	29	-	-	-	-

N.C.	-	-	30	-	-	-	-

N.C.	-	-	51	-	-	-	-

N.C.	-	-	52	-	-	-	-

N.C.	-	-	55	-	-	-	-

N.C.	-	-	57	-	-	-	-

N.C.	-	-	72	-	-	-	-

N.C.	-	-	74	-	-	-	-

N.C.	-	-	79	-	-	-	-

N.C.	-	-	80	-	-	-	-


EPM7096 EPLDs

The high-density EPM7096 EPLD, a member of the MAX 7000 family, is based on second-generation MAX architecture and has 1,800 usable gates. The EPM7096 EPLD can accommodate up to 76 inputs or 72 outputs, and has 96 logic cells divided into 6 LABs. Configurable expander product-term distribution allows up to 32 product terms per logic cell. The EPM7096 is available in 68-pin J-lead packages with 48 I/O pins, 84-pin J-lead packages with 60 I/O pins, and 100-pin QFP packages with 72 I/O pins. For complete information on EPM7096 EPLDs, refer to the current MAX 7000 Programmable Logic Device Family Data Sheet.

See also:

MAX 7000 EPLD Selection Guide

Recommended reading:

AN26 (EPLD/MPLD Design Guidelines)

AN31 (Fitting Designs in MAX 7000 EPLDs)

AN42 (Metastability in Altera Devices)

AB9 (Asynchronous Latches in Classic, MAX & STG EPLDs)

AB60 (Estimating a Design Fit)

AB87 (Troubleshooting Functional Problems in EPLDs)

AB89 (Minimizing Output Switching Noise in Altera EPLDs)

AB91 (External Clock Sources for Altera EPLDs)

AB94 (Solutions to Design Timing Problems for Altera EPLDs)

AB100 (Understanding Classic, MAX 5000 & MAX 7000 Timing)

Altera Device Package Outlines Data Sheet

Operating Requirements for Altera Devices Data Sheet

J-Lead	J-Lead

Function	LCell	LAB	QFP	(84-pin)	(68-pin)

Input/GCLK	-	-	89	83	67

Input/GCLRn	-	-	91	1	1

Input/OE1n	-	-	90	84	68

Input/OE2n	-	-	92	2	2

I/O or Buried	1	A	8	16	13

I/O or Buried	2	A	-	-	-

I/O or Buried	3	A	7	15	-

I/O or Buried	4	A	6	14	12

I/O or Buried	5	A	4	-	-

I/O or Buried	6	A	3	12	10

I/O or Buried	7	A	-	-	-

I/O or Buried	8	A	2	11	9

I/O or Buried	9	A	1	10	8

I/O or Buried	10	A	-	-	-

I/O or Buried	11	A	100	9	-

I/O or Buried	12	A	99	8	7

I/O or Buried	13	A	98	-	-

I/O or Buried	14	A	95	5	5

I/O or Buried	15	A	-	-	-

I/O or Buried	16	A	94	4	4

I/O or Buried	17	B	23	28	23

I/O or Buried	18	B	-	-	-

I/O or Buried	19	B	22	27	22

I/O or Buried	20	B	21	-	-

J-Lead	J-Lead

Function	LCell	LAB	QFP	(84-pin)	(68-pin)

I/O or Buried	21	B	19	25	20

I/O or Buried	22	B	18	24	-

I/O or Buried	23	B	-	-	-

I/O or Buried	24	B	17	23	19

I/O or Buried	25	B	16	22	18

I/O or Buried	26	B	-	-	-

I/O or Buried	27	B	15	21	17

I/O or Buried	28	B	14	20	-

I/O or Buried	29	B	12	18	15

I/O or Buried	30	B	11	-	-

I/O or Buried	31	B	-	-	-

I/O or Buried	32	B	10	17	14

I/O or Buried	33	C	39	41	33

I/O or Buried	34	C	-	-	-

I/O or Buried	35	C	38	40	32

I/O or Buried	36	C	35	-	-

I/O or Buried	37	C	34	37	30

I/O or Buried	38	C	33	36	-

I/O or Buried	39	C	-	-	-

I/O or Buried	40	C	32	35	29

I/O or Buried	41	C	31	34	28

I/O or Buried	42	C	-	-	-

I/O or Buried	43	C	30	33	27

I/O or Buried	44	C	29	-	-

I/O or Buried	45	C	27	31	25

J-Lead	J-Lead

Function	LCell	LAB	QFP	(84-pin)	(68-pin)

I/O or Buried	46	C	26	30	-

I/O or Buried	47	C	-	-	-

I/O or Buried	48	C	25	29	24

I/O or Buried	49	D	42	44	36

I/O or Buried	50	D	-	-	-

I/O or Buried	51	D	43	45	37

I/O or Buried	52	D	46	-	-

I/O or Buried	53	D	47	48	39

I/O or Buried	54	D	48	49	-

I/O or Buried	55	D	-	-	-

I/O or Buried	56	D	49	50	40

I/O or Buried	57	D	50	51	41

I/O or Buried	58	D	-	-	-

I/O or Buried	59	D	51	52	42

I/O or Buried	60	D	52	-	-

I/O or Buried	61	D	54	54	44

I/O or Buried	62	D	55	55	-

I/O or Buried	63	D	-	-	-

I/O or Buried	64	D	56	56	45

I/O or Buried	65	E	58	57	46

I/O or Buried	66	E	-	-	-

I/O or Buried	67	E	59	58	47

I/O or Buried	68	E	60	-	-

I/O or Buried	69	E	62	60	49

I/O or Buried	70	E	63	61	-

J-Lead	J-Lead

Function	LCell	LAB	QFP	(84-pin)	(68-pin)

I/O or Buried	71	E	-	-	-

I/O or Buried	72	E	64	62	50

I/O or Buried	73	E	65	63	51

I/O or Buried	74	E	-	-	-

I/O or Buried	75	E	66	64	52

I/O or Buried	76	E	67	65	-

I/O or Buried	77	E	69	67	54

I/O or Buried	78	E	70	-	-

I/O or Buried	79	E	-	-	-

I/O or Buried	80	E	71	68	55

I/O or Buried	81	F	73	69	56

I/O or Buried	82	F	-	-	-

I/O or Buried	83	F	74	70	-

I/O or Buried	84	F	75	71	57

I/O or Buried	85	F	77	-	-

I/O or Buried	86	F	78	73	59

I/O or Buried	87	F	-	-	-

I/O or Buried	88	F	79	74	60

I/O or Buried	89	F	80	75	61

I/O or Buried	90	F	-	-	-

I/O or Buried	91	F	81	76	-

I/O or Buried	92	F	82	77	62

I/O or Buried	93	F	83	-	-

I/O or Buried	94	F	86	80	64

I/O or Buried	95	F	-	-	-

J-Lead	J-Lead

Function	LCell	LAB	QFP	(84-pin)	(68-pin)

I/O or Buried	96	F	87	81	65

VCC	-	-	5	3	3

VCC	-	-	20	13	11

VCC	-	-	36	26	21

VCC	-	-	41	38	31

VCC	-	-	53	43	35

VCC	-	-	68	53	43

VCC	-	-	84	66	53

VCC	-	-	93	78	63

GND	-	-	13	7	6

GND	-	-	28	19	16

GND	-	-	40	32	26

GND	-	-	45	42	34

GND	-	-	61	47	38

GND	-	-	76	59	48

GND	-	-	88	72	58

GND	-	-	97	82	66

N.C.	-	-	9	6	-

N.C.	-	-	24	39	-

N.C.	-	-	37	46	-

N.C.	-	-	44	79	-

N.C.	-	-	57	-	-

N.C.	-	-	72	-	-

N.C.	-	-	85	-	-

N.C.	-	-	96	-	-


EPM7128E EPLDs

The high-density EPM7128E EPLD, a member of the MAX 7000 family, is based on second-generation MAX architecture and has 2,500 usable gates. The EPM7128E can accommodate up to 100 inputs or 96 outputs, and has 128 logic cells divided into 8 LABs. Configurable expander product-term distribution allows up to 32 product terms per logic cell. The EPM7128E is available in 84-pin J-lead and 100- and 160-pin QFP packages. For complete information on EPM7128E EPLDs, refer to the current MAX 7000 Programmable Logic Device Family Data Sheet.

See also:

MAX 7000 EPLD Selection Guide

Recommended reading:

AN26 (EPLD/MPLD Design Guidelines)

AN31 (Fitting Designs in MAX 7000 EPLDs)

AN42 (Metastability in Altera Devices)

AB9 (Asynchronous Latches in Classic, MAX & STG EPLDs)

AB60 (Estimating a Design Fit)

AB87 (Troubleshooting Functional Problems in EPLDs)

AB89 (Minimizing Output Switching Noise in Altera EPLDs)

AB91 (External Clock Sources for Altera EPLDs)

AB94 (Solutions to Design Timing Problems for Altera EPLDs)

AB100 (Understanding Classic, MAX 5000 & MAX 7000 Timing)

Altera Device Package Outlines Data Sheet

Operating Requirements for Altera Devices Data Sheet

OE MUX	QFP	QFP

Function	LCell	Pin;LCell(2)	LAB	(160-pin)	(100-pin)	J-Lead

Input/GCLK1	-	-;-	-	139	89	83

Input/GCLRn	-	-;-	-	141	91	1

Input/OE1	-	1;-	-	140	90	84

Input/OE2/GCLK2	-	2;-	-	142	92	2

I/O or Buried	1	-;-	A	160	4	-

I/O or Buried	2	-;-	A	-	-	-

I/O or Buried	3	-;3	A	159	3	12

I/O or Buried	4	-;-	A	158	-	-

I/O or Buried	5	-;4	A	153	2	11

I/O or Buried	6	-;-	A	152	1	10

I/O or Buried	7	-;-	A	-	-	-

I/O or Buried	8	6;5	A	151	100	9

I/O or Buried	9	-;-	A	150	99	-

I/O or Buried	10	-;-	A	-	-	-

I/O or Buried	11	3;1	A	149	98	8

I/O or Buried	12	-;-	A	147	-	-

I/O or Buried	13	5;-	A	146	96	6

I/O or Buried	14	-;-	A	145	95	5

I/O or Buried	15	-;-	A	-	-	-

I/O or Buried	16	4;6	A	144	94	4

I/O or Buried	17	-;-	B	21	16	22

I/O or Buried	18	-;-	B	-	-	-

I/O or Buried	19	-;5	B	20	15	21

I/O or Buried	20	-;-	B	19	-	-

I/O or Buried	21	-;2	B	18	14	20

OE MUX	QFP	QFP

Function	LCell	Pin;LCell(2)	LAB	(160-pin)	(100-pin)	J-Lead

I/O or Buried	22	-;-	B	16	12	-

I/O or Buried	23	-;-	B	-	-	-

I/O or Buried	24	1;3	B	15	11	18

I/O or Buried	25	-;-	B	14	10	17

I/O or Buried	26	-;-	B	-	-	-

I/O or Buried	27	5;6	B	13	9	16

I/O or Buried	28	-;-	B	12	-	-

I/O or Buried	29	3;-	B	11	8	15

I/O or Buried	30	-;-	B	10	7	-

I/O or Buried	31	-;-	B	-	-	-

I/O or Buried	32	2;1	B	9	6	14

I/O or Buried	33	-;-	C	41	27	-

I/O or Buried	34	-;-	C	-	-	-

I/O or Buried	35	-;3	C	33	26	31

I/O or Buried	36	-;-	C	32	-	-

I/O or Buried	37	-;4	C	31	25	30

I/O or Buried	38	-;-	C	30	24	29

I/O or Buried	39	-;-	C	-	-	-

I/O or Buried	40	6;5	C	29	23	28

I/O or Buried	41	-;-	C	28	22	-

I/O or Buried	42	-;-	C	-	-	-

I/O or Buried	43	-;1	C	27	21	27

I/O or Buried	44	-;-	C	25	-	-

I/O or Buried	45	5;-	C	24	19	25

I/O or Buried	46	-;-	C	23	18	24

OE MUX	QFP	QFP

Function	LCell	Pin;LCell(2)	LAB	(160-pin)	(100-pin)	J-Lead

I/O or Buried	47	-;-	C	-	-	-

I/O or Buried	48	4;6	C	22	17	23

I/O or Buried	49	-;-	D	59	39	41

I/O or Buried	50	-;-	D	-	-	-

I/O or Buried	51	-;5	D	58	38	40

I/O or Buried	52	-;-	D	57	--

I/O or Buried	53	-;2	D	56	37	39

I/O or Buried	54	-;-	D	54	35	-

I/O or Buried	55	-;-	D	-	-	-

I/O or Buried	56	1;3	D	53	34	37

I/O or Buried	57	-;-	D	52	33	36

I/O or Buried	58	-;-	D	-	-	-

I/O or Buried	59	4;6	D	51	32	35

I/O or Buried	60	-;-	D	50	-	-

I/O or Buried	61	3;-	D	49	31	34

I/O or Buried	62	-;-	D	48	30	-

I/O or Buried	63	-;-	D	-	-	-

I/O or Buried	64	2;1	D	43	29	33

I/O or Buried	65	-;-	E	62	42	44

I/O or Buried	66	-;-	E	-	-	-

I/O or Buried	67	-;4	E	63	43	45

I/O or Buried	68	-;-	E	64	-	-

I/O or Buried	69	-;2	E	65	44	46

I/O or Buried	70	-;-	E	67	46	-

I/O or Buried	71	-;-	E	-	-	-

OE MUX	QFP	QFP

Function	LCell	Pin;LCell(2)	LAB	(160-pin)	(100-pin)	J-Lead

I/O or Buried	72	1;3	E	68	47	48

I/O or Buried	73	-;-	E	69	48	49

I/O or Buried	74	-;-	E	-	-	-

I/O or Buried	75	-;6	E	70	49	50

I/O or Buried	76	-;-	E	71	-	-

I/O or Buried	77	3;-	E	72	50	51

I/O or Buried	78	-;-	E	73	51	-

I/O or Buried	79	-;-	E	-	-	-

I/O or Buried	80	2;1	E	78	52	52

I/O or Buried	81	-;-	F	80	54	-

I/O or Buried	82	-;-	F	-	-	-

I/O or Buried	83	-;3	F	88	55	54

I/O or Buried	84	-;-	F	89	-	-

I/O or Buried	85	-;4	F	90	56	55

I/O or Buried	86	-;-	F	91	57	56

I/O or Buried	87	-;-	F	-	-	-

I/O or Buried	88	6;5	F	92	58	57

I/O or Buried	89	-;-	F	93	59	-

I/O or Buried	90	-;-	F	-	-	-

I/O or Buried	91	-;1	F	94	60	58

I/O or Buried	92	-;-	F	96	-	-

I/O or Buried	93	5;-	F	97	62	60

I/O or Buried	94	-;-	F	98	63	61

I/O or Buried	95	-;-	F	-	-	-

I/O or Buried	96	4;6	F	99	64	62

OE MUX	QFP	QFP

Function	LCell	Pin;LCell(2)	LAB	(160-pin)	(100-pin)	J-Lead

I/O or Buried	97	-;-	G	100	65	63

I/O or Buried	98	-;-	G	-	-	-

I/O or Buried	99	6;5	G	101	66	64

I/O or Buried	100	-;-	G	102	-	-

I/O or Buried	101	-;2	G	103	67	65

I/O or Buried	102	-;-	G	105	69	-

I/O or Buried	103	-;-	G	-	-	-

I/O or Buried	104	1;3	G	106	70	67

I/O or Buried	105	-;-	G	107	71	68

I/O or Buried	106	-;-	G	-	-	-

I/O or Buried	107	-;6	G	108	72	69

I/O or Buried	108	-;-	G	109	-	-

I/O or Buried	109	3;-	G	110	73	70

I/O or Buried	110	-;-	G	111	74	-

I/O or Buried	111	-;-	G	-	-	-

I/O or Buried	112	2;1	G	112	75	71

I/O or Buried	113	-;-	H	121	77	-

I/O or Buried	114	-;-	H	-	-	-

I/O or Buried	115	-;3	H	122	78	73

I/O or Buried	116	-;-	H	123	-	-

I/O or Buried	117	-;4	H	128	79	74

I/O or Buried	118	-;-	H	129	80	75

I/O or Buried	119	-;-	H	-	-	-

I/O or Buried	120	6;4	H	130	81	76

I/O or Buried	121	-;-	H	131	82	-

OE MUX	QFP	QFP

Function	LCell	Pin;LCell(2)	LAB	(160-pin)	(100-pin)	J-Lead

I/O or Buried	122	-;-	H	-	-	-

I/O or Buried	123	-;1	H	132	83	77

I/O or Buried	124	-;-	H	134	-	-

I/O or Buried	125	5;-	H	135	85	79

I/O or Buried	126	-;-	H	136	86	80

I/O or Buried	127	-;-	H	-	-	-

I/O or Buried	128	4;6	H	137	87	81

VCC	-	-	-;-	-	8	5	3

VCC	-	-	-;-	-	26	20	13

VCC	-	-	-;-	-	55	36	26

VCC	-	-	-;-	-	61	41	38

VCC	-	-	-;-	-	79	53	43

VCC	-	-	-;-	-	104	68	53

VCC	-	-	-;-	-	133	84	66

VCC	-	-	-;-	-	143	93	78

GND	-	-	-;-	-	17	13	7

GND	-	-	-;-	-	42	28	19

GND	-	-	-;-	-	60	40	32

GND	-	-	-;-	-	66	45	42

GND	-	-	-;-	-	95	61	47

GND	-	-	-;-	-	113	76	59

GND	-	-	-;-	-	138	88	72

GND	-	-	-;-	-	148	97	82

N.C.	-	-	-;-	-	1	-	-

N.C.	-	-	-;-	-	2	-	-

OE MUX	QFP	QFP

Function	LCell	Pin;LCell(2)	LAB	(160-pin)	(100-pin)	J-Lead

N.C.	-	-	-;-	-	3	-	-

N.C.	-	-	-;-	-	4	-	-

N.C.	-	-;-	-	5	-	-

N.C.	-	-	-;-	-	6	-	-

N.C.	-	-	-;-	-	7	-	-

N.C.	-	-	-;-	-	34	-	-

N.C.	-	-	-;-	-	35	-	-

N.C.	-	-	-;-	-	36	-	-

N.C.	-	-	-;-	-	37	-	-

N.C.	-	-	-;-	-	38	-	-

N.C.	-	-	-;-	-	39	-	-

N.C.	-	-	-;-	-	40	-	-

N.C.	-	-	-;-	-	44	-	-

N.C.	-	-	-;-	-	45	-	-

N.C.	-	-	-;-	-	46	-	-

N.C.	-	-	-;-	-	47	-	-

N.C.	-	-	-;-	-	74	-	-

N.C.	-	-	-;-	-	75	-	-

N.C.	-	-	-;-	-	76	-	-

N.C.	-	-	-;-	-	77	-	-

N.C.	-	-	-;-	-	81	-	-

N.C.	-	-	-;-	-	82	-	-

N.C.	-	-	-;-	-	83	-	-

N.C.	-	-	-;-	-	84	-	-

N.C.	-	-	-;-	-	85	-	-

OE MUX	QFP	QFP

Function	LCell	Pin;LCell(2)	LAB	(160-pin)	(100-pin)	J-Lead

N.C.	-	-	-;-	-	86	-	-

N.C.	-	-	-;-	-	87	-	-

N.C.	-	-	-;-	-	114	-	-

N.C.	-	-	-;-	-	115	-	-

N.C.	-	-	-;-	-	116	-	-

N.C.	-	-	-;-	-	117	-	-

N.C.	-	-	-;-	-	118	-	-

N.C.	-	-	-;-	-	119	-	-

N.C	-	-	-;-	-	120	-	-

N.C.	-	-	-;-	-	124	-	-

N.C.	-	-	-;-	-	125	-	-

N.C.	-	-	-;-	-	126	-	-

N.C.	-	-	-;-	-	127	-	-

N.C.	-	-	-;-	-	154	-	-

N.C.	-	-	-;-	-	155	-	-

N.C.	-	-	-;-	-	156	-	-

N.C.	-	-	-;-	-	157	-	-


EPM7160E EPLDs

The high-density EPM7160E EPLD, a member of the MAX 7000 family, is based on second-generation MAX architecture and has 3,200 usable gates. The EPM7160E can accommodate up to 104 inputs or 100 outputs, and has 160 logic cells divided into 10 LABs. Configurable expander product-term distribution allows up to 32 product terms per logic cell. The EPM7160E is available in reprogrammable 84-pin J-lead, and 100- and 160-pin QFP packages. For complete information on EPM7160E EPLDs, refer to the current MAX 7000 Programmable Logic Device Family Data Sheet.

See also:

MAX 7000 EPLD Selection Guide

Recommended reading:

AN26 (EPLD/MPLD Design Guidelines)

AN31 (Fitting Designs in MAX 7000 EPLDs)

AN42 (Metastability in Altera Devices)

AB9 (Asynchronous Latches in Classic, MAX & STG EPLDs)

AB60 (Estimating a Design Fit)

AB87 (Troubleshooting Functional Problems in EPLDs)

AB89 (Minimizing Output Switching Noise in Altera EPLDs)

AB91 (External Clock Sources for Altera EPLDs)

AB94 (Solutions to Design Timing Problems for Altera EPLDs)

AB100 (Understanding Classic, MAX 5000 & MAX 7000 Timing)

Altera Device Package Outlines Data Sheet

Operating Requirements for Altera Devices Data Sheet

OE MUX

Function	LCell	Pin;LCell(2)	LAB	QFP (160-pin)	QFP (100-pin)	J-Lead

Input/GCLK1	-	-;-	-	139	89	83

Input/GCLRn	-	-;-	-	141	91	1

Input/OE1	-	1;-	-	140	90	84

Input/OE2/GCLK2 (1)	-	1;-	-	142	92	2

I/O or Buried	1	-;2	A	158	2	11

I/O or Buried	2	-;-	A	-	-	-

I/O or Buried	3	-;3	A	153	1	10

I/O or Buried	4	-;-	A	-	-	-

I/O or Buried	5	-;-	A	152	-	-

I/O or Buried	6	-;-	A	151	100	-

I/O or Buried	7	-;-	A	-	-	-

I/O or Buried	8	6;5	A	150	99	9

I/O or Buried	9	-;-	A	149	98	8

I/O or Buried	10	-;-	A	-	-	-

I/O or Buried	11	-;1	A	147	96	5

I/O or Buried	12	-;-	A	-	-	-

I/O or Buried	13	-;-	A	146	-	-

I/O or Buried	14	-;-	A	145	95	-

I/O or Buried	15	-;-	A	-	-	-

I/O or Buried	16	5;6	A	144	94	4

I/O or Buried	17	-;4	B	15	11	18

I/O or Buried	18	-;-	B	-	-	-

I/O or Buried	19	-;5	B	14	10	17

I/O or Buried	20	-;-	B	-	-	-

I/O or Buried	21	-;-	B	13	-	-

OE MUX

Function	LCell	Pin;LCell(2)	LAB	QFP (160-pin)	QFP (100-pin)	J-Lead

I/O or Buried	22	-;-	B	12	9	-

I/O or Buried	23	-;-	B	-	-	-

I/O or Buried	24	-;3	B	11	8	16

I/O or Buried	25	-;-	B	10	7	15

I/O or Buried	26	-;-	B	-	-	-

I/O or Buried	27	4;6	B	9	6	14

I/O or Buried	28	-;-	B	-	-	-

I/O or Buried	29	-;-	B	7	-	-

I/O or Buried	30	-;-	B	160	4	-

I/O or Buried	31	-;-	B	-	-	-

I/O or Buried	32	3;1	B	159	3	12

I/O or Buried	33	-;-	C	27	21	-

I/O or Buried	34	-;-	C	-	-	-

I/O or Buried	35	-;3	C	25	19	25

I/O or Buried	36	-;-	C	-	-	-

I/O or Buried	37	-;-	C	24	-	-

I/O or Buried	38	-;4	C	23	18	24

I/O or Buried	39	-;-	C	-	-	-

I/O or Buried	40	6;5	C	22	17	23

I/O or Buried	41	-;-	C	16	12	-

I/O or Buried	42	-;-	C	-	-	-

I/O or Buried	43	2;1	C	18	14	20

I/O or Buried	44	-;-	C	-	-	-

I/O or Buried	45	-;-	C	19	-	-

I/O or Buried	46	-;-	C	20	15	21

OE MUX

Function	LCell	Pin;LCell(2)	LAB	QFP (160-pin)	QFP (100-pin)	J-Lead

I/O or Buried	47	-;-	C	-	-	-

I/O or Buried	48	5;6	C	21	16	22

I/O or Buried	49	-;-	D	48	-	-

I/O or Buried	50	-;-	D	-	-	-

I/O or Buried	51	-;5	D	44	30	33

I/O or Buried	52	-;-	D	-	-	-

I/O or Buried	53	-;-	D	43	29	-

I/O or Buried	54	-;2	D	41	27	31

I/O or Buried	55	-;-	D	-	-	-

I/O or Buried	56	1;3	D	33	26	30

I/O or Buried	57	-;-	D	32	-	-

I/O or Buried	58	-;-	D	-	-	-

I/O or Buried	59	4;6	D	31	25	29

I/O or Buried	60	-;-	D	-	-	-

I/O or Buried	61	-;-	D	30	24	-

I/O or Buried	62	-;-	D	29	23	28

I/O or Buried	63	-;-	D	-	-	-

I/O or Buried	64	3;1	D	28	22	27

I/O or Buried	65	-;-	E	59	-	-

I/O or Buried	66	-;-	E	-	-	-

I/O or Buried	67	-;3	E	58	39	41

I/O or Buried	68	-;-	E	-	-

I/O or Buried	69	-;-	E	57	38	-

I/O or Buried	70	-;4	E	56	37	40

I/O or Buried	71	-;-	E	-	-	-

OE MUX

Function	LCell	Pin;LCell(2)	LAB	QFP (160-pin)	QFP (100-pin)	J-Lead

I/O or Buried	72	6;5	E	54	35	37

I/O or Buried	73	-;-	E	53	-	-

I/O or Buried	74	-;-	E	-	-	-

I/O or Buried	75	2;1	E	52	34	36

I/O or Buried	76	-;-	E	-	-	-

I/O or Buried	77	-;-	E	51	33	-

I/O or Buried	78	-;-	E	50	32	35

I/O or Buried	79	-;-	E	-	-	-

I/O or Buried	80	5;6	E	49	31	34

I/O or Buried	81	-;-	F	62	-	-

I/O or Buried	82	-;-	F	-	-	-

I/O or Buried	83	-;3	F	63	42	44

I/O or Buried	84	-;-	F	-	-	-

I/O or Buried	85	-;-	F	64	43	-

I/O or Buried	86	-;4	F	65	44	45

I/O or Buried	87	-;-	F	-	-	-

I/O or Buried	88	1;5	F	67	46	48

I/O or Buried	89	-;-	F	68	-	-

I/O or Buried	90	-;-	F	-	-	-

I/O or Buried	91	4;1	F	69	47	49

I/O or Buried	92	-;-	F	-	-	-

I/O or Buried	93	-;-	F	70	48	-

I/O or Buried	94	-;-	F	71	49	50

I/O or Buried	95	-;-	F	-	-	-

I/O or Buried	96	3;6	F	72	50	51

OE MUX

Function	LCell	Pin;LCell(2)	LAB	QFP (160-pin)	QFP (100-pin)	J-Lead

I/O or Buried	97	-;-	G	73	-	-

I/O or Buried	98	-;-	G	-	-	-

I/O or Buried	99	-;5	G	77	51	52

I/O or Buried	100	-;-	G	-	-	-

I/O or Buried	101	-;-	G	78	52	-

I/O or Buried	102	-;2	G	80	54	54

I/O or Buried	103	-;-	G	-	-	-

I/O or Buried	104	1;3	G	88	55	55

I/O or Buried	105	-;-	G	89	-	-

I/O or Buried	106	-;-	G	-	-	-

I/O or Buried	107	4;6	G	90	56	56

I/O or Buried	108	-;-	G	-	-	-

I/O or Buried	109	-;-	G	91	57	-

I/O or Buried	110	-;-	G	92	58	57

I/O or Buried	111	-;-	G	-	-	-

I/O or Buried	112	3;1	G	93	59	58

I/O or Buried	113	-;-	H	94	60	-

I/O or Buried	114	-;-	H	-	-	-

I/O or Buried	115	-;3	H	96	62	60

I/O or Buried	116	-;-	H	-	-	-

I/O or Buried	117	-;-	H	97	-	-

I/O or Buried	118	-;4	H	98	63	61

I/O or Buried	119	-;-	H	-	-	-

I/O or Buried	120	6;5	H	99	64	62

I/O or Buried	121	-;-	H	105	69	-

OE MUX

Function	LCell	Pin;LCell(2)	LAB	QFP (160-pin)	QFP (100-pin)	J-Lead

I/O or Buried	122	-;-	H	-	-	-

I/O or Buried	123	2;1	H	103	67	65

I/O or Buried	124	-;-	H	-	-	-

I/O or Buried	125	-;-	H	102	-	-

I/O or Buried	126	-;-	H	101	66	64

I/O or Buried	127	-;-	H	-	-	-

I/O or Buried	128	5;6	H	100	65	63

I/O or Buried	129	-;4	I	106	70	67

I/O or Buried	130	-;-	I	-	-	-

I/O or Buried	131	-;5	I	107	71	68

I/O or Buried	132	-;-	I	-	-	-

I/O or Buried	133	-;-	I	108	-	-

I/O or Buried	134	-;-	I	109	72	-

I/O or Buried	135	-;-	I	-	-	-

I/O or Buried	136	1;3	I	110	73	69

I/O or Buried	137	-;-	I	111	74	70

I/O or Buried	138	-;-	I	-	-	-

I/O or Buried	139	4;6	I	112	75	71

I/O or Buried	140	-;-	I	-	-	-

I/O or Buried	141	-;-	I	114	-	-

I/O or Buried	142	-;-	I	121	77	-

I/O or Buried	143	-;-	I	-	-	-

I/O or Buried	144	3;1	I	122	78	73

I/O or Buried	145	-;2	J	123	79	74

I/O or Buried	146	-;-	J	-	-	-

OE MUX

Function	LCell	Pin;LCell(2)	LAB	QFP (160-pin)	QFP (100-pin)	J-Lead

I/O or Buried	147	-;3	J	128	80	75

I/O or Buried	148	-;-	J	-	-	-

I/O or Buried	149	-;-	J	129	-	-

I/O or Buried	150	-;-	J	130	81	-

I/O or Buried	151	-;-	J	-	-	-

I/O or Buried	152	6;5	J	131	82	76

I/O or Buried	153	-;-	J	132	83	77

I/O or Buried	154	-;-	J	-	-	-

I/O or Buried	155	2;1	J	134	85	80

I/O or Buried	156	-;-	J	-	-	-

I/O or Buried	157	-;-	J	135	-	-

I/O or Buried	158	-;-	J	136	86	-

I/O or Buried	159	-;-	J	-	-	-

I/O or Buried	160	5,6	J	137	87	81

VCC	-	-;-	-	8	5	3

VCC	-	-;-	-	26	20	13

VCC	-	-;-	-	55	36	26

VCC	-	-;-	-	61	41	38

VCC	-	-;-	-	79	53	43

VCC	-	-;-	-	104	68	53

VCC	-	-;-	-	133	84	66

VCC	-	-;-	-	143	93	78

GND	-	-;-	-	17	13	7

GND	-	-;-	-	42	28	19

GND	-	-;-	-	60	40	32

OE MUX

Function	LCell	Pin;LCell(2)	LAB	QFP (160-pin)	QFP (100-pin)	J-Lead

GND	-	-;-	-	66	45	42

GND	-	-;-	-	95	61	47

GND	-	-;-	-	113	76	59

GND	-	-;-	-	138	88	72

GND	-	-;-	-	148	97	82

N.C.	-	-;-	-	1	-	6

N.C.	-	-;-	-	2	-	39

N.C.	-	-;-	-	3	-	46

N.C.	-	-;-	-	4	-	79

N.C.	-	-;-	-	5	-	-

N.C.	-	-;-	-	6	-	-

N.C.	-	-;-	-	34	-	-

N.C.	-	-;-	-	35	-	-

N.C.	-	-;-	-	36	-	-

N.C.	-	-;-	-	37	-	-

N.C.	-	-;-	-	38	-	-

N.C.	-	-;-	-	39	-	-

N.C.	-	-;-	-	40	-	-

N.C.	-	-;-	-	45	-	-

N.C.	-	-;-	-	46	-	-

N.C.	-	-;-	-	47	-	-

N.C.	-	-;-	-	74	-	-

N.C.	-	-;-	-	75	-	-

N.C.	-	-;-	-	76	-	-

N.C.	-	-;-	-	81	-	-

OE MUX

Function	LCell	Pin;LCell(2)	LAB	QFP (160-pin)	QFP (100-pin)	J-Lead

N.C.	-	-;-	-	82	-	-

N.C.	-	-;-	-	83	-	-

N.C.	-	-;-	-	84	-	-

N.C.	-	-;-	-	85	-	-

N.C.	-	-;-	-	86	-	-

N.C.	-	-;-	-	87	-	-

N.C.	-	-;-	-	115	-	-

N.C.	-	-;-	-	116	-	-

N.C.	-	-;-	-	117	-	-

N.C.	-	-;-	-	118	-	-

N.C.	-	-;-	-	119	-	-

N.C.	-	-;-	-	120	-	-

N.C.	-	-;-	-	124	-	-

N.C.	-	-;-	-	125	-	-

N.C.	-	-;-	-	126	-	-

N.C.	-	-;-	-	127	-	-

N.C.	-	-;-	-	154	-	-

N.C.	-	-;-	-	155	-	-

N.C.	-	-;-	-	156	-	-

N.C.	-	-;-	-	157	-	-


EPM7192E EPLDs

The high-density EPM7192E EPLD, a member of the MAX 7000 family, is based on second-generation MAX architecture and has 3,750 usable gates. The EPM7192E can accommodate up to 124 inputs or 120 outputs, and has 192 logic cells divided into 12 LABs. Configurable expander product-term distribution allows up to 32 product terms per logic cell. The EPM7192E is available in reprogrammable plastic 160-pin QFP and PGA packages. For complete information on EPM7192E EPLDs, refer to the current MAX 7000 Programmable Logic Device Family Data Sheet.

See also:

MAX 7000 EPLD Selection Guide

Recommended reading:

AN26 (EPLD/MPLD Design Guidelines)

AN31 (Fitting Designs in MAX 7000 EPLDs)

AN42 (Metastability in Altera Devices)

AB9 (Asynchronous Latches in Classic, MAX & STG EPLDs)

AB60 (Estimating a Design Fit)

AB87 (Troubleshooting Functional Problems in EPLDs)

AB89 (Minimizing Output Switching Noise in Altera EPLDs)

AB91 (External Clock Sources for Altera EPLDs)

AB94 (Solutions to Design Timing Problems for Altera EPLDs)

AB100 (Understanding Classic, MAX 5000 & MAX 7000 Timing)

Altera Device Package Outlines Data Sheet

Operating Requirements for Altera Devices Data Sheet

OE MUX

Function	LCell	Pin;LCell(2)	LAB	QFP	PGA

Input/GCLK1	-	-;-	-	139	M8

Input/GCLRn	-	-;-	-	141	N8

Input/OE1	-	1;-	-	140	P8

Input/OE2/GCLK2 (1)	-	1;-	-	142	R8

I/O or Buried	1	-;3	A	156	M12

I/O or Buried	2	-;-	A	-	-

I/O or Buried	3	-;2	A	154	P11

I/O or Buried	4	-;-	A	-	-

I/O or Buried	5	-;4	A	153	P12

I/O or Buried	6	-;5	A	152	P10

I/O or Buried	7	-;-	A	-	-

I/O or Buried	8	6;-	A	151	R12

I/O or Buried	9	3;-	A	150	N10

I/O or Buried	10	-;-	A	-	-

I/O or Buried	11	-;1	A	149	R11

I/O or Buried	12	-;-	A	-	-

I/O or Buried	13	-;-	A	147	R10

I/O or Buried	14	-;-	A	146	P9

I/O or Buried	15	-;-	A	-	-

I/O or Buried	16	4;6	A	145	R9

I/O or Buried	17	-;5	B	8	L14

I/O or Buried	18	-;-	B	-	-

I/O or Buried	19	-;2	B	7	M14

I/O or Buried	20	-;-	B	-	-

OE MUX

Function	LCell	Pin;LCell(2)	LAB	QFP	PGA

I/O or Buried	21	-;2	B	6	M15

I/O or Buried	22	-;3	B	5	N14

I/O or Buried	23	-;-	B	-	-

I/O or Buried	24	-;-	B	4	N15

I/O or Buried	25	5;-	B	2	P15

I/O or Buried	26	-;-	B	-	-

I/O or Buried	27	-;6	B	160	N13

I/O or Buried	28	-;-	B	-	-

I/O or Buried	29	-;-	B	159	P14

I/O or Buried	30	-;-	B	158	P13

I/O or Buried	31	-;-	B	-	-

I/O or Buried	32	2;1	B	157	R13

I/O or Buried	33	-;3	C	21	H14

I/O or Buried	34	-;-	C	-	-

I/O or Buried	35	-;2	C	20	J13

I/O or Buried	36	-;-	C	-	-

I/O or Buried	37	-;4	C	19	H15

I/O or Buried	38	-;5	C	17	J15

I/O or Buried	39	-;-	C	-	-

I/O or Buried	40	6;-	C	16	J14

I/O or Buried	41	3;-	C	15	K15

I/O or Buried	42	-;-	C	-	-

I/O or Buried	43	-;1	C	14	K13

I/O or Buried	44	-;-	C	-	-

I/O or Buried	45	-;-	C	13	L15

OE MUX

Function	LCell	Pin;LCell(2)	LAB	QFP	PGA

I/O or Buried	46	-;-	C	12	K14

I/O or Buried	47	-;-	C	-	-

I/O or Buried	48	4;6	C	9	L13

I/O or Buried	49	-;5	D	33	D15

I/O or Buried	50	-;-	D	-	-

I/O or Buried	51	-;4	D	31	E15

I/O or Buried	52	-;-	D	-	-

I/O or Buried	53	-;2	D	30	E14

I/O or Buried	54	-;3	D	29	F15

I/O or Buried	55	-;-	D	-	-

I/O or Buried	56	1;-	D	28	F13

I/O or Buried	57	5;-	D	27	G14

I/O or Buried	58	-;-	D	-	-

I/O or Buried	59	-;6	D	26	F14

I/O or Buried	60	-;-	D	-	-

I/O or Buried	61	-;-	D	24	G13

I/O or Buried	62	-;-	D	23	G15

I/O or Buried	63	-;-	D	-	-

I/O or Buried	64	2;1	D	22	H13

I/O or Buried	65	-;3	E	45	B12

I/O or Buried	66	-;-	E	-	-

I/O or Buried	67	-;2	E	44	B13

I/O or Buried	68	-;-	E	-	-

I/O or Buried	69	-;4	E	43	C13

I/O or Buried	70	-;5	E	42	B14

OE MUX

Function	LCell	Pin;LCell(2)	LAB	QFP	PGA

I/O or Buried	71	-;-	E	-	-

I/O or Buried	72	6;-	E	41	C14

I/O or Buried	73	3;-	E	38	D12

I/O or Buried	74	-;-	E	-	-

I/O or Buried	75	-;1	E	37	B15

I/O or Buried	76	-;-	E	-	-

I/O or Buried	77	-;-	E	36	D14

I/O or Buried	78	-;-	E	35	C15

I/O or Buried	79	-;-	E	-	-

I/O or Buried	80	4;6	E	34	E13

I/O or Buried	81	-;5	F	60	D8

I/O or Buried	82	-;-	F	-	-

I/O or Buried	83	-;4	F	59	A9

I/O or Buried	84	-;-	F	-	-

I/O or Buried	85	-;2	F	58	C8

I/O or Buried	86	-;3	F	53	B9

I/O or Buried	87	-;-	F	-	-

I/O or Buried	88	1;-	F	52	A10

I/O or Buried	89	5;-	F	51	B10

I/O or Buried	90	-;-	F	-	-

I/O or Buried	91	-;6	F	50	A11

I/O or Buried	92	-;-	F	-	-

I/O or Buried	93	-;-	F	49	B11

I/O or Buried	94	-;-	F	48	A12

I/O or Buried	95	-;-	F	-	-

OE MUX

Function	LCell	Pin;LCell(2)	LAB	QFP	PGA

I/O or Buried	96	2;0	F	46	A13

I/O or Buried	97	-;5	G	61	A8

I/O or Buried	98	-;-	G	-	-

I/O or Buried	99	-;4	G	62	B8

I/O or Buried	100	-;-	G	-	-

I/O or Buried	101	-;2	G	63	A7

I/O or Buried	102	-;3	G	68	A6

I/O or Buried	103	-;-	G	-	-

I/O or Buried	104	1;-	G	69	B7

I/O or Buried	105	5;-	G	70	A5

I/O or Buried	106	-;-	G	-	-

I/O or Buried	107	-;6	G	71	B6

I/O or Buried	108	-;-	G	-	-

I/O or Buried	109	-;-	G	72	A4

I/O or Buried	110	-;-	G	73	B5

I/O or Buried	111	-;-	G	-	-

I/O or Buried	112	2;0	G	75	D4

I/O or Buried	113	-;3	H	76	A3

I/O or Buried	114	-;-	H	-	-

I/O or Buried	115	-;2	H	77	B4

I/O or Buried	116	-;-	H	-	-

I/O or Buried	117	-;4	H	78	B3

I/O or Buried	118	-;5	H	79	C3

I/O or Buried	119	-;-	H	-	-

I/O or Buried	120	6;-	H	80	B2

OE MUX

Function	LCell	Pin;LCell(2)	LAB	QFP	PGA

I/O or Buried	121	3;-	H	83	B1

I/O or Buried	122	-;-	H	-	-

I/O or Buried	123	-;1	H	84	C2

I/O or Buried	124	-;-	H	-	-

I/O or Buried	125	-;-	H	85	C1

I/O or Buried	126	-;-	H	86	D2

I/O or Buried	127	-;-	H	-	-

I/O or Buried	128	4;6	H	87	D1

I/O or Buried	129	-;5	I	88	E3

I/O or Buried	130	-;-	I	-	-

I/O or Buried	131	-;4	I	90	F3

I/O or Buried	132	-;-	I	-	-

I/O or Buried	133	-;2	I	91	E2

I/O or Buried	134	-;3	I	92	F2

I/O or Buried	135	-;-	I	-	-

I/O or Buried	136	1;-	I	93	E1

I/O or Buried	137	5;-	I	94	G3

I/O or Buried	138	-;-	I	-	-

I/O or Buried	139	-;6	I	95	F1

I/O or Buried	140	-;-	I	-	-

I/O or Buried	141	-;-	I	97	G1

I/O or Buried	142	-;-	I	98	G2

I/O or Buried	143	-;-	I	-	-

I/O or Buried	144	2;1	I	99	H1

I/O or Buried	145	-;3	J	100	H2

OE MUX

Function	LCell	Pin;LCell(2)	LAB	QFP	PGA

I/O or Buried	146	-;-	J	-	-

I/O or Buried	147	-;2	J	101	J1

I/O or Buried	148	-;-	J	-	-

I/O or Buried	149	-;4	J	102	H3

I/O or Buried	150	-;5	J	104	J3

I/O or Buried	151	-;-	J	-	-

I/O or Buried	152	6;-	J	105	K1

I/O or Buried	153	3;-	J	106	J2

I/O or Buried	154	-;-	J	-	-

I/O or Buried	155	-;1	J	107	K2

I/O or Buried	156	-;-	J	-	-

I/O or Buried	157	-;-	J	108	K3

I/O or Buried	158	-;-	J	109	L1

I/O or Buried	159	-;-	J	-	-

I/O or Buried	160	4;6	J	112	M1

I/O or Buried	161	-;5	K	113	L2

I/O or Buried	162	-;-	K	-	-

I/O or Buried	163	-;4	K	114	N1

I/O or Buried	164	-;-	K	-	-

I/O or Buried	165	-;2	K	115	L3

I/O or Buried	166	-;3	K	116	P1

I/O or Buried	167	-;-	K	-	-

I/O or Buried	168	1;-	K	117	M2

I/O or Buried	169	5;-	K	119	N2

I/O or Buried	170	-;-	K	-	-

OE MUX

Function	LCell	Pin;LCell(2)	LAB	QFP	PGA

I/O or Buried	171	-;6	K	121	P2

I/O or Buried	172	-;-	K	-	-

I/O or Buried	173	-;-	K	122	N3

I/O or Buried	174	-;-	K	123	P3

I/O or Buried	175	-;-	K	-	-

I/O or Buried	176	-;1	K	124	P4

I/O or Buried	177	-;3	L	125	R3

I/O or Buried	178	-;-	L	-	-

I/O or Buried	179	-;2	L	127	R4

I/O or Buried	180	-;-	L	-	-

I/O or Buried	181	-;4	L	128	M4

I/O or Buried	182	-;5	L	129	R5

I/O or Buried	183	-;-	L	-	-

I/O or Buried	184	6;-	L	130	P5

I/O or Buried	185	3;-	L	131	R6

I/O or Buried	186	-;-	L	-	-

I/O or Buried	187	-;1	L	132	P6

I/O or Buried	188	-;-	L	-	-

I/O or Buried	189	-;-	L	134	N6

I/O or Buried	190	-;-	L	135	R7

I/O or Buried	191	-;-	L	-	-

I/O or Buried	192	4;6	L	136	P7

VCC	-	-;-	-	10	C5

VCC	-	-;-	-	25	C7

VCC	-	-;-	-	40	C9

OE MUX

Function	LCell	Pin;LCell(2)	LAB	QFP	PGA

VCC	-	-;-	-	55	C10

VCC	-	-;-	-	56	C12

VCC	-	-;-	-	65	D3

VCC	-	-;-	-	74	G12

VCC	-	-;-	-	89	H4

VCC	-	-;-	-	103	J12

VCC	-	-;-	-	118	M3

VCC	-	-;-	-	133	N5

VCC	-	-;-	-	137	N7

VCC	-	-;-	-	144	N9

VCC	-	-;-	-	155	N12

GND	-	-;-	-	3	C4

GND	-	-;-	-	18	C6

GND	-	-;-	-	32	C11

GND	-	-;-	-	47	D7

GND	-	-;-	-	57	D9

GND	-	-;-	-	64	D13

GND	-	-;-	-	66	G4

GND	-	-;-	-	81	H12

GND	-	-;-	-	96	J4

GND	-	-;-	-	111	M7

GND	-	-;-	-	126	M9

GND	-	-;-	-	138	M13

GND	-	-;-	-	143	N4

GND	-	-;-	-	148	N11

OE MUX

Function	LCell	Pin;LCell(2)	LAB	QFP	PGA

N.C.	-	-;-	-	1	A1

N.C.	-	-;-	-	11	A2

N.C.	-	-;-	-	39	A14

N.C.	-	-;-	-	54	A15

N.C.	-	-;-	-	67	R1

N.C.	-	-;-	-	82	R2

N.C.	-	-;-	-	110	R14

N.C.	-	-;-	-	120	R15


EPM7256E EPLDs

The high-density EPM7256E EPLD, a member of the MAX 7000 family, is based on second-generation MAX architecture and has 5,000 usable gates. It can accommodate up to 164 inputs or 160 outputs, and has 256 logic cells divided into 16 LABs. Configurable expander product-term distribution allows up to 32 product terms per logic cell. The EPM7256E is available in 192-pin PGA and 160- and 208-pin QFP packages. For complete information on EPM7256E EPLDs, refer to the current MAX 7000 Programmable Logic Device Family Data Sheet.

See also:

MAX 7000 EPLD Selection Guide

Recommended reading:

AN26 (EPLD/MPLD Design Guidelines)

AN27 (Implementing EISA Interfaces with MAX EPLDs)

AN31 (Fitting Designs in MAX 7000 EPLDs)

AN42 (Metastability in Altera Devices)

AB9 (Asynchronous Latches in Classic, MAX & STG EPLDs)

AB60 (Estimating a Design Fit)

AB87 (Troubleshooting Functional Problems in EPLDs)

AB89 (Minimizing Output Switching Noise in Altera EPLDs)

AB91 (External Clock Sources for Altera EPLDs)

AB94 (Solutions to Design Timing Problems for Altera EPLDs)

AB100 (Understanding Classic, MAX 5000 & MAX 7000 Timing)

Altera Device Package Outlines Data Sheet

Operating Requirements for Altera Devices Data Sheet

OE MUX	QFP	QFP

Function	LCell	Pin;LCell(2)	LAB	(208-pin)	(160-pin)	PGA

Input/OE2/GCLK2	-	-;-	-	181	142	U9

Input/GCLK1	-	-;-	-	184	139	P9

Input/GCLRn	-	-;-	-	182	141	R9

Input/OE1	-	1;-	-	183	140	T9

I/O or Buried	1	-;4	A	153	2	U17

I/O or Buried	2	-;-	A	-	-	-

I/O or Buried	3	-;5	A	154	1	R16

I/O or Buried	4	-;-	A	-	-	-

I/O or Buried	5	-;3	A	159	160	P14

I/O or Buried	6	-;-	A	160	-	U16

I/O or Buried	7	-;-	A	-	-	-

I/O or Buried	8	-;2	A	161	159	R15

I/O or Buried	9	-;6	A	162	158	U15

I/O or Buried	10	-;-	A	-	-	-

I/O or Buried	11	5;-	A	163	157	T15

I/O or Buried	12	-;-	A	-	-	-

I/O or Buried	13	-;-	A	164	156	U14

I/O or Buried	14	-;-	A	166	-	U13

I/O or Buried	15	-;-	A	-	-	-

I/O or Buried	16	2;1	A	167	154	T14

I/O or Buried	17	-;2	B	141	12	N17

I/O or Buried	18	-;-	B	-	-	-

I/O or Buried	19	-;3	B	142	11	M16

I/O or Buried	20	-;-	B	-	-	-

OE MUX	QFP	QFP

Function	LCell	Pin;LCell(2)	LAB	(208-pin)	(160-pin)	PGA

I/O or Buried	21	-;5	B	144	9	M15

I/O or Buried	22	-;-	B	145	-	P17

I/O or Buried	23	-;-	B	-	-	-

I/O or Buried	24	6;4	B	146	8	N16

I/O or Buried	25	-;1	B	147	7	R17

I/O or Buried	26	-;-	B	-	-	-

I/O or Buried	27	3;-	B	148	6	P16

I/O or Buried	28	-;-	B	-	-	-

I/O or Buried	29	-;-	B	149	5	T17

I/O or Buried	30	-;-	B	150	-	N15

I/O or Buried	31	-;-	B	-	-	-

I/O or Buried	32	4;6	B	151	4	T16

I/O or Buried	33	-;4	C	108	39	B17

I/O or Buried	34	-;-	C	-	-	-

I/O or Buried	35	-;5	C	109	38	C15

I/O or Buried	36	-;-	C	-	-	-

I/O or Buried	37	-;3	C	110	37	C17

I/O or Buried	38	-;-	C	111	-	C16

I/O or Buried	39	-;-	C	-	-	-

I/O or Buried	40	1;2	C	112	36	D17

I/O or Buried	41	-;6	C	113	35	D15

I/O or Buried	42	-;-	C	-	-	-

I/O or Buried	43	5;-	C	114	34	E17

I/O or Buried	44	-;-	C	-	-	-

I/O or Buried	45	-;-	C	115	33	D16

OE MUX	QFP	QFP

Function	LCell	Pin;LCell(2)	LAB	(208-pin)	(160-pin)	PGA

I/O or Buried	46	-;-	C	117	-	E15

I/O or Buried	47	-;-	C	-	-	-

I/O or Buried	48	2;1	C	118	31	F16

I/O or Buried	49	-;2	D	92	49	A14

I/O or Buried	50	-;-	D	-	-	-

I/O or Buried	51	-;3	D	93	48	B12

I/O or Buried	52	-;-	D	-	-	-

I/O or Buried	53	-;5	D	95	46	B13

I/O or Buried	54	-;-	D	96	-	A15

I/O or Buried	55	-;-	D	-	-	-

I/O or Buried	56	6;4	D	97	45	B14

I/O or Buried	57	-;1	D	98	44	A16

I/O or Buried	58	-;-	D	-	-	-

I/O or Buried	59	3;-	D	99	43	C14

I/O or Buried	60	-;-	D	-	-	-

I/O or Buried	61	-;-	D	100	42	B16

I/O or Buried	62	-;-	D	101	-	B15

I/O or Buried	63	-;-	D	-	-	-

I/O or Buried	64	4;6	D	102	41	A17

I/O or Buried	65	-;2	E	168	153	U12

I/O or Buried	66	-;-	E	-	-	-

I/O or Buried	67	-;3	E	169	152	R13

I/O or Buried	68	-;-	E	-	-	-

I/O or Buried	69	-;5	E	170	151	U11

I/O or Buried	70	-;-	E	171	-	T13

OE MUX	QFP	QFP

Function	LCell	Pin;LCell(2)	LAB	(208-pin)	(160-pin)	PGA

I/O or Buried	71	-;-	E	-	-	-

I/O or Buried	72	6;4	E	172	150	T11

I/O or Buried	73	-;1	E	173	149	T12

I/O or Buried	74	-;-	E	-	-	-

I/O or Buried	75	3;-	E	175	147	R12

I/O or Buried	76	-;-	E	-	-	-

I/O or Buried	77	-;-	E	176	146	U10

I/O or Buried	78	-;-	E	177	-	R10

I/O or Buried	79	-;-	E	-	-	-

I/O or Buried	80	4;6	E	178	145	T10

I/O or Buried	81	-;4	F	130	21	J16

I/O or Buried	82	-;-	F	-	-	-

I/O or Buried	83	-;5	F	131	20	J15

I/O or Buried	84	-;-	F	-	-	-

I/O or Buried	85	-;3	F	132	19	K17

I/O or Buried	86	-;-	F	133	-	J14

I/O or Buried	87	-;-	F	-	-	-

I/O or Buried	88	1;2	F	135	17	K16

I/O or Buried	89	-;6	F	136	16	K15

I/O or Buried	90	-;-	F	-	-	-

I/O or Buried	91	5;-	F	137	15	L17

I/O or Buried	92	-;-	F	-	-	-

I/O or Buried	93	-;-	F	138	14	L16

I/O or Buried	94	-;-	F	139	-	M17

I/O or Buried	95	-;-	F	-	-	-

OE MUX	QFP	QFP

Function	LCell	Pin;LCell(2)	LAB	(208-pin)	(160-pin)	PGA

I/O or Buried	96	2;1	F	140	13	L15

I/O or Buried	97	-;2	G	119	30	E16

I/O or Buried	98	-;-	G	-	-	-

I/O or Buried	99	-;3	G	120	29	F17

I/O or Buried	100	-;-	G	-	-	-

I/O or Buried	101	-;5	G	121	28	F15

I/O or Buried	102	-;-	G	122	-	G16

I/O or Buried	103	-;-	G	-	-	-

I/O or Buried	104	6;4	G	123	27	G15

I/O or Buried	105	-;1	G	124	26	G17

I/O or Buried	106	-;-	G	-	-	-

I/O or Buried	107	3;-	G	126	24	H17

I/O or Buried	108	-;-	G	-	-	-

I/O or Buried	109	-;-	G	127	23	H15

I/O or Buried	110	-;-	G	128	-	J17

I/O or Buried	111	-;-	G	-	-	-

I/O or Buried	112	4;6	G	129	22	H16

I/O or Buried	113	-;4	H	79	60	C9

I/O or Buried	114	-;-	H	-	-	-

I/O or Buried	115	-;5	H	80	59	D9

I/O or Buried	116	-;-	H	-	-	-

I/O or Buried	117	-;3	H	81	58	C10

I/O or Buried	118	-;-	H	84	-	A10

I/O or Buried	119	-;-	H	-	-	-

I/O or Buried	120	1;2	H	86	54	A11

OE MUX	QFP	QFP

Function	LCell	Pin;LCell(2)	LAB	(208-pin)	(160-pin)	PGA

I/O or Buried	121	-;6	H	87	53	B10

I/O or Buried	122	-;-	H	-	-	-

I/O or Buried	123	5;-	H	88	52	A12

I/O or Buried	124	-;-	H	-	-	-

I/O or Buried	125	-;-	H	89	51	B11

I/O or Buried	126	-;-	H	90	-	A13

I/O or Buried	127	-;-	H	-	-	-

I/O or Buried	128	2;1	H	91	50	C12

I/O or Buried	129	-;2	I	197	128	U6

I/O or Buried	130	-;-	I	-	-	-

I/O or Buried	131	-;3	I	196	129	T5

I/O or Buried	132	-;-	I	-	-	-

I/O or Buried	133	-;5	I	195	130	U7

I/O or Buried	134	-;-	I	194	-	T6

I/O or Buried	135	-;-	I	-	-	-

I/O or Buried	136	6;4	I	193	131	T7

I/O or Buried	137	-;1	I	192	132	R6

I/O or Buried	138	-;-	I	-	-	-

I/O or Buried	139	3;-	I	190	134	R7

I/O or Buried	140	-;-	I	-	-	-

I/O or Buried	141	-;-	I	189	135	U8

I/O or Buried	142	-;-	I	188	-	R8

I/O or Buried	143	-;-	I	-	-	-

I/O or Buried	144	4;6	I	187	136	T8

I/O or Buried	145	-;4	J	27	100	J2

OE MUX	QFP	QFP

Function	LCell	Pin;LCell(2)	LAB	(208-pin)	(160-pin)	PGA

I/O or Buried	146	-;-	J	-	-	-

I/O or Buried	147	-;5	J	26	101	J3

I/O or Buried	148	-;-	J	-	-	-

I/O or Buried	149	-;3	J	25	102	K1

I/O or Buried	150	-;-	J	24	-	J4

I/O or Buried	151	-;-	J	-	-	-

I/O or Buried	152	1;2	J	22	104	K2

I/O or Buried	153	-;6	J	21	105	K3

I/O or Buried	154	-;-	J	-	-	-

I/O or Buried	155	5;-	J	20	106	L1

I/O or Buried	156	-;-	J	-	-	-

I/O or Buried	157	-;-	J	19	107	L2

I/O or Buried	158	-;-	J	18	-	M1

I/O or Buried	159	-;-	J	-	-	-

I/O or Buried	160	2;1	J	17	108	L3

I/O or Buried	161	-;2	K	38	91	F3

I/O or Buried	162	-;-	K	-	-	-

I/O or Buried	163	-;3	K	37	92	F1

I/O or Buried	164	-;-	K	-	-	-

I/O or Buried	165	-;5	K	36	93	E2

I/O or Buried	166	-;-	K	35	-	G2

I/O or Buried	167	-;-	K	-	-	-

I/O or Buried	168	6;4	K	34	94	G3

I/O or Buried	169	-;1	K	33	95	G1

I/O or Buried	170	-;-	K	-	-	-

OE MUX	QFP	QFP

Function	LCell	Pin;LCell(2)	LAB	(208-pin)	(160-pin)	PGA

I/O or Buried	171	3;-	K	31	97	H1

I/O or Buried	172	-;-	K	-	-	-

I/O or Buried	173	-;-	K	30	98	H3

I/O or Buried	174	-;-	K	29	-	J1

I/O or Buried	175	-;-	K	-	-	-

I/O or Buried	176	4;6	K	28	99	H2

I/O or Buried	177	-;4	L	78	61	B9

I/O or Buried	178	-;-	L	-	-	-

I/O or Buried	179	-;5	L	77	62	C8

I/O or Buried	180	-;-	L	-	-	-

I/O or Buried	181	-;3	L	76	63	A9

I/O or Buried	182	-;-	L	73	-	A8

I/O or Buried	183	-;-	L	-	-	-

I/O or Buried	184	1;2	L	71	67	A7

I/O or Buried	185	-;6	L	70	68	B8

I/O or Buried	186	-;-	L	-	-	-

I/O or Buried	187	5;-	L	69	69	A6

I/O or Buried	188	-;-	L	-	-	-

I/O or Buried	189	-;-	L	68	70	B7

I/O or Buried	190	-;-	L	67	-	A5

I/O or Buried	191	-;-	L	-	-	-

I/O or Buried	192	2;1	L	66	71	C6

I/O or Buried	193	-;4	M	4	119	U1

I/O or Buried	194	-;-	M	-	-	-

I/O or Buried	195	-;5	M	3	120	R2

OE MUX	QFP	QFP

Function	LCell	Pin;LCell(2)	LAB	(208-pin)	(160-pin)	PGA

I/O or Buried	196	-;-	M	-	-	-

I/O or Buried	197	-;3	M	206	121	R3

I/O or Buried	198	-;-	M	205	-	U2

I/O or Buried	199	-;-	M	-	-	-

I/O or Buried	200	1;2	M	204	122	P4

I/O or Buried	201	-;6	M	203	123	U3

I/O or Buried	202	-;-	M	-	-	-

I/O or Buried	203	5;-	M	202	124	T3

I/O or Buried	204	-;-	M	-	-	-

I/O or Buried	205	-;-	M	201	125	U4

I/O or Buried	206	-;-	M	199	-	U5

I/O or Buried	207	-;-	M	-	-	-

I/O or Buried	208	-;1	M	198	127	T4

I/O or Buried	209	-;2	N	16	109	N1

I/O or Buried	210	-;-	N	-	-	-

I/O or Buried	211	-;3	N	15	110	M2

I/O or Buried	212	-;-	N	-	-	-

I/O or Buried	213	-;5	N	13	112	M3

I/O or Buried	214	-;-	N	12	-	P1

I/O or Buried	215	-;-	N	-	-	-

I/O or Buried	216	6;4	N	11	113	N2

I/O or Buried	217	-;1	N	10	114	R1

I/O or Buried	218	-;-	N	-	-	-

I/O or Buried	219	3;-	N	9	115	P2

I/O or Buried	220	-;-	N	-	-	-

OE MUX	QFP	QFP

Function	LCell	Pin;LCell(2)	LAB	(208-pin)	(160-pin)	PGA

I/O or Buried	221	-;-	N	8	116	T1

I/O or Buried	222	-;-	N	7	-	N3

I/O or Buried	223	-;-	N	-	-	-

I/O or Buried	224	4;6	N	6	117	T2

I/O or Buried	225	-;4	O	49	82	B1

I/O or Buried	226	-;-	O	-	-	-

I/O or Buried	227	-;5	O	48	83	C3

I/O or Buried	228	-;-	O	-	-	-

I/O or Buried	229	-;3	O	47	84	C1

I/O or Buried	230	-;-	O	46	-	D3

I/O or Buried	231	-;-	O	-	-	-

I/O or Buried	232	1;2	O	45	85	D1

I/O or Buried	233	-;6	O	44	86	C2

I/O or Buried	234	-;-	O	-	-	-

I/O or Buried	235	5;-	O	43	87	E1

I/O or Buried	236	-;-	O	-	-	-

I/O or Buried	237	-;-	O	42	88	E3

I/O or Buried	238	-;-	O	40	-	D2

I/O or Buried	239	-;-	O	-	-	-

I/O or Buried	240	2;1	O	39	90	F2

I/O or Buried	241	-;2	P	65	72	A4

I/O or Buried	242	-;-	P	-	-	-

I/O or Buried	243	-;3	P	64	73	B6

I/O or Buried	244	-;-	P	-	-	-

I/O or Buried	245	-;5	P	62	75	B5

OE MUX	QFP	QFP

Function	LCell	Pin;LCell(2)	LAB	(208-pin)	(160-pin)	PGA

I/O or Buried	246	-;-	P	61	-	A3

I/O or Buried	247	-;-	P	-	-	-

I/O or Buried	248	6;4	P	60	76	B4

I/O or Buried	249	-;1	P	59	77	A2

I/O or Buried	250	-;-	P	-	-	-

I/O or Buried	251	3;-	P	58	78	C4

I/O or Buried	252	-;-	P	-	-	-

I/O or Buried	253	-;-	P	57	79	B2

I/O or Buried	254	-;-	P	56	-	B3

I/O or Buried	255	-;-	P	-	-	-

I/O or Buried	256	4;6	P	55	80	A1

VCC	-	-;-	-	5	10	C5

VCC	-	-;-	-	23	25	C11

VCC	-	-;-	-	41	40	D7

VCC	-	-;-	-	63	55	D11

VCC	-	-;-	-	74	56	D14

VCC	-	-;-	-	83	65	G4

VCC	-	-;-	-	85	74	H14

VCC	-	-;-	-	107	89	K4

VCC	-	-;-	-	125	103	L14

VCC	-	-;-	-	143	118	P3

VCC	-	-;-	-	165	133	P7

VCC	-	-;-	-	179	137	P11

VCC	-	-;-	-	186	144	R5

VCC	-	-;-	-	191	155	R14

OE MUX	QFP	QFP

Function	LCell	Pin;LCell(2)	LAB	(208-pin)	(160-pin)	PGA

GND	-	-;-	-	14	3	C7

GND	-	-;-	-	32	18	C13

GND	-	-;-	-	50	32	D4

GND	-	-;-	-	72	47	D8

GND	-	-;-	-	75	57	D10

GND	-	-;-	-	82	64	G14

GND	-	-;-	-	94	66	H4

GND	-	-;-	-	116	81	K14

GND	-	-;-	-	134	96	L4

GND	-	-;-	-	152	111	P8

GND	-	-;-	-	174	126	P10

GND	-	-;-	-	180	138	P15

GND	-	-;-	-	185	143	R4

GND	-	-;-	-	200	148	R11

N.C.	-	-;-	-	1	-	-

N.C.	-	-;-	-	2	-	-

N.C.	-	-;-	-	51	-	-

N.C.	-	-;-	-	52	-	-

N.C.	-	-;-	-	53	-	-

N.C.	-	-;-	-	54	-	-

N.C.	-	-;-	-	103	-	-

N.C.	-	-;-	-	104	-	-

N.C.	-	-;-	-	105	-	-

N.C.	-	-;-	-	106	-	-

N.C.	-	-;-	-	155	-	-

OE MUX	QFP	QFP

Function	LCell	Pin;LCell(2)	LAB	(208-pin)	(160-pin)	PGA

N.C.	-	-;-	-	156	-	-

N.C.	-	-;-	-	157	-	-

N.C.	-	-;-	-	158	-	-

N.C.	-	-;-	-	207	-	-

N.C.	-	-;-	-	208	-	-


MAX 7000E Note 1
Note (1)

The OE2 pin can be used as a second global Clock pin only on MAX 7000E devices, not on MAX 7000 devices.


MAX 7000E Note 2
Note (2)

(MAX 7000E devices only) The data in the "OE MUX Pin;LCell" column lists the possible sources of the six global Output Enable signals (GOE1 through GOE6). For complete information on the global Output Enable signals, refer to the current MAX 7000 Programmable Logic Device Family Data Sheet. Numbers before the semicolon (;) represent global Output Enable signals that are fed by the pin in the corresponding "Function" column; numbers after the semicolon represent global Output Enable signals that are fed by the logic cell listed in the corresponding "LCell" column. Each Output Enable can be fed only by a single pin or logic cell. Dedicated input pins do not have logic cells.


MAX 7000 EPLD Selection Guide

The following table provides information on the MAX 7000 family of general-purpose EPLDs. MAX 7000 EPLDs are suitable for designs that require high performance, high I/O count, and densities of up to 256 macrocells (5,000 gates).

For up-to-date information on device availability, contact Altera Marketing. For more information on MAX 7000 devices, refer to the Altera Data Book or contact the Altera Literature Department for a copy of the current MAX 7000 Programmable Logic Device Family Data Sheet.

EPLD	Package	Temp.	Speed	tPD1	fCNT 	LCell	Ded.	I/O

Note (1)	Note (2)	Note (3)	Grade	(ns)	(MHz)	(Reg.)	Inputs

EPM7032	44L	C	-5	5.0	178.6	32	4	32

EPM7032	44L,44T	C	-6	6.0	151.5	32	4	32

EPM7032	44L,44Q,44T	C	-7	7.5	125.0	32	4	32

EPM7032	44L,44Q,44T	C	-10	10	100.0	32	4	32

EPM7032	44L,44Q,44T	C	-12	12	90.9	32	4	32

EPM7032	44L,44Q	I	-12	12	90.9	32	4	32

EPM7032	44L,44Q,44T	C,I	-15	15	76.9	32	4	32

EPM7032	44L	C	-15T	15	76.9	32	4	32

EPM7032V	44L,44T	C	-12	12	90.9	32	4	32

EPM7032V	44L,44T	C	-15	15	76.9	32	4	32

EPM7032V	44L,44T	C	-20	20	62.5	32	4	32

EPM7032V	44T	I	-20	20	62.5	32	4	32

EPM7064	44L,44T,68L,84L,100Q	C	-7	7.5	125.0	64	4	32,32,48,64,64

EPM7064	44L,68L,84L,100Q	C	-10	10	100.0	64	4	32,32,48,64,64

EPM7064	44L,68L,84L,100Q	C	-12	12	90.9	64	4	32,32,48,64,64

EPM7064	44L,44T,68L,84L,100Q	C	-15	15	76.9	64	4	32,32,48,64,64

EPM7064	44L,68L,84L,100Q	I	-15	15	76.9	64	4	32,32,48,64,64

EPM7096	68L,84L,100Q	C	-7	7	125.0	96	4	48,60,72

EPM7096	68L,84L,100Q	C	-10	10	100.0	96	4	48,60,72

EPM7096	68L,84L,100Q	C	-12	12	90.9	96	4	48,60,72

EPM7096	68L,84L,100Q	C,I	-15	15	76.9	96	4	48,60,72

EPM7128E	84L,100Q,160Q	C	-7	7.5	125.0	128	4	64,80,96

EPM7128E	84L,100Q,160Q	C	-10	10	100.0	128	4	64,80,96

EPM7128E	100Q,160Q	C	-10P	10	100.0	128	4	64,80,96

EPM7128E	84L,100Q,160Q	C	-12	12	90.9	128	4	64,80,96

EPM7128E	84L,100Q,160Q	C	-15	15	76.9	128	4	64,80,96

EPM7128E	100Q	I	-15	15	76.9	128	4	80

EPM7128E	84L,100Q,160Q	C	-20	20	62.5	128	4	64,80,96

EPM7128E	84L,100Q	I	-20	20	62.5	128	4	64,80

EPM7160E	84L,100Q,160Q	C	-10	10	100.0	160	4	60,80,100

EPM7160E	100Q,160Q	C	-10P	10	100.0	160	4	60,80,100

EPM7160E	84L,100Q,160Q	C	-12	12	90.9	160	4	60,80,100

EPM7160E	84L,100Q,160Q	C	-15	15	76.9	160	4	60,80,100

EPM7160E	84L,100Q,160Q	C	-20	20	62.5	160	4	60,80,100

EPM7160E	84L	I	-20	20	62.5	160	4	60

EPM7192E	160G,160Q	C	-12	12	90.9	192	4	120,120

EPM7192E	160Q	C	-12P	12	90.9	192	4	120

EPM7192E	160G,160Q	C,M	-15	15	76.9	192	4	120,120

EPM7192E	160G,160Q	C,I,M	-20	20	62.5	192	4	120,120

EPM7256E	160Q,192G,208R	C	-12	12	90.9	256	4	128,160,160

EPM7256E	160Q,208R	C	-12P	12	90.9	256	4	128,160

EPM7256E	160Q,192G,208R	C	-15	15	76.9	256	4	128,160,160

EPM7256E	192G,208W	M	-15	15	76.9	256	4	160,160

EPM7256E	160Q,192G,208R	C	-20	20	62.5	256	4	128,160,160

EPM7256E	192G,208R	I	-20	20	62.5	256	4	160,160

EPM7256E	192G,208W	M	-20	20	62.5	256	4	160,160

EPM7256E	208R	C	-20	20	62.5	256	4	160

Recommended reading:

AB46 (Selecting Sockets for J-Lead Packages)

AB60 (Estimating a Design Fit)

AB100 (Understanding Classic, MAX 5000 & MAX 7000 Timing)

Altera Device Package Outlines Data Sheet

Operating Requirements for Altera Devices Data Sheet

QFP Carrier & Development Socket Data Sheet


MPLDs

Altera Mask-Programmed Logic Devices (MPLDs) provide a masked alternative to programmable logic devices. By using a generic CMOS process and removing all EPROM/EEPROM/SRAM cells, Altera passes considerable savings on to customers who anticipate high-volume production. The combination of Altera programmable logic and MPLDs provides the best of both worlds: the fast time-to-market offered by programmable logic devices, and the low cost and low risk offered by MPLDs.

Altera handles the entire programmable logic device-to-MPLD conversion process so that no redesign effort is required on the part of the customer. Altera guarantees that the MPLD meets the worst-case AC and DC parameters of the original design. In addition, Altera automatically generates test vectors with over 95% fault coverage.

For additional information, refer to the current MPLDs: Mask-Programmed Logic Devices Data Sheet.

See also:

Design Doctor

Recommended reading:

AN26 (EPLD/MPLD Design Guidelines)

MPLD Conversion Information & Order Forms Workbook

PIB14 (MPLDs: The Fastest Route to High-Volume Production)


EPM9320 EPLDs

The EPM9320 EPLD, a member of the MAX 9000 family, provides 484 registers and a large number of storage elements for complex circuit applications.

The EPM9320 is available in 84-pin J-lead packages with 56 I/O pins, 208-pin QFP packages with 128 I/O pins, and 280-pin PGA packages with 164 I/O pins. It has 320 logic cells grouped into 20 LABs. These LABs are arranged into 4 rows and 5 columns. Each I/O element contains a bidirectional I/O buffer and an enable flipflop that can be used as either an input or output register. It also contains 4 dedicated fast inputs for synchronous control signals with large fan-outs. When used as outputs, the I/O registers provide fast Clock-to-output times; as inputs, they provide quick setup times. For complete information on EPM9320 devices, refer to the current MAX 9000 Programmable Logic Device Family Data Sheet.

See also:

MAX 9000 EPLD Selection Guide

Recommended reading:

AN42 (Metastability in Altera Devices)

AB144 (Understanding MAX 9000 Timing)

Operating Requirements for Altera Devices Data Sheet

QFP

Function	Dedicated Pin	Row	Col	(208-pin)	J-Lead	PGA

Ded. Prog. Pin	VPP (1)	-	-	48	56	C4

Ded. JTAG Pin	TMS	-	-	49	55	D6

Ded. JTAG Pin	TCLK	-	-	78	43	A9

Ded. JTAG Pin	TDI	-	-	79	42	C11

Ded. JTAG Pin	TDO	-	-	108	30	A18

Input/GCLK1	-	-	182	1	V10

Input/GCLK2	-	-	183	84	U10

Input/GCLR	-	-	153	13	V17

Input/GOE	-	-	4	72	W2

I/O	A	-	37	-	D1

I/O	A	-	38	59	E3

I/O	A	-	39	-	C1

I/O	A	-	40	58	D2

I/O	A	-	117	27	D18

I/O	A	-	119	26	E17

I/O	A	-	120	-	C19

I/O	A	-	-	-	A19

I/O	A	-	-	-	B1

I/O	A	-	-	-	B18

I/O	A	-	-	-	B19

I/O	A	-	-	-	C2

I/O	A	-	-	-	C3

QFP

Function	Dedicated Pin	Row	Col	(208-pin)	J-Lead	PGA

I/O	A	-	-	-	C18

I/O	A	-	-	-	D3

I/O	A	-	-	-	D17

I/O	B	-	32	63	G4

I/O	B	-	33	-	F1

I/O	B	-	34	62	F3

I/O	B	-	123	-	E18

I/O	B	-	124	23	G16

I/O	B	-	125	-	E19

I/O	B	-	126	22	G17

I/O	B	-	-	-	D19

I/O	B	-	-	-	E1

I/O	B	-	-	-	E2

I/O	B	-	-	-	F2

I/O	B	-	-	-	F4

I/O	B	-	-	-	F16

I/O	B	-	-	-	F17

I/O	B	-	-	-	F18

I/O	B	-	-	-	G2

I/O	C	-	26	66	J4

I/O	C	-	27	-	H1

I/O	C	-	28	65	H3

I/O	C	-	29	-	H2

I/O	C	-	129	20	J16

I/O	C	-	130	-	G19

QFP

Function	Dedicated Pin	Row	Col	(208-pin)	J-Lead	PGA

I/O	C	-	131	19	J17

I/O	C	-	-	-	F19

I/O	C	-	-	-	G1

I/O	C	-	-	-	G3

I/O	C	-	-	-	G18

I/O	C	-	-	-	H4

I/O	C	-	-	-	H16

I/O	C	-	-	-	H17

I/O	C	-	-	-	H18

I/O	C	-	-	-	J2

I/O	D	-	21	69	L3

I/O	D	-	22	-	K2

I/O	D	-	23	68	K4

I/O	D	-	134	-	J18

I/O	D	-	135	17	L17

I/O	D	-	136	-	J19

I/O	D	-	137	16	L16

I/O	D	-	-	-	H19

I/O	D	-	-	-	J1

I/O	D	-	-	-	J3

I/O	D	-	-	-	K1

I/O	D	-	-	-	K3

I/O	D	-	-	-	K16

I/O	D	-	-	-	K17

I/O	D	-	-	-	K18

QFP

Function	Dedicated Pin	Row	Col	(208-pin)	J-Lead	PGA

I/O	D	-	-	-	L1

I/O	-	1	97	34	B15

I/O	-	1	98	-	B14

I/O	-	1	99	33	C15

I/O	-	1	100	-	A15

I/O	-	1	101	-	B16

I/O	-	1	103	-	C16

I/O	-	1	104	32	A16

I/O	-	1	105	-	B17

I/O	-	1	106	31	A17

I/O	-	1	107	-	C17

I/O	-	1	154	-	W19

I/O	-	1	155	12	U16

I/O	-	1	156	-	V18

I/O	-	1	157	11	V16

I/O	-	1	158	-	W18

I/O	-	1	160	-	W17

I/O	-	1	161	-	U15

I/O	-	1	162	10	W16

I/O	-	1	163	-	V15

I/O	-	1	164	9	W15

I/O	-	2	86	39	B11

I/O	-	2	87	-	C13

I/O	-	2	88	38	A12

I/O	-	2	89	-	D12

QFP

Function	Dedicated Pin	Row	Col	(208-pin)	J-Lead	PGA

I/O	-	2	90	-	B12

I/O	-	2	92	-	A13

I/O	-	2	93	36	D13

I/O	-	2	94	-	B13

I/O	-	2	95	35	C14

I/O	-	2	96	-	A14

I/O	-	2	165	-	U14

I/O	-	2	166	8	W14

I/O	-	2	167	-	V14

I/O	-	2	168	7	W13

I/O	-	2	169	-	T12

I/O	-	2	171	-	U13

I/O	-	2	172	-	V12

I/O	-	2	173	5	V13

I/O	-	2	174	-	W12

I/O	-	2	175	4	T11

I/O	-	3	73	45	B9

I/O	-	3	74	-	A7

I/O	-	3	75	44	D10

I/O	-	3	76	-	A8

I/O	-	3	77	-	C10

I/O	-	3	80	-	B10

I/O	-	3	81	41	D11

I/O	-	3	82	-	A10

I/O	-	3	83	40	C12

QFP

Function	Dedicated Pin	Row	Col	(208-pin)	J-Lead	PGA

I/O	-	3	84	-	A11

I/O	-	3	177	-	U12

I/O	-	3	178	3	V11

I/O	-	3	179	-	T10

I/O	-	3	180	2	W11

I/O	-	3	181	-	U11

I/O	-	3	184	-	W10

I/O	-	3	185	-	U9

I/O	-	3	186	83	W9

I/O	-	3	187	-	T9

I/O	-	3	188	82	V9

I/O	-	4	61	50	C7

I/O	-	4	62	-	B5

I/O	-	4	63	49	B7

I/O	-	4	64	-	A4

I/O	-	4	65	-	C8

I/O	-	4	67	-	D9

I/O	-	4	68	47	A5

I/O	-	4	69	-	C9

I/O	-	4	70	46	A6

I/O	-	4	71	-	B8

I/O	-	4	190	-	W8

I/O	-	4	191	81	V8

I/O	-	4	192	-	W7

I/O	-	4	193	80	U8

QFP

Function	Dedicated Pin	Row	Col	(208-pin)	J-Lead	PGA

I/O	-	4	194	-	W6

I/O	-	4	196	-	V6

I/O	-	4	197	-	V7

I/O	-	4	198	78	W5

I/O	-	4	199	-	T8

I/O	-	4	200	77	V5

I/O	-	5	1	74	T6

I/O	-	5	2	-	V3

I/O	-	5	3	73	U4

I/O	-	5	50	54	B2

I/O	-	5	51	-	C5

I/O	-	5	52	53	A1

I/O	-	5	53	-	C6

I/O	-	5	54	-	B3

I/O	-	5	56	-	A2

I/O	-	5	57	52	D7

I/O	-	5	58	-	B4

I/O	-	5	59	51	D8

I/O	-	5	60	-	A3

I/O	-	5	201	-	U7

I/O	-	5	202	76	W4

I/O	-	5	203	-	T7

I/O	-	5	204	75	V4

I/O	-	5	205	-	U6

I/O	-	5	207	-	U5

QFP

Function	Dedicated Pin	Row	Col	(208-pin)	J-Lead	PGA

I/O	-	5	208	-	W3

VCC	-	-	5	14	D14

VCC	-	-	10	15	D15

VCC	-	-	19	21	E7

VCC	-	-	25	28	E8

VCC	-	-	30	37	E9

VCC	-	-	36	57	E10

VCC	-	-	45	60	E11

VCC	-	-	55	64	E12

VCC	-	-	72	71	E13

VCC	-	-	91	79	E14

VCC	-	-	111	-	R6

VCC	-	-	112	-	R7

VCC	-	-	127	-	R8

VCC	-	-	128	-	R9

VCC	-	-	138	-	R10

VCC	-	-	139	-	R11

VCC	-	-	148	-	R12

VCC	-	-	159	-	R13

VCC	-	-	176	-	R14

VCC	-	-	195	-	T13

VCC	-	-	-	-	T14

VCC	-	-	-	-	T15

GND	-	-	14	6	D4

GND	-	-	20	18	D5

GND	-	-	24	-	-

QFP

Function	Dedicated Pin	Row	Col	(208-pin)	J-Lead	PGA

GND	-	-	31	24	D16

GND	-	-	35	25	E4

GND	-	-	41	48	E5

GND	-	-	42	61	E6

GND	-	-	43	67	E15

GND	-	-	44	70	E16

GND	-	-	46	-	F5

GND	-	-	47	-	F15

GND	-	-	66	-	G5

GND	-	-	85	-	G15

GND	-	-	102	-	H5

GND	-	-	110	-	H15

GND	-	-	113	-	J5

GND	-	-	114	-	J15

GND	-	-	115	-	K5

GND	-	-	116	-	K15

GND	-	-	118	-	L5

GND	-	-	121	-	L15

GND	-	-	122	-	M5

GND	-	-	132	-	M15

GND	-	-	133	-	N5

GND	-	-	143	-	N15

GND	-	-	152	-	P4

GND	-	-	170	-	P5

GND	-	-	189	-	P15

GND	-	-	206	-	-

QFP

Function	Dedicated Pin	Row	Col	(208-pin)	J-Lead	PGA

GND	-	-	-	-	P16

GND	-	-	-	-	R4

GND	-	-	-	-	R5

GND	-	-	-	-	R15

GND	-	-	-	-	R16

GND	-	-	-	-	T4

GND	-	-	-	-	T5

GND	-	-	-	-	T16

N.C.	-	-	6	29	B6

N.C.	-	-	7	-	K19

N.C.	-	-	8	-	L2

N.C.	-	-	9	-	L4

N.C.	-	-	11	-	L18

N.C.	-	-	12	-	L19

N.C.	-	-	13	-	M1

N.C.	-	-	15	-	M2

N.C.	-	-	16	-	M3

N.C.	-	-	17	-	M4

N.C.	-	-	18	-	M16

N.C.	-	-	-	-	M17

N.C.	-	-	-	-	M18

N.C.	-	-	-	-	M19

N.C.	-	-	-	-	N1

N.C.	-	-	-	-	N2

N.C.	-	-	-	-	N3

QFP

Function	Dedicated Pin	Row	Col	(208-pin)	J-Lead	PGA

N.C.	-	-	109	-	N4

N.C.	-	-	140	-	N16

N.C.	-	-	141	-	N17

N.C.	-	-	142	-	N18

N.C.	-	-	144	-	N19

N.C.	-	-	145	-	P1

N.C.	-	-	146	-	P2

N.C.	-	-	147	-	P3

N.C.	-	-	149	-	P17

N.C.	-	-	150	-	P18

N.C.	-	-	151	-	P19

N.C.	-	-	-	-	R1

N.C.	-	-	-	-	R2

N.C.	-	-	-	-	R3

N.C.	-	-	-	-	R17

N.C.	-	-	-	-	R18

N.C.	-	-	-	-	R19

N.C.	-	-	-	-	T1

N.C.	-	-	-	-	T2

N.C.	-	-	-	-	T3

N.C.	-	-	-	-	T17

N.C.	-	-	-	-	T18

N.C.	-	-	-	-	T19

N.C.	-	-	-	-	U1

N.C.	-	-	-	-	U2

QFP

Function	Dedicated Pin	Row	Col	(208-pin)	J-Lead	PGA

N.C.	-	-	-	-	U3

N.C.	-	-	-	-	U17

N.C.	-	-	-	-	U18

N.C.	-	-	-	-	U19

N.C.	-	-	-	-	V1

N.C.	-	-	-	-	V2

N.C.	-	-	-	-	V19

N.C.	-	-	-	-	W1


EPM9400 EPLDs

The EPM9400 EPLD, a member of the MAX 9000 family, provides 580 registers and a large number of storage elements for complex circuit applications.

The EPM9400 is available in 208-pin QFP packages with 135 I/O pins and 240-pin QFP packages with 155 I/O pins. It has 400 logic cells grouped into 25 LABs. These LABs are arranged into 5 rows and 5 columns. Each I/O element contains a bidirectional I/O buffer and an enable flipflop that can be used as either an input or output register. It also contains 4 dedicated fast inputs for synchronous control signals with large fan-outs. When used as outputs, the I/O registers provide fast Clock-to-output times; as inputs, they provide quick setup times. For complete information on EPM9400 devices, refer to the current MAX 9000 Programmable Logic Device Family Data Sheet.

See also:

MAX 9000 EPLD Selection Guide


EPM9480 EPLDs

The EPM9480 EPLD, a member of the MAX 9000 family, provides 676 registers and a large number of storage elements for complex circuit applications.

The EPM9480 is available in 208-pin QFP packages with 142 I/O pins and 240-pin QFP packages with 171 I/O pins. It has 480 logic cells grouped into 30 LABs. These LABs are arranged into 6 rows and 5 columns. Each I/O element contains a bidirectional I/O buffer and an enable flipflop that can be used as either an input or output register. It also contains 4 dedicated fast inputs for synchronous control signals with large fan-outs. When used as outputs, the I/O registers provide fast Clock-to-output times; as inputs, they provide quick setup times. For complete information on EPM9480 devices, refer to the current MAX 9000 Programmable Logic Device Family Data Sheet.

See also:

MAX 9000 EPLD Selection Guide

QFP	QFP

Function	Dedicated Pin	Row	Col	(240-pin)	(208-pin)

Ded. Prog. Pin	VPP (1)	-	-	67	48

Ded. JTAG Pin	TCLK	-	-	68	49

Ded. JTAG Pin	TDO	-	-	91	78

Ded. JTAG Pin	TDI	-	-	92	79

Ded. JTAG Pin	TMS	-	-	114	108

Input/GCLK1	-	-	210	182

Input/GCLK2	-	-	211	183

Input/GCLR	-	-	187	153

Input/GOE	-	-	234	4

I/O	A	-	56	37

I/O	A	-	B1	57

I/O	A	-	58	39

I/O	A	-	59	40

I/O	A	-	60	117

I/O	A	-	61	119

I/O	A	-	62	-

I/O	A	-	63	-

I/O	A	-	118	-

I/O	A	-	119	-

I/O	A	-	120	-

I/O	A	-	121	-

I/O	A	-	122	-

I/O	A	-	123	-

I/O	A	-	124	-

QFP	QFP

Function	Dedicated Pin	Row	Col	(240-pin)	(208-pin)

I/O	A	-	125	120

I/O	B	-	46	32

I/O	B	-	47	33

I/O	B	-	48	34

I/O	B	-	49	123

I/O	B	-	50	124

I/O	B	-	51	125

I/O	B	-	52	126

I/O	B	-	53	-

I/O	B	-	128	-

I/O	B	-	129	-

I/O	B	-	130	-

I/O	B	-	131	-

I/O	B	-	132	-

I/O	B	-	133	-

I/O	B	-	134	-

I/O	B	-	135	-

I/O	C	-	36	26

I/O	C	-	37	27

I/O	C	-	38	28

I/O	C	-	39	29

I/O	C	-	40	-

I/O	C	-	41	-

I/O	C	-	42	-

I/O	C	-	43	-

QFP	QFP

Function	Dedicated Pin	Row	Col	(240-pin)	(208-pin)

I/O	C	-	138	-

I/O	C	-	139	-

I/O	C	-	140	-

I/O	C	-	141	-

I/O	C	-	142	129

I/O	C	-	143	130

I/O	C	-	144	131

I/O	C	-	145	-

I/O	D	-	26	-

I/O	D	-	27	21

I/O	D	-	28	22

I/O	D	-	29	23

I/O	D	-	30	-

I/O	D	-	31	-

I/O	D	-	32	-

I/O	D	-	33	-

I/O	D	-	148	-

I/O	D	-	149	-

I/O	D	-	150	-

I/O	D	-	151	134

I/O	D	-	152	135

I/O	D	-	153	136

I/O	D	-	154	137

I/O	D	-	155	-

I/O	E	-	16	-

QFP	QFP

Function	Dedicated Pin	Row	Col	(240-pin)	(208-pin)

I/O	E	-	17	15

I/O	E	-	18	16

I/O	E	-	19	17

I/O	E	-	20	18

I/O	E	-	21	-

I/O	E	-	22	-

I/O	E	-	23	-

I/O	E	-	158	-

I/O	E	-	159	-

I/O	E	-	160	-

I/O	E	-	161	-

I/O	E	-	162	140

I/O	E	-	163	141

I/O	E	-	164	142

I/O	E	-	165	-

I/O	F	-	6	-

I/O	F	-	7	11

I/O	F	-	8	12

I/O	F	-	9	13

I/O	F	-	10	-

I/O	F	-	11	-

I/O	F	-	12	-

I/O	F	-	13	-

I/O	F	-	168	-

I/O	F	-	169	-

QFP	QFP

Function	Dedicated Pin	Row	Col	(240-pin)	(208-pin)

I/O	F	-	170	-

I/O	F	-	171	-

I/O	F	-	172	144

I/O	F	-	173	145

I/O	F	-	174	146

I/O	F	-	175	147

I/O	-	1	106	97

I/O	-	1	107	99

I/O	-	1	108	100

I/O	-	1	109	101

I/O	-	1	111	104

I/O	-	1	112	106

I/O	-	1	113	107

I/O	-	1	188	154

I/O	-	1	189	155

I/O	-	1	190	157

I/O	-	1	191	158

I/O	-	1	193	160

I/O	-	1	194	161

I/O	-	1	195	162

I/O	-	1	196	164

I/O	-	1	-	98

I/O	-	1	-	156

I/O	-	1	-	105

I/O	-	1	-	103

QFP	QFP

Function	Dedicated Pin	Row	Col	(240-pin)	(208-pin)

I/O	-	1	-	163

I/O	-	2	97	86

I/O	-	2	98	88

I/O	-	2	99	89

I/O	-	2	100	90

I/O	-	2	102	92

I/O	-	2	103	93

I/O	-	2	104	95

I/O	-	2	105	96

I/O	-	2	197	165

I/O	-	2	198	166

I/O	-	2	199	168

I/O	-	2	201	171

I/O	-	2	202	172

I/O	-	2	203	173

I/O	-	2	204	175

I/O	-	2	-	94

I/O	-	2	-	87

I/O	-	2	-	167

I/O	-	2	-	169

I/O	-	2	-	174

I/O	-	3	87	73

I/O	-	3	88	75

I/O	-	3	89	76

I/O	-	3	90	77

QFP	QFP

Function	Dedicated Pin	Row	Col	(240-pin)	(208-pin)

I/O	-	3	93	81

I/O	-	3	94	83

I/O	-	3	95	84

I/O	-	3	206	177

I/O	-	3	207	178

I/O	-	3	208	180

I/O	-	3	209	181

I/O	-	3	212	184

I/O	-	3	213	185

I/O	-	3	214	186

I/O	-	3	215	188

I/O	-	3	-	74

I/O	-	3	-	80

I/O	-	3	-	179

I/O	-	3	-	187

I/O	-	3	-	82

I/O	-	4	77	61

I/O	-	4	78	63

I/O	-	4	79	64

I/O	-	4	80	65

I/O	-	4	82	67

I/O	-	4	83	68

I/O	-	4	84	70

I/O	-	4	85	71

I/O	-	4	217	190

QFP	QFP

Function	Dedicated Pin	Row	Col	(240-pin)	(208-pin)

I/O	-	4	218	191

I/O	-	4	219	193

I/O	-	4	221	196

I/O	-	4	222	197

I/O	-	4	223	198

I/O	-	4	224	200

I/O	-	4	-	194

I/O	-	4	-	192

I/O	-	4	-	199

I/O	-	4	-	69

I/O	-	4	-	62

I/O	-	5	69	50

I/O	-	5	70	52

I/O	-	5	71	53

I/O	-	5	72	54

I/O	-	5	74	57

I/O	-	5	75	59

I/O	-	5	76	60

I/O	-	5	225	201

I/O	-	5	226	202

I/O	-	5	227	204

I/O	-	5	228	205

I/O	-	5	230	207

I/O	-	5	231	208

I/O	-	5	232	1

QFP	QFP

Function	Dedicated Pin	Row	Col	(240-pin)	(208-pin)

I/O	-	5	233	3

I/O	-	5	-	58

I/O	-	5	-	56

I/O	-	5	-	51

I/O	-	5	-	2

I/O	-	5	-	203

VCC	-	-	4	5

VCC	-	-	15	10

VCC	-	-	24	19

VCC	-	-	35	25

VCC	-	-	44	30

VCC	-	-	55	36

VCC	-	-	64	45

VCC	-	-	73	55

VCC	-	-	86	72

VCC	-	-	101	91

VCC	-	-	116	111

VCC	-	-	117	112

VCC	-	-	136	127

VCC	-	-	137	128

VCC	-	-	156	138

VCC	-	-	157	139

VCC	-	-	176	148

VCC	-	-	177	159

VCC	-	-	192	176

QFP	QFP

Function	Dedicated Pin	Row	Col	(240-pin)	(208-pin)

VCC	-	-	205	195

VCC	-	-	220	-

VCC	-	-	235	-

GND	-	-	5	14

GND	-	-	14	20

GND	-	-	25	24

GND	-	-	34	31

GND	-	-	45	35

GND	-	-	54	41

GND	-	-	65	42

GND	-	-	66	43

GND	-	-	81	44

GND	-	-	96	46

GND	-	-	110	47

GND	-	-	115	66

GND	-	-	126	85

GND	-	-	127	102

GND	-	-	146	110

GND	-	-	147	113

GND	-	-	166	114

GND	-	-	167	115

GND	-	-	186	116

GND	-	-	200	118

GND	-	-	216	121

GND	-	-	229	122

QFP	QFP

Function	Dedicated Pin	Row	Col	(240-pin)	(208-pin)

GND	-	-	-	132

GND	-	-	-	133

GND	-	-	-	143

GND	-	-	-	152

GND	-	-	-	170

GND	-	-	-	189

GND	-	-	-	206

GND	-	-	-	-

GND	-	-	-	-

GND	-	-	-	-

GND	-	-	-	-

GND	-	-	-	-

GND	-	-	-	-

N.C.	-	-	1	6

N.C.	-	-	2	7

N.C.	-	-	3	8

N.C.	-	-	178	9

N.C.	-	-	179	109

N.C.	-	-	180	149

N.C.	-	-	181	150

N.C.	-	-	182	151

N.C.	-	-	183	-

N.C.	-	-	184	-

N.C.	-	-	185	-

N.C.	-	-	236	-

QFP	QFP

Function	Dedicated Pin	Row	Col	(240-pin)	(208-pin)

N.C.	-	-	237	-

N.C.	-	-	238	-

N.C.	-	-	239	-

N.C.	-	-	240	-

N.C.	-	-	-	-

N.C.	-	-	-	-

Recommended reading:

AN42 (Metastability in Altera Devices)

AB144 (Understanding MAX 9000 Timing)

Operating Requirements for Altera Devices Data Sheet


EPM9560 EPLDs

The EPM9560 EPLD, a member of the MAX 9000 family, provides 772 registers and a large number of storage elements for complex circuit applications. The EPM9560 meets the low power and voltage requirements of 3.3-V applications ranging from notebook computers to battery-operated, hand-held equipment.

The EPM9560 is available in 208-pin QFP packages with 149 I/O pins, 240-pin QFP packages with 187 I/O pins, and 280-pin PGA and 304-pin QFP packages with 212 I/O pins. It has 560 logic cells grouped into 35 LABs. These LABs are arranged into 7 rows and 5 columns. Each I/O element contains a bidirectional I/O buffer and an enable flipflop that can be used as either an input or output register. It also contains 4 dedicated fast inputs for synchronous control signals with large fan-outs. When used as outputs, the I/O registers provide fast Clock-to-output times; as inputs, they provide quick setup times. For complete information on EPM9560 devices, refer to the current MAX 9000 Programmable Logic Device Family Data Sheet.

See also:

MAX 9000 EPLD Selection Guide

Recommended reading:

Operating Requirements for Altera Devices Data Sheet

AN42 (Metastability in Altera Devices)

AB144 (Understanding MAX 9000 Timing)

QFP	QFP	QFP	PGA

Function	Dedicated Pin	Row	Col	(304-pin)	(240-pin)	(208-pin)	(280-pin)

Ded. Prog. Pin	VPP (1)	-	-	75	67	48	C4

Ded. JTAG Pin	TMS	-	-	85	68	49	D6

Ded. JTAG Pin	TCLK	-	-	114	91	78	A9

Ded. JTAG Pin	TDI	-	-	115	92	79	C11

Ded. JTAG Pin	TDO	-	-	144	114	108	A18

Input/GCLK1	-	-	266	210	182	V10

Input/GCLK2	-	-	267	211	183	U10

Input/GCLR	-	-	237	187	153	V17

Input/GOE	-	-	296	234	4	W2

I/O	A	-	64	56	37	D1

I/O	A	-	65	57	38	E3

I/O	A	-	66	58	39	C1

I/O	A	-	67	59	40	D2

I/O	A	-	68	60	-	B1

I/O	A	-	69	61	-	D3

I/O	A	-	70	62	-	C3

I/O	A	-	71	63	-	C2

I/O	A	-	158	118	-	C18

I/O	A	-	159	119	-	A19

I/O	A	-	160	120	-	D17

I/O	A	-	161	121	-	B18

I/O	A	-	162	122	117	D18

I/O	A	-	163	123	-	B19

I/O	A	-	164	124	119	E17

QFP	QFP	QFP

Function	Dedicated Pin	Row	Col	(304-pin)	(240-pin)	(208-pin)	PGA

I/O	A	-	165	125	120	C19

I/O	B	-	54	46	32	G2

I/O	B	-	55	47	-	G4

I/O	B	-	56	48	-	F1

I/O	B	-	57	49	33	F3

I/O	B	-	58	50	-	F2

I/O	B	-	59	51	-	F4

I/O	B	-	60	52	-	E1

I/O	B	-	61	53	34	E2

I/O	B	-	168	128	123	F16

I/O	B	-	169	129	-	D19

I/O	B	-	170	130	-	F17

I/O	B	-	171	131	-	E18

I/O	B	-	172	132	124	G16

I/O	B	-	173	133	-	E19

I/O	B	-	174	134	125	G17

I/O	B	-	175	135	126	F18

I/O	C	-	44	36	26	J2

I/O	C	-	45	37	27	J4

I/O	C	-	46	38	28	H1

I/O	C	-	47	39	29	H3

I/O	C	-	48	40	-	H2

I/O	C	-	49	41	-	H4

I/O	C	-	50	42	-	G1

I/O	C	-	51	43	-	G3

QFP	QFP	QFP

Function	Dedicated Pin	Row	Col	(304-pin)	(240-pin)	(208-pin)	PGA

I/O	C	-	178	138	-	H16

I/O	C	-	179	139	-	F19

I/O	C	-	180	140	-	H17

I/O	C	-	181	141	-	G18

I/O	C	-	182	142	129	J16

I/O	C	-	183	143	-	G19

I/O	C	-	184	144	130	J17

I/O	C	-	185	145	131	H18

I/O	D	-	34	26	21	L1

I/O	D	-	35	27	22	L3

I/O	D	-	36	28	-	K2

I/O	D	-	37	29	23	K4

I/O	D	-	38	30	-	K1

I/O	D	-	39	31	-	K3

I/O	D	-	40	32	-	J1

I/O	D	-	41	33	-	J3

I/O	D	-	188	148	-	K16

I/O	D	-	189	149	-	H19

I/O	D	-	190	150	-	K17

I/O	D	-	191	151	-	J18

I/O	D	-	192	152	134	L17

I/O	D	-	193	153	135	J19

I/O	D	-	194	154	136	L16

I/O	D	-	195	155	137	K18

I/O	E	-	24	16	15	N1

QFP	QFP	QFP

Function	Dedicated Pin	Row	Col	(304-pin)	(240-pin)	(208-pin)	PGA

I/O	E	-	25	17	16	N2

I/O	E	-	26	18	17	M2

I/O	E	-	27	19	18	M4

I/O	E	-	28	20	-	M1

I/O	E	-	29	21	-	M3

I/O	E	-	30	22	-	L2

I/O	E	-	31	23	-	L4

I/O	E	-	198	158	-	M17

I/O	E	-	199	159	-	K19

I/O	E	-	200	160	-	M16

I/O	E	-	201	161	-	L19

I/O	E	-	202	162	140	N17

I/O	E	-	203	163	-	L18

I/O	E	-	204	164	141	N16

I/O	E	-	205	165	142	M19

I/O	F	-	14	6	11	T2

I/O	F	-	15	7	12	P3

I/O	F	-	16	8	-	T1

I/O	F	-	17	9	13	P2

I/O	F	-	18	10	-	R1

I/O	F	-	19	11	-	N4

I/O	F	-	20	12	-	P1

I/O	F	-	21	13	-	N3

I/O	F	-	208	168	-	P18

I/O	F	-	209	169	-	M18

QFP	QFP	QFP

Function	Dedicated Pin	Row	Col	(304-pin)	(240-pin)	(208-pin)	PGA

I/O	F	-	210	170	-	P17

I/O	F	-	211	171	-	N19

I/O	F	-	212	172	144	R18

I/O	F	-	213	173	145	N18

I/O	F	-	214	174	146	R17

I/O	F	-	215	175	147	P19

I/O	G	-	4	236	6	V2

I/O	G	-	5	237	7	U3

I/O	G	-	6	238	8	V1

I/O	G	-	7	239	9	T3

I/O	G	-	8	240	-	U2

I/O	G	-	9	1	-	R3

I/O	G	-	10	2	-	U1

I/O	G	-	11	3	-	R2

I/O	G	-	218	178	-	T18

I/O	G	-	219	179	-	R19

I/O	G	-	220	180	-	T17

I/O	G	-	221	181	-	T19

I/O	G	-	222	182	149	U18

I/O	G	-	223	183	-	U19

I/O	G	-	224	184	150	U17

I/O	G	-	225	185	151	V19

I/O	-	1	133	106	97	B15

I/O	-	1	134	-	98	B14

I/O	-	1	135	107	99	C15

QFP	QFP	QFP

Function	Dedicated Pin	Row	Col	(304-pin)	(240-pin)	(208-pin)	PGA

I/O	-	1	136	108	100	A15

I/O	-	1	137	109	101	B16

I/O	-	1	139	-	103	C16

I/O	-	1	140	111	104	A16

I/O	-	1	141	-	105	B17

I/O	-	1	142	112	106	A17

I/O	-	1	143	113	107	C17

I/O	-	1	238	188	154	W19

I/O	-	1	239	-	155	U16

I/O	-	1	240	189	156	V18

I/O	-	1	241	190	157	V16

I/O	-	1	242	191	158	W18

I/O	-	1	244	193	160	W17

I/O	-	1	245	194	161	U15

I/O	-	1	246	-	162	W16

I/O	-	1	247	195	163	V15

I/O	-	1	248	196	164	W15

I/O	-	2	122	97	86	B11

I/O	-	2	123	-	87	C13

I/O	-	2	124	98	88	A12

I/O	-	2	125	99	89	D12

I/O	-	2	126	100	90	B12

I/O	-	2	128	102	92	A13

I/O	-	2	129	103	93	D13

I/O	-	2	130	-	94	B13

QFP	QFP	QFP

Function	Dedicated Pin	Row	Col	(304-pin)	(240-pin)	(208-pin)	PGA

I/O	-	2	131	104	95	C14

I/O	-	2	132	105	96	A14

I/O	-	2	249	197	165	U14

I/O	-	2	250	-	166	W14

I/O	-	2	251	198	167	V14

I/O	-	2	252	-	168	W13

I/O	-	2	253	199	169	T12

I/O	-	2	255	201	171	U13

I/O	-	2	256	202	172	V12

I/O	-	2	257	-	173	V13

I/O	-	2	258	203	174	W12

I/O	-	2	259	204	175	T11

I/O	-	3	109	87	73	B9

I/O	-	3	110	-	74	A7

I/O	-	3	111	88	75	D10

I/O	-	3	112	89	76	A8

I/O	-	3	113	90	77	C10

I/O	-	3	116	-	80	B10

I/O	-	3	117	93	81	D11

I/O	-	3	118	-	82	A10

I/O	-	3	119	94	83	C12

I/O	-	3	120	95	84	A11

I/O	-	3	261	206	177	U12

I/O	-	3	262	-	178	V11

I/O	-	3	263	207	179	T10

QFP	QFP	QFP

Function	Dedicated Pin	Row	Col	(304-pin)	(240-pin)	(208-pin)	PGA

I/O	-	3	264	208	180	W11

I/O	-	3	265	209	181	U11

I/O	-	3	268	212	184	W10

I/O	-	3	269	213	185	U9

I/O	-	3	270	-	186	W9

I/O	-	3	271	214	187	T9

I/O	-	3	272	215	188	V9

I/O	-	4	97	77	61	C7

I/O	-	4	98	-	62	B5

I/O	-	4	99	78	63	B7

I/O	-	4	100	79	64	A4

I/O	-	4	101	80	65	C8

I/O	-	4	103	82	67	D9

I/O	-	4	104	83	68	A5

I/O	-	4	105	-	69	C9

I/O	-	4	106	84	70	A6

I/O	-	4	107	85	71	B8

I/O	-	4	274	217	190	W8

I/O	-	4	275	-	191	V8

I/O	-	4	276	218	192	W7

I/O	-	4	277	-	193	U8

I/O	-	4	278	219	194	W6

I/O	-	4	280	221	196	V6

I/O	-	4	281	222	197	V7

I/O	-	4	282	-	198	W5

QFP	QFP	QFP

Function	Dedicated Pin	Row	Col	(304-pin)	(240-pin)	(208-pin)	PGA

I/O	-	4	283	223	199	T8

I/O	-	4	284	224	200	V5

I/O	-	5	86	69	50	B2

I/O	-	5	87	-	51	C5

I/O	-	5	88	70	52	A1

I/O	-	5	89	71	53	C6

I/O	-	5	90	72	54	B3

I/O	-	5	92	-	56	A2

I/O	-	5	93	74	57	D7

I/O	-	5	94	-	58	B4

I/O	-	5	95	75	59	D8

I/O	-	5	96	76	60	A3

I/O	-	5	285	225	201	U7

I/O	-	5	286	-	202	W4

I/O	-	5	287	226	203	T7

I/O	-	5	288	227	204	V4

I/O	-	5	289	228	205	U6

I/O	-	5	291	230	207	U5

I/O	-	5	292	231	208	W3

I/O	-	5	293	-	1	T6

I/O	-	5	294	232	2	V3

I/O	-	5	295	233	3	U4

VCC	-	-	3	4	5	D14

VCC	-	-	12	15	10	D15

VCC	-	-	23	24	19	E7

QFP	QFP	QFP

Function	Dedicated Pin	Row	Col	(304-pin)	(240-pin)	(208-pin)	PGA

VCC	-	-	32	35	25	E8

VCC	-	-	43	44	30	E9

VCC	-	-	52	55	36	E10

VCC	-	-	63	64	45	E11

VCC	-	-	72	73	55	E12

VCC	-	-	91	86	72	E13

VCC	-	-	108	101	91	E14

VCC	-	-	127	116	111	R6

VCC	-	-	156	117	112	R7

VCC	-	-	157	136	127	R8

VCC	-	-	176	137	128	R9

VCC	-	-	177	156	138	R10

VCC	-	-	196	157	139	R11

VCC	-	-	197	176	148	R12

VCC	-	-	216	177	159	R13

VCC	-	-	217	192	176	R14

VCC	-	-	243	205	195	T13

VCC	-	-	260	220	-	T14

VCC	-	-	279	235	-	T15

GND	-	-	-	5	14	D4

GND	-	-	-	14	20	D5

GND	-	-	-	25	24	D16

GND	-	-	-	34	31	E4

GND	-	-	-	45	35	E5

GND	-	-	-	54	41	E6

QFP	QFP	QFP

Function	Dedicated Pin	Row	Col	(304-pin)	(240-pin)	(208-pin)	PGA

GND	-	-	-	65	42	E15

GND	-	-	-	66	43	E16

GND	-	-	-	81	44	F5

GND	-	-	-	96	46	F15

GND	-	-	-	110	47	G5

GND	-	-	-	115	66	G15

GND	-	-	-	126	85	H5

GND	-	-	13	127	102	H15

GND	-	-	22	146	110	J5

GND	-	-	33	147	113	J15

GND	-	-	42	166	114	K5

GND	-	-	53	167	115	K15

GND	-	-	62	186	116	L5

GND	-	-	73	200	118	L15

GND	-	-	74	216	121	M5

GND	-	-	102	229	122	M15

GND	-	-	121	-	132	N5

GND	-	-	138	-	133	N15

GND	-	-	155	-	143	P4

GND	-	-	166	-	152	P5

GND	-	-	167	-	170	P15

GND	-	-	186	-	189	P16

GND	-	-	187	-	206	R4

GND	-	-	206	-	-	R5

GND	-	-	207	-	-	R15

QFP	QFP	QFP

Function	Dedicated Pin	Row	Col	(304-pin)	(240-pin)	(208-pin)	PGA

GND	-	-	226	-	-	R16

GND	-	-	254	-	-	T4

GND	-	-	273	-	-	T5

GND	-	-	290	-	-	T16

N.C.	-	-	1	-	109	-

N.C.	-	-	2	-	-	-

N.C.	-	-	76	-	-	-

N.C.	-	-	77	-	-	-

N.C.	-	-	78	-	-	-

N.C.	-	-	79	-	-	-

N.C.	-	-	80	-	-	-

N.C.	-	-	81	-	-	-

N.C.	-	-	82	-	-	-

N.C.	-	-	83	-	-	-

N.C.	-	-	84	-	-	-

N.C.	-	-	145	-	-	-

N.C.	-	-	146	-	-	-

N.C.	-	-	147	-	-	-

N.C.	-	-	148	-	-	-

N.C.	-	-	149	-	-	-

N.C.	-	-	150	-	-	-

N.C.	-	-	151	-	-	-

N.C.	-	-	152	-	-	-

N.C.	-	-	153	-	-	-

N.C.	-	-	154	-	-	-

QFP	QFP	QFP

Function	Dedicated Pin	Row	Col	(304-pin)	(240-pin)	(208-pin)	PGA

N.C.	-	-	227	-	-	-

N.C.	-	-	228	-	-	-

N.C.	-	-	229	-	-	-

N.C.	-	-	230	-	-	-

N.C.	-	-	231	-	-	-

N.C.	-	-	232	-	-	-

N.C.	-	-	233	-	-	-

N.C.	-	-	234	-	-	-

N.C.	-	-	235	-	-	-

N.C.	-	-	236	-	-	-

N.C.	-	-	297	-	-	-

N.C.	-	-	298	-	-	-

N.C.	-	-	299	-	-	-

N.C.	-	-	300	-	-	-

N.C.	-	-	301	-	-	-

N.C.	-	-	302	-	-	-

N.C.	-	-	303	-	-	B6

N.C.	-	-	304	-	-	W1


MAX9000 Vpp Note
Note (1):

The VPP pin is used for in-system programming. For devices operating at 5.0-V VCC, the VPP pin should be connected directly to VCC. For devices operating at 3.3-V VCC, VPP must be connected to a 5.0-V power supply during in-system programming. During normal operation, the VPP pin is pulled up internally and can be connected to VCC or left unconnected.


MAX 9000 EPLD Selection Guide

The following table provides information on the MAX 9000 family of general-purpose EPLDs. MAX 9000 EPLDs are suitable for designs that require high performance, high I/O count, and densities of up to 560 macrocells (12,000 gates).

MAX 9000 devices are in-system programmable through a 4-pin JTAG interface. ISP offers quick and efficient iterations during design development and debug cycles. All MAX 9000 devices provide JTAG boundary-scan testing circuitry.

For up-to-date information on device availability, contact Altera Marketing. For more information on the MAX 9000 devices, refer to the Altera Data Book or contact the Altera Literature Department for a copy of the MAX 9000 Programmable Logic Device Family Data Sheet.

EPLD	Package	Temp.	Speed	LCells	Flipflops	Ded.	I/O

Note (1)	Note (2)	Note (3)	Grade	(Reg.)	Inputs

EPM9320	280G	C	-15,-20	320	484	4	164

EPM9320	208R	C	-15,-20	320	484	4	128

EPM9320	84L	C	-15,-20	320	484	4	56

EPM9400	240R	C	-15,-20	400	580	4	155

EPM9400	208R	C	-15,-20	400	580	4	135

EPM9480	240R	C	-15,-20	480	676	4	171

EPM9480	208R	C	-15,-20	480	676	4	142

EPM9560	280G,304R	C	-15,-20	560	772	4	212

EPM9560	240R	C	-15,-20	560	772	4	187

EPM9560	208W	C	-15,-20	560	772	4	149

Recommended reading:

AB60 (Estimating a Design Fit)

AN42 (Metastability in Altera Devices)

AB141 (In-System Programmability in MAX 9000 Devices)

AB144 (Understanding MAX 9000 Timing)

Altera Device Package Outlines Data Sheet

Operating Requirements for Altera Devices Data Sheet

QFP Carrier & Development Socket Data Sheet


EPX740 Devices

The EPX740, a member of the FLASHlogic device family, provides 5,120 SRAM bits, 800 usable gates, and contains SRAM and non-volatile EPROM memory. At power-up, the contents of the EPROM cells are transferred to the corresponding SRAM cells. You can both configure the SRAM and program the EPROM memory of the EPX740.

The EPX740 is available in 44-pin plastic J-lead packages with 30 user I/O pins and 68-pin J-lead packages with 40 user I/O pins. The device has 40 logic cells grouped into 4 LABs. Each LAB can be configured as a 24V10 logic block of 10 logic cells or as a 128 x 10 SRAM block. The SRAM block can be defined with either a bidirectional I/O data bus or with separate input and output data buses. FLASHlogic devices contain built-in JTAG boundary-scan testing, ICR, and ISP support. EPX740 devices contain one JTAG TAP controller. For complete information on EPX740 devices, refer to the FLASHlogic Programmable Logic Device Family Data Sheet in the Altera Data Book.

See also:

FLASHlogic Selection Guide

Recommended reading:

BitBlaster Serial Download Cable Data Sheet

AN45 (Configuring FLASHlogic Devices)


EPX780/EPX880 Devices

The EPX780 and EPX880, members of the FLASHlogic device family, provide 10,240 SRAM bits and 1,600 usable gates. These devices are identical except the EPX780 contains SRAM and EPROM memory while the EPX880 contains SRAM and FLASH memory. At power-up, the contents of the EPROM or FLASH cells are transferred to the corresponding SRAM cells. You can both configure and program the EPX780 and EPX880 devices.

The EPX780 is available in 84-pin plastic J-lead packages with 60 user I/O pins and 132-pin QFP packages with 80 user I/O pins. The EPX880 is available in 132-pin QFP packages with 80 user I/O pins. These devices have 80 logic cells grouped into 8 LABs. Each LAB can be configured as a 24V10 logic block of 10 logic cells or as a 128 x 10 SRAM block. The SRAM block can be defined with either a bidirectional I/O data bus or with separate input and output data buses. FLASHlogic devices contain built-in JTAG boundary-scan testing, ICR, and ISP support. EPX780 and EPX880 devices each contain one JTAG TAP controller. For complete information on EPX780 and EPX880 devices, refer to the FLASHlogic Programmable Logic Device Family Data Sheet in the Altera Data Book.

See also:

FLASHlogic Selection Guide

Recommended reading:

BitBlaster Serial Download Cable Data Sheet

AN45 (Configuring FLASHlogic Devices)


EPX8160 Devices

The EPX8160, a member of the FLASHlogic device family, provides 20,480 SRAM bits, 3,200 usable gates, and contains SRAM and non-volatile FLASH memory. At power-up, the contents of the FLASH cells are transferred to the corresponding SRAM cells. You can both configure and program EPX8160 devices. You can make design changes in one half of the EPX8160 while the other half continues to operate.

The EPX8160 is available in 208-pin QFP packages with 120 user I/O pins. The device has 160 logic cells grouped into 16 LABs. Each LAB can be configured as a 24V10 logic block of 10 logic cells or as a 128 x 10 SRAM block. The SRAM block can be defined with either a bidirectional I/O data bus or with separate input and output data buses. FLASHlogic devices contain built-in JTAG boundary-scan testing, ICR, and ISP support. EPX8160 devices contain two JTAG TAP controllers. For complete information on EPX8160 devices, refer to the FLASHlogic Programmable Logic Device Family Data Sheet in the Altera Data Book.

See also:

FLASHlogic Selection Guide

Recommended reading:

BitBlaster Serial Download Cable Data Sheet

AN45 (Configuring FLASHlogic Devices)


FLASHlogic Selection Guide

The following table provides information on the FLASHlogic device family. FLASHlogic are suitable for prototyping and creating designs that require high performance, high I/O count, and densities of up to 20,480 SRAM bits and 160 logic cells (3,200 gates).

FLASHlogic devices are in-system programmable through a 4-pin JTAG interface. ISP offers quick and efficient iterations during design development and debug cycles. All FLASHlogic devices provide JTAG boundary-scan testing circuitry.

For up-to-date information on device availability, contact Altera Marketing. For more information on the FLASHlogic devices, refer to the Altera Data Book or contact the Altera Literature Department for a copy of the FLASHlogic Programmable Logic Device Family Data Sheet.

FLASHlogic	Package	Temp.	Speed	fCNT 	Macrocells	Ded.	I/O	Clocks	JTAG	VPP	VCC	GND

Note (1)	Note (2)	Note (3)	Grade	(MHz)	(Reg.)	Inputs

EPX740	44L	C	-10	83.3	40	0	30	2	4	1	3	4

EPX740	44L	C	-10Z	80.0	40	0	30	2	4	1	3	4

EPX740	44L	C,I	-12	66.0	40	0	30	2	4	1	3	4

EPX740	44L	C	-15,-15Z	50.0	40	0	30	2	4	1	3	4

EPX740	68L	C	-10,-10Z	83.3	40	10	40	2	4	1	5	6

EPX740	68L	C,I	-12	66.0	40	10	40	2	4	1	5	6

EPX740	68L	C	-15,-15Z	50.0	40	10	40	2	4	1	5	6

EPX780	84L	C	-10	83.3	80	0	60	2	4	1	8	9

EPX780	84L	C	-10Z	80.0	80	0	60	2	4	1	8	9

EPX780	84L	C	-12	66.0	80	0	60	2	4	1	8	9

EPX780	84L	C	-15,-15Z	50.0	80	0	60	2	4	1	8	9

EPX780	132Q	C	-10	83.3	80	22	80	2	4	1	10	13

EPX780	132Q	C	-10Z	80.0	80	22	80	2	4	1	10	13

EPX780	132Q	C,I	-12	66.0	80	22	80	2	4	1	10	13

EPX780	132Q	C	-15,-15Z	50.0	80	22	80	2	4	1	10	13

EPX880	132Q	C	-10	80.0	80	22	80	2	4	1	10	13

EPX880	132Q	C,I	-12	64.5	80	22	80	2	4	1	10	13

EPX8160	208Q	C	-10	80.0	160	48	120	4	4	2	12	18

EPX8160	208Q	C,I	-12	64.5	160	48	120	4	4	2	12	18

Recommended reading:

AN42 (Metastability in Altera Devices)

AN45 (Configuring FLASHlogic Devices)

AB60 (Estimating a Design Fit)

Altera Device Package Outlines Data Sheet

BitBlaster Serial Download Cable Data Sheet

Operating Requirements for Altera Devices Data Sheet


----------------------BEGINNING OF NON-TRANSLATED TEXT--------------------------------------------------

This file contains the following panels:

maxplus2.ini File

<project name>.ini File

maxplus2.idx File

Status Bar

----------------------END OF NON-TRANSLATED TEXT--------------------------------------------------


maxplus2.ini File Description (all applications)
maxplus2.ini File

A software initialization file (with the extension .ini), created during installation, that contains both Altera- and user-specified parameters that control the way MAX+PLUS II applications operate.

The maxplus2.ini file stores essential information for running MAX+PLUS II. For example, this file stores the pathnames of the primitive and macrofunction libraries and the default colors for your application windows. You can set all initialization file parameters from within the MAX+PLUS II software, so you should never edit the maxplus2.ini file.

The maxplus2.ini file can be stored in one of several locations: for a single user with a PC, it is stored in the directory where MAX+PLUS II is installed; on a workstation, it is stored in your home directory. If you use a network copy of MAX+PLUS II, or if a single computer is used by several engineers, you can create a local copy of the maxplus2.ini file and store it in any directory, provided that you have set up the correct variable to point to the local copy of the file.

If you delete this file, you must reinstall MAX+PLUS II.

See also:

Creating & Using a Local Copy of the maxplus2.ini File


maxplus2.idx File Description (all applications)
 maxplus2.idx File

An ASCII text file (with the extension .idx) that maps long filenames, i.e., filenames containing from 9 to 32 characters, to 8-character filenames.

MAX+PLUS II allows you to create files with names containing up to 32 name characters. Since DOS and Windows support only 8-character filenames, MAX+PLUS II automatically creates a maxplus2.idx file in any directory that contains longer filenames. The maxplus2.idx file maps long filenames to their 8-character counterparts. When these 8-character filenames appear in DOS and Windows, they contain a tilde (~) character as the fourth character in the filename.

1.	You should never edit a maxplus2.idx file or delete a filename that contains a tilde (~) as the fourth character in the name.

2.	If you accidentally delete the maxplus2.idx file, you can still open files that contain a tilde character in the filename. However, you may then need to save the file to its previous long filename to re-create the maxplus2.idx file.


Status Bar (all applications)
Status Bar

Displays a brief description of a highlighted menu command or an item in the toolbar. Show me

The status bar is displayed at the bottom of the MAX+PLUS II window. When you point to an item in the toolbar or highlight a menu command with the mouse or with keyboard commands, the status bar displays a brief description of the function of that item.

You can turn the status bar on and off by choosing Show Status Bar.

In the workstation-based version of MAX+PLUS II, the status bar displays the names of assigned nodes and pins in the Floorplan Editor when the mouse pointer passes over a pin, logic cell, I/O cell, or an assignment bin.

See also:

Getting Context-Sensitive Help

Showing the Status Bar

Showing the Toolbar


Status Bar popup
Status Bar


Creating a New File (all applications)
Creating a New File

To create a new file:

1.	Open the New dialog box by choosing New (File menu) or using a shortcut.

2.	Select the type of file to create.

3.	If you selected Graphic Editor file or Waveform Editor file, select the desired filename extension from the drop-down list box.

4.	Choose OK.

or:

Choose Graphic Editor, Symbol Editor, Text Editor, or Waveform Editor from the MAX+PLUS II menu to open an untitled file if that editor does not already have an open window. If the editor is already open, MAX+PLUS II brings the window of the most recently active file to the front.

When you create a new file, it is assumed to be part of the current project, and is assigned to the same device family as the project. After you save the file, you can change its device family if necessary. The device family for a design file is important if you use family-specific macrofunctions in your project.

See also:

Saving a File


Opening a File (all applications)
Opening a File

To open a file:

1.	Open the Open dialog box by choosing Open (File menu) or using a shortcut.

2.	If necessary, select a different drive and/or directory.

3.	Select a file type under Show in Files List.

4.	If necessary, select a different filename extension for Graphic Editor, Text Editor, or Waveform Editor files from the drop-down list box.

5.	Type a name in the File Name box or select a name in the Files box.

6.	Choose OK.

or:

Double-click Button 1 on a filename or file icon in the Hierarchy Display window to open that file. If a filename is followed by more than one icon, the filename is equivalent to the first icon.

or:

1.	Select one or more filenames or file icons in the Hierarchy Display window.

2.	Choose Open Editor (File menu).

or:

Double-click Button 1 on a macrofunction symbol in the Graphic Editor to open the design file that the symbol represents.

or:

Choose the Simulator’s Open SCF button to open the SCF for the current project or the Programmer’s Open SCF button to open the functional testing vectors for the current project.

or:

Choose one of the following commands from the File menu to open a file:

Command:	Action:

Hierarchy Up	Opens the design file that is one hierarchy level higher than the current file (available only in the Graphic, Text, and Waveform Editors). ???shortcut

Hierarchy Down	Opens the design file that is one hierarchy level lower than the current file (available only in the Graphic and Text Editors). You must first select a macrofunction symbol in the Graphic Editor or a design file name in the Text Editor. ???shortcut ???Specify Macrofunction dialog in TED

Hierarchy Top	Opens the design file at the top of the current hierarchy (available only in the Graphic, Text, and Waveform Editors).

Hierarchy Project Top	Opens the design file at the top of the project hierarchy. ???shortcut

or:

Double-click Button 1 on one of the following icons in the Compiler window after compilation to open the specified file or application:

Icon:	Action:

Opens the top-level design file of the project in the appropriate Graphic, Text, or Waveform Editor window.

Opens the Report File in a Text Editor window.

Loads the functional SNF, timing SNF, or linked SNF and opens the Simulator window.

Opens the EDIF Output File in a Text Editor window.

Opens the Verilog Output File in a Text Editor window.

Opens the VHDL Output File in a Text Editor window.

Opens the Verilog Output File plus other output file(s) in multiple Text Editor windows. The other output files are an EDIF Output File and/or a VHDL Output File, depending on the modules that were turned on during compilation.

Opens the VHDL Output File plus other output file(s) in multiple Text Editor windows. The other output files are an EDIF Output File and/or a Verilog Output File, depending on the modules that were turned on during compilation.

Loads the POF and opens the Programmer window.

Loads the POF and opens the Programmer window.

Loads the POF and opens the Programmer window.

Use the built-in hierarchy traversal features in MAX+PLUS II to move between design files for the current hierarchy tree. To open a lower-level file in a hierarchy, open the top-level file and then use the Hierarchy Display window or Hierarchy Down (File menu) to open the lower-level files. If you choose Open or Retrieve (File menu) to open a lower-level file, it is considered to be the top of a different hierarchy tree, and resource, device, and probe assignments that you enter are saved only for that hierarchy, not for the project.

See also:

Guidelines for Working with Assignments

Selecting a File Icon or Name


Navigating the Hierarchy (all applications)
Navigating the Hierarchy

You can move around in the current hierarchy of design files with the following File menu commands:

Command:	Action:

Hierarchy Up	Opens the design file that is one hierarchy level higher than the current file (available only in the Graphic, Text, and Waveform Editors).

Hierarchy Down	Opens the design file that is one hierarchy level lower than the current file (available in the Graphic and Text Editors only). You must first select a macrofunction symbol in the Graphic Editor or a macrofunction name in the Text Editor and choose Hierarchy Down (available only in the Graphic and Text Editors). ???Specify Macrofunction dialog in TED

Hierarchy Top	Opens the design file at the top of the current hierarchy (available only in the Graphic, Text, and Waveform Editors).

Hierarchy Project Top	Opens the design file at the top of the project hierarchy.

or:

Select a filename or file icon in the hierarchy tree shown in the Hierarchy Display window and choose Open Editor or double-click Button 1 on a filename or icon to open the file or bring the file’s window to the front. If a filename is followed by more than one icon, the filename is equivalent to the first icon.

or:

Double-click Button 1 on a filename or icon in the hierarchy tree shown in the Hierarchy Display window.

or:

Double-click Button 1 on a macrofunction symbol in the Graphic Editor.

To move to a file that is already open:

Choose an open file from the Window menu in any MAX+PLUS II application to bring its window to the front.

or:

Choose the Graphic, Symbol, Text, or Waveform Editor name from the MAX+PLUS II menu to bring the most recently active window in that editor to the front.

See also:

Filenames

File Icons

Guidelines for Working with Assignments


Updating the Hierarchy (all applications)
Updating the Hierarchy

You must update the hierarchy if you add a reference to a lower-level design file to a TDF, VHDL Design File, or EDIF Input File in the current hierarchy. Changes made in GDFs and OrCAD Schematic Files are automatically reflected in the Hierarchy Display window.??? (WDFs, ADFs, SMFs, and XNF Files are always the only file in a project or at the bottom of a hierarchy.)

To update the hierarchy:

1.	Open the design file in which you have made changes.

2.	If the design file is not part of the current project, change the project name.

3.	Choose one of the compilation commands from the File menu:

Project Save & Compile

Project Save, Compile & Simulate

Project Save & Check

Create Default Symbol (available only in the Graphic, Text, and Waveform Editors)

Create Default Include File (available only in the Graphic, Text, and Waveform Editors)

or:

Choose Start in the Compiler window.

The Start button and the Project Save & Compile and Project Save, Compile & Simulate commands run a full compilation; Project Save & Check, Create Default Symbol, and Create Default Include File run only the Compiler Netlist Extractor and Database Builder modules.

See also:

Changing the Project Name

Compiling a Project


Changing Colors in MAX+PLUS II (all applications)
Changing Colors in MAX+PLUS II

Altera sets the default colors for the MAX+PLUS II window elements. You can customize the colors with the Color Palette command.

To change the colors of items displayed in MAX+PLUS II applications:

1.	Choose Color Palette (Options menu). The Color Palette dialog box is displayed.

2.	Select one or more items in the Screen Elements box.

3.	Select a color for the item(s) from the MAX+PLUS II Colors box or in the Colors Set With Control Panel box.

Workstation users can customize the colors displayed under Colors Set with Control Panel by editing the win.ini file created by MAX+PLUS II. Go to Appendix B: Additional Workstation Configuration Information in the MAX+PLUS II Getting Started manual for details.

4.	If you wish, choose Preview to see how the color change(s) affect the screen display.

5.	If you wish to reset the colors to the default MAX+PLUS II color scheme, choose Reset.

6.	Choose OK to save the changes.

If your choice of colors would make some objects invisible on screen (e.g., if you choose the same color for Text and Window Background), MAX+PLUS II automatically resets the colors to ensure some contrast. Therefore, the colors displayed may not be exactly the same as the colors you choose.


Closing a MAX+PLUS II Application (all applications)
Closing a MAX+PLUS II Application

To close a MAX+PLUS II application, choose one of the following actions:

Choose Close (File menu) in the Graphic, Symbol, Text, or Waveform Editor.???

or:

Choose Close (Document Control menu).

or:

Double-click Button 1 on the Document Control Menu box.

If you have edited a file, you are asked whether you wish to save the changes. Choose Yes to save the edits or No to discard the edits.

If the current application is running a background process, you are asked if you wish to stop processing. Choose OK to close the application or Cancel to continue processing.

See also:

Closing a File

Exiting from MAX+PLUS II


Entering an Authorization Code (all applications)
Entering an Authorization Code

You must enter an authorization code to use MAX+PLUS II software and to enable all of the features you have purchased. If no authorization code is entered, only the Hierarchy Display, Text Editor, Message Processor, and Programmer are enabled.

If your software guard is labeled HPS, OS, or ES, you do not need to enter an authorization code.

To enter an authorization code:

1.	Follow the hardware and software installation instructions given in the read.me file and in Installation in the MAX+PLUS II Getting Started manual. Be sure to connect the MAX+PLUS II software guard to the parallel printer port on your computer.

2.	Choose Authorization Code (Options menu). The Authorization Code dialog box is displayed.

3.	Type the 24-character authorization code provided by Altera in the Authorization Code box. Type upper- and lowercase letters exactly as they are given (the code is case-sensitive).

4.	Choose Validate to check whether the code is recognized as a valid authorization code. The Expiration Date of the authorization code (if any), and the Enabled Features and Disabled Features that are included in your MAX+PLUS II software package are displayed.

5.	Choose OK to save the new authorization code.

6.	Exit and restart MAX+PLUS II before working with the software.

For assistance with authorization code problems, contact Altera Applications.

See also:

Exiting from MAX+PLUS II


Exiting from MAX+PLUS II (all applications)
Exiting from MAX+PLUS II

To exit from MAX+PLUS II, choose one of the following actions:

Choose Exit MAX+PLUS II from the (File menu).???

or:

Choose Close (Application Control menu).

or:

Double-click Button 1 on the Application Control menu box.

If you have edited one or more files, you are asked whether you wish to save the changes. In each case, choose Yes to save the edits or No to discard the edits.

If MAX+PLUS II is running a background process, you are asked whether you wish to halt processing. Choose OK to exit MAX+PLUS II or Cancel to continue processing.

See also:

Closing a MAX+PLUS II Application


Specifying a User Library (all applications)
Specifying a User Library

User libraries contain Symbol Files and design files for your own macrofunctions, as well as AHDL Include Files. A user library can also contain OrCAD Library Files. When a project is compiled, the Compiler searches directories for the logic represented by a Symbol or Include File in the following order:

Project directory

User library directories

\maxplus2\max2inc and \maxplus2\max2lib directories and their subdirectories

To add a user library:

1.	Choose User Libraries (Options menu). The User Libraries dialog box is displayed.

2.	Choose the directory that contains your user library from the Directories box or type a directory name in the Directory Name box.

3.	Choose Add to add the user library to the Existing Directories box.

4.	If you wish to change the priority of a selected user library in the Existing Directories box, choose Up or Down.

5.	Choose OK to save all changes.

To remove a user library:

1.	Choose User Libraries.

2.	Choose a user library from the Existing Directories box or type a directory name in the Directory Name box.

3.	Choose Delete to remove the user library from the Existing Directories box.

4.	Choose OK to save all changes.


Starting MAX+PLUS II Applications (all applications)
Starting MAX+PLUS II Applications

To start a MAX+PLUS II application:

Choose an application name from the MAX+PLUS II menu. If you choose Graphic Editor, Symbol Editor, Text Editor, or Waveform Editor, MAX+PLUS II opens a new, untitled file in that application or brings the window of the most recently active file to the front. If you choose a different application, the application is opened and data from the current project is loaded. If you choose the Hierarchy Display command, the current hierarchy tree is loaded.

or:

Open an existing file or create a new file to automatically start the appropriate editor.

or:

Double-click Button 1 on a file icon in the Compiler or Hierarchy Display to open the corresponding application and/or file.

See also:

Creating a New File

Opening a File


Switching Between MAX+PLUS II Applications (all applications)
Switching Between MAX+PLUS II Applications

To switch between open windows and applications:

Choose an application name from the MAX+PLUS II menu. If you choose Graphic Editor, Symbol Editor, Text Editor, Waveform Editor, or Message Processor, MAX+PLUS II opens a new untitled window in that application or brings most recently active window to the front. If you choose a different application, the application is opened and, if necessary, data from the current project is loaded. If you choose the Hierarchy Display command, the current hierarchy tree is loaded.

or:

Choose an open application window from the Window menu.

or:

Click Button 1 on an open window to make it active.

or:

Select a filename or file icon in the hierarchy tree shown in the Hierarchy Display window and choose Open Editor (File menu).

or:

Double-click Button 1 on a filename or file icon in the hierarchy tree shown in the Hierarchy Display window to bring the window for that file to the front.

or:

Choose Next (Document Control menu) to switch to the next open window.

The following MAX+PLUS II applications can have multiple open windows (either of the same file or of different files):

Graphic Editor

Text Editor

Waveform Editor

Symbol Editor

Message Processor

If you choose a single-window application from the MAX+PLUS II menu, MAX+PLUS II brings the window to the front. If you choose a multi-window application, MAX+PLUS II brings the most recently active window to the front or opens a new untitled file in that application.


Getting Help on a Message (all applications)
Getting Help on a Message

You can get help on any message shown in the Message Processor window with a click of a button. You can also get help on all messages that pop up when you are using MAX+PLUS II.

To get help on a Message Processor message:

1.	Select the message by clicking Button 1 on it or by clicking the left or right side of the Message button to scroll through the messages.

2.	Choose the Help on Message button.

To get help on a message that pops up when you are using MAX+PLUS II:

Press F1 when the message is displayed.

The MAX+PLUS II Help window is opened or brought to the front and displays information about the likely cause of each message and suggestions for corrective action.

You can also refer to the complete alphabetical list of MAX+PLUS II Messages for message explanations.

See also:

Locating the Source of a Message

MAX+PLUS II Messages

Message Format


Locating the Source of a Message (all applications)
Locating the Source of a Message

You can immediately locate the source of many messages generated by MAX+PLUS II background processes. The Message Processor can locate and highlight each separate source of a selected message in the appropriate design file(s) and/or ancillary file(s), or in the Floorplan Editor. You can also locate all sources of a particular message simultaneously in the Floorplan Editor.

To locate the source(s) of a message one-by-one:

1.	Select the message by clicking Button 1 on it or by clicking the left or right side of the Message button to scroll through the messages.

2.	If you wish to locate source(s) in the Floorplan Editor, turn on the Locate in Floorplan Editor option. Otherwise, messages are located in the appropriate design file(s) and/or ancillary file(s) or, if you are locating a message that occurs during simulation, in the SCF for the project.

3.	Click Button 1 on the right side of the Locate button.

or:

Double-click Button 1 on a message to find the first location of an error or warning. On a PC, MAX+PLUS II automatically opens the appropriate file in a Graphic, Text, or Waveform Editor window; on a workstation, text files are opened in a File Viewer window.

If the Locate in Floorplan Editor option is turned on, MAX+PLUS II automatically opens the Floorplan Editor window.

4.	If the text to the right side of the Locate button indicates that the currently selected error has multiple locations, switch to the Message Processor and click the right side of the Locate button again to find the next location of the error. You can find the previous error location by clicking the left side of the Locate button.

To locate all sources of a message simultaneously in the Floorplan Editor:

1.	Select the message by clicking Button 1 on it or by clicking the left or right side of the Message button to scroll through the messages.

2.	Turn on the Locate in Floorplan Editor option.

3.	Choose the Locate All button. MAX+PLUS II automatically opens the Floorplan Editor window and highlights all sources of the message in the first chip for the project. If the source(s) of a message are located in multiple chips of a multi-device project, one or more message box(es) are displayed in the Floorplan Editor to indicate these additional locations.

4.	To highlight locations in another chip, select a different chip from the Floorplan Editor’s Selected Node(s) & Pin(s) field and choose Locate All again.

See also:

Switching Between MAX+PLUS II Applications


Archiving a Project (all applications)
Archiving a Project

Archiving copies all files that belong to one project into a single archive directory. This process creates a backup copy of the project that ensures that subsequent edits to files in the project directory do not affect the backup files in the archive directory.

To archive the current project:

1.	Choose Project Archive (File menu). The Project Archive dialog box is displayed.

2.	Type a directory name and path in the Archive Directory box or select a drive and/or directory from the Drives and/or Directories boxes. If you type the name of a directory that does not exist, MAX+PLUS II creates it for you before archiving the project.

3.	Choose OK. If an existing file in the archive directory has the same name as one of the project’s files, you are asked if you wish to overwrite the file.

The following files that are part of the current project are copied to the archive directory:

Altera Design File (.adf)	Serial Bitstream File (.sbf)

Assignment & Configuration Output File (.aco)	Simulator Channel File (.scf)

Command File (.cmd)	Simulator Initialization File (.sif)

Compiler Netlist File (.cnf)	Simulator Netlist File (.snf)

Design Library System File (.dls)	SRAM Object File (.sof)

EDIF Input File (.edf)	State Machine File (.smf)

EDIF Command File (.edc)	Symbol File (.sym)

EDIF Output File (.edo)	Table File (.tbl)

Graphic Design File (.gdf)	Tabular Text File (.ttf)

Hexadecimal (Intel-Format) File (.hex)	Text Design Export File (.tdx)

Hierarchy Interconnect File (.hif)	Text Design File (.tdf)

History File (.hst)	Text Design Output File (.tdo)

Include File (.inc)	Timing Analyzer Output File (.tao)

JEDEC File (.jed)	Waveform Design File (.wdf)

Library Mapping File (.lmf)	Vector File (.vec)

Log File (.log)	Verilog Output File (.vo)

OrCAD Schematic File (.sch)	VHDL Design File (.vhd)

OrCAD Library File (.lib)	VHDL Output File (.vho)

Programmer Log File (.plf)	Xilinx Netlist Format File (.xnf)

Programmer Object File (.pof)

The following files are also archived, provided they have the same filename as the current project:

Assignment & Configuration File (.acf)	<Project Name>.ini

Fit File (.fit)	Report File (.rpt)

Fitter Input File (.fin)	Message Text File (.mtf)

MAX+PLUS II Message File (.mmf)	Probe & Resource Assignment File (.prb)


Changing the Project Name (all applications)
Changing the Project Name

A project consists of all related design files and ancillary files generated by MAX+PLUS II and the user. The project name is the same as the filename of a top-level design file or a programming file, without the filename extension. You can also specify a project name before you create a design file for the project. If you specify a project name before you create a design file for the project, the project is assumed to have the same device family as the previous project.

1.	Open or create a file that you wish to designate as the project name, as described in Opening a File or Creating a New File.

2.	While the file is displayed in the current Graphic, Text, or Waveform Editor window, choose Project Set Project to Current File (FIle menu) or use a shortcut.???format ./

or:

1.	Open the Project Name dialog box by choosing Project Name (FIle menu) or using a shortcut.

2.	If you wish to display only the tops of existing hierarchy trees--i.e., for projects that have already been fully or partially compiled--in the Files/Projects box, turn on the Show Only Tops of Hierarchies option. Otherwise, all design files and programming files in the current directory are displayed.

If you change the type but not the filename of the top-level design file in a project--e.g., if you have saved a top-level OrCAD Schematic File as a GDF, or if you have created a top-level TDF to replace a top-level GDF--you must turn this option off to view all different extensions for the file.

3.	If necessary, select a different drive and/or directory.

4.	Type a project name with up to 32 name characters in the Project Name box or select a filename in the Files/Projects box. You do not need to type an extension unless two or more files have the same filename. If you type the name of a subdirectory that does not exist, MAX+PLUS II offers to create if for you.

5.	Choose OK.

or:

Choose one of up to eight project names listed at the bottom of the Project submenu to change the project name to one of the eight most recently edited projects.

You cannot change the project name if MAX+PLUS II is running a background process.

See also:

Changing the File Type


Compiling a Project (all applications)
Compiling a Project

To compile the current project from any MAX+PLUS II application window:

Choose Project Save & Compile (File menu) or use a shortcut.

or:

Choose Project Save, Compile & Simulate (File menu) or use a shortcut.

MAX+PLUS II saves all ???design files in the current project and recompiles all files that have changed since the last compilation.

or:

To compile the current project from the Compiler window:

Choose the Start button in the Compiler window.

If you have made changes to any design files or ancillary files, you are asked if you wish to save the changes before beginning. Unsaved edits are not lost, but are not used in the compilation.

You can also partially compile a project with the Compiler Netlist Extractor and Database Builder by choosing Project Save & Check (File menu).

1.	If the current file is not part of the current project, it is not saved or compiled. Project Save & Compile operates only on the current project.

2.	If you open a lower-level file in the project with Open or Retrieve (File menu), it is considered to be the top of a different hierarchy tree, and edits you enter will not be saved when you compile the project. You must use the Hierarchy Display window or Hierarchy Down (File menu) to open the lower-level files in the hierarchy to ensure that your edits will be saved when you compile the project.

Only one project can be compiled at a time. If MAX+PLUS II is running a background process, the Start button and Project Save & Compile and Project Save, Compile & Simulate commands are not available.

See also:

Changing the File Type

Compiling a Project with Smart Recompile

Starting & Stopping the Compiler

Saving a File

Totally Recompiling a Project


Selecting Text (all applications)
Selecting Text

The following tables show keyboard and mouse methods for selecting text. These functions are the same as for all Windows applications and are provided here for your convenience.

Whole text blocks (comments) in Graphic and Symbol Editor files can be selected as objects with Button 1. See Selecting an Object for information.

When selecting text in dialog boxes with the mouse, use Button 1. In the Graphic, Symbol, and Waveform Editors, use Button 2 to select text in the window. In the Text Editor, you can use either Button 1 or Button 2 to select text in the window.

Mouse/Action:	Result:

Press, Drag, Release	Selects text from the point where the button is pressed, i.e., the insertion point, to the point where the button is released.

Click, Shift+Press+Drag, Release	Selects text from the point where the button is clicked to the point where the button is released.

Click, Move, Shift+Click	Selects text from the point where the button is first clicked to the point where the button is last clicked.

Double-Click 	Selects entire word on which the cursor is positioned.

Double-Click+Drag, Release	Selects text by word boundaries from the point where the button is double-clicked to the point where the button is released.

Key:	Result:

Shift+Right Arrow 	Selects text one character at a time to the right.

Shift+Left Arrow 	Selects text one character at a time to the left.

Shift+End	Selects text to the end of the line, including the end-of-line character.

Shift+Home	Selects text to the beginning of the line.

Ctrl+Shift+Right Arrow 	Selects text to the end of the next word.

Ctrl+Shift+Left Arrow 	Selects text to the beginning of the previous word.

The Text Editor allows you to select one or more entire lines of text by placing the mouse pointer in the left margin of the window.

To select an entire line:

1.	Move the pointer to the left margin of your text file in the Text Editor. The pointer changes to an inverted (i.e., right-pointing rather than left-pointing) arrow.

2.	Click Button 1 or Button 2 next to a line of text to select it.

To select multiple lines:

1.	Repeat step 1 above.

2.	Press Button 1 or Button 2 next to a line of text.

3.	Drag the mouse up or down in the left margin.

4.	Release the mouse button.

The Text Editor also allows you to select a column of text:

1.	Place the insertion point before the character at the top left corner of the column of text to be selected.

2.	Press and hold down the Ctrl key.

3.	Press Button 1 or 2 and drag the mouse until the column is highlighted. (After you press the mouse button, you can release the Ctrl key.)

4.	Release the mouse button.

The column of text is selected. You can now copy, cut, delete, or paste the text column.

1.	If you paste a column of text at the beginning or middle of a text file, the column is inserted into the file at the insertion point and into subsequent lines. Each line of text in the column is pasted into an existing line (if any). Existing text is not moved down to the end of the column.

2.	You cannot use column selection to select multiple items for entering resource assignments.

See also:

Copying, Cutting & Pasting Text

Deleting Text


Creating & Using a Local Copy of the maxplus2.ini File (all applications)
Creating & Using a Local Copy of the maxplus2.ini File

If you use a network copy of MAX+PLUS II, or if a single computer is used by several engineers, you can create a local copy of the maxplus2.ini File. You must then set up an environment variable that specifies the location of the file.

To set up a local copy of the maxplus2.ini file on a PC:

1.	Copy the existing maxplus2.ini file with the DOS Copy command or open the file with the Open command (File menu) and save it to the desired drive and directory with Save As (File menu).

2.	Edit the autoexec.bat file that is used to boot up your computer to include the following line:

set MAXPLUS2_INI=<drive and directory name>

3.	Save the changes to autoexec.bat and reboot your computer.

To set up a local copy of the maxplus2.ini file on a workstation:

Copy the existing maxplus2.ini file to your home directory with workstation commands. If you need to store the maxplus2.ini file in a different location, perform the following additional steps:

a.	If you are running a C shell, add the following line to the .cshrc file in your home directory:

setenv MAXPLUS2_INI <directory name>

b.	Type the following command at the C shell prompt:

source .cshrc

or:

a.	If you are running a Bourne shell, add the following line to the .profile file in your home directory:

set MAXPLUS2_INI=<directory name>

b.	Type the following command at the Bourne shell prompt:

source .profile


Clearing Timing Analysis Tags

You can clear some or all of the tagging that specifies that nodes are timing sources, timing destinations, or cut off (excluded).

To clear all timing analysis tags, including all source, destination, and cutoff node tagging:

In the Graphic, Text, Floorplan, or Waveform Editor, choose Clear All Timing Analysis Tags (Utilities menu).

To clear a particular type of tag:

1.	???Choose Timing Analysis Source, Timing Analysis Destination, or Timing Analysis Cutoff from the Node menu in the Timing Analyzer. The Timing Analysis Source dialog box, Timing Analysis Destination dialog box, or Timing Analysis Cutoff dialog box is displayed.

2.	Choose the Clear button to untag all nodes of the type specified in the dialog box, or select one or more nodes in the Selected Nodes box and choose the left direction button (<=) to move them into the Available Nodes box.

3.	Choose OK to save the changes.

When you remove all user-defined timing analysis source or destination tags, the Timing Analyzer reverts to default timing tagging for sources and destinations.

See also:

Tagging Timing Analysis Cutoff Nodes

Tagging Timing Analysis Source & Destination Nodes


Tagging Timing Analysis Cutoff Nodes

You can exclude a signal path from timing analysis by tagging a node as a cutoff node. When a cutoff node is tagged, only the signal path that leads to the node is included in the analysis. You can also change a source or destination tag on a node to be a cutoff tag.

To tag a timing analysis cutoff node:

1.	In the Graphic, Waveform, or Floorplan Editor, select one or more nodes and/or symbols. In the Text Editor, select a single node or pin name.

2.	Choose Timing Analysis Cutoff (Utilities menu) or use a shortcut???. The cutoff tagging overrides any previous source or destination tagging.

or:

1.	In the Timing Analyzer, open the Timing Analysis Cutoff dialog box by choosing Timing Analysis Cutoff (Node menu) or using a shortcut???.

2.	Type the node name or a text string that includes optional wildcard characters in the Node Name box.

3.	Turn on one or more Type options to specify the type of nodes to be tagged.

4.	If you wish to list all possible hierarchical node names for each node displayed in the Available Nodes list box, turn on Show All Node Name Synonyms. Synonyms are preceded by -> in the list.

5.	Choose List to list all nodes that match the name or text string in the Available Nodes box.

6.	Select one or more node names in the Available Nodes box.

7.	Choose the right direction button (=>) to move the selected nodes to the Selected Nodes box. This box also lists all cutoff nodes tagged in the Graphic, Text, Floorplan, and Waveform Editors. You can also double-click Button 1 on a single node name to move it into the Selected Nodes box.

8.	Choose OK.

See also:

Assigning Individual Timing Requirements

Choosing an Analysis Mode

Clearing Timing Analysis Tags

Cutting Off I/O Pin Feedback

Running a Timing Analysis

Tagging Timing Analysis Source & Destination Nodes


Tagging Timing Analysis Source & Destination Nodes

The Timing Analyzer provides default timing tagging for source and destination nodes for each analysis mode. As an alternative, you can tag specific nodes in the project as timing analysis source and destination nodes. Each node can be both a source and a destination. You can also change a source or destination tag on a node to be a cutoff tag.

To tag a timing analysis source or destination node, and thereby cancel all default timing tagging:

1.	In the Graphic, Waveform, or Floorplan Editor, select one or more nodes, pins, and/or symbols. In the Text Editor, select a single node or pin name.

2.	Choose Timing Analysis Source or Timing Analysis Destination (Utilities menu).

All default source or destination tagging is removed and only the selected items are tagged. The source or destination tagging overrides any previous cutoff tagging. If you selected a flipflop in the Graphic Editor, its Q output becomes a source or its data input becomes a destination.

or:

1.	In the Timing Analyzer, open the Timing Analysis Source dialog box or Timing Analysis Destination dialog box in one of the following ways:

Choose Timing Analysis Source (Node menu) or use a shortcut???

Choose Timing Analysis Destination (Node menu) or use a shortcut???

2.	(Optional) The * wildcard character in the Node Name box and the current Type options represent the default tagging. Although default source or destination tagging is removed when other sources or destinations are tagged, you can retain some or all default tags by choosing List and skipping to step 6.

3.	Type a node name or a text string that includes optional wildcard characters in the Node Name box.

4.	Turn on one or more Type options to specify the type of nodes to be tagged.

5.	If you wish to list all possible hierarchical node names for each node displayed in the Available Nodes list box, turn on Show All Node Name Synonyms. Synonyms are preceded by -> in the list.

6.	Choose List to list all nodes that match the name or text string and the Type options in the Available Nodes box.

7.	Select one or more node names in the Available Nodes box.

8.	Choose the right direction button (=>) to move the selected nodes to the Selected Nodes box. This box also lists all source or destination nodes tagged in the Graphic, Floorplan, Text, and Waveform Editors. You can also double-click Button 1 on a single node name to move it into the Selected Nodes box.

9.	Repeat steps 3 through 8 as necessary to tag additional nodes.

10.	Choose OK. If the current analysis mode is Delay Matrix or Setup/Hold Matrix, nodes that have been tagged now appear in the matrix.

See also:

Assigning Individual Timing Requirements

Choosing an Analysis Mode

Clearing Timing Analysis Tags

Cutting Off I/O Pin Feedback

Running a Timing Analysis

Tagging Timing Analysis Cutoff Nodes


Running a Timing Analysis

You can run the Timing Analyzer in its current analysis mode from the Timing Analyzer, or from the Graphic, Text, or Waveform Editor.

The steps in the following procedure summarize the actions needed to run a successful timing analysis.

To run the Timing Analyzer:

1.	Create a timing SNF for the project or a linked SNF that contains timing information only.

2.	Tag source and destination nodes for the analysis as described in Tagging Timing Analysis Source & Destination Nodes. If you do not tag any nodes, the Timing Analyzer provides default timing tagging.

3.	If you wish to reduce the number of delay paths analyzed, use one or more of the following methods:

Tag nodes to be cut off, as described in Tagging Timing Analysis Cutoff Nodes.

Turn on Cut Off I/O Pin Feedback (Options menu) to cut off the delay that is fed back from bidirectional (BIDIR or BIDIRC) pins.

Turn on Cut Off Clear & Preset Paths (Options menu)  to cut off the timing paths for all Clear and Preset signals in the project.

4.	Specify time restrictions, i.e., the minimum and maximum propagation delays that you wish to include in the analysis, as described in Specifying Time Restrictions. By default, all delays are included.

5.	Choose a timing analysis mode as described in Choosing an Analysis Mode.

6.	Choose the Start button in the Timing Analyzer window, or choose the Analyze Timing command in the Graphic, Text, Waveform, or Floorplan Editor.

See also:

Assigning Individual Timing Requirements

Clearing Timing Analysis Tags

Combining Multiple Projects for Simulation

Creating a Timing Simulator Netlist File

Cutting Off Clear & Preset Timing Paths

Cutting Off I/O Pin Feedback


Setting MAX+PLUS II Preferences (all applications)
Setting MAX+PLUS II Preferences

You can display the toolbar for quick access to frequently used commands, or hide the toolbar to increase the size of your work area.???

You can display the status bar to see short descriptions of menu commands and items in the toolbar, or hide the status bar to increase the size of your work area. Pointing to an item in the toolbar or to a menu command displays information on that item in the status bar.???

To show or hide the toolbar:

Choose Preferences (Options menu)

In some MAX+PLUS II applications, not all toolbar buttons and list boxes on the standard toolbar are visible if you run MAX+PLUS II with your computer screen in VGA mode: some items are "beyond" the right-hand edge of the screen. In higher-resolution screen modes (e.g., SuperVGA), all toolbar items are visible.

MAX+PLUS II provides an alternate toolbar, which contains the most useful subset of Graphic and Symbol Editor toolbar buttons, that can be used on VGA screens. To switch between the standard and alternate toolbars:

1.	Exit from MAX+PLUS II.

2.	From a DOS prompt, make a backup copy of the file maxplus2.tlm that exists in the MAX+PLUS II system directory. This file contains the standard arrangement of toolbar buttons.

3.	In the MAX+PLUS II system directory, copy the file 640x480.tlm to the name maxplus2.tlm.

4.	Restart MAX+PLUS II. If you wish to return to the standard arrangement of toolbar buttons, you can overwrite the 640x480.tlm file with your backup copy of the maxplus2.tlm file.

See also:

Getting Context-Sensitive Help


Closing a File

When you close a window, you have not necessarily closed a file. You must close all open windows to close the file. You can find out how many windows are open onto a file by checking the bottom of the Window menu or by examining the file icons displayed in the Hierarchy Display.

To close the current active window in any MAX+PLUS II editor:

Choose Close from the File or Document Control menu or double-click Button 1 on the Document Control Menu box.???

or:

1.	Select one or more filenames or file icons in the Hierarchy Display window. You may use area or object-by-object selection.

2.	Choose Close Editor (File menu) or use a shortcut.???

See also:

Selecting a File Icon or Name


Partitioning a Project

Large projects that cannot fit into one device can be partitioned into two or more devices of the same device family. The Partitioner divides a project into multiple devices automatically or according to your specifications. You can guide partitioning by making resource and device assignments and inserting primitives, reviewing the results of partitioning, and then adjusting or saving the partitioned project. The following procedures describe project partitioning:

Automatic Partitioning

Guiding the Partitioner

Viewing the Results of Partitioning

See also:

Assigning Connected Pins

Fitting & Refitting a Project

Guidelines for Working with Assignments

Connected Pin Assignments Section (ACF)

Recommended reading:

AB93 (Partitioning a Project with MAX+PLUS II Software)


Automatic Partitioning

Automatic partitioning is the simplest way to partition a project. If you do not make any chip assignments, the Compiler automatically partitions a project. Automatic partitioning can also occur if your project does not fit into a single device or if you specify AUTO as the device for the project.

The simplest way to partition a project consists of four steps:

1.	Choose a device family for the project with the Device command (Assign menu).

2.	Specify AUTO as the device with the Device command.

3.	If you wish to restrict the range of devices that the Compiler uses for automatic partitioning, use the Auto Device Selection dialog box to specify the range of devices, as described in Specifying Devices for Automatic Device Selection.

4	Compile the project.

The Partitioner chooses the device(s) from the specified device family and fits the project into them.

As an alternative to using the Device and Auto Device Selection dialog boxes, you can specify AUTO devices and select the range of devices for the Compiler to use for automatic partitioning with the Physical Chip Assignments Section and the Auto Device Choices Section, respectively, of the project’s ACF.

See also:

Assigning a Device

Compiling a Project

Fitting & Refitting a Project

Guiding the Partitioner

Viewing the Results of Partitioning

Recommended reading:

AB93 (Partitioning a Project with MAX+PLUS II Software)


Guiding the Partitioner

You can direct the Partitioner to divide the project according to your specifications by making resource and device assignments. You can specify resource and device assignments that affect partitioning with the Clique, Pin/Location/Chip, and Device commands, or in the Assignment & Configuration File (.acf) for the project.

To guide the Partitioner, use one or more of the following assignments and primitive insertion techniques:

Assignment:	Action:

Pin or Location + Chip	Assign nodes in a project to particular pins, logic cells, I/O cells, LABs, rows, or columns in one or more chips.

Chip	Assign multiple nodes to a chip to specify a block of logic functions to be placed in the same device. You can also make chip assignments on individual macrofunctions that you wish to implement in separate devices.

Clique	Make clique assignments to specify a block of logic functions to be placed together. You can specify a LAB, row, or chip clique, or a "best possible" clique that ensures that the Compiler attempts to fit all clique members into the smallest area possible. After compilation, you can check the Clique Assignments Section in the Report File to find out whether all members of a "best possible" clique were placed into the same LAB. Clique assignments allow you to split a project so that only a minimum number of signals travel between LABs, rows, or devices, and to ensure that there are no unnecessary delays on critical timing paths.

Clique + Pin or Location	Assign one member of a clique to a specific chip, LAB, column, or row, or to a specific pin, logic cell, or I/O cell within a chip. This type of assignment effectively assigns the entire clique to a chip, LAB, column, or row.

Device	Map the logic blocks you have previously defined with chip assignments to specific devices. If any logic blocks remain unassigned, the Partitioner will place them automatically.

Primitive:	Action:

LCELL 	In a multi-device project, if the outputs of a particular chip are combinatorial outputs, logic synthesis places them in the device that the outputs feed. You can force such outputs to remain in the assigned "source" chip if you feed the combinatorial logic outputs to LCELL buffers and assign the LCELL to the chip or to a pin or lgoic cell within the chip.

INPUTC, OUTPUTC &

BIDIRC	If you wish to implement individual macrofunctions to separate chips, you can use external connection pin primitives or the ACF Connected Pins Assignments Section to tie the macrofunction inputs and outputs together and specify which pins are connected together on your board. If you use external connection pin primitives, you must also assign each primitive to the appropriate chip. This technique is only needed in addition to the chip assignments if the macrofunctions have combinatorial outputs that would otherwise be placed in a different device by logic synthesis. In these cases, the external connection pin primitives can be used as an alternative to placing LCELL buffers on the combinatorial macrofunction outputs.

SOFT 	If a project compilation indicates that logic is too complex, or the Report File shows that the Logic Synthesizer needed to create a large number of synthesized logic cells, you can try inserting SOFT or LCELL buffers on the outputs of combinatorial logic functions. The Logic Synthesizer evaluates whether an LCELL buffer will help to implement the project, and chooses when to replace instances of SOFT primitive with LCELL primitives. For example, if logic is minimized so that a SOFT buffer is fed by a single input, the Logic Synthesizer removes the SOFT buffer.

See also:

Assigning a Clique

Assigning a Device

Assigning a Pin, Location, or Chip

Automatic Partitioning

Fitting & Refitting a Project

Guidelines for Working with Assignments

Implementing LCELL & SOFT Primitives (AHDL)

Viewing the Results of Partitioning

Recommended reading:

AB93 (Partitioning a Project with MAX+PLUS II Software)


Viewing the Results of Partitioning

To view the results of partitioning:

Open the Floorplan Editor and choose Last Compilation Floorplan (Layout menu) or use a shortcut??? The Compiler’s resource assignments can be viewed in both the Device View and LAB View for each chip. If you back-annotate the project with Back-Annotate Project (Assign menu) and choose Current Assignments Floorplan (Layout menu), you can then edit the assignments in the Floorplan Editor window. In addition, if your project contains Graphic Editor files, you can also turn on Show All Assignments (Options menu) to show all back-annotated pin, logic cell, and chip assignments in the current Graphic Editor file.

or:

Open the Report File for the project, which shows how the project is implemented in one or more devices. You can use the Compiler’s Report File Settings command (Processing menu) to include or exclude the following information: user resource and probe assignments, pin connections, file hierarchy, logic cell interconnections, and minimized equations.

or:

Open the Fit File for the project, which records all chip, device, pin, and buried logic cell assignments made by the Compiler’s Fitter module. User assignments are also shown and contrasted with Compiler assignments.

See also:

Automatic Partitioning

Back-Annotating Assignments for a Project

Fitting & Refitting a Project

Guiding the Partitioner

Opening a File

Recommended reading:

AB93 (Partitioning a Project with MAX+PLUS II Software)


Renaming a Megafunction or Macrofunction in the Current Project
Renaming a Macrofunction in the Current Project

You can rename any megafunction or macrofunction in a project to suit your needs. You should also rename any family-specific functions that appear in a super-project used for multi-project simulation. Since the sub-projects in a super-project can be targeted for different device families, the mega- and macrofunctions in each individual project must have unique names for correct error location, archiving, and hierarchy traversal.

To rename a mega- or macrofunction in the current project:

1.	In the Hierarchy Display window, select the file icon that represents the function to be renamed and choose Open Editor use a shortcut???stopped here

2.	Choose Save As (File menu) or use a shortcut to save the function to a different name in the project directory.

You should never save renamed mega- or macrofunctions to the MAX+PLUS II-provided directories of logic functions, i.e., the subdirectories of the \maxplus2\max2lib directory: these files may be erased when you install a newer version of MAX+PLUS II.

3.	Choose Create Default Symbol (File menu) to update the Symbol File that represents the current file.

or:

Choose Create Default Include File (File menu) to update the Include File that represents the current file.

4.	Repeat step 1 to open the higher-level design file that contains the renamed symbol or name (i.e., instance) and delete the original symbol or name for the function.

5.	Enter the symbol for the renamed function or type in the new name for the function.

6.	Choose Project Save & Check (File menu) or use a shortcut to update the hierarchy tree.

See also:

Combining Multiple Projects for Simulation

Compiling a Project

Creating a Default Include File

Creating the Default Symbol for a File

Entering a Symbol (Graphic Editor)

Navigating the Hierarchy

Opening a File

Saving a File

Updating the Hierarchy


Combining Multiple Projects for Simulation

You can create a super-project consisting of a top-level design file that contains symbols or instances representing multiple individual sub-projects. You can then compile the super-project to create a linked SNF for simulation and timing analysis.

A super-project allows you to combine projects implemented in different device families and to incorporate functional information that represents logic that is not implemented in an Altera device.

A linked SNF generated from a super-project combines the information in each sub-project’s SNF, i.e., data from functional, timing, and linked SNFs. You can use the linked SNF to perform a board-level simulation. If the linked SNF contains timing information only, you can also use it to run a timing analysis.

You can create a super-project as a "bottom-up" design that combines existing projects, or as a "top-down" design that consists of an entirely new super-project created from "scratch." If you use existing projects, you may want to archive each individual project to preserve a backup copy before creating the super-project.

To combine existing projects into a super-project ("bottom-up" design) and generate a linked SNF:

1.	Rename any family-specific macrofunctions used in the projects you intend to combine, as described in Renaming a Macrofunction in the Current Project. The macrofunctions must have unique names for correct error location, archiving, and hierarchy traversal.

2.	Recompile each sub-project with Total Recompile and Functional SNF Extractor, Timing SNF Extractor, or Linked SNF Extractor (Processing menu) turned on.

3.	Copy all sub-project files to a single super-project directory with Project Archive (File menu).

4.	In the super-project directory, create a super-project design file containing symbols or instances that represent the individual sub-projects. The super-project design file must follow the guidelines in File Structure Requirements for Multi-Project Simulation.

5.	In the Compiler, turn on Linked SNF Extractor (Processing menu). The Linked SNF Extractor module box appears in the window.

6.	To begin compilation, choose the Start button in the Compiler window or the Project Save & Compile command (File menu) in any MAX+PLUS II application. The Compiler creates a linked SNF only if the project compiles successfully.

If you make changes to an individual sub-project, recompile it, and generate a new SNF, you must rearchive the sub-project to the super-project directory, and then recompile the super-project to update the linked SNF.

To create an entirely new super-project ("top-down" design) and generate a linked SNF:

1.	Create a top-level super-project design file in a super-project directory, according to the guidelines in File Structure Requirements for Multi-Project Simulation. The symbols or instances in this top-level design file represent the logic you intend to create.

2.	Create the sub-projects in the super-project directory.

3.	Repeat steps 1, 2, 5, and 6 above.

See also:

Archiving a Project

Creating a Functional Simulator Netlist File (Compiler)

Creating a Timing Simulator Netlist File (Compiler)

Compiling a Project

Linked Simulation Mode (Simulator)

Running an Interactive-Mode Simulation (Simulator)

Simulator Netlist File (.snf)

Totally Recompiling a Project (Compiler)


name characters glossary definition
name characters

The characters A to Z, a to z, 0 to 9, slash (/), dash (-), and underscore (_) are legal for MAX+PLUS II breakpoint, chip, clique, file, group (bus), node, parameter, pin, pinstub, probe, logic synthesis style, and quoted and unquoted symbolic names, with the exceptions listed below. Case is not significant.

Item:	Name Character Exception:

filename	No slash (/) is permitted. Case is significant on UNIX workstations.

single-range group (bus) name	No slash (/) is permitted. The name is followed by a range of numbers or arithmetic expressions in brackets. The start and end of the range are separated by two periods. For example, group a[3..1] consists of the nodes a3, a2, and a1. In Graphic Editor files only, sequential bus names can also include a series of single-range bus names. For example, a[8..0],dout[6..4].

dual-range group (bus) name	Same as single-range group names, with two ranges of numbers or arithmetic expressions in brackets. For example, a[6..3][4..0].

sequential group (bus) name	The name consists of a series of comma-separated node names enclosed in parentheses. For example, group (a, b, c) consists of the nodes a, b, and c. In Graphic Editor files, parentheses are not used.

unquoted symbolic name (AHDL)	No dash (-) is permitted. Names cannot consist entirely of digits. AHDL keywords cannot be used.

VHDL names	No slash (/) or dash (-) is permitted. The name must start with a letter, cannot end with an underscore (_), and cannot contain two underscores (_ _) in a row. VHDL keywords cannot be used.

ACF names	Names that contain slash (/), dash (-), vertical bar (|), colon (:), and/or period (.) characters must be enclosed in double quotation marks (").


nesting glossary definition
nesting

The repetition of an element or statement within an AHDL statement, e.g., an If Statement within an If Statement.


network glossary definition
network

A group of interconnected node and/or bus lines, including nodes or buses that are connected by name only.


nil-period oscillation glossary definition
nil-period oscillation

Oscillation that occurs when an input vector is applied in functional simulation, but the propagation of signals through combinatorial logic causes an infinite number of logic level changes to occur on a buried or output node at the same time.


nil-time glitch glossary definition
nil-time glitch

A glitch that occurs when an input vector is applied in functional simulation, and the propagation of signals through combinatorial logic causes two or more logic level changes to occur on a buried or output node at the same time.


node glossary definition
node

A node represents a wire carrying a signal that travels between different logical components of a design file.

In the Graphic Editor files, nodes are represented as lines; in text files, they are symbolic names; in Waveform Editor files, they are waveforms.


Node Database File (.ndb) glossary definition
Node Database File (.ndb)

A file that contains the database of project node names, which supports resource and probe assignment edits with Assign menu commands and the Floorplan Editor. The Compiler Netlist Extractor and Database Builder modules of the Compiler generate a Node Database File for a project during project processing.

If you accidentally delete this file, you must recompile the project before you can use most Assign menu commands and Floorplan Editor functions. In addition, only pins are visible in the Floorplan Editor if a Node Database File is created with the Project Save & Check command (File menu): a full compilation is required to make buried nodes visible in the Floorplan Editor.


node/group information area glossary definition
node/group information area

Anywhere to the left of an actual waveform in a Waveform Editor file, i.e., the Name, Type, or Value field, as well as the column in which node and group handles are displayed.


node name glossary definition
node name

The name given to a signal in a design file. A node name can contain up to 32 of the following name characters: A to Z, a to z, 0 to 9, slash (/), dash (-), and underscore (_). Hierarchical node names can contain 128 characters, including vertical bar (|), colon (:), and period (.). Case is not significant.

Some restrictions apply to names in VHDL Design Files (.vhd) and unquoted port and symbolic names in AHDL Text Design Files (.tdf).


node type glossary definition
node type

The type of logic that drives a node or group in a Waveform Design File (.wdf) or Vector File (.vec). Four logic types are defined:

Type:	Meaning:

INPUT	Node or group is driven by an input pin.

COMB	Node or group is fed by combinatorial logic, e.g., an AND gate.

REG	Node or group is fed by a register (implemented with a logic cell on the device).

MACH	Node is fed by a state machine.


Normal logic synthesis style glossary definition
Normal logic synthesis style

The Altera-provided style that directs the Logic Synthesizer to optimize your project for minimum silicon resource usage.

The Normal style attempts to use device resources as efficiently as possible, without adding excessive timing delays.


NOT Gate Push-Back option glossary definition
NOT Gate Push-Back option

An advanced logic synthesis option that allows the Compiler’s Logic Synthesizer module to push an inversion (i.e., a NOT gate) back though a register and implement it on that register’s D input at advantageous locations in the project. When NOT Gate Push-Back is used, a register will power up to an active-high state, so it may need to be explicitly cleared during initial operation of the device.

ACF logic option syntax:

<name>: NOT_GATE_PUSH_BACK = (ON|OFF|DEFAULT|NULL)


NTSC glossary definition
NTSC

National Television System Committee. MAX+PLUS II provides an NTSC megafunction that produces a video control signal for complex pattern generation.


object glossary definition
object

Any symbol, other graphic, or block of free-floating text (i.e., a comment) that can be selected with Button 1.


object-by-object selection glossary definition
object-by-object selection

The process of selecting multiple non-contiguous objects. The first object is selected by clicking Button 1 on it. You can add or remove objects to the selection by pressing Shift while clicking on them with Button 1.

In the Graphic Editor, object-by-object selection can be used to select graphics and/or text blocks; in the Waveform Editor, to select nodes and groups; in the Floorplan Editor, to select pins, nodes, logic cells, or assignment bins; and in the Hierarchy Display, to select file icons.

In the Graphic Editor, multiple objects in a rectangular area can be selected and added to an existing selection by pressing Shift while dragging Button 1.


octal glossary definition
octal

The base 8 number system (radix). Octal digits are 0 though 7.

In AHDL, octal numbers are indicated with the following notation:

O"<series of digits 0 to 7>" or

Q"<series of digits 0 to 7>"

Example: Q"4671223"

In VHDL, octal numbers are indicated with the following notation:

8#<series of digits 0 to 7>#

Example: 8#4671223#


one-hot encoding glossary definition
one-hot encoding

A type of binary coding in which one and only one bit of a value is set to 1. For example, the four legal values 0001, 0010, 0100, and 1000 together comprise a "one-hot" code sample because in each of these four values a single bit is set to 1.

You can manually implement one-hot encoding. In addition, the Global Project Logic Synthesis command (Assign menu) includes a One-Hot State Machine Encoding option to allow the Compiler to automatically implement one-hot encoding for the entire project. Altera strongly recommends using the One-Hot State Machine Encoding option rather than manual one-hot encoding to implement one-hot encoding.

ACF global project option syntax:

ONE_HOT_STATE_MACHINE_ENCODING = (ON|OFF)


one's complement glossary definition
one’s complement

A system of representing binary numbers in which the negative of a number is obtained by inverting each bit individually.


operand glossary definition
operand

A node, group, or number that is acted upon in an operation.


operator glossary definition
operator

A symbol that signifies the action of an operation. AHDL and VHDL offer both logical and arithmetic operators.


Optimize option glossary definition
Optimize option

A logic synthesis option that directs the Compiler’s Logic Synthesizer module to choose the relative priority of optimizing speed (i.e., timing delays) and area (i.e., physical resource usage). The Optimize option can be set to 0 to minimize area, to 10 to maximize speed, or to a setting in between to adjust the speed/area tradeoff.

ACF logic option syntax:

<node>: OPTIMIZE_FOR_SPEED = (0-10)


OrCAD Library File (.lib) glossary definition
OrCAD Library File (.lib)

A binary file (with the extension .lib) containing information that describes how symbols are displayed in OrCAD Schematic Files (.sch).

The MAX+PLUS II Graphic Editor uses an OrCAD-generated OrCAD Library File to import an OrCAD Schematic File. The OrCAD Library File for each OrCAD Schematic File should contain all libraries for the OrCAD symbols used in the schematic. This OrCAD Library File must also be copied to same directory as the OrCAD Schematic File.


OrCAD Schematic File (.sch) glossary definition
OrCAD Schematic File (.sch)

A schematic design file (with the extension .sch) created with the OrCAD Draft schematic editor. You can open and edit an OrCAD Schematic File in MAX+PLUS II and save it as both a Graphic Design File (.gdf) and an OrCAD Schematic File (.sch). An OrCAD Schematic File can also be compiled directly by the MAX+PLUS II Compiler.


oscillation glossary definition
oscillation

An unstable logic level on a signal. When the Simulator is in timing or linked simulation mode, you can specify the time period that constitutes an oscillation and monitor the project for signals that do not stabilize within the defined period. When the Simulator is in functional simulation mode, you can monitor the project for nil-period oscillation only.


Output Enable glossary definition
Output Enable

A high logic level on the Output Enable signal enables the output.

In MAX 7000 devices (not including MAX 7000E devices), the signal from the active-low global Output Enable pin must be inverted and connected to the active-high Output Enable input of the TRI primitive. In all other device families, either active-high or active-low polarity can be used.

In MAX 9000 devices, the Fitter automatically inserts additional LCELL primitives to provide the correct polarity for a non-global Output Enable pin or an Output Enable signal driven by a logic cell.


package glossary definition
package

A collection of commonly used VHDL constructs that can be shared by more than one design unit, i.e., by multiple Entity Declarations, Architecture Declarations, Configuration Declarations, and Package Declarations. Packages consist of a Package Declaration and an optional Package Body (see Section 2.5: Package Declarations in the IEEE Standard VHDL Language Reference Manual for more information).

Packages are stored in design libraries. MAX+PLUS II provides the maxplus2 package in the altera library, which is located in the \maxplus2\max2vhdl directory. (On a UNIX workstation, the maxplus2 directory is a subdirectory of the /usr directory.)


Parallel Expanders glossary definition
Parallel Expanders

An expander product term that is "borrowed" from an adjacent logic cell in the same MAX 7000 or MAX 9000 Logic Array Block (LAB).

Parallel Expanders is also a logic option that you can apply to a logic function to allow it to borrow such parallel expanders. This option can reduce the number of shared expander product terms required in your project and increase the speed of your project. However, the project may use additional logic cells, and may be more difficult to fit.

ACF logic option syntax:

<name>: PARALLEL_EXPANDERS = (ON|OFF|DEFAULT|NULL)


parameter value search order glossary definition
{glos.bmp}parameter value search order

When a project is compiled, the Compiler searches for parameter values in the following order:

1.	As part of the instance of the logic function. For example, in a TDF, in an instance that is created in an Instance Declaration or an in-line reference, you can declare which parameters are used and optionally assign their values. In a GDF, you can select a symbol and use the Edit Ports/Parameters command (Symbol menu) to assign parameter values for that instance.

2.	As part of the instance of the logic function at the next higher hierarchy level. The parameter values for an instance of a logic function apply to the subdesigns of that logic function if the subdesign instances do not have assigned parameter values.

3.	In the global project default parameter values specified with the Global Project Parameters command (Assign menu). These values are stored in the ACF for the project.

4.	In the optional default value listed in the Parameters Statement(s) of the TDF or the PARAM primitives of the GDF that defines the logic function. These default values apply only to the file in which they are listed, they are not applied the file’s subdesigns.


parameterized module glossary definition
parameterized module

A logic function that uses parameters to achieve scalability, adaptability, and efficient silicon implementation. MAX+PLUS II supports a variety of parameterized modules (also called "parameterized functions"), including functions belonging to the Library of Parameterized Modules (LPM).

LPM functions provide architecture-independent design entry for all MAX+PLUS II-supported devices. The MAX+PLUS II Compiler includes built-in compilation support for LPM functions used in schematic, AHDL, and EDIF input files.


part glossary definition
part

A schematic symbol that is described in an OrCAD Library File. A part can represent either a primitive or macrofunction. MAX+PLUS II treats all OrCAD parts as symbols.


Partitioner glossary definition
Partitioner

The Compiler module that divides a project into multiple devices, minimizing the number of connections between devices.


Passive Parallel Asynchronous (PPA) glossary definition
Passive Parallel Asynchronous (PPA)

A configuration scheme in which an external controller, e.g., a CPU, loads the design data into a FLEX 8000 or FLEX 10K device via a common data bus. In this scheme, the device accepts a parallel byte of input data. Intelligent handshaking between the external controller and the device allows the external controller to configure the device.

The MAX+PLUS II Compiler automatically generates Tabular Text Files (.ttf) and Hexadecimal (Intel-format) Files (.hex) that contain the data for configuring a FLEX 8000 or FLEX 10K device in a PPA configuration scheme.


Passive Parallel Synchronous (PPS) glossary definition
Passive Parallel Synchronous (PPS)

A configuration scheme in which an external controller, e.g., a CPU, loads the design data into a FLEX 8000 or FLEX 10K device via a common data bus. Data is latched by the device on the first rising edge of a CPU-driven Clock signal. The next 8 falling Clock edges serialize this latched data within the device. The device latches the next 8-bit byte of data on every eighth rising edge of the Clock signal until the device is completely configured.

The MAX+PLUS II Compiler automatically generates Tabular Text Files (.ttf) and Hexadecimal (Intel-format) Files (.hex) that contain the data for configuring a FLEX 8000 or FLEX 10K device in a PPS configuration scheme.


Passive Serial (PS) glossary definition
Passive Serial (PS)

A configuration scheme in which an external controller passes configuration data to a FLEX 8000 or FLEX 10K device via a bit-wide serial data stream.

The device is treated as a slave device with a 5-wire interface to the external controller. The external controller can be an intelligent host such as a microcontroller or CPU, or the MAX+PLUS II Programmer used together with the PL-MPU Master Programming Unit, an appropriate device adapter, and the FLEX Download Cable.

The MAX+PLUS II Compiler automatically generates Tabular Text Files (.ttf) and Hexadecimal (Intel-format) Files (.hex) that contain the data for configuring a FLEX 8000 or FLEX 10K device in a PS configuration scheme.

After compilation, you can also create TTFs and Hex Files that contain the data for bit-slice PS configuration of multiple FLEX 8000 or FLEX 10K devices.


PGA glossary definition
PGA

Pin-grid array device package. A ceramic device package offered by Altera.


pin glossary definition
pin

A pin is an actual input or I/O pin on an Altera device.

In Graphic Editor files, a pin is represented by an INPUT, INPUTC, OUTPUT, OUTPUTC, BIDIR, or BIDIRC symbol. In a Text Design File (.tdf), a pin is represented as an INPUT, OUTPUT, or BIDIR port. In a VHDL Design File (.vhd), a pin is represented as an IN, OUT, or INOUT port. In a Waveform Design File (.wdf), a pin is represented as a node with an input, output, or bidirectional I/O type and a pin input, registered, or combinatorial node type.

You can assign a logic function to a specific pin number. You can also assign a logic function to a row or a column to ensure that the function is implemented in a pin on a particular row or column.


pin number glossary definition
pin number

A number used to assign an input or output signal in a design file, which corresponds to the pin number on an actual device.

Both letters and digits are used to specify pin numbers for PGA-package devices.


pinstub glossary definition
pinstub

In the Graphic and Symbol Editors, a pinstub is the location on the boundary of a symbol represented by an "x" in a Symbol File (.sym) and a name that represents an input or output of the primitive or of the megafunction or macrofunction design file that the symbol represents. A line (node) drawn in a schematic must connect to this pinstub to be recognized by the Compiler as a connection between the logic in the current file and the logic in the primitive, megafunction, or macrofunction.

You can specify whether or not to use an optional pinstub when you edit a symbol instance in a Graphic Editor file.

Pinstubs in Graphic Editor files are synonymous with ports in AHDL Function Prototypes and VHDL components. They are also synonymous with ports listed in the Subdesign Sections of lower-level Text Design Files (.tdf), and in Entity Declarations of lower-level VHDL Design Files (.vhd).


pinstub name glossary definition
pinstub name

A symbolic name that identifies an input or output of a logic function.

In the Symbol Editor, the "visible" pinstub name appears both inside and outside of the symbol. This "visible" pinstub name can be an abbreviation or an alias for the "full" pinstub name, which represents the full name of the original input, output, or bidirectional pin in a mega- or macrofunction design file or primitive Function Prototype.

You can specify whether or not to display the "visible" pinstub name in a Graphic Editor file when you create a pinstub in the Symbol Editor. The use or non-use of a particular pinstub (and hence its visibility) can be customized when you edit a symbol instance in the Graphic Editor with Edit Ports/Parameters (Symbol menu).

Pinstubs in Graphic Editor files are synonymous with ports in AHDL Function Prototypes and signals listed in the Subdesign Sections of lower-level Text Design Files (.tdf).


pixel glossary definition
pixel

Picture elements, i.e., the smallest unit of measure in the Symbol Editor. Eight pixels is equal to one grid unit (an Altera-defined unit of measure).


PLAD3-12 glossary definition
PLAD3-12

An adapter that plugs into the PL-MPU Master Programming Unit (MPU). This adapter allows you to use PLE-prefix adapters originally designed for use with the PLE3-12A programming unit. It also directly supports programming of EP330 DIP devices.


pldgates.lib glossary definition
pldgates.lib

An OrCAD Library File supported by MAX+PLUS II for use with OrCAD Schematic Files. The orcad.lmf file maps OrCAD functions from pldgates.lib to equivalent MAX+PLUS II macrofunctions.


PLDshell Plus glossary definition
PLDshell Plus

Altera’s Programmable Logic Shell. PLDshell Plus is a set of computer programs for designing and implementing custom logic circuits with Altera Classic and FLASHlogic devices. The MAX+PLUS II Programmer can program Classic and FLASHlogic devices with JEDEC Files (.jed) created by PLDshell Plus.


PLL glossary definition
PLL

Phase-locked loop. MAX+PLUS II provides a PLL megafunction that gives information on the phase and frequency differences between an input signal and a reference signal.


PLS-ES glossary definition
PLS-ES

A PC-based MAX+PLUS II development system, which is automatically provided on a site license when you purchase any PC-based MAX+PLUS II development system.

PLS-ES development systems include the following MAX+PLUS II applications and features:

Hierarchy Display

Graphic, Symbol, and Text Editors

Compilation support for Classic, MAX 5000, EPM7032, EPM7064, EPM7096, and EPF8282 devices

EDIF Interfaces (input and output)

Verilog and VHDL output

Timing Analyzer

Message Processor

Programmer


pointer or mouse pointer glossary definition
pointer or mouse pointer

An on-screen indicator that corresponds to the mouse’s movement. The pointer shows which area of the screen will be affected when you click a mouse button.

The pointer changes appearance and function depending on the currently selected palette tool and/or the location of the pointer itself (e.g., empty space vs. the end of a line). MAX+PLUS II applications use the following different pointers:

Pointer:	Type:	Application:

Selection	All

Text Entry	Graphic, Symbol, and Waveform Editors

Text Editing	Graphic, Symbol, Waveform, and Text Editors

Drawing	Graphic and Symbol Editors

Waveform Editing	Waveform Editor

Copy	Graphic, Symbol, Waveform, and Text Editors

Move	All editors

No-entry	Floorplan Editor

In addition, when you click on the context-sensitive help button on the toolbar ( [image]) or press Shift+F1, the following pointer appears and can be used to obtain context-sensitive help:

In MAX+PLUS II Help, the following pointer when the mouse is positioned over a jump to another help topic:


port glossary definition
port

A symbolic name that represents an input or output of a primitive or of a design file.

In AHDL, a port name in the Subdesign Section represents an input or output of the current file. This port name also appears in the Function Prototype for the function. When an instance of a primitive or lower-level design file is implemented with an Instance Declaration or an in-line reference, its ports are used to connect it to other functions in the TDF. After an instance is declared, its inputs and outputs are expressed as names in the format <instance name>.<port name> in the Logic Section. When an in-line reference is used, either named port association or positional port association can be used to connect the function’s ports to other functions in the TDF.

In VHDL, a port name in the Entity Declaration represents an input or output of the current file. When an instance of a primitive or lower-level design file is implemented with a Component Instantiation, its ports are connected to signals with Port Map Aspects.

A port name in an AHDL Subdesign Section or VHDL Entity Declaration is synonymous with a pin name in a Graphic Design File (.gdf) or Waveform Design File (.wdf). A port name that is appended to an instance name is synonymous with the full pinstub name in an instance of a symbol in a Graphic Editor file.


port (EDIF) glossary definition
port (EDIF)

An input or output of an EDIF cell, i.e., the input or output of a logic function.


power object glossary definition
power object

A graphic symbol in an OrCAD Schematic File that represents a connection to a power source.


Preset glossary definition
Preset

An input signal that asynchronously sets the output of a register to a logic high (1), regardless of other inputs.


primitive glossary definition
primitive

One of the basic functional blocks used to design circuits with MAX+PLUS II software. Primitives are used in Graphic Design Files (.gdf), AHDL Text Design Files (.tdf), and VHDL Design Files (.vhd).

Graphic Editor primitives include buffers, flipflops, a latch, input and output primitives, and logic primitives. Primitive symbols for Graphic Editor files are provided in the \maxplus2\max2lib\prim directory created during installation.

AHDL and VHDL primitives, which include buffers, flipflops, and a latch, are a subset of the primitive symbols used in Graphic Editor files. Other functions are represented by logical operators, ports, and other constructs. Function Prototypes for AHDL primitives are built into the MAX+PLUS II software; Component Declarations for VHDL primitives are provided in the maxplus2 package in the altera library, which is located in the \maxplus2\max2vhdl directory.

On a UNIX workstation, the maxplus2 directory is a subdirectory of the /usr directory.


primitive array glossary definition
primitive array

A single primitive that is connected to two or more buses in order to represent multiple primitives.


process glossary definition
process

One or more sequential operating steps that determine the behavior of a portion of a VHDL design. A process is defined with a Process Statement. A Process Statement is a concurrent statement; however, the statements within a Process Statement are sequential and execute in order, one after another.


probe glossary definition
probe

A unique name assigned to any node, e.g., the input or output of a primitive or macrofunction, which can be used instead of the full hierarchical node name throughout MAX+PLUS II. A probe name thus provides a short name to identify a node.


Probe & Resource Assignment File (.prb) glossary definition
Probe & Resource Assignment File (.prb) and Probe & Resource Assignment Backup File (.prk)

The Probe & Resource Assignment File (with the extension .prb) was used in pre-version 5.0 releases of MAX+PLUS II to store information about probe, pin, logic cell, chip, clique, logic option, and device assignments for each design file in a project. In MAX+PLUS II version 5.0 and higher, all assignment information is stored in the project’s Assignment & Configuration File (.acf). When you open a project created with an earlier version of MAX+PLUS II, the information from the obsolete .prb file is automatically converted into ACF format, and MAX+PLUS II renames the original .prb file with the .prk extension.


product term glossary definition
product term

Two or more factors in a Boolean expression combined with an AND operator constitute a product term, where "product" means "logic product."


Programmable Interconnect Array (PIA) glossary definition
Programmable Interconnect Array (PIA)

The portion of a MAX 5000 or MAX 7000 device that routes signals between different Logic Array Blocks (LABs).


Programmer Log File (.plf) glossary definition
Programmer Log File (.plf)

An ASCII file (with the extension .plf) generated by the Programmer that records programming session commands and messages.


Programmer Object File (.pof) glossary definition
Programmer Object File (.pof)

A binary file (with the extension .pof) generated by the Compiler’s Assembler module. This file contains the data used by the MAX+PLUS II Programmer to program an Altera device. The MAX+PLUS II Programmer can optionally save functional text vectors in a POF.


programming file glossary definition
programming file

A file containing data for programming Altera devices. Both the MAX+PLUS II Compiler and Programmer can generate programming files. The following programming file formats are available in MAX+PLUS II:

Hexadecimal (Intel-Format) File (.hex)

JEDEC File (.jed)

JTAG Chain File (.jcf)

Programmer Object File (.pof)

Raw Binary File (.rbf)

Serial Bitstream File (.sbf)

SRAM Object File (.sof)

Tabular Text File (.ttf)

POFs, SOFs, and JEDEC Files are used to program devices with the MAX+PLUS II Programmer; test vectors for functional testing can be saved in POFs and JEDEC Files. Hex Files, TTFs, RBFs, and SBFs are used to configure FLEX 8000 and FLEX 10K devices by other means. JCFs are used to program or configure one or more FLEX 10K, MAX 9000, or FLASHlogic devices in a multi-device JTAG chain.

JEDEC Files generated by A+PLUS and PLDshell Plus software can also be used to program Classic devices. The Programmer can save data read from an examined device in POF or JEDEC File format.


project glossary definition
project

A project consists of all files that are associated with a particular design, including all subdesign files and related ancillary files created by the user or by MAX+PLUS II software. The project name is the same as the name of the top-level design file in the project, without the filename extension.

MAX+PLUS II performs compilation, simulation, timing analysis, and programming on only one project at a time.


<project name>.ini file glossary definition
<project name>.ini and <project name>.ink files

The <project name>.ini file is a text file used in pre-version 5.0 releases of MAX+PLUS II. This file contained configuration parameters that controlled the project. In MAX+PLUS II version 5.0 and higher, all configuration parameters are stored in the project’s Assignment & Configuration File (.acf). When you open a project created with an earlier version of MAX+PLUS II, the information from the obsolete <project name>.ini file is automatically converted into ACF format, and MAX+PLUS II renames the original <project name>.ini file as <project name>.ink.


propagation delay glossary definition
propagation delay

The time required for any signal transition to travel between pins and/or nodes in a device.


property construct glossary definition
property construct

A name value pair associated with an EDIF object. In EDIF Input Files (.edf), property constructs are used to represent resource assignments, and string values within the property construct are used to indicate the values of resource assignments.

You can use properties to store project timing information in EDIF Output Files (.edo) if you select the EDIF Output File (.edo) option under Write Delay Constructs To in the EDIF Netlist Writer Settings dialog box.???


QFP glossary definition
QFP

Quad Flat Pack. A device package offered by Altera. Windowed ceramic QFP (CQFP), plastic QFP (PQFP), power QFP (RQFP), and plastic thin QFP (TQFP) packages are available.


race condition glossary definition
race condition

A condition in which a signal travels via two or more paths to a common circuit element, but the signals on these paths do not arrive at the same time. A race condition can cause glitches and unpredictable results.


radix glossary definition
radix

A number base. Group logic level and numerical values are entered and displayed in binary, decimal, hexadecimal, or octal radix in MAX+PLUS II.


range glossary definition
range

A sequence of numbers or arithmetic expressions that define the width of a group (bus) in a Graphic Editor or AHDL file. A range is enclosed in brackets; the most significant bit (MSB) of the range is shown first; the least significant bit (LSB) is shown last. The start and end of the range are separated by two periods.

Example: group a[2..0] consists of the nodes a2, a1, and a0; the MSB is a2; and the LSB is a0.


Raw Binary File (.rbf) glossary definition
Raw Binary File (.rbf)

A binary file (with the extension .rbf) containing configuration data for FLEX 8000 and FLEX 10K devices. This file is the binary equivalent of a Tabular Text File (.ttf).

You can create RBFs that support Passive Parallel Synchronous (PPS), Passive Parallel Asynchronous (PPA), and Passive Serial (PS) configuration schemes in MAX+PLUS II.


read.me file glossary definition
read.me file

A file provided with MAX+PLUS II software that contains information about changes made to the program since the release of the printed documentation and of MAX+PLUS II Help.

You should read the read.me file before you install MAX+PLUS II. You can also view the read.me file by choosing READ.ME from the Help menu after you have installed MAX+PLUS II.


Reduce Logic option glossary definition
Reduce Logic option

A logic synthesis option that directs the Compiler’s Logic Synthesizer module to globally consider the entire project when minimizing a logic gate. Reduce Logic detects and reduces inputs on gates that reduce to VCC or GND in the project as a whole. This reduction takes place even across SOFT buffer boundaries (but not LCELL boundaries).

If this option is turned off, logic minimization is performed locally, so that the Logic Synthesizer considers only the immediate two-level sum-of-products expression, and ignores fan-out destinations and recursive fan-in logic.

The following example shows how the Reduce Logic option can affect logic:

Before:	t = a&(b # w);	y = a # w&c;	w = (z&a # !z&b)	z = !c&d;

After:	t = a&(b # z);	y = a # b&c;	z = !c&d;

ACF logic option syntax:

<name>: REDUCE_LOGIC = (ON|OFF|DEFAULT|NULL)


Refactorization option glossary definition
Refactorization option

An advanced logic synthesis option that directs the Compiler’s Logic Synthesizer module to use an existing gate whenever it is advantageous to factor out logic in other gates in the project. This option may greatly decrease the amount of logic in a project, but may increase the propagation delays by adding extra levels of logic. However, if the output of a gate feeds an LCELL buffer, it is always treated as a unique signal and is not subject to Refactorization.

This option differs from the Subfactor Extraction option in that it only reuses an existing node, and does not create any new nodes. Turning this option on may also indirectly override turning the Duplicate Logic Extraction off.

The following example shows how the Refactorization option can affect logic:

Before:	t = a&b&c&d&e&f;	y = b&c&d&e&f&g;	z = d&e&f;

After:	t = a&b&c&z;	y = b&c&z&g;	z = d&e&f;

ACF logic option syntax:

<name>: REFACTORIZATION = (ON|OFF|DEFAULT|NULL)


Register Optimization option glossary definition
Register Optimization option

An advanced logic synthesis option that directs the Compiler’s Logic Synthesizer module to optimize logic on and across register boundaries. Registers may be added or removed from the project.

For example, if the output of one register clocks a second register, it may be possible to restructure the logic so that both registers are clocked by the same signal. Or, if several registers with the same Clock input are the only inputs to a lesser number of combinatorial logic cells, the registers can be changed to combinatorial logic cells and vice versa, which may allow further optimization of the resulting combinatorial network.

The following examples show how the Register Optimization option can affect logic:

Before:	a = TFF(en, clk1);	y = TFF(en, a);	z = TFF(en, y);

After:	a = TFF(en, clk1);	y = TFF(!a&en, clk1)	z = TFF(!a & !y &en, clk1);

Before:	a = y & z;	y = DFF(a # b, clk)	z = DFF(c&d, clk);

After:	a = DFF((a#b)&c&d, clk);

This option is available only if the SOFT Buffer Insertion logic option is turned on.

ACF logic option syntax:

<name>: REGISTER_OPTIMIZATION = (ON|OFF|DEFAULT|NULL)


register packing glossary definition
register packing

A feature of logic cells in MAX 9000 and FLEX 10K devices that allows two logic functions--a combinatorial logic function and a register with a single data input--to be implemented in the same logic cell.

You can manually implement register packing by assigning two logic functions to the same logic cell. In addition, the Global Project Logic Synthesis command includes an Automatic Register Packing option to allow the Compiler to automatically implement register packing for appropriate pairs of logic functions. Altera strongly recommends using the Automatic Register Packing option rather than manual logic cell assignments to implement register packing.

ACF global project option syntax:

AUTO_REGISTER_PACKING = (ON|OFF|NULL)


registered feedback glossary definition
registered feedback

Feedback that is the output of a flipflop or latch.


registered output glossary definition
registered output

The output of a flipflop or latch, which can feed an output pin on the device.


registered performance glossary definition
registered performance

The minimum required Clock period and the maximum Clock frequency for a circuit, which can be calculated in the MAX+PLUS II Timing Analyzer.

The Clock period equals the maximum delay from the Q output of a flipflop to the D or Clock Enable input of a flipflop, plus the internal setup time and propagation delay through the flipflop. The Clock frequency equals (1/Clock period).


relative path glossary definition
relative path

In computer directories, a relative path is a pathname that is relative to the current directory. A relative pathname begins with the next-lower- or next-higher-level directory name, in contrast to an absolute path, which always begins with a drive name plus a colon (e.g., c:).

In node and symbol names, a relative path is hierarchy pathname that is relative to the current file. A relative pathname begins with the net ID number or instance name of a logic function in the current file, in contrast to an absolute path, which always begins with a vertical bar (|) and the net ID number or instance name of a logic function in the top-level design file.


relative time vector pattern glossary definition
relative time vector pattern

Sets of logic values applied at various time intervals to specify input vectors for design simulation. These vector logic values are applied at the times specified in the Start, Interval, and Stop Sections of the Vector File (.vec).


Report File (.rpt) glossary definition
Report File (.rpt)

An ASCII text file (with the extension .rpt), generated by the Compiler’s Fitter module, that shows how device resources are used by the project. If a module preceding the Partitioner generates an error, this file is not generated. If the Partitioner generates an error, the Report File is generated in most cases.


Reset glossary definition
Reset

An active-high input signal that asynchronously resets the output of a register to a logic low (0) or a state machine to its initial state, regardless of other inputs.


reserved resources glossary definition
reserved resources

Device pin or logic cell resources that you have specified to remain unused with the Global Project Device Options command. Device resources can be reserved if you wish to leave additional logic capacity for future use. The Device Summary Section of the Report File shows how many resources are reserved.

You can also reserve a pin for future use by using the Pin/Location/Chip command to assign a pin number to an INPUT primitive/port that is not connected to other logic.


resource glossary definition
resource

A resource is a portion of an Altera device that performs a specific, user-defined task (e.g., pins, logic cells).


resource assignment glossary definition
resource assignment

An assignment of a logic function in a project to a particular pin, logic cell, I/O cell, embedded cell, logic array block (LAB), embedded array block (EAB), row, column, or chip. This type of resource assignment assigns a logic function to a physical resource in a device.

A resource assignment can also consist of a clique, logic option, connected pin, or timing requirement assignment to a particular logic function in a project. This type of resource assignment assigns a compilation resource to a logic function.


Resynthesize Network option glossary definition
Resynthesize Network option

An advanced logic synthesis option that directs the Compiler’s Logic Synthesizer module to completely restructure the network of nodes in the project. This option allows a combinatorial network to be partially or completely flattened to sum-of-products form and then refactored. The Logic Synthesizer compares the new network to the original network and retains the best one. The timing and form of the resulting logic may differ significantly from the logic in the original design file(s).

Turning this option on may partially override logic option settings of Minimization=Partial or Multi-Level Factoring=Off.

The following example shows how the Resynthesize Network option can affect logic:

Before:	t = e&(a # bc) # b((a#d)e # cf) # f&(a # b(c#d));

After:	t = (a # b&(c#d))&(e#f);

This option is available only if the SOFT Buffer Insertion logic option is turned on.

ACF logic option syntax:

<name>: RESYNTHESIZE_NETWORK = (ON|OFF|DEFAULT|NULL)


ripple Clock glossary definition
ripple Clock

A clocking scheme in which the Q output of one flipflop drives the Clock input to another flipflop.

Ripple clocking is commonly used to create a counter. It is unreliable if logic depends on the state of multiple flipflops within the logic that forms the ripple Clock.


RISEFALL primitive glossary definition
RISEFALL primitive

A primitive that provides a different propagation delay for low-to-high and high-to-low transitions. This primitive is always included in a timing Simulator Netlist File (.snf); it is optionally included in an EDIF Output File (.edo).


row glossary definition
row

A horizontal line of LABs connected by a row FastTrack Interconnect path in a FLEX 8000, FLEX 10K, or MAX 9000 device.


rubberbanding glossary definition
rubberbanding

A feature in the Graphic and Symbol Editors that, when turned on, allows you to move symbols and areas without losing signal connectivity. When rubberbanding is on, a line that connects two symbols bends and stretches to maintain the connection when you move one of the symbols.


SAM+PLUS glossary definition
SAM+PLUS

Altera’s Stand-Alone Microsequencer (SAM) Programmable Logic User System. SAM+PLUS is a set of computer programs and hardware support products that facilitate design and implementation of custom logic circuits with the EPS448 device.


SCF output overwriting rules glossary definition
SCF output overwriting rules

Outputs in the SCF are overwritten on the basis of the following combinations of options:

Check Outputs	Use Device	Effect on SCF Outputs:

Option:	Option:

Off	Off	Simulation outputs overwrite SCF outputs.

Off	On	Actual device outputs overwrite SCF outputs.

On	Off	SCF outputs are compared to simulation outputs but not overwritten.

On	On	SCF outputs are compared to actual device outputs but not overwritten, i.e., functional testing is performed. (Same as the Test button in the Programmer.)


secondary input glossary definition
secondary input

The Clock, Preset, and Reset (Clear) inputs to a register or a state machine in a design file.


Security Bit glossary definition
Security Bit

A bit that prevents an Altera device from being interrogated. This bit also prevents EPROM-based Altera devices from being inadvertently reprogrammed.

The Security Bit can be turned on or off for each device in a project, or for the entire project.

ACF syntax:

SECURITY_BIT = (ON | OFF | DEFAULT|NULL)


selection, area glossary definition
selection, area

A defined rectangular region that includes one or more adjacent objects. In the Graphic and Symbol Editors, this area is contained within a rectangular border called an area marquee. In the Waveform Editor, Floorplan Editor, and Hierarchy Display, all objects within an area selection are highlighted.

Area selection is the process of selecting multiple contiguous objects by dragging Button 1 with the Selection tool. In the Waveform Editor, such "objects" can consist of adjacent nodes and groups, whole waveforms, or intervals on one or more waveforms. In the Floorplan Editor, such "objects" can consist of adjacent pins, nodes, logic cells, or assignment bins. In the Hierarchy Display, file icons can be selected.

In the Graphic and Symbol Editors, symbols, arcs, circles, diagonal lines, and text blocks must lie completely within the area marquee to be selected. When an orthogonal line crosses the marquee, only the portion within the marquee is selected.


sequential group (or bus) name glossary definition
sequential group (or bus) name

A group (bus) name in an AHDL Text Design File (.tdf), Graphic Design File (.gdf), or Assignment & Configuration File (.acf) that consists of a series of comma-separated node names. In a TDF only, the node names must also be enclosed in parentheses.

Example: group (a, b, c) consists of the nodes a, b, and c.

In a Graphic Editor file or ACF only, a sequential bus name can include a single- or dual-range bus name in a series of names.

Example: a[8..0],dout[6..4]


Serial Bitstream File (.sbf) glossary definition
Serial Bitstream File (.sbf)

An ASCII file (with the extension .sbf) that contains the data for configuring a FLEX 8000 or FLEX 10K device with the BitBlaster from a system prompt. This file can be generated with the Combine Programming Files command (File menu) in the Compiler or the Simulator.


setup time glossary definition
setup time

On a flipflop, the setup time is the minimum time interval between the application of a signal at the input pin that feeds the data or Clock Enable input and a low-to-high transition at the input pin that feeds the Clock input of the flipflop or the Latch Enable input of the latch.

On a latch, the setup time is the minimum time interval between the application of a signal at the input pin that feeds the data input of a latch and a low-to-high transition at the input pin that feeds the Latch Enable input of the latch.

On an asynchronous RAM block, the setup time is the minimum time interval between the application of a signal at the input pin that feeds the data or address inputs and a low-to-high or high-to-low transition at the input pin that feeds the Write Enable input of the RAM block.

Internal setup times for flipflops, latches, and asynchronous RAM, which are not user-defined, similarly constrain signals that are generated within the device.


shared expanders and shareable expanders glossary definition
shared expanders and shareable expanders

A feature of MAX 5000, MAX 7000, and MAX 9000 device architecture that allows logic cells to use uncommitted product terms within the same Logic Array Block (LAB). A product term that is eligible to be shared in this manner is called a shareable expander; a product term that has been shared in this manner is called a shared expander.

The MAX+PLUS II Compiler automatically allocates shareable expanders when a project is compiled. A shared expander also can be allocated with an EXP primitive.


sheet glossary definition
sheet

A schematic symbol in an OrCAD Schematic File that represents a lower level of hierarchy in the current schematic. MAX+PLUS II saves all OrCAD sheets as parts.


sheet size glossary definition
sheet size

The size of a schematic drawing selected with the Size command (File menu) in the Graphic Editor. Sizes ranging from A (9 x 11 inch / 59 x 77 grid units) to H (143 x 143 inch / 999 x 999 grid units) are available in horizontal and vertical orientation.


sign-extend glossary definition
sign-extend

To extend a two’s complement binary number by padding to the left with 0’s if the number is positive, or with 1’s if the number is negative.


Simulator Channel File (.scf) or Channel File glossary definition
Simulator Channel File (.scf) or Channel File

A graphical waveform file (with the extension .scf) that is both an input and an output to the Simulator. This file contains a waveform representation of the vector values on the input nodes that drive simulation, as well as the buried and output nodes to be simulated. Waveforms in the file represent high (1), low (0), high-impedance (Z), and undefined (X) logic levels.

An SCF can be created and viewed in the Waveform Editor; the Simulator also automatically creates and updates an SCF during simulation. An SCF can also be used to provide the vector inputs for functional testing in the Programmer.


Simulator Initialization File (.sif) glossary definition
Simulator Initialization File (.sif)

A file (with the extension .sif) that saves all node, group, and memory values, including initialized values entered with the Simulator’s Initialize Nodes/Groups and Initialize Memory commands (Initialize menu) or the Command File (.cmd) GROUP INIT and NODE INIT commands. The SIF allows you to reuse a previously saved set of node and group values.


Simulator Netlist File (.snf) glossary definition
Simulator Netlist File (.snf)

A binary file (with the extension .snf) that contains the data for functional simulation, timing simulation or timing analysis, or linked multi-device simulation. Three optional Compiler modules create the different types of SNFs that contain the information required for different simulation modes and/or timing analysis:

Module:	Action:

Timing SNF Extractor	Generates a timing SNF that contains all data required for timing simulation and full timing analysis.

Functional SNF Extractor	Generates a functional SNF that contains all data required for functional simulation.

Linked SNF Extractor	Generates a linked SNF that combines timing and/or functional data from the timing, functional, and/or linked SNFs for other previously compiled projects. If all of the combined SNFs are timing SNFs, a linked SNF can also be used for full timing analysis.

Only one type of SNF can exist at any particular time for the same project.


Simulator Netlist File primitive glossary definition
Simulator Netlist File primitive

Any primitive used in a Simulator Netlist File (.snf), including AND, NAND, OR, NOT, XOR2, DELAY, TRI, LATCH, DFF, DFFE, JKFF, JKFFE, NOR, XNOR2, FILTER, and RISEFALL.


single-range group (or bus) name glossary definition
single-range group (or bus) name

The name of a group (or bus) of up to 256 nodes, consisting of up to 32 name characters, followed by a range of numbers or arithmetic expressions in brackets. The start and end of the range are separated by two periods. Each number in the sequence represents an individual node (or "bus bit").

Example: group a[4..1] consists of the nodes a4, a3, a2, and a1.

In a Graphic Editor files, a sequential bus name can also include one or more single-range bus names in a series. The first node of the series or the first node in the first range is the most significant bit of the bus; the last node of the series or the last node in the last range is the least significant bit.

Example: a[8..0], b1, dout[6..4]


single-window application glossary definition
single-window application

A MAX+PLUS II application that can have only one window open at a time. The following applications allow only single windows:

Hierarchy Display

Floorplan Editor

Compiler

Simulator

Timing Analyzer

Programmer


site license glossary definition
site license

A site license allows you to install an unlimited number of MAX+PLUS II systems with the PLS-ES feature set. The site license is available when you purchase a copy of MAX+PLUS II software.

The PLS-ES development system contains the following features:

Schematic design entry

Text design entry (AHDL)

Logic synthesis and device fitting

Timing analysis

Automatic error location

EDIF interfaces to other CAE tools

Verilog HDL and VHDL output

The additional MAX+PLUS II systems on a site license do require software registration and authorization codes. Each individual user must contact Altera to register and obtain an authorization code (at no cost). If no authorization code is present, he or she is authorized to use the PLS-ES feature set for MAX+PLUS II software only for a limited time.


slew rate glossary definition
slew rate

The speed at which a low-to-high or high-to-low transition occurs on an output pin.

Turning on the Slow Slew Rate logic synthesis option helps to reduce switching noise, but also results in a slower signal transition.


Slow Slew Rate option glossary definition
Slow Slew Rate option

A logic synthesis option that directs the Compiler’s Logic Synthesizer module to implement a slow low-to-high or high-to-low transition at an output pin. When a large number of output pins switch simultaneously, pins that use the slow slew rate help reduce switching noise.

In MAX 7000E devices, the Slow Slew Rate option and the Turbo Bit option are controlled by a single bit. Therefore, only one of these options can be turned on at any one time. If both options are turned on or if both options are turned off, the Compiler uses the Slow Slew Rate setting and ignores the Turbo Bit setting.

ACF logic option syntax:

<name>: SLOW_SLEW_RATE = (ON|OFF|DEFAULT|NULL)


SOFT Buffer Insertion option glossary definition
SOFT Buffer Insertion option

A logic synthesis option that directs the Compiler’s Logic Synthesizer module to insert SOFT buffers at advantageous locations in the project. If this option is turned on, illegal combinatorial feedback is automatically fixed. If this option is turned off, all logic gates--except those with manually entered SOFT or LCELL buffers--are flattened to sum-of-products form, and must fit in a single logic cell.

Altera recommends turning the SOFT Buffer Insertion option on for all FLEX 8000 and FLEX 10K-based projects. Turning this option on in the default logic synthesis style for the project as a whole can also help eliminate the "Logic too complex" errors that can occur in MAX 5000, MAX 7000, MAX 9000, and Classic-based projects. In addition, this option must be turned on to enable the following other options that can create gates:

Decompose Gates

Multi-Level Factoring

Resynthesize Network

Register Optimization

Subfactor Extraction

ACF logic option syntax:

<name>: SOFT_BUFFER_INSERTION = (ON|OFF|DEFAULT|NULL)


software guard glossary definition
software guard

A device that attaches to the parallel printer port on a PC. It is required to run MAX+PLUS II software for most single-user PC-based development systems.


SOIC glossary definition
SOIC

Small-outline integrated circuit. A plastic device package option.


source node glossary definition
source node

A node that is tagged (designated) as the source of a signal for the purpose of timing analysis. A source node is tagged with the Timing Analysis Source command, and can be any node that is the output of a primitive, megafunction, macrofunction, or I/O pin.


SRAM Object File (.sof) glossary definition
SRAM Object File (.sof)

A binary file (with the extension .sof), generated by the Compiler’s Assembler module, that contains the data for configuring an Altera FLEX 8000 or FLEX 10 device.


Standard Delay Format (SDF) Output File (.sdo) glossary definition
Standard Delay Format Output File (.sdo)

An optional output file (with the extension .sdo) containing timing delay information that allows you to perform back-annotation for simulation with VHDL simulators that use VITAL-compliant simulation libraries; back-annotation for simulation in Verilog simulators; and timing analysis and resynthesis with EDIF simulation and synthesis tools.The Standard Delay Format (SDF) is an industry-standard format.

The MAX+PLUS II Compiler’s EDIF, VHDL, and Verilog Netlist Writer modules of the MAX+PLUS II Compiler can generate SDF Output Files in SDF version 2.1 or 1.0 format.


standard synthesis glossary definition
standard synthesis

Logic synthesis that includes the following logic options:

XOR Synthesis

Turbo Bit (including logic cell Turbo Bit)

Parallel Expanders

Minimization (Full and Partial)

Standard synthesis includes only these logic options; other options listed in the Define Synthesis Style and Advanced Options dialog boxes are available only in multi-level synthesis. This type of logic synthesis is available only for the Classic, MAX 5000, MAX 7000/MAX 7000E, and MAX 9000 device families.


state glossary definition
state

A state is implemented in a device as a pattern of 1’s and 0’s (bits) that are the outputs of multiple flipflops (collectively called a state machine state register). States can be defined in an AHDL Text Design File (.tdf), a Waveform Design File (.wdf), a Vector File (.vec), a VHDL Design File (.vhd), or a State Machine File (.smf), and are reported in the State Machine Assignments Section of the Report File (.rpt).


state bit glossary definition
state bit

An output of a flipflop used by a state machine to store one bit of the value of the state machine.


state control equation glossary definition
state control equation

An AHDL equation that assigns a value to the Clock, Clock Enable, or Reset port(s) of the D or T flipflop(s) on which a state machine is implemented.


state machine glossary definition
state machine

A sequential circuit that advances through a number of states. A state machine can be defined in a Waveform Design File (.wdf), State Machine File (.smf), Vector File (.vec), VHDL Design File (.vhd), or in a State Machine Declaration in an AHDL Text Design File (.tdf).


State Machine File (.smf) glossary definition
State Machine File (.smf)

An ASCII file (with the extension .smf) that contains a state machine design created for use with Altera’s A+PLUS or SAM+PLUS software. This file contains a symbolic representation of the data for a circuit in terms of inputs, outputs, and transitions between states. The MAX+PLUS II Compiler automatically translates an SMF into an Altera Design File (.adf) and a Compiler Netlist File (.cnf) during compilation.


state name glossary definition
state name

A symbolic name that represents the state of a state machine.


state transition glossary definition
state transition

A conditional assignment of a state to the state machine variable. State transitions are created by conditionally assigning the state variables with a single behavioral construct.

In AHDL, state transitions are created with Case or Truth Table Statements. State transitions occur on the rising edge of the Clock.

In VHDL, state transitions are created with Case Statements. You must also provide a Wait Statement to cause each state transition to occur on a Clock edge.


static hazard glossary definition
static hazard

A static hazard occurs when the change in an input logic level causes an output level to momentarily change or experience a glitch.


status bar glossary definition
status bar

A line at the bottom of the MAX+PLUS II window that provides a brief description of a highlighted menu command or an item in the toolbar or tool palette.


string value glossary definition
string value

A value expressed as a string, or a sequence of printable characters enclosed in quotation marks ("). In EDIF Input Files (.edf), string values within the property construct are used to indicate the values of resource assignments.


subdesign glossary definition
subdesign

A lower-level design file in a MAX+PLUS II project, i.e., an Altera-provided or user-created megafunction or macrofunction.

Altera provides libraries of mega- and macrofunctions in the mega_lpm and mf subdirectories of the \maxplus2\max2lib directory. AHDL Include Files (.inc) for these functions are located in the \maxplus2\max2lib\mega_lpm and \maxplus2\max2inc directories, respectively. Component Declarations for functions supported by VHDL are provided in the maxplus2 package in the altera library, which is located in the \maxplus2\max2vhdl directory.

On a UNIX workstation, the maxplus2 directory is a subdirectory of the /usr directory.


subdesign name or entity name glossary definition
subdesign name or entity name

A name that represents the name of a subdesign. In AHDL, the subdesign name is a quoted or unquoted symbolic name that must be the same as the Text Design File (.tdf) filename. In VHDL, the entity name is an identifier.

Unquoted subdesign name (AHDL):

Maximum length:	32 characters

Legal characters:	a-z, A-Z, 0-9, and underscore (_)

An unquoted subdesign name cannot be a reserved AHDL identifier or keyword.

Quoted subdesign name (AHDL):

Maximum length:	32 characters

Legal characters:	a-z, A-Z, 0-9, dash (-), and underscore (_)

Identifier (VHDL):

Maximum length:	32 characters

Legal characters:	a-z, A-Z, 0-9 and underscore (_)

An identifier cannot begin with a digit or an underscore (_), cannot end with an underscore, and cannot have two underscores (_ _) in succession. It cannot be a keyword.

In the UNIX workstation environment, filenames and hence subdesign names are case-sensitive.


Subfactor Extraction option glossary definition
Subfactor Extraction option

An advanced logic synthesis option that directs the Compiler’s Logic Synthesizer module to extract subfactors that are common to two or more functions in a project, and create a new node that implements the common subfunction. This option may greatly decrease the amount of logic in a design, but may increase the logic delay by adding extra levels of logic. This option differs from the Refactorization option, which never creates a new node, but only reuses an existing node.

The following example shows how the Subfactor Extraction option can affect logic:

Before:	t = a&b&(c#d)&e;	y = (c#d)&e&(f#g);

After:	t = a&b&z;	y = z&(f#g);	z = (c#d)&e;

This option is available only if the SOFT Buffer Insertion logic option is turned on.

ACF logic option syntax:

<name>: SUBFACTOR_EXTRACTION = (ON|OFF|DEFAULT|NULL)


sum-of-products glossary definition
sum-of-products

A Boolean expression is said to be in sum-of-products form if it consists of product terms combined with the OR operator.


super-project and sub-project glossary definition
super-project and sub-project

A super-project consists of a top-level design file that contains symbols or instances representing multiple, individual projects.

A sub-project is any individual project that serves as part of a super-project. You can use any super-project as a sub-project in a higher-level super-project.


Symbol File (.sym) glossary definition
Symbol File (.sym)

A graphic file (with the extension .sym) created by the Symbol Editor or the Compiler Netlist Extractor module of the Compiler. This file represents a design file (i.e., megafunction or macrofunction) or MAX+PLUS II primitive with the same name and can be used in Graphic Design Files (.gdf).

When the Compiler’s Linked SNF Extractor module is turned on, a symbol in a Graphic Editor file represents a Simulator Netlist File (.snf), rather than a design file, during compilation.


symbol ID number or net ID number glossary definition
symbol ID number or net ID number

A number that uniquely identifies every node and symbol in a design file.

In the Graphic Editor, this number appears inside the bottom left corner of a symbol and reflects the order in which symbols are entered in a Graphic Editor file. In other types of design files, the Compiler assigns ID numbers to nodes when the project is compiled. In the Hierarchy Display window, the name of each lower-level design file is appended with a colon (:) plus the ID number or an AHDL or VHDL mega- or macrofunction instance name.


symbolic name or identifier glossary definition
symbolic name or identifier

A user-defined name in AHDL or VHDL.

Unquoted symbolic name (AHDL):

Maximum length:	32 characters

Legal characters:	a-z, A-Z, 0-9, slash (/), and underscore (_)

An unquoted symbolic name cannot consist entirely of digits and cannot be a reserved identifier or keyword.

Quoted symbolic name (AHDL):

Maximum length:	32 characters

Legal characters:	a-z, A-Z, 0-9, slash (/), dash (-), and underscore (_)

A quoted symbolic name cannot be a reserved identifier.

Identifier (VHDL):

Maximum length:	32 characters

Legal characters:	a-z, A-Z, 0-9, and underscore (_)

An identifier cannot begin with a digit or an underscore, cannot end with an underscore, and cannot have two underscores (_ _) in succession. It cannot be a keyword.


synchronous outputs glossary definition
synchronous outputs

Output signals that always change logic levels at the same time because they are clocked by a common Clock.


synthesized logic cells glossary definition
synthesized logic cells

Shareable expanders that have been converted by the Compiler’s Logic Synthesizer into logic cells to balance the number of shareable expanders in the device and to use device resources more efficiently.


Table File (.tbl) glossary definition
Table File (.tbl)

An ASCII file (with the extension .tbl) that contains a tabular-format list of all input vectors and output logic levels in the current Vector File (.vec) or Simulator Channel File (.scf). The Table File can be generated in the Simulator or Waveform Editor.


Tabular Text File (.ttf) glossary definition
Tabular Text File (.ttf)

An ASCII text file in tabular format (with the extension .ttf) containing configuration data for FLEX 8000 and FLEX 10K devices.

The MAX+PLUS II Compiler automatically creates TTFs containing configuration data for the sequential Passive Parallel Synchronous (PPS), Passive Parallel Asynchronous (PPA), and Passive Serial (PS) configuration schemes for FLEX 8000 devices, and the PS configuration scheme for FLEX 10K devices.

After compilation, you can also create TTFs that support other configuration schemes for FLEX 8000 and FLEX 10K devices.


tco (Clock to output delay) glossary definition
tco (Clock to output delay)

The time required to obtain a valid output at an output pin that is fed by a register after a Clock signal transition on an input pin that clocks the register. This time always represents an external pin-to-pin delay.

tco is also a timing assignment that specifies the maximum acceptable Clock to output delay. In MAX+PLUS II, you can specify a required tco for an entire project and/or for any input pin (INPUT or INPUTC), output pin (OUTPUT or OUTPUTC), or TRI buffer (i.e., BIDIR or BIDIRC pin output function) pin.

ACF timing assignment syntax:

<name>: TCO = <decimal number><time unit>

ACF global project option syntax:

TCO = <decimal number><time unit>


ternary operator glossary definition
ternary operator

An operator that selects between two expressions within an AHDL arithmetic expression. The ternary operator is used in the following format:

<expression 1> ? <expression 2> : <expression 3>

If the first expression is non-zero (true), the second expression is evaluated and given as the result of the ternary expression. Otherwise, the third expression is evaluated and given as the result of the ternary expression.


Text Design Backup File (.tdk) glossary definition
Text Design Backup File (.tdk)

An ASCII text file (with the extension .tdk) in the Altera Hardware Description Language (AHDL) that is backup copy of a Text Design File (.tdf) created with a pre-version 5.0 release of MAX+PLUS II.

In pre-version 5.0 releases of MAX+PLUS II, TDFs could contain resource and device assignments for a project. In MAX+PLUS II version 5.0 and higher, all assignment information is stored in the project’s Assignment & Configuration File (.acf). When you open a project created with an earlier version of MAX+PLUS II, the assignment information from a TDF is automatically converted into ACF format, and the assignments in the TDF are commented out. To preserve your original TDF, MAX+PLUS II saves a copy of the original file with the extension .tdk.


Text Design Export File (.tdx) glossary definition
Text Design Export File (.tdx)

An ASCII text file (with the extension .tdx) in the Altera Hardware Description Language (AHDL) that is optionally generated when you compile a Xilinx Netlist Format File (.xnf). It contains the same logic as the XNF File.

A Text Design Export File can be saved as a Text Design File (.tdf) and used to replace the corresponding XNF File in the hierarchy of a project.


Text Design File (.tdf) glossary definition
Text Design File (.tdf)

An ASCII text file (with the extension .tdf) written in the Altera Hardware Description Language (AHDL). Text Design Export Files (.tdx) and Text Design Output Files (.tdo) can be saved as TDFs and compiled with MAX+PLUS II.


Text Design Output File (.tdo) glossary definition
Text Design Output File (.tdo)

An ASCII text file (with the extension .tdo), generated by the MAX+PLUS II Compiler, that contains the Altera Hardware Description Language (AHDL) equivalent of the fully optimized logic for a device in the project.

The Compiler generates a TDO File, as well as an Assignment & Configuration Output File (.aco) when you compile a project if you turn on the Generate AHDL TDO File command (Processing menu).

You can save a TDO File as a Text Design File (.tdf) and recompile it. (You must also save the Assignment & Configuration Output File (.aco) as an Assignment & Configuration File (.acf) if you wish to preserve the assignments for the device.) TDO Files facilitate back-annotation and preserve the existing logic synthesis in the project.


text selection glossary definition
text selection

Any text characters selected in the Graphic, Text, Waveform, or Symbol Editor.


three-way checkbox glossary definition
three-way checkbox

A checkbox that has three different states.

State:	Meaning:

Unchecked	Off

Checked	On

Grayed	Default, i.e., the setting for the item is defined elsewhere.

In a logic synthesis style or in the setting for an individual logic option, a grayed checkbox indicates that the setting is specified elsewhere or at a higher level in the hierarchy. If a logic option is not specified elsewhere, its setting is determined by the default logic synthesis style for the entire project, which is specified with the Global Project Logic Synthesis command (Assign menu).

For a device option or dual-purpose pin, a grayed checkbox indicates that the setting is specified for the entire project with the Global Project Device Options command (Assign menu).


time-slice glossary definition
time-slice

A set of stable, unchanging waveforms that exists between two logic level transitions in a Waveform Design File (.wdf) or Simulator Channel File (.scf).


time unit glossary definition
time unit

A unit for specifying a time in MAX+PLUS II. Five time units are available:

Time Unit:	Abbreviation for:

ns	nanosecond

ms	millisecond

us	microsecond

s	second

mhz	megahertz

A time value is always followed immediately (i.e., with no space in between) by a time unit. If you do not enter a time unit, either ns or mhz is assumed as the default, depending on the appropriate context.


.time variable glossary definition
.time variable

Represents the current simulation time, which is shown in the Simulation Time field in the Simulator window. The .time variable can also be used in a breakpoint conditions list.


Timing Analyzer Output File (.tao) glossary definition
Timing Analyzer Output File (.tao)

An ASCII text file (with the extension .tao) that is used to save the results of the current timing analysis displayed in the MAX+PLUS II Timing Analyzer.


timing assignment glossary definition
timing assignment

An assignment that specifies desired speed performance on one or more logic functions.

The tpd, tsu, tco, and fmax timing assignments, as well as "timing cuts," are available. You can assign timing to individual logic functions and specify default timing for the project as a whole.


timing cut glossary definition
timing cut

A type of timing assignment that cuts the connections between the timing path for an individual node and other nodes in the project, to indicate that the Compiler should not consider the delay along this path when it attempts to meet the user’s desired speed performance while processing the project.

ACF timing assignment syntax:

<name>: CUT = (ON|OFF|DEFAULT|NULL)


timing simulation glossary definition
timing simulation

A MAX+PLUS II Simulator mode that uses a timing Simulator Netlist File (.snf) to simulate the logical and timing performance of a project.

Because the timing SNF is generated after logic synthesis, partitioning, and fitting are performed, timing simulation allows you to simulate only the nodes in a project that have not been removed by logic optimization.

When the SNF for the current project is a timing SNF, the title bar of the Simulator window displays Simulator: Timing Simulation to indicate that it is set up to run in the timing simulation mode.


timing Simulator Netlist File (.snf) glossary definition
timing Simulator Netlist File (.snf)

A binary file (with the extension .snf) that contains the data for timing simulation and timing analysis. This file is created by the MAX+PLUS II Compiler’s optional Timing SNF Extractor module.


Timing SNF Extractor glossary definition
Timing SNF Extractor

The Compiler module that creates the timing Simulator Netlist File (.snf), which contains the functional and timing data for the fully optimized project. This file is used for timing simulation and timing analysis. The Compiler’s EDIF Netlist Writer module also uses timing SNFs to generate EDIF Output Files (.edo).


Token File (.tok) glossary definition
Token Files (tedsdflt.tok and vhdstdfn.tok)

Token files are ASCII text files that store information necessary for the Text Editor to execute the Find Matching Delimiter (Utilities menu) and Syntax Coloring (Options menu) commands.

You should never edit a .tok file.


toolbar glossary definition
toolbar

A row of buttons and drop-down list boxes at the top of the MAX+PLUS II window. The buttons and list boxes on the toolbar allow you to execute commands quickly.

When you point to an item in the toolbar with the mouse, the status bar at the bottom of the window displays a brief description of the function of that item.


tool palette glossary definition
tool palette

A row of buttons on the left side of the MAX+PLUS II window. The buttons on the tool palette select different editing tools and/or allow you to execute commands quickly.

When you point to an item in the tool palette with the mouse, the status bar at the bottom of the window displays a brief description of the function of that item.


tpd (input to non-registered output delay) glossary definition
tpd (input to non-registered output delay)

The time required for a signal from an input pin to propagate through combinatorial logic and appear at an external output pin.

tpd is also a timing assignment that specifies the maximum acceptable input to non-registered output delay. In MAX+PLUS II, you can specify a required tpd for an entire project and/or for any input pin (INPUT or INPUTC), output pin (OUTPUT or OUTPUTC), or TRI buffer (i.e., BIDIR or BIDIRC pin output function) pin.

ACF timing assignment syntax:

<name>: TPD = <decimal number><time unit>

ACF global project option syntax:

TPD = <decimal number><time unit>


tri-state buffer glossary definition
tri-state buffer

A buffer with an input, output, and controlling Output Enable signal. If the Output Enable input is high, the output signal equals the input. If the Output Enable input is low, the output signal is in a state of high impedance. The tri-state buffer is implemented with the TRI primitive.

Tri-state buses can be implemented by tying multiple nodes together in a Graphic Editor file and with the TRI_STATE_NODE variable in an AHDL file.


truncate glossary definition
truncate

In AHDL, to shorten a binary number by subtracting digits from the left.


tsu (Clock setup time) glossary definition
tsu (Clock setup time)

The length of time for which data that feeds a register via its data or Enable input(s) must be present at an input pin before the Clock signal that clocks the register is asserted at the Clock pin.

tsu is also a timing assignment that specifies the maximum acceptable Clock setup time. In MAX+PLUS II, you can specify a required tsu for an entire project and/or for any input pin (INPUT or INPUTC) or bidirectional pin (BIDIR or BIDIRC input function).

ACF timing assignment syntax:

<name>: TSU = <decimal number><time unit>

ACF global project option syntax:

TSU = <decimal number><time unit>


ttl.lib file glossary definition
ttl.lib file

An OrCAD Library File supported by MAX+PLUS II for use with OrCAD Schematic Files. MAX+PLUS II supports all function name prefixes in ttl.lib automatically, so that only a single mapping is needed in the Library Mapping File orcad.lmf for all variations of a single function. MAX+PLUS II supports all of the following prefixes used in the ttl.lib file:

74LS	LS	74S	S

74ALS	ALS	74AS	AS

74HCTLS	HCTLS	74HCT	HCT

74HC	HC	74ACT	ACT

74AC	AC	74AHCT	ACHT

74FCT	FCT	74F	F

74C	C	74PCT	PCT

74BC	BC	74


Turbo Bit and logic cell Turbo Bit glossary definition
Turbo Bit and logic cell Turbo Bit

A control bit for choosing speed and power characteristics of an Altera device. If the Turbo Bit is on, the speed increases; if it is off, the power consumption decreases. The Turbo Bit can be turned on or off in a design file or the Compiler.

Turbo Bit availability differs for each device family.

Altera Device Family:	Turbo Bit Availability:

Classic	Applies to the entire device (specified as a device option)

MAX 5000	Not available

MAX 7000	Applies to individual logic cells within a device (specified as a logic option)

MAX 9000	Applies to individual logic cells within a device (specified as a logic option)

FLEX 8000	Not available

FLEX 10K	Not available

In MAX 7000E devices, the Turbo Bit option and the Slow Slew Rate option are controlled by a single bit. Therefore, only one of these options can be turned on at any one time. If both options are turned on or if both options are turned off, the Compiler uses the Slow Slew Rate setting and ignores the Turbo Bit setting.

ACF global project option syntax:

TURBO_BIT = (ON|OFF)

ACF logic option syntax:

<name>: TURBO_BIT = (ON|OFF|DEFAULT|NULL)


two's complement glossary definition
two’s complement

A system of representing binary numbers in which the negative of a number is equal to its inverse plus 1. Arithmetic operators in AHDL assume that groups they operate on are a two’s complement binary number. In VHDL, you must declare a two’s complement binary number with a signed data type.


type glossary definition
type (VHDL)

Specifies characteristics for signals, variables, and constants with a set of values and a set of operations. Types are described with Type Declarations, which define the name, values, and operations of a type. MAX+PLUS II supports the following types:

Type:	Description:

Scalar	Hold at most one value at a time. Supported Scalar types include Integer and Enumerated types.

Composite	Hold multiple values. Composite types include Array and Record types.


unary glossary definition
unary

An arithmetic operator that operates only on one operand.


user libraries glossary definition
user libraries

One or more directories that contain your own megafunctions, macrofunctions, Symbol Files (.sym), AHDL Include Files (.inc), or pre-compiled, user-defined VHDL packages.

The Compiler automatically searches for these user-specified libraries when it compiles a project. The Compiler’s VHDL Netlist Reader Settings command (Interfaces menu) specifies VHDL design libraries for the current project. You can specify which directories contain your other user libraries with the User Libraries command (Options menu) in any MAX+PLUS II application.


variable glossary definition
variable

A name that represents a node. In AHDL, a variable can also represent a state machine or an instance of a primitive, megafunction, or macrofunction and is declared in the Variable Section. In VHDL, variables have a single current value, and are declared and used only in processes and subprograms. A VHDL variable is declared with a Variable Declaration; the value of a variable can be modified with a Variable Assignment Statement.


VCC glossary definition
VCC

A high-level input voltage represented as a high (1) logic level in binary group values.

In an AHDL Text Design File (.tdf), VCC is a predefined constant and keyword, and the default active node value. In a VHDL Design File (.vhd), VCC is represented by '1'. In a Graphic Editor file, VCC is a primitive symbol. VCC is represented as a high (1) logic level in the Simulator and Waveform Editor.


Vector File (.vec) glossary definition
Vector File (.vec)

An ASCII file (with the extension .vec) that contains vectors that specify the logic levels of input nodes in a project. The Simulator uses this file to test the logical operation of the project; the Programmer and Simulator can also use a Vector File for functional testing.

In addition, a Vector File can also be converted into a Waveform Design File (.wdf) for design entry.


vector glossary definition
vector

A vector specifies the logic levels for an individual node within a project. The Simulator uses vectors to simulate the behavior of the project; the Programmer and Simulator use vectors for functional testing.

Vectors for simulation and functional can be defined in Vector Files (.vec) or Simulator Channel Files (.scf). Functional testing vectors can also be stored in programming files.

Vectors for design entry can be defined in a Waveform Design File (.wdf).


Verilog glossary definition
Verilog HDL

A Hardware Description Language (HDL).

You can generate an EDIF 2 0 0 or 3 0 0 netlist file from a Verilog HDL design that has been processed with a Verilog HDL synthesis tool, then import the file into MAX+PLUS II as an EDIF Input File (.edf). The MAX+PLUS II Compiler can also generate a Verilog Output File (.vo) that contains functional and timing information for simulation with a standard Verilog HDL simulator.


Verilog Netlist Writer glossary definition
Verilog Netlist Writer

The Compiler module that produces a Verilog Output File (.vo) for use with an industry-standard Verilog HDL simulator. It also generates an optional Standard Delay Format Output File (.sdo) that contains timing delay information.


Verilog Output File (.vo) glossary definition
Verilog Output File (.vo)

A Verilog Hardware Description Language (HDL) standard netlist file (with the extension .vo) that is generated by the Verilog Netlist Writer module of the Compiler. This file can be exported to an industry-standard Verilog HDL simulator for simulation.


VHDL glossary definition
VHDL

Very High Speed Integrated Circuit (VHSIC) Hardware Description Language.

You can create a VHDL Design File (.vhd) with the MAX+PLUS II Text Editor or any standard text editor and compile it directly with MAX+PLUS II. You can also generate an EDIF 2 0 0 or 3 0 0 netlist file from a VHDL design that has been processed with a VHDL synthesis tool, then import the file into MAX+PLUS II as an EDIF Input File (.edf). The MAX+PLUS II Compiler can also generate a VHDL Output File (.vho) that contains functional and timing information for simulation with a standard VHDL simulator.


VHDL Design File (.vhd) glossary definition
VHDL Design File (.vhd)

An ASCII text file (with the extension .vhd) written in the Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL). VHDL Design Files can be compiled by the MAX+PLUS II Compiler.


VHDL Memory Model Output File (.vmo) glossary definition
VHDL Memory Model Output File (.vmo)

A Compiler-generated VHDL standard netlist file (with the extension .vmo) that contains simulation models written in the Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL). The Compiler automatically generates a VHDL Memory Model Output File for the project when it generates an EDIF Output File (.edo) that contains one or more RAM or ROM blocks.


VHDL Netlist Reader glossary definition
VHDL Netlist Reader

The portion of the Compiler Netlist Extractor module that converts a Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) Design File (.vhd) into a MAX+PLUS II-compatible format.


VHDL Netlist Writer glossary definition
VHDL Netlist Writer

The Compiler Module that produces a Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) Output File (.vho) for use with any industry-standard VHDL simulator. It also generates an optional Standard Delay Format Output File (.sdo) that contains timing delay information..


VHDL Output File (.vho) glossary definition
VHDL Output File (.vho)

A Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) standard netlist file (with the extension .vho) that is generated by the VHDL Netlist Writer module of the Compiler. This file can be exported to an industry-standard VHDL simulator for simulation. A VHDL Output File cannot be compiled with the MAX+PLUS II Compiler.


VITAL glossary definition
VITAL (VHDL Initiative Toward ASIC Libraries)

An industry-standard format for Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) simulation libraries.

MAX+PLUS II provides VHDL cell simulation models that are VITAL-compliant. In addition, the EDIF, VHDL, and Verilog Netlist Writer modules of the MAX+PLUS II Compiler can generate an optional Standard Delay Format (SDF) Output File (.sdo) for use with VITAL-compliant simulation libraries.


Waveform Design File (.wdf) glossary definition
Waveform Design File (.wdf)

A graphical waveform design file (with the extension .wdf) created with the MAX+PLUS II Waveform Editor. This file represents logic with high (1), low (0), undefined (X), and high-impedance (Z) waveforms. It can also include state machines with waveforms that represent different state names.


waveform interval glossary definition
waveform interval

In the Waveform Editor, an interval is a segment of a node or group waveform that represents its logic level or state name over a specific period of time.


wildcard characters glossary definition
wildcard characters

Characters used as shorthand notation in pattern matching, to search for text or list node, to group or file names.

Character:	Finds:

?	A single character.

*	Zero or more characters. For example, A*B finds AB and all text strings that start with A and end with B.

The following wildcard characters are available only with the Find Text and Search & Replace commands (Utilities menu).

Character:	Finds:

^?	? (question mark)

^*	* (asterisk)

^^	^ (caret)


wire loop glossary definition
wire loop

A node (wire) that crosses the boundaries between hierarchical design files and feeds back to itself without passing through any logic.


wirelist glossary definition
wirelist

An ASCII file that contains timing and connectivity information for a design. A wirelist allows a design file to be used with design and simulation tools other than the one with which it was created.


WYSIWYG logic synthesis style glossary definition
WYSIWYG logic synthesis style

The Altera-provided style that directs the Logic Synthesizer to change the logic in your project as little as possible during compilation.

The WYSIWYG (what you see is what you get) style avoids removing or inserting additional logic, and turns off many logic synthesis options that might help a project to fit. However, if you wish to implement logic as you have entered it in your design files, this style preserves your logic, including inefficient and/or redundant logic, as much as possible.


Xilinx Netlist Format (XNF) File (.xnf) glossary definition
Xilinx Netlist Format (XNF) File (.xnf)

A netlist file (with the extension .xnf) generated by Xilinx software. XNF Files that are generated by running the Xilinx LCA2XNF utility can be compiled directly by the MAX+PLUS II Compiler. An XNF File can define all logic in a project, or be incorporated at the bottom level in a hierarchical project.


XNF Netlist Reader glossary definition
XNF Netlist Reader

The portion of the Compiler Netlist Extractor module that converts a Xilinx Netlist Format File (.xnf) into a MAX+PLUS II-compatible format. The LCA2XNF utility must be run with the -g option (for XACT version 4.0) or the -g -v options (for XACT version 5.0) to generate an XNF File that is compatible with MAX+PLUS II.


XOR Synthesis glossary definition
XOR Synthesis

A logic minimization option. When XOR Synthesis is on, the Compiler’s Logic Synthesizer module minimizes logic by creating new XOR gates that feed combinatorial (non-registered) logic cells. These XOR gates can then be efficiently implemented in the XOR gates in MAX 5000, MAX 7000, and MAX 9000 logic cell architectures. When this option is off, the Logic Synthesizer will never create new XOR gates for combinatorial logic cells; however, glitches are less likely to occur.

Since the Logic Synthesizer always uses existing XOR gates when appropriate, this logic option only controls the creation of new XOR gates.

ACF logic option syntax:

<name>: XOR_SYNTHESIS = (ON|OFF|DEFAULT|NULL)


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Entries that should have MAX 7000S references:

BitBlaster

COM or RS-232 port

device

device family

device option

I/O cell and I/O Cell Register

Definitions after this point are used in help panels but are not in the alpha list of glossary entries because they do not have a definition that is useful outside the context of a command or procedure (or whatever)

----------------------------END OF NON-TRANSLATED TEXT-------------------------------------


special characters glossary definition
special characters

The following special characters are available in the Find Text and Search & Replace commands (Utilities menu) in the Text Editor:

Character:	Finds:

^L, ^l	Page-break (form-feed) character

^N, ^n	End-of-line character

^T, ^t	Tab character

^?	? (question mark)

^*	* (asterisk)

^^	^ (caret)


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Note: In the K keywords, you must always use neutral double and single quotation marks. The MicroSoft Help Compiler does not process left and right quotation marks properly when they occur in the K keywords.

----------------------------END OF NON-TRANSLATED TEXT-------------------------------------


Use cross-reference shown in list of keywords to find information

Information on this topic is given under a different search keyword. Choose Search again and go to the keyword shown in parentheses in the list of keywords for information.


---------------------BEGINNING OF NON-TRANSLATED TEXT---------------------------------

Temporary place for New Entries

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memory bit and memory word glossary definitions
memory bit and memory word

A memory bit is an individual memory address in a memory (i.e., RAM or ROM) block.

A memory word is a group of memory bits in a RAM or ROM block.

For example, the content5_[4..0] memory word defines a byte of memory in which the individual memory bits are content5_4, content5_3, content5_2, content5_1, and content5_0.


memory segment glossary definition
memory segment or segment

The physical implementation of memory (i.e., RAM or ROM) in a device. A memory segment contains a sequence of memory bits corresponding to an address range.

In FLEX 10K devices, a memory segment consists of that portion of a bit-slice of a memory which is implemented in a single embedded cell. Each embedded cell implements up to 256 bits of memory. Multiple memory segments may be needed to create a single memory block.


parameter or parameterized glossary definition
parameter or parameterized

A parameter is an attribute of a logic function that determines the logic created or used to implement the function, i.e., a characteristic that determines the size, behavior, or silicon implementation of a function. The parameter information can be used to determine the actual primitives and other subdesigns needed to implement the logic of the function.

A parameterized function is a function whose behavior is controlled by one or more parameters. Some logic functions, such as the functions in the Library of Parameterized Modules (LPM), are inherently parameterized and require parameter values to be assigned.

Parameters can be assigned to any individual instance of a megafunction in MAX+PLUS II to control its size or implementation. Some parameters can also be applied to old-style macrofunctions to determine their style of implementation. MAX+PLUS II also allows you to assign global, project-wide default values for parameters.


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New Logic Options for 6.0

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Hierarchical Synthesis option glossary definition
Hierarchical Synthesis option

A logic synthesis option that directs the Compiler’s Logic Synthesizer to place logic cells around the input and output ports of a mega- or macrofunction, which prevents logic synthesis from merging logic from one mega- or macrofuntion to another.

When this option is turned on, the input and output ports of the macrofunction are observable in simulation and timing analysis.

This option will not insert an additional logic cell on the output of a function that is already implemented in a logic cell (e.g., a DFF).

This option is available only in multi-level synthesis.

ACF logic option syntax:

<name>: HIERARCHICAL_SYNTHESIS = (ON|OFF|DEFAULT|NULL)


Implement as Output of Logic Cell option glossary definition
Implement as Output of Logic Cell option

A logic synthesis option that directs the Compiler’s Logic Synthesizer to implement the output(s) of a primitive, megafunction, or macrofunction in a logic cell; the Compiler inserts a logic cell if one is not already used.

If this option is applied to a mega- or macrofunction, it operates on all outputs of the mega- or macrofunction.

If this option is applied to a logic function that is not already implemented in a logic cell, it forces the function to be the output of a logic cell, i.e., if it is applied to an AND2, it forces the AND2 to be the output of a logic cell, which is likely to result in increased resource usage.

When this option is turned on, the function's outputs are observable in simulation and timing analysis.

This option will not insert an additional logic cell on a function that is already implemented in a logic cell (e.g., a DFF).

This option is available only in multi-level synthesis.

ACF logic option syntax:

<name>: IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = (ON|OFF|DEFAULT|NULL)


Implement in EAB option glossary definition
Implement in EAB option

A FLEX 10K logic synthesis option that directs the Compiler’s Logic Synthesizer to implement the function in an EAB rather than in logic cell(s).

This option is ignored for logic functions that are not purely combinatorial.

You can turn on the Automatic Implement in EAB option in the Global Project Logic Synthesis dialog box (Assign menu) to set this option globally.

ACF global project option syntax:

AUTO_IMPLEMENT_IN_EAB = (ON|OFF)

ACF logic option syntax:

<name>: IMPLEMENT_IN_EAB = (ON|OFF|DEFAULT|NULL)


Insert Additional Logic Cell option glossary definition
Insert Additional Logic Cell option

A logic synthesis option that directs the Compiler’s Logic Synthesizer to insert an additional logic cell after the output(s) of the logic function to which it is applied, provided that the function already consumes one logic cell.

This option allows you to insert logic cells for routing purposes without actually adding LCELL primitives to your design file. If this option is applied to a macrofunction, it operates on all outputs of the macrofunction. If this option is applied to a logic function that is not already implemented in a logic cell(s), it is ignored, i.e., if it is applied to an AND2, it does not force the AND2 to be the output of a logic cell.

ACF logic option syntax:

<name>: INSERT_ADDITIONAL_LOGIC_CELL = (ON|OFF|DEFAULT|NULL)


Use LPM for AHDL Operators option glossary definition
Use LPM for AHDL Operators option

A logic synthesis option that directs the Compiler’s Logic Synthesizer to replace AHDL operators in Boolean expressions with LPM functions, e.g., substitute lpm_add_sub for AND operators.

ACF logic option syntax:

<name>: USE_LPM_FOR_AHDL_OPERATORS = (ON|OFF|DEFAULT|NULL)


Automatic Open-Drain Pins option glossary definition
Automatic Open-Drain Pins option

A logic synthesis option that directs the Compiler’s Logic Synthesizer to implement appropriate pins as open-drain pins.

ACF global project option syntax:

AUTO_OPEN_DRAIN_PINS = (ON|OFF)


Ignore SOFT Buffers option glossary definition
Ignore SOFT Buffers option

A logic synthesis option that directs the Compiler’s Logic Synthesizer to ignore manually instantiated SOFT buffers.

When this option is turned on, the Compiler also ignore SOFT buffers that are automatically inserted for the AND operators in AHDL (these SOFT buffers are inserted only if the Use LPM for AHDL Operators logic option is turned off).

ACF global project option syntax:

IGNORE_SOFT_BUFFERS = (ON|OFF|DEFAULT|NULL)


MAX+PLUS II Glossary
Glossary

Select the first letter of a glossary term to jump to the section of the list starting with that letter:

A B C D E F G H I J K L M N O P Q R S T U V W X

A

A+PLUS

absolute path

absolute time vector pattern

ACF

Active Parallel Down

Active Parallel Up

Active Serial

active-high node

active-low node

adding operator

ADF

AFD

AHDL

alias

Altera Design File (.adf)

Altera Field Diagnostic

Altera Hardware Description Language

Altera Megafunction Partner Program (AMPP)

ancillary file

APD

Application Control Menu box

APU

arbitrary group (or bus) name

architecture

area marquee

area selection (Floorplan Editor)

area selection (Graphic & Symbol Editors)

area selection (Hierarchy Display)

area selection (Waveform Editor)

arithmetic expressions (AHDL)

arithmetic operator

array

array signal

arrow keys

AS

ASCII

Assembler

Assignment & Configuration File (.acf)

Assignment & Configuration Output File (.aco)

assignment (AHDL & VHDL)

assignment (resource)

asynchronous input

authorization code

autoexec.bat file

automatic device selection

Automatic Open-Drain Pins option

automatic partitioning

B

back-annotation

background process

Backus-Naur Form

balloon text

batch mode

BGA

binary

bit-slice configuration

BIT0 option

BitBlaster

BitBlaster dipswitch settings

BNF

Boolean logic

branch button

branches

breakpoint

breakpoint operator

bulletin board service

buried node

buried register

bus

bus name

bus pinstub

Button 1

Button 2

C

Carry Chain option

Cascade Chain option

cell

Channel File (.scf)

checksum

chip

Classic

Clear

Clipboard

clique

Clock

Clock Enable

CNF

column

COM port

combinatorial feedback

combinatorial output

Command File (.cmd)

comment

comparator

Compiler Netlist Extractor

Compiler Netlist File (.cnf)

component

cone of logic

Configuration EPROM

configuration

configuration scheme

connected pin group

connected pin primitives

connection arrow

connection dot

construct

context-sensitive help

continuity checking

CQFP

CRC

cutoff node

cyclic redundancy check

D

DAT file

Database Builder

database

database files

De Morgan’s Inversion Theorem

decimal

Decompose Gates option

default setting

default Simulator Channel File (.scf)

default timing tagging

delay chain

delimiter

Design Doctor

Design Entity

design file

design library (VHDL)

Design Library System File (.dls)

destination node

Device Model File (.dmf)

device

device assignment

device family

device option

DIP

DMF

Document Control Menu box

dual I/O feedback

dual-purpose pins

dual-range group or bus name

Duplicate Logic Extraction option

dynamic models

E

EAB

EC

EC number

EDIF

EDIF Command File (.edc)

EDIF Input File (.edf)

EDIF Netlist Reader

EDIF Netlist Writer

EDIF Output File (.edo)

EEPROM

elaboration

electronic bulletin board service

Embedded Array Block

embedded cell (EC)

embedded cell number

End-of-File (EOF)

End-of-Line (EOL)

entity

entity name

EPLD

EPROM

evaluated function

excitation equation

expander networks, flipflops & latches

expander product term

extension

external connection pin primitive

external connection pinstub

F

family-specific mega- or macrofunction

fan-in

fan-out

Fast logic synthesis style

FastTrack Interconnect

file icon

filename

filename extension

FILTER primitive

Fit File (.fit)

Fitter

Fitter Input File (.fin)

FLASHlogic

FLEX Download Cable

FLEX 8000

FLEX 10K

flipflop

fmax

Function Prototype

functional comparison rules

functional simulation

functional Simulator Netlist File (.snf)

Functional SNF Extractor

G

gated Clock

GDF

glitch

global logic cell

global signal

GND

Graphic Design File (.gdf)

graphic selection

Gray code

grid unit

group

group information area

group name

H

hard logic function

help panel

hexadecimal

Hexadecimal (Intel-Format) File (.hex)

hierarchical node or symbol name

Hierarchical Synthesis option

Hierarchy Interconnect File (.hif)

hierarchy tree

HIF

History File (.hst)

hold time

I

I/O cell (IOC) number

I/O cell register

I/O feedback

I/O type

ICR

identifier

Ignore SOFT Buffers option

Implement as Output of Logic Cell option

Implement in EAB option

in-circuit reconfigurability

in-system programmability

Include File (.inc)

Insert Additional Logic Cell option

insertion point

instance

interactive mode

interval

ISP

J

J-lead

JCF

JEDEC File (.jed)

JLCC

JTAG boundary-scan testing

JTAG chain

JTAG Chain File (.jcf)

jump

K

keyword

L

LAB

latch

Latch Enable

LC

LC number

LCA2XNF utility

least significant bit

LEF

LEF2AHDL Converter

library

library of parameterized modules

Library Mapping File (.lmf)

license file

line style

linked simulation

linked Simulator Netlist File (.snf)

Linked SNF Extractor

LMF

location

Log File (.log)

Logic Array Block

logic cell (LC)

logic cell number

logic cell Turbo Bit

logic element

Logic Equation File (.lef)

logic function

logic level

logic option

logic primitive

Logic Programmer card

logic synthesis style

Logic Synthesizer

logical operator

LPM

LP6 Logic Programmer card dipswitch settings

LSB

M

macrocell

macrofunction

Master Programming Unit

MAX 5000

MAX 7000

MAX 9000

MAX+PLUS (DOS)

MAX+PLUS II

MAX+PLUS II Message File (.mmf)

max2inc

max2lib

maxplus2.idx file

maxplus2.ini file

Mealy state machine

megafunction

memory bit

Memory Initialization File (.mif)

Memory Initialization Output File (.mio)

memory word

Message Text File (.mtf)

metastability

metastable

MIF

Minimization option

MMF

Moore state machine

most significant bit

mouse pointer

MPLD

MPU

ms

MSB

MTF

multi-Clock network

multi-device JTAG chain

multi-level Clock

Multi-Level Factoring option

multi-level synthesis

multi-window application

multiplying operator

N

name characters

nesting

net ID number

network

nil-period oscillation

nil-time glitch

node

Node Database File (.ndb)

node information area

node name

node type

Normal logic synthesis style

NOT Gate Push-Back option

ns

NTSC

O

object (Graphic Editor)

object-by-object selection

octal

one-hot encoding

one’s complement

operand

operator

Optimize option

OrCAD Library File (.lib)

OrCAD Schematic File (.sch)

oscillation

Output Enable

P

<project name>.ini file

<project name>.ink file

package

parallel expanders

parameter

parameterized module

part

Partitioner

Passive Parallel Asynchronous

Passive Parallel Synchronous

Passive Serial

PDIP

PGA

PIA

pin

pin number

pinstub

pinstub name

pixel

PLAD3-12

PLCC

pldgates.lib

PLDshell Plus

PLF

PLL

PLS-ES

POF

pointer

port

port (EDIF)

power object

PPA

PPS

PQFP

Preset

primitive

primitive array

Probe & Resource Assignment Backup File (.prk)

Probe & Resource Assignment File (.prb)

probe

process

product term

Programmable Interconnect Array

Programmer card

Programmer Log File (.plf)

Programmer Object File (.pof)

programming file

programming unit

project

propagation delay

property construct

PS

Q

QFP

R

race condition

radix

range

Raw Binary File (.rbf)

read.me file

Reduce Logic option

Refactorization option

register

Register Optimization option

register packing

registered feedback

registered output

registered performance

relational operators

relative path

relative time vector pattern

Report File (.rpt)

reserved resources

Reset signal

resource

resource assignment

Resynthesize Network option

ripple Clock

RISEFALL primitive

row

RQFP

RS-232 port

rubberbanding

S

SAM+PLUS

SCF

SCF output overwriting rules

SDF Output File (.sdo)

secondary input

Security Bit

selection, area

selection, object-by-object

sequential group (or bus) name

Serial Bitstream File (.sbf)

setup time

shareable expanders

shared expanders

sheet

sheet size

SIF

sign-extend

Simulator Channel File (.scf)

Simulator Initialization File (.sif)

Simulator Netlist File (.snf)

Simulator Netlist File primitive

single-range group (or bus) name

single-window application

site license

slew rate

Slow Slew Rate option

SMF

SNF

SOF

SOFT Buffer Insertion option

software guard

SOIC

source node

spike

SRAM Object File (.sof)

Standard Delay Format Output File (.sdo)

standard synthesis

state

state bit

state control equation

state machine

State Machine File (.smf)

state name

state transition

static hazard

status bar

string value

sub-project

subdesign

subdesign name

Subfactor Extraction option

sum-of-products

super-project

Symbol File (.sym)

symbol ID number

symbolic name

synchronous outputs

synthesized logic cells

T

.time variable

Table File (.tbl)

Tabular Text File (.ttf)

tco

TDF

ternary operator

Text Design Backup File (.tdk)

Text Design Export File (.tdx)

Text Design File (.tdf)

Text Design Output File (.tdo)

text selection

three-way checkbox

time-slice

time unit

Timing Analyzer Output File (.tao)

timing assignment

timing cut

timing simulation

timing Simulator Netlist File (.snf)

Timing SNF Extractor

token files (.tok)

toolbar

tool palette

tpd

TQFP

tri-state buffer

truncate

tsu

TTF

ttl.lib file

Turbo Bit

two’s complement

type

U

unary

us

Use LPM for AHDL Operators option

user libraries

V

variable

VCC

vector

Vector File (.vec)

Verilog HDL

Verilog Netlist Writer

Verilog Output File (.vo)

VHDL

VHDL Design File (.vhd)

VHDL Memory Model Output File (.vmo)

VHDL Netlist Reader

VHDL Netlist Writer

VHDL Output File (.vho)

VITAL

W

Waveform Design File (.wdf)

waveform interval

WDF

wildcard characters

wire loop

wirelist

WYSIWIG logic synthesis style

X

Xilinx Netlist Format File (.xnf)

XNF Netlist Reader

XOR Synthesis option

New Entries

adding operators

Altera CompuServe Forum

Altera Customer Service Hotline

Altera Electronic Mail Address

Altera FTP Site

Altera Megafunction Partner (AMP) Program

Altera Technical Support Hotline

Altera World-Wide Web (WWW) Site

arithmetic operators

Button 1

Button 2

delimiter

dual-range group

elaboration

Embedded Array Block (EAB)

embedded cell (EC)

embedded cell (EC) number

evaluated function

FLEX 10K

JCF

JTAG Configuration File (.jcf)

License File (.dat)

megafunction

memory bit

Memory Initialization File (.mif)

Memory Initialization Output File (.mio)

memory word

MIF

MIO

multiplying operators

parameter

parameterized

pinstub alias

Serial Vector Format (.svf)

Standard Delay Format (SDF) Output File (.sdo)

status bar

Token File (.tok)

toolbar

tool palette

VHDL Memory Model Output File (.vmo)

VITAL


A+PLUS glossary definition
A+PLUS

Altera’s Programmable Logic User System. A+PLUS is a set of computer programs and hardware support products for designing and implementing custom logic circuits with Altera Classic devices. Altera Design Files (.adf) and State Machine Files (.smf) created for A+PLUS are automatically converted and processed with the MAX+PLUS II Compiler. The MAX+PLUS II Programmer can program Classic devices with JEDEC Files (.jed) created by A+PLUS.

A+PLUS is no longer offered by Altera. All new designs should be created with MAX+PLUS II.


absolute path glossary definition
absolute path

In computer directories, an absolute path is a pathname that is relative to the top-level directory on a drive. An absolute pathname drives always begins with the drive name plus a colon (e.g., c:).

In node and symbol names, an absolute path is a hierarchy pathname that is relative to the top-level design file of a project. The hierarchical node or symbol name of an absolute path begins with a vertical bar (|) and the net ID number or instance name of a logic function in the top-level design file.


absolute time vector pattern glossary definition
absolute time vector pattern

A series of logic values that specify the exact time for applying a set of input vectors for simulation, and optionally specify expected output levels. Absolute time vector patterns eliminate the need for Start and Interval Sections in the Vector File (.vec); Stop Sections are optional.


Active Parallel Down (APD) glossary definition
Active Parallel Down (APD)

A configuration scheme in which a byte-wide parallel PROM loads the design data into a FLEX 8000 device. The FLEX 8000 device first generates an address; the PROM subsequently returns the next byte of data. Addresses are generated by the FLEX 8000 device sequentially in descending order (3FFFFh to 00000h).

MAX+PLUS II automatically generates a Hexadecimal (Intel-Format) File (.hex) that contains the data for configuring a FLEX 8000 device in an APD configuration scheme.


Active Parallel Up (APU) glossary definition
Active Parallel Up (APU)

A configuration scheme in which a byte-wide parallel PROM loads the design data into a FLEX 8000 device. The FLEX 8000 device first generates an address; the PROM subsequently returns the next byte of data. Addresses are generated by the FLEX 8000 device sequentially in ascending order (00000h to 3FFFFh).

MAX+PLUS II automatically generates a Hexadecimal (Intel-Format) File (.hex) that contains the data for configuring a FLEX 8000 device in an APU configuration scheme.


Active Serial (AS) glossary definition
Active Serial (AS)

A configuration scheme in which a serial EPROM loads the design data into a FLEX 8000 device.

The Compiler automatically generates a Programmer Object File (.pof) for programming serial EPROM devices, such as the EPC1213 Configuration EPROM, whenever a FLEX 8000 project is compiled.

You can also use the Combine Programming Files command (File menu) in the Compiler or Programmer to generate POFs and Hexadecimal (Intel-Format) Files (.hex) that contain the data for AS configuration of multiple FLEX 8000 devices.


active-high node glossary definition
active-high node

A node that is activated when it is assigned a value of one (1 in AHDL or '1' in VHDL) or VCC (e.g., ena, clk).


active-low node glossary definition
active-low node

A node that is activated when it is assigned a value of zero (0 in AHDL or '0' in VHDL) or GND (e.g., clrn, prn, oen). In AHDL design files, an active-low node should be assigned a default value of VCC with the Defaults Statement.


adding operator glossary definition
adding operator

An operator that performs arithmetic addition and subtraction operations on groups and numbers.

In AHDL, supported adding operators in Boolean expressions consist of the prefix and binary plus (+) and minus (-) symbols. Supported adding operators in arithmetic expressions consist of the prefix and binary plus (+) and minus (-) symbols. Unary plus and minus symbols are used as prefixes to indicate positive and negative values. Binary plus and minus symbols are used between groups and numbers to indicate addition and subtraction.

In VHDL, supported adding operators consist of the prefix and binary plus (+) and minus (-) symbols and the concatenation operator (&). The concatenation operator (&) is predefined for any one-dimensional array type.

See Section 7.2.3: Adding Operators in the IEEE Standard VHDL Language Reference Manual for more information.


ALIAS glossary definition
alias

A user-defined alternate name for an EDIF keyword. Aliases can only be used with level 1 EDIF keywords. Other EDIF keywords or previously defined aliases cannot be used. In addition, aliases must follow the same syntactic rules as EDIF identifiers.


Altera Applications Department glossary definition
Altera Applications Department

The Altera Applications Department is available to help you with technical questions about Altera’s MAX+PLUS II development software and devices:

Altera Corporation

Applications Department

2610 Orchard Parkway

San Jose, CA  95134-2020

Technical Support Hotline:	(800) 800-EPLD or (408) 894-7000

Fax:	(408) 954-0348

E-mail address:	sos@altera.com

Electronic bulletin board service (BBS):	(408) 954-0104


Altera CompuServe Forum glossary definition
Altera CompuServe Forum

Altera provides the Altera Forum on CompuServe. You can use the forum to leave messages for other users or the Altera Applications Department, hold interactive conferences, or upload and download library files.

To access the Altera Forum, type go altera at any CompuServe command prompt.


Altera Customer Service Hotline glossary definition
 Altera Customer Service Hotline

From the United States and Canada, you can call the Altera Customer Service Hotline for help with non-technical customer service issues by dialing (800) SOS-EPLD or (408) 894-7000 between the hours of 7:30 a.m. and 5:00 p.m. Pacific Time.

From other locations, call (408) 894-7000 or your local Altera distributor.

You can also reach the Customer Service Department by fax at (408) 954-8186


Altera Design File (.adf) glossary definition
Altera Design File (.adf)

An ASCII-format file (with the extension .adf) for Boolean equation entry, used with Altera’s A+PLUS software. ADFs use a netlist format and Boolean equations to describe a design. The MAX+PLUS II Compiler automatically translates an ADF into a Compiler Netlist File (.cnf) during project compilation.

An ADF is also generated when a State Machine File (.smf) is compiled.


Altera electronic bulletin board service (BBS) glossary definition
Altera electronic bulletin board service (BBS)

An Altera Applications Department bulletin board service that provides continuous, round-the-clock access to up-to-date device and development tool information, electronic application notes and briefs, data sheet updates, customer newsletters, and software utility programs. The BBS supports baud rates of 1200, 2400, 4800, 9600, and 14400.

Telephone: 	(408) 954-0104

Refer to Appendix B: Altera Support Services in MAX+PLUS II Getting Started for information on logging onto the BBS.


Altera electronic mail address glossary definition
Altera electronic mail address

You can use Internet e-mail to send technical questions about devices and software to the Altera Applications Department. Inquiries sent by e-mail receive the same priority treatment as telephone calls, but since e-mail through the Internet can be delayed, Altera recommends using either the technical support hotline or fax for urgent issues.

Address your e-mail to the Altera Applications Department to sos@altera.com.


Altera Express glossary definition
Altera Express

An automated fax-back system that provides continzuous, round-the-clock access to up-to-date Altera documents, including the most commonly requested data sheets, application notes, and application briefs. Documents can be sent to any fax machine in the USA or Canada; international callers can retrieve information by calling from a fax telephone.

Telephone:

North America:	(800) 5-ALTERA

International:	(408) 894-7850


Altera Field Diagnostic (AFD) glossary definition
Altera Field Diagnostic (AFD)

An Altera utility that checks that the programming hardware is calibrated, the programming card is recognized, and the programming voltages are within tolerance.

All functions previously provided by this stand-alone utility are available via the Test button in the Hardware Setup dialog box available in the Programmer or Simulator.


Altera FTP Site glossary definition
Altera FTP site

Altera maintains a 24-hour file transfer protocol (FTP) site for instant access to the latest Altera product information. On-line versions of Altera application notes and briefs, recent quarterly newsletters, and software utility programs are available from the FTP site. You can also use the FTP site to transfer files to and from the Altera Applications Department for technical support and review.

To access the Altera FTP site, use your FTP software to log onto ftp.altera.com using anonymous as your user name, and your e-mail address as the password.


Altera Hardware Description Language (AHDL) glossary definition
Altera Hardware Description Language (AHDL)

A high-level, modular language that is completely integrated into the MAX+PLUS II system. You can create AHDL Text Design Files (.tdf) with the MAX+PLUS II Text Editor or any standard text editor, then compile, simulate, and program your projects within MAX+PLUS II. AHDL supports Boolean equation, state machine, conditional, and decode logic. AHDL also allows you to create and use parameterized functions, and includes full support for functions in the Library of Parameterized Modules (LPM).

Text Design Export files (.tdx) and Text Design Output Files (.tdo) generated by the MAX+PLUS II Compiler are also written in AHDL syntax.


Altera Literature Department glossary definition
Altera Literature Department

Altera Corporation

Literature Department

2610 Orchard Parkway

San Jose, CA 95134-2020

Telephone: (408) 894-7144

Fax: (408) 954-0348


Altera Marketing Department glossary definition
Altera Marketing Department

Altera Corporation

Marketing Department

2610 Orchard Parkway

San Jose, CA 95134-2020

Telephone: (408) 894-7000

Fax: (408) 248-6924


Altera Megafunction Partner (AMP) Program glossary definition
Altera Megafunction Partner Program (AMPP)

A program that offers support to third-party vendors to create and distribute megafunctions for use with MAX+PLUS II. You must enter an authorization code in your maxplus2.ini file to enable a particular megafunction for implementation in a design file.

Additionally, some vendors may provide the option to view and edit a megafunction design file.

For information on current AMPP vendors and available megafunctions, contact Altera Marketing.


Altera Technical Support Hotline glossary definition
Altera Technical Support Hotline

From the United States and Canada, you can reach the Altera Technical Support Hotline by dialing (800) 800-EPLD or (408) 894-7000 between the hours of 7:30 a.m. and 5:00 p.m. Pacific Time.

From other locations, call (408) 894-7000 or your local Altera distributor.


Altera World-Wide Web site glossary definition
Altera World-Wide Web (WWW) site

Altera provides a World-Wide Web (WWW) site for instant access to product information. The site provides an on-line, hypertext environment that allows you to browse through Altera product information, press releases, employment opportunities, and a corporate profile.

To access the Altera World-Wide Web site, point your Web browser software at http://www.altera.com.


ancillary file glossary definition
ancillary file

A file that is associated with a MAX+PLUS II project, but is not a design file in the project hierarchy tree. Most ancillary files also do not contain design logic. User-editable ancillary files with the same filename as the project appear in the Hierarchy Display window. See the following table:

Editable Ancillary Files:	Non-Editable Ancillary Files:

Assignment & Configuration File (.acf)	Compiler Netlist File (.cnf)

Assignment & Configuration Output File (.aco)	Hierarchy Interconnect File (.hif)

Command File (.cmd)	JEDEC File (.jed)

EDIF Command File (.edc)	Node Database File (.ndb)

Fit File (.fit)	Programmer Object File (.pof)

Hexadecimal (Intel-format) File (.hex)	Raw Binary File (.rbf)

History File (.hst)	Serial Bitstream File (.sbf)

Include File (.inc)	Simulator Initialization File (.sif)

JTAG Configuration File (.jcf)	Simulator Netlist File (.snf)

Library Mapping File (.lmf)	SRAM Object File (.sof)

Log File (.log)

Memory Initialization File (.mif)

Memory Initialization Output File (.mio)

Message Text File (.mtf)

Programmer Log File (.plf)

Report File (.rpt)

Simulator Channel File (.scf)

Standard Delay Format (SDF) Output File (.sdo)

Symbol File (.sym)

Table File (.tbl)

Tabular Text File (.ttf)

Text Design Export File (.tdx)

Text Design Output File (.tdo)

Timing Analyzer Output File (.tao)

Vector File (.vec)

VHDL Memory Model Output File (.vmo)


Application Control Menu box glossary definition
Application Control Menu box

The box in the top left corner of the title bar of the MAX+PLUS II window:

Clicking Button 1 on this box opens the Application Control Menu, which contains commands to move, change the size of, and close the MAX+PLUS II window. You can also switch to the Task List. Within MAX+PLUS II, this menu controls the window for the entire MAX+PLUS II program.


arbitrary group (or bus) name glossary definition
arbitrary group (or bus) name

A group name consisting of up to 32 name characters. The group may contain up to 256 individual nodes. Unlike a single- or dual-range group name (e.g., a[4..1] or b[2..0][3..1]) or sequential group name (e.g., (a,b,c) ), an arbitrary group name does not indicate how many members (bits) are included in the group.

The arbitrary group name is used only in Vector Files (.vec), Simulator Channel Files (.scf), and Waveform Design Files (.wdf).


architecture glossary definition
architecture

Describes the behavior, data flow, and/or structure of a VHDL design entity. An architecture is created with an Architecture Body. A single entity can have more than one architecture, e.g., one architecture can describe the behavior of a design, while a second architecture describes the design structure. Configuration Declarations are used to specify which architectures to use for each entity. However, Altera recommends that you have a single architecture for each entity.


area and area selection (in Graphic & Symbol Editors) glossary definition
area and area selection, in Graphic & Symbol Editors

A defined rectangular portion of a Graphic or Symbol Editor file that includes one or more adjacent objects. This area is contained within a rectangular border called an area marquee. You can edit an area in the same way that you edit any object within the area.

Area selection is the process of selecting multiple contiguous objects. Symbols, arcs, circles, diagonal lines, and text blocks must lie completely within the area marquee to be selected. When an orthogonal line crosses the marquee, only the portion within the marquee is selected.


area and area selection (in Floorplan Editor) glossary definition
area and area selection, in Floorplan Editor

A defined rectangular portion of a Floorplan Editor display that includes one or more adjacent pins, nodes, logic cells, or assignment bins. All selected items in the area are highlighted. You can copy, move, or delete an area.

Area selection is the process of selecting multiple contiguous objects. In the Floorplan Editor, such "objects" can consist of adjacent pins, nodes, or logic cells, or one or more assignment bins of the same type.


area and area selection (in Hierarchy Display) glossary definition
area and area selection, in Hierarchy Display

A defined rectangular portion of the Hierarchy Display that includes one or more adjacent filenames or file icons. All selected items in the area are highlighted. You can open or close all the files within a selected area.

Area selection is the process of selecting multiple contiguous objects. As you drag the mouse, a rectangular border called an area marquee is displayed. Filenames and file icons must lie completely within the area marquee to be selected.


area and area selection (in Waveform Editor) glossary definition
area and area selection, in Waveform Editor

A defined rectangular portion of a Waveform Editor file that includes one or more adjacent nodes and groups, whole waveforms, or waveform intervals. You can copy, move, or delete an area.

Area selection is the process of selecting multiple contiguous objects. In the Waveform Editor, such "objects" can consist of adjacent nodes and groups, whole waveforms, or intervals on one or more waveforms.


area marquee glossary definition
area marquee

In the Graphic or Symbol Editors, the rectangular boundary surrounding an area selection, which is created by dragging Button 1 with the Selection tool.

In the Hierarchy Display, the rectangular border that is visible as you drag the mouse to select an area. The marquee is visible only while you are dragging the mouse.


arithmetic expressions glossary definition
arithmetic expressions (AHDL)

Arithmetic expressions in AHDL consist of numbers or constants separated by arithmetic operators and comparators, and optionally grouped within parentheses. Each expression must resolve to a non-negative number.


arithmetic operator glossary definition
arithmetic operator

An operator that performs arithmetic addition and subtraction operations on groups and numbers.

In AHDL, supported arithmetic operators in Boolean expressions consist of the prefix and binary plus (+) and minus (-) symbols. Supported arithmetic operators in arithmetic expressions consist of the prefix and binary plus (+) and minus (-) symbols, as well as AND (&), NAND (!&), XOR ($), XNOR (!$), OR (#), NOR (!#), ternary (?), multiplication (*), division (DIV), modulus (MOD), exponentiation (^), and log base 2 (LOG2). Unary plus and minus symbols are used as prefixes to indicate positive and negative values. Binary plus and minus symbols are used between groups and numbers to indicate addition and subtraction.

In VHDL, supported arithmetic operators consist of the prefix and binary plus (+) and minus (-) symbols, as well as the operators for multiplication (*) and division (/). See Section 7.2.3: Adding Operators and Section 7.2.4: Multiplying Operators in the IEEE Standard VHDL Language Reference Manual for more information.


array signal glossary definition
array signal

An input to a logic function that does not pass through a GLOBAL buffer, i.e., a signal that passes through the array of the device.


arrow keys glossary definition
arrow keys

The Up, Down, Left, and Right Arrow keys on the keyboard.


ASCII glossary definition
ASCII

American Standard Code for Information Interchange. Text editing software used for any MAX+PLUS II text file, e.g., Text Design File (.tdf), Library Mapping File (.lmf), or Vector File (.vec), must conform to this textual data coding system.


Assembler glossary definition
Assembler

The Compiler module that creates one or more Programmer Object Files (.pof), SRAM Object Files (.sof), JEDEC Files (.jed), Tabular Text Files (.ttf), and Hexadecimal (Intel-format) Files (.hex) for programming Altera devices.


assignment glossary definition
assignment

In AHDL and VHDL, assignment refers to the transfer of a value to a symbolic name or group, usually through a Boolean equation. The value on the right side of the equation is assigned to the symbolic name or group on the left.


Assignment & Configuration File glossary definition
Assignment & Configuration File (.acf)

An ASCII file (with the extension .acf) that stores information about probe, pin, location, chip, clique, logic option, timing, connected pin and device assignments, as well as configuration settings for the Compiler, Simulator, and Timing Analyzer for an entire project.

The ACF stores information entered with menu commands in all MAX+PLUS II applications, as well as pin, location, and chip assignments entered in the Floorplan Editor window. You can also edit an ACF manually in a Text Editor window.


Assignment & Configuration Output File glossary definition
Assignment & Configuration Output File (.aco)

An ASCII file (with the extension .aco) that is generated when you generate a Text Design Export File (.tdo) for a project. Each TDO File always has a corresponding ACO File, with one TDO File and one ACO File generated for each device in the project.

An ACO File contains the original assignment information from the Assignment & Configuration File (.acf) that corresponds to the data in the TDO File. Information is stored in the ACF format. However, the node names in the ACO File are changed to match the new node names in the TDO File.

You can use an ACO File as an ACF and use it with a TDO File that has been saved as a Text Design File (.tdf).


asynchronous input glossary definition
asynchronous input

An input signal that is not synchronized to the device Clock. Asynchronous inputs cannot always meet the setup and hold time requirements of the flipflops they feed and can produce reliability problems such as race conditions.


authorization code glossary definition
authorization code

A code that enables MAX+PLUS II applications and features. This code, provided by Altera, is shown on the Altera Registration Card of new MAX+PLUS II systems. Contact Altera Marketing for information on obtaining an updated authorization code or an authorization code for an ES Site License.


autoexec.bat file glossary definition
autoexec.bat file

A DOS system file that is modified during installation of MAX+PLUS II PC-based software. (The original autoexec.bat file is saved as autoexec.bak.) DOS executes this file whenever the PC is booted.


automatic device selection glossary definition
automatic device selection

The process whereby the Compiler automatically selects the device(s) that implement the project most efficiently. You specify the individual devices from which the Compiler can choose with the Auto Device Selection dialog box, which is accessible via the Device command (Assign menu).


automatic partitioning glossary definition
automatic partitioning

The process during which the Compiler automatically divides a project into two or more devices from the same device family. Partitioning is performed along logic cell boundaries. The Compiler attempts to minimize the number of pins used for inter-device communication.


back-annotation glossary definition
back-annotation

The process of copying device and resource assignments made by the Compiler, which are stored in the Fit File (.fit), into the Assignment & Configuration File (.acf) for a project. The back-annotation process preserves the current fit in future compilations.


background process glossary definition
background process

An application or command that can run unattended as you perform another task and which can generate its own set of messages in a Message Processor window. The following MAX+PLUS II applications and commands are background processes:

Compiler

Programmer

Simulator

Timing Analyzer

ACF Reader

Waveform Editor Import Vector File command (File menu)

MAX+PLUS II Project Archive command (File menu)


Backus-Naur Form (BNF) glossary definition
Backus-Naur Form (BNF)

A notational convention used to describe the syntax of MAX+PLUS II text files, hierarchical node and symbol names, and messages. BNF uses the following notation rules:

Characters:	Meaning:

::=	"is defined as"

<...>	identifiers (i.e., variables)

[...]	optional items

{...}	repeated items (zero or more times)

(...)	grouped items

...|...	indicates a choice between items

:n:n	suffix indicates a range (e.g., <name_char>:1:8 means "from 1 to 8 name characters")

Courier font	Literal text in syntax descriptions. Bold Courier font is also sometimes used to help distinguish literal text from italic variables in syntax descriptions.


balloon text glossary definition
balloon text

Pop-up text in the Floorplan Editor that provides information on an item under the mouse pointer, such as a pin, I/O cell, logic cell, embedded cell, or an assignment bin. Information is displayed in the following formats:

<node name> @ <cell number>

<pin name> @ <pin number> (<pin function> (<dedicated pin name>))

where the <pin name> or <cell name> is replaced by the text <none> if no item is assigned to a particular resource. If multiple functions are assigned to the resource, the first two names are listed, followed by the text etc. if there are additional names. In a last compilation floorplan, the text (unrouted) appears after the pin or node name for items that did not fit successfully.


batch mode glossary definition
batch mode

The simulation mode in which Simulator commands are executed from a Command File (.cmd) rather than from on-screen options or menu commands.


BGA glossary definition
BGA

Ball-Grid Array. A device package offered by Altera.


binary glossary definition
binary

The base 2 number system (radix). Binary digits are 0 and 1.

In AHDL, binary numbers are indicated with the following notation:

B"<series of 0, 1, and X characters>"

where X="don’t care." Example: B"0110X1X10"

In VHDL, binary numbers are indicated with the following notation:

2#<series of 0, 1, and _ characters>#

where underline characters inserted between digits act as separators and do not affect the value of the number. Example: 2#1111_1111#


BIT0 option glossary definition
BIT0 option

An option that prevents certain warning messages if you use the lowest-numbered bit of a group as anything other than the least significant bit (LSB).

When you declare a group with a range of numbers, the first number listed is always the most significant bit (MSB), the last is always the LSB. If you specify a range in ascending order, a warning message is issued unless you have used the BIT0 option to specify that the lowest numbered bit is the MSB. If you set the BIT0 option to MSB, a warning message is generated if you specify a range in descending order. If you set BIT0 to ANY, you may specify ranges in either ascending or descending order without receiving a warning.


bit-slice configuration glossary definition
bit-slice configuration

A type of device configuration circuit in which up to eight FLEX 8000 and/or FLEX 10K devices are simultaneously configured by a parallel data source, e.g., a parallel EPROM or mass storage device. Each bit of configuration data provided by the byte-wide parallel data source is directed to a separate FLEX 8000 or FLEX 10K device.


BitBlaster glossary definition
BitBlaster

A serial download cable that allows both PC and workstation users to program and configure devices in-system. The BitBlaster provides programming support for MAX 9000 and FLASHlogic devices, and configuration support for FLEX 8000, FLEX 10K, and FLASHlogic devices. Multi-device JTAG chain programming and configuration are also available for FLEX 10K, MAX 9000, and FLASHlogic devices.

The BitBlaster is connected to an RS-232 serial cable, which in turn is connected to an RS-232 serial port (called a COM port on a PC) on a PC or workstation. The BitBlaster’s 10-pin female plug connects to a 10-pin male header on the circuit board that contains the target device(s). Programming or configuration data can be downloaded with the MAX+PLUS II Programmer or from a DOS or UNIX shell prompt.


BitBlaster dipswitch settings glossary definition
BitBlaster dipswitch settings

The BitBlaster can be configured for different baud rates. The following table lists the legal settings and corresponding baud rates for dipswitches 1 through 3 (1 = ON; 0 = OFF):

Baud Rate (bps)	1	2	3

9,600 	1	1	1

14,400 	0	1	1

19,200 	1	0	1

38,400 	0	0	1

57,600 	1	1	0

76,800 	0	1	0

115,200 	1	0	0

230,400 	0	0	0


Boolean logic glossary definition
Boolean logic

Logic that obeys the theorems of Boolean algebra (George Boole, "The Laws of Thought," 1854). The Boolean portion of a design is the portion which can be implemented in the AND-OR matrix of a device.


branch button glossary definition
branch button

A button in the Hierarchy Display that appears at the intersection of a higher-level branch and its lower-level branches. Clicking Button 1 on a "-" branch button hides all the lower-level branches that are associated with that button in the Hierarchy Display. Clicking Button 1 on the "+" branch button again restores the lower-level files to the Hierarchy Display.


branches glossary definition
branches

The extensions of the hierarchy tree that represent the different levels of the hierarchy. A branch consists of a design filename, a file icon, and any ancillary file icons. The intersections of branches are indicated by "+" and "-" branch buttons. Connection arrows lead from higher-level branches to lower-level branches.


breakpoint glossary definition
breakpoint

A user-defined set of conditions that will interrupt simulation when fulfilled.


breakpoint operator glossary definition
breakpoint operator

An operator used to compare node, group, and simulation time values in a breakpoint conditions list. Breakpoint operators are:

Operator:	Definition:

=	equal to

!=	not equal to

>	greater than

<	less than

<=	less than or equal to

>=	greater than or equal to

>->	goes to/transition


buried node glossary definition
buried node

A combinatorial or registered signal that does not drive an output pin.


buried register glossary definition
buried register

A register in an Altera device that does not drive its output to a pin. A buried register can be located on an I/O pin or on a logic cell that has no output to a pin. A buried register can be used to implement internal logic.


bus glossary definition
bus

A thick line in a Graphic Editor file that represents multiple nodes. A bus carries multiple signals between components of a design, and can represent from 2 to 256 nodes (i.e., bits).

In AHDL and Waveform Editor files, a group is synonymous with a bus.

In VHDL, a bus is a guarded signal that may have its drivers, i.e., signal sources, turned off. In VHDL, a group is called an array, and is not limited to 256 symbolic names. Examples of array types are STD_LOGIC_VECTOR or BIT_VECTOR. See Section 3.2.1: Array Types in the IEEE Standard VHDL Language Reference Manual for more information. Only one- and two- dimensional arrays of scalar elements are supported.


bus (or group) name glossary definition
bus (or group) name

The name of a bus (or group) of up to 256 nodes.

A single-range or dual-range name consists of up to 32 name characters, followed by one or two ranges of numbers or arithmetic expressions in brackets. (Dual-range names are not supported in Waveform Editor files.) The start and end of the number range are separated by two periods. Each number in the sequence represents an individual node (or bit).

Example: bus a[4..1] consists of the nodes a4, a3, a2, and a1.

Example: bus b[2..1][1..0] consists of the nodes b2_1, b2_0, b1_1, and b1_0.

A sequential name, consisting of a comma-separated list of names, can be entered in AHDL Text Design Files (.tdf), Graphic Design Files (.gdf), and Assignment & Configuration Files (.acf). In TDFs only, this list of names must be enclosed in parentheses. Sequential bus names can include single- and dual-range bus names.

Example: a[3..0],dout[6..4],z3

The first name in the series of names in a single-range, dual-range, or sequential name is the most significant bit (MSB) of the bus; the last name is the least significant bit (LSB).

An arbitrary bus name, consisting of up to 32 name characters, can be entered in a Waveform Design File (.wdf), Simulator Channel File (.scf), or Vector File (.vec). An arbitrary bus name does not indicate how many members are included in the bus.


bus pinstub glossary definition
bus pinstub

The location on the boundary of a mega- or macrofunction symbol, represented by an "x" in the Symbol File (.sym), that represents multiple inputs or outputs to the function. A bus (thick line) drawn in a Graphic Editor file must connect to a bus pinstub with the same number of bits to be recognized as a connection to the function.


Button 1 glossary definition
Button 1

The left button on a two- or three-button mouse.


Button 2 glossary definition
Button 2

The right button on a two-button mouse, or the middle and right buttons on a three-button mouse.


Carry Chain option glossary definition
Carry Chain option

A FLEX 8000 and FLEX 10K logic synthesis option that controls the use of carry chain logic.

When this option is set to AUTO, it directs the Compiler’s Logic Synthesizer module to insert carry chain logic--i.e., insert CARRY buffers--wherever it is useful. When you define a logic synthesis style, you can specify the maximum allowable length of a chain of these synthesized CARRY buffers. The AUTO setting does not force the Logic Synthesizer to use carry logic and has no effect on CARRY primitives that have been entered in design files.

When this option is set to MANUAL, the Logic Synthesizer uses only the CARRY primitives that have been manually entered in design files.

When the Carry Chain option is set to IGNORE, it directs the Logic Synthesizer to ignore CARRY buffers that have been entered manually in design files.

ACF logic option syntax:

<name>: CARRY_CHAIN = (AUTO|IGNORE|MANUAL|DEFAULT|NULL)

Multi-level synthesis may implement a FLEX 8000 or FLEX10K register in the counter mode even if it is not fed by a CARRY buffer. To prevent a register that is not explicitly fed by a CARRY buffer from using the counter mode, set the Carry Chain option to IGNORE for that register. If the register is explicitly fed by a CARRY buffer, you must also set the Carry Chain option to IGNORE on the CARRY buffer.

The following example shows a register implemented in counter mode without a carry chain input:

q   = dff ( (eqn & load # data & !load ) & clear, ... );

eqn = q & !ena # !q & ena;


Cascade Chain option glossary definition
Cascade Chain option

A FLEX 8000 and FLEX 10K logic synthesis option that controls the use of cascade chain logic.

When this option is set to AUTO, it directs the Compiler’s Logic Synthesizer module to insert cascade logic--i.e., insert CASCADE buffers--wherever it is useful. When you define a logic synthesis style, you can specify the maximum allowable length of a chain of these synthesized CASCADE buffers. The AUTO setting does not force the Logic Synthesizer to use cascade logic and has no effect on CASCADE primitives that have been entered in design files.

When the Cascade Chain option is set to IGNORE, it directs the Logic Synthesizer to ignore CASCADE buffers that have been entered manually in design files.

When this option is set to MANUAL, the Logic Synthesizer uses only the CASCADE primitives that have been manually entered in design files.

ACF logic option syntax:

<name>: CASCADE_CHAIN = (AUTO|IGNORE|MANUAL|DEFAULT|NULL)


cell glossary definition
cell

A unit in an EDIF hierarchical design that is analogous to a design file in MAX+PLUS II. The required Interface Section defines the ports of the cell; the optional Contents Section contains the properties of the cell.


checksum glossary definition
checksum

The sum of all the programming data bytes in a programming file. This number is used to compare a programming file with the data on a programmed device.


chip glossary definition
chip

A group of logic functions defined as a single, named unit. A chip is assigned to an actual device by either the user or the Compiler.

You can make chip assignments on logic functions in design files. Items that are assigned to the same chip are placed in the same device during compilation. The term device always refers to an actual programmable logic device, whereas the term chip always refers to a group of logic functions.

When the Compiler processes a project, each chip name is assigned to a corresponding programming file for a particular device.


Classic glossary definition
Classic

An Altera device family based on Altera’s original EPROM-based EPLD architecture. MAX+PLUS II provides support for the following Classic devices: EP220, EP320I, EP330, EP600I, EP610, EP610I, EP900I, EP910, EP910I, EP1800I, and EP1810 devices.


Clear glossary definition
Clear

An input signal that asynchronously resets a register, regardless of the Clock signal.


Clipboard glossary definition
Clipboard

A temporary storage location used to transfer data between documents and between applications. The Clipboard is used with the Copy, Cut, and Paste commands (Edit menu).


clique glossary definition
clique

A group of logic functions defined as a single, named unit. The Compiler attempts to keep clique members together when it fits the project. A clique assignment allows you to group all logic on a speed-critical path, thus improving performance.

If possible, all clique members are assigned to the same LAB. If the clique members will not fit into a single LAB, they are placed in the same row (in FLEX 10K, FLEX 8000, and MAX 9000 devices only) or the same device.


Clock glossary definition
Clock

A signal that triggers registers.

In a flipflop or state machine, the Clock is an edge-sensitive signal. The output of the flipflop can change only on the Clock edge. For example, in a D flipflop, the input value is stored and placed on the output at the Clock edge.

In some cases, MAX+PLUS II lists the Latch Enable input to a latch as a Clock, e.g., in a Delay Matrix timing analysis.


Clock Enable glossary definition
Clock Enable

The level-sensitive signal on an enabled flipflop, i.e., a flipflop with an "E" suffix, including DFFE, TFFE, SRFFE, and JKFFE. When the Clock Enable is low, Clock transitions on the Clock input to the flipflop are ignored.


column glossary definition
column

A vertical line of LABs connected by a column FastTrack Interconnect path in a FLEX 10K, FLEX 8000, or MAX 9000 device.


COM port glossary definition
COM or RS-232 port

An RS-232 serial communication port on a PC or workstation. The BitBlaster, which is used to configure and program devices in-system, must connect to a COM port.


combinatorial feedback glossary definition
combinatorial feedback

Feedback from a logic cell that goes back into the device’s logic array. It is the direct function of the inputs to a logic cell, and does not retain values from earlier inputs.


combinatorial output glossary definition
combinatorial output

Output from a logic cell that is a direct function of the inputs, without regard to the Clock; i.e., it does not retain values resulting from earlier inputs.


Command File (.cmd) glossary definition
Command File (.cmd)

An ASCII text file (with the extension .cmd) that contains commands for batch-mode simulation.


comment glossary definition
comment

In the Graphic and Symbol Editors, a comment is a free-floating block of text used to document the design. It is not associated with any object. A comment stands alone anywhere within Graphic Editor files. A comment also stands alone within the symbol border of a Symbol Editor file. Comments are ignored by the Compiler, and can be used to document various sections of a file.

In the Waveform Editor, a comment is a line of text used to annotate the waveforms in the waveform drawing area . It is not associated with any waveform. A comment is anchored to the time on the time scale where the first character is entered. A label appears in the Name field to indicate a comment line; when a comment is added between two existing nodes, it appears in a blank space, which is inserted between the waveforms. Comments are ignored by the Compiler.

In all MAX+PLUS II text files except VHDL Design Files (.vhd) and Assignment & Configuration Files (.acf), e.g., in Report Files (.rpt), Vector Files (.vec), and Text Design Files (.tdf), a comment is any string of characters enclosed in percent symbols (%). You can insert comments wherever white space is allowed in text files.

In VHDL Design Files and ACFs, comments begin with two dashes (--) and continue to the End-of-Line. AHDL TDFs also support VHDL-style comments. If you use a VHDL-style comment in a TDF, you must separate the two dashes from any preceding symbolic name with at least one space.

ACFs also support comments consisting of any string of characters enclosed between /* and */ characters. You can insert comments at any location in the file.


comparator or relational operator glossary definition
comparator or relational operator

A comparator, called a "relational operator" in VHDL, is an operator used to compare nodes, groups, and numbers. AHDL and VHDL provide the following comparators:

Comparator:	Definition:

==	equal to (AHDL only)

=	equal to (VHDL only)

!=	not equal to (AHDL only)

/=	not equal to (VHDL only)

>	greater than

<	less than

<=	less than or equal to

>=	greater than or equal to


Compiler Netlist Extractor glossary definition
Compiler Netlist Extractor

The Compiler module that creates Compiler Netlist Files (.cnf), Symbol Files (.sym), Include Files (.inc), and a Hierarchy Interconnect File (.hif) from the design files for a project. This module includes built-in EDIF, VHDL, and Xilinx Netlist Readers that convert EDIF Input Files (.edf), VHDL Design Files (.vhd), and Xilinx Netlist Format Files (.xnf) created with industry-standard CAE software. The Compiler Netlist Extractor also checks each design file in a project for problems such as duplicate node names, missing inputs and outputs, and outputs that are tied together.


Compiler Netlist File (.cnf) glossary definition
Compiler Netlist File (.cnf)

A binary file (with the extension .cnf) that contains the data from a design file. The CNF is created by the Compiler Netlist Extractor module of the MAX+PLUS II Compiler.


component glossary definition
component

Specifies the ports (pinstubs) of a logic function in VHDL. A component consists of the name of the function and a list of its inputs and outputs. Components are specified in the Component Declaration. They are often stored in packages. MAX+PLUS II includes a variety of megafunctions, macrofunctions, and primitives that are automatically installed in the subdirectories of the \maxplus2\max2lib directory. Components for those logic functions that are supported by VHDL are provided in the maxplus2 package in the altera library, which is located in the \maxplus2\max2vhdl directory.

On a UNIX workstation, the maxplus2 directory is a subdirectory of the /usr directory.

The logic of a megafunction or macrofunction is defined in a design file. You can insert an instance of a logic function into a VHDL Design File (.vhd) with a Component Instantiation Statement. You can also use a Register Inference to implement a register.


cone of logic glossary definition
cone of logic

A group of logic functions whose outputs eventually feed into a single gate.


configuration glossary definition
configuration

Maps instances of VHDL components to design entities and describes how design entities are combined to form a complete design. Configuration Declarations are used to specify which architectures to use for each entity.


Configuration EPROM glossary definition
Configuration EPROM

Altera’s family of serial EPROMs, which are designed to configure FLEX 8000 and FLEX 10K devices. This device family includes the EPC1, EPC1213, and EPC1064 devices.


configuration scheme glossary definition
configuration scheme

The method used to load data into a FLEX 8000 or FLEX 10K device. Six configuration schemes are available:

Active Serial (AS)

Active Parallel Up (APU)

Active Parallel Down (APD)

Passive Parallel Asynchronous (PPA)

Passive Parallel Synchronous (PPS)

Passive Serial (PS)

The FLEX 10K devices can be configured only with the AS, PPA, PPS, and PS configuration schemes.

FLEX 8000M devices can only be configured using the AS and PS configuration schemes.


connected pin group glossary definition
connected pins and connected pin group

Connected pins are pins that are externally connected on your circuit board. You can enter connected pin assignments to prepare a project for simulation and to help control project partitioning.

A connected pin group is a group of connected pins defined as a single, named unit.


connection arrow glossary definition
connection arrow

An arrow in the Hierarchy Display window that connects a higher-level design file, i.e., a hierarchy branch, to a lower-level design file in a hierarchy tree.


connection dot glossary definition
connection dot

A dot entered at an intersection of two signal lines (nodes or buses) in a Graphic Editor file. The connection dot indicates that the signals are logically connected.


construct glossary definition
construct

A unit in a text design language such as AHDL, VHDL, or EDIF.


context-sensitive help glossary definition
context-sensitive help

Help that is tailored to the current command, message, or object.

Typing Shift+F1 or choosing the [image] button on the toolbar changes the ordinary mouse pointer into the following context-sensitive help pointer:

You can click this pointer on words and objects on screen, menu commands, dialog boxes, and messages. Help about the item you select is displayed immediately.

The status bar also displays short descriptions of menu commands, palette tools, and toolbar buttons that you point to with the mouse.


continuity checking glossary definition
continuity checking

A test for open circuits between device pins and programming adapter sockets. This test verifies that a device is properly seated in the socket of the adapter.


cutoff node glossary definition
cutoff node

A node that is excluded from timing analysis. The signal associated with a node can be cut off from a timing analysis by tagging it with the Timing Analysis Cutoff command.


cyclic redundancy check (CRC) glossary definition
cyclic redundancy check (CRC)

A check performed on a block of data to determine whether an error has occurred during the process of reading, writing, or transmitting the data.


database glossary definition
database

A flattened representation of all design files in a MAX+PLUS II project hierarchy. The database is used internally by Compiler modules during compilation.


Database Builder glossary definition
Database Builder

The Compiler module that builds a single, fully flattened database that integrates all files in a project hierarchy. The Database Builder also examines the logical completeness and consistency of the project and checks for boundary connectivity and syntactical errors. In addition, it updates the Node Database File (.ndb), which contains the database of project node names and which supports resource and probe assignment edits with Assign menu commands and the Floorplan Editor.


database files glossary definition
database files (.db0, .db1, .db2, etc.)

Files that contain project compilation data, which are generated if the Compiler’s Smart Recompile command is turned on. The information in expanded database files is used to accelerate the speed of future recompilations. The database file with the extension .db0 is a copy of the Assignment & Configuration File (.acf) used to compile the project. The other database files, which have the extensions .db1, .db2, etc., are binary database files created by the Compiler at various points during its processing.


delay chain glossary definition
delay chain

A series of LCELL or EXP primitives used to create an intentional delay or asynchronous pulse. A delay chain is unreliable because the best-case delay of an LCELL or EXP cannot be guaranteed. This configuration also increases the sensitivity of the design to operating conditions.


delimiter glossary definition
delimiter

A text string, character, or keyword used to define the beginning or the end of a statement or construct in a text file.

For example, [ and ] are delimiters of AHDL group ranges and % is a comment delimiter in many MAX+PLUS II text files.


De Morgan's Inversion Theorem glossary definition
De Morgan’s Inversion Theorem

A theorem developed by Augustus De Morgan that is used in Boolean algebra. This theorem states that the complement of the product of the factors equals the sum of the complements of the addends; or that the complement of the sum of the addends equals the products of the complement of each factor.

Example: !(A & B) = !A # !B


decimal glossary definition
decimal

The base 10 number system (radix). Decimal digits are 0 through 9.

In AHDL and VHDL, no special notation is needed to indicate decimal digits.


Decompose Gates option glossary definition
Decompose Gates option

An advanced logic synthesis option that directs the Compiler’s Logic Synthesizer module to break up wide logic gates into smaller logic gates, or to merge smaller logic gates into wider logic gates. If this option is turned off, logic synthesis and other logic options may not yield the most efficient results.

The following example shows how the Decompose Gates option can affect logic:

Before:	t = a&b&c&d&e&f&g;

After:	t = a&b&c&y;	y = d&e&f&g;

This option is available only if the SOFT Buffer Insertion logic option is turned on.

ACF logic option syntax:

<name>: DECOMPOSE_GATES = (ON|OFF|DEFAULT|NULL)


default setting glossary definition
default setting

An option setting that does not specify a particular value. A default setting is an option setting that indicates that a non-default value is specified elsewhere, for example, at a higher level of the project hierarchy or in the default logic synthesis style for the project.

In several MAX+PLUS II dialog boxes, a three-way checkbox can be grayed to indicate a default setting. Other default settings are indicated with a radio button called Default, or an Assignment & Configuration File option setting of DEFAULT.


default Simulator Channel File (.scf) glossary definition
default Simulator Channel File (.scf)

A Simulator Channel File (.scf) that can contain all nodes and groups that are in the Simulator Netlist File (.snf) for a project. It is created automatically with the Enter Nodes from SNF command (Node menu) in the Waveform Editor.


default timing tagging glossary definition
default timing tagging

The Timing Analyzer provides the following default node tagging for timing analysis:

Analysis Mode:	Default Tagging:

Delay Matrix	All input pins are sources; all output pins are destinations.

Setup/Hold Matrix	All input pins are sources; all data and Clock inputs to registers, Latch Enable inputs to latches, and data, address, and Write Enable inputs to asynchronous RAM are destinations.

Registered Performance	All Q outputs of registers are sources; all data and Clock Enable inputs to registers are destinations.


Design Doctor glossary definition
Design Doctor

The Compiler utility that checks each design file in a project for logic that may cause reliability problems when the project is implemented in one or more devices. The Design Doctor runs in conjunction with the Logic Synthesizer module and analyzes the project with a predefined or customized set of design rules.


design file glossary definition
design file

A file that contains logic for a MAX+PLUS II project and is compiled by the Compiler. The following files are design files:

Altera Design File (.adf)

EDIF Input File (.edf) *

Graphic Design File (.gdf) *

OrCAD Schematic File (.sch) *

State Machine File (.smf)

Text Design File (.tdf) *

VHDL Design File (.vhd) *

Waveform Design File (.wdf)

Xilinx Netlist Format File (.xnf)

An asterisk (*) indicates the design files that can exist as top-level files in hierarchical projects. Other design files must be the only design file in a project or must exist at the bottom level of a hierarchical project.


design library (VHDL) glossary definition
design library (VHDL)

Stores VHDL units that have already been compiled. These units can be referenced in VHDL designs. Design libraries can contain one or more of the following units:

Entity Declarations

Architecture Declarations

Configuration Declarations

Package Declarations

Package Body Declarations

MAX+PLUS II provides the altera library, which includes the maxplus2 package, as well as the ieee and std libraries. These libraries are located in subdirectories of the \maxplus2\max2vhdl directory. (On a UNIX workstation, the maxplus2 directory is a subdirectory of the /usr directory.)


Design Library System File (.dls) glossary definition
Design Library System File (.dls)

A file (with the extension .dls) created by the Compiler and used temporarily during compilation of VHDL Design Files (.vhd).


destination node glossary definition
destination node

A node that is tagged (designated) as the destination of a signal for the purpose of timing analysis. A destination node is tagged with the Timing Analysis Destination command, and can be any node that is the input to a logic function or a pin.


device glossary definition
device

A device refers to an Altera programmable logic device, including Classic, MAX 5000, MAX 7000, MAX 9000, FLEX 8000, FLEX 10K, and FLASHlogic devices.

Altera also offers Configuration EPROM devices that are used to configure FLEX 8000 and FLEX 10K devices.


device assignment glossary definition
device assignment

A device assignment assigns a user-specified block of logic functions, called a chip, to a specific Altera device.


device family glossary definition
device family

A group of Altera programmable logic devices with the same fundamental architecture. Altera families include the Classic, MAX 5000, MAX 7000, MAX 9000, FLEX 8000, FLEX 10K, and FLASHlogic device families.

Altera also offers a Configuration EPROM device family that includes devices which are used to configure FLEX 8000 and FLEX 10K devices.


Device Model File (.dmf) glossary definition
Device Model File (.dmf)

A MAX+PLUS II system file (with the extension .dmf) that contains device timing information. DMFs for each Altera device are provided with the MAX+PLUS II software. The Timing SNF Extractor module of the Compiler uses DMFs to create timing Simulator Netlist Files (.snf).


device option glossary definition
device option

An option that controls a device. Altera devices offer the following device options:

Option:	Device Family:

Security Bit	Classic, MAX 5000, MAX 7000, and MAX 9000

Turbo Bit	Classic, MAX 7000, and MAX 9000 (logic cell Turbo Bit can be applied to all logic cells in a MAX 7000 or MAX 9000 device)

User-Supplied Start-Up Clock	FLEX 8000 and FLEX 10K

Auto-Restart Configuration on Frame Error	FLEX 8000 and FLEX 10K

Release Clears Before Tri-States	FLEX 8000 and FLEX 10K

Enable DCLK Output in User Mode	FLEX 8000

Disable Start-Up Time-Out	FLEX 8000

Enable JTAG Support	FLEX 8000

Enable Chip-Wide Reset	FLEX 10K

Enable Chip-Wide Output Enable	FLEX 10K

Enable INIT_DONE Output	FLEX 10K


DIP glossary definition
DIP

Dual In-Line Package. A device package option offered by Altera. Both ceramic DIP (CerDIP) and plastic DIP (PDIP) packages are available.


Document Control Menu box glossary definition
Document Control Menu box

The box in the far left corner of the title bar of an individual MAX+PLUS II application window:

Clicking Button 1 on this box opens the Document Control Menu, which contains commands to move, change the size of, and close the current window. Within MAX+PLUS II, this menu controls the windows for an individual application, such as the Compiler, Text Editor, etc.


dual I/O feedback glossary definition
dual I/O feedback

A combination of pin feedback and register or combinatorial feedback on the same logic cell.


dual-purpose pins glossary definition
dual-purpose pins

Pins used to configure a FLEX 8000 or FLEX 10K device that can be used as I/O pins after initialization. The dual-purpose pins available in a FLEX 8000 or FLEX 10K device are dependent on the device configuration scheme.


dual-range group (or bus) name glossary definition
dual-range group (or bus) name

The name of a group (or bus) of up to 256 nodes, consisting of up to 32 name characters, followed by a two ranges of numbers or arithmetic expressions in brackets. The start and end of the ranges are separated by two periods. Each set of numbers in the two ranges represents an individual node (or "bus bit").

Example: group a[2..1][5..3] consists of the nodes a2_5, a2_4, a2_3, a1_5, a1_4, and a1_3.

In a Graphic Editor files, a sequential bus name can also include one or more single- or dual-range bus names in a series. The first node of the series or the first node in the first range is the most significant bit of the bus; the last node of the series or the last node in the last range is the least significant bit.

Example: a[8..0][2..0], b1, dout[6..4]


Duplicate Logic Extraction option glossary definition
Duplicate Logic Extraction option

An advanced logic synthesis option that directs the Compiler’s Logic Synthesizer module to remove duplicate logic functions from the project. If two gates generate the same logic function, the second one will be deleted from the network and the first one will be made to fan out to the second gate’s destinations. However, if a gate’s output feeds an LCELL buffer, it is always treated as a unique signal and is not subject to Duplicate Logic Extraction.

A logic option setting of Refactorization=On may indirectly override turning the Duplicate Logic Extraction option off. If Duplicate Logic Extraction is turned on, it may cause other logic options to be ignored if a duplicate logic function is replaced by another logic function that has different logic option assignments.

The following example shows how the Duplicate Logic Extraction option can affect logic:

Before:	t = a&w	y = b&z	z = c&d # e&f;	w = c&d # e&f;

After:	t = a&z	y = b&z	z = c&d # e&f;

ACF logic option syntax:

<name>: DUPLICATE_LOGIC_EXTRACTION = (ON|OFF|DEFAULT|NULL)


dynamic models glossary definition
dynamic models

Models that represent actual combinatorial logic in timing Simulator Netlist Files (.snf).

Dynamic models are generated for the logic in a timing SNF when the Compiler’s Optimize Timing SNF command (Processing menu) is turned on. Instead of processing the combinatorial logic, the Simulator or Timing Analyzer refers to the representative dynamic model.

Dynamic models allow a simulation to run faster; however, the Compiler requires additional time to generate the SNF.


EDIF glossary definition
EDIF

Electronic Design Interchange Format. An industry-standard format for the transmission of design data.

You can generate an EDIF 2 0 0 or 3 0 0 netlist file from a schematic design or from a VHDL or Verilog HDL design that has been processed with an appropriate industry-standard synthesis tool and then import the file into MAX+PLUS II as an EDIF Input File (.edf). MAX+PLUS II supports EDIF Input Files that contain functions from the Library of Parameterized Modules (LPM). The MAX+PLUS II Compiler can also generate one or more EDIF Output Files (.edo) in either EDIF 2 0 0 or 3 0 0 format that contain functional or timing information for simulation with a standard EDIF simulator.


EDIF Command File (.edc) glossary definition
EDIF Command File (.edc)

An ASCII text file (with the extension .edc) used to customize the format of EDIF Output Files (.edo) created by the Compiler’s EDIF Netlist Writer module.


EDIF Input File (.edf) glossary definition
EDIF Input File (.edf)

An EDIF version 2 0 0 or 3 0 0 netlist file generated by any standard EDIF netlist writer. EDIF Input Files (with the extension .edf) can be compiled by the MAX+PLUS II Compiler. MAX+PLUS II supports EDIF Input Files that contain functions from the Library of Parameterized Modules (LPM).


EDIF Netlist Reader glossary definition
EDIF Netlist Reader

The portion of the Compiler Netlist Extractor module that converts an EDIF Input File (.edf) generated with other industry-standard CAE tools into a MAX+PLUS II-compatible format. MAX+PLUS II supports EDIF Input Files that contain functions from the Library of Parameterized Modules (LPM).


EDIF Netlist Writer glossary definition
EDIF Netlist Writer

The Compiler module that produces an EDIF Output File (.edo) for use with industry-standard simulators. It also generates an optional Standard Delay Format Output File (.sdo) that contains timing delay information, and depending of the design contents, may generate a VHDL Memory Model Output File (.vmo)..


EDIF Output File (.edo) glossary definition
EDIF Output File (.edo)

An EDIF version 2 0 0 or 3 0 0 netlist file (with the extension .edo) generated by the EDIF Netlist Writer module of the Compiler. This file can be exported to an industry-standard workstation or PC environment for simulation.


EEPROM glossary definition
EEPROM

Electrically Erasable Programmable Read-Only Memory. A form of reprogrammable semiconductor memory in which the contents (program) can be erased by subjecting the device to appropriate electrical signals.


elaboration (VHDL) glossary definition
elaboration (VHDL)

The process by which a declaration achieves its effect. Elaboration is also defined for design hierarchies, declarative parts, statement parts (containing concurrent statements), and concurrent statements.

See Section 12: Elaboration and Execution in the IEEE Standard VHDL Language Reference Manual for more information on elaboration of VHDL design hierarchy.


Embedded Array Block (EAB) glossary definition
Embedded Array Block (EAB)

A physically grouped set of 8 embedded cells that implement memory (RAM or ROM) or combinatorial logic in a FLEX 10K device. An EAB consists of an embedded cell array, with data, address, and control signal inputs and data outputs that are optionally registered.

A single EAB can implement a memory block of 256 x 8, 512 x 4, 1,024 x 2, or 2,048 x 1 bits. Each embedded cell within the EAB implements up to 256 bits of memory. For memory blocks of these sizes, an EAB has 8, 4, 2, or 1 outputs, respectively. Multiple EABs can be combined to create larger memory blocks.

The EAB is fed by row interconnect paths and a dedicated input bus.


embedded cell (EC) glossary definition
{bml glos.bmp}embedded cell (EC)

A memory element that exists in the embedded array of a FLEX 10K device, and which can implement memory (RAM or ROM) or combinatorial logic. An Embedded Array Block (EAB) consists of a group of 8 embedded cells that can implement a memory block of 256 x 8, 512 x 4, 1,024 x 2, or 2,048 x 1 bits. Each embedded cell within an EAB implements up to 256 bits of memory. Depending on the depth of the memory, up to 8 of the embedded cells in an EAB have outputs. For memory blocks of 256 x 8, 512 x 4, 1,024 x 2, or 2,048 x 1 bits, an EAB has 8, 4, 2, or 1 outputs, respectively.

Embedded cells have "numbers" of the format EC<number>_<row letter>, where <number> ranges from 1 to 8 and <row letter> consists of the row letter of the EAB.


embedded cell (EC) number glossary definition
embedded cell (EC) number

A number assigned to a logic function in a design file, which corresponds to an embedded cell number on the actual device.

Embedded cells have "numbers" of the format EC<number>_<row letter>, where <number> ranges from 1 to 8 and <row letter> consists of the row letter of the EAB.


End-of-File (EOF) glossary definition
End-of-File (EOF)

A control character indicating that the last item in a file has been read.


End-of-Line (EOL) glossary definition
End-of-Line (EOL)

A control character indicating the end of a line in a text file. In the PC environment, it is equivalent to <Carriage Return><Line Feed>. In the UNIX workstation environment, it is equivalent to <Line Feed>.


EPLD glossary definition
EPLD

Erasable Programmable Logic Device, i.e., an Altera device that is a member of the Classic, MAX 5000, MAX 7000, or MAX 9000 device families.


EPROM glossary definition
EPROM

Erasable Programmable Read-Only Memory. A form of reprogrammable semiconductor memory in which the contents (program) can be erased by subjecting the device to ultraviolet light of the proper wavelength.


evaluated function glossary definition
evaluated function

An mathematical function that evaluates an arithmetic expression and returns a value based on one or more arguments. The AHDL Define Statement can be used to create evaluated functions. The following example shows the definition of the evaluated function MAX:

DEFINE MAX(a,b) = (a > b) ? a : b;


excitation equation glossary definition
excitation equation

Combinatorial logic that directs state transitions in a state machine.


expander networks, flipflops & latches glossary definition
expander networks, flipflops & latches

An expander network consists of cross-coupled logic used to create additional latches or flipflops in a device. This logic may use expander product terms and/or multiple logic cells to implement a flipflop or latch.

A flipflop or latch that is created with cross-coupled logic can be unreliable and should only be implemented with the Altera-provided expdff, explatch, nandltch, or norlatch macrofunctions. In addition, these macrofunctions should be used only after all dedicated flipflop and latch resources in a device are used.


expander product term glossary definition
expander product term

A single product term with an inverted output that feeds back into the Logic Array Block (LAB) of a MAX 5000, MAX 7000, or MAX 9000 device.

An uncommitted expander product term that can be shared with other logic cells in the same LAB is called a shareable expander; a product term that has been shared in this manner is called a shared expander.

In MAX 7000 and MAX 9000 devices only, an expander product term that is "borrowed" from an adjacent logic cell in the same LAB is called a parallel expander.


external connection pin primitive glossary definition
external connection pin primitive

A primitive available in the Graphic Editor that has an external connection pinstub, i.e., INPUTC, OUTPUTC, and BIDIRC.

These primitives can be used to indicate the pins that are connected together on your circuit board.


external connection pinstub glossary definition
external connection pinstub

The pinstub on an external connection primitive--i.e., an INPUTC, OUTPUTC, or BIDIRC primitive--that is used to indicate that device pins are connected externally.


family-specific macrofunction glossary definition
family-specific mega- or macrofunction

An Altera-provided mega- or macrofunction that contains logic optimized for the architecture of a specific device family.

The functionality of a family-specific mega- or macrofunction is always the same, regardless of the device family for which it is designed. However, the actual primitives and nodes used within the mega- or macrofunction file can vary from family to family to take advantage of different device architectures, thus providing higher performance and/or more efficient implementation.


-------------------------------BEGINNING OF NON-TRANSLATED TEXT-----------------------------------

The following entry for Family-Specific Macrofunction is used only for the "Note" popup in the macrofunction panels.

-------------------------------END OF NON-TRANSLATED TEXT-----------------------------------


Family-Specific Macrofunction glossary definition
Family-Specific Macrofunction

A separate family-specific version of this macrofunction, which is optimized for the device family architecture, is available for each device family.

The functionality of a family-specific macrofunction is always the same, regardless of the device family for which it is designed. However, the actual primitives and nodes used within the macrofunction file can vary from family to family to take advantage of different device architectures, thus providing higher performance and/or more efficient implementation.

You can go to the lists of "Macrofunctions (by name)" or "Macrofunctions (by number)" in MAX+PLUS II Help for information on whether family-specific versions of a particular macrofunction are available.


fan-in and fan-out glossary definition
fan-in and fan-out

Fan-in refers to input signals that feed the input equations of a logic cell.

Fan-out refers to output signals that are fed by the output equations of a logic cell.


Fast logic synthesis style glossary definition
Fast logic synthesis style

The Altera-provided style that directs the Compiler‘s Logic Synthesizer module to optimize your project for maximum speed, rather than for minimum silicon usage.


FastTrack Interconnect  glossary definition
FastTrack Interconnect

Dedicated connection paths that span the entire width and height of a FLEX 8000, MAX 9000, or FLEX 10K device. These connection paths allow signals to travel between all Logic Array Blocks (LABs) in a device.


file icon glossary definition
file icon

An icon that appears in a MAX+PLUS II application window and represents a file in the current hierarchy tree. Double-clicking Button 1 on an icon opens the file that it represents.

In the Hierarchy Display, the file icon shows which MAX+PLUS II editor can open the file. The filename extension is displayed at the bottom of the file icon to show the file type; the filename is displayed to the left of the file icon.

In the Compiler, the file icons show input and output files for the current project.


filename glossary definition
filename

The name of a design file, ancillary file, or other file, without the extension.

A single filename can contain up to 32 name characters, plus a 3-character filename extension. A full pathname plus filename and extension can contain up to 128 characters.

Since Windows 3.1 and Windows for Workgroups 3.11 support only 8-character filenames, MAX+PLUS II maps longer filenames on these operating systems to 8-character filenames. These filename mappings are stored in the maxplus2.idx file in each directory that contains long filenames.

In the Hierarchy Display window, a filename, along with the file icon and filename extension, represents a file in the current hierarchy tree.


filename extension glossary definition
filename extension

The one, two, or three-letter extension of a filename that follows a period (.).

In the Hierarchy Display window, a filename extension, along with the filename and the file icon, represents a file in the current hierarchy or the current project.


FILTER primitive glossary definition
FILTER primitive

A primitive that specifies the minimum required time for a high or low signal pulse, as determined by the Compiler’s Timing SNF Extractor module. This primitive has no logical behavior, but can be useful for detecting glitches during simulation with the MAX+PLUS II Simulator or industry-standard simulation software.

The FILTER primitive is always included in a timing Simulator Netlist File (.snf); it is optionally included in an EDIF Output File (.edo).


Fit File (.fit) glossary definition
Fit File (.fit)

An ASCII file (with the extension .fit) generated by the Compiler that documents pin, logic cell, I/O cell, embedded cell, chip, and device assignments made during the last compilation. Assignments are recorded in Assignment & Configuration File (.acf) syntax.

The Fit File can be used for back-annotation and for functional testing in the Simulator and Programmer. To preserve assignments permanently, Fit File assignments can be back-annotated into a project’s ACF with the Back-Annotate Project command (Assign menu).

You can also display a read-only version of Fit File information from the most recent project compilation in the Floorplan Editor.


Fitter glossary definition
Fitter

The Compiler module that fits a project into one or more devices. The Fitter selects appropriate interconnection paths, and pin and logic cell assignments. It also generates part of the Report File (.rpt) and Fit File (.fit) for the project.


Fitter Input File (.fin) glossary definition
Fitter Input File (.fin)

A file (with the extension .fin) created by the Compiler and used temporarily during compilation.


FLASHlogic glossary definition
FLASHlogic (formerly FLEXlogic)

An Altera device family consisting of SRAM-based devices with shadow EPROM or shadow FLASH memory. The high-performance FLASHlogic device family includes the EPX8160, EPX880, EPX780, and EPX740 devices.

MAX+PLUS II provides programming-only support for FLASHlogic devices. Full compilation, simulation, timing analysis, and programming support for all FLASHlogic devices will be available in a future version of MAX+PLUS II.


FLEX Download Cable glossary definition
FLEX Download Cable

A cable used to download SRAM Object File (.sof) data in a passive serial (PS) configuration scheme to a FLEX 8000 or FLEX 10K device in an in-system circuit. You can configure FLEX 8000 and FLEX 10K devices with the FLEX Download Cable to allow in-circuit testing and prototyping on the circuit board.


FLEX 8000 glossary definition
FLEX 8000

An Altera device family based on Flexible Logic Element MatriX architecture. This SRAM-based family offers high-performance, register-intensive, high-gate-count devices. The FLEX 8000 device family includes the EPF8282, EPF8282V, EPF8282A, EPF8452, EPF8452A, EPF8636A, EPF8820, EPF8820A, EPF81188, EPF81188A, EPF81500, EPF81500A, and EPF8050M devices.

FLEX 8000A devices provide the same architectural features as equivalent FLEX 8000 devices, but offer faster speeds and smaller die sizes.

Altera recommends using FLEX 8000A devices rather than FLEX 8000 devices for new designs.

The EPF8050M device has a multi-chip module architecture. When you compile a project for the EPF8050M, the Report File (.rpt) includes information for up to four chips, each of which is labeled EPF8050M/4.


FLEX 10K glossary definition
FLEX 10K

An Altera device family based on Flexible Logic Element MatriX architecture. This SRAM-based family offers high-performance, register-intensive, high-gate-count devices with embedded arrays. The FLEX 10K device family includes the EPF10K50 device.


flipflop or register glossary definition
flipflop or register

An edge-triggered, clocked storage unit that stores a single bit of data. A low-to-high transition on the Clock signal changes the output of the flipflop, based on the value of the data input(s). This value is maintained until the next low-to-high transition of the Clock, or until the flipflop is preset or cleared.

Depending on the architecture of the device family, a register can be programmed as a level-sensitive flow-through latch or as an edge-triggered D,T, JK, or SR flipflop.


fmax (maximum Clock frequency) glossary definition
fmax (maximum Clock frequency)

The maximum Clock frequency that can be achieved without violating internal setup and hold time requirements.

fmax is also a timing assignment that specifies the minimum acceptable Clock frequency. In MAX+PLUS II, you can specify a required fmax for an entire project and/or for any input pin (INPUT or INPUTC), bidirectional pin (BIDIR or BIDIRC input function), or a register.

ACF timing assignment syntax:

<name>: FREQUENCY = <decimal number><time unit>

ACF global project option syntax:

FREQUENCY = <decimal number><time unit>


Function Prototype glossary definition
Function Prototype

Specifies the ports (pinstubs) of a primitive, megafunction, or macrofunction in AHDL. A Function Prototype consists of the name of the function, and a list of its inputs and outputs. For mega- and macrofunctions, the Function Prototype can also contain parameters that are used to specify the characteristics of the function. Function Prototypes are specified in the Function Prototype Statement. They are often stored in Include Files (.inc). Include Files that contain Function Prototypes for Altera-provided mega- and macrofunctions are located in the \maxplus2\max2lib\mega_lpm and \maxplus2\max2inc directories created during installation, respectively. (On a UNIX workstation, the maxplus2 directory is a subdirectory of the /usr directory.)

To implement an instance of a mega- or macrofunction, its logic must be defined in a design file and its Function Prototype must be declared. (Function Prototypes are optional for primitives.) You can then create an instance of the function with an Instance Declaration or an in-line reference.


functional comparison rules glossary definition
functional comparison rules

For every set of input vectors that are applied at a particular time ("tA"), the output logic levels used for comparison are determined by finding the time of the next transition on any input vector ("tB") and taking the output levels that existed 0.1 ns prior to that transition time. In other words, tA outputs are checked at tB - 0.1 ns.


functional simulation glossary definition
functional simulation

A MAX+PLUS II Simulator mode that uses a functional Simulator Netlist File (.snf) to simulate the logical performance of a project (without timing information).

Because the functional SNF is generated before logic synthesis, partitioning, or fitting are performed, functional simulation allows you to simulate all nodes in a project.

When the SNF for the current project is a functional SNF, the title bar of the Simulator window displays Simulator: Functional Simulation to indicate that it is set up to run in the functional simulation mode.


Functional SNF Extractor glossary definition
Functional SNF Extractor

The Compiler module that creates the functional Simulator Netlist File (.snf) required for functional simulation.


functional Simulator Netlist File (.snf) glossary definition
functional Simulator Netlist File (.snf)

A binary-format file (.snf) created by the Compiler’s Functional SNF Extractor module that contains the logic information required for functional simulation. A functional SNF contains no timing information.


gated Clock glossary definition
gated Clock

A Clock configuration in which the output of an AND or OR gate drives a Clock.


glitch or spike glossary definition
glitch or spike

A signal value pulse that occurs when a logic level changes two or more times over a short period.

When the Simulator is in timing or linked simulation mode, you can define the length of a glitch and monitor the project for pulses shorter than the defined value. When the Simulator is in functional simulation mode, you can monitor the project for nil-time glitches only.


global signal glossary definition
global signal

A signal from a dedicated input pin that does not pass through the logic array before performing its specified function. Clock, Preset, Clear, and Output Enable signals can be global signals.

A global signal can be designated during design entry with a GLOBAL primitive in a Graphic Design File (.gdf), Text Design File (.tdf), or VHDL Design File (.vhd). Or, when the appropriate Automatic Global option in the Global Project Logic Synthesis dialog box (Assign menu) is turned on, the Compiler chooses the signal that feeds the most flipflops as a global Clock, Preset, or Clear, and the signal that feeds the most TRI buffers is chosen as the global Output Enable.


global logic cell glossary definition
global logic cell

A logic cell that can feed every other cell in an Altera device. Most logic cells in Altera devices are global. Refer to individual device data sheets for specific information.


GND glossary definition
GND

A low-level input voltage.

GND is the default inactive node value. In an AHDL Text Design File (.tdf), GND is used as a predefined constant and keyword. In a VHDL Design File (.vhd), GND is represented by '0'. In a Graphic Editor file, GND is a primitive symbol. GND is represented as a low (0) logic level in the Simulator and Waveform Editor.


Graphic Design File (.gdf) glossary definition
Graphic Design File (.gdf)

A schematic design file (with the extension .gdf) created with the MAX+PLUS II Graphic Editor.

An OrCAD Schematic File (.sch) is automatically translated into a GDF and treated as a GDF in the MAX+PLUS II Graphic Editor and Compiler.


graphic selection glossary definition
graphic selection

An object or group of objects selected in the MAX+PLUS II Graphic or Symbol Editor.


Gray code glossary definition
Gray code

A counting scheme in which only one bit at a time changes value between consecutive count values. In contrast, a binary count sequence does not preclude more than one bit changing at consecutive count values. When only one bit changes, noise susceptibility is reduced in the circuit.


grid unit glossary definition
grid unit

An Altera-defined unit of measure used in the Graphic and Symbol Editors. One grid unit is equal to eight pixels. In the Graphic Editor, the grid unit is the smallest available unit. In the Symbol Editor, you can choose between grid and pixel units.

In the Waveform Editor, a grid unit is the user-defined time span between grid lines, specified with the Grid Size command (Options menu).


group or array glossary definition
group or array

In AHDL, a group is a collection of up to 256 symbolic names that are treated as a unit. A group name can be specified with a single-range group name, dual-range group name, or sequential group name format.

In VHDL, a group is called an array, and is not limited to 256 symbolic names. Examples of array types are STD_LOGIC_VECTOR or BIT_VECTOR. See Section 3.2.1: Array Types in the IEEE Standard VHDL Language Reference Manual for more information. Only one- and two- dimensional arrays of scalar elements are supported.

In the Waveform Editor and Simulator, a group is a collection of up to 256 nodes that are treated as a unit. In these applications, a group name can be specified with an arbitrary group name or single-range group name format.


hard logic function glossary definition
hard logic function

A logic function in a design file that is not removed during standard logic synthesis and therefore can be assigned to a physical resource such as a specific device, pin, logic cell, or I/O cell.

In Graphic Design Files (.gdf) and Text Design Files (.tdf), hard logic primitives/ports include INPUT, INPUTC, OUTPUT, OUTPUTC, BIDIR, BIDIRC, LCELL, MCELL, DFF, DFFE, TFF, TFFE,JKFF, JKFFE, SRFF, SRFFE, and LATCH. However, INPUT and INPUTC primitives that do not affect project outputs are not considered to be hard logic functions. When SOFT, TRI, and OPNDRN primitives are not removed during logic synthesis, they are also hard logic primitives. A macrofunction that contains a hard logic primitive is considered to be a hard logic function.

In Waveform Design Files (.wdf), hard logic functions are input nodes and output and buried nodes with registered and combinatorial node types.


help panel glossary definition
help panel

A single "page" in the on-line help system.

A help panel may have more information than the current window can hold. You can stretch the window or use the scroll bars along the side and/or bottom of the Help window to view all of the panel.


hexadecimal glossary definition
hexadecimal

The base 16 number system (radix). Hexadecimal digits are 0 through 9 and A through F.

In AHDL, hexadecimal numbers are indicated with the following notation:

X"<series of digits 0 to 9, A to F>" or

H"<series of digits 0 to 9, A to F>"

Example: H"123AECF"

In VHDL, hexadecimal numbers are indicated with the following notation:

16#<series of digits 0 to 9, A to F>#

Example: 16#FF#


Hexadecimal (Intel-Format) File (.hex) glossary definition
Hexadecimal (Intel-Format) File (.hex)

A hexadecimal file (with the extension .hex) in the Intel Hex format.

The MAX+PLUS II Compiler and Simulator can use Hex Files as inputs to specify the initial contents of a memory (e.g., a ROM).

The MAX+PLUS II Compiler automatically creates output Hex Files containing configuration data for the Active Parallel Up (APU) configuration scheme for a FLEX 8000 devices, and the Passive Serial (PS) configuration scheme for FLEX 10K devices.

After compilation, you can also create Hex Files that support other configuration schemes for FLEX 8000 and FLEX 10K devices.

If your project uses memory and you use a Hex File to specify its initial contents, you should name the file with a name that is not the same as the project name or any chip name within the project. Because the Compiler automatically generates Hex Files as outputs for FLEX 8000 and FLEX 10K devices, these output files may overwrite your initial memory content files.


hierarchical node or symbol name glossary definition
hierarchical node or symbol name

The unique name for a node or symbol that is based on its location in the hierarchy of design files and the net ID number or the AHDL or VHDL instance name of the logic function to which it is connected.

Every node and symbol in a project has a hierarchical name; you can also assign a node name or a probe name to a node.


Hierarchy Interconnect File (.hif) glossary definition
Hierarchy Interconnect File (.hif)

An ASCII file (with the extension .hif) created by the Compiler’s Netlist Extractor module. This file specifies the hierarchical interconnections between design files in a project.


hierarchy tree glossary definition
hierarchy tree

A hierarchy of design files or the representation of a hierarchy of design files that is displayed in the Hierarchy Display window. A hierarchy tree consists of two or more branches that include design filenames and ancillary filenames, file icons, and filename extensions. Connection arrows connect the branches of the hierarchy tree. The "+" and "-" branch buttons determine whether each branch appears in the Hierarchy Display.


History File (.hst) glossary definition
History File (.hst)

An ASCII file (with the extension .hst) created by the MAX+PLUS II Simulator. This time period records all commands, buttons, and on-screen options that are used during a simulation session, as well as their output.


hold time glossary definition
hold time

On a flipflop, the hold time is the minimum time period for which a signal must be retained on an input pin that feeds the data input or Clock Enable after an active transition at the input pin that feeds the flipflop’s Clock input.

On a latch, the hold time is the minimum time period for which a signal must be retained on an input pin that feeds the D input after an active transition at the input pin that feeds the Latch Enable input.

On an asynchronous RAM block, the hold time is the minimum time period for which a signal must be retained on an input pin that feeds the data or address inputs after an active transition at the input pin that feeds the RAM block’s Write Enable input.

Internal hold times for flipflops, latches, and asynchronous RAM, which are not user-controllable, similarly constrain internally generated signals.


in-circuit reconfigurability (ICR) glossary definition
in-circuit reconfigurability (ICR)

The capability of SRAM-based devices, such as Altera’s FLEX 8000, FLEX 10K, and FLASHlogic devices, to load configuration data at system power-up or during normal system operation after they have been mounted on a printed circuit board.

In-circuit reconfiguration can be performed an unlimited number of times with data from a local PROM such as an Altera Configuration EPROM, or with data downloaded by an external controller such as a CPU or the MAX+PLUS II Programmer. The Programmer also provides the capability to configure multiple devices in a JTAG chain.


Include File (.inc) glossary definition
Include File (.inc)

An ASCII text file (with the extension .inc) that can be imported into a Text Design File (.tdf) by an AHDL Include Statement. The Include File replaces the Include Statement that calls it. Include Files can contain Function Prototype, Define, Parameters, or Constant Statements. Include Files that contain Function Prototypes for Altera-provided mega- and macrofunctions are located in the \maxplus2\max2lib\mega_lpm and \maxplus2\max2inc directories created during installation, respectively. (On a UNIX workstation, the maxplus2 directory is a subdirectory of the /usr directory.)


insertion point glossary definition
insertion point

The location at which text or graphics are inserted.

In a dialog box or in the Text Editor window, the insertion point appears as a flashing vertical bar. In the Graphic or Symbol Editor, it appears as a flashing square. In the Waveform Editor, an insertion point in the waveform drawing area appears as a short horizontal line that extends to the right of the Time cursor. In the node/group information area, a name or blank space that is selected is interpreted as an insertion point.

When you type text, it appears to the left of the insertion point, which moves to the right as you type. When you enter or paste symbols or waveforms, the upper left corner of the item(s) appears at the insertion point.


instance glossary definition
instance

The use of a logic function in a design file. In the Graphic Editor, the instance is represented by the symbol (net) ID number in the lower left corner; in the Waveform Editor, it is the name of the node. In AHDL, instances are declared in one of two forms: an Instance Declaration that declares a variable of the type <primitive>, <megafunction>, or <macrofunction>, or an in-line logic function reference. In VHDL, instances of logic functions are declared with a Component Instantiation Statement; registers can also be implemented with Register Inferences.

In the Hierarchy Display, an instance of a mega- or macrofunction is represented by the function name, followed by a colon (:) and a net ID number. In an AHDL Variable Declaration and a VHDL Component Instantiation Statement, an instance is represented by the instance name followed by a colon and the function name.


interactive mode glossary definition
interactive mode

The simulation mode in which you choose on-screen options and buttons, and execute menu commands, with the keyboard or mouse.


in-system programmability (ISP) glossary definition
in-system programmability (ISP)

The capability of EEPROM- and FLASH-based devices, such as Altera’s MAX 9000 and FLASHlogic devices, to be programmed after they have been mounted on a printed circuit board.

The MAX+PLUS II Programmer supports in-system programming via the BitBlaster serial download cable. The Programmer also provides the capability to program multiple devices in a JTAG chain.


I/O cell (IOC) number glossary definition
I/O cell (IOC) number

A number assigned to a logic function in a design file, which corresponds to an I/O cell number on the actual device.

I/O cells have "numbers" of the format IOC_<pin number>, where <pin number> is the number of the pin associated with the I/O cell. In some device packages, the <pin number> may consist of both digits and letters.


I/O cell and I/O Cell Register glossary definition
I/O cell and I/O Cell Register

An I/O cell is a register that exists on the periphery of a FLEX 10K, FLEX 8000, or MAX 9000 device (also known as an I/O element) or a fast input-type logic cell that is associated with an I/O pin in a MAX 7000E device. I/O cells permit short setup time.

I/O Cell Register is a logic option that specifies that you wish to implement a register in an I/O cell on a FLEX 10K, FLEX 8000, MAX 9000, or MAX 7000E device. This logic option can be applied to individual logic functions. The Global Project Logic Synthesis command includes an Automatic I/O Cell Registers option to allow the Compiler to automatically implement appropriate logic functions in I/O cell registers.

In pre-version 5.0 releases of MAX+PLUS II, I/O cells were known as peripheral registers.

ACF individual logic option syntax:

<name>: IO_CELL_REGISTER = (ON|OFF|DEFAULT|NULL)

ACF global project option syntax:

AUTO_IO_CELL_REGISTERS = (ON|OFF)


I/O feedback glossary definition
I/O feedback

Feedback from the output pin on an Altera device. It allows an output pin to be also used as an input pin.


I/O type glossary definition
I/O type

The direction of signal travel for a node, pin, or state machine.

In the Graphic and Symbol Editors, pins and pinstubs can have I/O types of input, output, or bidirectional.

In AHDL, the I/O type of a port can be input, output, buried (i.e., buried output), machine input, or machine output.

In the Waveform Editor, the I/O type of a node can be input, output, or buried (i.e., buried output). Input and output I/O types can represent actual pin outputs; a buried I/O type always represents logic that does not feed a pin.


JEDEC File (.jed) glossary definition
JEDEC File (.jed)

An ASCII file (with the extension .jed) that contains programming information. JEDEC Files provide an industry-standard format for transferring information between a data preparation system and a logic device programmer. The MAX+PLUS II Compiler automatically generates JEDEC Files for the following devices during compilation:

EP330/EP320I/EP220 devices (Classic family)

EP610/EP610I/EP600I devices (Classic family)

EP910/EP910I/EP900I devices (Classic family)

EP1810/EP1800I devices (Classic family)

EPM5016 and EPM5032 devices (MAX 5000 family)

The MAX+PLUS II Programmer can use a JEDEC File created with MAX+PLUS II, MAX+PLUS (DOS), A+PLUS, or PLDshell Plus to program the Altera devices listed above, as well as FLASHlogic devices. The Programmer can also optionally save programming data plus functional test vectors in JEDEC File format.


J-lead glossary definition
J-lead

A device package option offered by Altera. Both ceramic J-lead chip carrier (JLCC) and plastic J-lead chip carrier (PLCC) packages are available.


JTAG boundary-scan testing glossary definition
JTAG boundary-scan testing

Testing that isolates a device’s internal circuitry from its I/O circuitry. This testing is made possible by the Joint Test Action Group (JTAG) Boundary-Scan Test (BST) architecture that is available in all FLEX 10K devices; all FLEX 8000 devices except the EPF8452, EPF8452A, EPF81188, and EPF81188A; all MAX 9000 devices; and all FLASHlogic devices. Serial data is shifted into boundary-scan cells in the device; observed data is shifted out and externally compared to expected results. Boundary-scan testing offers efficient PC board testing, providing an electronic substitute for the traditional "bed of nails" test fixture.

The JTAG BST architecture in all FLEX 10K, MAX 9000, and FLASHlogic devices also supports in-system multi-device JTAG chain device programming and configuration.


JTAG Chain File (.jcf) glossary definition
JTAG Chain File (.jcf)

An ASCII file (with the extension .jcf) that stores device names and optional programming file names for use in programming and/or configuring one or more devices in a JTAG chain. A JCF saves the information entered with the Programmer’s Multi-Device JTAG Chain Setup command (JTAG menu).


jump glossary definition
jump

Underlined text or a graphic that provides a link to other Help topics. The ordinary mouse pointer changes into the following hand pointer when it is over a jump:

You can click Button 1 on a jump that has a dotted underline to pop up a secondary topic on top of the current Help topic. Clicking on a jump with a solid underline makes that topic appear in the Help window.

You can also press Tab to select the next jump, then press Enter. Press Shift+Tab to select the previous jump.


keyword glossary definition
keyword

Words that are reserved for implementing syntax in files used as inputs to MAX+PLUS II, including AHDL Text Design Files (.tdf), Assignment & Configuration Files (.acf), Command Files (.cmd), EDIF Command Files (.edc), Library Mapping Files (.lmf), VHDL Design Files (.vhd), and Vector Files (.vec). For example, the keyword OF cannot be used as an unquoted symbolic name in an AHDL file.


latch glossary definition
latch

A level-sensitive clocked storage unit that stores a single bit of data. A high-to-low transition on the Latch Enable signal fixes the contents of the latch at the value of the data input until the next low-to-high transition of the Latch Enable.


Latch Enable glossary definition
Latch Enable

A level-sensitive signal that controls a latch. When it is high, the input flows through the output; when it is low, the output holds its last value.


LCA2XNF utility glossary definition
LCA2XNF utility

A Xilinx utility that generates a Xilinx Netlist Format File. To generate an XNF File that can be compiled with MAX+PLUS II, you must specify the -g command-line option for files created with XACT version 4.0, or the -g -v command-line options for files created with XACT version 5.0.


least significant bit (LSB) glossary definition
least significant bit (LSB)

The bit of a binary number that contributes the smallest quantity to the value of that number, i.e., the last member in a bus or group name. For example, the LSB for a bus or group named a[31..0] is a[0] (or a0).


Library Mapping File (.lmf) glossary definition
Library Mapping File (.lmf)

An ASCII text file (with the extension .lmf) used to map cells in EDIF Input Files (.edf) or symbols in OrCAD Schematic Files (.sch) to corresponding MAX+PLUS II primitives, megafunctions, and macrofunctions.


library of parameterized modules (LPM) glossary definition
Library of Parameterized Modules (LPM)

A technology-independent library of logic functions that are parameterized to achieve scalability and adaptability. Altera has implemented parameterized modules (also called "parameterized functions") from LPM version 2.0.1/2.1.0 that offer architecture-independent design entry for all MAX+PLUS II-supported devices. The MAX+PLUS II Compiler includes built-in compilation support for LPM functions used in schematic, AHDL, and EDIF input files.


License File (license.dat) glossary definition
license file (license.dat)

An ASCII file containing the list of features, software expiration date, number of licenses, and authorization code required to run MAXPLUS II on a UNIX workstation or on a PC that uses network licensing.

You can receive a license file by faxing the "Workstation Registration and License File Request Form" to Altera or by contacting Altera Marketing.


line style glossary definition
line style

The type of line chosen for line entry in the Graphic and Symbol Editors. The Line Style submenu of the Options menu and the Line Style drop-down list box on the toolbar display the current line style. The following styles are available:


linked simulation glossary definition
linked simulation

A MAX+PLUS II Simulator mode that uses a linked Simulator Netlist File (.snf) to simulate the logical performance of a super-project that consists of multiple, linked individual projects. A linked simulation uses the timing and/or functional netlist information from the combined SNFs of the individual linked sub-projects.

When the SNF for the current project is a linked SNF, the title bar of the Simulator window displays Simulator: Linked Simulation to indicate that it is set up to run in the linked simulation mode.


Linked SNF Extractor glossary definition
Linked SNF Extractor

The Compiler module that creates the linked Simulator Netlist File (.snf) required for multi-project simulation.


linked Simulator Netlist File (.snf) glossary definition
linked Simulator Netlist File (.snf)

A binary-format file (.snf) that contains timing and/or functional information for multi-project simulation. This file is created by the Compiler’s optional Linked SNF Extractor module when you compile a super-project created in a top-level design file, i.e., a project that combines instances of multiple, separate sub-projects.


location glossary definition
location

A generic term that refers to an assignable physical resource in the interior of an Altera device.

You can assign a logic function to one of the following locations:

An individual logic cell

An individual I/O cell

An individual embedded cell

A logic array block (LAB), embedded array block (EAB), row, or column

When you assign a logic function to a general location such as a LAB, EAB, row, or column, the Compiler can choose the best logic cell or embedded cell within the LAB, row, or column to use to implement the logic.


Log File (.log) glossary definition
Log File (.log)

An ASCII text file (with the extension .log) created by the MAX+PLUS II Simulator. The Log File records all commands, buttons, and on-screen options that are used during an interactive simulation session.


logic function or Design Entity glossary definition
logic function or Design Entity

A primitive, megafunction, macrofunction, or state machine, which may be represented as either a name or a symbol in a design file.


logical operator glossary definition
logical operator

An operator that performs a logic operation on nodes, groups, or numbers.

AHDL logical operators are NOT (!), AND (&), NAND (!&), OR (#), NOR (!#), XOR ($), and XNOR (!$).

VHDL logical operators are AND, NAND, OR, NOR, XOR, and NOT.


Logic Array Block (LAB) glossary definition
Logic Array Block (LAB)

A physically grouped set of logic resources in an Altera device. An LAB consists of a logic cell array and, in some device families, an expander product term array. Any signal that is available to any one logic cell in the LAB is available to the entire LAB.

In Classic devices, the logic in the LAB shares a global Clock signal. The LAB is fed by a global bus and a dedicated input bus. (In an EP1810 device, an LAB is synonymous with a quadrant.) In MAX 5000 and MAX 7000 devices, the LAB is fed by a Programmable Interconnect Array (PIA) and a dedicated input bus. In FLEX 8000, MAX 9000, and FLEX 10K devices, the LAB is fed by row FastTrack Interconnect paths and a dedicated input bus.


logic cell (LC) glossary definition
logic cell (LC)

The generic term for a basic building block of an Altera device. In Classic, MAX 5000, MAX 7000, and MAX 9000 devices, a logic cell (also called a macrocell) consists of two parts: combinatorial logic and a configurable register. The combinatorial logic allows a wide variety of logic functions. In FLEX 8000 and FLEX 10K devices, a logic cell (also called a logic element) consists of a look-up table (LUT), i.e., a function generator that quickly computes any function of four variables, and a programmable register to support sequential functions.

The register can be programmed as a flow-through latch; as a D, T, JK, or SR flipflop; or bypassed entirely for pure combinatorial logic. The register can feed other logic cells or feed back to the logic cell itself. Some logic cells feed output or bidirectional I/O pins on the device.

You can assign a logic function to a specific logic cell. You can also assign a logic function to a logic array block (LAB), a row, or a column to ensure that the function is implemented in a logic cell in a particular LAB, row, or column.

In FLEX 10K, FLEX 8000, and MAX 9000 devices, logic cells have "numbers" of the format LC<number>_<LAB name>, where <number> ranges from 1 to 8 and <LAB name> consists of the row letter and column number of the LAB. In Classic, MAX 5000, and MAX 7000 devices, logic cells have numbers of the format LC<number>, where <number> may consist of both digits and letters.

FLEX 10K, FLEX 8000, MAX 9000, and MAX 7000E devices have specialized logic cells, called I/O cells, on the periphery of the device.


logic cell (LC) number glossary definition
logic cell (LC) number

A number assigned to a logic function in a design file, which corresponds to a logic cell number on the actual device.

In FLEX 10K, FLEX 8000, and MAX 9000 devices, logic cells have "numbers" of the format LC<number>_<LAB name>, where <number> ranges from 1 to 8 and <LAB name> consists of the row letter and column number of the LAB. In Classic, MAX 5000, and MAX 7000 devices, logic cells have numbers of the format LC<number>, where <number> may consist of both digits and letters.


logic element glossary definition
logic element

A basic building block of an Altera FLEX 8000 or FLEX 10K device. A logic element (also known as a logic cell) consists of a look-up table (LUT)--i.e., a function generator that quickly computes any function of four variables--and a programmable flipflop to support sequential functions.

The register can be programmed as a flow-through latch; as a D, T, JK, or SR flipflop; or bypassed entirely for pure combinatorial logic. The register can feed other logic cells or feed back to the logic cell itself. Some logic cells feed output or bidirectional I/O pins on the device.

Logic elements (logic cells) have "numbers" of the format LC<number>_<LAB name>, where <number> ranges from 1 to 8 and <LAB name> consists of the row letter and column number of the LAB.


Logic Equation File (.lef) glossary definition
Logic Equation File (.lef)

An ASCII text file (with the extension .lef) generated by the A+PLUS Design Processor. The LEF expresses all design logic in terms of Boolean equations. An LEF can be saved as an Altera Design File (with the extension .adf) and compiled by the MAX+PLUS II Compiler.


LEF2AHDL Converter glossary definition
LEF2AHDL Converter

A utility available from Altera that converts a Logic Equation File (.lef) into an AHDL Text Design File (with the extension .tdf).


logic level glossary definition
logic level

The input and output logic levels of nodes and groups are defined with the following characters:

Character:	Logic Level:

0	Logic low (GND)

1	Logic high (VCC)

X	Undefined/Don’t Care (not permitted for initialization)

Z	High impedance (no input to pin); e.g., used for the "output" part of a bidirectional pin when the "input" part of the pin is driving in.

0 to 9, A to F	Used for groups and interpreted as binary, decimal, hexadecimal, or octal values according to the current radix. The most significant bit is first; the least significant bit is last.


logic option glossary definition
logic option

An option that controls the logic synthesis process on one or more logic functions.

A variety of logic options are available. Logic option assignments can be applied to individual logic functions; a group of logic option assignments, called a logic synthesis style, can be applied to individual logic functions. A default logic synthesis style is also applied to the project as a whole. The logic cell Turbo Bit logic option can also be turned on or off on a device-by-device basis.

Logic options can also be assigned as parameters for a megafunction or macrofunction.

 	Some logic options are not available with standard synthesis; all logic options are available with multi-level synthesis.


logic primitive glossary definition
logic primitive

A primitive that performs a logical operation on nodes or buses. Logic primitives include:

AND	NOR

BAND	NOT

BNAND	OR

BNOR	VCC

BOR	XNOR

GND	XOR

NAND

Logic primitives have the same function as the logical operators used in AHDL and VHDL.


Logic Programmer card glossary definition
Logic Programmer card

The LP6 expansion card required to run the MAX+PLUS II Programmer and program Altera devices.

MAX+PLUS II software currently supports the LP6 Programmer Card for use with PC-AT and compatible computers.


LP6 Logic Programmer card dipswitch settings glossary definition
LP6 Logic Programmer card dipswitch settings

The LP6 card can be configured for 16 different I/O addresses. The following table lists the legal settings for dipswitches 1 through 4 (1 = ON; 0 = OFF):

Base I/O Address (HEX)	Bit Settings

1	2	3	4

270	0	0	0	0

260	1	0	0	0

250	0	1	0	0

240	1	1	0	0

230	0	0	1	0

220	1	0	1	0

210	0	1	1	0

200	1	1	1	0

2F0	0	0	0	1

2E0	1	0	0	1

2D0	0	1	0	1

2C0	1	1	0	1

2B0	0	0	1	1

2A0	1	0	1	1

290	0	1	1	1

280 (default)	1	1	1	1


logic synthesis style glossary definition
logic synthesis style

A combination of logic synthesis option settings that are saved under a single name.

A logic synthesis style can be individually tailored for different device families, so that the logic synthesis option settings vary according to the architecture of the target device family.


Logic Synthesizer glossary definition
Logic Synthesizer

The Compiler module that uses several algorithms to minimize gate count, remove redundant logic, and utilize the device architecture as efficiently as possible. Processing can be customized with logic option and logic synthesis style assignments. This module also applies logic synthesis techniques to help implement timing requirements for a project.

Two types of logic synthesis are available: standard synthesis and multi-level synthesis. Some logic options are not available with standard synthesis.


macrocell glossary definition
macrocell

A basic building block in Altera Classic, MAX 5000, MAX 7000, and MAX 9000 devices. A macrocell (also known as a logic cell) consists of two parts: combinatorial logic and a configurable register. The combinatorial logic allows a wide variety of logic functions. Depending on the architecture of the device family, the register can be programmed as a flow-through latch; as a D, T, JK, or SR flipflop; or bypassed entirely for pure combinatorial logic. The register can feed other macrocells or feed back to the macrocell itself. Some macrocells feed output or bidirectional I/O pins on the device.

In Classic, MAX 5000, and MAX 7000 devices, macrocells (logic cells) have numbers of the format LC<number>, where <number> is specified in Devices & Adapters or the device data sheet. In MAX 9000 devices, macrocells have "numbers" of the format LC<number>_<LAB name>, where <number> ranges from 1 to 8 and <LAB name> consists of the row letter and column number of the LAB.


macrofunction glossary definition
macrofunction

A high-level building block that can be used together with gate and flipflop primitives and/or megafunctions in MAX+PLUS II design files.

In general, Altera recommends using megafunctions in preference to equivalent macrofunctions in all new projects. Megafunctions are easier to scale to different sizes and may offer more efficient logic synthesis and device implementation.

Altera provides a library of over 300 old-style macrofunctions in the \maxplus2\max2lib directory and its subdirectories created during installation. AHDL Include Files (.inc) for these macrofunctions are located in the \maxplus2\max2inc directory; VHDL Component Declarations for macrofunctions supported by VHDL are provided in the maxplus2 package in the altera library, which is located in the \maxplus2\max2vhdl directory.

On a UNIX workstation, the maxplus2 directory is a subdirectory of the /usr directory.

To view the file that contains the logic for a macrofunction, select the macrofunction symbol in the Graphic Editor or macrofunction name in the Text Editor and choose Hierarchy Down (File menu).


Master Programming Unit (MPU) glossary definition
Master Programming Unit (MPU)

A logic device programming box. The MPU works with zero-insertion-force sockets and individual adapters to program and test Altera devices.

The PL-MPU base unit and PLM-prefix adapters support both device programming and device testing. The PLE3-12 base unit, as well as adapters with other prefixes (e.g., PLE-prefix adapters and the PLAD3-12 adapter) support device programming only.


MAX 5000/EPS464 glossary definition
MAX 5000

An Altera device family based on the first generation of Multiple Array MatriX architecture. This EPROM-based device family includes the EPM5016, EPM5032, EPM5064, EPM5128, EPM5128A, EPM5130, EPM5192, and EPS464 devices.


MAX 7000 glossary definition
MAX 7000 (and MAX 7000E)

An Altera device family based on the second generation of Multiple Array MatriX architecture that includes MAX 7000 and MAX 7000E devices. These EPROM- and EEPROM-based devices include EPM7032, EPM7032V, EPM7064, EPM7096, EPM7128E, EPM7128, EPM7160E, EPM7160, EPM7192E, EPM7192, and EPM7256E devices.

MAX 7000E devices are enhanced versions of MAX 7000 devices and are function-, pin-, and programming-file-compatible with MAX 7000 devices. MAX 7000E devices differ from MAX 7000 devices in that they offer up to six pin- or logic-driven Output Enable signals, fast input setup times to logic cells, and multiple global Clocks with optional inversion.

Altera recommends using MAX 7000E devices rather than MAX 7000 devices for new designs.


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The text of the def_MAX7000 and def_MAX7000E glossary entries is identical now, because the two families are now considered to be one. However, since we use both entries in various Help files, it is better to have two identical popups.

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MAX 7000E glossary definition
MAX 7000 (and MAX 7000E)

An Altera device family based on the second generation of Multiple Array MatriX architecture that includes MAX 7000 and MAX 7000E devices. These EPROM- and EEPROM-based devices include EPM7032, EPM7032V, EPM7064, EPM7096, EPM7128E, EPM7128, EPM7160E, EPM7160, EPM7192E, EPM7192, and EPM7256E devices.

MAX 7000E devices are enhanced versions of MAX 7000 devices and are function-, pin-, and programming-file-compatible with MAX 7000 devices. MAX 7000E devices differ from MAX 7000 devices in that they offer up to six pin- or logic-driven Output Enable signals, fast input setup times to logic cells, and multiple global Clocks with optional inversion.

Altera recommends using MAX 7000E devices rather than MAX 7000 devices for new designs.


MAX 9000 glossary definition
MAX 9000

An Altera device family based on the third generation of Multiple Array MatriX architecture. These EEPROM-based devices include the EPM9560, EPM9480, EPM9400, and EPM9320 devices.


MAX+PLUS (DOS) glossary definition
MAX+PLUS (DOS)

Altera’s DOS-based Multiple Array MatriX Programmable Logic User System. MAX+PLUS is a set of computer programs and hardware support products for designing and implementing custom logic circuits with Altera Classic and MAX 5000 devices. Graphic Design Files (.gdf) created for MAX+PLUS are automatically converted and processed with the MAX+PLUS II Compiler; AHDL Text Design Files (.tdf) are compiled directly. The MAX+PLUS II Programmer can program Classic and MAX 5000 devices with JEDEC Files (.jed) and Programmer Object Files (.pof) created by MAX+PLUS.

MAX+PLUS is no longer offered by Altera. All new designs should be created with MAX+PLUS II.


MAX+PLUS II glossary definition
MAX+PLUS II

Altera’s Multiple Array MatriX Programmable Logic User System II. MAX+PLUS II is a set of computer programs and hardware support products that allow design and implementation of custom logic circuits with Classic, MAX 5000, MAX 7000, MAX 9000, FLEX 8000, FLEX 10K, and FLASHlogic devices.


MAX+PLUS II Message File (.mmf) glossary definition
MAX+PLUS II Message File (.mmf)

A binary file (with the extension .mmf) created by MAX+PLUS II that contains messages issued by any MAX+PLUS II application or command that runs as a background process, e.g., the Compiler and Programmer. This file is used to display messages in the Message Processor and to locate messages in design and ancillary files.


max2inc glossary definition
max2inc

A sub-directory of the maxplus2 directory containing AHDL Include Files (.inc) for all MAX+PLUS II macrofunctions. The files in this directory should not be modified in any way.

On a UNIX workstation, the maxplus2 directory is a subdirectory of the /usr directory.


max2lib glossary definition
max2lib

A subdirectory of the maxplus2 directory that contains Symbol Files (.sym), Graphic Design Files (.gdf), and Text Design Files (.tdf) for all MAX+PLUS II primitives, megafunctions, and macrofunctions supplied by Altera. These files are stored in the \prim, \mega_lpm, \mf, and \edif subdirectories of \max2lib. The \mega_lpm subdirectory also contains AHDL Include Files (.inc) for all MAX+PLUS II megafunctions. The files in these directories should not be modified in any way.

On a UNIX workstation, the maxplus2 directory is a subdirectory of the /usr directory.


maxplus2.idx file glossary definition
maxplus2.idx file

A text file, created automatically when you save a file, that maps filenames with more than eight characters to 8-character filenames.

MAX+PLUS II creates a maxplus2.idx file in each directory where you save a file that contains filenames with more than eight characters. The file is updated automatically each time you save a file with a long filename.


maxplus2.ini file glossary definition
maxplus2.ini file

A text file, created during installation, that contains the parameters that affect the way MAX+PLUS II applications operate. This file continuously records the options that you set in one session, so that they are automatically set for the next session.


Mealy state machine glossary definition
Mealy state machine

A type of state machine in which the outputs are a function of the inputs and the current state.

Mealy, George H., A Method for Synthesizing Sequential Circuits, in The Bell System Technical Journal, Vol. 34, American Telephone and Telegraph Company (September 1955).


megafunction glossary definition
megafunction

A complex or high-level building block that can be used together with gate and flipflop primitives and/or old-style macrofunctions in MAX+PLUS II design files.

Altera provides a library of megafunctions, including functions from the Library of Parameterized Modules (LPM) version 2.0.1/2.1.0, in the \maxplus2\max2lib\mega_lpm directory created during installation. AHDL Include Files (.inc) for these megafunctions are also located in the \maxplus2\max2lib\mega_lpm directory. (On a UNIX workstation, the maxplus2 directory is a subdirectory of the /usr directory.)

To view the file that contains the logic for a megafunction, select the megafunction symbol in the Graphic Editor or megafunction name in the Text Editor and choose Hierarchy Down (File menu).


Memory Initialization File (.mif) glossary definition
Memory Initialization File (.mif)

An ASCII file (with the extension .mif) that specifies the initial content of a memory block (RAM or ROM), i.e., the initial values for each address. This file is used during project compilation and/or simulation.


Memory Initialization Output File (.mio) glossary definition
Memory Initialization Output File (.mio)

An ASCII file (with the extension .mio) that is generated when the Compiler creates a Text Design Output File (.tdo) for a project. A TDO File that implements RAM or ROM always has an MIO File for each memory segment.

An MIO File specifies the memory addresses and values used to initialize a RAM or ROM segment, similar to the information in a Memory Initialization File (.mif).

You can rename an MIO File as an MIF and use it with a TDO File that has been saved as a Text Design File (.tdf).


Message Text File (.mtf) glossary definition
Message Text File (.mtf)

An ASCII file (with the extension .mtf) that contains the text of messages shown in a Message Processor window.


metastable state or metastability glossary definition
metastable state or metastability

Latches and flipflops are normally considered to have two unconditionally stable operating points, either 1 or 0. However, a third operating point called a metastable state or metastability exists when the cross-coupled arrangement is exactly balanced. This operating point is stable only if there is no noise in the system and the system is perfectly balanced.

A metastable latch or flipflop has an unpredictable delay and will therefore change its output at a time that differs from the value obtained from the worst-case timing analysis. Although this delay may not present a problem in a slow system, such a delay in a fast system may lead to a failure.


Minimization option glossary definition
Minimization option

A logic option that allows you to control the extent to which logic is reduced and simplified during logic synthesis. Minimization can be set to Full, Partial, or None.

If Minimization is set to Full, the Compiler’s Logic Synthesizer module minimizes a sum-of-products expression as much as possible, and removes redundant product terms. Full Minimization includes De Morgan’s inversion, and the resulting product terms may differ significantly from those in the original design file(s). This setting is appropriate for most logic.

If Minimization is set to Partial, the Logic Synthesizer performs simple logic optimization, but retains redundant product terms. Partial Minimization is the best setting for latches in MAX 7000 devices. When you use standard logic synthesis, Partial Minimization can be useful on SOFT, LCELL, OUTPUT, OUTPUTC, BIDIR, and BIDIRC primitives that are fed by combinatorial logic. A logic option setting of Resynthesize Network=On may partially override Minimization=Partial.

If Minimization is set to None, the Logic Synthesizer performs only trivial logic minimization, and retains redundant product terms.

The following examples shows how the Minimization options can affect logic:

Before:	t = a&b&!c # a&c # !a&d # b&d # c&d # a&b&c&d

None:	same as before

Partial:	t = a&b # a&c # !a&d # b&d # c&d

Full:	t = !(a&!b&!c # !a&!d )

ACF logic option syntax:

<name>: MINIMIZATION = (FULL|PARTIAL|NONE|DEFAULT|NULL)


Moore state machine glossary definition
Moore state machine

A state machine in which the present state depends only on its previous input and previous state, and the present output depends only on the present state.

Moore, Edward F., Gedanken-Experiments on Sequential Machines, in Automata Studies, Annals of Mathematics Studies Number 34, ed. C. E. Shannon and J. McCarthy, Princeton: Princeton University Press (1956).


most significant bit (MSB) glossary definition
most significant bit (MSB)

The bit of a binary number that contributes the greatest quantity to the value of that number, and the first member in a bus or group name. For example, the MSB for a bus named a[31..0] is a[31].


MPLD glossary definition
MPLD

Mask-Programmed Logic Device, i.e., a custom Altera device created by converting a design originally created for an Altera programmable logic device. Altera offers a program for converting customer designs into MPLDs, which are cost-effective alternatives for high-volume production.


multi-Clock network glossary definition
multi-Clock network

A Clock configuration in which there are two or more Clocks within a single device.


multi-device JTAG chain glossary definition
multi-device JTAG chain

A series of devices through which programming and/or configuration data are passed from device to device via the Joint Test Action Group (JTAG) Boundary-Scan Test (BST) circuitry.

MAX+PLUS II can program or configure multiple FLEX 10K, MAX 9000, and FLASHlogic devices in a multi-device JTAG chain.


Multi-Level Clock glossary definition
multi-level Clock

A Clock configuration in which a Clock is driven by combinatorial logic that expands beyond one level of logic, i.e., beyond a single AND or OR gate.


Multi-Level Factoring option glossary definition
Multi-Level Factoring option

A logic synthesis option that directs the Compiler’s Logic Synthesizer module to factor a sum-of-products or product-of-sums expression into multi-level form.

The following example shows how the Multi-Level Factoring option can affect logic:

Before:	t = a&e # b&c&e # b&d&e # a&f # b&c&f # b&d&f;

After:	t = (a # b&(c # d))&(e # f);

This option is available only if the SOFT Buffer Insertion logic option is turned on. A logic option setting of Resynthesize Network=On may partially override a logic option setting of Multi-Level Factoring=Off.

ACF logic option syntax:

<name>: MULTI_LEVEL_FACTORING = (ON|OFF|DEFAULT|NULL)


multi-level synthesis glossary definition
multi-level synthesis

Logic synthesis that takes advantage of all available logic options, including all options listed in the Define Synthesis Style and Advanced Options dialog boxes. This type of logic synthesis can handle projects with extremely complex logic, without requiring user intervention to achieve a fit.

Multi-level synthesis is only available for the MAX 5000, MAX 7000, MAX 9000, FLEX 8000, and FLEX 10K device families; it is always on for FLEX 8000 and FLEX 10K projects.

ACF global project option syntax:

MULTI_LEVEL_SYNTHESIS = (ON|OFF)


multi-window application glossary definition
multi-window application

A MAX+PLUS II application that allows you to open more than one window at the same time. The following applications allow multiple windows:

Graphic Editor

Text Editor

Waveform Editor

Symbol Editor

Message Processor


multiplying operator glossary definition
multiplying operator

In AHDL, multiplying operators perform multiplication and division operations on arithmetic expressions. Supported multiplying operators consist of multiplication (*), division (DIV), and modulus (MOD) operators.

In VHDL, multiplying operators perform arithmetic multiplication and division operations on groups and numbers. Supported multiplying operators consist of multiplication (*) and division (/) operators, which are predefined for any integer type. See Section 7.2.4: Multiplying Operators in the IEEE Standard VHDL Language Reference Manual for more information.


--------------------BEGINNING OF NON-TRANSLATED TEXT-----------------------------------------------

This file contains the following panels:

The messages in this file come from a variety of sources, including:

arcmsgs.msg	arcw module (NB: the arcw module includes project name change AND archiving functions) All arcw messages are documented in this file

maxmsgs.msg	maxw module

ffdmsgs.msg	ffdw module

prtmsgs.msg	prtw module

g2cmsgs.msg	g2cw module

an_msgs.msg	adftonet module

wprmsgs.msg	wprw module

s2emsgs.msg	s2ew module

ne_msgs.msg	netext module

ge_msgs.msg	genlib module

???what happened to fne_vhdl_not_found?

deleted from mnmess & here:

Command canceled

ssy_no_guard	MAX+PLUS II software guard MUST be installed

Out of expanded memory

--------------------END OF NON-TRANSLATED TEXT-----------------------------------------------


Archive failed

CAUSE:	MAX+PLUS II was unable to archive the project.

ACTION:	See the description of the message(s) that accompanies this message for further explanation.

See also:

Archiving a Project

MAX+PLUS II Messages

Message Format


Archive has been canceled

CAUSE:	MAX+PLUS II could not successfully create the archive directory, so the archive has been canceled.

ACTION:	Choose Project Archive (File menu) again and enter a new directory path.

See also:

Archiving a Project

MAX+PLUS II Messages

Message Format


Archiving <project name>

CAUSE:	MAX+PLUS II is currently archiving the specified project.

ACTION:	No action is required.

See also:

MAX+PLUS II Messages

Message Format


Invalid authorization code

CAUSE:	The authorization code you entered is incorrect, or is not the correct authorization code for your software guard.

ACTION:	Ensure that the software guard ID displayed in the Authorization Code dialog box (Options menu) is the same as the actual ID shown on the guard, and check that the guard is securely attached to a parallel port on your computer. Verify and re-enter the code. Be careful to distinguish between the letter L and the numeral 1. The authorization code is provided on the "STOP, READ THIS FIRST" card included with your MAX+PLUS II system, or is supplied by Altera.

See also:

Entering an Authorization Code

MAX+PLUS II Messages

Message Format


Can't archive file <name> cannot be archived: file does not exist
Can’t archive file <name>: file does not exist

CAUSE:	The specified file--a Fit File, Report File, maxplus2.ini, <project name>.ini, POF, SOF, or another file--does not exist for your project. These files are not required for archiving to be successful, but the MAX+PLUS II is warning you that they do not exist.

ACTION:	If you wish, you may recompile your project to generate the specified file(s), then archive the project again. Otherwise, no action is required.

See also:

MAX+PLUS II Messages

Message Format


Can't change project name to <name>
Can’t change project name to <name>

CAUSE:	MAX+PLUS II cannot change the project name to the specified name. This message may occur if your current top-level design file is an EDIF Input File or a VHDL Design File that has been compiled and which contains a subdesign with a name that does not match the filename.

ACTION:	Choose a different project name. You cannot save an EDIF Input File or a VHDL Design File to the name of a subdesign within that file.

See also:

Changing the Project Name

MAX+PLUS II Messages

Message Format


Can’t check file <filename>
Can’t copy file <name> onto itself

CAUSE:	You specified the same name for the archive directory as the project directory. MAX+PLUS II tried to copy the specified file onto itself.

ACTION:	Specify a different archive directory.

See also:

Archiving a Project

MAX+PLUS II Messages

Message Format


Can't create directory <name>
Can’t create directory <name>

CAUSE:	You chose a command that saves a file (e.g., Save As [File menu]), specified a directory name that did not exist, and chose Yes when MAX+PLUS II asked whether you wished to create the specified directory. However, MAX+PLUS II could not create the directory for one of the following reasons: the name contains an illegal character, you do not have write permission in the parent directory, or a file with that name already exists. You cannot create a directory that has the same name as a file.

ACTION:	Enter a different directory name with legal name characters, check that no file with the same name already exists, or check the write permissions in the directory where you wish to create the new directory. Remember that the \ character separates directory and file names in DOS and Windows; the / character separates directory and file names on UNIX workstations.

See also:

MAX+PLUS II Messages

Message Format

Saving a File


Can’t create project directory <name>

CAUSE:	MAX+PLUS II was unable to create an archive directory for the current project because you entered an invalid DOS pathname or because a file with that name already exists. You cannot create a directory that has the same name as a file.

ACTION:	Enter a different archive directory path and name with legal name characters, or delete the file and try again. Remember that the \ character separates directory and file names in DOS and Windows; the / character separates directory and file names on UNIX workstations.

See also:

Archiving a Project

MAX+PLUS II Messages

Message Format


Can’t delete style name <name
 Can’t delete style name <name>

CAUSE:	You tried to delete the "<new>" logic synthesis style name or the name of a predefined Altera logic synthesis style in the Define Synthesis Style dialog box. These style names cannot be deleted.

ACTION:	No action is required.

See also:

Defining a Logic Synthesis Style

MAX+PLUS II Messages

Message Format


Can’t edit MAX+PLUS II *.<extension> system files

CAUSE:	The file you tried to open is a MAX+PLUS II system file. MAX+PLUS II will prevent you from opening files that you should not edit directly, such as HIFs, MMFs, etc.

ACTION:	Try a different file.

See also:

MAX+PLUS II Messages

Message Format


Can’t find data in initial memory content (MIF/HEX) file

CAUSE:	The Memory Initialization File (.mif) or  Hexadecimal File (.hex) used to intialize memory does not contain any data.

ACTION:	Add data to the MIF or Hex File. Otherwise, remove the MIF or Hex File and specify a different source in the design file for the initialization of the RAM/ROM memory.

See also:

Initializing RAM/ROM Memory

MAX+PLUS II Messages

Message Format


Can’t find directory <directory name>
Can’t find directory <name>

CAUSE:	MAX+PLUS II could not find the specified directory when you entered a path and filename. This message may also indicate that the directory or disk is write-protected or corrupted.

ACTION:	Verify that you have entered the correct directory and path name and that the disk is not corrupted or write-protected.

See also:

MAX+PLUS II Messages

Message Format


Can’t find design file <name>

CAUSE:	During compilation or project archiving, MAX+PLUS II could not find the specified design file in the project directory or in any of the directories specified as MAX+PLUS II or user libraries. If the message occurs during archiving, it also indicates that an HIF exists for the project that indicates that the file should be present in the project directory or in one of the MAX+PLUS II or user libraries. This message may also indicate that the file or disk is read-protected, write-protected, or corrupted.

ACTION:	Check the project directory and the user and MAX+PLUS II libraries to make sure that the specified design file is listed. The User Libraries dialog box (Options menu) shows the user libraries for the current project; the maxplus2.ini file specifies the MAX+PLUS II libraries with the MAXPLUS_LIB variable. Make sure there is a design file for each HIF before archiving a project, and that the disk is not corrupted or read- or write-protected.

See also:

Archiving a Project

Creating & Using a Local Copy of the maxplus2.ini File

MAX+PLUS II Messages

Message Format

Specifying a User Library


Can’t find file <name>
Can’t find file <name> [<text>]

CAUSE:	After checking the specified directory and/or current DOS path, MAX+PLUS II could not find the specified file. This message may occur if the path or file does not exist, the file or disk is write-protected or corrupted, or if you have renamed a design file from outside of the MAX+PLUS II system. If the specified file is an EDIF Command File, the message indicates that the Compiler will also use default values.

ACTION:	Verify that you have entered the correct path/filename and that the disk is not corrupted or write-protected. Always rename a design file from within MAX+PLUS II, not from DOS.

See also:

MAX+PLUS II Messages

Message Format


Can’t find node <name> in this floorplan -- <text>
Can’t find node <name> in this floorplan -- [<text>]

CAUSE:	You tried to locate one or more nodes in the Floorplan Editor with the Find Node in Floorplan command (Utilities menu) or the Message Processor’s Locate or Locate All button. However, the node(s) do not appear in the current floorplan (e.g., the node(s) may have been synthesized away during compilation).

ACTION:	The node(s) either do not exist or appear in a different floorplan for the project. You can change the floorplan by choosing either Current Assignments Floorplan or Last Compilation Floorplan (Layout menu) in the Floorplan Editor (depending on which floorplan was originally displayed), and then repeat the find/locate action.

See also:

Finding Nodes & Pins in the Floorplan Editor

Locating the Source of a Message

MAX+PLUS II Messages

Message Format

Showing the Floorplan for Current Assignments

Showing the Floorplan for the Last Compilation


Can’t open file: <filename>
Can’t open file <filename>

CAUSE:	MAX+PLUS II could not open the specified file. This message may indicate that the file/path name was spelled incorrectly, the filename does not have the required extension, the file doesn’t exist, the disk is full, available memory is insufficient to open the file, an I/O error occurred when it opened the file, or your DOS config.sys file has a bad entry.

ACTION:	Ensure that you have at least 512 Kbytes of disk space, enough memory to run MAX+PLUS II, the disk is not corrupted, the disk is not read- or write-protected, and that buffers and files lines in your config.sys file are set to at least 15 and 50, respectively, i.e., buffers=15 and files=50.

See also:

MAX+PLUS II Messages

Message Format


Can’t overwrite file <filename>

CAUSE:	You tried to overwrite a file that is open, write-protected, or part of the current hierarchy tree. You can only overwrite files that are not write-protected, not open, and not part of the current hierarchy tree. Overwriting a file that is part of the current hierarchy tree would create recursive logic, which is not allowed in MAX+PLUS II.

ACTION:	If you wish to save the current file to the same name as another file that is already open, close the other file and try again. If the file you wish to overwrite is write-protected, change the write permissions and try again. Otherwise, save the file to a different filename.

See also:

MAX+PLUS II Messages

Message Format


Can't perform this action -- it edits the ACF for the project, which is already open in a Text Editor window etc.
Can’t perform this action -- it edits the ACF for the project, which is already open in a Text Editor window and contains unsaved changes. You must save the changes or close the file without saving before you can perform this action.

CAUSE:	You chose a menu command or attempted to perform another action that requires MAX+PLUS II to read data from and/or edit the ACF for the current project. Since the ACF is currently open in a Text Editor window, and contains unsaved changes, MAX+PLUS II cannot perform the desired action.

ACTION:	Either save the ACF in the Text Editor window or close the file without saving it before attempting to perform the desired action.

See also:

Closing a File

MAX+PLUS II Messages

Message Format

Saving a File


Can’t print: <text>

CAUSE:	MAX+PLUS II could not print. The <text> of the message usually indicates the source of the error.

ACTION:	Make sure the Windows Print Manager is set up correctly. Check the printer and/or plotter drivers: you may need to reinstall them. If the message indicates that it is necessary, delete some files to create more disk space or temporarily close other programs to make enough memory available. Refer to the Microsoft Windows User’s Guide and the documentation for your printer/plotter for more information.

See also:

MAX+PLUS II Messages

Message Format

Printing a File


Can’t read file <filename>

CAUSE:	MAX+PLUS II could not read the specified file. The file may be in a format that MAX+PLUS II does not recognize. This message may also indicate that the file or disk is corrupted.

ACTION:	Ensure that the file is in a format that MAX+PLUS II can recognize, and that the file or disk is not corrupted. You can also try typing chkdsk /f at a DOS prompt to check your disk for errors.

See also:

MAX+PLUS II Messages

Message Format


Can’t save file <filename>
Can’t save file <filename> [<text>]

CAUSE:	MAX+PLUS II could not save the specified file. The file may be write-protected or the disk may be full. Or, you may have tried to save to a filename of an existing file that is open and/or part of the current hierarchy tree, which is not allowed.

ACTION:	Ensure that the file/disk is not write protected. If the disk is full, delete some files to create disk space or save the file to a different disk. Save files only to filenames that are not part of the current hierarchy tree or that are not already open.

See also:

MAX+PLUS II Messages

Message Format


Can’t save hierarchy <design name>
Can’t save hierarchy for <name>

CAUSE:	MAX+PLUS II could not save the hierarchy for the specified project or file. The disk may be write-protected, corrupted, or full.

ACTION:	Ensure that the file/disk is not write protected or corrupted. If the disk is full, delete some files to create disk space or save the project to a different disk.

See also:

MAX+PLUS II Messages

Message Format


Can’t update ACF for this project before archiving -- archived file may be out of date

CAUSE:	When you chose Project Archive (File menu), MAX+PLUS II attempted to update the ACF for the project before archiving it, but could not. This message may indicate that the disk is full, the disk or file is read-protected, write-protected, missing or corrupted, or there has been a disk I/O error. Since MAX+PLUS II could not update the ACF, it has archived the existing ACF on disk. Therefore, the archived ACF may not be up to date.

ACTION:	Check that the file and/or disk are not corrupted or read- or write-protected. You should then choose Project Archive again to archive the updated versions of all files in your project.

See also:

Archiving a Project

MAX+PLUS II Messages

Message Format


Checkout of <application name> failed

CAUSE:	For the specified application or feature, there is no entry in the license file, other users are already using all available copies, or the license has expired.

ACTION:	Update the license file, as described in the MAX+PLUS II for Workstations Installation & System Administration Data Sheet. Contact Altera Marketing at (408) 894-7000 for information on how to purchase additional licenses or to renew an expired license.

See also:

MAX+PLUS II Messages

Message Format


Copied file <filename>

CAUSE:	MAX+PLUS II has successfully copied the specified file to the archive directory.

ACTION:	No action is required.

See also:

MAX+PLUS II Messages

Message Format


Directory <name> already exists [<text>]

CAUSE:	The directory name you specified is already used as a filename. MAX+PLUS II cannot change a file into a directory.

ACTION:	Enter a different directory name.

See also:

MAX+PLUS II Messages

Message Format


Directory <name> does not exist. OK to create it?

CAUSE:	You chose a command that saves or creates a file (e.g., Save As), but the specified directory name you entered does not exist.

ACTION:	Choose Yes to create the directory, No to return to the Save As dialog box and specify a different filename, or Cancel to cancel the command.

See also:

MAX+PLUS II Messages

Message Format

Saving a File


Error getting license file data

CAUSE:	The license manager cannot locate the license file on your workstation. This message can occur if your workstation does not have a license file or if the license manager does not have the correct pathname for the license file.

ACTION:	Ensure that each workstation has a valid license file, and that your environment variable LM_LICENSE_FILE is set to the correct path for the license file, as described in MAX+PLUS II Installation in the MAX+PLUS II Getting Started manual.

See also:

MAX+PLUS II Messages

Message Format


File <filename> already exists. OK to overwrite?
File <name> already exists. OK to overwrite?

CAUSE:	You chose a command that saves or creates a file (e.g., Save As, Create Default Symbol [File menu]), but a file with the specified name already exists.

ACTION:	Choose Yes or OK to overwrite the file, No to return to the Save As dialog box and specify a different filename, or Cancel to cancel the command. You can choose No, if available, to return to the Save As dialog box and specify a different filename.

See also:

Creating the Default Symbol for a File

MAX+PLUS II Messages

Message Format

Saving a File


Found node <name> in chip <name> -- select this chip in Floorplan Editor and repeat the find/locate action

CAUSE:	You tried to locate a node in a multi-device in the Floorplan Editor with the Find Node in Floorplan command (Utilities menu) or the Message Processor’s Locate or Locate All button. However, the node appears on a different chip.

ACTION:	In the Floorplan Editor, select the chip that contains the node from the Chip Name drop-down list box, and then repeat the find/locate action.

See also:

Finding Nodes & Pins in the Floorplan Editor

Locating the Source of a Message

MAX+PLUS II Messages

Message Format


Hex File contains invalid checksum <number> -- sum of bytes must be 0

CAUSE:	The Hexadecimal File (.hex) contains an illegal checksum value; the sum of bytes should equal 0.

ACTION:	Use the Message Processor’s Locate button to locate the error and correct it (i.e., edit the Hex File so that the sum of bytes equals 0). For more information on the format of the Hex File, refer to the Intel Hexadecimal Object File Format Specification, available from Intel Corporation.

See also:

Locating the Source of a Message

MAX+PLUS II Messages

Message Format


Hex File record error: <text>

CAUSE:	MAX+PLUS II has detected an error in one or more of the records in the  Hexadecimal File (.hex). The <text> at the end of the message usually indicates the source of the error. Each record contains the following fields: RECORD MARK, RECLEN (record length), LOAD OFFSET, RECTYP (record type), INFO or DATA, and CHKSUM (checksum). This error message can occur for a general error (e.g., record type is invalid) or an error in a particular record (e.g., Start Segment Address Record has an illegal format).

ACTION:	Use the Message Processor’s Locate button to locate the error(s) in the Hex File and correct them. For more information on the format of the Hex File, refer to the Intel Hexadecimal Object File Format Specification, available from Intel Corporation.

See also:

Locating the Source of a Message

MAX+PLUS II Messages

Message Format


I/O error - <text>
I/O error -- <text>

CAUSE:	The disk is full, the disk or file is read-protected, write-protected, missing or corrupted, there has been a disk I/O error, or the file format is out of date for the current version of MAX+PLUS II, so the file cannot be processed (i.e., opened, read, written, closed, or deleted). This error can also occur if the Compiler cannot find a design file because it is not listed in the maxplus2.ini file as a MAX+PLUS II or user library.

ACTION:	Check that the file and/or disk are not corrupted or read- or write-protected. If the file is corrupted or incompatible and was created by using MAX+PLUS II (i.e., a system file or an ancillary file with the extension .ini, .dbf, .cnf, .hif, .ndb, .prb, .sif, .snf, .pof, .jed, or .sof), you must delete and re-create the file. Many of these files can be re-created automatically by recompiling the project with the current version of MAX+PLUS II. If the file is specified as a corrupted, missing, or incompatible .crf, .ddf, .dmf, .daf, or .ptf file, reinstall MAX+PLUS II. If the specified file is an LMF or EDIF Command File, check the filenames you entered in the EDIF Netlist Reader Settings or EDIF Netlist Writer Settings dialog box (Interfaces menu), respectively. If the specified file is a MAX+PLUS II-provided macrofunction, and check the MAXPLUS_LIB variable in the maxplus2.ini file (if MAX+PLUS II is running, you must view the file from outside of MAX+PLUS II). If it does not list the correct directories, exit MAX+PLUS II, enter the correct directory names, save the changes, and restart MAX+PLUS II. If the file is a user-created design file, add the directory containing the file to the list of user libraries for the project with the User Libraries command (Options menu).

You should never edit MAX+PLUS II system files, including HIFs and or maxplus2.idx file. You should only edit the maxplus2.ini file if you are directed to do so in a message, Help procedure, or by Altera Applications.

See also:

MAX+PLUS II Installation in MAX+PLUS II Getting Started

Creating & Using a Local Copy of the maxplus2.ini File

Exiting from MAX+PLUS II

MAX+PLUS II Messages

Message Format

Specifying a User Library


Ignored initial memory content (MIF/HEX) file data -- address location is greater than the number of words

CAUSE:	The Memory Initialization File (.mif) or  Hexadecimal File (.hex) used to intialize memory contains more data fields than the memory depth (i.e., number of words) requires. The additional data is ignored. For example, the MIF or Hex File for a 2 x 8 RAM memory block may contain data for 6 addresses; since the depth is equal to 2, however, only the first 2 addresses are valid; the others are ignored.

ACTION:	Remove the unnecessary data.

See also:

Initializing RAM/ROM Memory

MAX+PLUS II Messages

Message Format


Illegal character in name
Illegal character in [<text>] name [<name>]

CAUSE:	You entered an illegal character in a name.

ACTION:	Re-enter the name with legal MAX+PLUS II name characters. When entering a filename, remember that the \ character separates directory and file names in DOS and Windows; the / character separates directory and file names on UNIX workstations.

See also:

MAX+PLUS II Messages

Message Format


Illegal device name <text>

CAUSE:	The specified name, which you entered in the Device dialog box (Assign menu), or which has occurred in the ACF, design file, or Fit File, is not a legal device name. If the error occurred in a GDF, it is in the title block of a MAX+PLUS (DOS) GDF. If the error occurred in an ADF or SMF, it is in the Part Section.

ACTION:	Use the Devices list box in the Device dialog box to select a legal device name. Check the design files and the Fit File for errors. (However, Fit Files should never be edited.) If you are using a GDF from MAX+PLUS (DOS), always open the file in MAX+PLUS II and update the title block before compiling.

See also:

ACF Format

Assigning a Device

Devices & Adapters

MAX+PLUS II Messages

Message Format


Illegal extension (*.<extension>) for the current editor
Illegal extension (.<extension>) for the current editor

CAUSE:	You specified an extension in the Save As dialog box (File menu) that is not valid for the current file.

ACTION:	Type a valid extension, or do not type an extension. If you do not type an extension, the filename is automatically appended with the extension shown in the Automatic Extension box.

See also:

MAX+PLUS II Messages

Message Format

Saving a File


Illegal filename: <name>

CAUSE:	You entered an illegal filename. This error can occur if you enter an illegal filename in a dialog box, or if you entered an illegal filename in your maxplus2.ini file before starting MAX+PLUS II.

ACTION:	Re-enter the name with legal MAX+PLUS II name characters. Up to 32 characters are permitted in the filename itself; a full pathname must not exceed 255 characters. When entering a filename, remember that the \ character separates directory and file names in DOS and Windows; the / character separates directory and file names on UNIX workstations.

See also:

MAX+PLUS II Messages

Message Format


Illegal file name or path: <text>

CAUSE:	You entered an illegal filename. The illegal portion of the name may consist of the disk drive name, the pathname, the filename, or the filename extension. This error can occur if you enter an illegal filename in a dialog box, or if you entered an illegal filename in your maxplus2.ini file before starting MAX+PLUS II.

ACTION:	Re-enter the name with legal MAX+PLUS II name characters. Up to 32 characters are permitted in the filename itself; a full pathname must not exceed 255 characters. When entering a filename, remember that the \ character separates directory and file names in DOS and Windows; the / character separates directory and file names on UNIX workstations.

See also:

MAX+PLUS II Messages

Message Format

Saving a File


Illegal option [<text>]
Illegal option [<text>] [for node <name>]

CAUSE:	You have made an option assignment--i.e., an illegal Turbo or Security Bit, BIT0, logic option, or logic synthesis style assignment--with an illegal option or style name or setting, or with additional unrecognizable text after the option or style setting. This message can also occur if you are compiling a GDF created with MAX+PLUS (DOS) that contains a title block with an illegal Turbo or Security Bit setting.

ACTION:	Check the assignment for errors. Use ON, OFF, and DEFAULT as option settings for Turbo and Security Bits in ACFs. You can use MSB, LSB, or ANY as the option settings for BIT0 in an AHDL TDF See logic option assignments for information on the syntax of all logic options and logic synthesis styles. If the error occurs for a MAX+PLUS (DOS) GDF, respecify the Turbo and/or Security Bit settings from within MAX+PLUS II.

See also:

Assigning an Individual Logic Option or Synthesis Style

Assigning Resources in a Third-Party Design Editor

MAX+PLUS II Messages

Message Format


Illegal timing assignment [name or] value [<text>]

CAUSE:	You have entered an illegal name or time value for a timing assignment. This message can occur if you choose OK after entering an illegal timing assignment in the Timing Requirement or Global Project Timing Requirements dialog box (Assign menu). It can also occur during compilation if you entered an illegal timing assignment in the project’s ACF.

ACTION:	Use the Timing Requirements or Global Projects Timing Requirements dialog box to enter a legal tpd, tco, tsu, fmax, and/or timing cut timing assignment. Be sure to enter a legal time followed immediately (i.e., with no space in between) by a time unit; the default unit is mhz for fmax and ns for tpd, tco, and tsu.

See also:

Assigning Individual Timing Requirements

Guidelines for Timing Assignments

MAX+PLUS II Messages

Message Format

Specifying Global Project Timing Requirements


Incorrect address range <number> in initial memory content (MIF/HEX) file

CAUSE:	The Memory Initialization File (.mif) or  Hexadecimal File (.hex) used to intialize memory contains an address that is outside the range of valid addresses. For example, this error occurs if you try to initialize Address 150 for a 100 x 2 RAM memory block, which contains Addresses 0 through 99.

ACTION:	Make sure that the addresses in the MIF or Hex File are less than or equal to the number of words minus 1 (e.g., Address 99 for a 100-word memory).

See also:

MAX+PLUS II Messages

Message Format


Internal error: <text>

An internal or stack overflow error may occur when a built-in software self-check fails. An internal error should be reported to the Altera Applications Department (go to Contacting Altera for information). Please report the exact message associated with the error and the exact keystrokes and mouse movements that led to the error.

If you are having a problem, please also do the following:

1.	Check whether the error can be reproduced.

2.	If you are running MAX+PLUS II under Windows 3.1 or Windows for Workgroups 3.11, determine the amount of available memory and free disk space by choosing About Program Manager from the Windows Program Manager’s Help menu.

3.	If you are running MAX+PLUS II under Windows 3.1 or Windows for Workgroups 3.11, determine the DOS version by typing ver at a DOS prompt. If you are running MAX+PLUS II on a Sun SPARCstation, HP 9000 Series 700, or ???rs6000 workstation, determine the operating system version by typing /usr/bin/uname -a at the prompt.

4.	If you are running MAX+PLUS II under Windows 3.1 or Windows for Workgroups 3.11, list the contents of your autoexec.bat and config.sys files. If you are running MAX+PLUS II on a SPARCstation, HP 9000 Series 700, or ???rs6000 workstation, list the contents of your .cshrc and .login files.

5.	Isolate or reduce the problem to its simplest form.

6.	Tell us the keystrokes you used and provide us with the files (or design data) that will re-create the problem. Go to Contacting Altera for information on the different ways to transfer data to Altera.

7.	Report the computer manufacturer and model number.

See also:

MAX+PLUS II Messages

Message Format

Recommended reading:

AB98 (Configuring Your PC for MAX+PLUS II Software)


Can't detect a software guard or a valid authorization code etc.
Can’t detect a software guard or a valid authorization code. However, you are authorized to use the MAX+PLUS II PLS-ES feature set until <time>. Press F1 for Help and info on obtaining an authorization code.

CAUSE:	Welcome to MAX+PLUS II! Because another MAX+PLUS II user at your company has purchased a copy of MAX+PLUS II software, your company has a site license to install an unlimited number of MAX+PLUS II systems with the PLS-ES feature set. Feel free to pass MAX+PLUS II software along to your colleagues. However, additional MAX+PLUS II systems on a site license do require you to contact Altera for a software authorization code. Since you do not have an authorization code, you are authorized to use the PLS-ES feature set for MAX+PLUS II software only for a limited time.

If you have installed a software guard, this message occurs only if the guard is not properly attached to the parallel printer port on your computer.

ACTION:	Contact Altera for an authorization code. Before contacting Altera, choose Authorization Code (Options menu) and make a note of the temporary "E"-prefix Software Guard ID shown in the dialog box.???

To contact Altera by fax, click on the underlined text here:

PLS-ES Site License Fax Form

You can then print a copy of the fax form by choosing the Print button at the top of the Help window.

If you cannot send a fax, you can contact Altera within North America by calling (800) SOS-EPLD. Customers outside North America should contact their local Altera distributor. You can also write to Altera at the following address:

Altera Corporation

2610 Orchard Parkway

San Jose, CA 95134-2020

USA

attn: PLS-ES Site Licensing


PLS-ES Site License Authorization Code Fax Form
FAX FORM: PLS-ES Site License Authorization Code Request

You can print a copy of this fax form by choosing the Print button at the top of the window.

To:	Altera PLS-ES Site Licensing

Fax Number:	(408) 954-8186

Please send me an authorization code for the MAX+PLUS II PLS-ES feature set.

My current "E"-prefix Software Guard ID is (as shown in the Authorization Code dialog box on the Options menu):

My Name:

Company:

Address:

City:

State/Province:

Country:

Zip/Postal Code:

Mail Stop:

Telephone Number:

Fax Number:


MAX+PLUS II system software problem: <text>

CAUSE:	Part of the system software required to run MAX+PLUS II is missing, corrupted, or expired, or your system lacks the necessary memory or disk space to run MAX+PLUS II. The <text> of the message indicates the source of the problem.

ACTION:	Reinstall MAX+PLUS II software. If you are using a demo version of MAX+PLUS II, you may need to contact Altera Marketing for a new authorization code.

See also:

MAX+PLUS II Messages

Message Format

Recommended reading:

MAX+PLUS II Installation in MAX+PLUS II Getting Started

read.me file for the current version of MAX+PLUS II


Memory <text> differs from MIF <text> -- ignoring MIF value

CAUSE:	The memory depth or width value you specified in your design file (GDF, TDF, or EDIF) does not match the depth or width in the Memory Initialization File (.mif) for the project.

ACTION:	No action is required. Make sure that the design files and MIF have the same depth and width values.

See also:

Initializing RAM/ROM Memory

MAX+PLUS II Messages

Message Format


MIF syntax error: <text>

CAUSE:	MAX+PLUS II has detected a syntax error in the project’s Memory Initialization File (.mif). The <text> at the end of the message usually indicates the source of the error (e.g.,  a missing or incorrect character or value).

ACTION:	Use the Message Processor’s Locate button to locate the error(s) in the MIF and correct them.

See also:

Locating the Source of a Message

MAX+PLUS II Messages

Message Format


OK to change project to <project name>?

CAUSE:	You selected a programming file that is not part of the current project or tried to save and check a file that is not part of the current project, so MAX+PLUS II is offering to automatically change the project name for you.

ACTION:	Choose OK to change the project name or Cancel to cancel the command.

See also:

MAX+PLUS II Messages

Message Format


OK to delete style <name>?

CAUSE:	You chose the Delete button in the Define Synthesis Style dialog box, so MAX+PLUS II is asking you to confirm whether you wish to delete the specified logic synthesis style.

ACTION:	Choose Yes to delete the style or No to keep it.

See also:

Defining a Logic Synthesis Style

MAX+PLUS II Messages

Message Format


One or more files in archive directory have the same name as the project. OK to overwrite these files?

CAUSE:	The archive directory you specified already exists. One or more of the files in this directory already have the same filename as the project. Therefore, if you continue archiving, you will overwrite the files in the directory that have the same names as the files you are archiving.

ACTION:	If you wish to continue, choose OK. To change the archive directory, choose Cancel, then choose Project Archive (File menu) again and specify a different directory.

See also:

MAX+PLUS II Messages

Message Format


Insufficient memory or I/O error <text>

CAUSE:	Available memory is insufficient or there is an I/O error, so MAX+PLUS II cannot operate normally. This message is most likely to occur when you start MAX+PLUS II with insufficient memory or insufficient swap space. It can also occur if one or more of the MAX+PLUS II system software libraries have become corrupted. Or, this message may occur when you are starting a network copy of MAX+PLUS II that experiences a time-out error (e.g., if the network is very busy).

ACTION:	Temporarily close other Windows programs to make enough memory available to run MAX+PLUS II and do not run other programs in the background. You may be able to free up more memory by exiting from Windows and then restarting Windows and MAX+PLUS II, and by increasing the size of the Windows swap file on your hard disk. You can also add more memory (RAM) to your computer.

If you have sufficient memory to run MAX+PLUS II, you may be experiencing a network time-out problem or have a corrupted MAX+PLUS II system software library. If you rule out the possibility of a network time-out, you may need to reinstall MAX+PLUS II software.

See also:

MAX+PLUS II Messages

Message Format

Recommended reading:

AB98 (Configuring Your PC for MAX+PLUS II Software)

MAX+PLUS II Installation in MAX+PLUS II Getting Started for information on maximizing available memory under Windows

Microsoft Windows User’s Guide for information on working with swap files under Windows

read.me file for the current version of MAX+PLUS II


Out of memory <text>

CAUSE:	Available memory is insufficient to continue running or to perform the specified operation.

ACTION:	Temporarily close other Windows programs to make enough memory available to run MAX+PLUS II and do not run other programs in the background. You may be able to free up more memory by exiting from Windows and then restarting Windows and MAX+PLUS II, and by increasing the size of the Windows swap file on your hard disk. You can also add more memory (RAM) to your computer.

If this message occurs during compilation, it may help to simplify the logic in your project by inserting LCELL or SOFT primitives. During project processing, these buffers may allow the Compiler to reduce the number of unique inputs that feed the node. It may also help to turn on the SOFT Buffer Insertion logic option in the global default logic synthesis style that is specified for the project as a whole.

See also:

Defining a Logic Synthesis Style

MAX+PLUS II Messages

Message Format

Specifying Global Project Logic Synthesis Settings

Recommended reading:

AB98 (Configuring Your PC for MAX+PLUS II Software)

MAX+PLUS II Installation in MAX+PLUS II Getting Started for information on maximizing available memory under Windows

Microsoft Windows User’s Guide for information on working with swap files


Out of MAX+PLUS II system resources. Terminating...

CAUSE:	MAX+PLUS II has run out of resources.

ACTION:	No action is required. MAX+PLUS II is closed automatically.

See also:

MAX+PLUS II Messages

Message Format


Pathname <name> does not exist [or contains an illegal character]

CAUSE:	You entered a pathname that does not exist or that contains an illegal character.

ACTION:	Enter an existing pathname for the file. If you entered the specified pathname in a dialog box, you can use Button 1 and the Directories box to navigate around the existing directories available on your computer. Enter a different path and file name with legal name characters and try again. Remember that the \ character separates directory and file names in DOS and Windows; the / character separates directory and file names on UNIX workstations.

See also:

MAX+PLUS II Messages

Message Format

Saving a File


Printer or plotter problem: <text>

CAUSE:	A problem exists with the setup or the device drivers for the printer or plotter. The <text> of the message indicates the source of the problem.

ACTION:	Check the printer setup listed in the Printer Setup dialog box (File menu). If you are running MAX+PLUS II under Windows, also check the setup in Printers in the Windows Control Panel; ensure that the printer and plotter drivers are compatible with Windows 3.1/Win32s and are installed in the correct directory; and refer to the Microsoft Windows User’s Guide and to the documentation for your printer or plotter for more information.

See also:

MAX+PLUS II Installation in MAX+PLUS II Getting Started

MAX+PLUS II Messages

Message Format


Project archived successfully

CAUSE:	MAX+PLUS II has archived your project without encountering any errors, and has successfully copied all files to the archive directory.

ACTION:	No action is required.

See also:

MAX+PLUS II Messages

Message Format


Project directory <name> does not exist. OK to create?
Project directory <name> does not exist. OK to create it?

CAUSE:	A directory name in the path you typed in the Project Name dialog box (File menu) does not exist, so MAX+PLUS II is offering to automatically create the directory.

ACTION:	Choose Yes to create the directory, No to return to the Project Name dialog box and specify a different name, or Cancel to cancel the command.

See also:

Changing the Project Name

MAX+PLUS II Messages

Message Format


Save all changes before compiling the project?

CAUSE:	You chose Start in the Compiler, but you have edited one or more files in the project since the project was last saved.

ACTION:	Choose Yes to save all changes before compiling the project, No to compile the project without saving changes, or Cancel to cancel the command. If you choose No, unsaved edits are not lost, but are not used in the compilation.

See also:

MAX+PLUS II Messages

Message Format


Saved file, but can’t check non-design file <filename>

CAUSE:	You chose Project Save & Check (File menu) when the current file was not a design file, so the MAX+PLUS II Compiler cannot process it. MAX+PLUS II has instead interpreted the command as a simple Save command (File menu).

ACTION:	No action is required. If you intended to save the current file as a design file, use Save As (File menu) to save the file with an appropriate extension for a design file.

See also:

MAX+PLUS II Messages

Message Format

Saving a File


Style name <name> already exists. OK to overwrite?

CAUSE:	You entered an existing logic synthesis style name in the Save Style As dialog box, so MAX+PLUS II is asking you to confirm whether you wish to overwrite the specified style.

ACTION:	Choose OK to overwrite the style, or choose Cancel to return to the Save Style As dialog box and specify a different name with up to 32 name characters.

See also:

Defining a Logic Synthesis Style

MAX+PLUS II Messages

Message Format


Style <name> has been edited. Do you want to save the edits?
Style name <name> has been edited. Do you want to save the edits?

CAUSE:	You chose a different logic synthesis style name in the Define Synthesis Style dialog box, but you had edited the settings for the current style, so MAX+PLUS II is asking you to confirm whether you wish to save or discard the unsaved edits to the specified style.

ACTION:	Choose Yes to save the edits to the current style, No to discard the edits, or Cancel to continue editing the current style.

See also:

Defining a Logic Synthesis Style

MAX+PLUS II Messages

Message Format


Symbol corrupted

CAUSE:	The symbol is corrupted. This message may occur if the file or disk is corrupted.

ACTION:	Quit MAX+PLUS II and ensure that the file or disk has not been corrupted. Then try restarting MAX+PLUS II. If this message occurs persistently for a symbol that represents one of your design files, you need to open the file and regenerate the symbol for it with Create Default Symbol (File menu). If it occurs persistently for another symbol, you must delete the symbol from the GDF.

See also:

Creating the Default Symbol for a File

MAX+PLUS II Messages

Message Format


Syntax error: [<text>]

CAUSE:	There is a syntax error in the specified file. The <text> at the end of the message usually indicates the source of the error.

ACTION:	Use the Message Processor to locate the source(s) of error and warning messages. If the error occurs in a design file that is imported into MAX+PLUS II, such as an EDIF Input File or an XNF File, it is best to edit the original source file, rather than the netlist that is imported into MAX+PLUS II.

See also:

Locating the Source of a Message

MAX+PLUS II Messages

Message Format


ACF syntax error: [<text>]

CAUSE:	There is a syntax error in the specified Assignment & Configuration File. The <text> at the end of the message usually indicates the source of the error.

ACTION:	If this message occurs after you save edits to an ACF in the Text Editor, use the Message Processor to locate the source(s) of error and warning messages. If it occurs when you first start MAX+PLUS II, you should open the ACF in the Text Editor, choose Save (File menu) to recheck the syntax, and then use the Message Processor to locate the source(s) of error and warning messages.

See also:

Locating the Source of a Message

Message Format


ADF syntax error: [<text>]

CAUSE:	There is a syntax error in the specified Altera Design File. The <text> at the end of the message usually indicates the source of the error.

ACTION:	Choose MAX+PLUS II Messages and scroll through the alphabetical list to locate the <text> of the message. Select the message for information on the probable cause and suggested action.

See also:

Locating the Source of a Message

Message Format


SMF syntax error: [<text>]

CAUSE:	There is a syntax error in the specified State Machine File. The <text> at the end of the message usually indicates the source of the error.

ACTION:	Choose MAX+PLUS II Messages and scroll through the alphabetical list to locate the <text> of the message. Select the message for information on the probable cause and suggested action.

See also:

Locating the Source of a Message

Message Format


TDF syntax error: [<text>]

CAUSE:	There is a syntax error in the specified Text Design File. The <text> at the end of the message usually indicates the source of the error.

ACTION:	Use the Message Processor to locate the source(s) of error and warning messages.

See also:

Locating the Source of a Message

MAX+PLUS II Messages

Message Format


Fit File syntax error: [<text>]

CAUSE:	There is a syntax error in the specified Fit File. The <text> at the end of the message usually indicates the source of the error.

ACTION:	Never edit the Fit File. You should recompile the project to generate a new Fit File that does not contain errors.

See also:

Locating the Source of a Message

MAX+PLUS II Messages

Message Format


Too many subdesigns -- only 200 are allowed

CAUSE:	Your project contains more than 200 subdesigns. MAX+PLUS II can archive up to 200 subdesigns.

ACTION:	Reorganize your project so you have fewer than 200 subdesigns, or archive the project manually.

See also:

Archiving a Project

MAX+PLUS II Messages

Message Format


Too many user libraries

CAUSE:	You have tried to add too many user libraries to the Existing Directories box in the User Libraries dialog box (Utilities menu).

ACTION:	Delete a library from the Existing Directories box and try again. You may need to move design files from one directory to another if your list of library directories would otherwise be too long. You can also move design files into the project directory: files in the project directory are automatically used in preference to files of the same name in the user or MAX+PLUS II libraries during compilation.

See also:

MAX+PLUS II Messages

Message Format

Specifying a User Library


Windows system error

CAUSE:	Microsoft Windows has experienced a system error.

ACTION:	Quit Windows, then restart Windows and MAX+PLUS II. It may also help to reboot your computer.

See also:

MAX+PLUS II Messages

Message Format


Message: Information on obtaining an authorization code on a site license
You have purchased an Altera development system that includes a site license to install an unlimited number of copies of MAX+PLUS II with the PLS-ES feature set. Press F1 for information on installing additional copies.

CAUSE:	Welcome to MAX+PLUS II! Because you have purchased a copy of MAX+PLUS II software, your company has a site license to install an unlimited number of MAX+PLUS II systems with the PLS-ES feature set. Feel free to pass MAX+PLUS II software along to your colleagues. However, additional MAX+PLUS II systems on a site license do require each individual user to contact Altera for a software authorization code.

ACTION:	When a user installs MAX+PLUS II software on another computer, he or she must contact Altera for an authorization code (at no cost). If no authorization code is present, he or she is authorized to use the PLS-ES feature set for MAX+PLUS II software only for a limited time.

Additional MAX+PLUS II site-license users must choose Authorization Code from the Options menu and make a note of the "E"-prefix Software Guard ID shown in the dialog box before contacting Altera.

To contact Altera by fax, click on the underlined text here:

PLS-ES Site License Fax Form

You can then print a copy of the fax form by choosing Print Topic from the File menu.

If you cannot send a fax, you can contact Altera within North America by calling (800) SOS-EPLD. Customers outside North America should contact their local Altera distributor. You can also write to Altera at the following address:

Altera Corporation

2610 Orchard Parkway

San Jose, CA 95134-2020

USA

attn: PLS-ES Site Licensing


Your version of MAX+PLUS II does not include the <name> application or feature

CAUSE:	The application or feature you tried to use is not available with the current configuration of MAX+PLUS II.

ACTION:	Choose an application or feature that was provided with your version of MAX+PLUS II. If you have purchased an upgrade to MAX+PLUS II, you may need to enter a new authorization code to enable new features and/or applications.

See also:

Entering an Authorization Code

MAX+PLUS II Messages

Message Format


Your version of MAX+PLUS II does not include an application that can edit *.<extension> files

CAUSE:	You tried to open a file with the specified extension, but the application that is needed to edit this type of file is not available with the current configuration of MAX+PLUS II.

ACTION:	Open only the types of files that are supported by your version of MAX+PLUS II. If you have purchased an upgrade to MAX+PLUS II, you may need to enter a new authorization code to enable new features and/or applications.

See also:

Entering an Authorization Code

MAX+PLUS II Messages

Message Format


--------------------BEGINNING OF NON-TRANSLATED TEXT-----------------------------------------------

the following panel should not??? appear on the mnmess list. users have been advised against changing the ini file, but apps may suggest changing it on limited occasions.

--------------------END OF NON-TRANSLATED TEXT-----------------------------------------------


 Variable <name> is set to <setting> [<text>]

CAUSE:	MAX+PLUS II has detected the specified variable and setting in the maxplus2.ini File or in the project’s Assignment & Configuration File (.acf). This variable may have been made available to you as part of a consultation with Altera Applications or in the read.me file file.

ACTION:	No action is required.

See also:

MAX+PLUS II Messages

Message Format


--------------------BEGINNING OF NON-TRANSLATED TEXT-----------------------------------------------

Following are the BLANK panels that Bill created for glmess.mac messages

--------------------END OF NON-TRANSLATED TEXT-----------------------------------------------


Illegal extension <extension> for a project name

CAUSE:	not written yet

ACTION:	not written yet

See also:

MAX+PLUS II Messages

Message Format


Megafunction authorization code error: <text>

CAUSE:	not written yet

ACTION:	not written yet

See also:

MAX+PLUS II Messages

Message Format


Can’t decrypt file <name> -- network license is not available

CAUSE:	not written yet

ACTION:	not written yet

See also:

MAX+PLUS II Messages

Message Format


File <name> is not recognized as part of the current project. Do you wish to change the project to <filename> before compiling?

CAUSE:	not written yet

ACTION:	not written yet

See also:

MAX+PLUS II Messages

Message Format


OK to use <filename> as the project name instead of <project name>?

CAUSE:	not written yet

ACTION:	not written yet

See also:

MAX+PLUS II Messages

Message Format


OK to exit from MAX+PLUS II?

CAUSE:	not written yet

ACTION:	not written yet

See also:

MAX+PLUS II Messages

Message Format


Can’t switch between network licensing and software guard-based authorization code until all MAX+PLUS II editor windows are clos
Can’t switch between network licensing and software guard-based authorization code until all MAX+PLUS II editor windows are closed

CAUSE:	not written yet

ACTION:	not written yet

See also:

MAX+PLUS II Messages

Message Format


Network licensing error: <text>

CAUSE:	not written yet

ACTION:	not written yet

See also:

MAX+PLUS II Messages

Message Format


Network license not available: <text>

CAUSE:	not written yet

ACTION:	not written yet

See also:

MAX+PLUS II Messages

Message Format


Invalid authorization code

CAUSE:	not written yet

ACTION:	not written yet

See also:

MAX+PLUS II Messages

Message Format


No software guard detected

CAUSE:	not written yet

ACTION:	not written yet

See also:

MAX+PLUS II Messages

Message Format


Memory declaration error: <text>

CAUSE:	not written yet

ACTION:	not written yet

See also:

MAX+PLUS II Messages

Message Format


Assert Statement message string uses <number> parameters, but only <number> are listed

CAUSE:	not written yet

ACTION:	not written yet

See also:

MAX+PLUS II Messages

Message Format


Illegal use of signal(s) <name(s)> in an arithmetic expression -- only Boolean expressions can contain signals

CAUSE:	not written yet

ACTION:	not written yet

See also:

MAX+PLUS II Messages

Message Format


Result of expression <name> is negative

CAUSE:	not written yet

ACTION:	not written yet

See also:

MAX+PLUS II Messages

Message Format


Can’t use <name> as an iterator variable -- it is already used as a constant, parameter, or node name

CAUSE:	not written yet

ACTION:	not written yet

See also:

MAX+PLUS II Messages

Message Format


Undefined evaluated function <name> in expression

CAUSE:	not written yet

ACTION:	not written yet

See also:

MAX+PLUS II Messages

Message Format


Illegal use of evaluated function <name> in a Boolean expression -- only arithmetic functions can contain evaluated functions

CAUSE:	not written yet

ACTION:	not written yet

See also:

MAX+PLUS II Messages

Message Format


Evaluated function <name> defined more than once

CAUSE:	not written yet

ACTION:	not written yet

See also:

MAX+PLUS II Messages

Message Format


Parameter <name> value assigned more than once

CAUSE:	not written yet

ACTION:	not written yet

See also:

MAX+PLUS II Messages

Message Format


Illegal message variable in Assert Statement -- only constants, parameters, and arithmetic expressions are allowed

CAUSE:	not written yet

ACTION:	not written yet

See also:

MAX+PLUS II Messages

Message Format


Illegal severity level <text> used in Assert Statement -- only INFO, ERROR, or WARNING is allowed

CAUSE:	not written yet

ACTION:	not written yet

See also:

MAX+PLUS II Messages

Message Format


Illegal quoted string <text> in arithmetic expression

CAUSE:	not written yet

ACTION:	not written yet

See also:

MAX+PLUS II Messages

Message Format


Illegal dual-range group notation

CAUSE:	not written yet

ACTION:	not written yet

See also:

MAX+PLUS II Messages

Message Format


Illegal mix of single- and dual-range group notation

CAUSE:	not written yet

ACTION:	not written yet

See also:

MAX+PLUS II Messages

Message Format


Can’t use non-numeric parameter value <text> in an arithmetic expression

CAUSE:	not written yet

ACTION:	not written yet

See also:

MAX+PLUS II Messages

Message Format


Symbolic name <name> was not declared as a <text>-range group

CAUSE:	not written yet

ACTION:	not written yet

See also:

MAX+PLUS II Messages

Message Format


Parameters cannot be applied to primitives

CAUSE:	not written yet

ACTION:	not written yet

See also:

MAX+PLUS II Messages

Message Format


Can’t find an inherited or default value for parameter <name>

CAUSE:	not written yet

ACTION:	not written yet

See also:

MAX+PLUS II Messages

Message Format


Can’t compare a number to a string

CAUSE:	not written yet

ACTION:	not written yet

See also:

MAX+PLUS II Messages

Message Format


Illegal quoted constant value: <text>

CAUSE:	not written yet

ACTION:	not written yet

See also:

MAX+PLUS II Messages

Message Format


Ignored operator instance name <name> -- instance names are permitted only for operators in Boolean expressions that generate lo
Ignored operator instance name <name> -- instance names are permitted only for operators in Boolean expressions that generate logic

CAUSE:	not written yet

ACTION:	not written yet

See also:

MAX+PLUS II Messages

Message Format


Ignored duplicate operator instance name <name> -- only the first is accepted (others are ignored)

CAUSE:	not written yet

ACTION:	not written yet

See also:

MAX+PLUS II Messages

Message Format


Parameter or constant <name> has not been defined -- assuming <name>was intended to be a quoted string

CAUSE:	not written yet

ACTION:	not written yet

See also:

MAX+PLUS II Messages

Message Format


You have selected <number> file(s) to print. OK to print the file(s)?

CAUSE:	not written yet

ACTION:	not written yet

See also:

MAX+PLUS II Messages

Message Format


Cant’ find hierarchy node <name>
Can’t find hierarchy node <name>

CAUSE:	not written yet

ACTION:	not written yet

See also:

MAX+PLUS II Messages

Message Format


--------------------BEGINNING OF NON-TRANSLATED TEXT-----------------------------------------------

This file contains descriptions of all global commands. Global commands are defined as commands that exist in all MAX+PLUS II applications or commands that exist in all design editor applications plus other applications. However, although assignment-type commands exist in all MAX+PLUS II applications, they are stored in fecom, not here.

At the end of the file, you will find the text of common "global"-type popups for dialog box segmented hypergraphics.

Note: the following dialog boxes do NOT have segmented hypergraphics: About MAX+PLUS II, Select Window. Segmented hypergraphics will be added for these dialog boxes only if the commands on the Help and Window menus are broken up into separate panels at some future date.

--------------------END OF NON-TRANSLATED TEXT-----------------------------------------------


Application & Document Control Menu Commands (all applications)
Application & Document Control Menu Commands

Shortcuts

Application Control menu commands manipulate windows and icons in all Windows applications???. Commands on this menu are available when you click Button 1 on the Application Control Menu box ( [image]).

Document Control commands manipulate windows within MAX+PLUS II. Commands on this menu are available when you click Button 1 on the Document Control Menu box ( [image]).

For more information on working with Microsoft Windows, choose Contents from the Help menu in the Windows Program Manager or consult the Microsoft Windows User’s Guide.

Command:	Action:

Restore	Restores a window to its original size after it has been shrunk to an icon with the Minimize command, enlarged with the Maximize command, or resized with the Size command.

Move	Allows you to move the window to another position on the desktop with the keyboard.

Size	Allows you to change the size of the window with the keyboard.

Minimize	Shrinks the active window to an icon.

Maximize	Enlarges the active window to its maximum size.

Close	Closes the active window.

Switch To	Displays the Task List, which lets you switch between running applications and rearrange windows and icons on your desktop.

Next	Switches to the next open MAX+PLUS II window or icon.

Shortcuts:

Close	Alt+F4

Switch To	Ctrl+Esc

Next	Ctrl+F6


MAX+PLUS II Menu Commands (all applications)
MAX+PLUS II Menu Commands

Shortcuts

MAX+PLUS II menu commands are used to start MAX+PLUS II applications and to switch between them.

The following applications are available from the MAX+PLUS II menu (* indicates single-window applications):

Command:	Action:

Hierarchy Display*	Opens the Hierarchy Display window, which shows the current hierarchy and provides a quick way to open and move between files in the current hierarchy or the project hierarchy.

Graphic Editor	Opens a Graphic Editor window, which offers a sophisticated schematic capture program that allows you to create and edit GDFs and OrCAD Schematic Files.

Text Editor	Opens a Text Editor window, which enables you to create, edit, and view AHDL TDFs and other MAX+PLUS II ASCII text files.

Waveform Editor	Opens a Waveform Editor window, which provides a graphical environment for creating and editing WDFs, and for creating simulation inputs and analyzing simulation outputs in SCFs.

Symbol Editor	Opens a Symbol Editor window, which allows you to view, create, and edit your own Symbol Files for use in Graphic Editor files.

Floorplan Editor*	Opens the Floorplan Editor window, which allows you to view and edit pin and logic cell assignments for the current project.

Compiler*	Opens the Compiler window, which enables you to synthesize the logic, fit the project, generate netlist files for simulation, and assemble a file for programming one or more Altera devices.

Simulator*	Opens the Simulator window, which allows you to model the logic and timing characteristics of a project before you actually commit it to hardware.

Timing Analyzer*	Opens the Timing Analyzer window, which enables you to analyze the timing performance of a project.

Programmer*	Opens the Programmer window, which, together with the MPU and appropriate adapters, allows you to program Altera devices.

Message Processor	Opens a Message Processor window, which displays error, information, and warning messages from other MAX+PLUS II applications and background processes.

If you choose a single-window application that is already open, MAX+PLUS II brings the open window to the front. If you choose a multi-window application, MAX+PLUS II brings the window of the most recently active file to the front or opens a new window in that application.

Some MAX+PLUS II development systems do not include all MAX+PLUS II applications. If your system is missing one or more applications, you may need to enter a new authorization code or use the Install program to install additional features and applications.

Shortcuts:

Hierarchy Display

Floorplan Editor

Compiler

Simulator

Timing Analyzer

Programmer

See also:

Entering an Authorization Code

Starting MAX+PLUS II Applications

Switching between MAX+PLUS II Applications


Project Name Command (all applications)
Project Name Command (File Menu)

Shortcuts

Specifies the project name.

The project name is the name of the top-level design file or a programming file in a hierarchy, without the filename extension. The project includes all design files and ancillary files in the hierarchy, as well as all other files generated for the project by the user and by MAX+PLUS II software.

Click Button 1 on any item in this dialog box for information on that item:

If you change the type but not the filename of the top-level design file in a project--e.g., if you have saved a top-level OrCAD Schematic File as a GDF, or if you have created a top-level TDF to replace a top-level GDF--you must use Change File Type (File menu) in the Hierarchy Display to update the hierarchy for the project.

If you specify a project name before you create a design file for the project, the project is assumed to have the same device family as the previous project.

This command is available only if MAX+PLUS II is not running a background process.

Shortcut:	Ctrl+J or

See also:

Changing the File Type (Hierarchy Display)

Changing the Project Name


Project Name

Specifies the name of the project. The name of the current project is displayed as the default.

You can type the name of an existing top-level design file or programming file, or select a filename in the Files/Projects box to copy it to the Project Name box. If you wish to name a project before you have created the top-level design file, you can type a new project name with up to 32 name characters. If you type the name of a directory that does not exist, MAX+PLUS II offers to create it for you.

You can type a text string that includes wildcard characters in the Project Name box and choose OK to update the contents of the Files/Projects box with the names of the files that match the text string. If Show Only Tops of Hierarchies is turned on, the Files/Projects box lists only top-level design files and programming files.


Files/Projects

The Files box lists files in the current directory that match the text string(s) in the Project Name box. By default, the Files box lists all design files and programming files.

The name of the Files box changes to Projects if Show Only Tops of Hierarchies is turned on. The Projects box lists only top-level design files and programming files, without their filename extensions.

Selecting a name in the Files/Projects box copies it to the Project Name box. If Show Only Tops of Hierarchies is turned off, you can also type a text string that includes wildcard characters in the Project Name box and choose OK to update the contents of the Files/Projects box with the names of the files that match the text string.


Show Only Tops of Hierarchies

Displays only top-level design files and programming files in the Files/Projects box.

When this option is turned off, the Files/Projects box lists all design files and programming files by default.


Directory is; Project Name command
Directory is

Displays the current directory. Files in the current directory are listed in the Files box.

You can type a different pathname in the Project Name box and choose OK or double-click Button 1 on a name in the Directories box to change the current directory.


Directories; Project Name command
Directories

Lists all available subdirectories of the current directory.

You can type a different absolute or relative pathname in the Project Name box and choose OK or double-click Button 1 on a name in the Directories box to change the current directory.


Project Name dialog box

Click Button 1 on any item in this dialog box for information on that item:


Project Set Project to Current File Command (all applications)
Project Set Project to Current File Command (File Menu)

Shortcuts

Changes the project name to the name of the file displayed in the current active window.

The project name is the name of the top-level design file or a programming file in a hierarchy, without the filename extension. The project includes all design files and ancillary files in the hierarchy, as well as all other files generated for the project by the user and by MAX+PLUS II software.

If you change the type but not the filename of the top-level design file in a project--e.g., if you have saved a top-level OrCAD Schematic File as a GDF, or if you have created a top-level TDF to replace a top-level GDF--you must use Project Set Project to Current File or the Hierarchy Display’s Change File Type command (File menu) to update the hierarchy for the project.

This command is available only if MAX+PLUS II is not running a background process.

See also:

Changing the File Type (Hierarchy Display)

Changing the Project Name


Project Save & Compile Command (all applications)
Project Save & Compile Command (File Menu)

Shortcuts

Saves all open Compiler input files in the current project and starts the MAX+PLUS II Compiler.

Project Save & Compile saves all open design files that are part of the current project, as well as ancillary files such as the project’s ACF and MIFs that contain information used by the Compiler.

As soon as the files are saved, the MAX+PLUS II Compiler window opens and the Compiler processes the project.

1.	If the current file is not part of the current project, it is not saved or compiled. Project Save & Compile operates only on the current project.

2.	If you open a lower-level file in the project with Open or Retrieve (File menu), it is considered to be the top of a different hierarchy tree, and edits you enter will not be saved when you compile the project. You must use the Hierarchy Display window or Hierarchy Down (File menu) to open the lower-level files in the hierarchy to ensure that your edits will be saved when you compile the project.

3.	When you save an OrCAD Schematic File in the Graphic Editor, some information from the original file is lost. Refer to Restrictions on OrCAD Schematic Files in MAX+PLUS II and Guidelines for Working with OrCAD Schematic Files for important information on working with OrCAD Schematic Files.

Project Save & Compile is not available if the project is untitled or if MAX+PLUS II is running a background process.

See also:

Changing the Project Name

Compiling a Project

Navigating the Hierarchy

Saving a File


Project Save & Simulate Command (all applications)
Project Save & Simulate Command (File Menu)

Shortcuts

Saves all Vector Files and/or SCFs in the current project that are specified with the Simulator’s Inputs/Outputs command (File menu) and starts the MAX+PLUS II Simulator.???

As soon as the files are saved, the MAX+PLUS II Simulator window opens and the Simulator processes the project.

The Simulator uses the SCF or Vector File with the same filename as the project, or the file that was last specified with Inputs/Outputs as the source of input vectors for the project. However, if both an SCF and a Vector File exist for the project, the Simulator uses the most recently edited file. This feature allows you to edit either file to adjust the simulation vectors before you resimulate the project.

Project Save & Simulate is not available if the project is untitled or MAX+PLUS II is running a background process.

If the current file is not part of the current project, it is not saved or used for simulation. Project Save & Simulate operates only on the current project.

See also:

Running an Interactive-Mode Simulation

Saving a File

Starting, Pausing & Stopping the Simulator


Project Save, Compile & Simulate Command (all applications)
Project Save, Compile & Simulate Command (File Menu)

Shortcuts

Saves all open Compiler and Simulator input files and then compiles and simulates the project.

??? design files in the current project, saves all open Vector Files and/or SCFs in the current project that are specified with the Simulator’s Inputs/Outputs command (File menu), and compiles and simulates the project.

Project Save, Compile & Simulate saves all design files that are part of the current project, as well as ancillary files such as the project’s ACF and MIFs that contain information used by the Compiler. Project Save, Compile & Simulate also saves all open ancillary files that contain information used by the Simulator, including Vector Files, SCFs, and MIFs.

The Simulator uses the SCF or Vector File with the same filename as the project, or the file that was last specified with Inputs/Outputs as the source of input vectors for the project. However, if both an SCF and a Vector File exist for the project, the Simulator uses the most recently edited file. This feature allows you to edit either file to adjust the simulation vectors before you recompile and resimulate the project.

As soon as the files are saved, the MAX+PLUS II Compiler processes the project; if compilation is successful, the MAX+PLUS II Simulator then simulates the project.

1.	If the current file is not part of the current project, it is not saved, compiled, or used for simulation. Project Save, Compile & Simulate operates only on the current project.???

2.	If you open a lower-level file in the project with Open or Retrieve (File menu), it is considered to be the top of a different hierarchy tree, and edits you enter will not be saved when you compile or simulate the project. You must use the Hierarchy Display window or Hierarchy Down (File menu) to open the lower-level files in the hierarchy to ensure that your edits will be saved when you compile the project.

3.	When you save an OrCAD Schematic File in the Graphic Editor, some information from the original file is lost. Refer to Restrictions on OrCAD Schematic Files in MAX+PLUS II and Guidelines for Working with OrCAD Schematic Files for important information on working with OrCAD Schematic Files.

Project Save, Compile & Simulate is not available if the project is untitled or if MAX+PLUS II is running a background process.

See also:

Changing the Project Name

Compiling a Project

Navigating the Hierarchy

Running an Interactive-Mode Simulation

Saving a File

Starting, Pausing & Stopping the Simulator


Project Archive Command (all applications)
Project Archive Command (File Menu)

Copies all files that belong to one project into a single archive directory.

Project Archive saves a backup copy of all files in a project. This process ensures that edits made subsequently to files in the project directory do not affect the files in the archive directory.

Click Button 1 on any item in this dialog box for information on that item:

When you choose OK, MAX+PLUS II copies all project files to the archive directory.

The following files that are part of the current project are copied to the archive directory:

Altera Design File (.adf)	Serial Bitstream File (.sbf)

Assignment & Configuration Output File (.aco)	Simulator Channel File (.scf)

Command File (.cmd)	Simulator Initialization File (.sif)

Compiler Netlist File (.cnf)	Simulator Netlist File (.snf)

Design Library System File (.dls)	SRAM Object File (.sof)

EDIF Input File (.edf)	State Machine File (.smf)

EDIF Command File (.edc)	Symbol File (.sym)

EDIF Output File (.edo)	Table File (.tbl)

Graphic Design File (.gdf)	Tabular Text File (.ttf)

Hexadecimal (Intel-Format) File (.hex)	Text Design Export File (.tdx)

Hierarchy Interconnect File (.hif)	Text Design File (.tdf)

History File (.hst)	Text Design Output File (.tdo)

Include File (.inc)	Timing Analyzer Output File (.tao)

JEDEC File (.jed)	Waveform Design File (.wdf)

Library Mapping File (.lmf)	Vector File (.vec)

Log File (.log)	Verilog Output File (.vo)

OrCAD Schematic File (.sch)	VHDL Design File (.vhd)

OrCAD Library File (.lib)	VHDL Output File (.vho)

Programmer Log File (.plf)	Xilinx Netlist Format File (.xnf)

Programmer Object File (.pof)

The following files are also archived, provided they have the same filename as the current project:

Assignment & Configuration File (.acf)	<Project Name>.ini

Fit File (.fit)	Report File (.rpt)

Fitter Input File (.fin)	Message Text File (.mtf)

MAX+PLUS II Message File (.mmf)	Probe & Resource Assignment File (.prb)

If an existing file in the archive directory has the same name as one of the project’s files, you are asked if you wish to overwrite the file.

Project Archive is not available if the project is untitled or if MAX+PLUS II is running a background process.

See also:

Archiving a Project


Archive Directory; Project Archive command
Archive Directory

Specifies the name of the archive directory. The default archive directory is a subdirectory of the current project directory called <project name>.dir.

You can type an absolute or relative pathname in the Archive Directory box or select an existing directory name in the Directories box to copy it to the Archive Directory box. If you type the name of a directory that does not exist, MAX+PLUS II creates it for you.


Directories (Project Archive command)
Directories

Lists all available subdirectories of the current directory.

You can type a different absolute or relative pathname in the Archive Directory box and choose OK or double-click Button 1 on a name in the Directories box to change the current directory.


Directory is; Project Archive command
Directory is

Displays the current directory. Files in the current directory are listed in the Files box.

You can type a different absolute or relative pathname in the Archive Directory box and choose OK or double-click Button 1 on a name in the Directories box to change the current directory.


Project Archive dialog box

Click Button 1 on any item in this dialog box for information on that item:


Project 1, 2, 3, 4... Command (all applications)
Project 1, 2, 3, 4... Command (File Menu)

Changes the project name to the name of a previously edited project.

The bottom of the Project menu can list up to eight previously edited projects, with the current project displayed first. Choose one of the displayed names to change the project name.

See also:

Changing the Project Name


New Command (all applications)
New Command (File Menu)

Shortcuts

Opens a new, untitled file in the Graphic, Text, Waveform, or Symbol Editor.

Click Button 1 on any item in this dialog box for information on that item:

When you create a new file, it is assumed to be part of the current project, and is assigned to the same device family as the project. After you save the file, you can change its device family if necessary. The device family for a design file is important if you use family-specific logic functions in your project.

Shortcut:	 ???or you can open an editor from the M+2 menu

See also:

Creating a New File

Saving a File


New dialog box

Click Button 1 on any item in this dialog box for information on that item:


Graphic Editor file

Creates a new, untitled file in a Graphic Editor window. You can select the .gdf or .sch filename extension in the drop-down list box to create a file in the GDF or OrCAD Schematic File format, respectively.


Symbol Editor file

Creates a new, untitled file in a Symbol Editor window.


Text Editor file

Creates a new, untitled file in a Text Editor window.


Waveform Editor file

Creates a new, untitled file in a Waveform Editor window. You can select the .scf or .wdf filename extension in the drop-down list box to create a file in the SCF or WDF format, respectively.


Open Command (all applications)
Open Command (File Menu)

Shortcuts

Opens a file, automatically starts the appropriate MAX+PLUS II editor, and makes the file the top of the current hierarchy.

Click Button 1 on any item in this dialog box for information on that item:

Use the built-in hierarchy traversal features in MAX+PLUS II to move between design files for the current hierarchy tree. To open a lower-level file in a hierarchy, open the top-level file and then use the Hierarchy Display window or Hierarchy Down (File menu) to open the lower-level files. If you choose Open or Retrieve (File menu) to open a lower-level file, it is considered to be the top of a different hierarchy, and resource, device, and probe assignments that you enter are saved only for that hierarchy, not for the project.

See also:

Guidelines for Working with Assignments

Opening a File

Retrieving a File


Open dialog box

Click Button 1 on any item in this dialog box for information on that item:


Delete File Command (all applications)
Delete File Command (File Menu)

Deletes one or more files.???

Click Button 1 on any item in this dialog box for information on that item:

See also:

Deleting a File


Delete File dialog box

Click Button 1 on any item in this dialog box for information on that item:


Hierarchy Commands (all applications)
Hierarchy Commands (File Menu)

Shortcuts

Hierarchy commands allow you to open or bring to the front other files in the current hierarchy.

Command:	Action:

Hierarchy Project Top	Opens the design file at the top of the project hierarchy.

Hierarchy Top	Opens the design file at the top of the current hierarchy. (Available only in the Graphic and Text Editors.)

Hierarchy Up	Opens the design file that is one hierarchy level higher than the current file if you are not already at the top of the hierarchy. (Available only in the Graphic, Text, and Waveform Editors.)

Hierarchy Down	Opens the design file that is one hierarchy level lower than the current file. (Available only in the Graphic and Text Editors.) Select the name or symbol that represents the file on the next lower hierarchy level and choose Hierarchy Down. If the name is part of a group, you are prompted to select a specific member of the group. You can also double-click Button 1 on a symbol in the Graphic Editor to perform this command. ???Specify Macrofunction dialog te_com_specify/te_bmp_specify

Use the built-in hierarchy traversal features in MAX+PLUS II to move between design files for the current hierarchy tree. To open a lower-level file in a hierarchy, open the top-level file and then use the Hierarchy Display window or Hierarchy Down to open the lower-level files. If you choose Open or Retrieve (File menu) to open a lower-level file, it is considered to be the top of a different hierarchy, and resource, device, and probe assignments that you enter are saved only for that hierarchy, not for the project.

MAX+PLUS II automatically starts the editor appropriate to the selected file. For example, if the file is a GDF, a Graphic Editor window is opened and the schematic is displayed.

MAX+PLUS II searches the directory of the top-level design file in the current hierarchy tree, the user libraries, and the subdirectories of the \maxplus2\max2lib directory for the lower-level design file.

Shortcuts:

Hierarchy Up	Ctrl+U

Hierarchy Down	Ctrl+D or double-click Button 1 on a megafunction or macrofunction symbol in the Graphic Editor

Hierarchy Project Top	Ctrl+T or

See also:

Guidelines for Working with Assignments

Navigating the Hierarchy


Exit MAX+PLUS II Command (all applications)
Exit MAX+PLUS II Command (File Menu)

Shortcuts

Closes all MAX+PLUS II windows and exits from MAX+PLUS II.

This command operates in the same way as the Application Control Menu’s Close command.

Exit MAX+PLUS II shuts down all windows and exits from MAX+PLUS II. If you have edited any files, you are asked whether you wish to save the changes. If MAX+PLUS II is running a background process, you are asked whether you wish to stop processing before the software shuts down.

You can use the Preferences command (Options menu) to specify whether or not MAX+PLUS II should confirm that you wish to exit when you choose Exit MAX+PLUS II.

See also:

Exiting from MAX+PLUS II

Setting MAX+PLUS II Preferences


User Libraries Command (all applications)
User Libraries Command (Options Menu)

Specifies a library that contains Symbol Files and design files for your own megafunctions and macrofunctions, as well as AHDL Include Files.

Click Button 1 on any item in this dialog box for information on that item:

When a project is compiled, the Compiler searches directories for the logic represented by a Symbol or Include File in the following order:

Project directory

User library directories

\maxplus2\max2inc and \maxplus2\max2lib directories and their subdirectories

If your project uses custom VHDL design libraries, use the Compiler’s VHDL Netlist Reader Settings command (Interfaces menu) to specify the design library names, as described in Compiling VHDL Design Files. Custom VHDL design libraries cannot be designated with the User Libraries command.

See also:

Specifying a User Library


Directory Name

Specifies the name of the library directory.

You can type an absolute or relative pathname in the Directory Name box or select an existing directory name in the Directories box to copy it to the Directory Name box.


Directories (User Libraries command)
Directories

Lists all available subdirectories of the current directory.

You can type a different absolute or relative pathname in the Directory Name box and choose OK or double-click Button 1 on a name in the Directories box to change the current directory.


Directory is; User Libraries command
Directory is

Displays the current directory. All subdirectories of the current directory are listed in the Directories box.

You can type a different absolute or relative pathname in the Directory Name box and choose OK or double-click Button 1 on a name in the Directories box to change the current directory.


Add (User Libraries command)
Add

Adds the library directory name specified in the Directory Name box to the list of directories in the Existing Directories box.


Delete (User Libraries command)
Delete

Deletes the selected library directory name from the Existing Directories box.


Existing Directories (prioritized)

Lists all existing library directories. During compilation, the Compiler searches for logic functions in these library directories in order from top to bottom.

When a directory name is selected in this box, you can choose Up or Down to change its order within the list.


Priority

Up	Moves the selected library directory name up in the Existing Directories box.

Down	Moves the selected library directory name down in the Existing Directories box.

During compilation, the Compiler searches for logic functions in the library directories in the Existing Directories box in order from top to bottom.


OK (User Libraries command)
OK

Saves all library directories listed in the Existing Directories box and closes the dialog box. Changes that have not been added to the Existing Directories box are not saved.


User Libraries dialog box

Click Button 1 on any item in this dialog box for information on that item:


Color Palette Command (all applications)
Color Palette Command (Options Menu)

Changes the display colors of items used in MAX+PLUS II.

Altera supplies default colors for items displayed in MAX+PLUS II application windows. You can customize the colors with the Color Palette command to suit your needs.

Click Button 1 on any item in this dialog box for information on that item:

If your choice of colors would make some objects invisible on screen (e.g., if you choose the same color for Text and Window Background), MAX+PLUS II automatically resets the colors to ensure some contrast. Therefore, the colors displayed may not be exactly the same as the colors you choose.

See also:

Changing Colors in MAX+PLUS II


Screen Elements

Lists the items visible in MAX+PLUS II application windows whose color can be changed. The current color for an item selected in the Screen Elements box is shown with a wide border under MAX+PLUS II Colors or Colors Set With Control Panel.

You can select any color from the options available under MAX+PLUS II Colors or Colors Set With Control Panel for an item selected in the Screen Elements box. On a PC, you can determine the colors available under Colors Set With Control Panel with the Windows Control Panel. On a workstation, you can determine these colors by editing the win.ini file created by MAX+PLUS II. Go to Appendix B: Additional Workstation Configuration Information in the MAX+PLUS II Getting Started manual for details.


Colors Set With Control Panel

Shows the colors for Window Background, Application Workspace, and Text in your current color scheme. On a PC, you can change these colors with the Windows Control Panel. On a workstation, you can determine these colors by editing the win.ini file created by MAX+PLUS II. Go to Appendix B: Additional Workstation Configuration Information in the MAX+PLUS II Getting Started manual for details.

You can select any color from the options available under Colors Set With Control Panel or MAX+PLUS II Colors for an item selected in the Screen Elements box. The current color for an item selected in the Screen Elements box is shown with a wide border.


MAX+PLUS II Colors

Shows the colors available for items in MAX+PLUS II application windows.

You can select any color from the options available under MAX+PLUS II Colors or Colors Set With Control Panel for an item selected in the Screen Elements box. The current color for an item selected in the Screen Elements box is shown with a wide border.


Preview

Lets you see color changes on the screen behind the Color Palette dialog box before actually implementing them.


Reset (Color Palette command)
Reset

Resets the colors to the default MAX+PLUS II color scheme. This color scheme ensures that all items are always visible, regardless of how you set up colors with the Windows ???Control Panel.


Color Palette dialog box

Click Button 1 on any item in this dialog box for information on that item:


Authorization Code Command (all applications)
Authorization Code Command (Options Menu)

Specifies an authorization code or a license file that enables MAX+PLUS II software features in a single- or multi-user installation of MAX+PLUS II.??? The Authorization Code dialog box also provides access to the Registration??? or Registration dialog box, which allow you to enter and fax software registration details to Altera.

Authorization Code allows you to enter a code that makes it possible to use MAX+PLUS II, and to change the authorization code when you receive a new product configuration. The authorization code is provided on the Maintenance Agreement Registration card for MAX+PLUS II, or by Altera. If no authorization code is entered, only the PLS-ES feature set is enabled.

If your software guard is labeled HPS, OS, or ES, you do not need to enter an authorization code. When these software guards are installed, the Software Guard ID field displays HPS, OS, or ES, respectively.

Click Button 1 on any item in this dialog box for information on that item:

For more information on network licensing, go to MAX+PLUS II Installation in the MAX+PLUS II Getting Started manual. For further assistance with authorization code and network licensing problems, contact Altera Applications.

See also:

Entering an Authorization Code

Exiting from MAX+PLUS II


Software Guard ID

Shows the identification number of the MAX+PLUS II software guard attached to the parallel printer port on your computer.


Expiration Date

Specifies the expiration date of your MAX+PLUS II software, if any.

You can enter a new authorization code in the Authorization Code box and choose Validate to update the expiration date.


Authorization Code

Specifies the 24-character authorization code for your copy of MAX+PLUS II software.

The authorization code is provided on the Maintenance Agreement Registration card for MAX+PLUS II, or by Altera. The code is case-sensitive, so you must type upper- and lowercase letters exactly as they appear in the code supplied by Altera.

After you type the authorization code, you can choose Validate to update the lists of features in the Enabled Features and Disabled Features boxes and the software expiration date (if any).


Authorization Code
Network License File

???


Disabled Features

Lists all MAX+PLUS II features that are currently disabled.

You can enter a new authorization code in the Authorization Code box and choose Validate to update the lists of features in the Enabled Features and Disabled Features boxes. If you have not installed all portions of MAX+PLUS II on your computer, you may need to use the Install program again to copy some features/applications onto your computer before they can be enabled.


Enabled Features

Lists all MAX+PLUS II features that are currently enabled.

You can enter a new authorization code in the Authorization Code box and choose Validate to update the lists of features in the Enabled Features and Disabled Features boxes. If you have not installed all portions of MAX+PLUS II on your computer, you may need to use the Install program again to copy some features/applications onto your computer before they can be enabled.


Validate

Checks the authorization code entered in the Authorization Code box. If the code is valid, the lists of features in the Enabled Features and Disabled Features boxes are updated to show the features that are available with the current authorization code, and the software expiration date (if any).

If you have not installed all portions of MAX+PLUS II on your computer, you may need to use the Install program again to copy some features/applications onto your computer before they can be enabled.


Register

???


Browse

???


Authorization Code dialog box

Click Button 1 on any item in this dialog box for information on that item:


MAX+PLUS II Registration Dialog Box (all applications)
MAX+PLUS II Registration Dialog Box (Options Menu)

Provides a quick way to enter MAX+PLUS II software registration information and allows you to print or fax the registration form to Altera.

You open the MAX+PLUS II Registration dialog box by choosing the Register button in the Authorization Code dialog box (Options menu).

MAX+PLUS II Registration allows you to enter a code that makes it possible to use MAX+PLUS II, and to change the authorization code when you receive a new product configuration. The authorization code is provided on the Maintenance Agreement Registration card for MAX+PLUS II, or by Altera. If no authorization code is entered, only the PLS-ES feature set is enabled.

Click Button 1 on any item in this dialog box for information on that item:

???For more information on network licensing, go to MAX+PLUS II Installation in the MAX+PLUS II Getting Started manual. For further assistance with authorization code and network licensing problems, contact Altera Applications.

See also:

Entering an Authorization Code

Exiting from MAX+PLUS II


MAX+PLUS II Registration Dialog Box
Registration ??? dialog box

Click Button 1 on any item in this dialog box for information on that item:


Help Menu Commands (all applications)
Help Menu Commands

Shortcuts

The Help menu commands provide access to the MAX+PLUS II Help system.

The following commands are available:

Command:	Action:

Search for Help on	Opens the Search dialog box, which contains a detailed on-line index for MAX+PLUS II Help. With this command, you can list and open all Help topics relevant to a keyword or phrase of interest. All Help topic titles are also listed by their names. For information on how to use this command, refer to Searching for a Help Topic.

MAX+PLUS II Table of Contents	Displays the top-level table of contents for Help, which organizes MAX+PLUS II information by applications and other topics, and shows the name and icon for each topic. When you choose a name or icon, a table of contents for that topic is displayed. You then select one of the topics for more detailed information. This command provides access to the same table of contents that is displayed when you choose the Contents button in the Help application.

<Application Name> Help

Table of Contents	Displays the table of contents for the current MAX+PLUS II application. You can select one of the topics for more detailed information.

Introduction	Provides an overview of the current MAX+PLUS II application and describes how to get started in Help.

Basic Tools	Describes items visible in the application window, input and output files, text file formats, etc. Each description also provides references to related topics.

Commands	Describes commands available in the current MAX+PLUS II application. Each description includes information on all dialog box options, when the command is available, and references to related topics.

Procedures	Describes step by step how to perform a specific task in the current MAX+PLUS II application, and references to related topics.

Golden Rules	Summarizes essential rules and guidelines for using the current MAX+PLUS II application, and references to related topics.

Shortcuts	Lists keyboard and mouse shortcuts for commands.

AHDL	Displays the table of contents for AHDL Help. You can select one of the topics for more detailed information.

VHDL	Displays the table of contents for VHDL Help. You can select one of the topics for more detailed information.

Megafunctions/LPM	Provides a description, function table, and Function Prototype of each megafunction supplied by Altera, including LPM functions.

Macrofunctions	Provides a description, function table, and Function Prototype of each macrofunction supplied by Altera.

Primitives	Provides a description, function table, and Function Prototype of each primitive supplied by Altera.

Devices & Adapters	Provides a descriptions of all Altera devices and programming adapters supported by the current version of MAX+PLUS II, including device selection guides and complete pin-out information.

Messages	Lists MAX+PLUS II error, information, and warning messages in alphabetical order and provides information on the possible cause(s) and recommended action(s).

Glossary	Defines terms used throughout MAX+PLUS II software and documentation.

READ.ME	Displays the read.me file provided with the current version of MAX+PLUS II software.

How to Use MAX+PLUS II Help	Describes how to get the most out of MAX+PLUS II Help. Information on how Help is organized, getting context-sensitive help, and Altera documentation conventions is included. This Help category is specifically written for MAX+PLUS II users--don’t miss it!

How to Use Help	Describes the basic mouse-clicking and keyboard steps for moving around in the Help application. Windows??? users can also refer to Windows Basics in the Microsoft Windows User’s Guide.

About MAX+PLUS II	Opens the About MAX+PLUS II dialog box, which gives the MAX+PLUS II version number, the current active application’s version number, and copyright information. Information about memory and system resource usage is also provided.

Regardless of how you enter MAX+PLUS II Help--whether via context-sensitive Help or a Help menu command--all other sections of Help are accessible to you. Refer to How to Use MAX+PLUS II Help for information on how to get the most out of MAX+PLUS II Help.

See also:

Getting Context-Sensitive Help

Understanding MAX+PLUS II Help Categories


About MAX+PLUS II dialog box


Preferences Command (all applications)
Preferences Command (Options Menu)

Specifies general preferences for your MAX+PLUS II setup, including whether to ask before closing MAX+PLUS II, whether to display the toolbar and status bar, and whether to automatically iconizing the Compiler and Simulator during project processing.

Click Button 1 on any item in this dialog box for information on that item:

???The toolbar is displayed below the menu bar in the MAX+PLUS II window. You can choose a toolbar button or select an option from a toolbar drop-down list box to enter commands or get context-sensitive help in the current MAX+PLUS II application.

???The status bar is displayed at the bottom of the MAX+PLUS II window. When you point to an item in the toolbar or highlight a menu command with the mouse or with keyboard commands, the status bar displays a brief description of the function of that item.

See also:

???Getting Context-Sensitive Help

???Setting MAX+PLUS II Preferences

Showing the Toolbar

Showing the Status Bar


Window Menu Commands

Shortcuts

The Window menu is available when multiple application and/or document windows are open in MAX+PLUS II.

Command:	Action:

New Window	Opens another window of the current file, allowing two different views of the same file. (Available only in the Graphic, Symbol, Text, and Waveform editors).

Tile Horizontally	Rearranges all active MAX+PLUS II application windows into non-overlapping windows arranged top-to-bottom on screen.

Tile Vertically	Rearranges all active MAX+PLUS II application windows into non-overlapping windows arranged left-to-right on screen.

Cascade	Rearranges all active windows so that they overlap with each title bar visible.

Arrange Icons	Aligns the application windows that have been iconized evenly across the bottom of the screen.

1, 2, 3 ... 9	Moves the specified window to the front of the desktop and makes it active.

More Windows	When more than nine windows are open, opens the Select Window dialog box that lists all open windows. You can select a file or application name to move the specified window to the front of the desktop and make it active.


Select Window dialog box


Print Setup Command
Print Setup Command (File Menu)

Selects a printing or plotting device.

Click Button 1 on any item in this dialog box for information on that item:

Any changes entered with this command apply to all Windows ???applications, not only to MAX+PLUS II.

Refer to the User’s Guide for your version of Microsoft Windows ??? for further information on Print Setup.

See also:

Print Command

Printing


Printer; Printer Setup dialog box
Printer

Specifies the printer to be used.

This box lists all printers set up during Windows ???installation. The current printer is selected as the default.


Setup; Printer Setup dialog box
Setup

Opens a dialog box that allows you to set options for the selected printer name shown in the Printer box. These options are printer-specific and are not documented here. The dialog box for many printer setups provide on-line help; try choosing the Help button (if available) or pressing F1. Otherwise, refer to the manual provided with your printer.


Printer Setup Dialog Box
Print Setup dialog box

Click Button 1 on any item in this dialog box for information on that item:


License Agreement Dialog Box

Shows the license agreement for MAX+PLUS II software.

The License Agreement dialog box is displayed when you start MAX+PLUS II for the first time after installing the software. You must read through the text in this dialog box before you can choose Yes and use MAX+PLUS II software. By using MAX+PLUS II software, you indicate your acceptance of the terms and conditions of this license agreement.

The text of the license agreement is repeated here for your convenience:

ALTERA PROGRAM LICENSE AGREEMENT

PLEASE REVIEW THE FOLLOWING TERMS AND CONDITIONS CAREFULLY BEFORE USING THE SOFTWARE. BY USING THIS SOFTWARE YOU INDICATE YOUR ACCEPTANCE OF SUCH TERMS AND CONDITIONS, WHICH CONSTITUTE THE LICENSE AGREEMENT BETWEEN YOU AND ALTERA CORPORATION ("ALTERA"). IN THE EVENT THAT YOU DO NOT AGREE WITH ANY OF THEM, YOU SHOULD PROMPTLY RETURN THE SOFTWARE UNUSED.

Program(s) as used in this Agreement is defined to mean: Whichever features of the software are enabled by the software protection mechanism corresponding to the configuration you have licensed. Any unenabled features are unlicensed and you agree not to use or access such features.

By this Agreement, ALTERA grants to you a non-exclusive license to the Programs (and any updates to Programs which you may acquire from ALTERA). The Programs (plus any unenabled features) are confidential and proprietary to ALTERA and its licensors, and ALTERA and its licensors retain all title, copyright, patent and other proprietary rights to the Programs (plus any unenabled features) and all copies thereof.

Pursuant to this Agreement, you may: (a) use the Programs on a single computer (or on networked workstations if you have purchased a floating node license); (b) make one copy of the Programs in any computer-readable or printed form for back-up or archival purposes only in support of your permitted use of the Programs and pursuant to the following paragraph (certain Programs, however, may include mechanisms to limit or inhibit copying); (c) merge or combine the Programs with another program for your permitted use of the Programs and pursuant to the following paragraph; and (d) transfer the Programs and license to another party if the other party agrees to accept the terms and conditions of this Agreement and pursuant to the following paragraph.

Any copy or portion of these Programs merged into another program(s) will continue to be subject to the terms and conditions of this Agreement. If you transfer the Programs, you must at the same time either transfer all copies, whether in printed or computer-readable form, to the same party or destroy any copies not transferred, including all portions of the Programs contained or merged into another program, and certify same to ALTERA. You must also reproduce and include the copyright and restricted rights notices on any copy, or portion merged or combined with another program(s).

Notwithstanding the restrictions on transfer which appear above, you may also copy the Programs onto another computer (or access it through networked workstations) for use by another person or persons within your company only; provided that (1) all such users agree to accept the terms and conditions of this Agreement, and (2) only the ES feature set of the Programs may be used by obtaining from ALTERA a separate user authorization code, which is available without any additional license fee. You and any subsequent users acknowledge that maintenance agreements and product migration capabilities are not available for the stand-alone ES feature set.

YOU MAY NOT USE, COPY, MODIFY, OR TRANSFER THE PROGRAMS, OR ANY COPY, OR MERGED OR COMBINED PORTION, IN WHOLE OR IN PART, EXCEPT AS EXPRESSLY PROVIDED FOR IN THIS AGREEMENT. IF YOU TRANSFER POSSESSION OF ANY COPY, OR MERGED OR COMBINED PORTION OF THE PROGRAMS TO ANOTHER PARTY EXCEPT AS EXPRESSLY PROVIDED HEREIN, YOUR LICENSE IS AUTOMATICALLY TERMINATED. YOU MAY NOT DECOMPILE, DISASSEMBLE OR OTHERWISE ATTEMPT TO ACCESS THE SOURCE CODE OF THE PROGRAMS; PROVIDED, HOWEVER, THAT IF YOU ARE LOCATED IN A MEMBER NATION OF THE EUROPEAN COMMUNITY, YOU MAY PERFORM LIMITED REVERSE-ENGINEERING, BUT ONLY AFTER NOTICE TO ALTERA AND ONLY TO THE EXTENT REQUIRED BY THE EC SOFTWARE DIRECTIVE.

Term

The license is effective until terminated. You may terminate it at any time by destroying the Programs together with all copies, modifications, and merged portions in any form. It will also terminate upon conditions set forth elsewhere in this Agreement or if you fail to comply with any term or condition of this Agreement. You agree upon such termination to destroy the Programs together with all copies, and merged or combined portions in any form and certify same to ALTERA.

Limited Warranty and Remedies

ALTERA warrants that the Programs will perform substantially in accordance with ALTERA's current Program documentation for a period of ninety (90) days from the date of delivery to you, as evidenced by a copy of your receipt. ALTERA warrants the diskette(s) on which Programs are furnished to be free from defects in materials and workmanship under normal use for a period of ninety (90) days from the date of delivery to you, as evidenced by a copy of your receipt. This warranty is limited to you and is not transferable.

During the 90-day warranty period, (1) ALTERA will replace any Program or diskette not meeting the foregoing warranty and which is returned to ALTERA or an Authorized ALTERA Distributor ("Authorized Distributor") with a copy of your receipt; or (2) if ALTERA or the Authorized Distributor is unable to deliver a replacement Program which performs substantially in accordance with current Program documentation or a diskette which is free of defects in materials or workmanship, you may terminate this Agreement by returning the Programs, and your money will be refunded. Any replacement Programs or diskettes will be warranted for the remainder of the original warranty period or thirty (30) days, whichever is longer.

THE FOREGOING WARRANTY DOES NOT EXTEND TO ANY DISKETTE WHICH HAS BEEN DAMAGED AS A RESULT OF ACCIDENT, MISUSE, ABUSE, OR AS A RESULT OF SERVICE OR MODIFICATION BY ANYONE OTHER THAN ALTERA OR AN AUTHORIZED DISTRIBUTOR.

EXCEPT AS EXPRESSLY SET FORTH ABOVE, NO OTHER WARRANTIES, EITHER EXPRESS OR IMPLIED, ARE MADE WITH RESPECT TO THESE PROGRAMS, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, AND ALTERA EXPRESSLY DISCLAIMS ALL WARRANTIES NOT STATED HEREIN. YOU ASSUME THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAMS. SHOULD THE PROGRAMS PROVE DEFECTIVE, YOU--AND NOT ALTERA OR AN AUTHORIZED DISTRIBUTOR--ASSUME THE ENTIRE COST OF NECESSARY SERVICING, REPAIR, OR CORRECTION.

Some states do not allow the exclusion of implied warranties, so the above exclusion may not apply to you.

ALTERA DOES NOT WARRANT THAT THE FUNCTIONS CONTAINED IN THE PROGRAMS WILL MEET YOUR REQUIREMENTS, OR THAT THE OPERATION OF THE PROGRAMS WILL BE UNINTERRUPTED OR ERROR-FREE. YOU ALSO ASSUME RESPONSIBILITY FOR THE SELECTION OF THE PROGRAMS TO ACHIEVE YOUR INTENDED RESULTS AND FOR THE INSTALLATION, USE, AND RESULTS OBTAINED FROM THE PROGRAMS.

YOUR SOLE REMEDIES AND ALTERA CORPORATION'S ENTIRE LIABILITY ARE AS SET FORTH ABOVE. IN NO EVENT WILL ALTERA BE LIABLE TO YOU OR ANY OTHER PERSON FOR ANY DAMAGES, INCLUDING ANY INCIDENTAL OR CONSEQUENTIAL DAMAGES, EXPENSES, LOST PROFITS, LOST SAVINGS, OR OTHER DAMAGES ARISING OUT OF THE USE OF OR INABILITY TO USE SUCH PROGRAMS.

Some states do not allow the limitation or exclusion of incidental or consequential damages, so the above limitations or exclusions may not apply to you.

THIS WARRANTY GIVES YOU SPECIFIC LEGAL RIGHTS, AND YOU MAY ALSO HAVE OTHER RIGHTS WHICH VARY FROM STATE TO STATE.

To the extent that the Programs are derived from third-party software, no such third party hereby warrants the Programs, assumes any liability regarding use of the Programs or undertakes to furnish you any support or information relating to the Programs.

General

Under no circumstances shall ALTERA be liable to any party in an amount beyond the purchase price of the products covered hereby.

You may not sublicense, assign, or transfer the license or the Programs, or disclose the Programs, except as expressly provided in this Agreement. Any attempt otherwise to sublicense, assign, or transfer any of the rights, duties, or obligations hereunder is void.

You shall not export the Programs or the direct product thereof without first obtaining the appropriate U.S. or other governmental licenses and approvals.

This Agreement is entered into for the benefit of ALTERA and its licensors and all rights granted to you and all obligations owed to ALTERA shall be enforceable by ALTERA and its licensors.

If you have any questions concerning this Agreement, including software maintenance or warranty service, you should contact ALTERA Corporation, 2610 Orchard Parkway, San Jose, CA 95134-2020.

This Agreement will be governed by the laws of the State of California.

The prevailing party in any legal action or arbitration arising out of this Agreement shall be entitled to reimbursement for its expenses, including court costs and reasonable attorneys' fees, in addition to any other rights and remedies such party may have.

YOU ACKNOWLEDGE THAT YOU HAVE READ THIS AGREEMENT, UNDERSTAND IT, AND AGREE TO BE BOUND BY ITS TERMS AND CONDITIONS; YOU FURTHER AGREE THAT IT IS THE COMPLETE AND EXCLUSIVE STATEMENT OF THE AGREEMENT BETWEEN US WHICH SUPERSEDES ANY PROPOSAL OR PRIOR AGREEMENT, ORAL OR WRITTEN, AND ANY OTHER COMMUNICATIONS BETWEEN US RELATING TO THE SUBJECT MATTER OF THIS AGREEMENT.

U.S. Government Restricted Rights

The Programs and documentation are provided with RESTRICTED RIGHTS. Use, duplication, or disclosure by the Government is subject to restrictions as set forth in subparagraph (c)(1)(ii) of The Rights in Technical Data and Computer Software clause at DFARS 252.227-7013 or subparagraphs (c)(1) and (2) of Commercial Computer Software--Restricted Rights at 48 CFR 52.227-19, as applicable. Contractor/manufacturer is ALTERA Corporation, 2610 Orchard Parkway, San Jose, CA 95134-2020 and its licensors.


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Common dialog box popups start here:

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Radix is;
Radix is

Displays the binary (BIN), decimal (DEC), hexadecimal (HEX), or octal (OCT) radix used to interpret and display the logic level of the group.


Directory is; static text
Directory is

Displays the current directory. Files in the current directory are listed in the Files box.

You can type a different absolute or relative pathname in the File Name box and choose OK or double-click Button 1 on a name in the Directories box to change the current directory.


Project Name is; static text
Project Name is

Displays the name of the current project.

You can change the current project with Project Name or Project Set Project to Current File (File menu).


Node Name; static text
Node Name is

Displays the hierarchical node name of the selected node or symbol. If you selected more than one node or symbol, the text MULTIPLE ITEMS is displayed.


Directories; list box
Directories

Lists all available subdirectories of the current directory.

You can type a different absolute or relative pathname in the File Name box and choose OK or double-click Button 1 on a name in the Directories box to change the current directory.


Drives; drop-down
Drives

Lists all available disk drives.

You can type a different absolute or relative pathname in the File Name box and choose OK or select a name in the Drives drop-down list box to change the current drive.


Hierarchy Path is; static text
Hierarchy Path is

Displays the hierarchical node name of the current design file. This hierarchy path is assumed when you enter a node or symbol name in the dialog box, i.e., the text you type is appended to the hierarchy path. You can also enter an absolute path or relative path to specify a different hierarchy path.

When the current file is the top-level design file in the hierarchy tree, the hierarchy path is shown as "|".


OK; standard first level dialog box
OK

Saves all changes and closes the dialog box.


Cancel; standard first level dialog box
Cancel

Closes the dialog box without saving any changes.


Printer is; Print Command (File Menu)
Printer is

Displays the current printer.

You can change the current printer with Printer Setup (File menu).


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There are 3 pairs of File Name/File popups in this file.

The following pair of File Name/File popups is for creating/saving files

--------------------END OF NON-TRANSLATED TEXT-----------------------------------------------


File Name; for saving/creating
File Name

Specifies the name of the file to be saved. The existing name of the file, if any, is displayed as the default.

You can type a filename with up to 32 name characters in the File Name box or select an existing filename in the Files box to copy it to the File Name box. You do not need to enter a filename extension: the extension shown in the Automatic Extension box is automatically appended to the filename. If you type the name of a directory that does not exist, MAX+PLUS II offers to create it for you.

You can also type a text string that includes wildcard characters in the File Name box and choose OK to update the contents of the Files box with the filenames that match the text string.


Files; for saving/creating
Files

Lists all files in the current directory that match the text string in the File Name box and the filename extension selected in the Automatic Extension box.

Selecting a filename in the Files box copies it to the File Name box. You can also type a text string that includes wildcard characters in the File Name box and/or select a different filename extension (if available) in the Automatic Extension box, and then choose OK to update the contents of the Files box with the filenames that match the new text string and extension.


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The following pair of File Name/File popups is for opening/selecting files

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File Name; for opening/selecting files
File Name

Specifies the name of the file.

You can type a filename in the File Name box or select a name in the Files box to copy it to the File Name box. You can also type a text string that contains wildcard characters in the File Name box and/or select a different filename extension (if available) in the Automatic Extension box, and then choose OK to update the contents of the Files box with the filenames that match the new text string and extension.


Files; for opening/selecting files
Files

Lists all files in the current directory that match the text string in the File Name box.

Selecting a filename in the Files box copies it to the File Name box. You can also type a text string that includes wildcard characters in the File Name box and/or select a different filename extension (if available) in the Automatic Extension box, and then choose OK to update the contents of the Files box with the filenames of the files that match the new text string and extension.


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The following pair of File Name/File popups is for the Open and Retrieve commands

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File Name; Open & Retrieve commands
File Name

Specifies the name of the file.

You can type a filename in the File Name box or select a name in the Files box to copy it to the File Name box. You can also type a text string that contains wildcard characters in the File Name box and/or select a different file type and filename extension in the Show in Files List box, and then choose OK to update the contents of the Files box with the filenames that match the new text string and extension.


Files; Open & Retrieve commands
Files

Lists all files in the current directory that match the text string in the File Name box and the filename extension that is selected in the Show in Files List box.

Selecting a filename in the Files box copies it to the File Name box. You can also type a text string that includes wildcard characters in the File Name box and/or select a different file type and filename extension in the Show in Files List box, and then choose OK to update the contents of the Files box with the filenames of the files that match the new text string and extension.


Automatic Extension; File-type dialog boxes with Automatic Extension box
Automatic Extension

Specifies the filename extension that is automatically appended to the filename specified in the File Name box. You can override the automatic extension by specifying a different extension in the File Name box.

In some applications, you can also select a different automatic extension in the Automatic Extension box.


Show in Files List; radio buttons in Open & Retrieve commands
Show in Files List

Specifies the file type and associated filename extension of filenames displayed in the Files box. The following options are available:

Option:	Action:

Graphic Editor files	Displays all Graphic Editor files that have the specified extension. The default extension is .gdf or the extension of the last file opened. You can select a different extension from the drop-down list box.

Text Editor files	Displays all Text Editor files that have the specified extension. The default extension is .tdf or the extension of the last file opened. You can select a different extension from the drop-down list box.

Waveform Editor files	Displays all Waveform Editor files that have the specified extension. The default extension is .scf or the extension of the last file opened. You can select a different extension from the drop-down list box.

Symbol Editor files (*.sym)	Displays all Symbol Editor files (with the extension .sym).

All files (*.*)	Displays all files.


Device Family; used only in PGM Select Device now
Device Family

Displays available device families. Select a device family to display the names of devices in that family in the Available Devices box.


Available Devices; used only in PGM Select Device now
Available Devices

Lists all Altera devices in the device family that is currently selected in the Device Family box.


Search for; Find Text and Search & Replace dialog boxes
Search For

Specifies the text to be found. You can enter up to 256 characters, including optional wildcard characters, in the search text.

If text is selected in the file or was entered in another editor’s Find Text or Search & Replace dialog box, it appears as the default search text.


Replace with; Find Text and Search & Replace dialog boxes
Replace With

Specifies the replacement text. Enter up to 256 characters.


Whole Word; Find Text and Search & Replace dialog boxes
Whole Word

Finds whole words only, not word fragments embedded within other words (e.g., DESIGN embedded in SUBDESIGN is not found).


Confirm; Find Text and Search & Replace dialog boxes
Confirm Each Change

Specifies whether MAX+PLUS II will ask before replacing each occurrence of the search text. Turning this option off allows MAX+PLUS II to replace all occurrences of the search text automatically.


Pause; Find Text and Search & Replace dialog boxes
Pause at End

Specifies whether MAX+PLUS II will pause when it reaches the end or beginning of the file (depending on whether you select Down or Up as the Direction) and ask whether you wish to continue the search.


Direction (Down & Up); Find Text and Search & Replace dialog boxes
Direction

Down	Searches from the current insertion point to the end of the file, jumps to the beginning of the file, and searches down to the insertion point.

Up	Searches from the current insertion point to the beginning of the file, jumps to the end of the file, and searches up to the insertion point.


Yes; second level dialog box for Search & Replace
Yes

Replaces the currently selected search text, then continues the search.


No; second level dialog box for Search & Replace
No

Leaves the currently selected search text unchanged, but continues the search.


Cancel; second level dialog box for Search & Replace
Cancel

Ends the search.


Copies; second level dialog box for Search & Replace
Copies

Specifies the number of copies to print. Multiple copies are collated.


Print Page Headers; second level dialog box for Search & Replace
Print Page Headers

Prints the filename, date, page count, and project name at the top of each page.


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Template panels -- not used in Help:

-------

 OK

Temporarily saves changes and closes the dialog box. You are returned to the <1st-level db name> dialog box. Changes made with the <2nd-level db name> dialog box are saved permanently when you choose OK in the <1st-level db name> dialog box.

-------

 Cancel

Closes the dialog box without saving any changes and returns you to the <1st-level db name> dialog box.

-------

 Existing <name>

Lists all existing <text> [for the current <text>].

Wording for specific commands:

Device:

Lists all existing device assignments for the current hierarchy tree.

Breakpoint:

Lists all existing breakpoints and breakpoint conditions for the current project.

Enable New Device Version:

Lists all existing passwords for the current device.

User Libraries:

Lists all existing user library directories. <add more info about priority>

-------

 Add

Adds the <text> specified in the <name> box to the Existing <name> box.

Wording for specific commands:

Breakpoint:

Assigns the breakpoint conditions listed in the Conditions box to the current Breakpoint Name. The new breakpoint and its conditions list is added to the Existing Breakpoints box.

User Libraries:

Adds the directory specified in the Directory Name box to the Existing Directories box.

Enable New Device Version:

Adds the password specified in the Password box to the Existing Passwords box.

-------

Delete

Deletes the selected <text> in the Existing <name> box.

Wording for specific commands:

Device:

Deletes the selected device assignment in the Existing Assignments box.

Breakpoint:

Deletes the selected breakpoint in the Existing Breakpoints box.

User Libraries:

Deletes the selected directory in the Existing Directories box.

Enter Assignments:

Deletes all probe and/or resource assignments for the selected node in the Existing Assignments box.

Enable New Device Version:

Deletes the selected password in the Existing Passwords box.

-------

Change

Changes the <text> for the current <name> to the <text> in the <name> box. The updated <text> is/are listed in the Existing <name> box.

Wording for specific commands:

Device:

Changes the device assignment for the current Chip Name to the device selected in the Devices box. The updated device assignment is listed in the Existing Assignments box.

Breakpoint:

Changes the breakpoint conditions for the current Breakpoint Name to include all conditions listed in the Conditions box. The updated breakpoint conditions are listed in the Existing Breakpoints box.

Enter Assignments:

Changes the probe and/or resource assignment(s) for the current Node Name to the resource(s) specified in the Probe, Pin/Logic Cell/Chip, Clique, Logic Options, and/or Timing boxes. The updated probe and/or resource assignment(s) are listed in the Existing Assignments box.

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Graphic & Symbol Editor Basic Tools
Basic Tools

Grid & Guidelines

Grid

Guidelines

Input & Output Files

Assignment & Configuration File (.acf)

ACF Format

Graphic Design File (.gdf)

Include File (.inc)

OrCAD Library File (.lib)

OrCAD Schematic File (.sch)

Symbol File (.sym)

Macrofunctions

Unused Inputs to Primitives & Macrofunctions

MAX+PLUS II Initialization & System Files

maxplus2.idx File

maxplus2.ini File

Mouse Behavior

Nodes, Names & Buses

Nodes

Pin & Node Names

Buses

Bus Names

Bus-to-Macrofunction Connections

Parameters

Primitives

Primitive Arrays

Primitive/Port Interconnections

Unused Inputs to Primitives & Macrofunctions

Parameters, Probe, Resource & Device Assignments

Parameters

Clique Assignments

Device Assignments

Logic Option Assignments

Pin, Location & Chip Assignments

Probe Assignments

Timing Assignments

Status Bar & Toolbar

Status Bar

Toolbar

Palette Tools

Selection Tool

Text Tool

Orthogonal Line Tool

Diagonal Line Tool

Arc Tool

Circle Tool

Symbol Elements

Pin Default Values

Pinstubs & Pinstub Names

Symbol Border

Symbol ID Number

Symbol Name

Text


Grid (Symbol Editor)
Grid

A series of invisible, non-printing horizontal and vertical lines that allow you to precisely enter and position objects in a Symbol File.

You can turn the grid on or off by choosing Snap to Grid (Options menu). When Snap to Grid is on, objects that you enter or move are "magnetically" pulled to the nearest grid line. The grid lines are permanently set to one grid unit horizontally and vertically.

When Snap to Grid is off, the grid has no effect on the objects you enter or move. Turning the grid on or off has no effect on objects already in your file.

Although the grid is not visible, Guideline Spacing and Show Guidelines (Options menu) set and display guidelines that provide a visual reference to the grid.

See also:

Changing the Guideline Spacing

Showing Guidelines

Snapping to the Grid


Guidelines (Graphic & Symbol Editors)
Guidelines

Dotted horizontal and vertical lines that provide a visual reference for entering, moving, and editing objects in a Graphic Editor file. Show me

Guideline Spacing (Options menu) lets you set the horizontal (X) and vertical (Y) spacings from 1 to 999 grid units.

The horizontal and vertical positions (coordinates) of the guidelines are displayed in grid units along the top and left edges of the drawing.

Show Guidelines (Options menu) displays or hides the guidelines. You can print a file with or without guidelines by turning Show Guidelines on or off before printing the file.

See also:

Changing the Guideline Spacing

Printing a File

Showing Guidelines


Mouse Behavior (Graphic & Symbol Editors)
Mouse Behavior

Use a two- or three-button mouse for the Graphic and Symbol Editors.

Button 1 corresponds to the left mouse button. Button 2 corresponds to the right button on a two-button mouse or the middle and right buttons on a three-button mouse.

You can use Button 1 to:

Choose a command, palette tool, and dialog box options and buttons.

Select, move, and copy objects.

Enter a symbol or pinstub. Double-click Button 1 in a blank space to open the Enter Symbol dialog box in the Graphic Editor or the Enter Pinstub dialog box in the Symbol Editor. Double-clicking Button 1 on an existing pinstub "x" also allows you to edit the pinstub.

Define an insertion point for pasting cut or copied objects. Click Button 1 in a blank space to define an insertion point.

Open a lower-level macrofunction in the current hierarchy. Double-click Button 1 on a macrofunction to open the design file that it represents.

Assign a primitive to a pin, logic cell, and/or chip. Double-click Button 1 on a primitive to open the Pin/Location/Chip dialog box.

Edit a pin, logic cell, chip, clique, probe, logic option, or timing assignment. Double-click Button 1 on an existing assignment to open the Pin/Location/Chip, Clique, Probe, Logic Options, or Timing Requirements dialog box .

Define an insertion point for entering a node or bus name. Click Button 1 on a line to define an insertion point.

Highlight a network of lines that are graphically connected. Double-click Button 1 on a line.

Select and edit text in a dialog box.

Draw a line, arc, or circle.

Enter a connection dot.

Enter or edit a comment. Click Button 1 in blank space to define an insertion point for text entry; click Button 1 to select a comment.

Edit the text of a pin name or pin default value. Click Button 1 in the text to define an insertion point for text entry; click Button 1 to select the text.

You can use Button 2 to:

Pop up a context-sensitive menu containing commands that can operate on the current selection. If no other item is selected and you click button two on an object, it also selects the item before popping up the context-sensitive menu.

Redefine the direction of a tangent line while drawing an arc.

See also:

Assigning a Clique

Assigning a Pin, Location, or Chip

Assigning an Individual Logic Option or Synthesis Style

Changing the Pinstub Name & I/O Type

Copying, Cutting & Pasting an Object

Copying, Cutting & Pasting Text

Drawing a Circle

Drawing a Line

Drawing an Arc

Entering a Connection Dot

Entering & Naming a Pinstub

Entering a Symbol

Entering a Text Block (Comment)

Naming a Node or Bus

Navigating the Hierarchy

Selecting an Object

Selecting Text


Nodes (Graphic Editor)
Nodes

Lines that represent wires in a circuit, which carry a signal between symbols in a GDF or OrCAD Schematic File. Show me

You can create a node by drawing a line with any line style except the bus style.

Although the Compiler interprets all line styles as logical connections, Altera recommends using the first style from the Line Style submenu (Options menu) for drawing nodes.

You can name nodes as described in the Naming a Node or Bus procedure. You can also change a comment into a node name by dragging it onto the node line and vice versa.

If you do not explicitly name a node, it has a default hierarchical node name.

When you enter a node in a Graphic Editor file, you must follow these rules:

When you connect a node to a symbol pinstub, you must draw the line right up to or over the stub so that no gap is left.

You must enter a connection dot to create a legal connection where two lines cross over or meet at a T intersection. Show me

A node name is required to connect a node to a bus, or if you wish to connect nodes by name only.

Lines that are not connected to symbols, nodes, or buses can be used freely in a Graphic Editor file; they are ignored when the project is compiled. However, nodes can be logically connected by name only; they need not be physically connected. Nodes are connected when their names are identical. Example

See also:

Drawing a Line

Entering a Connection Dot

Naming a Node or Bus

Recommended reading:

AB92 (Simulating Internal Nodes with MAX+PLUS II Software)


Pin & Node Names (Graphic Editor)
Pin & Node Names

Names that identify a pin or node.

A pin name is enclosed within a pin primitive symbol; a node name is a text block that is associated with a node line (wire). Selecting a node line also selects a name that is associated with the node. You can change a comment into a node name by dragging it onto a node line and vice versa.

When you enter a pin or node name in a Graphic Editor File, you must follow these rules:

It can contain up to 32 name characters. Example

It may not contain blank spaces. Leading or trailing spaces are ignored.

It must be unique, i.e., no two pins may have the same name in the same design file at the same hierarchy level.

Any node that is connected to a bus line must be named. Example

Two-dimensional node names must be expressed in the form: <name>[<width range>][<size range>].

1.	If you do not name a node, it has a default hierarchical node name.

2.	Assigning a single-range bus name to a pin creates an array of pins.

When you connect named pins and nodes to each other, you must follow these rules unless you use WIRE primitives to rename nodes:

A node connected to an input pin must have the same name as the input pin.

A node that feeds more than one output pin cannot be named.

A node that has one input pin as its source and one output pin as its destination cannot be named.

The WIRE primitive can be used to rename any node. Example

Nodes can be logically connected by name only; they need not be physically connected. Nodes are connected when their names are identical. Example

You can quickly locate a node or pin name in the current Graphic Editor file with Find Text or Find Node in Design File (Utilities menu). You can find a node or pin name in the floorplan for the project with Find Node in Floorplan (Utilities menu).

Compiler-generated pin names that contain the tilde (~) character may appear in the Fit File for a project. The tilde character is reserved for Compiler-generated names only; you cannot use it in your own pin, node, and group (bus) names.

See also:

Bus Names

Changing the Pin Name or Default Value

Hierarchical Node & Symbol Names

Naming a Node or Bus

Recommended reading:

AB92 (Simulating Internal Nodes with MAX+PLUS II Software)


Example: Renaming nodes with the WIRE primitive
Renaming nodes with the WIRE primitive


Example: pin and node names
Sample pin and node names

The following are examples of legal pin and node names (case is not significant):

A

a1 (same as A1)

nodea (same as NODEA)

Node123a

Node/123A

node-123A

123_ABC

node[1]

node[2][1]


Buses (Graphic Editor)
Buses

Wide lines that represent a logically related group of nodes. Show me

A bus contains from 1 to 256 individual nodes (or bits). You can create a bus by drawing a line with the bus line style.

You can name buses as described in the Naming a Node or Bus procedure. You can also change a comment into a bus name by dragging it onto the bus line. A bus name is required if the bus must connect to individual nodes, to create a primitive array, and to connect buses by name only.

If you do not explicitly name a bus, its width and default hierarchical bus name are determined by the name of the pin, primitive, or macrofunction pinstub to which it is attached.

When you enter a bus in a GDF or OrCAD Schematic File, you must follow these rules:

When you connect a bus to a symbol pinstub, you must draw the line right up to or over the pinstub so that no gap is left.

You must enter a connection dot to create a legal connection where two lines cross over or meet at a T intersection.

You must follow the guidelines for bus names and bus-to-macrofunction connections.

See also:

Drawing a Line

Entering a Connection Dot

Groups (AHDL)

Macrofunctions

Naming a Node or Bus

Ripping & Merging a Bus

Recommended reading:

AB82 (Emulating Internal Buses in Classic, MAX & STG EPLDs)

AB84 (DMA Controller with the EPM5064 MAX EPLD)

AB86 (Designing & Simulating Bidirectional Buses with MAX+PLUS II Software)


Bus Names (Graphic Editor)
Bus Names

The name of a bus or (group) of up to 256 nodes. A bus name can have one of two forms:

Single-range bus name	A single-range bus name consists of a bus identifier, followed by an optional bus width in brackets [ ]. The start and end of the number range are separated by two periods. Each number in the sequence represents an individual node (or "bus bit"). The bus identifier can contain up to 32 name characters. The bus width is a string that defines the number of bits (i.e., nodes) in a bus and uses the form [<MSB>..<LSB>]. The name of a single node within the bus can be specified with the identifier followed by the bit number, either with or without brackets. A two-dimensional single-range bus name consists of a bus identifier followed by a bus width in brackets and a bus size in brackets. Bus widths and sizes can each contain a maximum of 256 bits. Example.

Sequential bus name	A sequential bus name consists of a series of node names and/or more single-range bus names, separated by commas (,). The first node or bus bit in the series is the MSB, the last node in the series is the LSB. Example. You may involve two-dimensional buses and standard buses in the same sequence.

When you enter a bus name, you must follow these guidelines and rules:

A bus bit within a single-range bus name can contain up to three digits. You can use leading zeros to define a bus width or a bus size. Bus widths and sizes use the fewest number of characters necessary to represent their values. Example

If two single-range bus names have identical bus identifiers, MSB, LSB, and contain the same bits, both names represent the same bus, regardless of the bus name notation used. Example

A bus name can appear more than once on a bus line.

Since buses are interpreted as a sequence of individual nodes, the order of bus bits is important. Example

A bus is connected to a node by name only. Any node line that is connected to a bus line must be named. Example

Go to Legal Bus Names and Illegal Bus Names for additional bus name examples

You must name each bus, except in the following cases where bus names are optional. For documentation purposes, however, you may prefer to name all buses.

When the bus is directly connected to a pin with a single-range bus name or connects two bus macrofunctions. Example

When the bus wire is connected to a primitive array, if at least one segment of the network that contains this bus wire is explicitly named before any connection dots or if the network is connected to a pin with a single-range bus name. However, a bus that feeds multiple primitives must have a name inserted. Example 1 Example 2

Compiler-generated pin names that contain the tilde (~) character may appear in the Fit File for a project. The tilde character is reserved for Compiler-generated names only, you cannot use it in your own pin, node, and group (bus) names.

See also:

Bus-to-Macrofunction Connections

Groups (AHDL)

Naming a Node or Bus

Pin & Node Names

Ripping & Merging a Bus


Example: decimal bus name
Sample single-range bus names

The name DOUT[6..4] defines a bus with the following characteristics:

Bus identifier:	DOUT

Bus width:	[6..4], which defines 3 bits

Names of nodes (bits):	DOUT6, DOUT5, and DOUT4 or DOUT[6], DOUT[5], and DOUT[4]

MSB:	DOUT6 or DOUT[6]

LSB:	DOUT4 or DOUT[4]

The name DOUT[6..4][6..4] defines a two-dimensional bus with the following characteristics:

Bus identifier:	DOUT

Bus width:	[6..4]

Bus size:	[6..4], which, together with the bus width, defines 9 bits

Names of nodes (bits):	DOUT6_6, DOUT6_5, DOUT6_4, DOUT5_6, DOUT5_5, DOUT5_4, DOUT4_6, DOUT4_5, and DOUT4_4

MSB:	DOUT6_6

LSB:	DOUT4_4


Example: sequential bus name
Sample sequential bus names

The following examples show valid sequential bus names:

A, B, C

DOUT[6], DOUT[5], DOUT[4] (can also be represented as DOUT[6..4])

DOUT6, DOUT5, DOUT4

A[31..0], DOUT[6..4]

A[31..0], B, DOUT[6..4], C

A[31..0][2..0], DOUT[6..4][6..4]

The bus name DOUT6, DOUT5, DOUT4 represents a bus that contains three bits. The MSB is DOUT6 and the LSB is DOUT4.

The bus name A[31..0],DOUT[6..4] represents a bus that contains 35 bits. The MSB is A31 (or A[31]) and the LSB is DOUT4 or (DOUT[4]).

The bus name A[31..0][2..0],DOUT[6..4][6..4] represents a bus that contains 105 bits. The MSB is A31_2 and the LSB is DOUT4_4


Example: leading zeros in a bus name
Leading zeros in a bus name

Bus name Z[15..00] represents the nodes Z15, Z14,...Z00, which can also be written as Z[15], Z[14], ... Z[00].

The first zero in Z00 is a leading zero. The bus name can also be expressed as Z[15..0], where the LSB is Z0.

Two-dimensional bus name Z[15..00][11..00] represents the nodes Z15_11, Z15_10,...Z00_00.

The first zeros in Z00_00 are leading zeros. The two-dimensional bus name can also be expressed as Z[15..0][11..0], where the LSB is Z0_0.


Example: identical bus names
Identical bus names

Both A[7..0] and A[7..3],A[2..0] represent the same bus. The MSB and LSB are A7 and A0, respectively.

However, A[0..7] is not identical. The MSB is A0 and the LSB is A7.

Both A[7..0][2..0] and A[7..3][2..0],A[2..0][2..0] represent the same two-dimensional bus. The MSB and LSB are A7_2 and A0_0, respectively.

However, A[0..7][2..0] is not identical. The MSB is A0_2 and the LSB is A7_0.


Illegal Bus Names (Graphic Editor)
Illegal Bus Names

The following are examples of illegal bus names:

Bus Name	Problem:

A[1..0000]	The bus bit 0000 has more than three digits.

A*[31..0]	The asterisk (*) is not a valid name character.

B[256..0]	The bus width is greater than 256 bits.

C[ ]	In the Graphic Editor, empty brackets ([ ]) are not allowed.

See also:

Groups (AHDL)

Legal Bus Names

Naming a Node or Bus


Legal Bus Names (Graphic Editor)
Legal Bus Names

The following are examples of legal bus names:

Bus Name:	Defines:

A[31..00]	The name defines a 32-bit bus whose identifier is A. The individual bits of this bus are A31, A30, A29 ... A00 (or A[31], A[30], A[29] ... A[00]). The MSB in this example is A31 (or A[31]), and the LSB is A00 (or A[00]).

DOUT[6..4]	The name defines a bus that has a bus identifier DOUT and contains three bits: DOUT6, DOUT5, and DOUT4 (or DOUT[6], DOUT[5], and DOUT[4]). The MSB is DOUT6, and the LSB is DOUT4.

DOUT[6..4][6..4]	The name defines a two-dimensional bus that has a bus identifier DOUT and contains nine bits: DOUT6_6, DOUT6_5, DOUT6_4, DOUT5_6, DOUT5_5, DOUT5_4, DOUT4_6, DOUT4_5, and DOUT4_4 The MSB is DOUT6_6, and the LSB is DOUT4_4.

A[31..0],DOUT[6..4]	The name defines a bus containing 35 bits. The MSB is A31 and the LSB is DOUT4.

D[6..4][6..4], A[2..0]	The name defines a two-dimentional bus in a sequence with a standard bus that have bus identifiers D and A and contain 12 bits: D6_6, D6_5, D6_4, D5_6, D5_5, D5_4, D4_6, D4_5, D4_4, A2, A1, and A0. The MSB is D6_6, and the LSB is A0.

See also:

Groups (AHDL)

Illegal Bus Names

Naming a Node or Bus


Bus-to-Macrofunction Connections (Graphic Editor)
Bus-to-Macrofunction Connections

The following rules apply when you connect buses to macrofunctions in the Graphic Editor.

A bus can be connected to a macrofunction only if the bus pinstub on the macrofunction symbol has the same width (i.e., number of bits) as the bus. The number of bits in a bus must equal the number of bits in the bus pinstub. In contrast, you can connect buses to a primitive to form a primitive array.

When you create a symbol with Create Default Symbol (Symbol menu), MAX+PLUS II automatically places a bus pinstub in a symbol that represents a design file if a pin in the design file has a single-range bus name.

When you manually edit a symbol with Edit Ports/Parameters (Symbol menu), you create a bus pinstub with Enter Pinstub (Element menu).

Since buses and bus pinstub names are interpreted as a sequence of individual nodes, the order of bus bits is important. Example

A pin in a macrofunction must have a single-range bus name to be represented as a bus pinstub in the symbol for the macrofunction.

Buses can be logically connected by name only; they need not be physically connected. Buses are connected when two or more bus nodes have identical bus identifiers and share common bits in the bus width. Example.

See also:

Drawing a Line

Entering & Naming a Pinstub

Naming a Node or Bus

Ripping & Merging a Bus

Recommended reading:

AB84 (DMA Controller with the EPM5064 MAX EPLD)

AB86 (Designing & Simulating Bidirectional Buses with MAX+PLUS II Software)


Example: busses need not by physically connected
Busses need not be physically connected

Two buses named DOUT[6..4] in a Graphic Design File are considered to be logically connected to one another even though they never meet because they both have a width of three bits, and the bits names in each bus directly correspond to those of the other bus (i.e., DOUT6, DOUT5, and DOUT4).


Example: the order of bus bits is important
The order of bus bits is important

If a bus named DOUT[6..4] is connected to an input named IN[2..0], the Graphic Editor makes the following connections:

DOUT6 connects to IN2

DOUT5 connects to IN1

DOUT4 connects to IN0

If a two-dimensional bus named DOUT[6..4][1..0] is connected to an input named IN[5..0], the Graphic Editor makes the following connections:

DOUT6_1 connects to IN5

DOUT6_0 connects to IN4

DOUT5_1 connects to IN3

DOUT5_0 connects to IN2

DOUT4_1 connects to IN1

DOUT4_0 connects to IN0


Palette tools (Graphic & Symbol Editors)
Palette Tools

Click Button 1 on any item in this tool palette for information on that item:


Orthogonal Line tool (Graphic & Symbol Editors)
Orthogonal Line Tool

Draws a horizontal and/or vertical line in the direction of the mouse pointer movement

You draw a line by using Button 1 to select the Orthogonal Line tool , pressing Button 1 to anchor the line, dragging the mouse, and then releasing Button 1 when the line has the desired length.

If the mouse moves in a diagonal direction, two lines--one horizontal and one vertical--are drawn.

See also:

Changing the Line Style

Drawing a Line

Selecting an Object


Diagonal Line tool (Graphic & Symbol Editors)
Diagonal Line Tool

Draws a line in the direction of the mouse pointer movement.

The diagonal line tool draws a single line at any angle. If you draw a line horizontally or vertically, it becomes an orthogonal line.

You draw a line by selecting the Diagonal Line tool with Button 1, pressing Button 1 to anchor the line, dragging the mouse, and then releasing Button 1 when the line has the desired length.

See also:

Changing the Line Style

Drawing a Line

Selecting an Object


Arc tool (Graphic & Symbol Editors)
Arc Tool

Draws an arc with an angle of up to 180°.

You draw an arc by selecting the Arc tool with Button 1, pressing Button 1 to define the starting point of the arc, dragging the mouse, and then releasing Button 1 when the arc has the desired length and radius. Once you release Button 1, you cannot resize the arc.

You can reposition an arc while you are drawing it by pressing Button 2 to redefine the direction of the tangent line. The tangent line to the arc is defined by the anchor("starting") point and the initial direction of mouse dragging. The new tangent line passes through the starting and end points of the initial arc. After you release Button 2, you can continue drawing the new arc.

Connection dots can be entered at the ends of an arc.

See also:

Changing the Line Style

Drawing a Line

Selecting an Object


Circle tool (Graphic & Symbol Editors)
Circle Tool

Draws a circle in the Graphic Editor window.

You can draw a circle by selecting the Circle tool with Button 1, pressing Button 1 to define the edge of the circle, dragging the mouse, and then releasing Button 1 when the circle has the desired diameter. Once you release Button 1, you cannot resize the circle.

See also:

Changing the Line Style

Drawing a Line

Selecting an Object


Selection tool (Graphic & Symbol Editors)
Selection Tool

Allows you to perform manipulatory functions on objects in the Graphic and Symbol Editor windows.

With the Selection tool, you can:

Select, edit, move, and/or copy objects.

Define an insertion point for primitives, megafunctions, or macrofunctions.

See also:

Changing the Line Style

Drawing a Line

Selecting an Object


Text tool (Graphic & Symbol Editors)
Text Tool

Allows you to enter and edit text in the Waveform Editor.

You can use the Text tool to edit node names by pressing Button 1 and dragging the mouse over the text you wish to edit.

You can also use the Text tool to enter comments in empty space. For example, you can use comments to help describe the function of sections of your design or keep track of critical notes.

You can turn comments into node names by dragging them onto unnamed nodes.

See also:

Changing the Line Style

Drawing a Line

Selecting an Object


Primitive Arrays (Graphic Editor)
Primitive Arrays

A primitive array is a single primitive that represents multiple identical primitives. You can use primitive arrays to create a more compact GDF or OrCAD Schematic File by entering a single primitive that the Compiler Netlist Extractor translates into multiple primitives.

You can create primitive arrays in two ways:

If all the pinstubs of the primitive are connected to buses with n members, the primitive is translated into an array of n individual primitives. Each individual node of the bus is connected to the corresponding pinstub of each individual primitive in the array. Example

An INPUT, INPUTC, OUTPUT, OUTPUTC, BIDIR, or BIDIRC pin primitive that is given a single-range bus name is translated into an array of primitives. You cannot use a sequential bus name to name a pin primitive.

If some of the primitive’s pinstubs are connected to buses with n members and some are connected to single nodes, the primitive is translated into an array of n primitives. In this case, each individual node of the bus is connected to the corresponding pinstub of each primitive in the array, and each single node that is not part of a bus is connected to the same pinstub of each primitive. Example

You must name all nodes and buses that are used to create a primitive array except in the following cases, where node and bus names are optional:

A single node that is connected to a primitive array.

A bus wire that is connected to a primitive array, if at least one segment of the network that contains this bus wire is explicitly named before any connection dots or if the network is connected to a pin with a single-range bus name. Example

You cannot enter probe and resource assignments on primitive symbols used to create a primitive array. Refer to Guidelines for Working with Assignments for information on how to enter assignments for a primitive array.

See also:

Bus Names

Bus-to-Macrofunction Connections

Nodes

Pin & Node Names


Example: primitive array with a primitive connected to three buses
Primitive array with a primitive connected to three buses

In this example, a primitive array is created by connecting three buses, A[0..2], B[0..2], and C[0..2], to two INPUT pins, an OUTPUT pin, and an AND2 gate.

During processing, the Compiler translates this primitive array into six INPUT pins, three OUTPUT pins, and three AND2 gates, with the following connections:

One AND2 gate is connected to nodes A0, B0, and C0.

One AND2 gate is connected to nodes A1, B1, and C1.

One AND2 gate is connected to nodes A2, B2, and C2.

Input pins A0, A1, and A2 are connected to nodes A0, A1, and A2, respectively.

Input pins B0, B1, and B2 are connected to nodes B0, B1, and B2, respectively.

Output pins C0, C1, and C2 are connected to nodes C0, C1, and C2, respectively.


Example: primitive array with a primitive connected to two buses and a single node
Primitive array with a primitive connected to two buses and a single node

In this example, a primitive array is created by connecting two buses, B[0..2] and C[0..2], and a single node (A) to two INPUT pins, an OUTPUT pin, and an AND2 gate.

This schematic creates an array that includes six INPUT pins and six AND2 primitives.

During processing, the Compiler translates this primitive array into four INPUT pins, three OUTPUT pins, and three AND2 gates, with the following connections:

One AND2 gate is connected to nodes A, B0, and C0.

One AND2 gate is connected to nodes A, B1, and C1.

One AND2 gate is connected to nodes A, B2, and C2.

Input pin A is connected to node A.

Input pins B0, B1, and B2 are connected to nodes B0, B1, and B2, respectively.

Output pins C0, C1, and C2 are connected to nodes C0, C1, and C2, respectively.


Pin Default Values (Graphic Editor)
Pin Default Values

The values assigned to unconnected INPUT, INPUTC, BIDIR, and BIDIRC primitives when the symbol that represents the current GDF or OrCAD Schematic File is used in a higher-level design file. Show me.

Signal default values can be VCC or GND. Default values are effective only for lower-level design files; they are ignored for top-level design files.

To edit the default value, select the text by double-clicking Button 1 on it or press Button 2 and choose Edit Pin Default Value from the pop-up menu, then type VCC or GND.

1.	You can edit text in the default value text field but cannot leave the field empty.

2.	You should never edit a primitive symbol in the Symbol Editor. If you wish, you can open the Symbol File and use Copy and Paste (Edit menu) to copy the graphics in the file to the Symbol File for a macrofunction.

See also:

Changing the Pin Default Value


Pinstubs & Pinstub Names (Graphic & Symbol Editors)
Pinstubs & Pinstub Names

A pinstub is an "x" on a symbol border, visible when a Symbol File is open in the Symbol Editor, that represents an input or output of the symbol. Show me

A pinstub name on a macrofunction symbol represents a pin or port name in the macrofunction file, i.e., a design file. Therefore, pinstub names must have the same names as the pins or ports that they represent.

A node drawn in a GDF or OrCAD Schematic File must connect to a pinstub to be recognized as a symbol connection by the Compiler. If you enter two symbols so that their borders meet and pinstubs line up, the symbols become logically connected.

Pinstubs and pinstub names are automatically generated when you create a symbol with Create Default Symbol (Symbol menu). In a manually edited symbol, a pinstub is both created and named with Enter Pinstub (Element menu) in the Symbol Editor. A pinstub "x" is always displayed in the Graphic Editor, whereas the pinstub name is displayed only if you turn on the Show in Graphic Editor option in this dialog box.

A pinstub "x" is always associated with a name: if you delete the pinstub, the name is automatically deleted and vice versa. This association is maintained regardless of where the pinstub name is moved within the symbol border. In the Symbol Editor, pinstub names are also duplicated outside the symbol border. These names cannot be moved or edited and are always shown next to the associated pinstub "x." They are not visible in Graphic Editor files but can help you keep track of which pinstub is associated with a name while you are editing the symbol. Show me

The INPUTC, OUTPUTC, and BIRDIRC primitives include special external connection pinstubs. You can connect these pinstubs to specify the device pins that are externally connected on your board.

1.	You should never edit a primitive symbol in the Symbol Editor. If you wish, you can open the Symbol File and use Copy and Paste (Edit menu) to copy the graphics in the file to the Symbol File for a macrofunction.

2.	Refer to Symbol File for important information on editing symbols in OrCAD Schematic Files.

See also:

Bus Names

Changing the Pinstub Name & I/O Type

Entering & Naming a Pinstub

Pin & Node Names

Assigning Connected Pins


Symbol Border (Graphic & Symbol Editors)
Symbol Border

The symbol border is the visible border containing the symbol name, symbol ID number, and pinstubs and pinstub names. Show me

In the Symbol Editor, you can resize the border of a macrofunction symbol by dragging it with Button 1, but you must always work within the symbol border. You may need to move objects within a symbol before enlarging or reducing the border.

1.	You should never edit a primitive symbol in the Symbol Editor. If you wish, you can open the Symbol File and use Copy and Paste (Edit menu) to copy the graphics in the file to the Symbol File for a macrofunction.

2.	Refer to Symbol File for important information on editing symbols in OrCAD Schematic Files.

See also:

Changing the Symbol Size


Symbol ID Number (Graphic & Symbol Editors)
Symbol ID Number

Each symbol is uniquely identified with a symbol ID number, which appears by default in the lower left corner of the symbol. MAX+PLUS II assigns symbol ID numbers in the order in which you enter symbols in a GDF or OrCAD Schematic File. For example, the first symbol entered is assigned the ID number 1. If you delete a symbol, the ID number is deleted with it. Show me

The Compiler also assigns symbol or "net" ID numbers to nodes in other types of design files.

MAX+PLUS II uses net and symbol ID numbers to identify each node and symbol in a project, incorporating them into hierarchical node and symbol names. You can use Find Node in Design File (Utilities menu) to locate symbols and nodes with these names and ID numbers.

In the Symbol Editor, you can move the symbol ID number for a macrofunction to a different location within the symbol border, but you cannot delete it.

1.	You should never edit a primitive symbol in the Symbol Editor. If you wish, you can open the Symbol File and use Copy and Paste (Edit menu) to copy the graphics in the file to the Symbol File for a macrofunction.

2.	If you save a GDF as an OrCAD Schematic File and then edit the file with OrCAD, some information from the original file is lost. For example, symbol ID numbers are reassigned randomly in OrCAD Schematic Files. Refer to Restrictions on OrCAD Schematic Files in MAX+PLUS II and Guidelines for Working with OrCAD Schematic Files for important information on working with OrCAD Schematic Files.

See also:

Entering a Symbol

Finding Nodes & Symbols in Design Files

Recommended reading:

AB92 (Simulating Internal Nodes with MAX+PLUS II Software)


Symbol Name (Graphic & Symbol Editors)
Symbol Name

Shows the name of the Symbol File that represents a primitive or macrofunction. A symbol that represents an Altera-provided macrofunction or any other design file must have the same name as that file. Show me

A symbol must have only one name, which can contain up to 32 name characters. In the Symbol Editor, you can edit a macrofunction symbol name by double-clicking in the name with Button 1 or pressing Button 2 on the symbol name and choosing Edit Selected Text from the Button 2 pop-up menu. However, you must ensure that the symbol name matches the corresponding design file name before you compile the project.

1.	You should never edit a primitive symbol in the Symbol Editor. If you wish, you can open the Symbol File and use Copy and Paste to copy the graphics in the file to the Symbol File for a macrofunction.

2.	Refer to Symbol File for important information on editing symbols in OrCAD Schematic Files.

See also:

Creating the Default Symbol for a File

Editing the Symbol for a File


Text (Graphic & Symbol Editors)
Text

Text appears in many areas within a GDF, OrCAD Schematic File, or Symbol File. Text appears either in association with an object--e.g., as a node name, bus name, symbol name, probe or resource assignment--or in a separate block that is used for documentation purposes.

Free-floating text that is not associated with any object is considered to be a comment. You can use comments, which are ignored by the Compiler, to provide information on a circuit design. A comment stands alone within a Symbol File, GDF, or OrCAD Schematic File. You can enter a comment in the Graphic or Symbol Editor window by clicking Button 1 on the text entry tool palette button, defining an insertion point anywhere in blank space, and then typing in the desired text. However, if you enter or move a comment so that it touches a bus or node line, it becomes a bus or node name.

Other types of text are always associated with an object, including pin, node, bus, symbol, and pinstub names; probes; and resource assignments. If you delete the object, the associated text is deleted automatically. You can also drag a node or bus name away from the associated line to change it into a comment.

In addition to comments, you can edit the following types of text that appear in a GDF, OrCAD Schematic File, or Symbol File:

Application:	Type of Text:

Graphic Editor	Bus Names

Node Names

Symbol Editor	Pinstub Names

Symbol Names

The Find Text and Search & Replace (Utilities menu) commands in the Graphic and Symbol Editors allow you to locate and edit all types of text.

See also:

Changing the Pin Name or Default Value

Changing the Pinstub Name & I/O Type

Changing the Text Size

Copying, Cutting & Pasting Text

Deleting Text

Entering & Naming a Pinstub

Entering a Text Block (Comment)

Finding Text

Finding & Replacing Text

Naming a Node or Bus

Ripping & Merging a Bus

Selecting Text


Graphic Design File (.gdf) Description
Graphic Design File (.gdf)

A binary file (with the extension .gdf), created with the Graphic Editor, that contains a logic schematic. You can also save an OrCAD Schematic File as a GDF.

A GDF can contain Altera-provided primitive, megafunction, and macrofunction symbols, as well as user-created megafunction and macrofunction symbols that represent any type of MAX+PLUS II design file into a GDF.

A single GDF can be used to define all logic in a project, or can be incorporated at any hierarchy level in a hierarchical project. MAX+PLUS II automatically creates a Symbol File that represents a GDF when you choose Create Default Symbol (File menu). This symbol and the logic it represents can be incorporated into another GDF.

You can use GDF logic in an AHDL TDF by including a Function Prototype and inserting an instance of the macrofunction into the TDF. You can also automatically generate a default Include File that contains a Function Prototype for a GDF with Create Default Include File (File menu).

You can also use GDF logic in a VHDL Design File by declaring a package for the project--containing Component Declarations for all lower-level entities--in the top-level design file.

You can create a super-project GDF containing symbols that represent multiple individual sub-projects. In this type of GDF, the symbols represent the SNFs for each individual project, not the actual design files. You can compile the super-project to generate a linked SNF that combines the timing and functional SNF information for each sub-project. This SNF allows you to perform a board-level-type simulation. For more information on super-project GDFs, refer to the guidelines in File Structure Requirements for Multi-Project Simulation.

The MAX+PLUS II Compiler automatically compiles GDFs created with the MAX+PLUS II or MAX+PLUS (DOS) Graphic Editor.

The file icon for each GDF that is part of the current hierarchy tree appears in the Hierarchy Display window.

A GDF created with the MAX+PLUS (DOS) Graphic Editor contains the default or manually edited symbol that represents the file; the symbol is not stored separately in a Symbol File. Therefore, you should open, update, and save the file in the MAX+PLUS II Graphic Editor to produce a separate Symbol File to use with MAX+PLUS II.

See also:

Combining Multiple Projects for Simulation

Creating a Default Include File

Creating & Using Custom Macrofunctions (AHDL)

Creating the Default Symbol for a File


Symbol File (.sym) Description
Symbol File (.sym)

A binary file (with the extension .sym) containing a primitive symbol or a symbol that represents a design file with the same filename.

A Symbol File can contain a default or customized symbol that represents a design file, i.e., a user-defined macrofunction. Altera also provides symbols for all MAX+PLUS II primitives and macrofunctions.

Symbols are used in GDFs and OrCAD Schematic Files. A Graphic Editor file can contain symbols that represent all types of user-created design files, as well as Altera-provided primitives and macrofunctions. You can store your own design files and the symbols that represent them in user libraries that provide easy access during design entry.

The first time you save a GDF or WDF, MAX+PLUS II automatically creates a Symbol File with a default symbol that includes pinstubs for all inputs and outputs of the file. The default symbols for text-based design files--including TDFs, ADFs, SMFs, EDIF Input Files, VHDL Desing Files, and XNF Files--are first created when you choose the Create Default Symbol (File menu) command or compile the project. A Symbol File that represents a design file must always have the same filename as the design file.

You can open the Symbol Editor and edit the symbol that represents a design file with the Edit Symbol command (Symbol menu) in the Graphic, Text, or Waveform Editor.

A default or manually edited symbol is not automatically updated to reflect changes to the design file that it represents. Therefore, if the number and/or names of inputs and outputs of a design file change, you must explicitly update a symbol with Create Default Symbol or Edit Symbol.

A GDF created with the MAX+PLUS (DOS) Graphic Editor contains the default or manually edited symbol that represents the file; the symbol is not stored separately in a Symbol File. Therefore, you should open, update, and save a MAX+PLUS (DOS) GDF in the MAX+PLUS II Graphic Editor to produce a separate Symbol File to use with MAX+PLUS II.

The file icon for a Symbol File with the same filename as the top-level design file in the current hierarchy tree appears in the Hierarchy Display window.

When you open an OrCAD Schematic File in the Graphic Editor, MAX+PLUS II automatically translates the symbol and pinstub names in the original OrCAD file into their equivalent MAX+PLUS II symbol and pinstub names by using the mappings provided in the orcad.lmf file. However, the shape and pinstub locations in the original OrCAD symbol, which are stored in an OrCAD Library File, are preserved to maintain connectivity.

When you save an OrCAD Schematic File as a GDF, the "converted" OrCAD symbols do not have a corresponding Symbol File on disk. The only Symbol File that is available for you to edit or update is the Altera-provided version of the file, which may have a significantly different appearance. Therefore, you should exercise caution if you wish to edit or update a symbol in a file that is imported from OrCAD because you may lose connectivity in your schematic.

See also:

Creating the Default Symbol for a File

Editing the Symbol for a File

Specifying a User Library

Updating a Symbol in a Graphic Editor File


Example 2: Bus name placement for primitive arrays
Bus name placement for primitive arrays


Example 4: Naming nodes that are connected to buses
Naming nodes that are connected to buses


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Assignment Locations on Symbols

Probe and resource assignments are attached to symbols at the following locations:

Probes	On an input or output of a symbol.

Pins/LCs/Chips	On the bottom left corner of the symbol. Assignments on INPUT, INPUTC, OUTPUT, OUTPUTC, BIDIR, and BIDIRC pin symbols appear to the left or right of the symbol.

Cliques	On the top left corner of the symbol.

Logic Options	On the bottom right corner of the symbol.

Timing Assignments	On the top right corner of the symbol.


Symbol Elements


Connection by name only


Example: Bus name exceptions for primitive arrays
Bus name exceptions for primitive arrays


Example: Bus name exceptions
Bus name exceptions


Graphic: line style options
Line Style Options


Graphic Editor Window


Pin, Node, & Bus Names
Pin, Node & Bus Names


Pin Default Values


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Graphic & Symbol Editor Contents
Graphic & Symbol Editor Help Contents

Introduction

Basic Tools (including primitives and macrofunctions)

Commands

Procedures

Golden Rules

Shortcuts

Messages

Glossary


Graphic & Symbol Editors--Context-Sensitive Help
Graphic & Symbol Editor Context-Sensitive Help

Context-sensitive help is available for all Graphic & Symbol Editor commands, dialog boxes and messages, and the following basic tools:

Grid & Guidelines

Grid

Guidelines

Macrofunctions

Nodes, Names & Buses

Nodes

Pin & Node Names

Buses

Bus Names

Bus-to-Macrofunction Connections

Palette Tools

Orthogonal Line Tool

Diagonal Line Tool

Arc Tool

Circle Tool

Primitives

Probe, Resource & Device Assignments

Clique Assignments

Logic Option Assignments

Pin, Location & Chip Assignments

Probe Assignments

Timing Assignments

Status Bar & Toolbar

Status Bar

Toolbar

Symbol Elements

Pin Default Values

Pinstubs & Pinstub Names

Symbol Border

Symbol ID Number

Symbol Name

Text

For information on other basic tools, see Graphic & Symbol Editor Basic Tools.

See also:

Getting Context-Sensitive Help


Graphic & Symbol Editor Introduction
Introduction

The MAX+PLUS II Graphic Editor is a sophisticated schematic capture program that allows you to enter both simple and complex designs quickly and easily. Show me

With the Symbol Editor, you can view, create, and edit symbols that represent design files. These symbols can then be used in schematics created with the Graphic Editor. Show me

Together, the Graphic and Symbol Editors make it easy for you to enter and edit schematic designs.

How Do the Graphic & Symbol Editors Work?

The Graphic Editor allows you to create and edit a GDF that includes any combination of macrofunction and primitive symbols. The Graphic Editor also allows you to open an OrCAD Schematic File and save it as a GDF.

A Graphic Editor file incorporates the design logic represented by each symbol into a design hierarchy. You can choose from libraries containing over 300 Altera-provided macrofunctions and primitives, or use your own custom macrofunction symbols that represent other design files, including other Graphic Editor files. In addition, you can freely combine Graphic Editor files with other types of design files in a hierarchical project.

MAX+PLUS II allows you to automatically generate a symbol that represents any design file. You can use the Symbol Editor to customize these Symbol Files and use any combination of symbols in a Graphic Editor file. When a symbol has been modified, you can easily update it in any Graphic Editor file.

With the Graphic Editor, you connect symbols by drawing single nodes or buses that represent multiple logically grouped nodes. By assigning names to nodes and buses, you can connect symbols by name only. In addition, you can use primitive arrays to represent multiple symbols that are logically grouped.

When moving a symbol or area in the Graphic Editor, you can use rubberbanding to preserve signal connectivity. You can flip and rotate symbols or areas, and zoom in and out to change the view of the file.

All MAX+PLUS II design editors allow you to enter device and resource assignments, and tag timing source and destination nodes for timing analysis. You can also traverse the hierarchy of a project, allowing MAX+PLUS II to automatically open the appropriate editor for each design file. When you compile a project, the Message Processor can automatically locate and highlight any errors in the Graphic & Symbol Editor windows.

Where to Start

Altera offers a variety of information to help you create designs with MAX+PLUS II and the Graphic and Symbol Editors.

On-Line Help

On-line help supplies complete reference and how-to information on using the MAX+PLUS II Graphic and Symbol Editors.

Graphic & Symbol Editor Help Contents provides access to all on-line Graphic and Symbol Editor Help.

Graphic & Symbol Editor Golden Rules describes essential guidelines and recommendations for using the Graphic and Symbol Editors.

Recommended Reading

Additional Altera publications help you understand MAX+PLUS II and the Graphic and Symbol Editors. The following application notes and briefs are relevant to using the Graphic Editor:

AN26 (ELPD/MPLD Design Guidelines)

AB9 (Asynchronous Latches in Classic, MAX & STG EPLDs)

AB60 (Estimating a Design Fit)

AB77 (Fitting Complex Designs in MAX 5000 EPLDs)

AB82 (Emulating Internal Buses in Classic, MAX & STG EPLDs)

AB86 (Designing & Simulating Bidirectional Buses with MAX+PLUS II Software)

AB87 (Troubleshooting Functional Problems in EPLDs)

AB88 (Optimizing Counter Design for Altera EPLDs)

AB92 (Simulating Internal Nodes with MAX+PLUS II Software)

AB93 (Partitioning a Project with MAX+PLUS II Software)

AB94 (Solutions to Design Timing Problems for Altera EPLDs)

Specific design applications that include design entry with the Graphic Editor are also available:

AN16 (Integrating PAL, GAL & PLA Devices with the EPM5032 MAX EPLD)

AN17 (Integrating an Intelligent I/O Subsystem with a Single EPM5130 MAX EPLD)

AN20 (Fast Bus Controllers with the EPM5016 MAX EPLD)

AN21 (Designing a FIFO Controller with an EPM5064 MAX EPLD)

AN27 (Implementing EISA Interfaces with MAX EPLDs)

AB27 (EP1810 Classic EPLD as a Bar Code Decoder)

AB83 (Programmable Frequency Divider with the EP610 Classic EPLD)

AB84 (DMA Controller with the EPM5064 MAX EPLD)

AB95 (Designing Phase-Locked Loops with Altera EPLDs)

See also:

How to Use MAX+PLUS II Help


Graphic Editor Window


Symbol Editor Window


Graphic & Symbol Editor Golden Rules
Golden Rules

The following golden rules will help you use the Graphic and Symbol Editors effectively:

Graphic & Symbol Editor Design Entry Golden Rules

When naming nodes, pins, and buses, follow the MAX+PLUS II naming conventions in Pin & Node Names and Bus Names.

When connecting a primitive to another primitive, use only legal interconnections; not all primitives may connect to all other primitives. For a list of the legal interconnections for primitives (except logic primitives), see Primitive/Port Interconnections.

Although the Compiler interprets all line styles as logical connections, Altera recommends using the solid line style for drawing nodes. Buses must be drawn with the bus (wide) line style.

When connecting buses to macrofunctions, follow the rules in Bus-to-Macrofunction Connections.

Avoid entering a node or bus name so that it touches two lines; the text may become associated with the wrong line. If you are not sure whether a name is attached to a certain line, click Button 1 on the line to highlight the line and the name associated with it.

To modify the symbol for an Altera-provided macrofunction, first use Save As to save a copy of both its Symbol File and the design file to your project directory.

The Symbol File that represents a macrofunction must have the same filename as the macrofunction.

Although you cannot modify primitive symbols, you can open the Symbol File and use Copy and Paste to copy the graphics in the file to the Symbol File for a macrofunction.

When multiple bidirectional or output pins are tied together, you cannot connect the external connection pinstubs of external connection pin primitives for hardware-assisted functional simulation or functional testing.

A logical connection does not automatically occur when two lines meet or cross over each other. To create a connection, you must enter a connection dot as described in Entering a Connection Dot.

Use caution when flipping or rotating symbols or areas--connectivity between a flipped or rotated symbol or area and the surrounding logic is not maintained even if Rubberbanding is turned on.

Use only the EXPDFF, EXPLATCH, NANDLTCH, and NORLTCH macrofunctions provided with the MAX+PLUS II Macrofunction Library; do not create your own cross-coupled structures. Avoid tying multiple EXPDFF, EXPLATCH, NANDLTCH, and NORLTCH together. Multiple instances of these macrofunctions should always be separated by LCELL primitives.

If you import a project that includes OrCAD Schematic Files into MAX+PLUS II, Altera strongly recommends that you open the files in the Graphic Editor, save the files as GDFs with Save As, and then specify the top-level GDF as the project name instead of the OrCAD Schematic File. You can then take advantage of the error location capabilities of MAX+PLUS II during compilation to find and then correct any problems with the logic. See OrCAD Schematic File for more information on the restrictions associated with using OrCAD Schematic Files.

To make your Graphic Editor files more compact, use the following guidelines:

Use a bus to represent multiple nodes that are logically grouped.

Create a primitive array by connecting buses to a primitive symbol to represent multiple identical symbols.

Use buses and nodes that are logically connected by name only; they do not need to be physically connected. Buses are logically connected when two or more nodes in each bus have the same name.

Move symbols closer together to conserve space; the symbols are connected if the pinstubs are touching and are properly aligned.

General Design Entry Golden Rules

The following guidelines are common to all MAX+PLUS II Editors:

Be sure to refer to Guidelines for Working with Assignments for absolutely essential information on using all types of resource, probe, and device assignments.

If you wish to load a register on specific rising edges of the global Clock, Altera recommends that you use the Clock Enable input of one of the DFFE, JKFFE, SRFFE, or TFFE flipflops to control when the register is loaded.

When you start work on a new design file, specify the target device family with Device right away so that you can take advantage of family-specific macrofunctions. If you dont specify a device family, the family for the current project is assumed.

Use the Design Doctor to check the reliability of your project logic during compilation. Follow Project Reliability Guidelines to create reliable projects.

The Altera-provided default logic synthesis styles have different settings for different device families to ensure that each architecture is used most efficiently. When you use an Altera-provided style, the settings for that style will change when you change the device family. After changing the device family, check the new style settings to ensure that they conform to your needs.

General MAX+PLUS II Golden Rules

When you start work on a new design file, name it as the current project with Project Name right away so that you can compile it easily. You can always change the project name later.

Use the built-in hierarchy traversal features in MAX+PLUS II to move between design files for the current hierarchy. To open a lower-level file in a hierarchy, open the top-level file and then use the Hierarchy Display window or Hierarchy Down to open the lower-level files. If you choose Open or Retrieve to open a lower-level file, it is considered to be the top of a different hierarchy tree, and resource, device, and probe assignments that you enter are saved only for that hierarchy, not for the project.

When you create an ancillary file for a project, the icon for the file will appear in the Hierarchy Display if you use the same filename as the project.

Dont edit any MAX+PLUS II system files, including HIFs, maxplus2.idx, or the maxplus2.ini file.

Use the Save As command if you wish to rename a design file or an ancillary file. Dont rename design files from outside of the MAX+PLUS II system (e.g., from DOS or with the Windows File Manager).

When you have completed a project, use Project Archive to ensure that you save a complete backup copy of all project files that will not be affected by future edits or deletions.


Graphic & Symbol Editor Shortcuts
Shortcuts

The following list provides shortcuts for Graphic and Symbol Editor commands:

Command:	Shortcut:

Context-Sensitive Help	Shift+F1 or

Cascade	Shift+F5

Clique	Double-click Button 1 on a clique assignment to edit a clique

Close	Ctrl+F4 or double-click Button 1 on the Document Control Menu box

Compiler

Copy	Ctrl+C or Ctrl+Insert, or [image] or Press Ctrl+Button 1, drag, and release with the Selection pointer

Cut	Ctrl+X or Shift+Del, or

Delete	Del or Backspace

Enter Pinstub	Double-click Button 1 on or within the symbol border or on a pinstub x to create or edit a pinstub

Enter Symbol	Double-click Button 1 on a blank space

Exit MAX+PLUS II	Alt+F4 or double-click Button 1 on the Application Control Menu box

Find Next	Ctrl+N

Find Node in Design File	Ctrl+B or

Find Node in Floorplan Editor

Find Node Destination	Ctrl+Shift+D

Find Node Source	Ctrl+Shift+S

Find Previous	Ctrl+Shift+N

Find Text	Ctrl+F or

Fit in Window	Ctrl+W or

Flip Horizontal

Flip Vertical

Floorplan Editor

Font commands

Hierarchy Display

Hierarchy Down	Ctrl+D or double-click Button 1 on a macrofunction symbol

Hierarchy Project Top	Ctrl+T or

Hierarchy Up	Ctrl+U

Info	Ctrl+I

Line Style commands

Logic Options	Double-click Button 1 on a logic option assignment to edit a logic option

Maximum Size	Ctrl+2

New

Next	Ctrl+F6

Normal Size	Ctrl+1

Open	Ctrl+O or

Paste	Ctrl+V or Shift+Insert, or

Pin/Location/Chip	Double-click Button 1 on a primitive symbol or a pin, logic cell, or chip assignment

Print 	Ctrl+P or

Probe	Double-click Button 1 on a probe assignment to edit a probe

Programmer

Project Name	Ctrl+J or

Project Save & Check

Project Save & Compile	Ctrl+L or

Project Save & Simulate	Ctrl+Shift+L or

Project Set Project to Current File	Ctrl+Shift+J or

Rubberbanding	On:  Off:

Save	Ctrl+S or

Save & Check	Ctrl+K or

Search & Replace	Ctrl+R or

Show All	Ctrl+Shift+M or

Show Guidelines	Ctrl+Shift+G

Simulator

Snap to Grid

Switch To	Ctrl+Esc

Text Size commands

Tile	Shift+F4

Timing Requirements	Double-click Button 1 on a timing assignment

Timing Analyzer

Timing Cutoff	Ctrl+Alt+C

Timing Destination	Ctrl+Alt+D

Timing Source	Ctrl+Alt+S

Toggle Connection Dot

Undo	Ctrl+Z or Alt+Backspace or

Zoom In	Ctrl+Space or

Zoom Out	Ctrl+Shift+Space or

See also:

Guidelines for Workstation Help Users

Selecting Text

Showing the Toolbar


Graphic & Symbol Editor Procedures
Procedures

Assignments & Compiler Configuration Settings

Assigning a Clique

Assigning a Device

Assigning a Pin, Location, or Chip

Assigning a Probe

Assigning an Individual Logic Option or Synthesis Style

Assigning Connected Pins

Assigning Individual Timing Requirements

Back-Annotating Assignments for a Project

Clearing Assignments for a Project

Converting an Obsolete Assignment Format

Copying a Resource Assignment

Defining a Logic Synthesis Style

Deleting an Assignment

Guidelines for Achieving Maximum Speed Performance

Guidelines for First-Time Project Fitting

Guidelines for Timing Assignments

Guidelines for Working with Assignments

Ignoring Project Assignments during Compilation

Logic Synthesis Style & Logic Option Rules

Moving a Probe or Resource Assignment

Searching the Node Database

Selecting a Probe and Resource Assignment

Showing Parameters and Probe & Resource Assignments

Specifying Devices for Automatic Device Selection

Specifying Global Project FLEX 8000 Device & Pin Options

Specifying Global Project Logic Synthesis Settings

Specifying Global Project Security Bit & Reserved Resource Settings

Specifying Global Project Timing Requirements

Specifying Individual Device Security & Turbo Bit Options

Specifying Individual FLEX 8000 Device & Pin Options

File Management

Changing the File Size

Closing a File

Creating a Default Include File

Creating a New File

Getting Information on a File

Opening a File

Printing a File (Graphic Editor)

Printing a File (Symbol Editor)

Retrieving a File

Saving a File

Grid & Guidelines

Changing the Guideline Spacing

Showing Guidelines

Snapping to the Grid

Hierarchy

Navigating the Hierarchy

Updating the Hierarchy

MAX+PLUS II Management

Changing Colors in MAX+PLUS II

Closing a MAX+PLUS II Application

Creating & Using a Local Copy of the maxplus2.ini File

Entering an Authorization Code

Exiting from MAX+PLUS II

Specifying a User Library

Starting MAX+PLUS II Applications

Switching Between MAX+PLUS II Applications

Messages

Getting Help on a Message

Locating the Source of a Message

Project Management

Archiving a Project

Changing the Project Name

Combining Multiple Projects for Simulation

Compiling a Project

Creating & Using a Local Copy of the maxplus2.ini File

Ensuring Project Reliability

Project Reliability Guidelines

Partitioning a Project

Automatic Partitioning

Guiding the Partitioner

Viewing the Results of Partitioning

Renaming a Macrofunction in the Current Project

Status Bar & Toolbar

Showing the Status Bar

Showing the Toolbar

Symbols & Other Graphics

Changing the Line Style

Changing the Pin Name or Default Value

Changing the Pinstub Name, I/O Type & Default Status

Changing the Symbol Size

Clearing Timing Tags

Copying, Cutting & Pasting an Object

Creating the Default Symbol for a File

Deleting an Object

Drawing a Circle

Drawing a Line

Drawing an Arc

Editing the Symbol for a File

Entering & Naming a Pinstub

Entering a Connection Dot

Entering a Symbol

Finding a Node Source or Destination

Finding Nodes & Pins in the Floorplan Editor

Finding Nodes & Symbols in Design Files

Flipping a Selection

Moving an Object

Naming a Node or Bus

Ripping & Merging a Bus

Rotating a Selection

Selecting an Object

Selecting a Node Network

Selecting a Pinstub

Tagging Timing Cutoff Nodes

Tagging Timing Source & Destination Nodes

Turning Rubberbanding On or Off

Updating a Symbol in a Graphic Editor File

Text

Changing the Font

Changing the Text Size

Copying, Cutting & Pasting Text

Deleting Text

Entering a Text Block (Comment)

Finding Text

Finding & Replacing Text

Selecting Text

Timing Analysis

Running a Timing Analysis

Undoing Edits

Viewing a File

Fitting a File into the Window

Zooming In & Out


Changing the File Size (Graphic Editor)
Changing the File Size

To change the size of a GDF or OrCAD Schematic File:

1.	Choose Size (File menu). The Size dialog box is displayed.

2.	Select the desired sheet orientation.

3.	Select the desired sheet size or Automatic in the Sheet Size box.

4.	Choose OK.

If you select Automatic, the Graphic Editor selects the smallest sheet size and orientation that can contain the current objects in the file.

If you print or plot a Graphic Editor file on a sheet with the same size specified in this command, all objects in the file are printed at Normal Size (View menu). If you print the file on smaller paper, objects in the file are scaled according to the parameters specified with Print (File menu).

See also:

Printing a File


Printing a File (Graphic Editor)
Printing a File

You can print any GDF or OrCAD Schematic File from MAX+PLUS II, including Altera-provided MAX+PLUS II megafunctions and macrofunctions, that appear in the current Graphic Editor window.

To print the current file in the Graphic Editor window:

1.	If you wish, turn on one or more of the following Options menu commands to print the specified item(s) with the file:

Show Parameters

Show Probes

Show Pins/Locations/Chips

Show Cliques & Timing Assignments

Show Logic Options

Show All

Show Guidelines

2.	Open the Print dialog box by choosing Print (File menu) or using a shortcut.

3.	If necessary, change the settings for one or more of the following printing options:

Option:	Action:

Copies	Specifies the number of copies to print. Multiple copies are collated.

Pages

All	Prints the entire file. The current sheet size, as determined by Size (File menu), is displayed for your reference.

Selected Area	Prints only the currently selected area.

Fit Into

? % of One Page	Scales the selected print area (All or Selected Area) to fit into a percentage (up to 100%) of a single page.

? Pages	Specifies the number of pages (1, 4, or 9) used to print the file. Scales the selected print area (All or Selected Area) to 100%, 200%, 300%, or 400% of the paper size.

Print

Symbol Borders & Numbers	Prints the symbol borders and the symbol ID numbers.

Pin Default Values	Prints the default values for unconnected pins.

Page Headers	Prints the filename, date, page count, and project name at the top of each page.

Sheet Border	Prints the border specified with Size.

All 	Prints the symbol borders and numbers, pin default values, page headers, and the sheet border.

4.	Choose OK.

To change the printer and printer options:

1.	Choose Print Setup (File menu). The Print Setup dialog box is displayed.

2.	Select the correct printer.

3.	If you wish to modify your print setup, choose Setup to open a dialog box that controls options for your printer, change any desired options, and choose OK to return to the Print Setup dialog box.

4.	Choose OK in the Print Setup dialog box.

See also:

Showing Guidelines

Showing Parameters and Probe & Resource Assignments


Printing a File (Symbol Editor)
Printing a File

To print the current Symbol File:

1.	To print guidelines in the file, turn on Show Guidelines (Options menu) or use a shortcut.

2.	Open the Print dialog box by choosing Print (File menu) or using a shortcut.

3.	If necessary, change the settings for one or more of the following printing options:

Option:	Action:

Copies	Specifies the number of copies to print. Multiple copies are collated.

Fit into ? % of One Page	Scales the selected print area (All or Selected Area) to fit into a percentage (up to 100%) of a single page.

Print Page Headers	Prints the filename, date, page count, and project name at the top of each page.

4.	Choose OK.

To change the printer and printer options:

1.	Choose Print setup (File menu). The Print setup dialog box is displayed.

2.	Select the correct printer.

3.	If you wish to modify your print setup, choose Setup to open a dialog box that controls options for your printer, change any desired options, and choose OK to return to the Print setup dialog box.

4.	Choose OK in Print setup dialog box.

See also:

Showing Guidelines


Changing the Guideline Spacing (Graphic & Symbol Editors)
Changing the Guideline Spacing

To change the spacing of the horizontal and vertical guidelines:

1.	Choose Guideline Spacing (Options menu). The Guideline Spacing dialog box is displayed.

2.	Type an integer between 1 and 999 in the X (Horizontal) Spacing and Y (Vertical) Spacing boxes.

3.	Choose OK.

If the guidelines are not visible, you can display them by choosing Show Guidelines (Options menu) or using a shortcut. When the guidelines are visible, their X and Y coordinates appear along the top and left edges of the drawing, reflecting the current guideline spacing.

See also:

Showing Guidelines


Showing Guidelines (Graphic & Symbol Editors)
Showing Guidelines

The guidelines provide a visual reference to aid in aligning objects in the Graphic and Symbol Editors. Showing the guidelines has no effect on whether the Symbol Editor’s Snap to Grid command (Options menu) is turned on or off.

To show or hide the guidelines:

Choose Show Guidelines (Options menu) or use a shortcut.

See also:

Changing the Guideline Spacing


Snapping to the Grid (Symbol Editor)
Snapping to the Grid

The grid in the Symbol Editor allows you to precisely position objects within a symbol. When the grid is turned on, grid lines become "magnetic" and objects that are entered, moved, or resized will snap to them. Turning the grid on or off has no effect on the placement of existing objects already in a file.

To turn the snap to grid feature on or off:

Choose Snap to Grid (Options menu) or use a shortcut.

Any objects or text that you enter or move are pulled to the nearest grid line intersection.

See also:

Showing Guidelines


Moving a Probe or Resource Assignment (Graphic Editor)
Moving a Probe or Resource Assignment

You can move a single probe, or one or more pin, logic cell, chip, clique, or logic option assignments in the current GDF or OrCAD Schematic File:

To move a single probe or one or more resource assignments:

1.	With the Selection tool [image], select a single probe or one or more resource assignments.

2.	Point to the selected assignment(s).

3.	Press Button 1.

4.	Drag the probe or resource assignment(s) to the center of the symbol to which you want the assignment to move.

5.	Release Button 1. If you move a probe in this way, it is automatically placed on the first output pinstub of the symbol.

or:

1.	Select a probe or resource assignment.

2.	Point to the symbol to which you want the assignment(s) to move. If you are moving a probe, point to the pinstub to which you want the assignment to move.

3.	Press Shift and click Button 1.

To move a single probe or resource assignment:

1.	Point to an assignment.

2.	Press Button 1.

3.	Drag the probe or resource assignment to the center of the symbol to which you want the assignment to move.

4.	Release Button 1. If you move a probe in this way it is automatically placed on the first output pinstub of the symbol.

See also:

Clearing Assignments for a Project

Copying a Resource Assignment

Deleting an Assignment

Moving an Object

Selecting a Probe or Resource Assignment

Showing Parameters and Probe & Resource Assignments


Selecting a Probe or Resource Assignment (Graphic Editor)
Selecting a Probe or Resource Assignment

When you select a symbol to which assignments are attached, the assignments are also selected.

To select a probe or resource assignment without selecting the entire symbol to which it is attached:

With the Selection tool ( [image]), click Button 1 on the assignment.

See also:

Copying a Resource Assignment

Moving a Probe or Resource Assignment

Selecting an Object

Showing Parameters and Probe & Resource Assignments


Showing Probe & Resource Assignments (Graphic Editor)
Showing Parameters and Probe & Resource Assignments

Probe and resource assignments can be shown only in the Graphic Editor window. Parameters can be shown in both the Graphic and Symbol Editor windows.

To display or hide probes and/or resource assignments:

Choose one or more of the following Options menu commands:

Command:	Function:

Show Parameters	Displays or hides parameters from view.

Show Probes	Displays or hides probes from view.

Show Pins/Locations/Chips	Displays or hides pin, logic cell, and chip assignments from view.

Show Cliques & Timing Assignments	Displays or hides cliques and timing assignments from view.

Show Logic Options	Displays or hides logic option assignments from view.

Show All	Displays or hides all probe and resource assignments.

Pin, logic cell, and chip assignments appear on the bottom left corner of a symbol. Note that pin assignments on pin symbols (INPUT, INPUTC, OUTPUT, OUTPUTC, BIDIR, and BIDIRC) appear to the left or right of the symbol. Clique assignments appear on the top left corner, and logic options appear on the bottom right corner. Probe assignments are attached to an individual pinstub of a symbol.

Assignments that are displayed in the window are printed when the file is printed.

See also:

Printing a File


Changing the Line Style (GraphicEditor & Symbol Editor)
Changing the Line Style

To change the style of one or more selected lines:

1.	Select one or more lines.

2.	Choose Line Style (Options menu) and select a line style from the submenu or use a shortcut.

All selected lines are changed to the specified style.

To set the line style for new line entries:

1.	Click Button 1 in a blank space in the window to ensure that no lines are selected.

2.	Repeat step 2 above.

The Line Style drop-down list box on the toolbar displays the current line style for new line entries.

See also:

Drawing a Line

Selecting an Object


Changing the Pin Name or Default Value (Graphic Editor)
Changing the Pin Name or Default Value

To change the pin name for INPUT, INPUTC, OUTPUT, OUTPUTC, BIDIR, and BIDIRC primitives:

1.	Press Button 2 on the pin and choose Edit Pin Name from the pop-up menu or use a shortcut.

2.	Type a new pin name with up to 32 name characters.

3.	If you wish to allow the Graphic Editor to automatically select the pin name of the next pin for editing, press Enter.

To change the pin default values assigned to unconnected INPUT, INPUTC, BIDIR, and BIDIRC primitives:

1.	Press Button 2 on the pin and choose Edit Pin Default Value from the pop-up menu or use a shortcut.

2.	Type VCC or GND as the new default value.

3.	If you wish to allow the Graphic Editor to automatically select the default value of the next pin for editing, press Enter.

You can edit the pin name or default value text field, but cannot leave the field empty.

See also:

Bus Names

Selecting Text


Changing the Pinstub Name & I/O Type (Symbol Editor)
Changing the Pinstub Name & I/O Type

To change a pinstub name:

1.	Press Button 2 on the pinstub name within the symbol border and choose Edit Selected Text from pthe pop-up menu or use a shortcut.

2.	Type new text.

You can edit text in the pinstub name text field but cannot leave the field empty.

To change a pinstub name and/or the pinstub I/O type:

1.	Select the "x" of the pinstub you want to modify and open the Enter Pinstub dialog box by choosing Enter Pinstub (Element menu) or using a shortcut.

2.	Type a name with up to 32 name characters in the Pinstub Name box.

3.	If necessary, select a different pinstub I/O type under I/O Type.

4.	If you wish to see the symbol’s pinstub names when the symbol is used in a GDF or OrCAD Schematic File, turn on Show in Graphic Editor.

5.	Choose OK.

6.	After saving your edits, choose Update Symbol (Symbol menu) in the appropriate Graphic Editor file(s) to update the appearance of the symbol.

Refer to Guidelines for Working with OrCAD Schematic Files for important information on editing symbols in OrCAD Schematic Files.

See also:

Entering & Naming a Pinstub

Selecting Text

Updating a Symbol in a Graphic Editor File


Changing the Symbol Size (Symbol Editor)
Changing the Symbol Size

To increase or reduce the size of a symbol:

1.	Point to the symbol border.

2.	Press Button 1 and drag the border away from or towards the center of the symbol to increase or decrease its size.

3.	After saving your edits, choose Update Symbol (Symbol menu) in the appropriate Graphic Editor file(s) to update the appearance of the symbol.

The pinstubs in a symbol move automatically as you resize the symbol. However, names and other elements within the border do not move automatically. Since the Symbol Editor will not allow you to resize a symbol so that elements are outside the border, you may have to move symbol elements closer together before you decrease the size of a symbol.

Refer to Guidelines for Working with OrCAD Schematic Files for important information on editing symbols in OrCAD Schematic Files.

See also:

Updating a Symbol in a Graphic Editor File


Copying, Cutting & Pasting an Object (Graphic & Symbol Editors)
Copying, Cutting & Pasting an Object

To copy and paste an object:

1.	With the Selection tool ( [image]), select one or more objects to copy. You can use area or object-by-object selection.

2.	Choose Copy (Edit menu) or use a shortcut. The object or selection is placed on the Clipboard.

3.	Click Button 1 to define an insertion point.

4.	Choose Paste (Edit menu) or use a shortcut.

or:

1.	Select one or more objects to copy. You can use area or object-by-object selection.

2.	Press Ctrl and point to a selected object.

3.	Press Button 1 and drag the object(s) to a new location. A copy of the object(s) is created but not placed on the Clipboard.

4.	Release Button 1.

You can also press Ctrl after you have started dragging a selection to change a move operation into a copy operation.

To cut and paste an object:

1.	Select one or more objects to cut. You can use area or object-by-object selection.

2.	Choose Cut (Edit menu) or use a shortcut. The object or selection is placed on the Clipboard.

3.	Click Button 1 to define an insertion point.

4.	Choose Paste or use a shortcut.

The insertion point defines the top left corner of the pasted object(s), i.e., copied or cut objects are pasted to the right and below the insertion point.

Text can be copied or cut and pasted into other MAX+PLUS II files and into different types of text fields. Example

An object can be pasted only if it is compatible with the target file format (i.e., a GDF or Symbol File).

If you paste a symbol into a Graphic Editor file that already contains a different version of that symbol, the appearance of the pasted symbol automatically changes to match the symbol that already exists in the target file. Example

See also:

Copying a Resource Assignment

Copying, Cutting & Pasting Text

Deleting an Object

Moving an Object

Selecting an Object


Deleting an Object (Graphic & Symbol Editors)
Deleting an Object

To delete an object:

1.	Select one or more objects to delete. You can use area or object-by-object selection.

2.	Choose Delete (Edit menu) or use a shortcut.

Delete removes the selection from the file without replacing the contents of the Clipboard. To remove a selection from the file and store it on the Clipboard, you must choose Cut (Edit menu) instead of Delete.

See also:

Copying, Cutting & Pasting an Object

Deleting an Assignment

Deleting Text

Selecting an Object


Drawing a Circle (Graphic & Symbol Editors)
Drawing a Circle

To draw a circle:

1.	Select the Circle tool with Button 1.

2.	Press Button 1 to define an anchor point.

3.	Drag the mouse until the desired diameter has been obtained.

4.	Release Button 1 to finish the circle.

A circle cannot be resized once Button 1 has been released.


Drawing a Line (Graphic & Symbol Editors)
Drawing a Line

To draw a line:

1.	Select the Orthogonal Line or Diagonal Line tool with Button 1.

2.	If necessary, choose the Line Style command (Options menu) or use a shortcut.The current line style for a new line is shown on the toolbar.

3.	Press Button 1 to define an anchor point.

4.	While holding Button 1 down, drag the mouse until the desired length has been obtained. If you wish to form a horizontal and vertical line that meet at a right angle, drag the mouse in a diagonal direction when using the Orthogonal Line tool.

5.	Release Button 1 to finish the line.

If a line starts or ends in a T intersection with another line, a connection dot is entered automatically.

If you draw a new line on top of an existing line with the same style, the two lines are automatically merged.

If you enter or move two symbols so that their borders and pinstubs touch, the symbols become logically connected. If you then move one of the symbols when Rubberbanding (Options menu) is turned on, a new node or bus line forms automatically between the connected pinstubs of the two symbols.

Although the Compiler interprets all line styles as logical connections, Altera recommends using the first style on the Line Style menu for drawing nodes. Buses can only be drawn with the last style on the Line Style menu.

See also:

Changing the Line Style

Deleting an Object

Entering a Connection Dot


Drawing an Arc (Graphic & Symbol Editors)
Drawing an Arc

The Arc tool draws an arc of up to 180°.

To draw an arc:

1.	Select the Arc tool with Button 1.

2.	Press Button 1 to define an anchor point.

3.	While holding Button 1 down, drag the mouse until the desired radius has been obtained.

4.	If you wish to reposition the arc while you are drawing it, click Button 2 to redefine the direction of the tangent line and continue drawing.

5.	Release Button 1 to finish the arc.

You cannot resize an arc once you have released Button 1.

See also:

Deleting an Object


Entering & Naming a Pinstub (Symbol Editor)
Entering & Naming a Pinstub

To enter and name a pinstub:

1.	Click Button 1 on or within the symbol border to define an insertion point and open the Enter Pinstub dialog box by choosing Enter Pinstub (Elements menu) or using a shortcut.

2.	Type a name with up to 32 name characters in the Pinstub Name box. If you are creating or editing a symbol that represents an AHDL TDF, you can omit any single quotes (') in AHDL port names.

3.	If necessary, select a different pinstub I/O type under I/O Type.

4.	If you wish to see the symbol’s pinstub names when the symbol is used in a Graphic Editor file, turn on Show in Graphic Editor.

5.	Choose OK.

6.	After saving your edits, choose Update Symbol (Symbol menu) in the appropriate Graphic Editor file(s) to update the appearance of the symbol.

Refer to Guidelines for Working with OrCAD Schematic Files for important information on editing symbols in OrCAD Schematic Files.

See also:

Changing the Pinstub Name & I/O Type

Pinstubs & Pinstub Names

Selecting Text

Updating a Symbol in a Graphic Editor File


Entering a Connection Dot (Graphic Editor)
Entering a Connection Dot

The fact that two node or bus lines meet at a T intersection or cross over each other does not constitute a logical connection: you must enter a connection dot to create a connection.

To enter or delete a connection dot:

Choose Toggle Connection Dot (Edit menu) on the intersection of two lines or use a shortcut.

Connection dots can also be entered at the ends of an arc.


Entering a Symbol (Graphic Editor)
Entering a Symbol

To enter a symbol:

1.	Click Button 1 to define the insertion point for the symbol and open the Enter Symbol dialog box by choosing Enter Symbol (Symbol menu) or using a shortcut.

2.	If necessary, select a different drive and/or directory in the Directories box or select a library name in the Symbol Libraries box.

3.	Type a symbol name in the Symbol Name box or select a symbol from Symbol Files box.

4.	Choose OK.

1.	If you enter or move two symbols so that their borders and pinstubs touch, the symbols become logically connected. If you then move one of the symbols when Rubberbanding (Options menu) is turned on, a new node or bus line forms automatically between the connected pinstubs of the two symbols.

2.	If you enter a symbol into a Graphic Editor file that already contains a different version of that symbol, the appearance of the symbol you enter automatically changes to match the symbol that already exists in the target file. Example

See also:

Creating the Default Symbol for a File

Editing the Symbol for a File

Macrofunctions

Primitives

Specifying a User Library

Updating a Symbol in a Graphic Editor File


Finding a Node Source or Destination (Graphic Editor)
Finding a Node Source or Destination

To find the source or destination of a node or bus:

1.	With the Selection tool ( [image]) or a Line Drawing tool ( [image]), select a segment of a node or bus line. You can select multiple segments if they belong to the same node or bus.

2.	Choose Find Node Source (Utilities menu) or use a shortcut.The entire network of wires is highlighted, including portions of the net that are connected by name only and the symbol that feeds the selected node or bus.

or:

Choose Find Node Destination (Utilities menu) or use a shortcut. The entire network of wires is highlighted, including portions of the net that are connected by name only and the first symbol that is fed by the selected node or bus.

3.	Choose Find Next (Utilities menu) to locate the next source or destination symbol (if any) or use a shortcut. It is not necessary to reselect the node or bus to continue finding destinations. Continue choosing Find Next to locate all destinations.

4.	To locate a previous source or destination, choose Find Previous (Utilities menu) or use a shortcut.

See also:

Selecting an Object


Flipping a Selection (Graphic & Symbol Editors)
Flipping a Selection

To flip an object-by-object or area selection horizontally or vertically:

1.	With the Selection tool ( [image]), select one or more objects to flip.

2.	Choose Flip Horizontal or Flip Vertical (Edit menu) or use a shortcut.

Each symbol in an object-by-object selection is individually flipped along its horizontal or vertical axis. If you are flipping an area selection, the entire selection is flipped along its horizontal or vertical axis.

All text fields inside a symbol are moved to reflect its new orientation. The location of resource assignments on a symbol does not change when the symbol is flipped; e.g., clique assignments are always on the top left corner of a symbol. Probes flip with the symbol to maintain the attachment to the pinstubs to which they are assigned.

Connectivity between a flipped symbol and the surrounding logic is not maintained, even if Rubberbanding (Options menu) is turned on.

See also:

Moving an Object

Rotating a Selection

Selecting an Object


Moving an Object (Graphic & Symbol Editors)
Moving an Object

To move one or more objects:

1.	With the Selection tool ( [image]), select one or more objects. You can use area or object-by-object selection.

2.	Point to an object in the selection.

3.	Press Button 1.

4.	Drag the selection to a new location.

5.	Release Button 1.

To maintain connectivity between the moved objects and the surrounding logic, turn rubberbanding on before moving the objects. You can turn rubberbanding on or off by choosing the Rubberbanding command (Options menu). Rubberbanding is not available for arcs that connect symbols or other objects.

If you move two symbols so that their borders and pinstubs touch, the two symbols become logically connected. If you then move one of the symbols with Rubberbanding turned on, a line forms automatically between the connected pinstubs.

See also:

Copying, Cutting & Pasting an Object

Deleting an Object

Moving a Probe or Resource Assignment

Selecting an Object


Naming a Node or Bus (Graphic Editor)
Naming a Node or Bus

To assign a name to a node or bus:

1.	Click Button 1 on the node or bus line you wish to name. An insertion point appears to show where the name will be inserted.

2.	Type a node or bus name with up to 32 name characters.

or:

1.	Press Button 2 on a node or bus and chose Edit Node/Bus Name to define an insertion point.

2.	Type a node or bus name with up to 32 name characters.

or:

1.	Click Button 1 in a blank space to define an insertion point.

2.	Type a node or bus name with up to 32 name characters.

3.	With the Selection tool, select and drag the name onto a node or bus line.

To edit a node or bus name:

1.	Double-click Button 1 on the node or bus name to select it.

2.	Type new text for the node or bus name.

or:

Press Delete to delete the node or bus name.

3.	If you wish to automatically select the next node or bus name for editing, press Enter.

Nodes can be logically connected by name only; they need not be physically connected. Nodes are logically connected when their names are identical. Example

Compiler-generated pin names that contain the tilde (~) character may appear in the Fit File for a project. The tilde character is reserved for Compiler-generated names only; you cannot use it in your own pin, node, and group (bus) names.

See also:

Bus Names

Pin & Node Names

Ripping & Merging a Bus

Selecting an Object

Recommended reading:

AB92 (Simulating Internal Nodes with MAX+PLUS II Software)


Ripping & Merging a Bus (Graphic Editor)
Ripping & Merging a Bus

During bus ripping, one bus is divided into two or more separate buses. Each node name within the new bus names must be a node that also exists in the original bus.

To rip a bus into two or more buses:

1.	Determine the number of buses required.

2.	Draw the new bus lines.

3.	If you wish, connect the new buses to the original bus. Buses can be logically connected by name only; a physical connection is optional.

4.	Select and name each new bus.

Conversely, two or more buses can be merged to form one bus. The name of the new bus must include each node name within the original buses.

To merge two or more buses:

1.	Connect the buses that will be merged. Buses can be logically connected by name only; a physical connection is optional.

2.	Draw the new bus line.

3.	If you wish, connect the new bus to the original buses.

4.	Select and name the new bus.

See also:

Bus-to-Macrofunction Connections

Changing the Line Style

Drawing a Line

Entering a Connection Dot

Primitive Arrays

Naming a Node or Bus

Selecting an Object


Rotating a Selection (Graphic & Symbol Editors)
Rotating a Selection

To rotate an object-by-object selection or area selection:

1.	Select one or more objects to rotate.

2.	Choose Rotate 90°, Rotate 180°, or Rotate 270° (Edit menu) or use a shortcut.

Each symbol or text block in an object-by-object selection is individually rotated around its center. If you are rotating an area selection, the entire selection is rotated around its center.

All text fields inside a symbol are moved to reflect its new orientation. The location of resource assignments on a symbol does not change when the symbol is rotated; e.g., clique assignments are always on the top left corner of a symbol. Probes rotate with the symbol to maintain the attachment to the pinstubs to which they are assigned.

Connectivity between a rotated symbol and the surrounding logic is not maintained, even if Rubberbanding (Options menu) is turned on.

See also:

Flipping a Selection

Moving an Object

Selecting an Object


Selecting an Object (Graphic & Symbol Editors)
Selecting an Object

In the Graphic and Symbol Editors, two types of selection are available: area selection and object-by-object selection. Objects are selected with Button 1 and additional keys.

To select a single object:

With the Selection tool ( [image]), click Button 1 on the object.

To select an area, point to an empty space with the Selection tool ( [image]) and use one of the following mouse/key combinations:

Mouse/Key:	Action:

Press, Drag, Release	Selects all objects from the point where Button 1 is pressed to the point where it is released. You must press Button 1 over a blank space; otherwise, you will move the selected object instead of selecting an area.

Click, Move, Shift+Click	Selects all objects between the first click and the Shift+Click.

The area is denoted by the area marquee that surrounds it. The portion of an orthogonal line that lies within the area marquee is selected; all other objects and diagonal lines must be fully within the marquee to be selected.

To select more than one discontiguous object, use one of the following mouse/key combinations:

Mouse/Key:	Action:

Double-Click	Selects the entire network of lines that are physically connected to the line that is under the mouse pointer. To select the entire network of lines connected to the selected line or node, including lines connected by name only, choose one of the following Utilities menu commands:

Find Node Source or a shortcut

Find Node Destination or a shortcut

Shift+Click	Selects a single object and adds it to a previous selection.

Shift+Press, Drag, Release	Selects all objects from the point where Button 1 is pressed to the point where it is released and adds the objects to an existing selection, if any.

Objects that cross a selection boundary are also selected. A selection boundary is not visible after objects are selected.

You can mix area and object-by-object selection. However, adding additional objects to an area selection will change it to a object-by-object selection.


Selecting a Node Network (Graphic Editor)
Selecting a Node Network

To select an entire network of node or bus lines:

Double-click Button 1 on a node.

The entire network of lines is highlighted, but does not include portions of the network that are connected by name only. To trace an entire network of lines, including portions of the network that are connected by name only, choose one of the following Utilities menu commands:

Find Node Source or a shortcut

Find Node Destination or a shortcut

See also:

Finding a Node Source or Destination

Selecting an Object


Selecting a Pinstub (Graphic & Symbol Editors)
Selecting a Pinstub

To select a pinstub in the Symbol Editor:

With the Selection tool ( [image]), click Button 1 on the pinstub "x."

To select a pinstub in the Graphic Editor before entering or moving a probe:

With the Selection tool [image], click Button 1 inside the symbol border near the pinstub before choosing Probe (Assign menu). The symbol, as well as the pinstub within it, is selected.

See also:

Assigning a Probe

Changing the Pinstub Name & I/O Type

Deleting an Object

Moving a Probe or Resource Assignment

Selecting an Object


Turning Rubberbanding On or Off (Graphic & Symbol Editors)
Turning Rubberbanding On or Off

When rubberbanding is on, you can move any symbol(s) or an area while preserving signal connectivity. Connectivity is retained for orthogonal and diagonal node and bus lines that end on a symbol pinstub or pass through an area marquee, regardless of where the symbol(s) or area is moved.

Rubberbanding does not occur for arcs that connect symbols or other objects, or when a selection is flipped or rotated.

To turn rubberbanding on or off:

Choose Rubberbanding (Options menu) or use a shortcut.


Updating a Symbol in a Graphic Editor File (Graphic Editor)
Updating a Symbol in a Graphic Editor File

When you edit a symbol or when you change the inputs and outputs of the design file that the symbol represents, instances of that symbol that have been entered in a GDF or OrCAD Schematic File need to be updated to the new version. Updating symbols ensures that the file will compile properly.

To update all the symbols in a Graphic Editor file:

1.	Choose Update Symbol (Symbol menu). The Update Symbol dialog box is displayed.

2.	Select All Symbols in the File.

3.	Choose OK.

To update one or more symbols in a Graphic Editor file:

1.	With the Selection tool ( [image]), select the symbol(s) you wish to update.

2.	Choose Update Symbol. The Update Symbol dialog box is displayed.

3.	Select All Occurrences of Selected Symbol(s).

4.	Choose OK.

Refer to Guidelines for Working with OrCAD Schematic Files for important information on editing symbols in OrCAD Schematic Files.

See also:

Selecting an Object


Changing the Text Size (Graphic & Symbol Editors)
Changing the Text Size

To change the size of selected text:

1.	Select one or more text blocks with Button 1.

2.	Choose Text Size (Options menu) and select a size from the submenu or use a shortcut.

All selected text is changed to the specified size.

To set the text size for new text entries:

1.	Click Button 1 in a blank space in the window to ensure that no text is selected.

2.	Repeat step 2 above.

All text entered will appear in the specified text size. The Text Size drop-down list box on the toolbar displays the current text size for new text entries.

See also:

Changing the Font

Selecting an Object


Changing the Font (Graphic & Symbol Editors)
Changing the Font

To change the font of a selected text block:

Choose Font (Options menu) and select a font from the submenu or use a shortcut.

All selected is changed to the specified font. The Font drop-down list box on the toolbar displays the current font for new text entries.

See also:

Changing the Text Size


Entering a Text Block [Comment] (Graphic & Symbol Editors)
Entering a Text Block (Comment)

A comment is a block of text used to document a file. A comment is not logically associated with any object within the symbol border of a Symbol File or anywhere in a GDF or OrCAD Schematic File. Comments can be used to provide information about various sections of a file and are ignored by the Compiler.

To enter a comment:

1.	Click Button 1 in a blank space to define an insertion point.

2.	Type the desired text.

3.	To start another comment under the current comment, press Enter.

You can change a comment into a node or bus name by selecting the comment and dragging it onto a node or bus line.

When you are editing a comment, pressing Enter selects the next comment below the current comment in the file.

See also:

Naming a Node or Bus


Finding Text (Graphic & Symbol Editors)
Finding Text

To find a specific string of text:

1.	If necessary, adjust your on-screen display by choosing one of the following View menu commands:

Normal Sizege_com_zoom or a shortcut

Maximum Sizege_com_zoom or a shortcut

Text may not be visible at other display scales.

2.	(Graphic Editor only) If necessary, turn on Show All (Options menu) or use a shortcut to ensure that any previously hidden assignment text can be found. Find Text searches only for visible text, so Show All must be turned on to find assignments.

3.	Move the insertion point to define where the search will begin or select the text you wish to search for.

4.	Open the Graphic Editor Find Text dialog box or the Symbol Editor Find Text dialog box by choosing Find Text (Graphic Editor) or Find Text (Symbol Editor) (Utilities menu) or using a shortcut. If you selected text in step 3 or if you entered text in another editor’s Find Text dialog box, the text appears as the default search text in the Search For box.

5.	If you did not select text in step 3, type the search text in the Search For box, including optional wildcard characters. If you use the * wildcard character, the Whole Word option is turned on automatically.

6.	If you wish, turn on one or more of the following options:

Option:	Action:

Whole Word 	Finds occurrences of the search text that are whole words only.

Pause at End	Pauses the search at the end of the file.

Node & Bus Names	(Graphic Editor) Finds only the text that occurs in node or bus names.

Text in Symbols	(Graphic Editor) Finds only the editable text that occurs within a symbol, e.g., a symbol name.

Comments	(Graphic Editor) Finds only the text that occurs in comments.

All 	(Graphic Editor) Finds all occurrences of the specified search text.

7.	Select Up or Down under Direction to search up or down within the file.

8.	Choose OK to begin the search.

9.	If you wish to find the next or previous occurrence of the search text after the first occurrence has been found, choose Find Text, Find Next, or Find Previous (Utilities menu).

See also:

Finding & Replacing Text

Selecting Text


Finding & Replacing Text (Graphic & Symbol Editors)
Finding & Replacing Text

To find and replace text:

1.	If necessary, choose Normal Size or Maximum Size (View mwnu). Text may not be visible at other display scales.

2.	In the Graphic Editor, turn on Show All (Options menu) to ensure that any previously hidden assignment text can be found. Search & Replace searches only for visible text.

3.	Move the insertion point to define where the search will begin or select the text you wish to search for.

4.	Open the Graphic Editor Search & Replace dialog box or the Symbol Editor Search & Replace dialog box by choosing Search & Replace (Graphic Editor) or Search & Replace (Symbol Editor). (Utilities menu) or using a shortcut. If you selected text in step 3 or if you entered text in another editor’s Find Text dialog box, the text appears as the default search text in the Search For box.

5.	If you did not select text in step 3, type the search text in the Search For box, including optional wildcard characters. If you use the * wildcard character, the Whole Word option is turned on automatically.

6.	Type the new text in the Replace With box.

7.	If you wish, turn on one or more of the following options:

Option:	Action:

Whole Word 	Finds occurrences of the search text that are whole words only.

Confirm Each Change	Specifies that the Graphic or Symbol Editor must ask before replacing an occurrence of the search text.

Pause at End	Pauses the search at the end of the file.

Node & Bus Names	(Graphic Editor) Finds only the text that occurs in node or bus names.

Editable Text in Symbols	(Graphic Editor) Finds only the editable text that occurs within a symbol, e.g., a symbol name.

Comments	(Graphic Editor) Finds only the text that occurs in comments.

All 	(Graphic Editor) Finds occurrences of the specified search text that occur in all locations.

8.	Select Up or Down under Direction to search up or down within the file.

9.	Choose OK to begin the search.

10.	If you wish to find the next or previous occurrence of the search text after the first occurrence has been found, choose one of the following Utilities menu commands:

Find Text (Graphic Editor) or a shortcut

Find Text (Symbol Editor) or a shortcut

Find Next or a shortcut

Find Previous or a shortcut

If the search text is located and the Confirm Each Change option is turned on, a dialog box opens and asks whether you wish to replace the selection. Choose one of the following options:

Button/Option:	Action:

Confirm Each Change	Specifies whether the Graphic Editor will ask before replacing an occurrence of the search text. If you turn this option off, all occurrences are replaced.

Yes	Replaces the currently selected search text, then continues the search.

No	Leaves the currently selected search text unchanged, but continues the search.

Cancel	Ends the search.

See also:

Finding Text

Selecting Text


Fitting a File into the Window (Graphic & Symbol Editors)
Fitting a File into the Window

To view the entire file:

Choose Fit in Window. (View menu) or use a shortcut.

Fit in Window changes the display scale to fit the entire file, including the drawing sheet border, in the current window.

See also:

Zooming In & Out


Zooming In & Out (Graphic & Symbol Editors)
Zooming In & Out

To change the view of the file, select one of the following buttons or View menu commands:

Button/Command:	Action:

Fit in Window command	Zooms out to fit the entire file, including the drawing sheet border, in the current window. Shortcuts.

Zoom In button	Increases the scale of the objects displayed, showing a smaller portion of the file. When you reach the maximum enlargement, the button is dimmed and is no longer available. Shortcuts.

Zoom Out button	Reduces the scale of the objects displayed, showing a greater portion of the file. When you reach the maximum reduction, the button is dimmed and is no longer available. Shortcuts.

Normal Size command	Zooms in to display objects at normal (full) size. Shortcuts.

Maximum Size command	Zooms in to display objects at maximum size. Shortcuts.

When you use the keyboard shortcuts for the View commands, you can zoom as you are selecting, moving, or drawing an object or area.

See also:

Fitting a File into the Window


Primitives (all editor applications)
Primitives

MAX+PLUS II provides a variety of primitive functions for circuit design. Since AHDL and VHDL logical operators, ports, and some statements replace primitives in AHDL and VHDL files, AHDL and VHDL primitives are a subset of those available for GDFs, as shown below.

Primitive Arrays

Primitive/Port Interconnections

Unused Inputs to Primitives & Macrofunctions

Buffer Primitives

CARRY	OPNDRN

CASCADE	SOFT

EXP	TRI

GLOBAL  (SCLK)	WIRE (GDFs only)

LCELL  (MCELL)

Flipflop & Latch Primitives

DFF	SRFF

DFFE	SRFFE

JKFF	TFF

JKFFE	TFFE

LATCH

Input & Output Primitives/Ports

BIDIR or INOUT	BIDIRC (GDFs only)

INPUT or IN	INPUTC (GDFs only)

OUTPUT or OUT	OUTPUTC (GDFs only)

Logic Primitives (GDFs only)

AND	NOR

BAND	NOT

BNAND	OR

BNOR	VCC

BOR	XNOR

GND	XOR

NAND

Title Block (GDFs only)

1.	AHDL Function Prototypes are not needed for primitives in TDFs. However, you can redefine the calling order of the primitive inputs by including a Function Prototype Statement in your TDF.

2.	VHDL does not support macrofunctions, primitives, or ports with names that are VHDL keywords or that begin with a number, e.g., 74-series macrofunctions. To use these functions in a VHDL Design File, see Using a MAX+PLUS II Macrofunction or Primitive.


Primitive/Port Interconnections

Not all primitives/ports may connect to all other primitives in a design file. The following lists show the possible interconnections for all primitives/ports except logic primitives:

Source	|	Destination

|

|

|	OUTPUT/	OUTPUTC	BIDIR/	BIDIRC	TRI	GLOBAL	LCELL	EXP	SOFT	Logic	INPUT/	INPUTC	CARRY	CASCADE	OPNDRN

|	OUT	INOUT	Note (1)	IN(2)

|

INPUT	|	Y	Y	N	N	Y	Y	na	na	na	Y	Y	Y	na	na	Y

  or IN	|

INPUTC	|	Y	Y	N	N	Y	Y	na	na	na	Y	Y	Y	na	na	Y

OUTPUT(3)	|	N	N	N	N	N	N	N	N	N	N	N	N	na	na	N

  or OUT	|

OUTPUTC(3)	|	N	N	N	N	N	N	N	N	N	N	N	N	na	N

BIDIR(3)	|	N	N	N	N	Y	N	na	na	na	Y	Y	Y	na	na	Y

  or INOUT	|

BIDIRC(3)	|	N	N	N	N	Y	N	na	na	na	Y	Y	Y	na	na	Y

TRI	|	Y	Y	Y	Y	N(4)	na	N(4)	N(4)	N(4)	N(4)	N(4)	N(4)	na	na	N(4)

GLOBAL(5)	|	na	na	N	N	(6)	Y	na	na	na	na	na	na	Y	na	na

LCELL(7)	|	Y	Y	N	N	Y	na	na	na	na	Y	na	na	na	na	Y

EXP	|	na	na	N	N	na	N	na	na	na	Y	na	na	na	na	na

SOFT	|	Y	Y	N	N	na	N	na	na	na	Y	na	na	na	na	na

VCC	|	Y	Y	N	N	Y	N	na	na	na	Y	Y	Y	na	na	Y

GND	|	Y	Y	N	N	Y	N	na	na	na	Y	Y	Y	na	na	Y

Logic	|	Y	Y	N	N	Y	N	Y	Y	Y	Y	Y	Y	Y	Y	Y

Reg Out	|	Y	Y	N	N	Y	N	na	na	Y	Y	Y	Y	na	na	Y

CARRY	|	na	na	na	na	na	na	Y	na	na	Y	na	na	na	na	na

CASCADE	|	na	na	na	na	na	na	na	na	na	Y	na	na	na	na	na

OPNDRN	|	Y	Y	Y	Y	N(4)	na	N(4)	N(4)	N(4)	N(4)	N(4)	N(4)	na	na	N(4)

Source	|	Register

|

|	CLK	PRN	CLRN

|

INPUT	|	Y	Y	Y

  or IN	|

INPUTC	|	Y	Y	Y

OUTPUT(3)	|	N	N	N

  or OUT	|

OUTPUTC(3)	|	N	N	N

BIDIR	|	Y	Y	Y

  or INOUT	|

BIDIRC	|	Y	Y	Y

TRI	|	N(4)	N(4)	N(4)

GLOBAL(5)	|	Y	Y	Y

LCELL(7)	|	Y	Y	Y

EXP	|	na	na	na

SOFT	|	Y	Y	Y

VCC	|	N	Y	Y

GND	|	N	Y	Y

Logic	|	Y	Y	Y

Reg Out	|	Y	Y	Y

CARRY	|	na	na	na

CASCADE	|	na	na	na

OPNDRN	|	N(4)	N(4)	N(4)

Legend:

Y	Interconnection is legal.

N	Interconnection is illegal.

na	Interconnection is legal but not advisable or may implement logic inefficiently.

Notes:

(1)	Includes both data and Output Enable inputs to TRI.

(2)	The INPUT or IN primitive/port can only be fed by device pins or higher levels in the hierarchy.

(3)	The OUTPUT (or OUT), OUTPUTC, and BIDIR (or INOUT), and BIDIRC primitives/ports can only drive out to device pins or higher levels in the hierarchy.

(4)	These connections change to legal (Y) or not advisable (na) only if the output of the TRI or OPNDRN is also connected to a BIDIR/INOUT or BIDIRC primitive/port.

(5)	SCLK in MAX+PLUS (DOS) designs is interpreted as GLOBAL. New projects should only use GLOBAL.

(6)	Connecting a GLOBAL output to the TRI Output Enable input is legal in FLEX 8000 and FLEX 10K devices. Connections to Output Enable in other devices are ignored.

(7)	MCELL in pre-version 3.0 MAX+PLUS II design files is interpreted as LCELL. New projects should only use LCELL.

See also:

Unused Inputs to Primitives & Macrofunctions


Unused Inputs to Primitives & Macrofunctions

The following rules apply to unconnected input ports on primitive and macrofunction symbols and instances.

Unused inputs to flipflop primitives have the following defaults:

CLRN:	VCC (inactive)

PRN:	VCC (inactive)

ENA:	VCC (active)

The data and Clock inputs to flipflops and the data and ENA inputs to latches are required.

An unused OE input to a TRI buffer defaults to VCC (active, output enabled).

Unused inputs to logic primitives in Graphic Editor files must be connected to VCC or GND.

The default logic levels for unused inputs to macrofunctions are documented in the Help for each macrofunction.

See also:

Primitives

Primitive Arrays

Primitive/Port Interconnections

Specifying Global Project Logic Synthesis Settings

Macrofunctions (by function)

Macrofunctions (by number)


CARRY Primitive

Function Prototype: 	FUNCTION CARRY (in)

                       RETURNS (out);

The CARRY primitive designates the carry-out logic for a function, and acts as the carry-in to another function. The carry function implements fast carry-chain logic for functions such as adders and counters.

The CARRY primitive is supported only for the FLEX 8000 and FLEX 10K device families; it is ignored for other devices.

When you use a CARRY primitive, you must observe the following rules:

A CARRY primitive can feed one or two cones of logic. If the CARRY primitive feeds two cones of logic, then one and only one of the cones of logic must be buffered by another CARRY primitive. In this case, both cones of logic are implemented in the same logic cell. You must follow this rule to tie down the sum and carry-out functions for the first stage of an adder or counter.

A cone of logic fed by a CARRY primitive can have up to two inputs. A third input is allowed only if it is a CARRY input.

A cone of logic that feeds a CARRY primitive can have up to two inputs. A third input is allowed only if it is a CARRY input.

The CARRY primitive cannot feed an OUTPUT or OUTPUTC pin.

The CARRY primitive cannot be fed by an INPUT or INPUTC pin or a register.

Two CARRY primitives cannot feed the same gate.

If you use the CARRY primitive incorrectly, it is ignored and the Compiler issues a warning.

You can allow the Compiler to automatically insert or remove CARRY primitives during logic synthesis with the Carry Chain logic option or a logic synthesis style that includes the Carry Chain option.

Multi-level synthesis may implement a FLEX 8000 or FLEX 10K register in the counter mode even if it is not fed by a CARRY buffer. To prevent a register that is not explicitly fed by a CARRY buffer from using the counter mode, set the Carry Chain option to IGNORE for that register. If the register is explicitly fed by a CARRY buffer, you must also set the Carry Chain option to IGNORE on the CARRY buffer.

The following example shows a register implemented in counter mode without a carry chain input:

q   = dff ( (eqn & load # data & !load ) & clear, ... );

eqn = q & !ena # !q & ena;

See also:

Assigning an Individual Logic Option or Synthesis Style

Primitive/Port Interconnections

Specifying Global Project Logic Synthesis Settings

Unused Inputs to Primitives & Macrofunctions


CASCADE Primitive

Function Prototype: 	FUNCTION CASCADE (in)

RETURNS (out);

The CASCADE buffer designates the cascade-out function from an AND or OR gate, and acts as a cascade-in to another AND or OR gate. The cascade-in function allows a cascade, which is a fast output located on each combinatorial logic cell, to be ORed or ANDed with the output of an adjacent combinatorial logic cell in the device. With the CASCADE primitive, the AND or OR gate that feeds the CASCADE primitive and the AND or OR gate that is fed by the CASCADE primitive are placed in the device, with the first symbol logically ORed or ANDed into the second.

The CASCADE primitive is supported only for the FLEX 8000 and FLEX 10K device families; it is ignored for other devices.

When you use a CASCADE primitive, you must observe the following rules:

A CASCADE primitive can only feed or be fed by a single gate, which must be an AND or an OR gate.

An inverted OR gate is treated as an AND gate and vice-versa. Logical equivalents of AND gates are BAND, BNAND, and NOR. Logical equivalents of OR gates are BOR, BNOR, and NAND.

Two CASCADE primitives cannot feed the same gate.

A CASCADE primitive cannot feed an XOR gate.

A CASCADE primitive cannot feed an OUTPUT or OUTPUTC pin primitive or a register.

The De Morgan’s inversion theorem implementation of cascaded AND and OR gates requires all primitives in a cascaded chain to be of the same type. A cascaded AND gate cannot feed a cascaded OR gate, and vice-versa.

If you use the CASCADE primitive incorrectly, it is ignored and the Compiler issues a warning.

You can allow the Compiler to automatically insert or remove CASCADE primitives during logic synthesis with the Cascade Chain logic option or a logic synthesis style that includes the Cascade option.

See also:

Assigning an Individual Logic Option or Synthesis Style

Primitive/Port Interconnections

Specifying Global Project Logic Synthesis Settings

Unused Inputs to Primitives & Macrofunctions


EXP Primitive

Function Prototype: 	FUNCTION EXP (in)

RETURNS (out);

The EXP expander buffer specifies that an expander product term is desired in the project. The expander product is inverted in the device.

The EXP primitive is supported only for the MAX5000, MAX 7000, and MAX9000 device families; it is treated as a NOT gate in other device families. Refer to individual device data sheets for information on how specific devices use logic cells and expander product terms.

Whether or not an expander product term is used depends on the logic polarity required by the destination functions. For example, if an EXP buffer feeds two AND gates (i.e., product terms) and the second AND gate has a inverted input, the EXP feeding the inverted input is removed during logic synthesis, thereby creating positive logic. The EXP feeding the non-inverted input is not removed and the expander product term is used to implement logic. (Normally, the Logic Synthesizer determines where to insert or remove EXP buffers. Altera recommends that only experienced MAX+PLUS II designers should use the EXP primitive in their projects.)

In devices that contain multiple LABs, the EXP buffer output can only feed logic within a single LAB. The EXP is duplicated for each LAB that requires it. If a project contains a large number of expanders, the Logic Synthesizer may convert them into LCELL buffers to balance expander product term and logic cell usage.

Do not use EXP primitives to create an intentional delay or asynchronous pulse. The delay of these elements varies with temperature, power supply voltage, and device fabrication process, so race conditions can occur and create an unreliable circuit.

See also:

Devices & Adapters

Primitive/Port Interconnections

Race Condition Guidelines

Unused Inputs to Primitives & Macrofunctions

Using MAX+PLUS II Buffer & Expander Primitives in a Third-Party Design Editor

Recommended reading:

AB77 (Fitting Complex Designs in MAX 5000 EPLDs)

AN26 (EPLD/MPLD Design Guidelines)


GLOBAL (SCLK) Primitive
GLOBAL Primitive

Function Prototype:	FUNCTION GLOBAL (in)

RETURNS (out);

The GLOBAL buffer indicates that a signal must use a global (synchronous) Clock, Clear, Preset, or Output Enable signal, instead of signals generated with internal logic or driven by ordinary I/O pins. Global signals are used in different device families according to global signal availability.

The SCLK buffer is available for backward compatibility and can be used in place of a GLOBAL primitive only to specify a global Clock in Classic and MAX 5000 devices. SCLK may be used to request global clocking of a register when the Clock is driven by a pin. A direct connection must exist from the input pin to SCLK to the register.

The GLOBAL primitive is ignored for devices that do not support it. In addition, global and array clocking are not allowed within the same LAB in MAX 5000 devices.

If an input pin feeds directly to the input of GLOBAL, the output of GLOBAL can be used to feed a Clock, Clear, Preset, or Output Enable input to a primitive. A direct connection must exist from the output of GLOBAL to the input of the register or the TRI buffer. A NOT gate may be required between the input pin and GLOBAL when the GLOBAL buffer feeds the Output Enable input of a TRI buffer.

A single input may pass through GLOBAL before feeding the Clock, Clear, or Preset input of a register, or the Output Enable input of a TRI buffer.

Global signals propagate more quickly than array signals and may free up device resources for other logic. GLOBAL should be used to implement global clocking in a portion or all of the project. To verify that registers are globally clocked, you can refer to the Report File for the processed project.

If your MAX 5000 device project contains global and array (asynchronous) clocking and the Fitter module of the Compiler cannot find a fit, removing the GLOBAL buffer may make a fit possible. If you encounter a similar problem with a MAX 7000 project, replace array clocking with global clocking.

As an alternative to using the GLOBAL primitive, you can direct the Compiler to automatically select an existing signal in a project to be a global Clock, Clear, Preset, or Output Enable signal with the Global Project Logic Synthesis command (Assign menu).

See also:

Clock Configuration Guidelines

Preset & Clear Configuration Guidelines

Master Reset Guidelines

Primitive/Port Interconnections

Report File Format

Specifying Global Project Logic Synthesis Settings

Unused Inputs to Primitives & Macrofunctions

Using MAX+PLUS II Buffer & Expander Primitives in a Third-Party Design Editor

Recommended reading:

AN26 (EPLD/MPLD Design Guidelines)

AB87 (Troubleshooting Functional Problems in EPLDs)

AB94 (Solutions to Design Timing Problems for Altera EPLDs)

AB143 (Understanding FLEX 8000 Timing)

AB144 (Understanding MAX 9000 Timing)

AN42 (Metastability in Altera Devices)


Global Signal Availability (pop-up)
Global Signal Availability

Classic	MAX 5000	MAX 7000/	FLEX 8000	MAX 9000	FLEX 10K

MAX 7000E

Global Clock

Global Clear	 (1)

Global Preset	 (1)

Global Output Enable	 (1)

Note:

(1)	Available for EPS464 devices only.


LCELL (MCELL) Primitive
LCELL Primitive

Function Prototype: 	FUNCTION LCELL (in)

RETURNS (out);

The LCELL buffer allocates a logic cell for the project. The LCELL buffer produces the true and the complement of a logic function and makes both available to all logic in the device. (The output of the LCELL buffer must feed through a NOT gate to use the complement of the logic function.)

The MCELL buffer, which has the same functionality as the LCELL buffer, is available for backward compatibility with earlier versions of MAX+PLUS II. New projects should use LCELL exclusively.

An LCELL buffer always consumes one logic cell. It is not removed from a project during logic synthesis.

Do not use LCELL primitives to create an intentional delay or asynchronous pulse. The delay of these elements varies with temperature, power supply voltage, and device fabrication process, so race conditions can occur and create an unreliable circuit.

In standard logic synthesis, combinatorial feedback from a logic cell to itself is illegal unless an LCELL buffer is used. The Logic Synthesizer detects illegal combinatorial feedback and issues an error message when a project is compiled with standard synthesis. If you use multi-level synthesis, the Logic Synthesizer automatically inserts an LCELL buffer.

You can use the Compiler’s Fitter Settings command (Processing menu) to direct the Compiler to automatically insert LCELL buffers into a project if they are needed to achieve a fit when user-defined resource and device assignments would otherwise prevent a project from fitting.

See also:

Fitting & Refitting a Project (Compiler)

Implementing LCELL & SOFT Primitives (AHDL)

Primitive/Port Interconnections

Race Condition Guidelines

SOFT Primitive

Unused Inputs to Primitives & Macrofunctions

Using MAX+PLUS II Buffer & Expander Primitives in a Third-Party Design Editor

Recommended reading:

AN26 (EPLD/MPLD Design Guidelines)

AB9 (Asynchronous Latches in Classic, MAX & STG EPLDs)

AB60 (Estimating a Design Fit)

AB77 (Fitting Complex Designs in MAX 5000 EPLDs)

AB93 (Partitioning a Project with MAX+PLUS II Software)

AB143 (Understanding FLEX 8000 Timing)

AB144 (Understanding MAX 9000 Timing)

AN42 (Metastability in Altera Devices)


SOFT Primitive

Function Prototype: 	FUNCTION SOFT (in)

RETURNS (out);

The SOFT buffer specifies that a logic cell may be needed in the project. During project processing, the Logic Synthesizer examines the logic feeding the primitive and determines whether a logic cell is needed. If it is needed, the SOFT buffer is converted into an LCELL; if not, the SOFT buffer is removed.

If the Compiler indicates that the project is too complex, you can edit the project by inserting SOFT buffers to prevent logic expansion. For example, you can add a SOFT buffer at the combinatorial output of a logic function to decouple two combinatorial circuits. You can also include the SOFT Buffer Insertion logic option in the default logic synthesis styles for a project to allow the Compiler to insert SOFT buffers automatically.

See also:

Defining a Logic Synthesis Style

Implementing LCELL & SOFT Primitives (AHDL)

Primitive/Port Interconnections

Specifying Global Project Logic Synthesis Settings

Unused Inputs to Primitives & Macrofunctions

Using MAX+PLUS II Buffer & Expander Primitives in a Third-Party Design Editor

Recommended reading:

AN17 (Integrating an Intelligent I/O Subsystem with a Single EPM5130 MAX EPLD)

AB60 (Estimating a Design Fit)

AB77 (Fitting Complex Designs in MAX 5000 EPLDs)


TRI Primitive

Function Prototype: 	FUNCTION TRI (in, oe)

RETURNS (out);

The TRI primitive is a tri-state buffer with an input, output, and Output Enable signal. If the Output Enable input to the TRI buffer is high, the output will be driven by the Input.

The Output Enable defaults to VCC.

If the Output Enable of a TRI buffer is connected to VCC or a logic function that will minimize to true, a TRI buffer may be converted into a SOFT buffer during logic synthesis.

When you use a TRI buffer, you must observe the following rules:

A TRI buffer may drive only one BIDIR or BIDIRC pin. You must use a BIDIR or BIDIRC pin if feedback is included after the TRI buffer.

If a TRI buffer feeds logic, it must also feed a BIDIR or BIDIRC pin. If it feeds a BIDIR or BIDIRC pin, it may not feed any other outputs.

See also:

OPNDRN Primitive

BTRI Macrofunction

Primitive/Port Interconnections

Unused Inputs to Primitives & Macrofunctions


OPNDRN Primitive

Function Prototype: 	FUNCTION OPNDRN (in)

RETURNS (out);

The OPNDRN primitive is similar to a TRI primitive, with a single input and a single output. The OPNDRN primitive is equivalent to a TRI primitive whose Output Enable input is fed by any signal, but whose primary input is fed by a GND primitive.

If the input to the OPNDRN primitive is low, the output will be low. If the input is high, the output will be a high-impedance logic level.

The OPNDRN primitive is supported only for the FLEX 10K device family; it is converted to a TRI primitive for other devices.

If you turn on the Automatic Open-Drain Pins option in the Global Project Logic Synthesis dialog box (Assign menu) for a FLEX 10K-based project, the Compiler converts the following structures to the OPNDRN primitive:

TRI primitive whose Output Enable input is fed by any signal, but whose primary input is fed by a GND primitive

A TRI primitive whose Output Enable input is fed by the complement of its primary input.

When you use an OPNDRN buffer, you must observe the following rules:

An OPNDRN buffer may drive only one BIDIR or BIDIRC pin.

If an OPNDRN buffer feeds logic, it must also feed a BIDIR or BIDIRC pin. If it feeds a BIDIR or BIDIRC pin, it may not feed any other outputs.

See also:

Primitive/Port Interconnections

Unused Inputs to Primitives & Macrofunctions


DFF Primitive (D-Type Flipflop)

Function Prototype: 	FUNCTION DFF (D, CLK, CLRN, PRN)

RETURNS (Q);

Inputs	|	Outputs

PRN	CLRN	CLK	D	|	Q

L	H	X	X	|	H

H	L	X	X	|	L

L	L	X	X	|	Illegal

H	H	L	|	L

H	H	H	|	H

H	H	L	X	|	Qo*

H	H	H	X	|	Qo

*	Qo = level of Q before Clock pulse

All flipflops are positive-edge-triggered.

See also:

Clock Configuration Guidelines

DFFE Primitive

Master Reset Guidelines

Preset & Clear Configuration Guidelines

Primitive/Port Interconnections

Unused Inputs to Primitives & Macrofunctions

Recommended reading:

AB94 (Solutions to Design Timing Problems for Altera EPLDs)

AN42 (Metastability in Altera Devices)


DFFE Primitive (D-Type Flipflop with Clock Enable)

Function Prototype: 	FUNCTION DFFE (D, CLK, CLRN, PRN, ENA)

RETURNS (Q);

Inputs	|	Output

CLRN	PRN	ENA	D	CLK	|	Q

L	H	X	X	X	|	L

H	L	X	X	X	|	H

L	L	X	X	X	|	Illegal

H	H	L	X	X	|	Qo*

H	H	H	L	|	L

H	H	H	H	|	H

H	H	X	X	L	|	Qo*

*	Qo = level of Q before Clock pulse

All flipflops are positive-edge-triggered.

When the ENA (Clock Enable) input is high, the flipflop passes a signal from D to Q. When the ENA input is low, the state of Q is maintained, regardless of the D input.

For devices that do not support Clock Enable, logic synthesis generates logic equations containing flipflops with Clock Enables. These logic equations correctly emulate the logic specified in your project.

The ENADFF macrofunction has the same functionality as the DFFE primitive.

See also:

Clock Configuration Guidelines

DFF Primitive

Master Reset Guidelines

Preset & Clear Configuration Guidelines

Primitive/Port Interconnections

Unused Inputs to Primitives & Macrofunctions

Recommended reading:

AB94 (Solutions to Design Timing Problems for Altera EPLDs)

AN42 (Metastability in Altera Devices)


JKFF Primitive (JK-Type Flipflop)

Function Prototype: 	FUNCTION JKFF (J, K, CLK, CLRN, PRN)

RETURNS (Q);

Inputs	|	Outputs

PRN	CLRN	CLK	J	K	|	Q

L	H	X	X	X	|	H

H	L	X	X	X	|	L

L	L	X	X	X	|	Illegal

H	H	L	X	X	|	Qo*

H	H	L	L	|	Qo*

H	H	H	L	|	H

H	H	L	H	|	L

H	H	H	H	|	Toggle

*	Qo = level of Q before Clock pulse

All flipflops are positive-edge-triggered.

See also:

Clock Configuration Guidelines

JKFFE Primitive

Master Reset Guidelines

Preset & Clear Configuration Guidelines

Primitive/Port Interconnections

Unused Inputs to Primitives & Macrofunctions

Recommended reading:

AB94 (Solutions to Design Timing Problems for Altera EPLDs)

AN42 (Metastability in Altera Devices)


JKFFE Primitive (JK-Type Flipflop with Clock Enable)

Function Prototype: 	FUNCTION JKFFE (J, K, CLK, CLRN, PRN, ENA)

RETURNS (Q);

Inputs	|	Output

ENA	PRN	CLRN	CLK	J	K	|	Q

X	L	H	X	X	X	|	H

X	H	L	X	X	X	|	L

X	L	L	X	X	X	|	Illegal

X	H	H	L	X	X	|	Qo*

H	H	H	L	L	|	Qo*

H	H	H	H	L	|	H

H	H	H	L	H	|	L

H	H	H	H	H	|	Toggle

L	H	H	X	X	X	|	Qo*

*	Qo = level of Q before Clock pulse

All flipflops are positive-edge-triggered.

When the ENA (Clock Enable) input is high, the flipflop passes a signal that is dependent on the J and K inputs to Q. When the ENA input is low, the state of Q is maintained, regardless of the J or K inputs.

For devices that do not support Clock Enable, logic synthesis generates logic equations containing flipflops with Clock Enables. These logic equations correctly emulate the logic specified in your project.

See also:

Clock Configuration Guidelines

JKFF Primitive

Master Reset Guidelines

Preset & Clear Configuration Guidelines

Primitive/Port Interconnections

Unused Inputs to Primitives & Macrofunctions

Recommended reading:

AB94 (Solutions to Design Timing Problems for Altera EPLDs)

AN42 (Metastability in Altera Devices)


LATCH Primitive

Function Prototype: 	FUNCTION LATCH (D, ENA)

RETURNS (Q);

Inputs	|	Output

ENA	D	|	Q

L	X	|	Qo*

H	L	|	L

H	H	|	H

*	Qo = level of Q before Clock pulse

Latches are level-sensitive.

When the ENA (Latch Enable) input is high, the latch passes a signal from D to Q. When the ENA input is low, the state of Q is maintained, regardless of the D input.

For devices that do not support Latch Enable, logic synthesis generates logic equations containing latches with Latch Enables. These logic equations correctly emulate the logic specified in your project.

See also:

Primitive/Port Interconnections

Unused Inputs to Primitives & Macrofunctions

Recommended reading:

AB9 (Asynchronous Latches in Classic, MAX & STG EPLDs)

AB77 (Fitting Complex Designs in MAX 5000 EPLDs)

AB94 (Solutions to Design Timing Problems for Altera EPLDs)

AB143 (Understanding FLEX 8000 Timing)

AB144 (Understanding MAX 9000 Timing)

AN42 (Metastability in Altera Devices)


SRFF Primitive (SR-Type Flipflop)

Function Prototype: 	FUNCTION SRFF (S, R, CLK, CLRN, PRN)

RETURNS (Q);

Inputs	|	Outputs

PRN	CLRN	CLK	S	R	|	Q

L	H	X	X	X	|	H

H	L	X	X	X	|	L

L	L	X	X	X	|	Illegal

H	H	L	X	X	|	Qo*

H	H	L	L	|	Qo*

H	H	H	L	|	H

H	H	L	H	|	L

H	H	H	H	|	Toggle

*	Qo = level of Q before Clock pulse

All flipflops are positive-edge-triggered.

See also:

Clock Configuration Guidelines

Master Reset Guidelines

Preset & Clear Configuration Guidelines

Primitive/Port Interconnections

SRFFE Primitive

Unused Inputs to Primitives & Macrofunctions

Recommended reading:

AB94 (Solutions to Design Timing Problems for Altera EPLDs)

AN42 (Metastability in Altera Devices)


SRFFE Primitive (SR-Type Flipflop with Clock Enable)

Function Prototype: 	FUNCTION SRFFE (S, R, CLK, CLRN, PRN, ENA)

RETURNS (Q);

Inputs	|	Output

ENA	PRN	CLRN	CLK	S	R	|	Q

X	L	H	X	X	X	|	H

X	H	L	X	X	X	|	L

X	L	L	X	X	X	|	Illegal

X	H	H	L	X	X	|	Qo*

H	H	H	L	L	|	Qo*

H	H	H	H	L	|	H

H	H	H	L	H	|	L

H	H	H	H	H	|	Toggle

L	H	H	X	X	X	|	Qo*

*	Qo = level of Q before Clock pulse

All flipflops are positive-edge-triggered.

When the ENA (Clock Enable) input is high, the flipflop passes a signal that is dependent on the S and R inputs to Q. When the ENA input is low, the state of Q is maintained, regardless of the S and R inputs.

For devices that do not support Clock Enable, logic synthesis generates logic equations containing flipflops with Clock Enables. These logic equations correctly emulate the logic specified in your project.

See also:

Clock Configuration Guidelines

Master Reset Guidelines

Preset & Clear Configuration Guidelines

Primitive/Port Interconnections

SRFF Primitive

Unused Inputs to Primitives & Macrofunctions

Recommended reading:

AB94 (Solutions to Design Timing Problems for Altera EPLDs)

AN42 (Metastability in Altera Devices)


TFF Primitive (T-Type Flipflop)

Function Prototype: 	FUNCTION TFF (T, CLK, CLRN, PRN)

RETURNS (Q);

Inputs	|	Outputs

PRN	CLRN	CLK	T	|	Q

L	H	X	X	|	H

H	L	X	X	|	L

L	L	X	X	|	Illegal

H	H	L	|	Qo*

H	H	H	|	Toggle

H	H	L	X	|	Qo*

*	Qo = level of Q before Clock pulse

All flipflops are positive-edge-triggered.

See also:

Clock Configuration Guidelines

Master Reset Guidelines

Preset & Clear Configuration Guidelines

Primitive/Port Interconnections

TFFE Primitive

Unused Inputs to Primitives & Macrofunctions

Recommended reading:

AB94 (Solutions to Design Timing Problems for Altera EPLDs)

AN42 (Metastability in Altera Devices)


TFFE Primitive (T-Type Flipflop with Clock Enable)

Function Prototype: 	FUNCTION TFFE (T, CLK, CLRN, PRN, ENA)

RETURNS (Q);

Inputs	|	Output

CLRN	PRN	ENA	T	CLK	|	Q

L	H	X	X	X	|	L

H	L	X	X	X	|	H

L	L	X	X	X	|	Illegal

H	H	L	X	X	|	Qo*

H	H	H	L	|	Qo*

H	H	H	H	|	Toggle

H	H	X	X	L	|	Qo*

*	Qo = level of Q before Clock pulse

All flipflops are positive-edge-triggered.

When the ENA (Clock Enable) input is high, the flipflop passes a signal from T to Q. When the ENA input is low, the state of Q is maintained, regardless of the T input.

For devices that do not support Clock Enable, logic synthesis generates logic equations containing flipflops with Clock Enables. These logic equations correctly emulate the logic specified in any project.

See also:

Clock Configuration Guidelines

Master Reset Guidelines

Preset & Clear Configuration Guidelines

Primitive/Port Interconnections

TFF Primitive

Unused Inputs to Primitives & Macrofunctions

Recommended reading:

AB94 (Solutions to Design Timing Problems for Altera EPLDs)

AN42 (Metastability in Altera Devices)


Pinstub/Stub Names for Primitive
Pinstub Names in Primitives

CLK	=	Register Clock Input

CLRN	=	Clear Input

D, J, K, R, S, T	=	Data input from Logic Array

ENA	=	Latch Enable or Clock Enable Input

PRN	=	Preset Input

Q	=	Output


BIDIR or INOUT Primitive/Port

AHDL Syntax:	io : BIDIR;

VHDL Syntax:	io : INOUT

Source:	TRI

Destination:	device I/O pin at top level of hierarchy tree or higher-level file in hierarchy tree

If TRI is disabled, external input is allowed. If TRI is enabled and an external signal is applied, signal contention is possible and could damage the device.

In the Graphic Editor, you may edit the PIN_NAME and pin default value text fields in this primitive.

Pin assignments may be made only in the top-level design file of a hierarchy of design files. Pin assignments made in lower-level files are ignored during compilation.

See also:

Assigning a Pin, Location, or Chip

Assigning Connected Pins

BIDIRC Primitive

Guidelines for Working with Assignments

Implementing Bidirectional Pins (AHDL)

Ports (AHDL)

Primitive/Port Interconnections

Unused Inputs to Primitives & Macrofunctions

Recommended reading:

AB60 (Estimating a Design Fit)

AB77 (Fitting Complex Designs in MAX 5000 EPLDs)

AB86 (Designing & Simulating Bidirectional Buses with MAX+PLUS II Software)

AB93 (Partitioning a Project with MAX+PLUS II Software)


INPUT or IN Primitive/Port

AHDL Syntax:	in1 : INPUT;

VHDL Syntax:	in1 : IN

Source:	device pin at top level of hierarchy tree or higher-level file in hierarchy tree

Destination:	all primitives or macrofunctions except BIDIR, BIDIRC, VCC, GND

In the Graphic Editor, you can edit the PIN_NAME and pin default value text fields in this primitive.

1.	Assigning a pin to an unconnected INPUT primitive reserves the pin for future use.

2.	Pin assignments may be made only in the top-level design file of a hierarchy of design files. Pin assignments made in lower-level files are ignored during compilation.

See also:

Assigning a Pin, Location, or Chip

Assigning Connected Pins

Guidelines for Working with Assignments

INPUTC Primitive

Ports (AHDL)

Primitive/Port Interconnections

Unused Inputs to Primitives & Macrofunctions

Recommended reading:

AB60 (Estimating a Design Fit)

AB77 (Fitting Complex Designs in MAX 5000 EPLDs)

AB93 (Partitioning a Project with MAX+PLUS II Software)


OUTPUT or OUT Primitive/Port

AHDL Syntax:	out1 : OUTPUT;

VHDL Syntax:	out1 : OUT

Source:	all pins except BIDIR

Destination:	device pin at top level of hierarchy tree or higher-level file in hierarchy tree

In the Graphic Editor, you can edit the PIN_NAME and pin default value text fields in this primitive.

Pin assignments may be made only in the top-level design file of a hierarchy of design files. Pin assignments made in lower-level files are ignored during compilation.

See also:

Assigning a Pin, Location, or Chip

Assigning Connected Pins

Guidelines for Working with Assignments

OUTPUTC Primitive

Ports (AHDL)

Primitive/Port Interconnections

Unused Inputs to Primitives & Macrofunctions

Recommended reading:

AB60 (Estimating a Design Fit)

AB77 (Fitting Complex Designs in MAX 5000 EPLDs)

AB93 (Partitioning a Project with MAX+PLUS II Software)


BIDIRC Primitive

Source:	TRI

Destination:	device I/O pin

External Connection:	INPUTC, OUTPUTC, or BIDIRC

The BIDIRC external connection pin primitive is identical to the BIDIR primitive, except for an additional external connection pinstub that is used to specify that device pins are externally connected.

The following rules apply to using the BIDIRC primitive:

If TRI is disabled, external input is allowed. If TRI is enabled and an external signal is applied, signal contention is possible and could damage the device.

You can only connect an external connection pinstub to the external connection pinstub of an INPUTC, OUTPUTC, or BIDIRC primitive.

You can connect external connection pinstubs with a bus line; however, the width of the bus name must equal the width of the pin name.

In the Graphic Editor, you can edit the PIN_NAME and pin default value text fields in the BIDIRC primitive.

As an alternative to using the INPUTC, OUTPUTC, and BIDIRC primitives, you can specify external pin connections with the Connected Pins command (Assign menu) or in a Connected Pin Assignments Section of an ACF. Connecting the external connection pinstubs of these primitives in a Graphic Editor file automatically creates a Connected Pin Assignments Section in the ACF for the hierarchy tree.

Pin assignments can be made only in the top-level design file of a hierarchy of design files. Pin assignments made in lower-level files are ignored during compilation.

See also:

Assigning a Pin, Location, or Chip

Assigning Connected Pins

Guidelines for Working with Assignments

Primitive/Port Interconnections

Unused Inputs to Primitives & Macrofunctions

Recommended reading:

AB60 (Estimating a Design Fit)

AB77 (Fitting Complex Designs in MAX 5000 EPLDs)

AB86 (Designing & Simulating Bidirectional Buses with MAX+PLUS II Software)

AB93 (Partitioning a Project with MAXPLUS II Software)


INPUTC Primitive

Source:	device pin

Destination:	all primitives or macrofunctions except BIDIR, BIDIRC, VCC, GND

External Connection:	BIDIRC, INPUTC, or OUTPUTC

The INPUTC external connection pin primitive is identical to the INPUT primitive, except for an additional external connection pinstub that is used to specify that device pins are externally connected.

The following rules apply to using the INPUTC primitive:

You can only connect an external connection pinstub to the external connection pinstub of a BIDIRC, INPUTC, or OUTPUTC primitive.

You can connect external connection pinstubs with a bus line; however, the width of the bus name must equal the width of the pin name.

In the Graphic Editor, you can edit the PIN_NAME and pin default value text fields in the INPUTC primitive.

As an alternative to using the INPUTC, OUTPUTC, and BIDIRC primitives, you can specify external pin connections with the Connected Pins command (Assign menu) or in a Connected Pin Assignments Section of an ACF. Connecting the external connection pinstubs of these primitives in a Graphic Editor file automatically creates a Connected Pin Assignments Section in the ACF for the hierarchy tree.

1.	Assigning a pin to an unconnected INPUTC primitive reserves the pin for future use.

2.	Pin assignments may be made only in the top-level design file of a hierarchy of design files. Pin assignments made in lower-level files are ignored during compilation.

See also:

Assigning a Pin, Location, or Chip

Assigning Connected Pins

Guidelines for Working with Assignments

Primitive/Port Interconnections

Unused Inputs to Primitives & Macrofunctions

Recommended reading:

AB60 (Estimating a Design Fit)

AB77 (Fitting Complex Designs in MAX 5000 EPLDs)

AB93 (Partitioning a Project with MAX+PLUS II Software)


OUTPUTC Primitive

Source:	all pins except BIDIR

Destination:	device pin

External Connection:	BIDIRC, INPUTC, or OUTPUTC

This external connection pin primitive is identical to the OUTPUT primitive, except for an additional pinstub called the external connection pinstub.

You must follow these rules when using the OUTPUTC primitive:

You can only connect an external connection pinstub to the external connection pinstub of a BIDIRC, INPUTC, or OUTPUTC primitive.

You can connect external connection pinstubs with a bus line; however, the width of the bus name must equal the width of the pin name.

In the Graphic Editor, you can edit the PIN_NAME and pin default value text fields in the OUTPUTC primitive.

As an alternative to using the INPUTC, OUTPUTC, and BIDIRC primitives, you can specify external pin connections with the Connected Pins command (Assign menu) or in a Connected Pin Assignments Section of an ACF. Connecting the external connection pinstubs of these primitives in a Graphic Editor file automatically creates a Connected Pin Assignments Section in the ACF for the hierarchy tree.

Pin assignments can be made only in the top-level design file of a hierarchy of design files. Pin assignments made in lower-level files are ignored during compilation.

See also:

Assigning a Pin, Location, or Chip

Assigning Connected Pins

Guidelines for Working with Assignments

Primitive/Port Interconnections

Unused Inputs to Primitives & Macrofunctions

Recommended reading:

AB60 (Estimating a Design Fit)

AB77 (Fitting Complex Designs in MAX 5000 EPLDs)

AB93 (Partitioning a Project with MAX+PLUS II Software)


AND Primitives

Name:	AND2, AND3, AND4, AND6, AND8, AND12

Output Description:	OUT = logical AND of inputs

Input Description:	IN1, IN2, ...IN12 = 2, 3, 4, 6, 8, or 12 inputs

See also:

Primitive/Port Interconnections

Unused Inputs to Primitives & Macrofunctions


BAND Primitives

Name:	BAND2, BAND3, BAND4, BAND6, BAND8, BAND12

Output Description:	OUT = logical BAND of inputs

Input Description:	IN1, IN2, ...IN12 = 2, 3, 4, 6, 8, or 12 inputs

See also:

Primitive/Port Interconnections

Unused Inputs to Primitives & Macrofunctions


BNAND Primitives

Name:	BNAND2, BNAND3, BNAND4, BNAND6, BNAND8, BNAND12

Output Description:	OUT = logical BNAND of inputs (i.e., a logical OR of active-high signals or, for active-low signals, a logical AND)

Input Description:	IN1, IN2, ...IN12 = 2, 3, 4, 6, 8, or 12 inputs

See also:

Primitive/Port Interconnections

Unused Inputs to Primitives & Macrofunctions


BNOR Primitives

Name:	BNOR2, BNOR3, BNOR4, BNOR6, BNOR8, BNOR12

Output Description:	OUT = logical BNOR of inputs

Input Description:	IN1, IN2, ...IN12 = 2, 3, 4, 6, 8, or 12 inputs

See also:

Primitive/Port Interconnections

Unused Inputs to Primitives & Macrofunctions


BOR Primitives

Name:	BOR2, BOR3, BOR4, BOR6, BOR8, BOR12

Output Description:	OUT = logical BOR of inputs

Input Description:	IN1, IN2, ...IN12 = 2, 3, 4, 6, 8, or 12 inputs

See also:

Primitive/Port Interconnections

Unused Inputs to Primitives & Macrofunctions


GND Primitive

Name:	GND

Description:	Assigns a node or bus to GND

See also:

Primitive/Port Interconnections

Unused Inputs to Primitives & Macrofunctions


NAND Primitives

Name:	NAND2, NAND3, NAND4, NAND6, NAND8, NAND12

Output Description:	OUT = logical NAND of inputs

Input Description:	IN1, IN2, ...IN12 = 2, 3, 4, 6, 8, or 12 inputs

See also:

Primitive/Port Interconnections

Unused Inputs to Primitives & Macrofunctions


NOR Primitives

Name:	NOR2, NOR3, NOR4, NOR6, NOR8, NOR12

Output Description:	OUT = logical NOR of inputs

Input Description:	IN1, IN2, ...IN12 = 2, 3, 4, 6, 8, or 12 inputs

See also:

Primitive/Port Interconnections

Unused Inputs to Primitives & Macrofunctions


NOT Primitive

Name:	NOT

Output Description:	OUT = inverse of input

Input Description:	IN = 1 input

See also:

Primitive/Port Interconnections

Unused Inputs to Primitives & Macrofunctions


OR Primitives

Name:	OR2, OR3, OR4, OR6, OR8, OR12

Output Description:	OUT = logical OR of inputs

Input Description:	IN1, IN2, ...IN12 = 2, 3, 4, 6, 8, or 12 inputs

See also:

Primitive/Port Interconnections

Unused Inputs to Primitives & Macrofunctions


VCC Primitive

Name:	VCC

Description:	Assigns a node or bus to VCC

See also:

Primitive/Port Interconnections

Unused Inputs to Primitives & Macrofunctions


XNOR Primitive

Name:	XNOR

Description:	OUT = logical exclusive NOR of inputs IN1 and IN2

See also:

Primitive/Port Interconnections

Unused Inputs to Primitives & Macrofunctions


XOR Primitive

Name:	XOR

Description:	OUT = logical exclusive OR of inputs IN1 and IN2

See also:

Primitive/Port Interconnections

Unused Inputs to Primitives & Macrofunctions


Title Block Primitive

The title block allows you to store identification information about your GDF or OrCAD Schematic File. The title block is for documentation purposes only and is not required in your project. The title block includes the following data fields:

Field:	Description:

COMPANY     Your company name

TITLE       Title of the drawing

DESIGNER    Your name

SIZE        Drawing size

NUMBER      Drawing reference number

REV         Revision identification

DATE        Date of last edit

SHEET       Page identification

Every time a Graphic Editor file is saved, MAX+PLUS II automatically updates the DATE and SHEET fields in the file’s title block. The contents of the COMPANY and DESIGNER fields are determined during MAX+PLUS II installation and are stored in the maxplus2.ini File.

To edit the title block, select the text by double-clicking on it with Button 2 , then type the desired text.

You can edit text in the TITLE, SIZE, NUMBER, and REV fields but cannot leave these fields empty.

See also:

Changing the File Size

Creating & Using a Local Copy of the maxplus2.ini File


WIRE Primitive

Name:	WIRE

Output Description:	OUT = input

Input Description:	IN

The WIRE primitive is used to rename a node. WIRE primitives do not have any associated logic behavior. Example

See also:

Naming a Node or Bus

Pin & Node Names

Primitive/Port Interconnections

Unused Inputs to Primitives & Macrofunctions


---------------------------------------BEGINNING OF NON-TRANSLATED TEXT-----------------------------------------

The following GEDMSG.MSG messages are documented in GLMESS.MAC:

CGED_OVERWRITE_FILE

SGED_FILE_OPEN

SGED_FILE_FORMAT

SGED_FILE_READ

SGED_FILE_WRITE

SGED_PRINTER_DC

SGED_START_PRINT

SGED_PRINT_DISK

SGED_PRINT_MEM

SGED_PRINT

SGED_OUT_OF_MEMORY

The following GEDMSG.MSG messages are documented in EDMESS.MAC:

SGED_TEXT_NOT_FOUND

SGED_NODE_NOT_FOUND

SGED_SEARCH_DONE

SGED_CANT_ERASE_TEXT

SGED_CANT_DELETE_TEXT

YGED_CONT_SEARCH_AT_BOTTOM

YGED_CONT_SEARCH_AT_TOP

sged_font_size_not_supported

sged_font_not_supported

sged_not_default_font_size

Documented in wedmess

QGED_CREATE_NEW_FILE

Remember to document C&A ok in gedmsgs.msg:

YGED_CONT_SEARCH_AT_BOTTOM

YGED_CONT_SEARCH_AT_TOP

After 3.0, change the following message

Can't find symbol -- symbol <name> is not on library path

to

Can't find symbol -- symbol <name> not on library path

---------------------------------------END OF NON-TRANSLATED TEXT-----------------------------------------


Cant find node destination

CAUSE:	You chose Find Node Destination (Utilities menu), and a destination for the selected node or bus cannot be located. This message may occur if the node or bus line is not attached to another line or symbol.

ACTION:	Check the line-to-line and line-to-symbol connections.

See also:

Finding a Node Source or Destination

MAX+PLUS II Messages

Message Format


Cant find node source

CAUSE:	You chose Find Node Source (Utilities menu), and a source for the selected node or bus cannot be located. This message may occur if the node or bus line is not attached to another line or symbol.

ACTION:	Check the node-to-node and node-to-symbol connections.

See also:

Finding a Node Source or Destination

MAX+PLUS II Messages

Message Format


Can't find symbol <name> -- symbol is not on library path
Can't find symbol <name>  -- symbol is not on a library path

CAUSE:	You chose Enter Symbol (Symbol menu), and the symbol name that you typed does not exist in the current directory or is not in a directory that is recognized as a user or MAX+PLUS II library.

ACTION:	Ensure that you entered the symbol name correctly and/or add the directory that contains the symbol to your list of user libraries with User Libraries (Options menu).

See also:

Entering a Symbol

Specifying a User Library

MAX+PLUS II Messages

Message Format


 Cant save edits to a file that was not created by the Graphic Editor

CAUSE:	In a MAX+PLUS (DOS) project you compiled an ADF or a TDF and the MAX+PLUS (DOS) Compiler created a GDF that contains a token symbol for the file. You then opened this GDF with the MAX+PLUS II Graphic Editor. Since this GDF has an old format and contains only a token symbol, you cannot enter and save new information.

ACTION:	Recompile the project with MAX+PLUS II to create new Symbol Files for all design files. Do not edit GDFs that contain token symbols generated by MAX+PLUS II (DOS).

See also:

MAX+PLUS II Messages

Message Format


Can't save edits to a Symbol File for a primitive
 Cant save edits to a Symbol File for a primitive

CAUSE:	You have opened and/or edited and attempted to save changes to a Symbol File for an Altera-provided primitive. Since you cannot edit an Altera-provided primitive, the Graphic Editor is warning you that edits will not be saved.

ACTION:	Use Copy and Paste (Edit menu) to copy the symbol contents to another Symbol File for use as a macrofunction symbol if you do not wish to discard your edits.

See also:

MAX+PLUS II Messages

Message Format

Copying, Cutting & Pasting an Object


 Cant update symbol <name> -- symbol is not on a library path

CAUSE:	You chose Update Symbol (Symbol menu), and the symbol(s) that you have selected are not listed in the user or MAX+PLUS II library paths.

ACTION:	Add the directory that contains the symbol to your user libraries with User Libraries (Options menu).

See also:

MAX+PLUS II Messages

Message Format

Specifying a User Library


Guideline spacing value must be an integer between 1 and 999

CAUSE:	You chose Guideline Spacing (Options menu), and entered an illegal horizontal and/or vertical spacing value.

ACTION:	Make sure you typed the correct spacing value(s). Remember that Guideline Spacing only accepts integer values between 1 and 999.

See also:

MAX+PLUS II Messages

Message Format


Insertion point is not defined. OK to enter in center of window?

CAUSE:	You chose Enter Symbol (Symbol menu) or Paste (Edit menu) without first selecting an insertion point.

ACTION:	If you do not want the symbol or Clipboard information to be entered in the center of the current window, choose Cancel to cancel the command. Otherwise, choose OK. If you wish to specify an insertion point, move the mouse cursor to the desired location, press Button 1, then choose Enter Symbol or Paste again.

See also:

Copying, Cutting & Pasting an Object

Copying, Cutting & Pasting Text

Entering a Symbol

MAX+PLUS II Messages

Message Format


Move canceled--assignment must be attached to a symbol
Move or copy canceled--assignment must be attached to a symbol

CAUSE:	You moved or copied and released a probe or resource assignment into a blank space in the file. Probes and assignments must always be associated with a symbol, so the action was canceled. This message may also occur if you try to move or copy multiple probes or both a probe and a resource assignment at the same time.

ACTION:	No action is required. The assignment returns to its original location. If you wish to move or copy the assignment, select it again, drag it, and release it over another symbol. Always move or copy each probe in a separate operation from moving or copying a resource assignment or another probe.

See also:

Copying a Resource Assignment

Deleting an Assignment

MAX+PLUS II Messages

Message Format

Moving a Probe or Resource Assignment


Node or bus lines overlap if drawn with orthogonal lines. OK to replace orthogonal lines with diagonal lines?

CAUSE:	The node(s) you have moved are overlapping one or more other nodes and the Graphic Editor is unable to draw orthogonal lines that maintain connectivity. Therefore, the Graphic Editor is offering to draw the node connections with diagonal lines.

ACTION:	If you want the Graphic Editor to draw diagonal lines to prevent overlapping nodes, choose OK. If you want the nodes to overlap and are not concerned about changes in connectivity, choose No. If you want the nodes to return to their original position, choose Cancel. You may then select and move the node(s) again.

See also:

MAX+PLUS II Messages

Message Format

Moving an Object


Misleading location of pinstub name <name>. OK to save file?
 Pinstub name <name> is in a misleading location. OK to save the file?

CAUSE:	You chose Save (File menu), and a pinstub name on the inside of the symbol has been moved so that it is not adjacent to the pinstub associated with that name. A different name may be closer to the pinstub than its real name and may be misleading.

ACTION:	If you do not wish to save the current configuration of the pinstub names, choose Cancel to cancel the command. If you wish to save the changes, choose OK. If you wish to move the name to its original location and do not remember the pinstub with which it is associated, check the name displayed outside the symbol. Pinstub names displayed on the outside of the symbol cannot be edited or moved, so they are always next to the associated pinstub.

See also:

Changing the Pinstub Name & I/O Type

Entering & Naming a Pinstub

MAX+PLUS II Messages

Message Format

Moving an Object

Pinstubs & Pinstub Names


Sheet size <name>:<dimensions> selected for file
Sheet size <size>:<dimensions> selected for file

CAUSE:	You chose Size (File menu), and selected Automatic from the Sheet Size list box. The Graphic Editor selected the smallest sheet size and orientation that will fit the objects in the current file.

ACTION:	If you do not want to use the selected sheet size, choose Cancel to cancel the command. Otherwise, choose OK. The default sheet size for a new file is D (22 x 34 inches/154 x 238 grid units).

See also:

MAX+PLUS II Messages

Message Format


Sheet size too small for drawing

CAUSE:	You chose Size (File menu), and the sheet size you selected is too small to contain the objects in the current file.

ACTION:	Select another sheet size and/or orientation, or select Automatic in the Sheet Size box. The default sheet size for a new file is D (22 x 34 inches/154 x 238 grid units).

See also:

Changing the File Size

MAX+PLUS II Messages

Message Format


Symbol <name> is not on a library path

CAUSE:	You chose Enter Symbol (Symbol menu), and specified a symbol that is not in the current directory or is not in a directory that is recognized as a user or MAX+PLUS II library. Therefore, when the Compiler processes this file, it will not be able to locate the corresponding design file.

ACTION:	Delete the symbol or add the directory that contains the symbol to the list of user libraries with User Libraries (Options menu).

See also:

Entering a Symbol

Specifying a User Library

MAX+PLUS II Messages

Message Format


 Cant find OrCAD part: <name>

CAUSE:	You tried to open or compile an OrCAD Schematic File, but the file contains an OrCAD part that is not present in the OrCAD Library File with the same filename.

ACTION:	Create a single OrCAD Library File that contains the libraries of all symbols used in the OrCAD Schematic File, and copy it to the project directory or to a user library directory before opening or compiling the file in MAX+PLUS II.

See also:

Compiling OrCAD Schematic Files

Guidelines for Working with OrCAD Schematic Files

MAX+PLUS II Messages

Message Format

Restrictions on OrCAD Schematic Files in MAX+PLUS II

Specifying a User Library


Multiple OrCAD part mappings: both OrCAD parts <name> and <name> mapped to MAX+PLUS II symbol <name>, but...
 Multiple OrCAD part mappings: both OrCAD parts <name> and <name> mapped to MAX+PLUS II symbol <name>, but the Graphic Editor can display only one version of this symbol

CAUSE:	You tried to open or compile an OrCAD Schematic File, but the file has multiple parts (i.e., symbols) that are mapped to the specified MAX+PLUS II logic function. Since MAX+PLUS II Graphic Editor can display only one version of the specified MAX+PLUS II logic function, the connectivity of some of the symbols in the OrCAD Schematic File may be lost. This message typically occurs if you have mixed both TTL and PLDGATE parts in the same OrCAD Schematic File.

ACTION:	Check the connectivity in the OrCAD Schematic File. In general, you should not mix different versions of the same part in an OrCAD Schematic File that is opened in MAX+PLUS II.

See also:

Compiling OrCAD Schematic Files

Guidelines for Working with OrCAD Schematic Files

MAX+PLUS II Messages

Message Format

Restrictions on OrCAD Schematic Files in MAX+PLUS II


 Cant display OrCAD part <name> as a primitive -- creating it as a macrofunction instead

CAUSE:	A part in an OrCAD Schematic File has the same name as a MAX+PLUS II primitive, but its pins cannot be mapped exactly to the pinstubs used in the MAX+PLUS II primitives.

ACTION:	To correct this problem, perform one of the following tasks:

Switch to the OrCAD Library Files pldgates.lib and ttl.lib.

Create a GDF that uses the same pin names as the OrCAD part and connect the pins to the inputs and outputs of the MAX+PLUS II primitive.

Update the symbol in the Graphic Editor. The OrCAD part will be replaced by the MAX+PLUS II primitive.

See also:

Compiling OrCAD Schematic Files

MAX+PLUS II Messages

Message Format

Updating a Symbol in a Graphic Editor File


Information on instance-specific ports and parameters will be lost if this file is saved as an OrCAD Schematic file. OK to save
Information on instance-specific ports and parameters will be lost if this file is saved as an OrCAD Schematic file. OK to save the file anyway?

CAUSE:	OrCAD Schematic Files do not accept information on instance specific ports and parameters. Specified port and parameter information will be lost if file is saved as an OrCAD schematic file.

ACTION:	Choose OK to save file or Cancel to cancel the save.

See also:

MAX+PLUS II Messages

Message Format


MAX+PLUS II symbol <name> (ID <net ID number>) contains pinstubs(s) that cannot be placed on OrCAD grid units -- some connectivi
MAX+PLUS II symbol <name> (ID <net ID number>) contains pinstubs(s) that cannot be placed on OrCAD grid units -- some connectivity will be lost

CAUSE:	(see message title).

ACTION:	Choose OK to save truncated parameter information or Cancel to return to the Edit Parameter dialog box with original parameters.

See also:

MAX+PLUS II Messages

Message Format


Graphic & Symbol Editor Commands
Commands

For Help, choose a command name or dialog box name from the following list. Menu names are not included on the list.

About MAX+PLUS II	MAX 7000S Individual Device Options

Advanced Options	MAX+PLUS II Registration

AHDL	MAX+PLUS II Table of Contents

Analyze Timing	Maximize

Archive	Maximum Size

Arrange Icons	Message Processor

Authorization Code	Messages

Auto Device Selection	Minimize

Back-Annotate Project	More Windows

Basic Tools	Move

Cascade	Name

Classic & MAX Global Project Device Options	New Features in This Release

Classic & MAX Individual Device Options	New Window

Clear All Timing Analysis Tags	New

Clear Project Assignments	Next

Clique	Normal Size

Close (File menu)	Open

Close ( [image] and [image] menus)	Paste

Color Palette	Pin/Location/Chip

Commands	Preferences

Compiler	Primitives

Connected Pins	Print (Graphic Editor)

Convert Obsolete Assignment Format	Print (Symbol Editor)

Copy	Print Setup

Create Default Include File	Probe

Create Default Symbol	Procedures

Cut	Programmer

Define Synthesis Style	Project 1, 2, 3, 4...

Delete File	Project Archive

Delete	Project Name

Device	Project Save & Check

Devices & Adapters	Project Save & Compile

Edit Pin Default Value	Project Save & Simulate

Edit Pin Name	Project Save, Compile & Simulate

Edit Ports/Parameters	Project Set Project to Current File

Edit Symbol 	READ.ME

Enter Parameters	Rename Chip

Enter Pinstub	Restore

Enter Symbol	Retrieve

ES Site License Authorization Request	Rotate 90°

Exit MAX+PLUS II	Rotate 180°

Find Last Edit	Rotate 270°

Find Next	Rubberbanding

Find Node Destination	Save & Check

Find Node in Design File	Save & Compile

Find Node in Floorplan Editor	Save & Simulate

Find Node Source	Save As

Find Previous	Save Style As

Find Text (Graphic Editor)	Save, Compile & Simulate

Find Text (Symbol Editor)	Save

Fit in Window	Search & Replace (Graphic Editor)

FLEX 10K Global Project Device Options	Search & Replace (Symbol Editor)

FLEX 10K Individual Device Options	Search for Help on

FLEX 8000 Global Project Device Options	Search Node Database

FLEX 8000 Individual Device Options	Set Project to Current File

Flip Horizontal	Shortcuts

Flip Vertical	Show All

Floorplan Editor	Show Cliques & Timing Assignments

Font	Show Guidelines

Global Project Device Options	Show Logic Options

Global Project Logic Synthesis	Show Parameters

Global Project Parameters	Show Pins/Locations/Chips

Global Project Timing Requirements	Show Probes

Glossary	Show Status Bar

Golden Rules	Show Toolbar

Graphic Editor	Simulator

Graphic Editor Help Basic Tools	Size (File menu)

Graphic Editor Help Commands	Size ( [image] and [image] menus)

Graphic Editor Help Golden Rules	Snap to Grid (Symbol Editor Only)

Graphic Editor Help Introduction	Switch To

Graphic Editor Help Procedures	Symbol Editor

Graphic Editor Help Shortcuts	Table of Contents

Graphic Editor Help Table of Contents	Text Editor

Guideline Spacing	Text Size

Hierarchy Display	Tile Horizontally

Hierarchy Down	Tile Vertically

Hierarchy Project Top	Timing Analysis Cutoff

Hierarchy Top	Timing Analysis Destination

Hierarchy Up	Timing Analysis Source

How to Use Help	Timing Analyzer

How to Use MAX+PLUS II Help	Timing Requirements

Ignore Project Assignments	Toggle Connection Dot

Individual Logic Options	Undo

Info	Update Symbol

Introduction	User Libraries

Line Style	VHDL

Logic Options	Waveform Editor

Macrofunctions	Zoom In

MAX 7000S Global Project Device Options	Zoom Out


Save As Command (Graphic & Symbol Editors)
Save As Command (File Menu)

Saves a new version of the current file under a different name, in a different directory, or on a different drive. Save As also saves a new file for the first time.

Click Button 1 on any item in this dialog box for information on that item:

You can save a GDF as an OrCAD Schematic File and vice versa. Symbol Files are always saved with the .sym filename extension.

When you save an OrCAD Schematic File in the Graphic Editor, MAX+PLUS II retains as much information as possible from the original file, but some information is lost. Refer to Restrictions on OrCAD Schematic Files in MAX+PLUS II and Guidelines for Working with OrCAD Schematic Files for important information on working with OrCAD Schematic Files.

See also:

Creating the Default Symbol for a File

Project Save & Compile Command

Save Command

Save & Check Command

Saving a File


Size Command (Graphic Editor)
Size Command (File Menu)

Changes the sheet size for the current Graphic Editor file.

Click Button 1 on any item in this dialog box for information on that item:

When you edit a Graphic Editor file, all objects must be within the sheet border. You can see the border of the sheet as you zoom out within the Graphic Editor window. The sheet size also determines the size of objects displayed as you zoom out to fit more of the file into the window.

If you print or plot a Graphic Editor file on a sheet with the same size specified in this command, all objects in the file are printed at Normal Size (View menu). If you print the file on smaller paper, objects in the file are scaled according to the parameters specified with Print (File menu).

See also:

Changing the File Size

Zooming In & Out


Orientation

Selects a Horizontal (A to H) or Vertical (AV to HV) orientation for the sheet sizes displayed in the Sheet Size box.


Sheet Size

Specifies the sheet size. The sizes listed in the sheet size box are determined by the currently selected Orientation. The default sheet size is D: 22 x 34 inches (154 x 238 GUs).

The following sheet sizes are available:

Size:	Inches (grid units):

Automatic	Selects the smallest sheet size and orientation that will fit the current objects within the file.

A/AV	9 x 11 in. 	(59 x 77 GUs)

B/BV	11 x 17 in. 	(77 x 119 GUs)

C/CV	17 x 22 in.	(119 x 154 GUs)

D/DV	22 x 34 in. 	(154 x 238 GUs)

E/EV	34 x 44 in. 	(238 x 308 GUs)

F/FV	44 x 68 in. 	(308 x 476 GUs)

G/GV	68 x 88 in. 	(476 x 616 GUs)

H/HV	143 x 143 in. 	(999 x 999 GUs)


Graphic: Size dialog box
Size dialog box

Click Button 1 on any item in this dialog box for information on that item:


Print Command (Graphic Editor)
Print Command (File Menu)

Shortcuts

Prints the file in the currently active window.

Click Button 1 on any item in this dialog box for information on that item:

To print parameters, probe assignments, resource assignments, and guidelines, turn on one or more of the following Options menu commands before printing the file:

Command:	Action:

Show Parameters	Displays or hides parameters.

Show Guidelines	Displays or hides guidelines.

Show Probes	Displays or hides all probe assignments.

Show Pins/Locations/Chips	Displays or hides all pin, logic cell, and chip assignments.

Show Cliques & Timing Assignments	Displays or hides all clique and timing assignments.

Show Logic Options	Displays or hides all logic option, and logic synthesis style assignments.

Show All	Displays or hides all probe and resource assignments.

MAX+PLUS II prints the file according to the settings for the current printer, which are specified with Print Setup (File menu).

To stop printing, choose Cancel.

See also:

Printing a File

Showing Guidelines

Showing Probe & Resource Assignments


Pages

All 	Specifies that the entire file will be printed.

Selected Area	Specifies that the current selected area will be printed.

Fit Into? % of One Page	Scales the selected print area (All or Selected Area) to fit into a percentage (up to 100%) of one single page.

Fit Into? Pages	Specifies the number of pages (1, 4, or 9) you want to fit the file on. Scales the selected print area (All or Selected Area) to 100%, 200%, 300%, or 400% of the paper size.

File Sheet Size	Shows the drawing size of the file determined by Size (File menu).


Print

Symbol Borders and Numbers	Prints the symbol borders and the symbol ID numbers.

Pin Default Values	Prints the default values for unconnected pins.

Page Headers	Prints the filename, date, page count, and project name at the top of each page.

Sheet Border	Prints the border specified with Size (File menu).

All 	Prints the symbol borders and numbers, pin default values, page headers, and the sheet border.


Graphic: Print dialog box (Graphic Editor)
Print dialog box

Click Button 1 on any item in this dialog box for information on that item:


Print Command (Symbol Editor)
Print Command (File Menu)

Shortcuts

Prints the file in the currently active window.

Click Button 1 on any item in this dialog box for information on that item:

MAX+PLUS II prints the file according to the settings for the current printer, which are specified with Print Setup (File menu).

To stop printing, choose Cancel.

To print guidelines or parameters, turn on Show Guidelines or Show Parameters (Options menu) to display them.

See also:

Printing a File

Showing Guidelines


Fit Into: % of One Page

Scales the file to fit into a percentage (up to 100%) of a single page.


Graphic: Print dialog box (Symbol Editor)
Print dialog box

Click Button 1 on any item in this dialog box for information on that item:


Cut Command (Graphic & Symbol Editors)
Cut Command (Edit Menu)

Shortcuts

Deletes one or more selected items from your file and places it on the Clipboard. The previous contents of the Clipboard are erased.

Use Paste (Edit menu) to insert the cut selection at a different location. The contents of the Clipboard can be pasted repeatedly. Cut text can be pasted into other MAX+PLUS II files and into different types of text fields. An object can be pasted only if it is compatible with the target file format (e.g., GDF or Symbol File). Example

Use Delete (Edit menu) instead of Cut to remove a selection from your file without affecting the contents of the Clipboard.

See also:

Copying, Cutting & Pasting an Object

Copying, Cutting & Pasting Text

Deleting an Object

Deleting Text

Selecting an Object

Selecting Text


Example:  A pin name from a GDF can be pasted into a TDF.
A pin name from a GDF can be pasted into a TDF.


Copy Command (Graphic & Symbol Editors)
Copy Command (Edit Menu)

Shortcuts

Copies one or more selected items from the file and places them on the Clipboard. The previous contents of the Clipboard are erased.

Use Paste (Edit menu) to insert the copied selection at a different location. The contents of the Clipboard can be pasted repeatedly. Copied text can be pasted into other MAX+PLUS II files and into different types of text fields. An object can be pasted only if it is compatible with the target file format (e.g., GDF or Symbol File). Example

After you choose Copy, the items remain selected.

See also:

Copying, Cutting & Pasting an Object

Copying, Cutting & Pasting Text

Selecting an Object

Selecting Text


Paste Command (Graphic & Symbol Editors)
Paste Command (Edit Menu)

Shortcuts

Places a copy of the Clipboard’s contents at the insertion point or overwrites selected text.

The Clipboard contents are defined with the last Cut or Copy command (Edit menu).

If a graphical insertion point has been defined, Paste inserts the object(s) in the Clipboard so that their top left corner is at the insertion point. If a text insertion point has been defined, Paste inserts the text to the left of the insertion point. If text is selected, Paste overwrites the selection. If no insertion point is defined, you are given the option to paste the object(s) in the center of the Graphic Editor window or to cancel the paste. The contents of the Clipboard can be pasted repeatedly.

Cut or copied text can be pasted into different MAX+PLUS II files and into different types of text fields. An object can be pasted only if it is compatible with the target file format (e.g., GDF or Symbol File). Example

If you paste a symbol into a Graphic Editor file that already contains a different version of that symbol, the appearance of the pasted symbol automatically changes to match the symbol that already exists in the target file. Example

See also:

Copying, Cutting & Pasting an Object

Copying, Cutting & Pasting Text

Selecting an Object

Selecting Text


Example: A symbol changing appearance to match symbol in a target file.
A 7400 macrofunction provided in MAX+PLUS II does not look the same as the functionally equivalent 74LS00 symbol provided in OrCAD schematic capture tools. Since MAX+PLUS II uses the orcad.lmf file to rename OrCAD symbols, an OrCAD Schematic File that is opened in MAX+PLUS II displays the 74LS00 as a 7400 symbol with a different shape. Therefore, if you paste the MAX+PLUS II version of the 7400 symbol into a file that already contains a converted OrCAD 7400 symbol, the MAX+PLUS II version of the 7400 will automatically change (in appearance only) to match the symbol in the target file.

Conversely, if you paste a converted OrCAD version of the 7400 symbol into a file that already contains the MAX+PLUS II 7400 symbol, the OrCAD symbol will automatically change to match the MAX+PLUS II version of the symbol.


Flip Horizontal & Flip Vertical Commands (Graphic & Symbol Editors)
Flip Horizontal & Flip Vertical Commands (Edit Menu)

Shortcuts

Flip an object or an area along its horizontal or vertical axis.

Each object in an object-by-object selection is individually flipped along its horizontal or vertical axis. All objects in an area selection are flipped along the horizontal or vertical axis of the area.

All text fields inside a symbol are moved to reflect its new orientation. The location of parameters and resource assignments on a symbol does not change when the symbol is flipped; e.g., clique assignments are always on the top left corner of a symbol. Probes flip with the symbol to maintain the attachment to the pinstubs to which they are assigned.

Connectivity between a flipped symbol or area and the surrounding logic is not maintained even if Rubberbanding (Options menu) is on.

See also:

Flipping a Selection

Rotating a Selection

Selecting an Object


Rotate Commands (Graphic & Symbol Editors)
Rotate Commands (Edit Menu)

Shortcuts

Rotate an object or an area counterclockwise around its center.

Command:	Action:

Rotate 90°	Rotates an object or area 90° counterclockwise.

Rotate 180°	Rotates an object or area 180° counterclockwise.

Rotate 270°	Rotates an object or area 270° counterclockwise.

Each object in an object-by-object selection is individually rotated around its center. When you use a Rotate command with an area selection, the area is rotated around its center.

All text fields inside a symbol are moved to reflect its new orientation. The location of parameters and resource assignments on a symbol does not change when the symbol is rotated; e.g., clique assignments are always on the top left corner of a symbol. Probes rotate with the symbol to maintain the attachment to the pinstubs to which they are assigned.

Connectivity between a flipped symbol or area and the surrounding logic is not maintained even if Rubberbanding (Options menu) is on.

See also:

Flipping a Selection

Rotating a Selection

Selecting an Object

Selecting Text


View Commands (Graphic & Symbol Editors)
View Commands (View Menu)

Allow you to change the display scale of the objects in the current window.

Command:	Action:

Fit in Window	Changes the display scale to fit the entire file, including the drawing sheet border, in the current window. Shortcuts

Zoom In	Increases the scale of the objects displayed, showing a smaller portion of the file. Shortcuts

Zoom Out	Reduces the scale of the objects displayed, showing a larger portion of the file. Shortcuts

Normal Size	Zooms in or out to display objects at normal (full) size. Shortcuts

Maximum Size	Zooms in to display objects at maximum resolution. Shortcuts

If objects are selected, the window zooms in and out on the objects. If an insertion point is defined, the window zooms in and out on the insertion point. Otherwise, the reference point for zooming is the center of the window.

Zoom In increases the display scale incrementally, eventually reaching the scale provided by Maximum Size. Zoom Out decreases the display scale incrementally to reach the size provided by Fit in Window.

When you choose Fit in Window or Zoom Out, some items (e.g., text or objects within a symbol) in the window may disappear. All items in the file are visible at Normal Size and Maximum Size.

You can use the keyboard shortcuts to zoom in or out as you select, move, or draw an object or area.

See also:

Fitting a File into the Window

Zooming In & Out


Enter Symbol Command (Graphic Editor)
Enter Symbol Command (Symbol Menu)

Shortcuts

Enters a symbol into the current Graphic Editor file.

For a parameterized symbol, the Enter Symbol dialog box also automatically opens the Edit Ports/Parameters dialog box, which allows you to assign parameter values, turn ports on and off, and invert ports before you finish entering the symbol in a file.

Click Button 1 on any item in this dialog box for information on that item:

If you define an insertion point by clicking Button 1 before choosing Enter Symbol, the symbol is placed with its top left corner at the insertion point. If no insertion point is defined, you are given the option to place the symbol in the center of the window.

1.	If you enter two symbols so that their borders and pinstubs touch, the symbols become logically connected. If you then move one of the symbols when Rubberbanding (Options menu) is turned on, a node or bus line forms automatically between the connected pinstubs.

2.	If you enter a symbol into a Graphic Editor file that already contains a different version of that symbol, the appearance of the symbol you enter automatically changes to match the symbol that already exists in the target file. Example

See also:

Entering a Symbol

Macrofunctions

Megafunctions/LPM

Primitives

Specifying a User Library


Symbol Name

Specifies the symbol name.

You can type a symbol name in the Symbol Name box or select a name in the Symbol Files box to copy it to the Symbol Name box. You can also type a text string that includes wildcard characters in the Symbol Name box and choose OK to update the contents of the Symbol Files box with the symbol names that match the text string.

If you enter the name of a symbol from a directory that is not listed in the Symbol Libraries box, the GDF will not compile unless you add the directory to your list of user libraries with User Libraries (Options menu).


Symbol Libraries

Lists all MAX+PLUS II-provided and user-defined library directories that contain symbols. Double-clicking Button 1 on a symbol library name displays its contents in the Symbol Files box. You can add another library to the list in the Symbol Libraries box with User Libraries (Options menu).


Symbol Files

Lists all symbol files in the current directory that match the text string in the Symbol Name box.

Selecting a symbol name in the Symbol Files box copies it to the Symbol Name box. You can also type a text string that includes wildcard characters in the Symbol Name box and then choose OK to update the contents of the Symbol Files box with the symbol names that match the new text string.


Directories

Lists all available disk drives and all subdirectories of the current directory.

You can type a different absolute or relative pathname in the Symbol Name box and choose OK or double-click Button 1 on a name in the Directories or Symbol Libraries box to change the current directory.

If you select a directory that is not listed in the Symbol Libraries box, you must add it to the list of user libraries with User Libraries (Options menu) to ensure that the project will compile properly.


Example: A symbol changing appearance to match symbol in a target file.
A 7400 macrofunction provided in MAX+PLUS II does not look the same as the functionally equivalent 74LS00 symbol provided in OrCAD schematic capture tools. Since MAX+PLUS II uses the orcad.lmf file to rename OrCAD symbols, an OrCAD Schematic File that is opened in MAX+PLUS II displays the 74LS00 as a 7400 symbol with a different shape. Therefore, if you enter the MAX+PLUS II version of the 7400 symbol into a file that already contains a converted OrCAD 7400 symbol, the appearance of the MAX+PLUS II version of the 7400 will automatically change to match the symbol in the target file.

Conversely, if you paste a converted OrCAD version of the 7400 symbol into a file that already contains the MAX+PLUS II 7400 symbol, the appearance of the OrCAD symbol will automatically change to match the MAX+PLUS II version of the symbol.


Graphic: Enter Symbol dialog box
Enter Symbol dialog box

Click Button 1 on any item in this dialog box for information on that item:


Edit Ports/Parameters Command (Graphic Editor)
Edit Ports/Parameters Command (Symbol Menu)

Shortcuts

Allows you to assign parameter values, and turn ports on or off for a megafunction or macrofunction. You can also identify which ports, if any, to invert.

Click Button 1 on any item in this dialog box for information on that item:

Parameters that have been assigned a value appear on the top right corner of a symbol if Show Parameters (Options menu) is turned on. Parameters with a value of <none> are not shown in the Graphic Editor window, but can be viewed in the Edit Ports/Paramters dialog box.

Only ports with the status Used appear in the symbol. Inverted ports are indicated with an auto-generated "bubble" and a label: for single-node ports, a 1; for bus ports, an inversion pattern in AHDL hexadecimal number format. If all members (bits) of a bus are inverted, the pattern is displayed as F*.

If you change the Symbol File using Create Default Symbol or by editing the file in the Symbol Editor, you must use Update Symbol to update the symbol. You do not need to use Update Symbol, however, if you use Edit Ports/Parameters to customize an individual mega- or macrofunction symbol in your GDF.

See also:

Customizing a Mega- or Macrofunction’s Ports & Parameters

Entering a Symbol

Macrofunctions

Megafunctions/LPM

Primitives

Specifying a User Library


Function Name

Displays the name of the megafunction or macrofunction for which you wish to edit ports and parameters.


Help on <function name> or Help

When the button appears as Help on <function name>, it opens MAX+PLUS II Help on the logicfunction displayed in the Function Name field.

When the button appears as Help, it indicates that the function is not an Altera-provided function, and instead, opens the help topic describing the Edit Ports/Parameters command.


Port Name

Displays the name of the port to be edited. You can select a different port in the Port Name/Status/Inversion list box.


Port Status

Specifies whether or not the port displayed in the Port Name field is used by the currently selected megafunction or macrofunction.

For ports with the status Used, the corresponding pinstubs and pinstub names will be displayed in the symbol instance in the GDF. Conversely, ports that are set to Unused do not appear in the symbol.


Inversion

Specifies whether the port or members (bits)of the bus port displayed in the Port Name field should be inverted.

You can invert the polarity of the bits in a variety of ways:

Option:	Action:

All	Inverts all of the bits.

None	Inverts none of the bits.

Pattern/Radix	Inverts a subset of bits. Enter a number in decimal, binary, octal, or hexadecimal radix to specify the bits to invert.

Although you can enter an inversion pattern in decimal, binary, octal, or hexadecimal format, the pattern is always displayed in the symbol in AHDL hexadecimal number format.


Port Name/Status/Inversion

Lists all available ports for the currently selected megafunction or macrofunction, including each port’s status (i.e., used or unused) and port inversion, if any.

You can select any of the available ports and edit its status and inversion state.

Although you can enter an inversion pattern in decimal, binary, octal, or hexadecimal format, the pattern is always displayed in the symbol in AHDL hexadecimal number format.


Parameter Name

Specifies the name of the parameter you wish to add, edit, clear, or delete.

You can either enter a parameter name with up to 32 name characters, or select an existing parameter from the Parameter Name/Value list box.

1. Predefined parameters (i.e., parameters entered with the Enter Parameters dialog box in the Symbol File for the function ) appear automatically in the Parameter Name/Value list box; they cannot be deleted. However, you can choose the Clear button to clear any predefined parameter’s value to <none>. The Compiler looks for parameter values using parameter value search order.

2. You can also clear the value, but not delete, a parameter defined for the current symbol instance by deleting the text in the Parameter Value box and choosing OK.


Parameter Description

Provides a brief description of the parameter displayed in the Parameter Name box.

Parameter descriptions are available only for Altera-provided megafunctions that are inherently parameterized.


Parameter Value

Specifies the value for the parameter displayed in the Parameter Name box.

If suitable predefined values are available, you can select a value in the drop-down list box. Otherwise, you can either enter a decimal, binary, octal, or hexadecimal number or a quoted or unquoted string (e.g., "unsigned"), as suggested in the Parameter Description.

You can also assign a null value to a parameter either by choosing Clear or deleting the text in the Parameter Value box and choosing Change. The Compiler looks for parameter values using the parameter search order. (The Clear button is enabled only for predefined parameters, i.e., parameters created with the Enter Parameters command in the Symbol File for the function, which cannot be deleted.)


Parameter Name/Value

Lists the existing parameters and parameter values for the currently selected megafunction or macrofunction. The list box contains all predefined parameters (i.e., parameters created for the function with the Enter Parameters command in the Symbol File) as well as any parameters defined for the current symbol instance (i.e., parameters entered with this dialog box).

You can select a parameter in this box to fill in the Parameter Name, Parameter Description, and Parameter Value fields. You can then edit the parameter name or value and choose Change to update the Parameter Name/Value list box.

If you select an existing parameter, change the Parameter Name, and choose Add, a new parameter is created. The previously selected parameter is not overwritten and both entries appear in the Parameter Name/Value list box.


Add/Change

Assigns the value shown in the Parameter Value box to the parameter specified in the Parameter Name box. The new or updated parameter is listed in the Parameter Name/Value list box.

The Add button changes into the Change button if you are editing an existing parameter. Choosing OK always saves the currently selected parameter and parameter value, as well as all parameters and values in the Parameter Name/Value list box.

If you select an existing parameter, change the Parameter Name, and choose Add, a new parameter is created. The previously selected parameter is not overwritten and both entries appear in the Parameter Name/Value list box.


Delete/Clear

The Delete button deletes the parameter displayed in the Parameter Name box. The Clear button does not delete a parameter, but clears the value shown in the Parameter Value field to <none>.

The Delete button changes to Clear if you have selected a predefined parameter (i.e., a parameter created in the Symbol File for the function and which cannot be deleted). When you clear a predefined parameter, its value is set to <none>. The Compiler looks for parameter values using the parameter value search order.

You can also clear, but not delete, a parameter defined for the current symbol instance (i.e., parameters entered with this dialog box) by typing <none> in the Parameter Value box and choosing Change.


Edit Ports/Parameters dialog box

Click Button 1 on any item in this dialog box for information on that item:


Update Symbol Command (Graphic Editor)
Update Symbol Command (Symbol Menu)

Updates one or more symbols that have changed since they were added to the current Graphic Editor file.

When you edit a symbol or when an automatically-generated symbol changes to reflect different inputs and outputs, instances of that symbol that have been entered in a Graphic Editor file need to be updated to the new version. Updating symbols ensures that the file will compile properly.

If you change the Symbol File using Create Default Symbol or by editing the file in the Symbol Editor, you must use Update Symbol to update the symbol. You do not need to use Update Symbol, however, if you use Edit Ports/Parameters to customize an individual megafunction or macrofunction symbol in your GDF.

Click Button 1 on any item in this dialog box for information on that item:

If the symbol border or pinstubs have changed, you must ensure that node and bus connections have not been broken and that the symbol does not overlap other objects in the file. Use Find Node in Design File (Utilities menu) to search for all occurrences of the updated symbols and edit the file accordingly.

Refer to Guidelines for Working with OrCAD Schematic Files for important information on editing symbols in OrCAD Schematic Files.

See also:

Creating the Default Symbol for a File

Customizing a Mega- or Macrofunction’s Ports & Parameters

Editing the Symbol for a File

Finding Nodes & Pins in the Floorplan Editor

Finding Nodes & Symbols in Design Files

Selecting an Object

Updating a Symbol in a Graphic Editor File


Update

All Occurrences of Selected Symbol(s)	Updates only the selected symbol(s) in the file. You can select multiple symbols with area or object-by-object selection.

All Symbols in the File	Updates all the symbols in the file.


Graphic: Update Symbol dialog box
Update Symbol dialog box

Click Button 1 on any item in this dialog box for information on that item:


Enter Pinstub Command (Symbol Editor)
Enter Pinstub Command (Element Menu)

Shortcuts

Creates a new pinstub and pinstub name in a Symbol File at the current insertion point. Enter Pinstub also allows you to modify an existing pinstub.

Click Button 1 on any item in this dialog box for information on that item:

The pinstub appears on the symbol border. The pinstub name appears both inside and outside the border. The name inside the border can be moved freely, but always maintains the logical association with the pinstub. The pinstub name outside the border cannot be moved or edited, and is not visible in the Graphic Editor. It remains in a fixed position outside the symbol to show which pinstub "x" is associated with a pinstub name.

Pinstubs and pinstub names are always displayed in the Symbol Editor window, regardless of their status (i.e., used or unused). However, pinstubs with the status Unused will not appear in the symbol in the Graphic Editor.

A node or bus drawn in a Graphic Editor file must connect to a pinstub to be recognized by the Compiler as a symbol connection.

After you modify a symbol with Enter Pinstub, you should update the symbol in existing Graphic Editor files.

Enter Pinstub is available only if you have defined an insertion point or selected an existing pinstub.

Refer to Guidelines for Working with OrCAD Schematic Files for important information on editing symbols in OrCAD Schematic Files.

See also:

Changing the Pinstub Name & I/O Type

Entering & Naming a Pinstub

Updating a Symbol in a Graphic Editor File


Graphic: Enter Pinstub dialog box
Enter Pinstub dialog box

Click Button 1 on any item in this dialog box for information on that item:


Full Pinstub Name

Specifies the full name of the pinstub. You can enter up to 32 name characters.

If you are creating or editing a symbol that represents an AHDL TDF, you can omit any single quotes (') in AHDL port names from the pinstub name.


Visible Pinstub Name

Specifies an abbreviated name for the pinstub. You can enter up to 32 name characters.

If you are creating or editing a symbol that represents an AHDL TDF, you can omit any single quotes (') in AHDL port names from the pinstub name.


I/O Type

Specifies the I/O type of the pinstub as Input Pin, Output Pin, or Bidirectional Pin.


Default Status

Specifies whether or not the pinstub displayed in the Pinstub Name field is used by the currently selected symbol.

Pinstubs and pinstub names are always displayed in the Symbol Editor window, regardless of their status. However, pinstubs with the status Unused will not appear in the symbol in the Graphic Editor.


Show Visible Pinstub Name in Graphic Editor

Specifies whether the pinstub name should be displayed when the symbol is used in a Graphic Editor file. (Regardless of whether you turn this option on, a line that indicates the pinstub location is always displayed.)


Enter Parameters Command (Symbol Editor)
Enter Parameters Command (Element Menu)

Shortcuts

Allows you to create or edit a parameter and assign parameter values for a megafunction or macrofunction.

Click Button 1 on any item in this dialog box for information on that item:

In the Graphic Editor, parameters that have been assigned a value appear on the top right corner of a symbol if Show Parameters is turned on. In the Symbol Editor, all parameters are displayed, including those with a value of <none>.

After you modify a symbol with Enter Parameters, you should update the symbol in existing Graphic Editor files.

See also:

Changing the Pinstub Name, I/O Type & Default Status

Entering a Parameter

Entering & Naming a Pinstub

Updating a Symbol in a Graphic Editor File


Parameter Name

Specifies the name of the parameter you wish to add, edit, clear, or delete.

You can either enter up to 32 name characters, or select an existing parameter from the Parameters list box.


Parameter Value

Specifies a value for the parameter displayed in the Parameter Name field.

You can either enter a decimal, binary, octal, or hexadecimal number or a quoted or unquoted string (e.g., "unsigned").

If you delete the text in the Parameter Value field and choose OK, the parameter is automatically assigned a value of <none>; the Compiler then uses the global default, a default defined higher in the hierarchy, or (if no default exists) the parameter value defined within the underlying design file.


Parameters List Box

Lists the existing parameters and parameter values for the currently selected macrofunction.

You can select a parameter in this box to fill in the Parameter Name and Parameter Value fields. You can then edit the parameter and choose Change to update the Parameters list box.

If you select an existing parameter, change the Parameter Name, and choose Add, a new parameter is created. The previously selected parameter is not overwritten and both entries appear in the Parameters list box.


Add/Change

Assigns the value shown in the Parameter Value field to the parameter specified in the Parameter Name field. The new or updated parameter is listed in the Parameters list box.

The Add button changes into the Change button if you are editing an existing parameter. Choosing OK always saves the currently selected parameter and parameter value as well as all parameters and values in the Parameters list box.

If you select an existing parameter, change the Parameter Name, and choose Add, a new parameter is created. The previously selected parameter is not overwritten and both entries appear in the Parameters list box.


Delete

Deletes the parameter displayed in the Parameter Name field.


Enter Parameters dialog box

Click Button 1 on any item in this dialog box for information on that item:


Find Text Command (Graphic Editor)
Find Text Command (Utilities Menu)

Shortcuts

Searches from the insertion point for the first occurrence of the specified text in the current file.

Click Button 1 on any item in this dialog box for information on that item:

After the first occurrence of the search text is found, you can choose Find Next or Find Previous (Utilities menu) to continue the search.

Find Text finds only the text that is displayed in the Graphic Editor window. To display all parameters and probe and resource assignments, turn on Show All before you begin the search.

At certain display scales, text is not visible. You can choose Normal Size or Maximum Size (View menu) to make all text visible before you begin the search.

See also:

Finding Text

Finding & Replacing Text


Types of Text to Find

Node & Bus Names	Finds only the text that occurs in node or bus names.

Text in Symbols	Finds any type of text that occurs within a symbol or in an assignment to a symbol, e.g., a pin name, symbol name, or clique assignment. Text that occurs in parameters and probe and resource assignments is found only if they are displayed. You can turn on Show All (Options menu) to display all assignments

Comments	Finds only the text that occurs in comments.

All 	Finds all occurrences of the specified search text.


Graphic: Find Text dialog box (Graphic Editor)
Find Text dialog box

Click Button 1 on any item in this dialog box for information on that item:


Find Text Command (Symbol Editor)
Find Text Command (Utilities Menu)

Shortcuts

Searches from the insertion point for the first occurrence of the specified text in the current file.

Click Button 1 on any item in this dialog box for information on that item:

After the first occurrence of the search text is found, you can enter Find Next or Find Previous (Utilities menu) to continue the search.

See also:

Finding Text

Finding & Replacing Text


Graphic: Find Text dialog box (Symbol Editor)
Find Text dialog box

Click Button 1 on any item in this dialog box for information on that item:


Find Node Source & Destination Commands (Graphic Editor)
Find Node Source & Destination Commands (Utilities Menu)

Locates the source or destination(s) of the selected node or bus.

Command:	Action:

Find Node Source	Finds the source of a selected node or bus. The entire network of wires (lines) is selected, including portions of the network that are connected by name only, and the symbol that feeds the selected node or bus. Shortcuts

Find Node Destination	Finds the destination of a selected node or bus. The entire network of wires is selected, including portions of the network that are connected by name only, and the first symbol that is fed by the selected node or bus. Shortcuts

You can choose Find Next (Utilities menu) to locate the next source or destination symbol (if any). It is not necessary to reselect the line segment to locate additional destinations. Continue choosing Find Next to locate all sources or destinations.

Double-clicking Button 1 on a node or bus line with the Selection tool ( [image]) selects all lines that are graphically connected to that line.

See also:

Finding a Node Source or Destination

Selecting a Node Network


Find Next Command (Graphic & Symbol Editors)
Find Next Command (Utilities Menu)

Shortcuts

Locates the next occurrence of the search text specified with Find Text or Search & Replace, or the next source or destination of a node or bus selected for Find Node Source or Find Node Destination.

Choose Find Next to continue the action of the following Utilities menu commands:

Command:	Action:

Find Text	Finds the next occurrence of the search text and selects it for edit. If you specified Down, Find Next searches from the top to the bottom of the file; if you specified Up, it searches from the bottom to the top.

Search & Replace	Same as Find Text.

Find Node Destination	Finds the next destination of the selected node or bus (if any).

Find Node Source	Finds the next source of the selected node or bus (if any).

See also:

Finding a Node Source or Destination

Finding Text

Finding & Replacing Text


Find Previous Command (Graphic & Symbol Editors)
Find Previous Command (Utilities Menu)

Shortcuts

Locates the previous occurrence of the search text specified with Find Text or Search & Replace, or the previous source or destination of a node or bus selected for Find Node Source or Find Node Destination.

Choose Find Previous to continue the action of the following Utilities menu commands:

Command:	Action:

Find Text	Searches opposite to the direction specified in Find Text. Finds the next occurrence of the search text and selects it for edit. If you specified Down, Find Next searches from the bottom to the top of the file; if you specified Up, it searches from the top to the bottom.

Search & Replace	Same as Find Text.

Find Node Destination	Finds the previous destination of the selected node or bus (if any).

Find Node Source	Finds the previous source of the selected node or bus (if any).

See also:

Finding a Node Source or Destination

Finding Text

Finding & Replacing Text


Search & Replace Command (Graphic Editor)
Search & Replace Command (Utilities Menu)

Shortcuts

Searches from the insertion point for specified text in the current file and replaces it.

Click Button 1 on any item in this dialog box for information on that item:

If the Graphic Editor locates the search text when the Confirm Each Change option is turned on, a dialog box appears. Click Button 1 on any item in this dialog box for information on that item:

After you finish using the Search & Replace command, you can choose Find Text, Find Next, or Find Previous (Utilities menu) to continue the search.

At certain display scales, text is not visible. You can choose Normal Size or Maximum Size (View menu) to make all text visible before you begin the search.

See also:

Finding Text

Finding & Replacing Text


Types of Text to Find

Node & Bus Names	Finds only the text that occurs in node and bus names.

Editable Text in Symbols	Finds only the editable text that occurs within a symbol, e.g., a pin name or pin default value.

Comments	Finds only the text that occurs in comments.

All 	Replaces all occurrences of the specified search text.


Graphic: Search and Replace dialog box (Graphic Editor)
Search & Replace dialog box

Click Button 1 on any item in this dialog box for information on that item:


Search & Replace Command (Symbol Editor)
Search & Replace Command (Utilities Menu)

Shortcuts

Searches from the insertion point for specified text in the current file and replaces it.

Click Button 1 on any item in this dialog box for information on that item:

If the Symbol Editor locates the search text when the Confirm Each Change option is turned on, a dialog box appears. Click Button 1 on any item in this dialog box for information on that item:

After you finish using the Search & Replace command, you can choose Find Text, Find Next, or Find Previous (Utilities menu) to continue the search.

See also:

Finding Text

Finding & Replacing Text


Graphic: Search and Replace dialog box (Symbol Editor)
Search & Replace dialog box

Click Button 1 on any item in this dialog box for information on that item:


Text Size Commands (Graphic & Symbol Editor)
Text Size Commands (Options Menu)

Shortcuts

Apply a text size to a selection or set the size for new text entry.

A variety of text sizes between 6 and 96 points are available for TrueType fonts installed on your computer. The Altera font is available in 7, 10, and 12 point sizes for use in the MAX+PLUS II Graphic and Symbol Editors.

Commands on the Text Size submenu apply the specified text size to all text blocks that have been selected in the file. If no text is selected, the current active text size is changed, so that all new text entered is in the specified text size.

The Text Size drop-down list box on the toolbar also displays the current text size. You can type a text size or choose a text size in this drop-down list box.

See also:

Changing the Text Size

Copying, Cutting & Pasting Text

Entering a Text Block (Comment)

Selecting an Object


Font Commands (Graphic & Symbol Editors)
Font Commands (Options Menu)

Shortcuts

Apply a font to a selection or set the font for new text entry.

MAX+PLUS II provides the Altera font and any TrueType fonts installed on your computer.

Commands on the Font submenu apply the specified font to all selected text blocks in the file. If no text is selected, the current active text size is changed, so that all new text entered is in the specified size.

The Font drop-down list box on the toolbar also displays the current font. You can type a font name or choose a font in this drop-down list box.

See also:

Changing the Font

Changing the Text Size

Entering a Text Block (Comment)


Line Style Commands (Graphic & Symbol Editors)
Line Style Commands (Options Menu)

Shortcuts

Apply a line style to a selection or set the line style for new line entry with the Orthogonal Line tool and the Diagonal Line tool. The following line styles are available:

The default line style is the solid line style.

Commands on the Line Style submenu apply the specified line style to all selected lines in the file. If no lines are selected, the active line style is changed, so that all new lines entered are in the new style.

The Line Style drop-down list box on the toolbar also displays the current line style. You can choose a line style in this drop-down list box in exactly the same way as in the Line Style submenu.

Although the Compiler interprets all line styles as logical connections, Altera recommends using the first style on the Line Style submenu for drawing nodes. To draw buses you must use the second style on the Line Style submenu.

See also:

Changing the Line Style

Drawing a Line


Rubberbanding Command (Graphic & Symbol Editors)
Rubberbanding Command (Options Menu)

Shortcuts

Turns the rubberbanding function on or off.

When rubberbanding is on, you can move any symbol(s) or an area while preserving signal connectivity. Connectivity is retained for orthogonal and diagonal node and bus lines that end on a symbol border or pass through an area marquee, regardless of where the symbol(s) or area is moved. The Graphic Editor automatically lengthens or shortens orthogonal or diagonal lines to maintain connections.

If you move a selection in such a way that it causes node or bus lines to overlap, the Graphic Editor alerts you and allows you to cancel the move or replace orthogonal lines with diagonal lines that preserve connectivity.

It may be necessary to turn Rubberbanding off when moving or editing a selection.

Rubberbanding does not occur for arcs that connect symbols or other objects.

See also:

Moving an Object

Turning Rubberbanding On or Off


Show Assignment/Parameters Commands (Graphic Editor)
Show Assignment/Parameters Commands (Options Menu)

Probe and resource assignments can be shown only in the Graphic Editor window. Parameters can be shown in both the Graphic and Symbol Editor windows.

Display or hide any or all probe and resource assignments. Show me

Command:	Action:

Show Parameters	Displays or hides parameters from view.

Show Probes	Displays or hides probe assignments from view. Probes are attached to an input or output of a symbol.

Show Pins/Locations/Chips	Displays or hides pin, logic cell, and chip assignments from view. Pin, logic cell, and chip assignments are attached to the bottom left corner of a symbol. Note that pin assignments on pin primitives (INPUT, INPUTC, OUTPUT, OUTPUTC, BIDIR, and BIDIRC) appear to the left or right of the symbol.

Show Cliques & Timing Assignments	Displays or hides both clique and timing assignments from view. Clique and timing assignments are attached to the top left corner of a symbol.

Show Logic Options	Displays or hides logic option assignments and/or logic synthesis style assignments from view. Logic options are attached to the bottom right corner of a symbol.

Show All	Displays or hides all probe and resource assignments. Shortcuts

See also:

Assigning a Clique

Assigning a Pin, Location, or Chip

Assigning a Probe

Assigning an Individual Logic Option or Synthesis Style

Assigning Individual Timing Requirements

Showing Parameters and Probe & Resource Assignments


Snap to Grid Command (Symbol Editor)
Snap to Grid Command (Options Menu)

Shortcuts

Turns the "magnetic" drawing grid that pulls objects to the nearest grid unit (GU) boundary on or off.

Snap to Grid is used to position text blocks and other objects with precision. If Snap to Grid is on, any object you place or move is pulled to the nearest GU boundary.

The Symbol Editor’s grid is permanently set to 1 by 1 grid units.

Although the grid is invisible, you can set Guideline Spacing to 1 by 1 grid units and turn on Show Guidelines (Options menu) for a reference.

See also:

Changing the Guideline Spacing

Showing Guidelines

Snapping to the Grid


Show Guidelines Command (Graphic & Symbol Editors)
Show Guidelines Command (Options Menu)

Shortcuts

Displays or hides guidelines from view.

Guidelines help you align objects in the file. Spacing between the guidelines is set with Guideline Spacing (Options menu).

This command has no effect on the Snap to Grid (Options menu) function in the Symbol Editor.

See also:

Changing the Guideline Spacing

Showing Guidelines


Guideline Spacing Command (Graphic & Symbol Editors)
Guideline Spacing Command (Options Menu)

Specifies the X (horizontal) and Y (vertical) spacings for guidelines.

Click Button 1 on any item in this dialog box for information on that item:

If the guidelines are not visible, you can display them by turning on Show Guidelines (Options menu). When the guidelines are visible, their X and Y coordinates appear along the top and left edges of the drawing, reflecting the current guideline spacing.

See also:

Changing the Guideline Spacing

Showing Guidelines


X and Y Spacing

Specifies the X (Horizontal) and Y (Vertical) spacing values. The spacing values must be an integer between 1 and 999, where each number represents one grid unit.


Graphic: Guideline Spacing dialog box
Guideline Spacing dialog box

Click Button 1 on any item in this dialog box for information on that item:


Example: Macrofunctions

The following example connects two macrofunctions that are assigned to two different chips.


Example: Global Clock

The following example routes a global Clock, calculated_clk, back in the device via a dedicated global input pin. The same technique can be used to route other global signals.


Example: Bidirectional bus

The following example ties several bus signals together into a bidirectional bus.


Example: Global signal and logic signal on the same device

The following example connects a logic signal and a global Clock signal.


Edit Pin Name Command (Graphic Editor)
Edit Pin Name Command (Button 2 Menu)

Shortcuts

Selects an existing pin name for editing.

Pressing Button 2 on a pin and choosing Edit Pin Name from the pop-up menu selects the existing pin name and allows you to type a new name.

You can edit the pin name text field, but you cannot leave the field empty.

See also:

Changing the Pin Name or Default Value


Edit Node/Bus Name Command (Graphic Editor)
Edit Node/Bus Name Command (Button 2 Menu)

Shortcuts

Selects an existing node or bus name for edit or allows you to enter a node or bus name on a selected node or bus line.

Pressing Button 2 on an existing node or bus name and choosing Edit Node/Bus Name selects the existing name and allows you to type a new node or bus name.

Pressing Button 2 on an unnamed node or bus line and choosing Edit Node/Bus Name selects the line and defines an insertion point for text entry.

See also:

Naming a Node or Bus


Enter Node/Bus Name Command (Graphic Editor)
Enter Node/Bus Name Command (Button 2 Menu)

Allows you to enter a node or bus name on a line.

Pressing Button 2 on a node or bus line and choosing Enter Node/Bus Name defines an insertion point and allows you to type a node or bus name.

Pressing Button 2 on a named node or bus line and choosing Enter Node/Bus Name selects the existing node or bus name and allows you to edit the existing name just as you would with Edit Node/Bus Name.

If you choose Enter Node/Bus Name on a line where the existing name lies off the current screen, MAX+PLUS II automatically scrolls to display the existing name for edit.

See also:

Naming a Node or Bus


Edit Pin Default Value Command (Graphic Editor)
Edit Pin Default Value Command (Button 2 Menu)

Shortcuts

Selects the pin default value on a pin primitive for edit.

Pressing Button 2 on a pin primitive and choosing Edit Pin Default Value from the pop-up menu selects the existing default value and allows you to type a new default value of VCC or GND.

You can edit the default value text field, but you cannot leave the field empty.

See also:

Changing the Pin Name or Default Value


Edit Selected Text Command (Graphic & Symbol Editors)
Edit Selected Text Command (Button 2 Menu)

Shortcuts

Selects an existing block of free-floating text (i.e., a comment) for editing.

Pressing Button 2 on an existing comment and choosing Edit Selected Text from the pop-up menu selects the existing comment and allows you to type a new comment. Once the text has been selected, you can also use the mouse to define a new insertion point within the text, i.e., you can edit the existing text without deleting the previous text.

See also:

Selecting Text

Entering a Text Block (Comment)


Enter Text Command (Graphic & Symbol Editors)
Enter Text Command (Button 2 Menu)

Creates a text insertion point in blank space.

Pressing Button 2 in a blank space and choosing Enter Text from the pop-up menu defines an insertion point and allows you to type the desired text.

See also:

Entering a Text Block (Comment)


Toggle Connection Dot Command
Toggle Connection Dot Command (Edit Menu)

Shortcuts

Enters or deletes a connection dot on a node or bus line.

When you draw a node line that meets another at a "T" intersection, a connection dot is entered automatically.

See also:

Entering a Connection Dot


--------------------------------------BEGINNING OF NON-TRANSLATED TEXT-----------------------------------------

The following G2CMSGS.MSG messages that are documented elsewhere (not in this file):

FG2C_CLOSE_FAILED	GLMESS.MAC

EG2C_ILL_PART_NAME	GLMESS.MAC

EG2C_ILL_MACROFUNC_NAME	HRMESS.MAC

EG2C_DUPLICATE_PIN_NAME	COMESS.MAC

EG2C_NODE_MISSING_SOURCE	COMESS.MAC

WG2C_BAD_PART_NAME	GLMESS.MAC

WG2C_INVALID_TURBO_OPTION	GLMESS.MAC

WG2C_INVALID_SECURITY_OPT	GLMESS.MAC

FG2C_COMMAND_LINE	not used in M+2

---------------------------------------END OF NON-TRANSLATED TEXT-----------------------------------------


Bus name is allowed only on bus line -- <bus name> {ID <net ID number>)
Bus name is allowed only on bus line -- <bus name> (ID <net ID number>)

CAUSE:	A single node (a thin line) with the specified net ID number has a bus name associated with it. Bus names may only be used to identify buses, i.e., wide lines, in a Graphic Editor file.

ACTION:	Rename the node or, if a bus is required, change the thin line to a bus line.

See also:

Changing the Line Style

MAX+PLUS II Messages

Message Format

Naming a Node or Bus


Cant assign a pin to pin <name> [and pin <name>] because one or more pins have the same name

CAUSE:	You assigned a pin number to a pin name, but one or more pins also have that same name. You can only assign a pin number to a pin that has a unique name. This message may also occur if you copy a pin primitive that has a pin assignment, or if you have two pins with the same name and attempt to enter an assignment on one of them.

ACTION:	Ensure that all pin names are unique, then make the assignment again. If you received this message after copying a pin primitive with an assignment, the duplicate assignment is automatically discarded.

See also:

Assigning a Pin, Location, or Chip

Changing the Pin Name or Default Value (Graphic Editor)

MAX+PLUS II Messages

Message Format

Pin & Node Names (Graphic Editor)


Cant recognize symbol <name> (ID <net ID number>)

CAUSE:	The Compiler found an unrecognizable symbol.

ACTION:	Open the design file thatthe symbol represents and choose Create Default Symbol (File menu) to automatically generate a new symbol for the file. Then use Update Symbol (Symbol menu) to update any occurrences of the symbol in a GDF, save the changes, and recompile the project.

See also:

Creating the Default Symbol for a File

MAX+PLUS II Messages

Message Format

Updating a Symbol in a GDF


Connected pin <name> (ID <net ID number>) can't drive logic

CAUSE:	The specified pins external connection pinstub is connected to logic. An external connection pinstub can only be connected to another external connection pinstub.

ACTION:	Connect the specified external connection pinstub to the external connection pinstub of an appropriate external connection pin primitve.

See also:

Assigning Connected Pins

MAX+PLUS II Messages

Message Format


Ignored primitive/macrofunction symbol (ID <net ID number>) -- it has no output
Ignored primitive/macrofunction symbol <symbol> (ID <net ID number>) -- it has no output

CAUSE:	The specified symbol has been ignored by the Compiler because its output(s) are unconnected.

ACTION:	You should connect the output(s) to another symbol or delete the specified symbol from the design file.

See also:

Bus-to-Macrofunciton Connections

Deleting an Object

MAX+PLUS II Messages

Message Format

Primitive/Port Interconnections


Illegal bus connection in pinstub <name> (ID <net ID number>) -- bus should be named

CAUSE:	An unnamed bus is connected to the specified pinstub. This message may occur if you have placed a bus name on a bus line after, rather than before, a connection dot where a second bus of a different width branches out: the Compiler cannot assume that the same bus name applies both before and after the connection dot.

ACTION:	Name the bus or move the bus name so that it is before the connection dot.

See also:

Bus-to-Macrofunciton Connections

Bus Names

MAX+PLUS II Messages

Message Format

Naming a Node or Bus

Primitive Arrays

Primitive/Port Interconnections


Illegal bus range in <bus name> (ID <net ID number>)

CAUSE:	You entered a range for the specified bus that is not supported by MAX+PLUS II. You can only enter numbers between 0 and 255.

ACTION:	Re-enter the bus name with legal name characters.

See also:

MAX+PLUS II Messages

Message Format

Naming a Node or Bus


Illegal node or pin name <node/pin name> (ID <net ID number>)
Illegal node or pin name <name>  (ID <net ID number>)(<text>)

CAUSE:	The specified node or pin name contains an illegal character.

ACTION:	Use pin and node names that contain up to 32 name characters. Do not name nodes as VCC or GND.

See also:

MAX+PLUS II Messages

Message Format

Naming a Node or Bus

Pin & Node Names


Illegal pin <net ID number> default value -- <text>
Illegal pin (ID <net ID number>)default value -- <text>

CAUSE:	You entered text other than VCC or GND as the pin default value in a symbol.

ACTION:	Enter VCC or GND in the specified field.

See also:

Changing the Pin Name or Default Value

MAX+PLUS II Messages

Message Format


Network too complex <filename>
Network too complex in <filename>

CAUSE:	The network of lines and connection dots in the specified GDF is too complicated.

ACTION:	Simplify the layout of the project. Use hierarchical files if necessary.

See also:

MAX+PLUS II Messages

Message Format


No superset bus at connection -- <bus name>

CAUSE:	You have entered a connection dot to connect buses, but the resulting buses do not contain all of the bits in the other buses.

ACTION:	You may remove the connection dot or change the bus names to include the correct number of bits.

See also:

Buses

MAX+PLUS II Messages

Message Format


Node for pin <name> (ID <net ID number>) must have the same name as the pin

CAUSE:	The node name placed on the line that is attached to the output of the specified pin is not the same as the pin name.

ACTION:	Change the node name to have the same name as the input or I/O pin that feeds it (i.e., to which it is attached), or change the pin name to match the node name. You can also use the Wire Primitive to rename the node.

See also:

MAX+PLUS II Messages

Message Format

Naming a Node or Bus

Pin and Node Names

Primitive/Port Interconnections


Node has more than one name -- <node name>

CAUSE:	You have entered different node names at two different locations on the same line. The specified node name is the second name that was found. This message may also occur if a bus line completely overlaps a non-bus (i.e., node) line in a GDF created with an earlier version of MAX+PLUS II.

ACTION:	Remove one of the names. (Use only one name on each line.) If you are compiling an older GDF, try deleting and reentering bus lines--you may find a node line underneath that is causing the problem.

See also:

MAX+PLUS II Messages

Message Format

Naming a Node or Bus

Pin and Node Names


Output pinstubs [<node name>] ID <net ID number> and [<node name>] ID <net ID number> are tied together
Output pinstubs <node name> (ID <net ID number>) and <node name> (ID <net ID number>) are tied together

CAUSE:	The project contains two output nodes that are connected only by a line, i.e., the output pinstub of one symbol is connected to the output pinstub of another symbol. This type of wired OR (i.e., short-circuit) connection is not permitted. This message may also occur if two output pinstubs on the same symbol are accidentally wired together.

ACTION:	Break all wired OR connections. Always use a logic primitive to combine the signals.

See also:

MAX+PLUS II Messages

Message Format


Buses on output pinstubs [<node name>] ID <net ID number> and [<node name>] ID <net ID number> are tied together
Buses on output pinstubs <node name> (ID <net ID number>) and <node name> (ID <net ID number>) are tied together

CAUSE:	The project contains two output pinstubs that are connected only by a bus line, i.e., the output pinstub of one macrofunction is connected to the output pinstub of another macrofunction by a bus line. This message may also occur if two output pinstubs on the same macrofunction are accidentally connected by a bus line.

ACTION:	Insert wire primitives on the output pinstubs of the macrofunctions to break the buses up into their individual logic signals.

See also:

MAX+PLUS II Messages

Message Format


Pin symbol <name> (ID <net ID number>) has more than one line connected to it

CAUSE:	A GDF contains a pinstub that is connected to more than one line.

ACTION:	Delete the extra lines that should not be connected to the pinstub. Each pinstub may be connected to only one line.

See also:

Deleting an Object

MAX+PLUS II Messages

Message Format


Project has too many symbols in <filename>

CAUSE:	The specified GDF contains too many symbols (i.e., too many Altera-provided macrofunctions and/or symbols for design files that you have created).

ACTION:	Simplify the projects logic. You can divide, and thus simplify, the specified GDF's logic by using hierarchical design files.

See also:

MAX+PLUS II Messages

Message Format


Symbol <net ID number> has more than one name -- <symbol name>

CAUSE:	The symbol with the specified net ID number has more than one name.

ACTION:	Use the Symbol Editor to remove one of the symbol names.

See also:

Editing the Symbol for a File

MAX+PLUS II Messages

Message Format


Symbol <net ID number> has no name

CAUSE:	The specified symbol does not have a text attribute that identifies it as a symbol. This message may occur if you changed the symbols text attribute incorrectly.

ACTION:	Remove or replace the symbol.

See also:

Deleting an Object

Entering a Symbol

MAX+PLUS II Messages

Message Format


Symbol <name> (ID <net ID number>) has no <text>

CAUSE:	The specified symbol has no input or output pinstubs.

ACTION:	Create at least one input and one output pinstub in each symbol.

See also:

MAX+PLUS II Messages

Message Format


Symbol <name> (ID <net ID number>) overlaps another symbol

CAUSE:	The specified symbol overlaps another symbol.

ACTION:	Move one of the symbols.

See also:

MAX+PLUS II Messages

Message Format


Width mismatch in pinstub <name> (ID <net ID number>)

CAUSE:	The project contains a bus line connected to a bus pinstub that has a different number of bits than the bus. This message may also occur if you create a primitive array by connecting buses to the node pinstubs on primitives, if the bus widths on the different pinstubs are incompatible.

ACTION:	For a bus connection to a bus macrofunction, make sure the bus and bus pinstub have the same number of bits. For a primitive array, make sure the bus widths on the different node pinstubs are compatible.

See also:

Bus-to-Macrofunction Connections

Bus Names

MAX+PLUS II Messages

Message Format

Primitive/Port Interconnections


Illegal character in parameter declaration: <parameter name> = <parameter value>

CAUSE:	not yet written

ACTION:	not yet written

See also:

MAX+PLUS II Messages

Message Format


Value of <parameter name> parameter is unresolved or illegal (<value>)

CAUSE:	The parameter value you defined for this parameter is cannot be resolved or is already used in another expression.

ACTION:	Give the parameter a legal value.

See also:

MAX+PLUS II Messages

Message Format


Illegal non-hexadecimal character(s) in port inversion pattern: <character(s)>

CAUSE:	The inversion pattern for the port contains illegal non-hexadecimal characters.

ACTION:	Correct the pattern.

See also:

MAX+PLUS II Messages

Message Format


-----BEGINNING OF NON-TRANSLATED TEXT-----

The following FI_MSGS.MSG messages are not documented in this file:

EFI_ILLEGAL_CLK_IO	COMESS.MAC

EFI_REPORT_FILE_OPEN_ERRORF	GLMESS.MAC

EFI_TOO_MANY_DUALS	COMESS.MAC

EFI_TOO_MANY_EXPANDERS	COMESS.MAC

EFI_TOO_MANY_INPUT_IO	COMESS.MAC

EFI_TOO_MANY_IO	COMESS.MAC

EFI_TOO_MANY_LAB_EXP	COMESS.MAC

EFI_TOO_MANY_LAB_IO	COMESS.MAC

EFI_TOO_MANY_LAB_PIA	COMESS.MAC

EFI_TOO_MANY_MACROCELLS	COMESS.MAC

EFI_TOO_MANY_MCELL_EXP	PARTMESS.MAC

EFI_TOO_MANY_OUTPUTS	COMESS.MAC

EFI_TOO_MANY_PIA_INPUTS	PARTMESS.MAC

FFI_PROJECT_TOO_COMPLEX	COMESS.MAC

mfi_prj_cfg_value_not_def	glmess.mac

mfi_mp2_cfg_value_not_def	glmess.mac

-----END OF NON-TRANSLATED TEXT-----


BIDIR pin <name> cannot feed <signal name>
 BIDIR pin <name> cannot feed global <text>

CAUSE:	A bidirectional pin (BIDIR or BIDIRC)cannot be the source for the specified global signal.

ACTION:	Remove the GLOBAL buffer that the bidirectional pin feeds, or change the logic so that the destination of this signal is a dedicated input.

See also:

MAX+PLUS II Messages

Message Format

Primitive Interconnections


 BIDIR pin <name> must have same pin assignments

CAUSE:	You have assigned different pin numbers to the specified pin name, which is listed in both the Inputs and Outputs sections of an SMF or ADF. When bidirectional pins are used, both pin assignments must be the same.

ACTION:	Ensure that each bidirectional pin name is assigned to the same pin number in both sections.

See also:

Assigning a Pin, Location, or Chip

Deleting an Assignment

MAX+PLUS II Messages

Message Format


Can’t find a fit for this project, though one may exist

CAUSE:	Your project is too complex to be automatically fitted by the Compiler’s Fitter module.

ACTION:	Try to fit the project manually by with pin, logic cell, chip, and/or clique assignments. Please contact Altera Applications for assistance: it will help us improve future versions of MAX+PLUS II.

See also:

Adjusting the Fit During Compilation

Assigning a Clique

Assigning a Pin, Location, or Chip

Fitting & Refitting a Project

MAX+PLUS II Messages

Message Format


Can’t find legal LAB for <node name>

CAUSE:	The current device cannot accommodate all of the resources required by your project (e.g., input or output pins, logic cells, or expanders), so the Fitter is unable to find a suitable location for the logic associated with the specified node.

ACTION:	Try to simplify the project’s logic by inserting LCELL or SOFT buffers into the design files. During project processing, these buffers may allow the Compiler to reduce the number of unique inputs in the project. You may need to use a different (higher-capacity) device, or partition the project.

See also:

Devices & Adapters

MAX+PLUS II Messages

Message Format

Partitioning a Project


Can’t assign pin to <macrocell>
Can’t find legal pin or logic cell for <node name>

CAUSE:	The current arrangement of other logic in the device is such that the Fitter cannot find a suitable location for the specified pin or logic cell.

ACTION:	Try to simplify the project’s logic by inserting LCELL or SOFT buffers into the design file. During project processing, these buffers may allow the Compiler to reduce the number of unique inputs in the project. You may need to use a different (higher capacity) device, or partition the project.

See also:

Assigning a Clique

Assigning a Pin, Location, or Chip

Devices & Adapters

Fitting & Refitting a Project

MAX+PLUS II Messages

Message Format

Partitioning a Project


Can’t partition project into rows
Can’t partition project into rows <text>

CAUSE:	The Fitter was unable to legally partition a FLEX 8000, FLEX 10K or MAX 9000 project into rows. In FLEX 8000 or FLEX 10K projects, this message may occur when a project has a large number of unique secondary inputs or a large number of carry or cascade chains. In MAX 9000 projects, this message may occur when a project has too many expander product terms.

ACTION:	For FLEX 8000 or FLEX 10K projects, change your project to use fewer unique secondary inputs, or, for non-speed-critical parts of your project, turn off the Carry Chain and Cascade Chain logic options. You can also turn on the Output Pins Fed by Carry Chains option in the expanded  Fitter Settings dialog box (Processing menu) to direct the Compiler to insert LCELL buffers automatically if an output pin that is fed by a carry chain would otherwise prevent the project from fitting.

For MAX 9000 projects, change your project to use fewer expander product terms. You can also turn on the Multi-Level Synthesis option in the Global Project Logic Synthesis dialog box (Assign menu). In addition,you can specify a smaller percentage for Fan-In per Logic Cell in the expanded Fitter Settings dialog box.

For all projects, you can also turn on the Row Pins with Fan-Out Greater Than % of the Logic Cells per Row option in the expanded Fitter Settings dialog box and specify a small percentage (e.g., 10%). This option directs the Compiler to insert LCELL buffers automatically if row pins that have a fan-out greater than the specified percentage of the logic cells per row would otherwise prevent the project from fitting.

See also:

Fitting & Refitting a Project

MAX+PLUS II Messages

Message Format

Specifying Fitter Settings


Can’t partition row <letter> into LABs
Can’t partition row <letter> into LABs <text>

CAUSE:	The Fitter was unable to legally partition a FLEX 8000, FLEX 10K, or MAX 9000 project into LABs. In FLEX 8000 projects, this message may occur when a project has a large number of unique secondary inputs or a large number of carry or cascade chains. In MAX 9000 projects, this message may occur when a project has too many expander product terms or when a logic cell requires too many fan-ins.

ACTION:	For FLEX 8000 of FLEX 10K projects, change your project to use fewer unique secondary inputs, or, for non-speed-critical parts of your project, turn off the Carry Chain and Cascade Chain logic options.

For MAX 9000 projects, change your project to use fewer expander product terms or reduce the number of fan-ins. You can also turn on the Multi-Level Synthesis option in the Global Project Logic Synthesis dialog box (Assign menu).

See also:

MAX+PLUS II Messages

Message Format


Can’t put both <pin name> and <pin name> on <text>
Can’t put both <pin name> and <pin name> on <text> <number>

CAUSE:	You have assigned two different pin names to the same pin number (or logic cell number if you are using buried logic). This message may also occur if one of the pins is a reserved configuration pin or JTAG pin. The Fitter cannot assign conflicting resources to the same pin or logic cell.

ACTION:	Assign one of the names to a different pin (or logic cell). Refer to the Pin/LC/Chip Assignments Section of the Report File for information. If one pin is a reserved configuration pin or JTAG pin, you can change the reserved status of the pin by choosing the Global Project Device Options command (Assign menu), choosing the FLEX 8000 Device Options button, and turning off the Reserved option in the Global Project FLEX 8000 Device Options (Assign menu).

See also:

Assigning a Pin, Location, or Chip

Deleting an Assignment

MAX+PLUS II Messages

Message Format


Can’t put pin <name> on dedicated global Clock input pin <number>.
Can’t put pin <name> on dedicated global Clock input pin <number>

CAUSE:	The signal assigned to the dedicated Clock pin is not a global Clock input signal.

ACTION:	Change the existing Clock into a global Clock input by inserting a GLOBAL primitive. Or, delete the pin assignment.

In an ADF, unspecified Clock inputs are treated as synchronous (global) Clock inputs in A+PLUS but are treated as array (asynchronous) Clock inputs in MAX+PLUS II. To ensure that you obtain the same fit when you compile an ADF with MAX+PLUS II, edit the original design file by inserting a GLOBAL buffer (which is the same as an SCLK buffer) at the unspecified Clock inputs, re-create the ADF (if necessary), then compile with MAX+PLUS II. For more information on converting ADFs, see Altera Design Files.

See also:

Assigning a Pin, Location, or Chip

Deleting an Assignment

MAX+PLUS II Messages

Message Format


Can’t use both <equation name> and <equation name> in flipflop <node name>

CAUSE:	You have logic implemented on two equations of a flipflop, but there is only one product term shared by both equations.

ACTION:	Change the logic so that one of those two input signals is either VCC or GND.

See also:

MAX+PLUS II Messages

Message Format


Chip <name> in device <name> has less than <number>% of <text> available for future logic changes etc.
Chip <name> in device <name> has less than <number>% of <text> available for future logic changes -- if your project is likely to change, Altera recommends using a larger device

CAUSE:	The specified chip uses a high percentage of pins or logic cells.

ACTION:	Select a larger device or ensure that your project is in its final stage. If your project is already partitioned among multiple devices, specify some of the devices’ I/O pins or logic cells to be reserved resources to allow additional logic capacity for future use. Specify a percentage for the I/O Pins or Logic Cells options under Reserved Resources in the Global Project Device Options dialog box (Assign menu).

See also:

Fitting & Refitting a Project

MAX+PLUS II Messages

Message Format


Conflicting Clock -- globally clocked register <name> conflicts with Clock input <name> that feeds the LAB

CAUSE:	You have assigned a register that is clocked by a global signal to a LAB that has a different Clock input. The Compiler cannot assign two signals with different Clocks to the same LAB.

ACTION:	Use different pin assignments or allow the Fitter to make pin assignments.

See also:

Assigning a Pin, Location, or Chip

Clearing Assignments for a Project

Deleting an Assignment

MAX+PLUS II Messages

Message Format


Device does not support array <text>

CAUSE:	An array Clock or array Output Enable is required to successfully implement your project. However, the device you selected for the project does not support array Clock or array Output Enable.

ACTION:	Use Global Project Logic Synthesis (Assign menu) to specify an automatic global Clock and/or Output Enable signal, or select another device that supports an array Clock or array Output Enable.

See also:

Devices & Adapters

MAX+PLUS II Messages

Message Format

Specifying Global Project Logic Synthesis Settings


Device requires too many (<number>/<number>) global <text> signals

CAUSE:	There are too many GLOBAL buffers feeding the Clock, Clear, Preset, or Output Enable signals used in the device. The ratio shown is the number of signals requested to the number available in the current device.

ACTION:	Reduce the number of global signals to the number allowed, let the Partitioner partition the project, or use array signals. You can also try removing all GLOBAL primitives and directing the Compiler to select one or more automatic global signals with the Global Project Logic Synthesis command (Assign menu).

See also:

MAX+PLUS II Messages

Message Format

Partitioning a Project

Specifying Global Project Logic Synthesis Settings


Device requires too many (<number>/<number>) <text> signals

CAUSE:	In FLEX 8000 devices, there is a limit of 2 Clock, 2 Clear, and 1 Preset signal per LAB. The current device requires more signals than are available in all LABs in the device. The ratio shown is the number of signals requested to the number available in the current device.

ACTION:	Change your project to use fewer unique Clock, Clear, and Preset signals. For example, you might change a ripple counter into a carry look-ahead counter.

See also:

MAX+PLUS II Messages

Message Format


Device uses too many (<number>/<number>) I/O cell <text> signals

CAUSE:	The project requires too many of the specified type of signals to feed logic that is assigned to I/O cell registers. The ratio shown is the number of signals requested to the number available in the current device.

ACTION:	Partition the project into multiple devices, reduce the number of registers placed in I/O cell registers, or change your logic so that the I/O cell registers do not use as many of the specified type of signal.

See also:

MAX+PLUS II Messages

Message Format

Partitioning a Project


Equation for <text> input of <register name> can only be VCC or GND [or Q or !Q]
Equation for <text> input of <register name> can only be VCC or GND [or Q or NQ]

CAUSE:	The input equation for a register in the project has a general product term other than just VCC or GND (or VCC, GND, Q or NQ).

ACTION:	Replace the logic or equation with VCC or GND or try a different device that allows the logic.

See also:

Assigning a Device

Devices & Adapters

MAX+PLUS II Messages

Message Format


Externally connect global Clock signal <name> to pins <text>

CAUSE:	Your project contains a global Clock input that feeds multiple LABs in a single Classic device

ACTION:	You must physically wire multiple Clock pins together to implement the project. See the Multiple Pin Connections Section of the Report File.

See also:

MAX+PLUS II Messages

Message Format


Fitting attempt <number> ended at <time> with <number> unplaced pins or logic cells

CAUSE:	The Fitter always tries several times to fit a project. This message indicates that the Fitter has tried unsuccessfully to fit the project on the specified attempt, and that it is currently trying again, while using the information learned from previous fitting attempts.

ACTION:	No action is required. However, if the number of unplaced logic cells or pins is high, the chance of finding a fit in successive fitting attempts may be small. In this case, you may wish to cancel the compilation and contact Altera Applications for assistance.

See also:

Fitting & Refitting a Project

MAX+PLUS II Messages

Message Format

Partitioning a Project

Starting & Stopping the Compiler


Synchronous clock <pin name> can be assigned only to dedicated clock pin <number>
Global Clock <name> can be assigned only to dedicated Clock pin <number>

CAUSE:	You have assigned the specified synchronous Clock input to a pin other than the dedicated synchronous Clock pin. Synchronous Clock inputs must come from the specified dedicated Clock pin.

ACTION:	Change your assignment or allow the Fitter to make resource assignments automatically.

See also:

Assigning a Pin, Location, or Chip

Deleting an Assignment

Devices & Adapters

MAX+PLUS II Messages

Message Format


Synchronous clock conflict: <node name> versus <node name>
Global Clock conflict: <node name> versus <node name>

CAUSE:	Two nodes with different types of Clock or Latch Enable inputs have been assigned to the same LAB of a MAX 5000 device: one input is the output of a  GLOBAL primitive (synchronous), the other is an array signal (asynchronous).

ACTION:	Try one of the following remedies: use the same GLOBAL primitive output as the source of all Clock and Latch Enable inputs, remove all GLOBAL primitives, use new pin assignments to explicitly assign asynchronous and synchronous logic to different LABs, or allow the Fitter to make pin assignments or use a device from the MAX 7000 or FLEX 8000 family. If the target device has only one LAB, all Clocks must be either synchronous or asynchronous.

See also:

Assigning a Pin, Location, or Chip

Deleting an Assignment

MAX+PLUS II Messages

Message Format


Global <text> input cannot be used for another global input
Can’t use Global <text> input for another global input

CAUSE:	The specified global Clock, Output Enable, Preset, or Clear signal is also used as another type of global signal. For example, this message can occur if you use the same signal as both a Clock and a Preset.

ACTION:	Use another input pin for the other signal.

See also:

MAX+PLUS II Messages

Message Format


Global signal <name> is assigned to local pin <number> in LAB <name>

CAUSE:	You assigned a signal in an EP1810 device that must be assigned to a global logic cell to a local logic cell.

ACTION:	Assign the signal to a global logic cell or let the Fitter make resource assignments automatically.

See also:

Assigning a Pin, Location, or Chip

Clearing Assignments for a Project

Deleting an Assignment

MAX+PLUS II Messages

Message Format


I/O pin cannot be used as <signal name> input

CAUSE:	You assigned the pin that feeds a GLOBAL buffer that drives a Clock, Clear, Preset, or Output Enable signal to an I/O pin on the device, which is illegal.

ACTION:	Change or delete the assignment.

See also:

Assigning a Pin, Location, or Chip

Deleting an Assignment

Devices & Adapters

MAX+PLUS II Messages

Message Format


Ignored assignment of node <name> to <location> -- <location name> is full
Ignored assignment of node <name> to <row or LAB> -- <row or LAB name> is full

CAUSE:	You have assigned the specified node to a LAB or row that is already full of user-assigned logic cells.

ACTION:	Assign the node to another LAB or row or assign fewer logic cells to the LAB or row.

See also:

Assigning a Pin, Location, or Chip

Deleting an Assignment

Fitting & Refitting a Project

MAX+PLUS II Messages

Message Format


Ignored assignment of node <name> to column -- buried nodes cannot have column assignments in the current version of MAX+PLUS II

CAUSE:	You have assigned the specified buried  node to a column. You can only assign pins or I/O cell registers to a column in the current version of MAX+PLUS II.

ACTION:	Delete the column assignment on the buried node.

See also:

Assigning a Pin, Location, or Chip

Deleting an Assignment

MAX+PLUS II Messages

Message Format


Illegal assignment of global cell <name> and input <name> on logic cell <name>

CAUSE:	You have assigned a buried global logic cell to the same location as an input pin on an EP1810 device. In this situation, the buried logic cell is unable to appropriate the I/O feedback path that drives the global bus feeding all LABs in the device. A logic cell placed under an input pin in an EP1810 device can only feed its own LAB.

ACTION:	Change the assignment so that the global logic cell is assigned to a location where an input pin is not present, or change the logic so that the logic cell feeds its own LAB.

See also:

Assigning a Pin, Location, or Chip

Deleting an Assignment

MAX+PLUS II Messages

Message Format


Illegal assignment on nondual feedback macrocell -- <name>  and <name>  on macrocell <number>
Illegal assignment on non-dual I/O feedback logic cell -- <name> and <name> on logic cell <number>

CAUSE:	You have assigned a buried logic cell and an input pin to a logic cell that does not support dual I/O feedback

ACTION:	Remove the pin assignment or assign the two items to different logic cells.

See also:

Assigning a Pin, Location, or Chip

Deleting an Assignment

MAX+PLUS II Messages

Message Format


Illegal assignment -- <name> on pin [or logic cell] <number>

CAUSE:	Your project contains an assignment to a pin or logic cell that was physically impossible. For example, an I/O pin may have been assigned to a dedicated input pin or a buried logic cell.

ACTION:	Remove or change the assignment.

See also:

Assigning a Pin, Location, or Chip

MAX+PLUS II Messages

Message Format


Illegal pin assignment -- node <name> is on pin <number>, which is <text>

CAUSE:	You assigned the specified node to a pin that is reserved for the reason specified in the message. This message may occur for global signals; you selected one of the Automatic Global Clock, Clear, Preset, or Output Enable options with the Global Project Logic Synthesis command (Assign menu), but your project contains a pin name that is assigned to the dedicated global signal pin.

ACTION:	Change or remove the pin assignment, or turn off the Automatic Global option.

See also:

Adjusting the Fit During Compilation

Assigning a Pin, Location, or Chip

Deleting an Assignment

Devices & Adapters

MAX+PLUS II Messages

Message Format

Specifying Global Project Logic Synthesis Settings


Illegal pin assignment --  pin <number> reserved for [automatic] global Clock signal <name
Illegal pin assignment -- pin <number> reserved for [automatic] global Clock signal <name>

CAUSE:	The specified pin assignment is illegal because your project contains a global Clock, Clear, Preset, or Output Enable signal that is supposed to be assigned to the pin number. This pin number can be used only for the signal input that must be driven by the specified pin. This pin number can be sued only to feed a GLOBAL primitive that drives the specified global signal, or to feed an automatic global signal created by the Compiler.

ACTION:	Change or remove the illegal pin assignment. If you enter a pin assignment for a global signal, you must assign it to the dedicated pin number specified in this message.

See also:

Assigning a Pin, Location, or Chip

MAX+PLUS II Messages

Message Format


Illegal pin assignments for logic cell <text> and pin <text>

CAUSE:	The specified logic cell and pin do not have the same pin assignments, or the logic cell is assigned to a buried logic cell rather than an I/O logic cell.

ACTION:	Edit the pin assignments for the specified logic cell and pin, or assign the logic cell to an I/O logic cell.

See also:

Assigning a Pin, Location, or Chip

MAX+PLUS II Messages

Message Format


Illegal product term on the <input name> input equation of <register name>
Illegal product term on the <text> input equation of <register name>

CAUSE:	The current device does not support Clear or Preset signals, but a design file in your project contains logic that feeds these register inputs.

ACTION:	Replace the Clear or Preset with VCC or GND, or use a different device.

See also:

Assigning a Device

Devices & Adapters

MAX+PLUS II Messages

Message Format


 Illegal setting in maxplus2.ini file: <variable> = <setting> -- setting must be ON or OFF

CAUSE:	You have entered an illegal setting for a variable in the maxplus2.ini file.

ACTION:	Usually, you should avoid editing the maxplus2.ini file. However, you can edit the file to change the specified setting to ON or OFF. Contact Altera Applications for assistance.

See also:

MAX+PLUS II Messages

Message Format


JTAG boundary-scan testing not supported in <device name>

CAUSE:	You have selected the Enable JTAG Support option in the Global Project FLEX 8000 Device Options dialog box (Assign menu), but the specified FLEX 8000 device does not support JTAG boundary-scan testing.

ACTION:	Turn off the Enable JTAG Support option. You can specify this option with the Global Project FLEX 8000 Device Options dialog box or the FLEX 8000 Individual Device Options dialog box (Assign menu).

See also:

MAX+PLUS II Messages

Message Format

Specifying Individual FLEX 8000 Device & Pin Options

Specifying Global Project FLEX 8000 Device & Pin Options


Logic Array Block <LAB name> cannot be reached by pin

CAUSE:	The specified LAB has assignments that are illegal because a logic cell in the LAB must be fed by an input pin that is currently assigned to a different row in the device.

ACTION:	Change your assignments or allow the Fitter to make the resource assignments automatically.

See also:

Assigning a Pin, Location, or Chip

Deleting an Assignment

Fitting & Refitting a Project

MAX+PLUS II Messages

Message Format


Logic Array Block <LAB name> cannot reach pin

CAUSE:	The specified LAB has assignments that are illegal because a logic cell in the LAB must feed an output pin that is currently assigned to a different column in the device.

ACTION:	Change your assignments or allow the Fitter to make the resource assignments automatically.

See also:

Fitting & Refitting a Project

MAX+PLUS II Messages

Message Format


Logic Array Block <LAB name> cannot feed the secondary input to an I/O cell

CAUSE:	The specified LAB has a carry chain or cascade chain in it that feeds the secondary input to an I/O cell signal. In FLEX 8000 devices, LC1 (i.e., the first logic cell) of a LAB always feeds the secondary input to an I/O cell. Therefore, if the second member of a carry or cascade chain feeds an I/O cell signal and the entire chain is in one LAB, the project won’t fit.

ACTION:	Assign the source of the signal to LC1 of an LAB, or insert an LCELL between the I/O cell signal and the carry chain that feeds it.

See also:

MAX+PLUS II Messages

Message Format


Logic Array Block <LAB name> requires too many [(<number>/<number>)] <resource> [as a result of user assignments]

CAUSE:	Your project calls for more of the specified resource than is available in the specified LAB. Some messages show the ratio of the number of resources requested to the number available in the specified LAB or indicate that the problem results from resource assignments entered in the project’s design files.

ACTION:	If the specified resource is input from the PIA, try to simplify the project’s logic by inserting SOFT or LCELL buffers. During project processing, these buffers may allow the Compiler to reduce the number of unique inputs that feed the LAB. If the specified resource is I/O pins or inputs from the PIA, you can also try removing or changing pin assignments. If the specified resource is Clock, Clear, or Preset signals, change your assignments so that you do not assign as many unique signals of that type to the specified LAB, or change the project so that it uses fewer unique signals of that type. If the preceding remedies do not help, you may need to use a larger device, or partition the project into smaller functional parts.

For MAX 9000 projects, you can also turn on the Multi-Level Synthesis option in the Global Project Logic Synthesis dialog box (Assign menu). You can also specify a small percentage (e.g., 10%) for the Fan-In per Logic Cell option in the expanded Fitter Settings dialog box (Processing menu). This option specifies the percentage of fan-in allowed per logic cell, relative to the default value for the device family.

See also:

Fitting & Refitting a Project

Implementing LCELL & SOFT Primitives (AHDL)

MAX+PLUS II Messages

Message Format

Partitioning a Project

Recommended reading:

AB77 (Fitting Complex Designs in MAX 5000 EPLDs)


Logic cell <name> feeds too many secondary signals on row <number> to work on the ES version of the EPF10K50 device. etc.
Logic cell <name> feeds too many secondary signals on row <number> to work on the ES version of the EPF10K50 device. This design does fit and will work in the non-ES version. Please contact Altera Applications for further assistance.

CAUSE:	The specified logic cell feeds more secondary signals (Clock Clear, or asynchronous load signals) than are allowed for the specified device. The specified device for the project is an ES version of the EPF10K50 device, which allows only a limited number of secondary signals per row to be driven by a logic cell.

ACTION:	Try the following actions:

1.	Use the non-ES version of the EPF10K50 device.

2.	In the Other Configuration Section of the project ACF, add the following line:

REDUCE_SECONDARY_LOADING_10K=ON

Turning on this option will help eliminate the error, but may impact project fitting.

3.	Create a new section in the project ACF by adding the following lines:

10kES_LOGIC_OPTION

BEGIN

     <name> : MAX_SECONDARY_FANOUT=n

END;

where 1 < n  < <total number of cells being fed>

This logic option will insert one or more LCELL primitive(s) after the specified logic cell <name> to reduce the fan-out on the secondary signal. Specifying a smaller number for n will reduce the chance of the error occurring, but may cause more LCELL primitives to be used.

4. 	In the Other Configuration Section of the project ACF, add the following line:

DESIGN_MAX_SECONDARY_FANOUT=n

where 1 < n  < <total number of cells being fed>

This logic option will insert LCELL primitives after every node that feeds secondary signals in the project to reduce the fan-out on the secondary signals. Specifying a smaller number for n will reduce the chance of the error occurring, but may cause more LCELL primitives to be used.

5.	Contact the Altera Applications Department for additional assistance.

See also:

MAX+PLUS II Messages

Message Format


Logic cell <name> must be global

CAUSE:	The specified logic must be placed on a global logic cell but all global logic cells have already been used.

ACTION:	Reduce the number of signals that this logic feeds so that it can be placed on a local logic cell instead, or contact Altera Applications for additional suggestions.

See also:

MAX+PLUS II Messages

Message Format


Output Enable source <node name> cannot feed both inverted and non-inverted signals to TRI buffers

CAUSE:	In your 7000E device project, a logic cell feeds both an inverted and non-inverted signal to two TRI buffers. The logic cell can feed either an inverted or a non-inverted signal to TRI buffers, but not both.

ACTION:	You must create a new logic cell at the output of the existing logic cell, so that one logic cell feeds an inverted signal to a TRI buffer while the other feeds a non-inverted signal to another TRI buffer.

See also:

MAX+PLUS II Messages

Message Format


New pin and/or logic cell assignments differ from those in the design file(s)

CAUSE:	The Fitter reassigned some pins and/or buried logic cells to different locations than you had specified in the original design files.

ACTION:	No action is required. However, if you wish to retain the Fitter’s pin and logic cell assignments during future compilations, you should back-annotate the assignments.

See also:

Back-Annotating Assignments for a Project

MAX+PLUS II Messages

Message Format


No dual I/O feedback available in logic cells in this device

CAUSE:	The device does not support both I/O and logic cell feedbacks in a single logic cell, i.e., it does not support dual I/O feedback.

ACTION:	Try using either one of the feedbacks in a single logic cell, or use Classic EP1810, MAX 5000, or MAX 7000 devices, which contain dual I/O feedback logic cells.

See also:

Assigning a Device

Devices & Adapters

MAX+PLUS II Messages

Message Format


No fit possible <text>
No fit possible with the current device

CAUSE:	The Fitter has determined that your project’s logic won’t fit into the target device.

ACTION:	Check the Report File to determine why the project did not fit. Change or delete your pin assignments; change the design files; try a different device; or use automatic device selection.

See also:

Assigning a Device

Assigning a Pin, Location, or Chip

Clearing Assignments for a Project

Deleting an Assignment

Fitting & Refitting a Project

MAX+PLUS II Messages

Message Format

Specifying Devices for Automatic Device Selection

Recommended reading:

AB60 (Estimating a Design Fit)


Node <name> assigned to pin <name> will not be tri-stated during device configuration

CAUSE:	During FLEX 8000 device configuration, the specified pin drives out while the rest of the pins are tri-stated.

ACTION:	You must make sure that your board will allow the specified pin to drive out during configuration, or change the pin to be a reserved pin with the FLEX 8000 Individual Device Options dialog box (Assign menu) or the  Global Project FLEX 8000 Device Options dialog box (Assign menu).

See also:

Assigning a Pin, Location, or Chip

MAX+PLUS II Messages

Message Format

Specifying Individual FLEX 8000 Device & Pin Options

Specifying Global Project FLEX 8000 Device & Pin Options

Recommended reading:

AN33 (Configuring FLEX 8000 Devices)


Node <name> assigned to row <letter>, but feeds pin <name> assigned to row <letter>

CAUSE:	The specified node is assigned to a different row than the pin that it feeds, but it can only feed pins in the same row.

ACTION:	Change your assignments or allow the Fitter to make resource assignments automatically.You can also use Fitter Settings (Processing menu) to direct the Compiler to automatically insert LCELL buffers into the project if they are needed to achieve a fit. However, when additional LCELL buffers are inserted, the project will use more logic cells and will have slower performance.

See also:

Assigning a Pin, Location, or Chip

Deleting an Assignment

Devices & Adapters

Fitting & Refitting a Project

MAX+PLUS II Messages

Message Format

Specifying Fitter Settings


Node <name> assigned to row <letter>, but is fed by pin <name> assigned to row <letter>

CAUSE:	The specified node is assigned to a different row than the pin that feeds it, but the pin can only feed logic cells in the same row.

ACTION:	Change your assignments or allow the Fitter to make resource assignments automatically. You can also use Fitter Settings (Processing menu) to direct the Compiler to automatically insert LCELL buffers into the project if they are needed to achieve a fit. However, when additional LCELL buffers are inserted, the project will use more logic cells and will have slower performance.

See also:

Assigning a Pin, Location, or Chip

Deleting an Assignment

Devices & Adapters

Fitting & Refitting a Project

MAX+PLUS II Messages

Message Format

Specifying Fitter Settings


Signal <name> cannot use the global I/O feedback since Output Enable is not VCC
Node <name> can’t use the global I/O feedback because Output Enable is not VCC

CAUSE:	The specified node in an EP1810 device must use the global I/O feedback, but the Output Enable is a product term. The Output Enable must be VCC for the signal to use the global I/O feedback.

ACTION:	Change the Output Enable to VCC.

See also:

MAX+PLUS II Messages

Message Format


Node <node name> carries into <node name> which is assigned to a non-adjacent location
Node <node name> carries into <node name>, which is assigned to a non-adjacent location

CAUSE:	You have assigned a node to a location that prevents it from carrying into the next node in the carry chain. Carry chains can only run between adjacent logic cells, e.g., between two adjacent logic cells in the same LAB or the last logic cell in one LAB and the first logic cell of an adjacent LAB in the same row.

ACTION:	Change the assignments.

See also:

Assigning a Pin, Location, or Chip

Deleting an Assignment

Fitting & Refitting a Project

MAX+PLUS II Messages

Message Format


Node <node name> cascades into <node name> which is assigned to a non-adjacent location
Node <node name> cascades into <node name>, which is assigned to a non-adjacent location

CAUSE:	You have assigned a node to a location that prevents it from cascading into the next node in the cascade chain. Cascade chains can only run between adjacent logic cells, e.g., between two adjacent logic cells in the same LAB or the last logic cell in one LAB and the first logic cell of an adjacent LAB in the same row.

ACTION:	Change the assignments.

See also:

Assigning a Pin, Location, or Chip

Deleting an Assignment

Fitting & Refitting a Project

MAX+PLUS II Messages

Message Format


No COCF
Node <name> has both combinatorial output and combinatorial feedback, which are not supported on this device

CAUSE:	The specified device does not support both combinatorial output and combinatorial feedback, but the specified node in the project requires it.

ACTION:	Use another device or try changing the project logic from combinatorial feedback to I/O feedback.

See also:

Assigning a Device

Devices & Adapters

MAX+PLUS II Messages

Message Format


No ROIF
Node <name> has both register output and I/O feedback, which are not supported on this device

CAUSE:	The specified device does not support both register output and I/O feedback, but the specified node in the project requires it.

ACTION:	Use another device or try changing the project logic from I/O feedback to combinatorial feedback.

See also:

Assigning a Device

MAX+PLUS II Messages

Message Format


Signal <name> has global macrocell feedback -- EP1800 only supports local macrocell feedbacks
Node <name> has global logic cell feedback -- EP1810 devices support only local logic cell feedbacks

CAUSE:	The EP1810 architecture allows only local logic cell feedback on a dual I/O feedback logic cell but this project contains a logic cell that has a global signal on the logic cell feedback and an I/O feedback.

ACTION:	Separate the signals into two logic cells, which can then be placed into two global logic cells in the device.

See also:

Assigning a Pin, Location, or Chip

MAX+PLUS II Messages

Message Format

Pin, Logic Cell & Chip Assignments


Node <name> is assigned to row <letter> as a result of input/output pin assignments etc.
Node <name> is assigned to row <letter> as a result of input/output pin assignments, but is part of a carry or cascade chain with logic cells that must be in row <letter>

CAUSE:	The specified node is assigned to one row as a result of pin assignments, but is also part of a carry chain or cascade chain with logic cells in another row.

ACTION:	Change your assignment or allow the Fitter to make resource assignments automatically. You can also set the Carry Chain, and/or Cascade Chain logic options to IGNORE to direct the Logic Synthesizer to ignore CARRY or CASCADE buffers in your design files.

See also:

Assigning a Pin, Location, or Chip

Deleting an Assignment

Devices & Adapters

Fitting & Refitting a Project

MAX+PLUS II Messages

Message Format


Node <name> is fed by both pin <name> in row <letter> and pin <name> in row <letter>

CAUSE:	The specified node is fed by pins in different rows, but a pin can only feed logic cells in the same row.

ACTION:	Change your assignment or allow the Fitter to make resource assignments automatically.

See also:

Assigning a Pin, Location, or Chip

Deleting an Assignment

Devices & Adapters

Fitting & Refitting a Project

MAX+PLUS II Messages

Message Format


Node <name> is fed by pin <name> in row <letter>, but also feeds pin <name> in row <letter>

CAUSE:	The specified node is fed by a pin in one row but also feeds a pin in a different row. A pin can only feed or be fed by a node in the same row.

ACTION:	Change the assignment, or allow the Fitter to make resource assignments automatically. You can also use Fitter Settings (Processing menu) to direct the Compiler to automatically insert LCELL buffers into the project if they are needed to achieve a fit. However, when additional LCELL buffers are inserted, the project will use more logic cells and will have slower performance.

See also:

Adjusting the Fit During Compilation

Assigning a Pin, Location, or Chip

Deleting an Assignment

Devices & Adapters

Fitting & Refitting a Project

MAX+PLUS II Messages

Message Format

Specifying Fitter Settings


Node <name> that feeds output pin <name> assigned to pin <name> also feeds etc.
Node <name> that feeds output pin <name> assigned to pin <name> also feeds an I/O cell signal. No logic cell can reach both locations simultaneously

CAUSE:	The specified node feeds a pin where none of the logic cells that can feed that pin can also feed the I/O cell signal, which is an Output Enable or the signal that feeds the Clock, Clear, Preset, or Clk Enable of an I/O cell register.Only a limited number of logic cells can feed a given horizontal pin in the device and only a limited number of logic cells can feed an I/O cell signal.

ACTION:	Use Fitter Settings (Processing menu) to direct the Compiler to automatically insert LCELL buffers into the project if they are needed to achieve a fit. However, when additional LCELL buffers are inserted, the project will use more logic cells and will have slower performance. You can also create a second node so that one node feeds the output pin while the other feeds the I/O cell signal, or change or delete the pin assignment.

See also:

Assigning a Pin, Location, or Chip

Deleting an Assignment

Fitting & Refitting a Project

MAX+PLUS II Messages

Message Format

Moving a Probe or Resource Assignment

Specifying Fitter Settings


Parallel Expanders conflict -- node <name> on <pin or LC number> cannot borrow parallel expanders

CAUSE:	You made a pin or logic cell assignments that places the specified node in a location that prevents it from using the parallel expanders required to implement the logic.

ACTION:	Change your assignments or turn off the Parallel Expanders logic option on the specified node. Using synchronous Clock and Clear signals may also help avoid parallel expander conflicts.

See also:

Assigning a Logic Option

Assigning a Pin, Location, or Chip

Deleting an Assignment

Fitting & Refitting a Project

MAX+PLUS II Messages

Message Format


Parallel Expander conflict -- node <name> on <pin or MC number> conflicts with node <name> on <pin or MC number>.
Parallel Expanders conflict -- node <name> on <pin or LC number> conflicts with node <name> on <pin or LC number>

CAUSE:	You made a pin or logic cell assignment that places the specified node in a location such that another node will prevent it from using the parallel expanders required to implement the project.

ACTION:	Change or remove your assignments or turn off the Parallel Expanders logic option on the specified node. Using synchronous Clock and Clear signals may also help avoid parallel expander conflicts.

See also:

Assigning a Logic Option

Assigning a Pin, Location, or Chip

Deleting an Assignment

Fitting & Refitting a Project

MAX+PLUS II Messages

Message Format


 Pin or logic cell <name> can’t drive an Output Enable signal

CAUSE:	In a MAX 7000E device project, you have assigned an Output Enable signal to the specified logic cell, but the physical position of this logic cell does not allow it to drive an Output Enable signal.

ACTION:	Delete the assignment.

See also:

Assigning a Pin, Location, or Chip

Deleting an Assignment

Devices & Adapters

MAX+PLUS II Messages

Message Format


Percentage specified for the Logic Cells per Row option in the Compiler’s Fitter Settings dialog box etc.
Percentage specified for the Logic Cells per Row option in the Compiler’s Fitter Settings dialog box is too low (<percentage>) -- it must be <text>

CAUSE:	You have specified a percentage for the Logic Cells per Row option in the expanded Fitter Settings dialog box (Processing menu). However, the percentage you have specified is too small for the project to fit into the selected device.

ACTION:	Change the percentage specfied for the Logic Cells per Row option. If the message gives a minimum percentage, specify a percentage that is at least as high as the specified percentage. You must also ensure that the percentage is high enough to allow a minimum of 5 fan-ins per logic cell.

See also:

Fitting & Refitting a Project

MAX+PLUS II Messages

Message Format

Specifying Fitter Settings


Pin [or logic cell] <name> can’t feed <destination> [as a result of user assignments]

CAUSE:	A pin or logic cell was not able to feed the specified destination because of routing problems caused by user-defined resource assignments.

ACTION:	Move the pin or logic cell or the pin or logic cell that it feeds. For further assistance, call Altera Applications.

See also:

Fitting & Refitting a Project

MAX+PLUS II Messages

Message Format


Project fit with the following "Advanced Try Harder/Longer Compilation" Fitter Settings etc.
Project fit with the following "Advanced Try Harder/Longer Compilation" Fitter Settings. To preserve the fit in future compilations, change to "Custom" in the Fitter Settings dialog box <text>

CAUSE:	You chose the the Advanced Try Harder/Longer Compilation Fitting option in the Fitter Settings dialog box (Processing menu). Fitting was successful when the Fitter used the Fitter settings specified in the message.

ACTION:	No action is necessary if the time required to recompile the project with the Advanced Try Harder/Longer Compilation Fitting setting is not a problem for you. To accelerate future project compilations while preserving the current fit, follow the instructions listed in the message.

See also:

MAX+PLUS II Messages

Message Format

Specifying Fitter Settings


Project requires too many (<number>/<number>) <text> logic cells

CAUSE:	You have requested more of the specified type of logic cell than are available in the target device. The ratio shown is the number of logic cells requested to the number available in the current device.

ACTION:	Try to simplify the project’s logic by inserting or removing SOFT and/or LCELL buffers. During project processing, these buffers may allow the Compiler to reduce the number of unique signals in the project. Turning off the Parallel Expanders logic option on the specific nodes may also reduce the number of logic cells required by a project. If the message indicates that too many global logic cells are required, you can try removing GLOBAL buffers and making some signals asynchronous. If the message indicates that too many dual I/O feedback logic cells are required, you can separate the input and output portions of one or more such logic cells into INPUTC and OUTPUTC external connection pin primitives that are wired together externally.You can also use the Connected Pins command (Assign menu) to specify external pin connections. Otherwise, you may also need to use a different (higher-capacity) device, or partition the project among additional devices.

See also:

Fitting & Refitting a Project

Implementing LCELL & SOFT Primitives

MAX+PLUS II Messages

Message Format

Partitioning a Project


Project requires too many (<number>/<number>) <text> pins [<text>]

CAUSE:	You have requested more of the specified type of pin than are available in the target device. The ratio shown is the number of resources requested to the number available in the current device.

ACTION:	If the specified resource is output or I/O pins, you must change the project to use fewer pins, use a different (higher-capacity) device, or partition the project among additional devices. If the message indicates that some dual-purpose pins are reserved, you can also try unreserving one or more of these pins. If the message indicates that too many pins are required if all parallel expanders are used, turn off the Parallel Expanders logic option on one or more logic functions.

See also:

Fitting & Refitting a Project

MAX+PLUS II Messages

Message Format

Partitioning a Project

Specifying Individual FLEX 8000 Device & Pin Options

Specifying Global Project FLEX 8000 Device & Pin Options


Project requires too many (<number>/<number>)  output pins, including <number> Output Enable etc.
Project requires too many (<number>/<number>) output pins, including <number> Output Enable signals implemented on logic cells

CAUSE:	You have requested more output pins than are available in the target device, including one or more Output Enable signals implemented on logic cells. The ratio shown is the number of resources requested to the number available in the current device. In MAX 7000 devices, the logic cell that generates an Output Enable must be in the position of an I/O pin. You can use this I/O pin as an input pin, but not as an output pin. If you use the I/O pin as an output pin, the Output Enable signal cannot be implemented.

ACTION:	You must change the project to use fewer pins, use a different (higher-capacity) device, or partition the project among additional devices.

See also:

Fitting & Refitting a Project

MAX+PLUS II Messages

Message Format

Partitioning a Project

Specifying Individual FLEX 8000 Device & Pin Options

Specifying Global Project FLEX 8000 Device & Pin Options


Project requires too many (<number>/<number>) shareable expanders
Project requires too many (<number>/<number>) [shareable] expanders

CAUSE:	You have requested more shareable expanders than are available in the target device. The ratio shown is the number of shareable expanders requested to the number available in the current device.

ACTION:	Change the project to use fewer EXP buffers, insert SOFT and/or LCELL buffers after EXP buffers, turn on the Multi-Level Synthesis option in the Global Project Logic Synthesis dialog box (Assign menu). During project processing, SOFT and LCELL buffers may allow the Compiler to reduce the number of unique signals in the project. You can also try turning on the Parallel Expanders logic option on one or more logic functions. Otherwise, you may also need to use a different (higher-capacity) device, or partition the project among additional devices.

See also:

Fitting & Refitting a Project

MAX+PLUS II Messages

Message Format

Partitioning a Project


Report File contains advance information
Report File contains advance information. Specifications for <device name> are subject to change. Contact Altera Marketing for information on availability [<text>]

CAUSE:	The Compiler has created a Report File that contains only preliminary information because the specified device was not yet available when the current version of MAX+PLUS II software was released.

ACTION:	If you wish to use this device, contact Altera Applications for information on its availability.

See also:

MAX+PLUS II Messages

Message Format


Turbo is set to ON for <name> -- pin assignments require borrowing and lending of parallel expanders with <name>

CAUSE:	You have assigned a node to a pin that requires a particular node to feed it. This node must lend or borrow a parallel expander from another node that has a different setting for the Turbo Bit logic option. Since these two nodes must have the same Turbo Bit setting, the Compiler has turned the Turbo Bit on for the specified node.

ACTION:	No action is required. To avoid this warning in the future, change or delete the pin assignment, or turn on the Turbo Bit logic option for the specified node.

See also:

Assigning a Pin, Location, or Chip

Deleting an Assignment

Devices & Adapters

MAX+PLUS II Messages

Message Format


The following topics must be re-checked after 6.0


Project compilation canceled by user request

CAUSE:	You chose the Stop After This Attempt or the Stop & Create Report File button in the Partitioner/Fitter Status dialog box, so compilation stopped before it was completed.

ACTION:	No action is required. You can restart compilation from the beginning with Project Save & Compile (File menu) or with the Compiler’s Start button.

See also:

MAX+PLUS II Messages

Message Format


Project requires too many (<number>/<number>) Embedded Array Blocks

CAUSE:	You have requested more Embedded Array Blocks than are available in the target device. The ratio shown is the number of EABs requested to the number available in the current device.

ACTION:	Change the project to use fewer EABs. Otherwise, you may also need to use a different (higher-capacity) device, or partition the project among additional devices.

See also:

Fitting & Refitting a Project

MAX+PLUS II Messages

Message Format

Partitioning a Project


Pin I/O cell signal <text> <name> can’t feed <name> as a result of user assignment

CAUSE:	The specified pin I/O cell signal cannot feed the specified destination due to a u.ser assignment on the I/O cell signal, the destination pin or I/O cell, or another logic cell

ACTION:	Try to simplify the project’s logic by inserting LCELL or SOFT buffers into the design file. During project processing, these buffers may allow the Compiler to reduce the number of unique inputs in the project. Or, delete the assignment.

See also:

MAX+PLUS II Messages

Message Format


Too many <text> would be required if <text> <name> were placed in <address>

CAUSE:	The specified logic cell, input, or Embedded Array Block ia assigned to the specified row, section, or Logic Array Block. However, this assignment will require too many logic cells, Output Enabledef_out_en signals, expander networks RAM bits, Clock signals, asynchronous load signals, Preset signals, expander product term, or Clock Enable signals.

ACTION:	Try to simplify the project’s logic by inserting LCELL or SOFT buffers into the design file. During project processing, these buffers may allow the Compiler to reduce the number of unique inputs in the project. Or, delete the assignment.

See also:

MAX+PLUS II Messages

Message Format


Too many output cells would be in the same column if <text> <name> were placed in <location>

CAUSE:	The specified logic cell, input, or Embedded Array Block ia assigned to the specified row, section, or Logic Array Block. However, this assignment will require too many logic cells, Output Enabledef_out_en signals, expander networks RAM bits, Clock signals, asynchronous load signals, Preset signals, expander product term, or Clock Enable signals to be in the same column.

ACTION:	Try to simplify the project’s logic by inserting LCELL or SOFT buffers into the design file. During project processing, these buffers may allow the Compiler to reduce the number of unique inputs in the project. Or, delete the assignment.

See also:

MAX+PLUS II Messages

Message Format


Can’t place <text> <name> in <location> due to other constraints

CAUSE:	Can’t place the specified pin, I/O cell, EAB, or logic celll in the appropriate position in the specified LAB because it feeds a user-assigned horizontal pin, it feeds a peripheral register as a secondary signal, or is an Output Enable signal.

ACTION:	Try to simplify the project’s logic by inserting LCELL or SOFT buffers into the design file. During project processing, these buffers may allow the Compiler to reduce the number of unique inputs in the project. Or, delete the assignment.

See also:

MAX+PLUS II Messages

Message Format


Can’t place <text> <name> in <location> to allow it to feed an assigned vertical I/O pin

CAUSE:	Can’t place the specified pin, I/O cell, EAB, or logic celll in the appropriate position in the specified LAB because it feeds a user-assigned verical pin, it feeds a peripheral register as a secondary signal, or is an Output Enable signal.

ACTION:	Try to simplify the project’s logic by inserting LCELL or SOFT buffers into the design file. During project processing, these buffers may allow the Compiler to reduce the number of unique inputs in the project. Or, delete the assignment.

See also:

MAX+PLUS II Messages

Message Format


Too many logic cells assigned to row <number>

CAUSE:	Too many logic cellsare assigned to the specified row as a result of user assignments.

ACTION:	Try to simplify the project’s logic by inserting LCELL or SOFT buffers into the design file. During project processing, these buffers may allow the Compiler to reduce the number of unique inputs in the project. Or, delete the assignment.

See also:

MAX+PLUS II Messages

Message Format


Can’t place multi-LAB chain that starts with logic cell <name>

CAUSE:	The multi-LABcarry chain that starts with the specified logic cell can not be placed in the appropriate location.

ACTION:	Try to simplify the project’s logic by inserting LCELL or SOFT buffers into the design file. During project processing, these buffers may allow the Compiler to reduce the number of unique inputs in the project. Or, change or delete the buried assignment(s).

See also:

MAX+PLUS II Messages

Message Format


Logic cell <name> feeds a vertical I/O pin <name> <text>

CAUSE:	The specified logic cell that is assigned to a column also feeds a vertical I/O pin in a different column. However the logic cell and  the vertical I/O pin that it feeds must be in the same column to fit in the selected device.

ACTION:	Try to simplify the project’s logic by inserting LCELL or SOFT buffers into the design file. During project processing, these buffers may allow the Compiler to reduce the number of unique inputs in the project. Or, delete the assignment.

See also:

MAX+PLUS II Messages

Message Format


Can’t place clique containing <name> -- clique assignment conflicts with indirect assignment(s) caused by pin assignment(s)

CAUSE:	The specified clique cannot be placed in its assigned location as a result of indirect user assignments.

ACTION:	Try to simplify the project’s logic by inserting LCELL or SOFT buffers into the design file. During project processing, these buffers may allow the Compiler to reduce the number of unique inputs in the project. Or, delete the assignment.

See also:

MAX+PLUS II Messages

Message Format


Horizontal pin assignment <name> requires logic cell <name> to be placed in same row (row <number>), <text>

CAUSE:	The specified horizontal pinassignment requires that the specified logic cell be placed in the specified row. However this placement is not allowed as result of conflicting user assignments.

ACTION:	Try to simplify the project’s logic by inserting LCELL or SOFT buffers into the design file. During project processing, these buffers may allow the Compiler to reduce the number of unique inputs in the project. Or, delete the assignment.

See also:

MAX+PLUS II Messages

Message Format


Carry or cascade chain must be placed in only one row -- logic cell <name> is assigned to row <number>, but one end of its chain
Carry or cascade chain must be placed in only one row -- logic cell <name> is assigned to row <number>, but one end of its chain, <name> is assigned to row <number>

CAUSE:	A carry chain or cascade chain starts with a logic cellin one row, and ends with a logic cell in a different row. However, the carry or cascade chain must be placed in only one  row.

ACTION:	Change the assignments  to allow the entire carry or cascade chain to be in one row. Or delete the assignments.

See also:

MAX+PLUS II Messages

Message Format


Logic cell <name>, which is part of a carry or cascade chain (with logic cell <name> at one end) cannot be assigned to row <numb
Logic cell <name>, which is part of a carry or cascade chain (with logic cell <name> at one end) cannot be assigned to row <number>, because the row is full

CAUSE:	The specified logic cell, which is part of a carry chain or cascade chain cannot be placed in the specified row because too many carry or cascade chains are assigned to the row, the carry or cascade chain is too long, or there are conflicting user assignments

ACTION:	Reduce the size of the carry chain or specify a value for the Max. Auto Length box for the Carry Chain or Cascade Chain option on the Define Synthesis Style dialog box.

See also:

MAX+PLUS II Messages

Message Format


Row <number> requires too many row FastTrack Interconnects

CAUSE:	The specified row requires more row FastTrack Interconnect than are available in the device.

ACTION:	Try to simplify the project’s logic by inserting LCELL or SOFT buffers into the design file. During project processing, these buffers may allow the Compiler to reduce the number of unique inputs in the project. Or, delete the assignment.

See also:

MAX+PLUS II Messages

Message Format


Ignored inserting a LCELL after node <name> -- cannot insert a LCELL after
Ignored inserting a LCELL after node <name> -- cannot insert a LCELL afte a global pin

CAUSE:	blah blah.

ACTION:	Try to simplify the project’s logic by inserting LCELL or SOFT buffers into the design file. During project processing, these buffers may allow the Compiler to reduce the number of unique inputs in the project. Or, delete the assignment.

See also:

MAX+PLUS II Messages

Message Format


TDO File was not generated -- project contains encrypted design file

CAUSE:	You have turned on the Generate AHDL TDO File command (Processing menu), but the Compiler could not generate an AHDL Text Design Output File because the project contains an encrypted design file.

ACTION:	No action is required. You can not generate TDO Files from encrypted design files.

See also:

MAX+PLUS II Messages

Message Format


Floorplan Editor Basic Tools
Basic Tools

Assignment Bins

LAB Assignment Bin

EAB Assignment Bin

Row Assignment Bin

Column Assignment Bin

Device Assignment Bin

Color Legend

Fields

Chip Name Field

Unassigned Nodes & Pins Box

Selected Node(s) & Pin(s) Field

Floorplan Displays

Device View

LAB View

Input & Output Files

Assignment & Configuration File (.acf)

ACF Format

Fit File (.fit)

MAX+PLUS II Initialization & System Files

maxplus2.idx File

maxplus2.ini File

Mouse Behavior

Options & Buttons

Zoom In & Zoom Out Buttons

Parameters

Probe, Resource & Device Assignments

Clique Assignments

Connected Pin Assignments

Device Assignments

Guidelines for Timing Assignments

Logic Option Assignments

Pin, Location & Chip Assignments

Probe Assignments

Timing Assignments

Report File Equation Viewer

Status Bar & Toolbar

Status Bar

Toolbar


LAB, EAB, Row, Column & Device Assignment Bins (Floorplan Editor)
LAB, EAB, Row, Column & Device Assignment Bins

Implements and stores pin, logic cell (including I/O cell), and/or embedded cell assignments made to an LAB, EAB, row, column, or device. Show me

LAB, EAB, Row, Column, and Device Assignment Bins are available when you display the LAB View of the Floorplan Editor. Instead of entering an assignment to a specific pin or logic cell, you can make assignments to general locations. You can use Button 1 to drag a node or pin you wish to assign to one or more of the following types of assignment bin(s):

Type:	Description:

LAB Assignment Bin	Located at the top or bottom of each LAB. Assignment(s) made to an LAB Assignment Bin are implemented in one or more logic cells in that LAB.

EAB Assignment Bin	Located at the bottom of each EAB. Assignment(s) made to the EAB Assignment Bin are implemented in one or more embedded cells in that EAB.

"Col EAB" Bin	Located at the top of the column of EABs. Assignment(s) made to this bin are implemented in any embedded cell and/or EAB in the embedded array of the device.

Row Assignment Bin	Located beneath each row letter on the left-hand side of the display area. Nodes assigned to a Row Assignment Bin are implemented in one or more logic, I/O, or embedded cells in any location in that row; pins assigned to a Row Assignment Bin are implemented in one or more pins in that row.

"Any Row" Assignment Bin	Assignment(s) made to this bin are implemented in any row in the device.

Column Assignment Bin	Located beneath each column number at the top of the display area. Nodes assigned to a Column Assignment Bin are implemented in one or more logic, I/O, or embedded cells in any location in that column; pins assigned to a Column Assignment Bin are implemented in one or more pins in that column.

"Any Column" Assignment Bin	Assignment(s) made to this bin are implemented in any column in the device.

Device Assignment Bin	Located in the upper left-hand corner of the display area, under the label AoD, an abbreviation for Anywhere on Device. Assignment(s) made to the Device Assignment Bin are implemented in one or more logic, I/O, or embedded cells or pins in any location in the device.

When you make assignments to a bin, the total number of assignments made to a particular bin appears on the bin itself.

When you place the mouse pointer directly over an assignment bin with a single assignment, the assignment is displayed next to the bin as balloon text. When multiple logic functions are assigned to a bin, the first two items are listed in balloon text, followed by the text etc. if there are additional items. You can then use the drop-down list box in the Selected Node(s) & Pin(s) field to select a specific assignment to edit or delete.

See also:

Assigning a Pin, Location, or Chip

Viewing a Device in the Device View or LAB View


Color Legend (Floorplan Editor)
Color Legend

Shows the color scheme used to display items in the Floorplan Editor. The color legend also contains information on fan-out and routing. Show me

Altera supplies colors/identifiers for the following items in the Floorplan Editor window:

Type:	Description:

Unassigned	Node that is currently unassigned.

Unrouted	Node assigned to a location without any routing to other nodes. This occurs when the Fitter fails to achieve a fit.

Nonassignable	VCC, GND, and reserved pins.

Carry & Cascade Chains	Carry and cascade chain locations. (FLEX 8000, and FLEX 10K devices only)

Parallel Expanders	Parallel expander locations. (MAX 7000, and MAX 9000 devices only)

Row & Column FastTrack/	Node that feeds one or more other nodes along both row and

Dedicated Input	column FastTrack paths. Dedicated input pins automatically feed nodes along both rows and columns.

Row FastTrack	Node that feeds one or more other nodes along row FastTrack paths.

Column FastTrack	Node that feeds one or more other nodes along column FastTrack paths.

Local LAB Fan-Out Only	Node that feeds one or more other nodes within the same LAB.

Device-Wide Fan-Out	Node that feeds one or more other nodes anywhere in the device.

1.	The Routing Statistics command provides additional information to distinguish between carry and cascade chains.

2.	The routing information displayed in the Color Legend is available only for projects compiled with MAX+PLUS II version 5.2 or higher. You must recompile projects created with earlier versions of MAX+PLUS II to view their routing information in the Floorplan Editor.

See also:

Showing Node Fan-In or Fan-Out

Showing Routing Statistics


Chip Name Field (Floorplan Editor)
Chip Name Field

Specifies the name of a chip in the current project. The name of the device assigned to the chip also appears in parentheses after the chip name. Show me

The Device View or LAB View shows the device assigned to the chip, unless you have assigned a chip to AUTO.

If your project contains multiple chips, you can select a chip name from the drop-down list box to display the device assigned to that chip and its current assignments. You can assign a chip to a device with Device.

See also:

Assigning a Device


Unassigned Nodes & Pins Box (Floorplan Editor)
Unassigned Nodes & Pins Box

Lists all nodes and pins in the current project that are unassigned or illegally assigned. Show me

The Unassigned Nodes & Pins box lists the node and pin names in alphanumerical order. A node "handle" appears to the left of the name to indicated whether the node represents input pins, output pins, buried logic, or memory nodes. If you choose Last Compilation Floorplan (Layout menu), unrouted (i.e., illegally assigned) node and pin names are displayed in red.

To assign a node or pin from the Unassigned Nodes & Pins box to a specific pin, logic cell, I/O cell, or embedded cell, you can drag the node handle with Button 1 from the Unassigned Nodes & Pins box to the appropriate pin, logic cell, I/O cell, or embedded cell. You can also drag an unassigned node to an LAB, EAB, Row, Column, and/or Device Assignment Bin. In addition, you can drag an unassigned pin to a Row, Column, or Device Assignment Bin. Once you assign a particular node or pin, its name no longer appears in the Unassigned Nodes & Pins box.

To select multiple adjacent nodes in the Unassigned Nodes & Pins box, you drag Button 1 through the node names (not the node handles); pressing Ctrl while clicking Button 1 on an item adds or removes it from the current selection. To move a selected item from the Unassigned Nodes & Pins box to the Device or LAB View, you simply drag it by its node handle; if multiple items are selected, you simply drag the handle of one of the selected items.

When you delete an existing assignment, the node or pin reappears in the Unassigned Nodes & Pins box. You can delete assignments by dragging them with Button 1 to or from a pin, logic cell, I/O cell, embedded cell, LAB, EAB, or any assignment bin back to the Unassigned Nodes & Pins box, or by selecting the assignments and choosing Delete or Cut (Edit menu).

See also:

Assigning a Pin, Location, or Chip

Copying, Cutting & Pasting Node and Pin Assignments


Selected Node(s) & Pin(s) Field (Floorplan Editor)
Selected Node(s) & Pin(s) Field

Shows the pin or node name(s) assigned to the pin, logic cell, I/O cell, embedded cell, row, column, LAB, EAB, or chip that is selected in the current Device View or LAB View. Show me

If you select multiple pins, logic cells, or embedded cells, or select a LAB, EAB, Row, Column, or Device Assignment Bin that contains multiple assignments, the Selected Node(s) & Pin(s) field displays the text <Multiple Items>. To view the individual assignments in the selection, open the drop-down list box. You can use the drop-down list box to select one of the assignments to edit or delete.

Information is displayed in the Selected Node(s) & Pin(s) field in the same format as information in balloon text.

See also:

Assigning a Pin, Location, or Chip


Device View Display (Floorplan Editor)
Device View Display

Graphically represents the exterior of the current device package, including each individual pin location and pin number. Show me

In the Device View display, assigned and unassigned pins are designated according to the scheme shown in the Color Legend.

You can enter and edit assignments to pins in the Device View display. When you assign a pin name to a specific pin, the pin changes color and the pin name appears adjacent to the pin. For PGA and BGA packages, which are displayed from their bottom view, the pin name and assignment, if any, are displayed next to the pin as balloon text when you place the mouse pointer directly over that pin.

To identify dedicated input pins on PGA and BGA packages, you can select a dedicated input pin in the LAB View display and then switch to the Device View display to see the highlighted pin.

You can zoom in or out to view the device at different scales. At display scales where text is not easily readable, assignments are displayed next to the pins as balloon text when you place the pointer directly over an individual pin.

Double-clicking Button 1 on a blank portion of the device in the Device View display changes the view to the LAB View display, and vice versa. You can also select it with the Device View command (Layout menu).

The Floorplan Editor cannot display a floorplan for a chip assigned to an AUTO device.

See also:

Assigning a Device

Assigning a Pin, Location, or Chip

Viewing a Device in the Device View or LAB View

Zooming In & Out


LAB View Display (Floorplan Editor)
LAB View Display

Graphically represents the interior and exterior of the current device, including each individual logic cell, I/O cell, embedded cell, LAB, and EAB. Show me

The LAB View display shows the LABs in the device labeled by row and column and EABs for devices with embedded arrays. For some device packages, it also displays individual device pins. Assigned and unassigned pins and logic cells are designated according to the scheme shown in the Color Legend.

To identify the correct physical locations of dedicated input pins on PGA and BGA packages, you can select a dedicated input pin in the LAB View display and then switch to the Device View display to see the highlighted pin.

You can enter and edit logic cell, embedded cell, and pin assignments in the LAB View display. When you assign a node or pin name to a specific pin, logic cell, I/O cell, or embedded cell, the assigned resource changes color. You can also assign logic functions to one or more pins, logic cells, or embedded cells using the Row, Column, LAB (logic cells only), EAB (embedded cells only), and/or Device. Assignment Bins.When you make assignments to a bin, the total number of assignments made to a particular assignment bin appears on the bin itself. Show me

When you place the mouse pointer directly over an assignment bin with a single assignment, the assignment is displayed next to the bin as balloon text. When multiple logic functions are assigned to a bin, the first two items are listed in balloon text, followed by the text etc. if there are additional items. You can select a bin and then use the drop-down list box in the Selected Node(s) & Pin(s) field to select a specific assignment within the bin to edit or delete.

You can zoom in or out to view the LAB(s) in the device at different scales.

Double-clicking Button 1 on a blank portion of the device in the LAB View display changes the view to the Device View display, and vice versa. You can also select it with the LAB View command (Layout menu).

The Floorplan Editor cannot display a floorplan for a chip assigned to an AUTO device.

See also:

Assigning a Pin, Location, or Chip

Viewing a Device in the Device View or LAB View

Zooming In & Out


Mouse Behavior (Floorplan Editor)
Mouse Behavior

Use a two- or three-button mouse for the Floorplan Editor.

Button 1 corresponds to the left mouse button. Button 2 corresponds to the right button on a two-button mouse or the middle and right buttons on a three-button mouse.

You can use Button 1 to:

Choose a command, Floorplan Editor window options, dialog box options and buttons, and items in drop-down list boxes.

Select and drag one or more nodes from the Unassigned Nodes & Pins box to a pin, logic cell, I/O cell, or embedded cell; or to an LAB, row, EAB,  column, or device assignment bin, and vice versa.

Select and drag one or more pins from the Unassigned Nodes & Pins box to a pin, or to a row, column, or device assignment bin, and vice versa.

Select multiple pins, nodes, logic cells, embedded cells, or assignment bins using object-by-object selection or area selection.

Switch to the LAB View display by double-clicking on a blank portion of the device in the Device View display, and vice versa.

Select and edit text in a dialog box.

You can use Button 2 to pop-up a context-sensitive menu containing commands that can operate on the current selection. If no other item is selected and you click Button 2 on a pin, logic cell, I/O cell, embedded cell, or assignment bin, it also selects the item before popping up the context-sensitive menu.

Refer to Floorplan Editor Procedures for step-by-step instructions that describe how to manipulate assignments and other items in the Floorplan Editor.

See also:

Assigning a Pin, Location, or Chip

Copying, Cutting & Pasting Node and Pin Assignments

Copying, Cutting & Pasting Text

Selecting a Node, Pin, or Other Object

Selecting Text


Parameters (all applications)
Parameters

Attributes of a megafunction or macrofunction that determine the logic created or used to implement the function, i.e., characteristics that determine the size, behavior, or silicon implementation of a function. For example, parameters are often used to define the width of a bus.

A parameterized function is a function whose behavior is controlled by one or more parameters. Some logic functions, such as the megafunctions in the Library of Parameterized Modules (LPM), are inherently parameterized and require parameter values to be assigned. Parameters can also optionally be assigned to some functions that are not inherently parameterized, such as old-style macrofunctions, to determine their style of implementation.

When you use an existing parameterized function, such as an LPM function, you can customize the parameters used and assign parameter values on an instance-by-instance basis. In a GDF, you can customize an instance (i.e., symbol) with the Graphic Editor’s Edit Ports/Parameters command (Symbol menu). In an AHDL TDF, you can declare parameters and assign values when you create an instance with an Instance Declaration or an in-line reference.

Parameter values are not necessarily specified on an instance-by-instance basis. Because parameter values can be inherited from higher hierarchical levels a hierarchical project, the Compiler searches for parameter values in the following parameter value search order:

1.	As part of the instance of the logic function. For example, in a TDF, in an instance that is created in an Instance Declaration or an in-line reference, you can declare which parameters are used and optionally assign their values. In a GDF, you can select a symbol and use the Edit Ports/Parameters command (Symbol menu) to assign parameter values for that instance.

2.	As part of the instance of the logic function at the next higher hierarchy level. The parameter values for an instance of a logic function apply to the subdesigns of that logic function if the subdesign instances do not have assigned parameter values.

3.	In the global project default parameter values specified with the Global Project Parameters command (Assign menu). These values are stored in the ACF for the project.

4.	In the optional default value listed in the Parameters Statement(s) of the TDF or the PARAM primitives of the GDF that defines the logic function. These default values apply only to the file in which they are listed, they are not applied the file’s subdesigns.

When you create a parameterized design file, you can specify the parameters used within that file and optional default parameter values (which are used only if no parameter values are specified elsewhere). In a GDF, you specify the parameters used within the current file with PARAM primitives; in a TDF, the parameters used within the current file are specified in a Parameters Statement. Once you create a parameterized design file, you can use the Create Default Include File and Create Default Symbol commands (File menu) to create default AHDL Function Prototypes (in Include Files) and symbols (in Symbol Files), respectively, that include the names (but not the values) of parameters used within the file. You can edit the parameters and parameter values for a Symbol File with the Symbol Editor’s Enter Parameters command (Element menu). These parameter names and values then appear as the defaults for each instance of the symbol when it is first entered in a GDF. Once you enter the symbol in a GDF, these default parameters and values can be customized with Edit Ports/Parameters on an instance-by-instance basis.

MAX+PLUS II allows you to assign global, project-wide default values for parameters with the Global Project Parameters command (Assign menu). As an alternative to using Global Project Parameters, you can specify default parameter settings in the Global Project Parameters Section of the ACF.

The following guidelines apply to parameters:

All logic options can be assigned as parameters for individual instances of mega- or macrofunctions. A logic option that is assigned to a logic function instance as a parameter overrides the global project default synthesis style--which is specified with Global Project Logic Synthesis  (Assign menu)--for that instance. However, if an instance has the same logic option assigned both as a parameter and as an individual logic option, the logic option setting overrides the parameter setting. In addition, logic options cannot be assigned as global, project-wide default parameter values with Global Project Parameters.

You cannot assign a value to the predefined Altera parameter DEVICE_FAMILY, which represents the device family assigned for the project. However, you can use the parameter value in comparisons. The legal values are FLEX10K, FLEX8000, MAX9000, MAX7000E, MAX7000, MAX5000, CLASSIC, and EP330/EP320.

The predefined Altera LATENCY parameter can be assigned to an instance of a mega- or macrofunction. However, the parameter applies only to that instance, and is not inherited by the subdesigns of that instance.

All logic options can be assigned as parameters for individual mega- or macrofunctions. However, logic options cannot be assigned global, project-wide default parameter values.

Parameters appear on the top right corner of a symbol in the Graphic or Symbol Editor if Show Parameters (Options menu) is turned on. (Show All also displays or hides all parameters in the current GDF.) Show me

Double-clicking Button 1 on a parameter opens the Edit Ports/Parameters or Enter Parameters dialog box in the Graphic and Symbol Editors, respectively. Show Parameters or Show All displays or hides all parameters in the current GDF. You can print a Graphic or Symbol Editor file that shows parameters by turning on Show Parameters (or Show All) before printing the file.

See also:

Customizing a Mega- or Macrofunction’s Ports & Parameters

Entering a Parameter

Showing Parameters and Probe & Resource Assignments

Specifying Global Project Parameters


Clique Assignments (all applications)
Clique Assignments

A group of logic functions defined as a single, named unit. A clique is a resource assignment that groups a block of logic functions together. The Compiler attempts to keep clique members together when it fits the project. A clique assignment allows you to group all logic on a speed-critical path, thus ensuring optimum speed.

You cannot assign pins to a clique.

If possible, all clique members are assigned to the same LAB. If the clique members will not fit into a single LAB, they are placed in the same row (FLEX 10K, FLEX 8000, and MAX 9000 devices only) or the same device.

Cliques therefore allow you to partition a project so that only a minimum number of signals travel between LABs, rows, and devices, and to ensure that no unnecessary LAB-to-LAB, row-to-row, or device-to-device delays exist on critical timing paths.

The MAX+PLUS II Compiler automatically assigns a clique to a device. However, since all members of a clique are fitted into the same device, assigning one clique member to a particular LAB, row, or chip effectively assigns the whole clique to a specific location.

You can assign a logic function to a clique name with up to 32 name characters with Clique. As an alternative to using the Clique command, you can enter clique assignments with the Clique Assignments Section of the ACF for the hierarchy tree.

Be sure to refer to Guidelines for Working with Assignments for absolutely essential information on using all types of resource, probe, and device assignments.

In the Graphic Editor only, the clique assignment appears on the top left corner of the symbol assigned to it (below any timing assignments). Show me

Double-clicking Button 1 on a clique assignment in the Graphic Editor opens the Clique dialog box. Show Cliques or Show All displays or hides all clique assignments in the current GDF. You can print a Graphic Editor file that shows clique assignments by turning on either of these commands before printing the file.

See also:

Assigning a Clique

Assigning a Pin, Location, or Chip

Assigning Resources in a Third-Party Design Editor

Clique Assignments Section (Report File)

Partitioning a Project

Printing a File (Graphic Editor)

Resource Assignments in EDIF Input Files


Assignments on Symbols (Graphic Editor)
Assignments on Symbols


Connected Pin Assignments (all applications)
Connected Pin Assignments

Assign multiple pins in the current hierarchy tree to a connected pin group that specifies which pins are connected together on your circuit board.

Connected pin assignments are useful for preparing single- and multi-device projects for timing simulation and linked simulation. Connected pin assignments can also have a limited effect on manual partitioning.

You can enter a connected pin assignment with the Connected Pins command in any MAX+PLUS II application. As an alternative to using the Connected Pins command, you can specify connected pin assignments in the Connected Pin Assignments Section of the ACF for the hierarchy tree or with the external connection pin primitives--INPUTC, OUTPUTC, and BIDIRC--that are available in Graphic Editor files.

If you compile a project to create a timing SNF, connected pin assignments are required for all inter-device connections. They are not required to indicate inter-device connections if a top-level super-project design file is compiled to create a linked SNF, except in the following cases (which also apply to timing SNFs):

You can tie bidirectional pins together into a bidirectional bus. The Simulator can simulate the behavior of the bidirectional bus and detect logic contention errors.

Global Clock and Output Enable signals can be generated within a project. These signals can be routed through an output pin and back into an appropriate dedicated global input pin.

When you need to implement a global signal and a logic signal on one pin in a device that does not support this capability, two separate pins can be used (one for each signal) and tied together.

You cannot connect pins externally for hardware-assisted functional simulation or functional testing when multiple bidirectional or output pins are tied together.

You can also use connected pin assignments to guide partitioning. If you wish to manually partition a project so that each individual macrofunction is implemented in a different device from the same device family, you can assign each macrofunction to a different chip. You can then use the connected pin assignments to tie the macrofunctions’ inputs and outputs together and specify which pins are connected together on your board.

You must also make the appropriate chip assignments on the pin primitives. The connected pin assignments change the outcome of partitioning only if the macrofunctions have combinatorial outputs that might otherwise be placed in a different device by logic synthesis. In these cases, the connected pin assignments prevent the Compiler from moving logic to a different chip. If the macrofunctions have combinatorial outputs, as an alternative to using connected pin assignments, you can place LCELL buffers on the combinatorial macrofunction outputs and assign them to the chip that contains the "source" macrofunction.

1.	If you have already created separate projects that use devices from one or more device families, you can create a top-level super-project that contains instances of each of the individual sub-projects, and use ordinary node connections rather than connected pin assignments to indicate board-level interconnections. Connected pin assignments are needed only in the cases described above if a super-project is compiled to create a linked SNF.

2.	Connecting the external connection pinstub of INPUTC, OUTPUTC, and BIDIRC primitives in a Graphic Editor file automatically creates a connected pin group that appears in the Connected Pins dialog box and in the Connected Pin Assignments Section of the ACF for the hierarchy tree.

See also:

Assigning Connected Pins

Assigning a Pin, Location, or Chip

Multiple Pin Connections Section (Report File)


Device Assignments (all applications)
Device Assignments

Assign all logic in a project to a single device, or map all of the chip assignments in a multi-device project to specific devices. You can also set the Security Bit, Turbo Bit, and other device options for specific devices on a device-by-device basis.

You can enter a device assignment with the Device command in any MAX+PLUS II application. You can assign a device family, then select a specific device or AUTO. If AUTO is selected, you can allow the Compiler to choose any device that best suits the project, or you can direct the Compiler to choose from a restricted set of devices with the Auto Device Selection dialog box. You can also assign a device in the Physical Chip Assignments Section section of the ACF for the hierarchy tree, and specify AUTO devices with the ACF’s Auto Device Choices Section.

Be sure to refer to Guidelines for Working with Assignments for absolutely essential information on using all types of resource, probe, and device assignments.

When you enter a device assignment, you can also specify the settings for several device options:

The Options button in the Device dialog box opens the Individual Device Options dialog box, which allows you to specify the setting for the Turbo Bit logic option and the Security Bit on a device-by-device basis.

The FLEX 8000 Options button in the Individual Device Options dialog box opens the FLEX 8000 Individual Device Options dialog box, which allows you to specify special device options and to reserve dual-purpose pins for FLEX 8000 devices on a device-by-device basis.

You can also specify default project-wide settings for the Turbo Bit (as part of a global default logic synthesis style), Security Bit, and FLEX 8000/FLEX 8000M device options with the Global Project Device Options and FLEX 8000 Device Options dialog boxes. In addition, you can set the Security Bit on a device-by-device basis in the Programmer.

See also:

Assigning a Device

Assigning Resources in a Third-Party Design Editor

Device Summary Section (Report File)

Partitioning a Project

Setting the Security Bit (Programmer)

Specifying Devices for Automatic Device Selection

Specifying Global Project FLEX 8000 Device & Pin Options

Specifying Global Project Logic Synthesis Settings

Specifying Global Project Security Bit & Reserved Resource Settings

Specifying Individual Device Security & Turbo Bit Options

Specifying Individual FLEX 8000 Device & Pin Options


Logic Option Assignments (all applications)
Logic Option Assignments

Resource assignments that guide logic synthesis on individual logic functions.

MAX+PLUS II provides a variety of logic options to control logic synthesis during compilation. You can specify the logic option settings for individual logic functions within each design file by applying a logic synthesis style and/or by applying individual logic option assignments. In addition, you can apply the Turbo Bit logic option on a device-by-device basis for individual devices in a multi-device project.

MAX+PLUS II provides three predefined logic synthesis styles that specify the settings for all available logic options: Normal, Fast, and WYSIWYG. You can use these styles on individual logic functions, and/or specify one of these styles as the project-wide default style with the Global Project Logic Synthesis  command. Each style contains different combinations of logic option settings that are tailored for different device families. You can also create your own style that defines the behavior of some or all of the available logic options with the Define Synthesis Style dialog box.

1.	Altera recommends assigning logic synthesis styles rather than individual logic option assignments whenever possible. When both types of assignments are used, the Compiler combines the assignments according to Logic Synthesis Style & Logic Option Rules.

2.	Be sure to refer to Guidelines for Working with Assignments for absolutely essential information on using all types of types of resource, probe, and device assignments.

The following individual logic options are provided in MAX+PLUS II. Some options are available only in a particular device family or in multi-level logic synthesis:

Carry Chain	Parallel Expanders

Cascade Chain	Reduce Logic

Decompose Gates	Refactorization

Duplicate Logic Extraction	Register Optimization

Resynthesize Network	Slow Slew Rate

I/O Cell Register	SOFT Buffer Insertion

Minimization	Subfactor Extraction

Multi-Level Factoring	Turbo Bit

NOT Gate Push-Back	XOR Synthesis

Optimize

The following commands are used to enter logic option and logic synthesis style assignments:

Command:	Action:

Logic Options	Sets a logic synthesis style for one or more selected individual logic functions. Also, the Individual Synthesis Options button opens the Individual Logic Options dialog box, which allows you to assign individual logic options for the selected logic functions.

Device	The Options button opens the Individual Device Options dialog box, which allows you to specify the default logic cell Turbo Bit setting for all logic cells in a particular device. This command allows you to set the Turbo Bit on a device-by-device basis in a multi-device project.

Global Project Logic Synthesis	Specifies the default logic synthesis style for all logic functions in the project.

As an alternative to using these commands, you can specify the global project logic synthesis style in the Global Project Synthesis/Assignment Options Section and/or individual logic option assignments in the Logic Options Section of the ACF for the hierarchy tree, respectively. You can also define logic synthesis styles in the ACF’s Logic Synthesis Style Definition.

In the Graphic Editor only, the logic option (and style) assignment(s) for a symbol appear on its bottom right corner. Show me

Double-clicking Button 1 on a logic option assignment in the Graphic Editor opens the Logic Options dialog box. Show Logic Options or Show All displays or hides all logic option assignments in the current GDF. You can print a Graphic Editor file that shows the logic options by turning on either of these commands before printing the file.

See also:

Assigning an Individual Logic Option or Synthesis Style

Assigning Resources in a Third-Party Design Editor

Defining a Logic Synthesis Style

Partitioning a Project

Printing a File (Graphic Editor)

Resource Assignments in EDIF Input Files

Specifying Global Project Logic Synthesis Settings


Logic Synthesis Style & Logic Option Rules

A logic synthesis style consists of a combination of logic option settings that turn multiple logic options on and off at the same time. The following rules apply to using logic synthesis styles and individual logic options:

A style can be used in combination with individual logic option settings. The setting for a particular logic option within a style is always overridden by an individual setting for that logic option at the same hierarchical level in the project. Example

You can explicitly apply only one style to a logic function; there is no limit to the number of individual logic option settings. Example

Applying a style to a logic function overrides the style or individual logic option applied at a higher level in the hierarchy. The settings within the style applied to the logic function override the settings applied to the macrofunction that contains the logic function. Example

The Compiler uses a default logic synthesis style for the entire project. The settings for each logic option in this default style apply only if you do not specify settings elsewhere, i.e., they apply to logic functions that do not have other explicit logic option or logic synthesis style settings. Therefore, explicit assignments of individual logic options override the project-wide default style only for those individual logic options; the settings for other logic options within the project-wide default style still apply. Similarly, the settings for logic options in an explicitly assigned (non-default) style override the settings for those logic options within the project-wide default style; the settings for other logic options within the project-wide default style still apply. Example

The Altera-provided Normal, Fast, and WYSIWYG logic synthesis styles specify a setting for every available individual logic option. Altera does not recommend editing the logic option settings in these styles. If you do edit these styles, you should save the new settings to a different style name.

The Carry Chain and Cascade Chain logic options are set to Ignore in the Altera-supplied Normal style, to Manual in the WYSIWYG style, and to Auto in the Fast style. Since many FLEX 8000 family-specific macrofunction contain CASCADE and CARRY buffers, you may wish to use a style other than Normal as the default logic synthesis style for a project that contains these macrofunctions.

Within a style, the setting for any logic option can be specified explicitly, e.g., as on or off. A setting can also be specified as "default," which is represented as a grayed three-way checkbox in the Define Synthesis Style dialog box. If the setting for a logic option is specified as "default," the Compiler searches for an individual logic option assignment or for a logic option setting in a style applied at a higher level of the project hierarchy. If no other setting is found, the Compiler uses the setting in the project-wide default style.

When you create a style that is applied to individual logic functions, you should use the default setting for all options that are not immediately relevant. In contrast, you should specify a non-default setting for each option when you create a style that is applied to the project as a whole. If you use a default setting in a project-wide style, the Logic Synthesizer will substitute the corresponding setting from the Altera-provided Normal style during compilation.

The Logic Synthesizer provides two basic types of logic synthesis: multi-level logic synthesis and standard synthesis. Multi-level synthesis allows you to assign a pin, logic cell, chip, clique, logic option, or logic synthesis style to any logic function. With standard synthesis, you can make these assignments only on hard logic functions; assignments on a macrofunction affect only the hard logic functions within the macrofunction.

If the Compiler issues "Logic too complex" messages for your project during compilation, turning on the SOFT Buffer Insertion logic option in the default logic synthesis style for the project can help the Compiler to simplify the logic in your project.

Be sure to refer to Guidelines for Working with Assignments for additional essential information on using all types of types of resource, probe, and device assignments.

See also:

Assigning an Individual Logic Option or Synthesis Style

Assigning Resources in a Third-Party Design Editor

Defining a Logic Synthesis Style

Guidelines for Working with Assignments

Resource Assignments in EDIF Input Files

Specifying Global Project Logic Synthesis Settings


Example: Combination of Multiple Logic Options & a Single Synthesis Style

The settings for the Parallel Expanders, Minimization, and Turbo Bit logic options on a logic function in a MAX 7000-based project override the settings for these options in the Normal logic synthesis style:

<node name> : STYLE=NORMAL;

<node name> : PARALLEL_EXPANDERS=ON;

<node name> : MINIMIZATION=PARTIAL;

<node name> : TURBO_BIT=ON


Example: Priority of Logic Option & Logic Synthesis Style Settings

Project-wide default logic synthesis style:	STYLE=FAST;

Assignment on a 74192 macrofunction in the project:	STYLE=NORMAL;

PARALLEL_EXPANDERS=ON;

Assignment on a TFF in the 74192 macrofunction:	PARALLEL_EXPANDERS=OFF;

MINIMIZATION=PARTIAL;

TURBO_BIT=ON;

The default project-wide Fast logic synthesis style is overridden by the Normal style and Parallel Expanders setting that are applied to the 74192 macrofunction within the project. The settings for the Parallel Expanders, Minimization, and Turbo Bit logic options on the TFF override the settings for these options in the Normal logic synthesis style and Parallel Expanders setting that are applied to the 74192 that contains the TFF.


Pin, Location & Chip Assignments (all applications)
Pin, Location & Chip Assignments

Assign a single logic function to a specific pin or location within a chip, or assign one or more logic functions to a specific chip. A pin assignment can also be used to reserve a pin for future use.

If you wish to set and/or maintain the performance of a project that is partitioned into multiple devices, you can assign logic functions to a chip. Assigning related logic functions to a chip--or to an LAB, row, or column within a chip--can minimize timing delays. In addition, you can assign a logic function to a specific pin, logic cell,or I/O cell within a chip. Chip and location assignments allow you to control project fitting so that only a minimum number of signals travel between LABs, rows, columns, and devices, and to ensure that no unnecessary delays exist on critical timing paths.

To reserve a pin for future use, you can also enter a pin symbol or declare a pin name, assign it to a specific pin, and disconnect the pin from other logic.

For specific pin and location assignments to take effect, you must assign specific devices for the project with Device or in the Physical Chip Assignments Section of the ACF. The Compiler ignores pin, logic cell, and I/O cell assignments for chips that are assigned to AUTO devices.

You can enter a pin, location, or chip assignment with Pin/Location/Chip or with the Floorplan Editor. As an alternative to using Pin/Location/Chip or the Floorplan Editor, you can also enter assignments in the Physical Chip Assignments Section section of the ACF.

Be sure to refer to Guidelines for Working with Assignments for absolutely essential information on using all types of resource, probe, and device assignments.

A chip name may contain up to 32 name characters. These names are used as the filenames of the programming files generated during project compilation. Pin and logic cell numbers are available in Devices & Adapters or individual device data sheets.

In the Graphic Editor only, on INPUT, INPUTC, OUTPUT, OUTPUTC, BIDIR, and BIDIRC pin primitives, the pin, location, and chip assignment appears opposite the input or output of the symbol; on other symbols, they appear on the bottom left corner of the symbol. Assignments are shown in the format <chip name> @ <pin or location identifier>. Show me

In the Graphic Editor, double-clicking Button 1 on a pin, location, or chip assignment, or on a primitive symbol, opens the Pin/Location/Chip dialog box. Show Pins/Locations/Chips or Show All displays or hides all pin, location, and chip assignments in the current GDF or OrCAD Schematic File. You can print a Graphic Editor file that shows the assignments by turning on either of these commands before printing the file.

See also:

Assigning a Pin, Location, or Chip

Assigning Resources in a Third-Party Design Editor

Fitter Settings Command (Compiler)

Fitting & Refitting a Project (Compiler)

Partitioning a Project

Pin/Location/Chip Assignments Section (Report File)

Printing a File (Graphic Editor)

Resource Assignments in EDIF Input Files


Probe Assignments (all applications)
Probe Assignments

Give unique names to inputs or outputs of a logic function.

The probe name replaces the often lengthy hierarchical node name that would otherwise appear after compilation in the SNF and Report File for the project. A probe name also makes it easier to search for a node in a different part of the hierarchy with Find Node in Design File.

You can create a probe name with up to 32 name characters with Probe. Because a probe name must be unique, you cannot copy a probe. After you enter a probe, you must compile the project to make the probe name appear in the SNF or Report File. As an alternative to using Probe, you can enter probe assignments in the Probe Assignments Section of the ACF.

Be sure to refer to Guidelines for Working with Assignments for absolutely essential information on using all types of types of resource, probe, and device assignments.

In the Graphic Editor, the probe assignment appears next to a pinstub of the symbol to which it is assigned. Show me

Double-clicking Button 1 on a probe assignment in the Graphic Editor opens the Probe dialog box. Show Probes or Show All displays or hides all probe assignments in the current GDF. You can print a Graphic Editor file that shows all probes by turning on either of these commands before printing the file.

See also:

Assigning a Probe

Finding Nodes & Symbols in Design Files

Finding Nodes & Pins in the Floorplan Editor

Hierarchical Node & Symbol Names

Printing a File (Graphic Editor)

Probe Assignments Section (Report File)


Timing Assignments (all applications)
Timing Assignments

Resource assignments that guide compilation to achieve speed performance on individual logic functions.

MAX+PLUS II offers tpd, tco, tsu, fmax, and timing cut timing assignments to control logic synthesis and fitting on individual logic functions during compilation. You can enter timing assignments for individual logic functions within each design file and/or specify project-wide default timing specifications.

1.	Refer to Guidelines for Timing Assignments and Guidelines for Achieving Maximum Speed Performance for information on how to use timing assignments effectively.

2.	Be sure to refer to Guidelines for Working with Assignments for absolutely essential information on using all types of resource, probe, and device assignments.

The following commands are used to enter timing assignments:

Command:	Action:

Timing Requirements	Specifies tpd, tco, tsu, fmax, and/or timing cut assignments for one or more selected individual logic functions.

Global Project Timing Requirements 	Specifies optional project default tpd, tco, tsu, and/or fmax timing for all logic functions in the project, as well as project-wide bidirectional pin feedback and Preset and Clear timing cuts.

As an alternative to using these commands, you can enter timing assignments in the Timing Requirement Assignments Section of the ACF.

In the Graphic Editor only, timing assignments for a symbol appear on its top left corner (above any clique assignments). Show me

Double-clicking Button 1 on a timing assignment in the Graphic Editor opens the Timing dialog box. Show Timing Assignments or Show All displays or hides all timing assignments in the current GDF. You can print a Graphic Editor file that shows timing assignments by turning on either of these commands before printing the file.

See also:

Assigning Individual Timing Requirements

Printing a File (Graphic Editor)

Specifying Global Project Timing Requirements


Report File Equation Viewer (Floorplan Editor)
Report File Equation Viewer

Displays Report File (.rpt) routing and equation information for pin, logic cell, and embedded cell assignments.

When you turn on the Report File Equation Viewer command (Layout menu), the Report File Equation Viewer is displayed at the bottom of the Floorplan Editor window.

Click Button 1 on any item in this picture for information on that item:

You can choose one or more items in the floorplan to display its equations, fan-in, and fan-out in the Equation Viewer.

See also:

Viewing Equations in the Floorplan Editor

Showing Node Fan-In or Fan-Out

Showing Paths

Showing Routing Statistics


Equations; Report File Equation Viewer
Equations (n)

Lists all of the equations for the selected node(s) and/or pin(s), with n indicating the total number of equations listed.


Fan-In; Report File Equation Viewer
Fan-In (n)

Lists all nodes that feed the selected logic cells, embedded cells, and/or pin(s), with n indicating the total number of nodes listed. Nodes are labeled as follows:

Node Type:	Label:

Input pin	IN

Output pin	OUT

Bidirectional pin	bidir

Registered node	REG

Combinatorial node	COMB

Memory node	MEM

Double-clicking Button 1 on a node in this list is a shortcut for selecting the node and choosing the < Go To button to display its equations, fan-in, and fan-out.


Fan-Out; Report File Equation Viewer
Fan-Out (n)

Lists all nodes that are fed by the selected logic cells, embedded cells, and/or pin(s), with n indicating the total number of nodes listed. Nodes are labeled as follows:

Node Type:	Label:

Input pin	IN

Output pin	OUT

Bidirectional pin	bidir

Registered node	REG

Combinatorial node	COMB

Memory node	MEM

Double-clicking Button 1 on a node in this list is a shortcut for selecting the node and choosing the Go To > button to display its equations, fan-in, and fan-out.


< Go To; Report File Equation Viewer
< Go To

Switches the display of Equation Viewer information from the current selection to the selected node(s) in the Fan-In box. When you select one or more nodes in the Fan-In box and then choose the < Go To button, the Equations box displays equation and routing information for that selection. If you choose < Go To without selecting any nodes, the Equation Viewer displays equation and routing information for all nodes listed in the Fan-In box.

Double-clicking Button 1 on a node in the Fan-In box is a shortcut for selecting the node and choosing the < Go To button to display its equations, fan-in, and fan-out.


Go To >; Report File Equation Viewer
Go To >

Switches the display of Equation Viewer information from the current selection to the selected node(s) in the Fan-Out box. When you select one or more nodes in the Fan-Out box and then choose the Go To > button, the Equations box displays equation and routing information for that selection. If you choose Go To > without selecting any nodes, the Equation Viewer displays equation and routing information for all nodes listed in the Fan-Out box.

Double-clicking Button 1 on a node in the Fan-Out box is a shortcut for selecting the node and choosing the Go To > button to display its equations, fan-in, and fan-out.


Floorplan Editor--Context-Sensitive Help
Floorplan Editor Context-Sensitive Help

Context-sensitive help is available for all Floorplan Editor commands, dialog boxes and messages, and the following basic tools:

Assignment Bins

Row Assignment Bin

Column Assignment Bin

LAB Assignment Bin

Device Assignment Bin

Color Legend

Fields

Chip Name Field

Unassigned Nodes & Pins Box

Selected Node(s) & Pin(s) Field

Floorplan Displays

Device View

LAB View

Options & Buttons

Zoom In & Zoom Out Buttons

Status Bar & Toolbar

Status Bar

Toolbar

For information on other basic tools, see Floorplan Editor Basic Tools.

See also:

Getting Context-Sensitive Help


Floorplan Editor Window


Floorplan Editor Window Device View
Floorplan Editor Window


Floorplan Editor Window


Floorplan Editor Window


Floorplan Editor Help Contents

Introduction

Basic Tools

Commands

Procedures

Golden Rules

Shortcuts

Messages

Glossary


Floorplan Editor Introduction
Introduction

You can use the MAX+PLUS II Floorplan Editor to assign physical device resources or to view Compiler partitioning and fitting results. Show me

You can easily assign logic to a device, to any row or column within a device, or to a specific LAB, pin, logic cell, or I/O cell.

In addition, after you compile your project, you can use the Floorplan Editor to view the Compiler’s logic placement. You can then compare your own assignments to the Compiler’s assignments, if they differ, and back-annotate the results of compilation.

How Does the Floorplan Editor Work?

The Floorplan Editor provides a convenient method to enter and edit physical device resource assignments for your project. Two displays are available:

The Device View shows all pins on a device package and their function.

The LAB View shows the interior of the device, including all LABs and the individual logic cells within each LAB. In FLEX 8000, FLEX 8000M, and MAX 9000 devices, I/O cell locations are also displayed. In addition, pin locations are displayed for some device packages.

A color legend clearly indicates unassigned and assigned pins, logic cells, and I/O cells; unrouted items; and nonassignable items such as VCC, GND, and reserved pins.

The Floorplan Editor provides a list of unassigned node and pin names in your project. Each name has a handle that you can drag to an individual pin, logic cell, or I/O cell in the Device View or LAB View display. Conversely, you can drag a node or pin with an existing assignment back to the list of unassigned nodes or to a different location on the device.

You can also make a more general assignment to the assignment "bin" for an entire LAB or a device, and then allow the Compiler to select the most appropriate location within the LAB or device. In FLEX 8000 and FLEX 8000M devices, you can also assign nodes and pins to row and column bins. Each generic assignment bin displays a number showing the number of nodes or pins assigned to it.

The Floorplan Editor also allows you to view and edit your current assignments, which are stored in the project’s ACF. You can also display a non-editable (read-only) view of the results of the last compilation, which are stored in the Fit File, regardless of whether fitting was successful. Any items with illegal assignments are displayed in red in the list of unassigned node and pin names. If you wish, you can back-annotate the results of the compilation and edit the assignments.

The MAX+PLUS II Floorplan Editor provides many other useful features. For example, you can zoom in and out to various display scales, so that you can see an entire device at a glance or a detailed portion of it. You can copy, cut, paste, and delete one or more selected assignments, and search for an assignment by its pin or logic cell number or its node name.

Where to Start

Altera offers a wide range of information to help you create and manage assignments with MAX+PLUS II and the Floorplan Editor.

On-Line Help

On-line help supplies complete reference and how-to information on using the Floorplan Editor.

Floorplan Editor Help Contents provides access to all on-line Floorplan Editor Help.

Floorplan Editor Golden Rules summarizes essential rules and guidelines for using the Floorplan Editor.

See also:

How to Use MAX+PLUS II Help


Floorplan Editor Golden Rules
Golden Rules

The following guidelines will help you use the Floorplan Editor effectively:

To avoid making illegal assignments, use Copy only in cases when you need to assign the same pin or node name to multiple places, e.g., in projects targeted for multiple devices.

If you use the Floorplan Editor to view of the results of the last compilation, you can back-annotate the results of the compilation with Back-Annotate Project and edit the assignments.

General Design Entry Golden Rules

Be sure to refer to Guidelines for Working with Assignments for absolutely essential information on using all types of resource, probe, and device assignments.

When you start work on a new design file, specify the target device family with Device right away so that you can take advantage of family-specific macrofunctions. If you don’t specify a device family, the family for the current project is assumed.

Use the Design Doctor to check the reliability of your project logic during compilation. Follow Project Reliability Guidelines to create reliable projects.

The Altera-provided default logic synthesis styles have different settings for different device families to ensure that each architecture is used most efficiently. When you use an Altera-provided style, the settings for that style will change when you change the device family. After changing the device family, check the new style settings to ensure that they conform to your needs.

General MAX+PLUS II Golden Rules

When you start work on a new design file, name it as the current project with Project Name right away so that you can compile it easily. You can always change the name later.

Use the built-in hierarchy traversal features in MAX+PLUS II to move between design files for the current hierarchy. To open a lower-level file in a hierarchy, open the top-level file and then use the Hierarchy Display window or Hierarchy Down to open the lower-level files. If you choose Open or Retrieve to open a lower-level file, it is considered to be the top of a different hierarchy tree, and resource, device, and probe assignments that you enter are saved only for that hierarchy, not for the project.

When you create an ancillary file for a project, the icon for the file will appear in the Hierarchy Display if you use the same filename as the project.

Don’t edit any MAX+PLUS II system files, including HIFs, maxplus2.idx files, or the maxplus2.ini file.

Use the Save As command if you wish to rename a design file or an ancillary file. Don’t rename design files from outside of MAX+PLUS II system (e.g., from DOS or with the Windows File Manager).

When you have completed a project, use Project Archive to ensure that you save a complete backup copy of all project files that will not be affected by future edits or deletions.


Floorplan Editor Shortcuts
Shortcuts

The following list provides shortcuts for Floorplan Editor commands:

Command:	Shortcut:

Context-Sensitive Help	Shift+F1 or

Cascade	Shift+F4

Close	Ctrl+F4 or double-click Button 1 on the Document Control Menu box

Compiler

Copy	Ctrl+C or Ctrl+Ins or [image] or Alt+Press Button 1, Drag, Release on a node or group handle

Cut	Ctrl+X or Shift+Del or

Delete	Del

Exit MAX+PLUS II	Alt+F4 or double-click Button 1 on the Application Control Menu box

Find Next	Ctrl+N

Find Node in Design File	Ctrl+B or

Find Node in Floorplan

Find Previous	Ctrl+Shift+N

Find Text	Ctrl+F or

Fit in Window	Ctrl+F or

Floorplan Editor

Hierarchy Display

Hierarchy Project Top	Ctrl+T or

Maximum Size	Ctrl+2

Next	Ctrl+F6

Normal Size	Ctrl+1

Open	Ctrl+O or

Paste	Ctrl+V or Shift+Ins or

Programmer

Project Name	Ctrl+J or

Project Save & Compile	Ctrl+L or

Project Save & Simulate	Ctrl+Shift+L or

Show Node Fan-In

Show Node Fan-Out

Simulator

Switch To	Ctrl+Esc

Tile	Shift+F4

Timing Analyzer

Undo	Ctrl-Z or

Zoom In	Ctrl+Space or Zoom In button

Zoom Out	Ctrl+Shift+Space or Zoom Out button


--------------------BEGINNING OF NON-TRANSLATED TEXT-----------------------------------------------

Floorplan Editor commands that will be available post-5.0:

Fit in Windowfe_com_fitwin	Ctrl+W or

Saveke_com_save	Ctrl+S or

Search & Replaceke_com_replace	Ctrl+R or

Go Tofe_com_goto

Printfe_com_print

Printer Setupke_com_prset

Selectfe_com_select

--------------------END OF NON-TRANSLATED TEXT-----------------------------------------------


Floorplan Editor Procedures
Procedures

Assignments & Compiler Configuration Settings

Assigning a Clique

Assigning a Device

Assigning a Pin, Location, or Chip

Assigning a Probe

Assigning an Individual Logic Option or Synthesis Style

Assigning Connected Pins

Assigning Individual Timing Requirements

Back-Annotating Assignments for a Project

Clearing Assignments for a Project

Converting an Obsolete Assignment Format

Copying a Resource Assignment

Copying, Cutting & Pasting Node & Pin Assignments

Defining a Logic Synthesis Style

Deleting an Assignment

Demoting an Assignment

Guidelines for Achieving Maximum Speed Performance

Guidelines for First-Time Project Fitting

Guidelines for Timing Assignments

Guidelines for Working with Assignments

Ignoring Project Assignments during Compilation

Logic Synthesis Style & Logic Option Rules

Renaming a Chip

Searching the Node Database

Specifying Devices for Automatic Device Selection

Specifying Global Project Classic & MAX Device Options

Specifying Global Project FLEX 10K Device & Pin Options

Specifying Global Project FLEX 8000 Device & Pin Options

Specifying Global Project Logic Synthesis Settings

Specifying Global Project Parameters

Specifying Global Project Timing Requirements

Specifying Individual Classic & MAX Device Options

Specifying Individual FLEX 10K Device & Pin Options

Specifying Individual FLEX 8000 Device & Pin Options

File Management

Creating a New File

Getting Information on a File

Opening a File

Saving a File

Floorplan Display

Showing the Floorplan for Current Assignments

Showing the Floorplan for the Last Compilation

Viewing a Device in the Device View or LAB View

Hierarchy

Navigating the Hierarchy

Updating the Hierarchy

MAX+PLUS II Management

Changing Colors in MAX+PLUS II

Closing a MAX+PLUS II Application

Creating & Using a Local Copy of the maxplus2.ini File

Entering an Authorization Code

Exiting from MAX+PLUS II

Specifying a User Library

Starting MAX+PLUS II Applications

Switching Between MAX+PLUS II Applications

Messages

Getting Help on a Message

Locating the Source of a Message

Nodes, Pins, Logic Cells, & Assignment Bins

Selecting a Node, Pin, or Other Object

Project Management

Archiving a Project

Changing the Project Name

Combining Multiple Projects for Simulation

Compiling a Project

Ensuring Project Reliability

Project Reliability Guidelines

Partitioning a Project

Automatic Partitioning

Guiding the Partitioner

Viewing the Results of Partitioning

Renaming a Macrofunction in the Current Project

Routing Information

Showing Node Fan-In or Fan-Out

Showing Paths

Showing Routing Statistics

Viewing Equations in the Floorplan Editor

Status Bar & Toolbar

Showing the Status Bar

Showing the Toolbar

Symbols

Finding Nodes & Pins in the Floorplan Editor

Finding Nodes & Symbols in Design Files

Text

Copying, Cutting & Pasting Text

Deleting Text

Finding Text

Selecting Text

Timing Analysis

Running a Timing Analysis

Undoing Edits

Viewing a Floorplan Display

Fitting the Floorplan into the Window

Showing Moved Nodes in Gray

Turning Full Screen Viewing On or Off

Zooming In & Out


Assigning a Clique (all applications)
Assigning a Clique

You can enter and modify clique assignments with the Clique command in any MAX+PLUS II application. These assignments are saved in the ACF for the current hierarchy tree. As an alternative to using Clique, you can enter all clique assignments in text format in the Clique Assignments Section of an ACF.

Be sure to refer to Guidelines for Working with Assignments for absolutely essential information on using all types of resource, probe, and device assignments. For information on specific assignments to enter and other techniques to improve speed performance in your MAX+PLUS II projects, go to Guidelines for Achieving Maximum Speed Performance.

To enter or edit a clique assignment:

1.	(Optional) Select one or more nodes and/or symbols.

You cannot assign pins to a clique.

2.	Choose Clique (Assign menu). The Clique dialog box is displayed. If you selected a node or symbol before opening the Clique dialog box, its hierarchical name is displayed in the Node Name box. If you selected multiple items before opening Clique, the text **-Multiple Items-** is displayed in the Node Name box.

3.	If you did not select a node or symbol before opening the Clique dialog box, type a name in the Node Name box or choose Search to select a name with the Search Node Database dialog box. If you wish to edit an existing clique assignment, you can select it in the Existing Clique Assignments box.

4.	Specify a clique name by typing a name with up to 32 name characters in the Clique Name box or by selecting an existing name from the drop-down list box. If you selected a node or symbol before opening the Clique dialog box, its existing clique assignment is shown as the default in the Clique Name box. If you selected multiple items before opening Clique, an existing clique assignment, if any, is displayed only if all of the selected items belong to the same clique.

5.	Choose OK to save the most recent clique assignment change for the current hierarchy tree and close the dialog box.

or:

Choose Add to implement the new assignment, then repeat steps 3 through 5 if you wish to enter additional clique assignments or change existing assignments. The Add button changes into a Change button if you are editing an existing clique assignment. After you choose Add or Change, the new or updated assignment is displayed in the Existing Clique Assignments box.

If Show Cliques or Show All  (Options menu) is turned on in the Graphic Editor, the name of the clique appears next to the top left corner of any symbol assigned to the clique. (Clique assignments are displayed below all timing assignments.) Show me

To edit an existing clique assignment in a Graphic Editor file:

Double-click Button 1 on a clique assignment to open the Clique dialog box, follow steps 4 and 5 in the procedure above, and choose OK.

See also:

Assigning Resources in a Third-Party Design Editor

Back-Annotating Assignments for a Project

Clearing Assignments for a Project

Copying a Resource Assignment

Deleting an Assignment

Fitting & Refitting a Project

Partitioning a Project

Selecting a Node, Pin, or Other Object (Floorplan Editor)

Showing Parameters and Probe & Resource Assignments (Graphic Editor)


Assigning a Device (all applications)
Assigning a Device

You can assign a single device for the current project or assign chips in a multi-device project to specific devices with the Device command in any MAX+PLUS II application. These assignments are saved in the ACF for the current hierarchy tree. As an alternative, you can enter all device assignments in text format in the Physical Chip Assignments Section of an ACF. Device assignments and chip assignments control how logic is partitioned among multiple devices.

Be sure to refer to Guidelines for Working with Assignments for absolutely essential information on using all types of resource, probe, and device assignments.

To assign a single device for the current project:

1.	Choose Device (Assign menu). The Device dialog box is displayed.

2.	Select a device family from the Device Family drop-down list box. All devices in the selected family are shown in the Devices box.

3.	If you wish to list all packages, operating temperatures, and speed grades, turn on Show All Packages & Speed Grades.

4.	If you wish to use automatic device selection, select AUTO as the device and choose the Auto Device button to open the Auto Device Selection dialog box. Follow the steps in Specifying Devices for Automatic Device Selection.

or:

To assign a specific device, type or select a device name in the Devices box. Refer to Devices & Adapters for information on devices.

5.	If you wish to set options on a device-by-device basis, choose the Device Options button to open the Individual Device Options dialog box, which differs depending on the device that is currently selected. Follow the steps in one of the following procedures:

Specifying Individual Classic & MAX Device Options

Specifying Individual FLEX 10K Device & Pin Options

Specifying Individual FLEX 8000 Device & Pin Options

6.	If you wish to ensure that device-related logic synthesis, including timing assignment-driven synthesis, remains constant from one compilation to the next, turn on Maintain Stable Synthesis Regardless of Device or Speed Grade Changes.

7.	Choose OK.

To assign multiple devices for the current project:

1.	Choose Device.

2.	Select a device family from the Device Family drop-down list box. All devices in the selected family are shown in the Devices box.

3.	If you wish to list all packages, operating temperatures, and speed grades, turn on Show All Packages and Speed Grades.

4.	Choose the Edit Chips button to open the expanded Device dialog box.

5.	Type a chip name with up to 32 name characters in the Chip Name box to create a new chip or select an existing name from the drop-down list box. If you want to edit an existing assignment, you can select it in the Existing Device Assignments box.

6.	Repeat steps 4 through 6 in the procedure above to assign a device.

7.	If you wish to rename a chip to transfer all all pin and location assignments from the old chip to the new chip, choose the Rename Chip button to open the Rename Chip dialog box. Follow the steps in Renaming a Chip.

8.	Choose OK to save the most recent device assignment change for the current hierarchy tree and close the dialog box.

or:

Choose Add to implement the new assignment, then repeat steps 2 through 8 if you wish to enter additional device assignments or change existing assignments. The Add button changes into a Change button if you are editing an existing device assignment. After you choose Add or Change, the new or updated assignment is displayed in the Existing Device Assignments box.

See also:

Assigning Resources in a Third-Party Design Editor

Back-Annotating Assignments for a Project

Clearing Assignments for a Project

Copying a Resource Assignment

Deleting an Assignment

Fitting & Refitting a Project

Partitioning a Project

Recommended reading:

AB93 (Partitioning a Project with MAX+PLUS II Software)


Assigning a Pin, Location, or Chip (all applications)
Assigning a Pin, Location, or Chip

You can assign one or more selected logic functions to a specific chip, or a single logic function to a specific pin, logic cell, or embedded cell within a chip. In addition, instead of entering an assignment to a specific pin, logic cell, or embedded cell, you can make an assignment to a more general location, such as an LAB, EAB, row, or column. These assignments are saved in the ACF for the project. You can also enter a pin assignment to an input pin that is not connected to other logic to reserve a pin for future use, and assign two logic functions to a single logic cell to implement register packing.

Be sure to refer to Guidelines for Working with Assignments for absolutely essential information on using all types of resource, probe, and device assignments.

To enter pin, location, or chip assignments in any MAX+PLUS II application:

1.	(Optional) Select one or more nodes and/or symbols.

2.	Open the Pin/Location/Chip dialog box by choosing Pin/Location/Chip (Assign menu) or using a shortcut. If you selected a node or symbol before opening the Pin/Location/Chip dialog box, its hierarchical name is displayed in the Node Name box. If you selected multiple items before opening Pin/Location/Chip, the text **-Multiple Items-** is displayed in the Node Name box.

3.	If you did not select a node or symbol name before opening the Pin/Location/Chip dialog box, type a name in the Node Name box or choose Search to select one or more names with the Search Node Database dialog box. If you wish to edit an existing assignment, you can select it in the Existing Pin/Location/Chip Assignments box.

4.	If you wish to specify a particular chip, type a chip name with up to 32 name characters or select an existing chip name from the drop-down list box. The chip name is optional for a project that fits into a single device. (The chip name defaults to the project name.)

5.	Under Chip Resource, choose an assignment option and type an assignment or select an assignment option from the drop-down list box.

Option:	Action:

Pin	Specifies the pin number for the node name shown in the Node Name box.

LC/IOC/EC	Specifies the logic cell or I/O cell, or embedded cell number for the node name shown in the Node Name box.

LAB/EAB	Specifies the LAB or EAB name for the node names shown in the Node Name box.

Pin Type	Specifies the type of the current pin. If you have previously compiled the project, MAX+PLUS II automatically displays the pin type as Input, Output, or Bidir. Otherwise, the pin type is shown as Unspecified.

Row	Specifies the row name for the node names  shown in the Node Name box.

Col	Specifies the column number for the node names shown in the Node Name box.

6.	If necessary, specify the pin type as Input, Output, or Bidir with the Pin Type (Only for Special Cases) drop-down list box. In most cases you do not need to edit the Pin Type and can leave it as Unspecified. Exception

7.	Choose OK to save the most recent assignment change for the current hierarchy tree and close the dialog box.

or:

Choose Add to implement the new assignment, then repeat steps 3 through 7 if you wish to enter additional assignments or change existing assignments. The Add button changes into a Change button if you are editing an existing assignment. After you choose Add or Change, the new or updated assignment is displayed in the Existing Pin/Location/Chip Assignments box.

If you change only the chip name or pin type when editing an existing pin, location, or chip assignment, a new assignment is created. If you wish to change the chip name or pin type of an existing assignment, you must first add a new assignment and then delete the original one.

To edit an existing pin, location, or chip assignment in a Graphic Editor file:

Double-click Button 1 on a pin, location, or chip assignment to open the Pin/Location/Chip dialog box, edit the assignment, and choose OK.

If Show Pins/Location/Chips or Show All  (Options menu) is turned on in the Graphic Editor, the pin, logic cell, or chip assignment appears on any symbol with an assignment. Show me

To enter an individual pin, logic cell, I/O cell, or embedded cell assignment in the Floorplan Editor:

1.	If necessary, choose the Current Assignments command (Layout menu). You cannot edit assignments when the Floorplan Editor is displaying Fit File information from the last compilation.

2.	If you have a multi-device project, select the chip to edit in the Chip Names box.

3.	Choose the Device View or LAB View command (Layout menu). Although you can see pins while in LAB view for some device packages, not all LAB views display pins.

4.	Press Button 1 on a single node "handle" in the Unassigned Nodes & Pins box. (The handle, which indicates the node type, appears to the left of the name.) While holding Button 1 down, drag the node to a pin, logic cell, I/O cell, or embedded cell.

or:

Select an existing assignment from the floorplan and drag it to a new location. If you choose an assignment bin with multiple assignments, you can select a specific assignment from the Selected Node(s) & Pin(s) field, and then drag that assignment to a different location.

5 .	Release Button 1. The pin, logic cell, I/O cell, or embedded cell is highlighted, and its name changes to reflect the new assignment.

To enter pin and logic cell assignments in the Floorplan Editor on an LAB (logic cells only), EAB (embedded cells only), row, column, or anywhere on the chip:

1.	Repeat steps 1 and 2 in the procedure immediately above.

2.	If necessary, choose LAB View (Layout menu).

3.	Select one or more nodes in the Unassigned Nodes & Pins box. You can use  object-by-object or area selection.

or:

Select one or more existing assignment from the floorplan. If you choose an assignment bin with multiple assignments, you can move all of the assignments, or select a single assignment from the Selected Node(s) & Pin(s) field.

4.	While holding Button 1 down, drag the selected node(s) and/or pin(s) to an LAB Assignment Bin, EAB Assignment Bin, Row Assignment Bin, Column Assignment Bin, or the Device Assignment Bin (abbreviated with the label AoD, which stands for Anywhere on Device) in the LAB View display. To  move  items from the  Unassigned Nodes & Pins box, you must drag the node handle of one of the selected items.

5.	Release Button 1. The bin that contains these new assignments is highlighted, and the number of assigned items displayed on the bin changes to reflect the new assignment(s).

See also:

Assigning Resources in a Third-Party Design Editor

Back-Annotating Assignments for a Project

Clearing Assignments for a Project

Copying a Resource Assignment

Copying, Cutting & Pasting Node & Pin Assignments

Deleting an Assignment

Fitting & Refitting a Project

Partitioning a Project

Pin, Location & Chip Assignments

Selecting a Node, Pin, or Other Object (Floorplan Editor)

Showing Parameters and Probe & Resource Assignments (Graphic Editor)

Recommended reading:

AB93 (Partitioning a Project with MAX+PLUS II Software)


When to specify pin type popup
You must specify the Pin Type in the following cases:

For signals that travel between devices in a multi-device project, you must specify the Pin Type to distinguish the output of one device from the input(s) to other devices. In FLEX 8000 devices, you can also optionally assign the logic cell that feeds a device output to a location.

When an output and input pin on a MAX 7000 device are wired together to drive an Output Enable signal, you must specify the Pin Type to distinguish the output from the input.


Assigning a Probe (all applications)
Assigning a Probe

You can enter a probe assignment to give a short, unique name to an input or output of a primitive or macrofunction.

Be sure to refer to Guidelines for Working with Assignments for absolutely essential information on using all types of resource, probe, and device assignments.

To enter or edit a probe assignment:

1.	(Optional) Select a single node, symbol, or pinstub (as described in Selecting a Prinstub).

2.	Open the Probe dialog box by choosing Probe (Assign menu) or using a shortcut. If you selected a node or symbol before opening the Probe dialog box, its hierarchical name is displayed in the Node Name box.

3.	If you did not select a node or symbol before opening the Probe dialog box, type a name in the Node Name box or choose Search to select a name with the Search Node Database dialog box. If you wish to edit an existing probe assignment, you can select it in the Existing Probe Assignments box.

4.	Specify a probe name by typing a name with up to 32 name characters in the Probe Name box or by selecting an existing name from the drop-down list box. If you selected a node or symbol before opening the Probe dialog box, its existing probe assignment is shown as the default in the Probe Name box.

5.	Choose OK to save the most recent probe assignment change for the current hierarchy tree and close the dialog box.

or:

Choose Add to implement the new assignment, then repeat steps 3 through 5 if you wish to enter additional probe assignments or change existing assignments. The Add button changes into a Change button if you are editing an existing probe assignment. After you choose Add or Change, the new or updated assignment is displayed in the Existing Probe Assignments box.

To edit an existing probe assignment in a Graphic Editor file:

Double-click Button 1 on a probe assignment to open the Probe dialog box, enter a new probe name, and choose OK.

If Show Probes or Show All  (Options menu) is turned on in the Graphic Editor, the probe appears attached to the pinstub to which it is assigned. Show me

See also:

Clearing Assignments for a Project

Copying a Resource Assignment

Deleting an Assignment

Guidelines for Working with Assignments

Selecting a Node, Pin, or Other Object (Floorplan Editor)

Showing Parameters and Probe & Resource Assignments (Graphic Editor)


Assigning an Individual Logic Option or Synthesis Style (all applications)
Assigning an Individual Logic Option or Synthesis Style

You can assign a logic synthesis style and/or logic option that controls how the Compiler synthesizes logic for one or more selected nodes and/or symbols.

The easiest way to assign logic options is to assign an Altera-provided logic synthesis style to one or more nodes. Altera provides the following three logic synthesis styles: Normal, Fast, and WYSIWYG. You can also create a custom style, or specify individual logic options.

Each project has a default logic synthesis style that is specified with the Global Project Logic Synthesis command (Assign menu). The individual assignments you enter override the project-wide default style.

1.	Altera recommends assigning logic synthesis styles rather than individual logic options whenever possible. When both types of assignments are used, the Compiler combines the assignments according to Logic Synthesis Style & Logic Option Rules.

2.	Be sure to refer to Guidelines for Working with Assignments for absolutely essential information on using all types of resource, probe, and device assignments.

To enter individual logic synthesis styles and/or logic option assignments:

1.	(Optional) Select one or more nodes and/or symbols.

2.	Open the Logic Options dialog box by choosing Logic Options (Assign menu) or using a shortcut. If you selected a node or symbol before opening the Logic Options dialog box, its hierarchical name is displayed in the Node Name box. If you selected multiple items before opening Logic Options, the text **-Multiple Items-** is displayed in the Node Name box.

3.	If you did not select a node or symbol name before opening the Logic Options dialog box, type a name in the Node Name box or choose Search to select a name with the Search Node Database dialog box. If you wish to edit an existing logic option assignment, you can select it in the Existing Logic Option Assignments box.

4.	Choose a logic synthesis style from the Style drop-down list box to assign the style to the selected item(s).

or:

Choose Define Synthesis Style to open the Define Synthesis Style dialog box and create or edit a style, as described in Defining a Logic Synthesis Style. Choose OK to return to the Logic Options dialog box, and then assign the style to the selected items.

or:

Choose Individual Logic Options to open the Individual Logic Options dialog box, specify individual logic options, and choose OK to return to the Logic Options dialog box. When the Individual Synthesis Options dialog box is open, you can also choose Advanced Options to open the Advanced Options dialog box and specify additional individual logic options.

The following individual logic options are available. Some options are available only in a particular device family or in multi-level logic synthesis:

Carry Chain	Parallel Expanders

Cascade Chain	Reduce Logic

Decompose Gates	Refactorization

Duplicate Logic Extraction	Register Optimization

Resynthesize Network	Slow Slew Rate

I/O Cell Register	SOFT Buffer Insertion

Minimization	Subfactor Extraction

Multi-Level Factoring	Turbo Bit

NOT Gate Push-Back	XOR Synthesis

5.	Choose OK to save all assignment changes. These changes are saved to the ACF when you save the current design file.

To edit an existing logic option or style assignment in a Graphic Editor file:

Double-click Button 1 on a logic option or style assignment to open the Logic Options dialog box, enter a new logic synthesis style and/or options, and choose OK.

If Show Logic Options or Show All  (Options menu) is turned on in the Graphic Editor, the logic option(s) and/or styles appear on the bottom right corner of any symbol with a logic option assignment. Show me

See also:

Assigning Resources in a Third-Party Design Editor

Back-Annotating Assignments for a Project

Clearing Assignments for a Project

Copying a Resource Assignment

Deleting an Assignment

Fitting & Refitting a Project

Guidelines for Working with Assignments

Logic Option Assignments

Selecting a Node, Pin, or Other Object (Floorplan Editor)

Showing Parameters and Probe & Resource Assignments (Graphic Editor)

Specifying Global Project Logic Synthesis Settings


Assigning Connected Pins (all applications)
Assigning Connected Pins

You can enter external pin connection information to describe which pins in a multi-device project are connected together on your circuit board. Connected pin assignments are useful for preparing multi-device projects for timing simulation and linked simulation. They can also have a limited effect on manual partitioning. You can implement connected pin assignments with external connection pin primitives--INPUTC, OUTPUTC, and BIDIRC--in Graphic Editor files or with the Connected Pins command in any MAX+PLUS II application.

Go to Connected Pin Assignments for detailed information on the appropriate uses of connected pin assignments.

To enter or edit a connected pin assignment in any MAX+PLUS II application:

1.	(Optional) Select one or more nodes and/or symbols.

2.	Open the Connected Pins dialog box by choosing Connected Pins (Assign menu) or using a shortcut. If you selected a node or symbol before opening the Connected Pins dialog box, its hierarchical name is displayed in the Node Name box. If you selected multiple items before opening Connected Pins, the text **-Multiple Items-** is displayed in the Node Name box.

3.	If you did not select a node or symbol name before opening the Connected Pins  dialog box, type a name in the Node Name box or choose Search to select a name with the Search Node Database dialog box. If you wish to edit an existing connected pin assignment, you can select it in the Existing Connected Pin Groups box.

4.	Specify a connected pin group by typing a name with up to 32 name characters in the Connected Pin Group box or by selecting an existing name from the drop-down list box. If you selected a node or symbol before opening the Connected Pins dialog box, its existing connected pin assignment is shown as the default in the Connected Pin Group box. If you selected multiple items before opening Connected Pins, an existing connected pin assignment, if any, is displayed only if all of the selected items belong to the same connected pin group.

5.	Choose OK to save the most recent connected pin assignment change for the current hierarchy tree and close the dialog box.

or:

Choose Add to implement the new assignment, then repeat steps 3 through 5 if you wish to enter additional connected pin assignments or change existing assignments. The Add button changes into a Change button if you are editing an existing connected pin assignment. After you choose Add or Change, the new or updated assignment is displayed in the Existing Connected Pin Groups box.

To enter or edit a connected pin assignment in a Graphic Editor file:

Draw a node or bus line from the external connection pinstub of an INPUTC, OUTPUTC, or BIDIRC primitive to the external connection pinstub of another INPUTC, OUTPUTC, or BIDIRC primitive.

1.	You cannot connect pins externally for hardware-assisted functional simulation or functional testing when multiple bidirectional or output pins are tied together.

2.	Be sure to refer to Guidelines for Working with Assignments for absolutely essential information on using all types of resource, probe, and device assignments.

See also:

Combining Multiple Projects for Simulation (Compiler)

File Structure Requirements for Multi-Projects Simulation

Drawing a Line (Graphic Editor)

Devices & Adapters

Partitioning a Project

Primitive/Port Interconnections


Assigning Individual Timing Requirements (all applications)
Assigning Individual Timing Requirements

You can ensure that the Compiler optimizes your project for speed by entering timing assignments on one or more selected nodes and/or symbols in the current project.

1.	Refer to Guidelines for Timing Assignments and Guidelines for Achieving Maximum Speed Performance for information on how to use timing assignments effectively.

2.	Be sure to refer to Guidelines for Working with Assignments for absolutely essential information on using all types of resource, probe, and device assignments.

You can also specify default timing for the current project with Global Project Timing Requirements. Any individual timing assignments you enter override the project-wide default timing requirements.

To enter individual timing assignments:

1.	(Optional) Select one or more nodes and/or symbols.

2.	Open the Timing Requirements dialog box by choosing Timing Requirements (Assign menu) or using a shortcut. If you selected a node or symbol before opening the Timing Requirements dialog box, its hierarchical name is displayed in the Node Name box. If you selected multiple items before opening Timing Requirements, the text **-Multiple Items-** is displayed in the Node Name box.

3.	If you did not select a node or symbol before opening the Timing Requirements dialog box, type a name in the Node Name box or choose Search to select a name with the Search Node Database dialog box. If you wish to edit an existing timing assignment, you can select it in the Existing Timing Requirements box.

4.	Under Timing Requirements, specify one or more of the following options. (If you selected a node or symbol before opening the Timing Requirements dialog box, its existing assignments are shown as the default under Timing Requirements. If you selected multiple items before opening Timing Requirements, existing timing requirements, if any, are displayed only if all of the selected items have the same assignment; otherwise, the text ???? is displayed.)

The time you enter in each field should be followed immediately (i.e., with no space in between) by a time unit; the default unit is ns:

Option:	Action:

tpd	Specifies the maximum acceptable tpd for the selected node(s) and/or symbol(s).

tsu	Specifies the maximum acceptable tsu for the selected node(s) and/or symbol(s).

tco	Specifies the maximum acceptable tco for the selected node(s) and/or symbol(s).

fmax	Specifies the minimum acceptable fmax for the selected node(s) and/or symbol(s).

or:

To cut off the timing path for the currently selected node(s) so that it is not considered during compilation, turn on Cut Timing Path. When Cut Timing Path is turned on, it overrides any tpd, tsu, tco, or fmax assignment for a node.

5.	Choose OK to save all assignment changes in the ACF for the project.

To edit an existing timing assignment in a Graphic Editor file:

Double-click Button 1 on a timing assignment to open the Timing dialog box, enter new timing assignments and/or cuts, and choose OK.

If Show Timing Assignments or Show All  (Options menu) is turned on in the Graphic Editor, timing assignments appear on the top left corner of any symbol with an assignment. (Timing assignments are displayed above all clique assignments.) Show me

See also:

Assigning Resources in a Third-Party Design Editor

Clearing Assignments for a Project

Copying a Resource Assignment

Deleting an Assignment

Selecting a Node, Pin, or Other Object (Floorplan Editor)

Showing Parameters and Probe & Resource Assignments (Graphic Editor)

Specifying Global Project Timing Requirements


Back-Annotating Assignments for a Project (all applications)
Back-Annotating Assignments for a Project

Back-annotation is the process of copying the device, pin, logic cell (including I/O cell), and chip assignments in the Fit File from a compiled project into its ACF. This process ensures that subsequent compilations produce the same fit.

Since the Fit File is overwritten each time the project is compiled, back-annotation can be useful for retaining the current resource and device assignments for future compilations. Changes to the design files, changes to logic synthesis styles, and changes to future releases of MAX+PLUS II can all alter how the Compiler’s Fitter module places the project into one or more devices, and determine whether future compilations will use the same resource assignments.

To back-annotate resource and device assignments for the current project to the ACF:

1.	Choose Back-Annotate Project (Assign menu). The Back-Annotate Project dialog box is displayed.

2.	Select the assignments to be back-annotated.

3.	Choose OK.

Back-Annotate Project copies the pin, logic cell, chip, and device assignments from the Fit File that was generated with the most recent successful compilation into the ACF, overwriting the previous assignments. All back-annotated resource and device assignments are listed under Existing Assignments in the Pin/Location/Chip and Device dialog boxes.

The Compiler transforms clique and timing assignments into pin and logic cell assignments during compilation. Logic option assignments control logic synthesis, which in turn influences the project’s fit. Since clique, timing, and logic option assignments are not recorded in the Fit File, you cannot automatically back-annotate these assignments. In addition, connected pin assignments are not affected by back-annotation.

See also:

Assigning a Device

Assigning a Pin, Location, or Chip

Clearing Assignments for a Project

Deleting an Assignment

Fitting & Refitting a Project

Specifying Global Project Logic Synthesis Settings

Specifying Global Project Timing Requirements

Recommended reading:

AB93 (Partitioning a Project with MAX+PLUS II Software)


Clearing Assignments for a Project (all applications)
Clearing Assignments for a Project

You can clear (i.e., delete) probe, resource, and device assignments from the ACF for the current project.

To clear one or more different types of assignments in the ACF for the current project:

1.	Choose Clear Project Assignments (Assign menu). The Clear Project Assignments dialog box is displayed.

2.	Turn on the options that clear the desired assignments.

3.	Choose OK.

Clear Project Assignments affects probe, resource, and device assignments entered with the Pin/Location/Chip, Clique, Logic Options, Timing Requirements, Probe, and Device commands (Assign menu) in any MAX+PLUS II application, assignments entered in an ACF, and assignments that have been back-annotated with Back-Annotate Project (Assign menu). All of these assignments are stored in the ACF for the project.

See also:

Assigning a Clique

Assigning a Device

Assigning an Individual Logic Option or Synthesis Style

Assigning a Pin, Location, or Chip

Assigning a Probe

Assigning Individual Timing Requirements

Back-Annotating Assignments for a Project

Deleting an Assignment

Guidelines for Working with Assignments

Refitting a Project

Specifying Global Project Logic Synthesis Settings

Specifying Global Project Timing Requirements

Recommended reading:

AB93 (Partitioning a Project with MAX+PLUS II Software)


Converting an Obsolete Assignment Format (all applications)
Converting an Obsolete Assignment Format

Built-in backward compatibility in MAX+PLUS II ensures that when you open a project that was created with a pre-version 5.0 release of MAX+PLUS II, all resource, probe, and device assignment information and configuration information that exists in the project’s top-level TDF (if any), .prb file, and <project name>.ini file is automatically converted into the Assignment & Configuration File (.acf) format. However, if MAX+PLUS II reports a conversion error when opening your project, your assignments may not be fully converted into the ACF format. After you have edited the file(s) to correct the error(s) that caused the automatic conversion to fail, you can manually restart the conversion process with Convert Obsolete Assignment Format.

To reconvert assignment and configuration information from projects created with pre-version 5.0 releases of MAX+PLUS II:

Choose Convert Obsolete Assignment Format (Assign menu).

After the conversion is complete, a message is displayed to indicate that conversion has been successful.

You should use Convert Obsolete Assignment Format only if MAX+PLUS II reports a conversion error when you first open a project created with a pre-version 5.0 release of MAX+PLUS II. Convert Obsolete Assignment Format will overwrite any new assignments that you have entered with MAX+PLUS II version 5.0 or higher with the assignments from the older TDF, .prb file, and <project name>.ini file.


Copying a Resource Assignment (all applications)
Copying a Resource Assignment

To copy a pin, logic cell, embedded cell, chip, clique, logic option, timing, or connected pin assignment in the current file:

1.	(Optional) Select one or more nodes and/or symbols.

2.	Choose one of the following commands: Clique, Pin/Location/Chip, Logic Options, Timing Requirements, or Connected Pins (Assign menu). If you selected a node or symbol before opening the dialog box, its hierarchical name is displayed in the Node Name box. If you selected multiple items, the text **-Multiple Items-** is displayed in the Node Name box.

3.	If you did not select a node or symbol name before opening the dialog box, type a name in the Node Name box or choose Search to select a name with the Search Node Database dialog box.

4.	Select an existing resource assignment from the box of existing assignments.

5.	Type a different name in the Node Name box or choose Search to select a name with the Search Node Database dialog box

6.	Choose Add to copy the assignment to the box of existing assignments.

7.	Choose OK to record all assignment changes in the ACF for the project.

To copy a pin, logic cell, embedded cell, or chip assignment in the Floorplan Editor:

1.	If necessary, choose the Current Assignments command (Layout menu). You cannot edit assignments when the Floorplan Editor is displaying Fit File information from the last compilation.

2.	If you have a multi-device project, select the chip to edit in the Chip Names box.

3.	Choose the Device View or LAB View command (Layout menu). Although you can see pins while in LAB view for some device packages, not all LAB views display pins.

4.	Use Button 1 to select one or more existing assignment from the floorplan. You can use  object-by-object or area selection.

5.	(Optional) If you choose an assignment bin with multiple assignments, you can select a specific assignment from the Selected Node(s) & Pin(s) field.

6.	Choose Copy (Edit menu) or use a shortcut.

7.	Select a pin, logic cell, embedded cell, or assignment bin to which you wish to copy the assignment(s).

8.	Choose Paste (Edit menu) or use a shortcut.

See also:

Assigning a Clique

Assigning a Logic Option

Assigning a Pin, Location, or Chip

Assigning Individual Timing Requirements

Deleting an Assignment

Guidelines for Working with Assignments

Selecting a Node, Pin, or Other Object (Floorplan Editor)

Showing Parameters and Probe & Resource Assignments (Graphic Editor)

Recommended reading:

AB93 (Partitioning a Project with MAX+PLUS II Software)


Defining a Logic Synthesis Style

MAX+PLUS II allows you to create and apply one or more logic synthesis styles to individual logic functions in your design files. You can also create and apply a single default logic synthesis style for the project as a whole.

When you create a logic synthesis style, you can specify the settings for some or all of the available logic options. If a style includes default setting--i.e., it does not include a setting for a particular logic option--the Compiler searches for a setting at a higher level of the project hierarchy. A default style always exists for the project as a whole, and is specified with the Global Project Logic Synthesis command. If you do not specify a default style, the Normal style is assumed. Whether or not you choose to define the behavior of all options should depend on how you plan to use the style:

When you create a style to apply to the project as a whole, you should specify a non-default setting for each option. If you use a default setting in a project-wide style, the Logic Synthesizer substitutes the corresponding setting from the Altera-provided Normal style during compilation.

When you create a style to apply to individual logic functions, you should specify the default setting for all options that are not immediately relevant. If a style contains these default settings, the Compiler uses settings that are specified elsewhere, according to Logic Synthesis Style & Logic Option Rules.

To create or edit a logic synthesis style:

1.	Choose Global Project Logic Synthesis (Assign menu). The Global Project Logic Synthesis dialog box is displayed.

or:

Select one or more nodes and/or symbols and choose Logic Options (Assign menu) or use a shortcut to open he Logic Options dialog box.

2.	Choose the Define Synthesis Style button. The Define Synthesis Style dialog box is displayed.

3.	Select the name of an existing style, or select <new> from the Style drop-down list box. You can also choose an existing style to use as the basis for a new style.

4.	If you wish, select a different device family from the Device Family drop-down list box.

5.	To reset all options for the current device family, choose Use Default. If you are editing an Altera-provided style, Use Default button changes all settings to the predefined Altera settings for the style. If you are editing a user-defined style, it sets all radio button and three-way checkbox options to the default setting. You can choose this button at any time to reset the options for the current family.

6.	Choose a setting for one or more of the following logic options. Radio buttons or three-way checkboxes are used to specify each option or the default setting. Any options that are dimmed do not apply to the current device family, or are available only when Multi-Level Synthesis is turned on in the Global Project Logic Synthesis dialog box.

Slow Slew Rate 	Use LPM for AHDL Operators

XOR Synthesis	Minimization

Turbo Bit 	Carry Chain

Parallel Expanders 	Cascade Chain

Ignore SOFT Buffers

For the Cascade Chain and Carry Chain options, you can also limit the maximum length of the cascade or carry chain by typing a whole non-zero number in the Max. Length box. The upper limit on the length of the chain depends on the resources available in the target device(s) for the project.

7.	If you wish to set advanced logic options for the current device family, choose Advanced Options. The Advanced Options dialog box is displayed.

a.	Choose a setting for one or more of the following options. Three-way checkboxes are used to specify each option.

SOFT Buffer Insertion 	Refactorization

Decompose Gates 	Subfactor Extraction

Reduce Logic 	Multi-Level Factoring

Duplicate Logic Extraction 	Resynthesize Network

NOT Gate Push-Back 	Register Optimization

b.	To reset all options in this dialog box for the current device family, choose Use Default. If you are editing an Altera-provided style, Use Default changes all settings to the predefined Altera settings for the style. If you are editing a user-defined style, all radio button and three-way checkbox options are set to the default state. You can choose this button at any time to reset the options.

c.	Choose OK to temporarily save the changes and return to the Define Synthesis Style dialog box. The changes entered in the Advanced Options dialog box are saved permanently when you save the style.

8.	If you wish to specify different options for a different device family to be saved in the current style, repeat steps 4 through 7. Within a single style, you can define different logic option settings for different device families to fine-tune the logic synthesis process for a particular architecture.

9.	If you wish to save the settings to a new style name:

a.	Choose Save Style As. The Save Style As dialog box is displayed.

b.	Type a name with up to 32 name characters in the Style Name box. The current style name is displayed as the default.

c.	Choose OK to save the logic option settings under the specified style name and return to the Define Synthesis Style dialog box.

10.	If you wish to define additional styles, repeat steps 3 through 8. If you edit an existing style and then choose another style to edit, MAX+PLUS II always asks whether you wish to save the changes.

11.	 If you wish to delete the current style shown in the Style box, choose Delete Style. (You cannot delete the <new>, Normal, Fast, and WYSIWYG styles.)

12.	Choose OK to save all changes since the last save, or choose Cancel to discard all changes since the last save.

See also:

Assigning an Individual Logic Option or Synthesis Style

Specifying Global Project Logic Synthesis Settings


Deleting an Assignment (all applications)
Deleting an Assignment

To delete a probe or resource assignment in the current file:

1.	(Optional) Select a pinstub, node, or symbol.

2.	Depending on the type of assignment, choose the Pin/Location/Chip, Clique, Logic Options, Timing Requirements, or Probe command (Assign menu).

3.	If you did not select a node or symbol in step 1, select a name in the box of existing assignments. If you selected a node or symbol before opening the dialog box, the name or hierarchical name is displayed.

4.	Choose the Delete button to remove all assignments for the node.

or:

Select the probe, chip, logic cell, pin, clique, logic option, or timing assignment you wish to delete, press the Del key to delete the assignment, and choose Change to record the changed assignments in the Existing Assignments box.

5.	Choose OK to save all assignment changes to the ACF for the project.

To delete probe and/or resource assignments in the Graphic Editor:

1.	Select one or more assignments to delete with Button 1.

2.	Choose Delete (Edit menu) or use shortcut.

To delete resource assignments in the Floorplan Editor:

1.	Select one or more assignments to delete. You can use area  or object-by-object selection.

2.	Choose Delete or use shortcut. The unassigned nodes and pins are displayed in the Unassigned Nodes and Pins box.

To delete a device assignment:

1.	Choose Device (Assign menu). The Device dialog box is displayed.

2.	Choose the Edit Chips button to open the expanded Device dialog box.

3.	Type the name of a previously assigned chip in the Chip Name box or select an existing name from the drop-down list box. Any existing device assignments are listed in the Existing Assignments box.

4.	Select the assignment you wish to delete from the Existing Assignments box..

5.	Choose Delete or use shortcut to delete the assignment.

1.	Only the device assignment is deleted. The chip name is assigned to AUTO. If you wish, you can re-select it from the Chip Name box and assign it to a different device.

2.	A single-device project that is not assigned to a specific device is assigned to AUTO.

6.	Choose OK to record all assignment changes in the ACF for the project.

See also:

Assigning a Clique

Assigning a Device

Assigning an Individual Logic Option or Synthesis Style

Assigning a Pin, Location, or Chip

Assigning a Probe

Assigning Individual Timing Requirements

Back-Annotating Assignments for a Project

Clearing Assignments for a Project

Copying a Resource Assignment

Deleting an Assignment

Guidelines for Working with Assignments

Refitting a Project

Selecting a Node, Pin, or Other Object

Selecting Text

Showing Parameters and Probe & Resource Assignments (Graphic Editor)

Specifying Global Project Logic Synthesis Settings

Specifying Global Project Timing Requirements

Recommended reading:

AB93 (Partitioning a Project with MAX+PLUS II Software)


Demoting an Assignment (Floorplan Editor)
Demoting an Assignment

You can "demote" selected pin and/or location assignment(s) to less restrictive assignments so that the Compiler can more freely rearrange the assignments for greater efficiency.

You can choose to demote any combination of assignments, including assignments to pins, logic cells, I/O cells, rows, columns, and/or LABs.

To demote one or more pin and/or logic cell assignment(s) in the current floorplan:

1.	Select one or more assignments to demote. You can use area or object-by-object selection.

2.	Open the Demote Assignments dialog box by choosing Demote Assignments (Assign menu) or using a shortcut.

3.	Select one of the following types of assignment bins under Demote Assignments to:

Device Assignment Bin	Column Assignment Bin

Any Column Assignment Bin	Row Assignment Bin

Any Row Assignment Bin	LAB Assignment Bin

4.	Choose OK. The selected assignments are demoted to the designated type of assignment bin.

See also:

Assigning a Pin, Location, or Chip

Fitting & Refitting a Project

Guidelines for Working with Assignments

Selecting a Node, Pin, or Other Object

Recommended reading:

AB93 (Partitioning a Project with MAX+PLUS II Software)


Ignoring Project Assignments during Compilation (all applications)
Ignoring Project Assignments during Compilation

If you compile a project with assignments that fails to fit, you can set the Compiler to ignore specified individual and global assignments. You can then recompile the project to determine whether the assignments prevented the project from fitting.

As an alternative, you can specify options to be ignored during compilation in the Ignored Assignments Section of the ACF.

1.	Refer to Guidelines for Timing Assignments for information on how to use timing assignments effectively.

2.	Be sure to refer to Guidelines for Working with Assignments for absolutely essential information on using all types of resource, probe, and device assignments.

To ignore assignments when compiling the current project:

1.	Choose Ignore Project Assignments (Assign menu). The Ignore Project Assignments dialog box is displayed.

2.	Turn on the options that specify the desired assignments to be ignored.

3.	Choose OK.

See also:

Clearing Assignments for a Project

Deleting an Assignment

Selecting a Probe or Resource Assignment

Showing Parameters and Probe & Resource Assignments

Specifying Global Project Timing Requirements


Renaming a Chip (all applications)
Renaming a Chip

You can easily rename a chip--and thus transfer all pin and location assignments from the old chip to the new chip--without manually editing the ACF for the project.

If you save a top-level design file to a new name and the current chip names are based on the project name, MAX+PLUS II usually can automatically rename chips, and the Rename Chip dialog box is not needed. The Rename Chip dialog box is useful for renaming chips if your current project contains chip names that are not based on the project name and you wish to save the top-level-design file to a new name. If both projects are in the same directory and you do not rename the chips in one of them, the programming files from one project--whose names are based on chip names--can overwrite the programming files from the other.

To rename a chip:

1.	Choose Device (Assign menu). The Device dialog box is displayed.

2.	Choose the Edit Chips button to open the expanded Device dialog box.

3.	Choose the the Rename Chip button. The Rename Chip dialog box is displayed.

4.	Type a chip name with with up to 32 name characters in the New Chip Name box.

5.	Choose OK. You are returned to the Device dialog box.

See also:

Assigning a Device

Assigning a Pin, Location, or Chip


Searching the Node Database (all applications)
Searching the Node Database

You can search the node database to find and select any node or pin in the current project.

To select a node or pin from the database:

1.	To open the Search Node Database dialog box, choose the Search button in one of the following dialog boxes: Clique, Pin/Location/Chip, Probe, Logic Options, Timing Requirements, or Connected Pins (Assign menu).

2.	Type a text string that contains wildcard character for pattern matching when generating the list of nodes in the Names in Database box.

3.	Turn on one or more List Nodes of Type options to specify the type of nodes and pins to list.

4.	If you wish to list all possible hierarchical node names, turn on the Show All Node Name Synonyms option.

5.	To list functions implemented in logic cells, turn on the Functions Implemented in Logic Cells option.

6.	Choose List to list all nodes and pins that match the List Nodes of Type options and the text string in the Node Name field in the Names in Database box.

7.	Select a node or pin from the Names in Database box. The node or pin name replaces the text in the Node Name field.

8.	Choose OK to close the Search Node Database dialog box. The selected node or pin name is copied to the Node Name field of the first-level dialog box.

Until the project has been compiled, only nodes to which assignments have been made are listed when you choose the List button. You must compile the project before all existing nodes can be listed.

See also:

Assigning a Clique

Assigning a Pin, Location, or Chip

Assigning a Probe

Assigning an Individual Logic Option or Synthesis Style

Assigning Connected Pins

Assigning Individual Timing Requirements


Specifying Devices for Automatic Device Selection (all applications)
Specifying Devices for Automatic Device Selection

Although the Compiler can automatically select the devices for a project, you can control the devices the Compiler uses. You can specify a particular device family, which devices the Compiler can choose from that family, and the number allowed of each device. You can also direct the Compiler to ask before it adds devices during partitioning.

The Compiler automatically selects devices in the following circumstances:

When one or more device assignments assign chip(s) to AUTO device(s) in the Device dialog box. AUTO is also the default if no user-specified chip or device assignments exist.

When the existing devices assigned for the project cannot fit all of the project's logic and additional devices must be added.

If you do not choose specific devices or a specific number of devices, the Compiler defaults to an unlimited number of devices from the current device family.

To specify devices for the Compiler to use in automatic device selection:

1.	Choose Device (Assign menu).

2.	Select a device family from the Device Family box. All devices in the selected family are shown in the Devices box.

3.	Choose the Auto Device button to open the Auto Device Selection dialog box. The Auto Device Selection dialog box is displayed with the name of the device family you selected. All devices in the selected family are shown in the Available Devices box. By default, generic devices for the selected family are listed in the # / Selected Devices box.

4.	To show device names with package types and speed grades in the Available Devices box, turn on Show All Packages & Speed Grades.

5.	If you wish to remove devices from the list of devices to be used for the project, select one or more device names from the # / Selected Devices box and choose the left direction button (<=). Or, double-click Button 1 on a single name to move it out of the box.

6.	If you wish to add devices to the list of selected devices, double-click Button 1 on a single name in the Available Devices box or select one or more device names and choose the right direction button (=>).

7.	If you wish, select one or more devices in the # / Selected Devices box and select Limited or Unlimited under Number Allowed. If you select Limited, type an integer between 1 and 99 in the text box.

8.	To direct the Compiler to ask before adding devices during partitioning, turn on Ask Before Adding Extra Devices . This feature is useful if you want your project to fit into a single device.

9.	Choose OK.

10.	To begin compilation, choose the Start button in the Compiler window or the Project Save & Compile command (File menu) in any MAX+PLUS II application.

Be sure to refer to Guidelines for Working with Assignments for absolutely essential information on using all types of types of resource, probe, and device assignments.

See also:

Adjusting the Fit During Compilation

Assigning a Device

Fitting & Refitting a Project

Partitioning a Project


Specifying Global Project Classic & MAX Device Options (all applications)
Specifying Global Project Classic & MAX Device Options

You can specify default device options settings, such as the Security Bit and the percentage of reserved pin and/or logic cell resources, for all Classic, MAX 5000, MAX 7000, or MAX 9000 devices used in the current project. These defaults apply only to those devices for which you have not already specified a setting in the design files.

You can also set the Security Bit for each device in a project on a device-by-device basis with the Individual Classic & MAX Device Options dialog box (opened from the Device dialog box). The Security Bit setting can also be overridden after compilation with the Programmer’s Security Bit option.

After you specify the reserved resources, to see the actual percentage of resources remaining in each device after a project is compiled, refer to the Device Summary Section of the Report File.

To set the project-wide default Security Bit and reserved resources settings:

1.	Specify the Classic, MAX 5000, MAX 7000, or MAX 9000 device family for the current project. Follow the steps in Assigning a Device.

2.	Choose Global Project Device Options (Assign menu). The Classic & MAX Global Project Device Options dialog box is displayed.

3.	Turn Security Bit on or off.

4.	To specify a percentage of resources to be reserved, type an integer between 0 and 99 in the I/O Pins and/or Logic Cells box or use the arrow keys to select a number.

5.	Choose OK.

See also:

Adjusting the Fit During Compilation

Assigning a Device

Back-Annotating Assignments for a Project

Fitting & Refitting a Project

Setting the Security Bit (Programmer)

Specifying Global Project FLEX 10K Device & Pin Options

Specifying Global Project FLEX 8000 Device & Pin Options

Specifying Individual Classic & MAX Device Options

Specifying Individual FLEX 10K Device & Pin Options

Specifying Individual FLEX 8000 Device & Pin Options


Specifying Global Project FLEX 8000 Device & Pin Options (all applications)
Specifying Global Project FLEX 8000 Device & Pin Options

When you implement a project in one or more FLEX 8000 devices, you can set several device options and reserve dual-purpose pins so they are not used as I/O pins during user mode, i.e., after configuration and initialization have been completed. Reserved dual-purpose pins can be tri-stated or allowed to drive out VCC, GND, or a signal.

You can specify the project-wide default settings for these device and pin options in any MAX+PLUS II application. You can also override these defaults by setting the options on a device-by-device basis with the Individual FLEX 8000 Device Options dialog box (opened from the Device dialog box).

To specify project-wide default FLEX 8000 device and pin options:

1.	Specify the FLEX 8000 device family for the current project. Follow the steps in Assigning a Device.

2.	Choose Global Project Device Options (Assign menu). The FLEX 8000 Global Project Device Options dialog box is displayed.

3.	If you wish, turn on one or more of the following device options:

User-Supplied Start-Up Clock	Enable DCLK Output in User Mode

Auto-Restart Configuration on Frame Error	Disable Start-Up Time-Out

Release Clears Before Tri-States	Enable JTAG Support

4.	If you wish, select a different FLEX 8000 device configuration scheme from the Configuration Scheme drop-down list box. The following configuration schemes are available:

Active Serial	Passive Serial

Active Parallel Up	Passive Parallel Synchronous

Active Parallel Down	Passive Parallel Asynchronous

After you choose a particular configuration scheme, the Reserve and Tri-State settings for the pins listed under Dual-Purpose Configuration Pins change to show the recommended settings for the dual-purpose pins in the specified configuration scheme.

5.	If you wish to reserve a pin listed under Dual-Purpose Programming Pins, turn on Reserve. The Reserve option determines whether the pin is used as an I/O pin in user mode.

6.	For each dual-purpose pin that is reserved (i.e., checked) in step 5, turn on Tri-State to tri-state a pin (i.e., place the pin in a state of high impedance) listed under Dual-Purpose Programming Pins.

7.	If necessary, repeat steps 5 and 6 for the pin(s) listed under Not Affected By Configuration Scheme.

8.	Choose OK to save all changes.

9.	To begin compilation, choose the Start button in the Compiler window or the Project Save & Compile command (File menu) in any MAX+PLUS II application.

See also:

Devices & Adapters

Specifying Global Project Classic & MAX Device Options

Specifying Global Project FLEX 10K Device & Pin Options

Specifying Individual Classic & MAX Device Options

Specifying Individual FLEX 10K Device & Pin Options

Specifying Individual FLEX 8000 Device & Pin Options

Recommended reading:

AN33 (Configuring FLEX 8000 Devices)

AN38 (Configuring Multiple FLEX 8000 Devices)


Specifying Global Project FLEX 10K Device & Pin Options (all applications)
Specifying Global Project FLEX 10K Device & Pin Options

When you implement a project in one or more FLEX 10K devices, you can set several device options and reserve dual-purpose pins so they are not used as I/O pins during user mode, i.e., after configuration and initialization have been completed. Reserved dual-purpose pins can be tri-stated or allowed to drive out VCC, GND, or a signal.

You can specify the project-wide default settings for these device and pin options in any MAX+PLUS II application. You can also override these defaults by setting the options on a device-by-device basis with the Individual FLEX 10K Device Options dialog box (opened from the Device dialog box).

To specify project-wide default FLEX 8000 device and pin options:

1.	Specify the FLEX 10K device family for the current project. Follow the steps in Assigning a Device.

2.	Choose Global Project Device Options (Assign menu). The FLEX 10K Global Project Device Options dialog box is displayed.

3.	If you wish, turn on one or more of the following device options:

User-Supplied Start-Up Clock	Enable Chip-Wide Reset

Auto-Restart Configuration on Frame Error	Enable Chip-Wide Output Enable

Release Clears Before Tri-States	Enable INIT_DONE Output

4.	If you wish, select a different FLEX 10K device configuration scheme from the Configuration Scheme drop-down list box. The following configuration schemes are available:

Passive Serial

Passive Parallel Synchronous

Passive Parallel Asynchronous

After you choose a particular configuration scheme, the Reserve and Tri-State settings for the pins listed under Dual-Purpose Configuration Pins change to show the recommended settings for the dual-purpose pins in the specified configuration scheme.

5.	If you wish to reserve a pin listed under Dual-Purpose Programming Pins, turn on Reserve. The Reserve option determines whether the pin is used as an I/O pin in user mode.

6.	For each dual-purpose pin that is reserved (i.e., checked) in step 5, turn on Tri-State to tri-state a pin (i.e., place the pin in a state of high impedance) listed under Dual-Purpose Programming Pins.

7.	If necessary, repeat steps 5 and 6 for the pin(s) listed under Not Affected By Configuration Scheme.

8.	Choose OK to save all changes.

9.	To begin compilation, choose the Start button in the Compiler window or the Project Save & Compile command (File menu) in any MAX+PLUS II application.

Specifying Global Project Classic & MAX Device Options

Specifying Global Project FLEX 8000 Device & Pin Options

Specifying Individual Classic & MAX Device Options

Specifying Individual FLEX 10K Device & Pin Options

Specifying Individual FLEX 8000 Device & Pin Options

Recommended reading:

AN 59 (Configuring FLEX 10K Devices)


Specifying Global Project Logic Synthesis Settings (all applications)
Specifying Global Project Logic Synthesis Settings

You can specify a default logic synthesis style and which global signals, such as Clock, Clear (or Reset), Preset, and/or Output Enable signals, the Compiler should automatically create for the project as a whole. In addition, you can also specify global default settings for logic options, such as automatic one-hot encoding, register packing, and open-drain pins.

You can apply one of the Altera-provided logic synthesis styles as the project-wide default style, or create your own style with the Define Synthesis Style dialog box. Within a design file, you can override the project’s default logic synthesis style on one or more logic functions by assigning a different logic synthesis style or individual logic option. You can also override the default logic synthesis style for the logic cell Turbo Bit option on a device-by-device basis.

Be sure to refer to Guidelines for Working with Assignments for absolutely essential information on using all types of types of resource, probe, and device assignments, including logic synthesis style and logic option assignments.

The Compiler can create automatic global signals specified with this command only if the devices for the project have unused global signals after the Compiler has implemented the global signals you have explicitly specified, if any, with the GLOBAL primitive in design files for the project.

MAX+PLUS II version 6.0 and higher may create more automatic global signals for some devices than earlier versions of MAX+PLUS II. If you have problems with fitting projects that compiled with earlier versions of MAX+PLUS II because of automatic global signal changes, you should turn off the appropriate option under Automatic Global. You can then implement global signals by inserting GLOBAL buffers into your project.

To set the project-wide default style for logic synthesis and create automatic global signals:

1.	Choose Global Project Logic Synthesis (Assign menu). The Global Project Logic Synthesis dialog box is displayed.

2.	Select a logic synthesis style from the Global Project Synthesis Style box. If the style you select does not specify all logic option settings (i.e., if any logic option is set to the default state with the three-way checkbox), the Compiler uses the settings from the Normal style for those options.

3.	If you wish, set the Optimizedef_optimize option to 0 to minimize area, to 10 to maximize speed, or to a setting in between to adjust the speed/area tradeoff.

4.	If you wish, turn on one or more of the following logic options:

Multi-Level Synthesis fpr MAX Devices	Automatic Register Packing

One-Hot State Machine Encoding	Automatic Open Pins

Automatic I/O Cell Registers	Automatic Implement in EAB

5.	If you wish, turn on one or more of the options under Automatic Global to create global signals for the project. (The Clear option provides a global Reset signal for a state machine.) Global signals are used in different device families according to global signal availability.

6.	To create a new logic synthesis style or edit an existing style in the Define Synthesis Style dialog box, as described in Defining a Logic Synthesis Style, choose Define Synthesis Style.

7.	Choose OK.

See also:

Assigning a Device

Assigning an Individual Logic Option or Synthesis Style

Fitting & Refitting a Project


Specifying Global Project Parameters (all applications)
Specifying Global Project Parameters

You can specify default parameters and parameter values for the current project.

Be sure to refer to Guidelines for Working with Assignments for absolutely essential information on using all types of types of resource, probe, and device assignments, including logic synthesis style and logic option assignments.

To set the project-wide default parameters:

1.	Choose Global Project Parameters (Assign menu). The Global Project Parameters dialog box is displayed.

2.	Type a name with up to 32 name characters in the Parameter Name field. If you wish to edit an existing parameter, you can select it in the Parameters list box.

3.	Enter a decimal, binary, octal, or hexadecimal number or a quoted or unquoted string (e.g., "unsigned") in the Parameter Value field.

4.	Choose OK to save the changes and additions and close the dialog box.

or:

Choose Add to implement the new parameter, then repeat steps 2 through 4 if you wish to enter additional parameters or change existing parameters. The Add button changes into a Change button if you are editing an existing parameter. After you choose Add or Change, the new or updated parameter is displayed in the Parameters list box.

If you change only the parameter name when editing an existing parameter, a new parameter is created. If you wish to change the name of an existing parameter, you must first add a new parameter and then delete the original one.

See also:

Customizing a Macrofunction's Ports and Parameters

Deleting a Parameter

Entering a Parameter


Specifying Global Project Timing Requirements (all applications)
Specifying Global Project Timing Requirements

You can specify the default timing for tpd, tco, tsu, and/or fmax for the entire project.

To specify the default timing for the project:

1.	Choose Global Project Timing Requirements (Assign menu). The Global Project Timing Requirements dialog box is displayed.

2.	Under Global Project Timing Requirements, specify one or more of the following options. The time you enter in each field should be followed immediately (i.e., with no space in between) by a time unit:

Option:	Action:

tpd	Specifies the maximum acceptable default tpd for the project.

tsu	Specifies the maximum acceptable default tsu for the project.

tco	Specifies the maximum acceptable default tco for the project.

fmax	Specifies the minimum acceptable default fmax for the project.

3.	If you wish to cut the connections between the timing paths for all bidirectional pins in the project, turn on Cut All Bidirectional Feedback Timing Paths.

4.	If you wish to cut the connections between the timing paths for all Preset and Clear signals in the project, turn on Cut All Clear & Preset Timing Paths.

5.	Choose OK to save all changes.

6.	To begin compilation, choose the Start button in the Compiler window or the Project Save & Compile command (File menu) in any MAX+PLUS II application.

You can also assign a timing specification to selected nodes and/or symbols with the Timing Requirements command (Assign menu) in any MAX+PLUS II application.

1.	Refer to Guidelines for Timing Assignments and Guidelines for Achieving Maximum Speed Performance for information on how to use timing assignments effectively.

2.	Be sure to refer to Guidelines for Working with Assignments for absolutely essential information on using all types of resource, probe, and device assignments.

See also:

Assigning Individual Timing Requirements

Fitting & Refitting a Project


Specifying Individual Classic & MAX Device Options (all applications)
Specifying Individual Classic & MAX Device Options

You can set the Security and Turbo Bit for each Classic, MAX 5000, MAX 7000, or MAX 9000 device in a project on a device-by-device basis.

You can specify the default Security Bit setting for the entire project with the Classic & MAX Global Project Device Options dialog box. (You open this dialog box by choosing the Global Project Device Options command (Assign menu) when the Classic or MAX device family is currently specified for the project.) The Security Bit setting can also be overridden after compilation with the Programmer’s Security Bit option.

To specify the Security and Turbo Bit setting for the current device:

1.	Choose Device (Assign menu). The Device dialog box is displayed.

2.	Specify the Classic, MAX 5000, MAX 7000, or MAX 9000 device family for the current project.

3.	Choose the Device Options button to open the Classic & MAX Individual Device Options dialog box.

4.	Specify a setting for the Turbo Bit device option for the device. You can set the three-way checkbox to on or off, or leave it grayed to allow the default logic synthesis style for the entire project to specify the default Turbo Bit setting for all devices in the project.

5.	Specify a setting for the Security Bit device option for the device. You can set the three-way checkbox to on or off, or leave it grayed to allow the Classic & MAX Global Project Device Options dialog box or the Programmer’s Security Bit option to set the Security Bit.

6.	Choose OK to save all changes and return to the Device dialog box.

As an alternative, you can assign Turbo and Security Bit settings in the ACF.

See also:

Assigning a Device

Setting the Security Bit (Programmer)

Specifying Global Project Classic & MAX Device Options

Specifying Global Project FLEX 10K Device & Pin Options

Specifying Global Project FLEX 8000 Device & Pin Options

Specifying Individual FLEX 10K Device & Pin Options

Specifying Individual FLEX 8000 Device & Pin Options


Specifying Individual FLEX 8000 Device & Pin Options

When you assign a chip to a FLEX 8000 device, you can specify the settings for FLEX 8000-specific device options and pin options. You can set these options on a device-by-device basis when you assign a chip to a device with  Device in any MAX+PLUS II application.

You can also specify the project-wide default settings for FLEX 8000-specific device and pin options with the FLEX 8000 Global Project Device Options dialog box. (You open this dialog box by choosing the Global Project Device Options command (Assign menu) when the FLEX 8000 device family is currently specified for the project.) These settings are used only if you specify the default (grayed) option with the three-way checkboxes while specifying individual options (as described in this procedure).

To specify device and pin options for a single FLEX 8000 device (i.e., on a device-by-device basis):

1.	Choose Device (Assign menu). The Device dialog box is displayed.

2.	Specify the FLEX 8000 device family for the current project.

2.	Choose the Device Options button to open the FLEX 8000 Individual Device Options dialog box.

3.	If you wish, turn on one or more of the following device options with the three-way checkboxes:

User-Supplied Start-Up Clock	Enable DCLK Output in User Mode

Auto-Restart Configuration on Frame Error	Disable Start-Up Time-Out

Release Clears Before Tri-States	Enable JTAG Support

4.	If you wish to specify a configuration scheme, choose Use Global Project Setting to use the setting specified for the project as a whole in the FLEX 8000 Global Project Device Options dialog box, or choose a configuration scheme from the Configuration Scheme drop-down list box. The following configuration schemes are available:

Active Serial	Passive Serial

Active Parallel Up	Passive Parallel Synchronous

Active Parallel Down	Passive Parallel Asynchronous

If you choose a particular configuration scheme, the Reserve and Tri-State settings for the pins listed under Dual-Purpose Configuration Pins change to show the recommended settings for the dual-purpose pins in the selected configuration scheme.

5.	If you wish, specify the Reserve setting for individual dual-purpose pins with the three-way checkbox. The Reserve option determines whether the pin is used as an I/O pin in user mode.

6.	If you wish, for each dual-purpose pin that is reserved (i.e., checked) in step 6, specify the Tri-State setting with the three-way checkbox. The Tri-State option determines whether the pin is tri-stated or allowed to drive out a signal in user mode.

7.	Choose OK to save all changes and return to the Device dialog box.

See also:

Devices & Adapters

Specifying Global Project Classic & MAX Device Options

Specifying Global Project FLEX 10K Device & Pin Options

Specifying Global Project FLEX 8000 Device & Pin Options

Specifying Individual Classic & MAX Device Options

Specifying Individual FLEX 8000 Device & Pin Options

Recommended reading:

AN33 (Configuring FLEX 8000 Devices)

AN38 (Configuring Multiple FLEX 8000 Devices)


Specifying Individual FLEX 10K Device & Pin Options

When you assign a chip to a FLEX 10K device, you can specify the settings for FLEX 10K-specific device options and pin options. You can set these options on a device-by-device basis when you assign a chip to a device with  Device in any MAX+PLUS II application.

You can also specify the project-wide default settings for FLEX 10K-specific device and pin options with the FLEX 10K Global Project Device Options dialog box. (You open this dialog box by choosing the Global Project Device Options command (Assign menu) when the FLEX 10K device family is currently specified for the project.) These settings are used only if you specify the default (grayed) option with the three-way checkboxes while specifying individual options (as described in this procedure).

To specify device and pin options for a single FLEX 10K device (i.e., on a device-by-device basis):

1.	Choose Device (Assign menu). The Device dialog box is displayed.

2.	Specify the FLEX 10K device family for the current project.

2.	Choose the Device Options button to open the FLEX 10K Individual Device Options dialog box.

3.	If you wish, turn on one or more of the following device options with the three-way checkboxes:

User-Supplied Start-Up Clock	Enable Chip-Wide Reset

Auto-Restart Configuration on Frame Error	Enable Chip-Wide Output Enable

Release Clears Before Tri-States	Enable INIT_DONE Output

4.	If you wish to specify a configuration scheme, choose Use Global Project Setting to use the setting specified for the project as a whole in the FLEX 8000 Global Project Device Options dialog box, or choose a configuration scheme from the Configuration Scheme drop-down list box. The following configuration schemes are available:

Passive Serial

Passive Parallel Synchronous

Passive Parallel Asynchronous

If you choose a particular configuration scheme, the Reserve and Tri-State settings for the pins listed under Dual-Purpose Configuration Pins change to show the recommended settings for the dual-purpose pins in the selected configuration scheme.

5.	If you wish, specify the Reserve setting for individual dual-purpose pins with the three-way checkbox. The Reserve option determines whether the pin is used as an I/O pin in user mode.

6.	If you wish, for each dual-purpose pin that is reserved (i.e., checked) in step 6, specify the Tri-State setting with the three-way checkbox. The Tri-State option determines whether the pin is tri-stated or allowed to drive out a signal in user mode.

7.	Choose OK to save all changes and return to the Device dialog box.

Specifying Global Project Classic & MAX Device Options

Specifying Global Project FLEX 10K Device & Pin Options

Specifying Global Project FLEX 8000 Device & Pin Options

Specifying Individual Classic & MAX Device Options

Specifying Individual FLEX 8000 Device & Pin Options

Recommended reading:

AN 59 (Configuring FLEX 10K Devices)


Showing the Floorplan for Current Assignments (Floorplan Editor)
Showing the Floorplan for Current Assignments

You can display and edit the current pin, logic cell, and/or I/O cell assignments to a device in the Floorplan Editor. You can use the Floorplan Editor to enter and edit assignments for the current project. In addition, the Floorplan Editor reflects any changes to assignments made with other assignment entry methods, such as the Pin/Location/Chip command or text entry in an ACF.

The Floorplan Editor cannot display a floorplan for a chip assigned to an AUTO device.

To display the floorplan for current assignments in the Floorplan Editor:

Choose the Current Assignments Floorplan command (Layout menu).

See also:

Showing Moved Nodes in Gray

Showing the Floorplan for the Last Compilation

Viewing a Device in the Device View or LAB View


Showing the Floorplan for the Last Compilation (Floorplan Editor)
Showing the Floorplan for the Last Compilation

In the Floorplan Editor, you can display a read-only version of the project’s assignment information from the most recent project compilation. This information is stored in the Fit File for the project.

To display the read-only floorplan for the last compilation in the Floorplan Editor:

Choose the Last Compilation Floorplan command (Layout menu).

The text Last Compilation (Successful) or Last Compilation (Unsuccessful) appears in the title bar depending on the results of the compilation.

This command is available only if you have previously compiled the project until the Fitter has generated a Fit File and Report File.

See also:

Showing Moved Nodes in Gray

Showing the Floorplan for Current Assignments

Viewing a Device in the Device View or LAB View


Viewing a Device in the Device View or the LAB View (Floorplan Editor)
Viewing a Device in the Device View or LAB View

You can view a device for the current project in the Floorplan Editor in either the Device View  or LAB View display. In the Device View display, which is the default display, you can make pin assignments to individual pins. In the LAB View display, you can enter pin and location assignments.

The Floorplan Editor cannot display a floorplan for a chip assigned to an AUTO device.

To view a device in the Device View or LAB View display in the Floorplan Editor:

1.	If you have a partitioned project, select the chip name and corresponding device that you wish to view in the Chip Name field.

2.	Double-click Button 1 on a blank portion of the device in either the Device View or LAB View display to switch to the other view.

or:

Choose the Device View or LAB View command (Layout menu).

See also:

Showing Moved Nodes in Gray

Showing the Floorplan for Current Assignments

Showing the Floorplan for the Last Compilation

Turning Full Screen Viewing On or Off


Selecting a Node, Pin, or Other Object (Floorplan Editor)
Selecting a Node, Pin, or Other Object

In the Floorplan Editor, two types of selection are available: area selection and object-by-object selection. You can select one or more pins, nodes, logic cells, I/O cells, embedded cells, or assignment bins in the display area, or pin and/or node names in the Unassigned Nodes & Pins box with Button 1 and additional keys.

To select a single object:

Click Button 1 on the object.

Clicking Button 1 on a pin name or pin number also selects a pin.

If the selected object has multiple assignments, the Selected Node(s) & Pin(s) field displays the text <Multiple items>. To select one of these assignments:

Use Button 1 to select a specific assignment from the drop-down list box in the Selected Node(s) & Pin(s) field.

To select more than one discontiguous object in the device, use one of the following mouse/key combinations:

Mouse/Key:	Action:

Shift+Click	Selects a single object and adds it to a previous selection.

Shift+Press, Drag, Release	Selects all objects from the point where Button 1 is pressed to the point where it is released and adds the objects to an existing selection, if any.

You can mix area and object-by-object selection.

To select more than one discontiguous object in the Unassigned Nodes & Pins box, use one of the following mouse/key combinations:

Mouse/Key:	Action:

Ctrl+Click	Selects a single object and adds it to a previous selection.

Ctrl+Press, Drag, Release	Selects all objects from the point where Button 1 is pressed to the point where it is released and adds the objects to an existing selection, if any.

You can mix area and object-by-object selection.

To select an area within the device, you must point to an empty space. To select an area in the  Unassigned Nodes & Pins box, point to a node or pin name (not the node "handle" that appears to the left of the name). Then, use one of the following mouse/key combinations:

Mouse/Key:	Action:

Press, Drag, Release	Selects all objects from where Button 1 is pressed to where it is released.

Click, Move, Shift+Click	Selects all objects between the first click and the Shift+Click.

When you have selected one or more item(s) in the Unassigned Nodes & Pins box, you can move them to the Device or LAB View by dragging the node handle of one of the selected item(s).


Showing Moved Nodes in Gray (Floorplan Editor)
Showing Moved Nodes in Gray

You can display nodes that have been moved since the last compilation and back-annotation of the project in gray, so that you can easily track the differences between the current assignments and the last compilation fit.

To show moved nodes in gray:

Turn on Show Moved Nodes in Gray (Options menu).

See also:

Viewing a Device in the Device View or LAB View


Showing Node Fan-In or Fan-Out (Floorplan Editor)
Showing Node Fan-In or Fan-Out

You can display fan-in and/or fan-out routing information for one or more selected logic cells, I/O cells, and/or pins in the LAB View display.

To show routing information:

1.	If you wish to view fan-in data, turn on Show Node Fan-In (Options menu).

2.	If you wish to view fan-out data, turn on Show Node Fan-Out (Options menu).

3.	Select one or more logic cells, I/O cells, and/or pins. The Floorplan Editor shows the fan-in paths as pink lines feeding into the left side of the selected items, and the fan-out paths as aqua-blue lines feeding out from the right side.

You can use the Show Node Fan-In and Show Node Fan-Out commands separately or together. However, if both commands are turned on, only the fan-out lines are displayed between items with mutual fan-in and fan-out.

The fan-in and/or fan-out lines are updated automatically when you move a logic cell, I/O cell, or pin.

The routing information displayed with these commands is available only for projects compiled with MAX+PLUS II version 5.2 or higher. You must recompile projects created with earlier versions of MAX+PLUS II to view their routing information in the Floorplan Editor.

See also:

Selecting a Node, Pin, or Other Object

Showing Paths

Showing Routing Statistics

Viewing Equations in the Floorplan Editor


Showing Paths (Floorplan Editor)
Showing Paths

You can display the path between selected logic cells, I/O cells, embedded cells, and/or pins that feed one another.

To show paths:

Turn on Show Path (Options menu).

The paths are updated automatically when you move a logic cell, I/O cell, embedded cell, or pin.

bmc hand.bmp}	The routing information displayed with this command is available only for projects compiled with MAX+PLUS II version 5.2 or higher. You must recompile projects created with earlier versions of MAX+PLUS II to view their routing information in the Floorplan Editor.

See also:

Selecting a Node, Pin, or Other Object

Showing Node Fan-In or Fan-Out

Showing Routing Statistics

Viewing Equations in the Floorplan Editor


Showing Routing Statistics (Floorplan Editor)
Showing Routing Statistics

You can display routing information for one or more selected pins, logic cells, I/O cells, and/or LABs, and/or calculate the most congested areas in the current chip.

To show routing information:

1.	Double-click Button 1 on any pin, logic cell, or assignment bin in the Device View or LAB View display.

or:

Select one or more pins, logic cells, I/O cells, or assignment bins and choose the Routing Statistics command (Options menu). The Routing Statistics dialog box is displayed with the pertinent information.

2.	To show information about the most congested areas of the chip, choose the Calculate Most Congested Areas button. The MAX+PLUS II Floorplan Editor calculates the most congested areas and displays the results in the expanded Routing Statistics dialog box.

1.	Depending on the size of the target chip and the number of resource assignments, it may take several seconds to calculate the most congested areas of the chip.

2.	The routing information displayed with Routing Statistics is available only for projects compiled with MAX+PLUS II version 5.2 or higher. You must recompile projects created with earlier versions of MAX+PLUS II to view their routing information in the Floorplan Editor.

See also:

Selecting a Node, Pin, or Other Object

Showing Node Fan-In or Fan-Out

Showing Paths

Viewing Equations in the Floorplan Editor


Viewing Equations in the Floorplan Editor (Floorplan Editor)
Viewing Equations in the Floorplan Editor

You can display Report File (.rpt) routing and equation information for pin, logic cell, and embedded cell assignments.

To view equations and routing information:

1.	(Optional) Select one or more assignments.

2.	Turn on Report File Equation Viewer (Layout menu). The Report File Equation Viewer is displayed at the bottom of the Floorplan Editor window. If you selected an assignment before choosing Report File Equation Viewer, data for the selected item(s) appears in the Equation Viewer.

3.	If you did not select an assignment before displaying the Equation Viewer, select one or more assignments in the Floorplan Editor window to view their equations, fan-in, and fan-out.

4.	If you wish, you can select a node in the Fan-In or Fan-Out box and choose the Go To button to display equations for that node.

or:

Double-click Button 1 on a node listed in the Fan-In or Fan-Out box.

See also:

Selecting a Node, Pin, or Other Object

Showing Node Fan-In or Fan-Out

Showing Paths

Showing Routing Statistics


Copying, Cutting & Pasting Node and Pin Assignments (Floorplan Editor)
Copying, Cutting & Pasting Node and Pin Assignments

You can copy, cut, and paste pin assignments to pins, rows, columns, or a device; and node assignments to logic cells, I/O cells, LABs, rows, columns, and/or chips. You can also copy and cut unassigned nodes or pins from the Unassigned Nodes & Pins box and paste (i.e., assign) them on pins, logic cells, LABs, rows, columns, and/or chips.

To avoid making illegal assignments, use Copy only in cases when you need to assign the same pin name or node name to multiple places, e.g., for signals that travel between devices in partitioned projects or for pins that are externally connected on MAX 7000 devices.

To copy and paste assignments or unassigned nodes:

1.	Select one or more assignments in the Device View  or LAB View display or select one or more unassigned nodes from the Unassigned Nodes & Pins box to copy. You can use area or object-by-object selection.

2.	Choose Copy (Edit menu) or use a shortcut. The selection is placed on the Clipboard.

3.	If you are partitioning your project into multiple chips, type a chip name or select a name from the Chip Name drop-down list box.

4.	Select one or more pins, logic cells, or I/O cells or select a row assignment bin, column assignment bin, LAB assignment bin, or device assignment bin to select the destination for the paste(d) items.

5.	Choose Paste (Edit menu) or use a shortcut.

To cut and paste assignments or unassigned nodes:

1.	Select one or more assignments in the Device View  or LAB View display or select one or more unassigned nodes from the Unassigned Nodes & Pins box to copy. You can use area or object-by-object selection.

2.	Choose Cut (Edit menu) or use a shortcut.

If you cut one or more assignment(s), the unassigned node(s) immediately appear in the Unassigned Nodes & Pins box until you paste the selection. If you cut one or more unassigned nodes, the unassigned nodes remain displayed in the Unassigned Nodes & Pins box until you paste the selection.

3.	Select one or more pins, logic cells, or I/O cells or select a row assignment bin, column assignment bin, LAB assignment bin, or device assignment bin to select the destination for the paste(d) items.

4.	Choose Paste (Edit menu) or use a shortcut.

See also:

Assigning a Pin, Location, or Chip

Deleting an Assignment

Selecting a Node, Pin, or Other Object

Guidelines for Working with Assignments


Finding Text (Floorplan Editor)
Finding Text

To find a specific string of text in the current chip:

1.	If necessary, change the view as described in Viewing a Device in the Device View or LAB View, and/or turn off the Full Screen command (Layout menu). The Floorplan Editor can find text only if it is displayed in the current view.

2.	Open the Find Text dialog box by choosing Find Text (Utilities menu) or using a shortcut.

3.	Type up to 256 characters of search text, including optional wildcard characters, in the Search For box.

4.	If you wish, turn on one or more of the following options:

Option:	Action:

Whole Word	Finds occurrences of the search text that are whole words only.

Pause at End	Pauses the search when the Floorplan Editor reaches the end of the floorplan.

5.	Turn on one or more Types of Text to Find options.

6.	Choose OK to begin the search.

7.	If you wish to find the next or previous occurrence of the search text after the first occurrence has been found, choose Find Text, Find Next, or Find Previous (Utilities menu).

8.	If you wish to search for text in another chip, select a different chip name in the Chip Name field and choose Find Text, Find Next, or Find Previous.

See also:

Selecting Text


Fitting the Floorplan into the Window (Floorplan Editor)
Fitting the Floorplan into the Window

To view the entire floorplan in the Floorplan Editor:

Choose Fit in Window (View menu).

Fit in Window changes the display scale to fit the entire device or LAB in the current window.

See also:

Turning Full Screen Viewing On or Off

Zooming In & Out


Turning Full Screen Viewing On or Off (Floorplan Editor)
Turning Full Screen Viewing On or Off

To turn full screen viewing on or off:

Choose Full Screen (Layout menu).

You can also type Esc to turn off the full screen mode.

Full Screen expands the Device View or LAB View display by hiding the top half of the Floorplan Editor window, which contains the following items:

Chip Name Field

Color Legend

Selected Node(s) & Pin(s) Field

Unassigned Nodes & Pins Box

Zoom In & Zoom Out Buttons

To switch between different floorplans for the current project, you can choose the Current Assignments Floorplan or Last Compilation Floorplan commands (Layout menu). To change the view of the current floorplan, choose the Device View or LAB View commands (Layout menu), or double-click Button 1 on a blank portion of the current display to switch to the other view.

See also:

Fitting the Floorplan into the Window

Zooming In & Out


Zooming In & Out (Floorplan Editor)
Zooming In & Out

To change the view of the current floorplan, select one of the following buttons or View menu commands:

Command/Button:	Action:

Fit in Window command	Zooms out to fit the entire device in the current window. Shortcut: Ctrl+W

Zoom In command	Increases the scale of the device displayed, showing a smaller portion of the device. When you reach the maximum reduction, the button is dimmed and is no longer available. Shortcut: Ctrl+Space

Zoom Out command	Reduces the scale of the device displayed, showing a greater portion of the device. When you reach the maximum enlargement, the button is dimmed and is no longer available. Shortcut: Ctrl+Shift+Space

Normal Size command	Zooms in or out to display the device at normal (full) size. Shortcut: Ctrl+1

Maximum Size command	Zooms in to display the device at maximum size. Shortcut: Ctrl+2

If objects are selected, the window zooms in and out on the objects. Otherwise, the reference point for zooming is the center of the device.

You can use the Full Screen command (Layout menu) to expand the Device View or LAB View display by hiding the top half of the Floorplan Editor window.

See also:

Fitting the Floorplan into the Window

Turning Full Screen Viewing On or Off


Guidelines for Timing Assignments

The information and guidelines on using timing assignments presented here will help you use timing assignments effectively.

These guidelines describe the types of logic functions that can accept timing assignments and how the Compiler interprets and resolves timing assignments. For information on specific assignments to enter and other techniques to improve speed performance in your MAX+PLUS II projects, go to Guidelines for Achieving Maximum Speed Performance.

Be sure to refer to Guidelines for Working with Assignments for absolutely essential information on using all types of resource, probe, and device assignments.

Logic Functions for Timing Assignments

You can assign timing to the following types of nodes and pins (or ports):

Input pins: INPUT, INPUTC, and IN

Output pins: OUTPUT, OUTPUTC, and OUT

Bidirectional pins: BIDIR, BIDIRC, and INOUT:

Input	A timing specification on a bidirectional (BIDIR, BIDIRC, or INOUT) pin/port applies to the input function of the pin.

Output	A timing specification on the TRI buffer that feeds the bidirectional pin/port applies to the output function of the pin.

Any register, including:

DFF	SRFF

DFFE	SRFFE

JKFF	TFF

JKFFE	TFFE

Latches are treated as combinatorial logic, not as registers. For the purpose of timing assignments, combinatorial logic includes logic primitives, latches, and asynchronous register paths (e.g., register PRN or CLRN inputs to Q outputs).

The following table shows the types of pins and ports that are appropriate locations for each different type of timing assignment, and the signal paths that they affect. Assignments to other types of logic functions not listed here are ignored:

Assignment	Legal	Affected	Affected

Type:	Location:	Signal Source:	Signal Destination:

Note (1)	Note (1)	Note (1))

tpd	INPUT and OUTPUT	INPUT pins that feed	OUTPUT pins that are

pins	combinatorial outputs	fed combinatorially

tco	OUTPUT pin fed 	INPUT pin that feeds 	OUTPUT pin fed

combinatorially by 	a register’s CLK input 	combinatorially by

the Q output of a 	through combinatorial 	the Q output of a

register or INPUT pin 	logic	register

that feed a register’s

CLK input through

combinatorial logic

tsu	INPUT pin that feeds	INPUT pin that feeds	Data or ENA input of a

a register’s data or ENA 	a register’s data or ENA 	register fed combinatorially

input through 	input through 	by the INPUT pin

combinatorial logic	combinatorial logic	Note (2)

fmax	INPUT pin that feeds	Q output of a register	Data input to the same

a register’s CLK 	Note (3)	register or to another

input or the  Q output	register

of a register	Note (2)

How the Compiler Interprets & Resolves Timing Assignments

The Compiler interprets timing assignments as follows:

Project default timing specified with Global Project Timing Requirements (Assign menu) is overridden by timing assignments on individual logic functions specified with Timing Requirements (Assign menu).

A timing assignment on an input pin applies to all logic fed by that pin.

A timing assignment on an output pin applies to all logic that feeds that pin.

A timing assignment on a register applies to all paths driven from the Q output of the register.

A timing cut on an individual logic function cuts all timing paths that pass through that logic function so that the Compiler will ignore the delays along the paths when it processes the project. The signal paths themselves are not cut; they are simply excluding from the timing constraints.

If tpd timing assignments exist on both an output pin and on an input pin that feeds it, the assignment on the output pin overrides the assignment on the input pin.

A tco timing assignment on an output pin can refer to a chain of multiple registers only if the Q output of one register feeds the Clock input of another register. If the Q output of a register affects only the data inputs of other registers, the tco assignment applies only to the final register that feeds to output pins. In addition, if tco timing assignments exist on both an output pin and on an input pin that feeds it, the assignment on the output pin overrides the assignment on the input pin.

The tsu timing assignment on an input pin affects only those registers in which the data input is a function of that input pin.

The fmax assignment on a register does not specify the timing from the register to an output pin. It controls only the delay from its Q output to the data input of itself or of other registers. An fmax assignment on a register cannot override explicit fmax assignments on other registers. An fmax assignment on a register also cannot override the tsu assignment on an input pin that feeds the register’s Clock Enable input.

If you enter an fmax assignment on a register that generates a ripple Clock, the fmax is propagated through each successive downstream register at one-half the frequency of the previous register (e.g., as in a frequency divider).

See also:

Assigning Individual Timing Requirements

Specifying Global Project Timing Requirements


Note 1 for timing assignment guidelines
Note (1)

Input portions of BIDIR, BIDIRC, and INOUT pins/ports are considered to be INPUT pins. TRI buffers that feed BIDIR, BIDIRC, or INOUT pins/ports are considered to be OUTPUT pins.


Note 2 for timing assignment guidelines
Note (2)

Includes the internal tsu (setup time) for the register, i.e., the time required for a signal to be stable at the register input before the Clock’s rising edge.


Note 3 for timing assignment guidelines
Note (3)

Includes the internal trd (register delay) for the register, i.e., the delay from the rising edge of the register’s Clock to the time the data appears at the register output.


Guidelines for Working with Assignments

Observe the following guidelines when making device, probe, and resource assignments in MAX+PLUS II:

General Guidelines

You can enter assignments for the current project by choosing Assign menu commands, moving node and pin names in the Floorplan Editor, or by manually editing the ACF with the same filename as the top-level design file of the project in a Text Editor window. All of these assignment methods edit the ACF. However, only one application can edit the ACF at any one time. If you are manually editing the ACF in a Text Editor window, you must save your edits every time you choose an Assign menu command or switch to the Floorplan Editor. Since manually editing the ACF is most apt to generate errors, Altera recommends entering assignments with Assign menu commands and the Floorplan Editor.

You should compile a project for the first time without any assignments. Before you compile a project for the first time, you must manually enter the names of nodes and pins for which you wish to enter assignments. After you compile the project, a full database of all node and pin names in the project is available via the Search Node Database dialog box.

You can also use Project Save & Check (File menu) to create a Node Database File. All node and pin names in this file can be viewed and selected in the Search Node Database dialog box. However, only pin names in the Node Database File appear and are assignable in the Floorplan Editor window. To assign buried nodes in the Floorplan Editor, you must fully compile the project.

To enter assignments in a hierarchical project with menu commands, open the top-level design file in the hierarchy tree by choosing Open (File menu) or by double-clicking Button 1 on the icon that represents the file in the Hierarchy Display window. To then enter assignments in a lower-level file in the hierarchy, use the Hierarchy Display window or Hierarchy Down (File menu) to open the lower-level files in the hierarchy. If you open a lower-level file with the Open or Retrieve command (File menu), it is considered to be the top of a different hierarchy tree, and assignments that you enter are saved only for that hierarchy, not for the project.

In order to enter pin and location assignments with the Pin/Location/Chip command (Assign menu), you must assign specific devices for the project with Device (Assign menu). The Pin/Location/Chip command does not allow you to enter pin and location assignments on chips that are assigned to  AUTO devices, and the Compiler ignores assignments that are manually entered in an ACF  for chips that are assigned to AUTO devices.

The default name for a chip is the project name; the chip name is optional for a project that fits into a single device. However, if you have a multi-device project, you should not use the project name for any of the chips. Otherwise, the Compiler cannot generate a timing SNF for the entire project.

To assign all logic functions in a macrofunction to the same clique or chip, make the assignment to the macrofunction itself. You can make an assignment on an entire macrofunction and make a different assignment on a logic function within the macrofunction. The assignment on the lower-level function overrides the assignment on the macrofunction, while the macrofunction assignment remains valid for all other unassigned lower-level logic functions within the macrofunction.

Graphic Editor-Specific Guidelines

To edit probe and resource assignments in the Graphic Editor, you can double-click Button 1 on an assignment as a shortcut for opening the appropriate command dialog box. Double-clicking Button 1 on a primitive also opens the Pin/Location/Chip dialog box. You can also edit assignments in the Graphic Editor window by selecting the assignment text with Button 2 and typing a new assignment.

To enter resource assignments on symbols in a Graphic Editor primitive array, you must manually edit the ACF to implement the assignments. After you have compiled the project, you can back-annotate the Fit File into the ACF and enter assignments in that file.

Refer to Guidelines for Working with OrCAD Schematic Files for important information on working with assignments in OrCAD Schematic Files: you can only enter pin and chip assignments in these files, and the assignments must be made only to pin primitives. You must manually edit the ACF to enter all other types of assignments.

General Logic Synthesis/Timing/Fitting Guidelines

The Logic Synthesizer provides two basic types of logic synthesis: multi-level logic synthesis and standard synthesis. Multi-level synthesis allows you to assign resource assignments on any logic function. With standard synthesis, you can make resource assignments only on hard logic functions unless the SOFT Buffer Insertion logic option is turned on. Any assignments on a macrofunction affect only the hard logic functions within the macrofunction if SOFT Buffer Insertion is turned off.

With standard logic synthesis, if a macrofunction contains no hard logic functions, the Compiler ignores clique and chip assignments unless the SOFT Buffer Insertion logic option is turned on. Example

Altera recommends assigning a logic synthesis style rather than individual logic options whenever possible. When both types of assignments are used, the Compiler combines them according to Logic Synthesis Style & Logic Option Rules. Each project has a default logic synthesis style that is specified with the Global Project Logic Synthesis  command (Assign menu).

Refer to Guidelines for First-Time Project Fitting for information on how to achieve a successful fit during first-time fitting. If your project does not fit during the first compilation, refer to Fitting & Refitting a Project. The "Fitting & Refitting a Project" topic provides access to a wealth of fitting guidelines, and includes directions for using logic synthesis effectively to achieve a fit. This topic helps you navigate effectively through the Help information that is provided in the following topics:

FLEX 8000 Device "No Fit" Refitting Suggestions

Classic, MAX 5000, MAX 7000 & MAX 9000 Device "No Fit" Refitting Suggestions

Reducing Logic Cell Usage in FLEX 8000 Devices

Reducing Logic Cell Usage in Classic, MAX 5000, MAX 7000 & MAX 9000 Devices

Guidelines for Achieving Maximum Speed Performance

Refer to Guidelines for Timing Assignments for information on how to use timing assignments effectively.

If you wish to edit assignments made by the Compiler, back-annotate them with the Back-Annotate Project command (Assign menu). You can then edit the assignments by choosing Assign menu commands, moving node and pin names in the Floorplan Editor, or by manually editing the ACF. However, Altera strongly recommends that you allow the Compiler to choose pin, logic cell, and I/O cell assignments until the project is near completion.

Third-Party Interfaces Guidelines

If you import a project that includes OrCAD Schematic Files into MAX+PLUS II, Altera strongly recommends that you open the files in the Graphic Editor, save the files as GDFs with Save As (File menu), and then specify the top-level GDF as the project name instead of the OrCAD Schematic File. If you save an OrCAD Schematic File as a GDF, you can enter all types of resource and device assignments for the file. Otherwise, you must enter resource and device assignments manually in an ACF with the same name as the top-level OrCAD Schematic File.

If you import a project that includes XNF Files into MAX+PLUS II, you must enter resource and device assignments with MAX+PLUS II.

If you have another industry-standard design editor that generates EDIF netlist files, you can make resource assignments in that editor’s design file before you generate an EDIF Input File from it. Resource assignments are placed into an EDIF file as Property constructs by the netlist writer that generates the file. MAX+PLUS II then automatically converts the assignments into the ACF format. However, after you import the file into MAX+PLUS II, you should enter all assignments only with MAX+PLUS II. If you plan to reopen your design files to enter edits during the design cycle, you should enter all assignments only in your third-party editor.

8.	If your third-party design entry software saves assignments in a <project name>.ini, Probe & Resource Assignment File, and/or TDF, you should add the following line to your maxplus2.ini file:

THIRD_PARTY_ASSIGNMENTS=ON

This variable allows MAX+PLUS II to automatically convert assignments from your files into the ACF format each time you open a project in MAX+PLUS II. Assignments in your <project name>.ini file, .prb file, and TDF are converted and added to the existing ACF for your project. This variable allows you to continue to edit assignments with your third-party tool through all design iterations, and ensures that your updated assignments are incorporated into the MAX+PLUS II-compatible ACF format.

See also:

Assigning a Clique

Assigning a Device

Assigning a Pin, Location, or Chip

Assigning a Probe

Assigning an Individual Logic Option or Synthesis Style

Assigning Connected Pins

Assigning Individual Timing Requirements

Assigning Resources in a Third-Party Design Editor

Bank-Annotating Assignments for a Project

Clearing Assignments for a Project

Fitting & Refitting a Project (Compiler)

Guiding the Partitioner

Navigating the Hierarchy

Partitioning a Project

Resource Assignments in EDIF Input Files

Specifying Global Project Logic Synthesis Settings


Example: How non-hard logic functions are munched
If a 74151 macrofunction assigned to CHIP_B fed a DFF primitive assigned to CHIP_A, the chip assignment would be meaningless because the 74151 contains no hard logic primitives. Since the macrofunction would be implemented in the same logic cell as the primitives, there would be 11 signals feeding CHIP_A rather than one signal as might be expected. However, you can feed the output of a macrofunction to an LCELL buffer and make an assignment on the LCELL to ensure that the clique or chip assignment is preserved.


--------------------BEGINNING OF NON-TRANSLATED TEXT-----------------------------------------------

This file contains messages for the Floorplan Editor and for the Assign menu-type commands. It has messages from the following modules:

acfw

asgw

aedw

nam

bak

It also contains messages from the hrw module related to the ACF.

Messages from other applications/files that are documented here:

STAN_ILLEGAL_PATH_COUNT	TANMSGS.MSG

EDBB_ILLEGAL_JTAG_USER_CODE	DBBMSGS.MSG

--------------------END OF NON-TRANSLATED TEXT-----------------------------------------------


ACF contains syntax errors....
ACF contains syntax errors. You must either correct the ACF or overwrite it with system defaults before completing this action. To save the existing ACF and obtain a list of errors, choose Cancel, then open and save the file in the Text Editor. To overwrite the existing ACF with system defaults, choose OK.

CAUSE:	You tried to compile the current project or make assignments using a command on the Assign menu. MAX+PLUS II cannot complete the action, however, because the specified ACF contains syntax errors.

ACTION:	If you wish to correct the existing ACF, choose Cancel. You can then open the ACF in the Text Editor, choose Save (File menu) to recheck the syntax, and then use the Message Processor to locate the source(s) of error and warning messages. Otherwise, to overwrite the existing ACF with system defaults--and lose any resource or device assignments in the file--, choose OK in the message box.

See also:

Locating the Source of a Message

MAX+PLUS II Messages

Message Format


ACF syntax error on or before <text>

CAUSE:	MAX+PLUS II has detected a syntax error in the project’s Assignment & Configuration File, either in the <text> specified at the end of the message or somewhere before or after the <text> (e.g., a missing semicolon after end).

ACTION:	Use the Message Processor’s Locate button to locate the error(s) in the ACF. After you correct the error(s), save the ACF to verify that the file is error-free.

See also:

ACF Format

Locating the Source of a Message

MAX+PLUS II Messages

Message Format


Can’t assign a probe to a bus or primitive array

CAUSE:	You selected a bus (or group) name or primitive array and chose Probe (Assign menu) to assign a probe name. However, you cannot make a probe assignment to a bus/group name.

ACTION:	No action is required. If you wish to assign a probe to a single item, you must deselect the bus or primitive array and choose Probe again, then enter the individual node name for which you wish to create a probe.

See also:

Assigning a Probe

MAX+PLUS II Messages

Message Format


Can’t convert old-style assignments in <filename> to new format

CAUSE:	MAX+PLUS II could not convert the old-style assignment and/or configuration information into the new format when you opened a project created with a pre-version 5.0 release of MAX+PLUS II. This message is usually caused by a syntax error in the specified file. This message may also be displayed after you have received an I/O or memory error.

ACTION:	If the specified file is a .prb file or <project name>.ini file, you must re-enter the assignment and configuration information from within MAX+PLUS II (e.g., with menu commands). If the specified file is a TDF, open the file and choose the Save & Check (File menu) to check the file for syntax errors. After you have corrected the errors, choose Convert Obsolete Assignment Format (Assign menu) to restart the conversion process.

See also:

Compiling a Project

Converting an Obsolete Assignment Format

MAX+PLUS II Messages

Message Format


Can’t implement illegal resource number/name entered in the Pin, Logic Cell, LAB, Row, or Column drop-down list box

CAUSE:	In the Pin/Location/Chip dialog box, you typed a pin number, logic cell number, I/O cell (IOC) number, LAB name, row name, or column number that does not exist on the device that corresponds to the chip name shown in the Chip Name box. You can only enter an assignment to a pin or another resource if it exists on the device assigned to the chip. This message may occur if you enter an assignment for a new chip that has not been assigned to a specific device (new chips default to AUTO devices).

ACTION:	If the current chip is not assigned to a specific device, choose the Assign Device button to open the Device dialog box and assign a specific device. If you already have a device assignment, type or select a legal resource number or name in the Pin, Logic Cell, LAB, Row, or Column drop-down list box. These list boxes automatically show all legal resource numbers/names if you have assigned the current chip to a specific device. Refer to Devices & Adapters for more information on pin and logic cell locations for a particular device package.

See also:

Assigning a Device

Assigning a Pin, Location, or Chip

MAX+PLUS II Messages

Message Format


 Can’t open the <name> dialog box until <text>

CAUSE:	You attempted to open the specified dialog box, but you have not entered adequate information to identify the item to which the assignment should be applied.

ACTION:	Enter the information requested in the message and try again.

See also:

Assigning a Device

Assigning an Individual Logic Option or Synthesis Style

MAX+PLUS II Messages

Message Format


Can’t perform this action -- the database of project node names is being updated by the Compiler and is locked

CAUSE:	You tried to perform an action for which MAX+PLUS II requires access to the database of project node and pin names. This database is typically reserved for Compiler use during the early phases of project compilation. This message may occur if you attempt to add or change an assignment or if you try to open the Search Node Database dialog box while the database is being updated.

ACTION:	Try again later or halt the compilation.

See also:

MAX+PLUS II Messages

Message Format


Can’t read line <number> of Report File Equations Section -- recompile the project to create a new Report File

CAUSE:	You tried to view equations and routing information using the Report File Equation Viewer, but the Floorplan Editor was not able to read part of the Equations Section of the Report File (.rpt). The Report File may have been inadvertently edited by a user or corrupted by the system.

ACTION:	Recompile the project to generate a new Report File, and then view the equations and routing information in the Floorplan Editor. If the problem persists, contact Altera Applications.

See also:

Compiling a Project

MAX+PLUS II Messages

Message Format


 Can’t search -- project has not been compiled, so no database of node names is available

CAUSE:	You chose the List button in the Search Node Database dialog box. However, since the project has not yet been compiled, no datable of node and pin names, which is stored in the Compiler-generated Node Database File, exists. Therefore, no names can appear in the dialog box. The node names database is created only after the project has been compiled.

ACTION:	Compile the project and try again.

See also:

MAX+PLUS II Messages

Message Format

Searching the Node Database


Can’t view equations while Report File is being written

CAUSE:	You tried to view equations and routing information using the Floorplan Editor’s Report File Equation Viewer before the Compiler finished generating the Report File (.rpt).

ACTION:	Wait until the Compiler generates a Report File before you attempt to view equations and routing information.

See also:

MAX+PLUS II Messages

Message Format

Viewing Equations in the Floorplan Editor


Can’t view floorplan for last compilation -- no Fit FIle is available for this device

CAUSE:	You opened the Floorplan Editor and chose Last Compilation Floorplan (Layout menu) to display the floorplan for the most recent compilation. However, since the currently assigned device is an advance information device, no Fit File (.fit) exists for it; therefore, the Floorplan Editor cannot display any fitting information from the last compilation.

ACTION:	Select a device that is not an advance information device, recompile the project to create a Fit File, and then view the floorplan for the last compilation.

See also:

Compiling a Project

MAX+PLUS II Messages

Message Format

Showing the Floorplan for Current Assignments


 Chip <name> already exists in the ACF

CAUSE:	The chip name you typed in the Rename Chip dialog box already exists in the Assignment & Configuration File (.acf).

ACTION:	Type a new chip name, or choose Cancel to retain the original name.

See also:

Assigning a Pin, Location, or Chip

MAX+PLUS II Messages

Message Format

Renaming a Chip


 Chip <name> has pin/location/chip assignments. OK to delete chip and all of its assignments?

CAUSE:	You chose the Delete button in the Device dialog box when the specified chip was selected in the Existing Device Assignments box. Since this chip contains pin/location/chip assignments, MAX+PLUS II is warning you that these assignments will be deleted, along with the chip, from the Assignment & Configuration File (.acf).

ACTION:	To delete the chip and its assignments, choose OK. To retain the chip and its assignments, choose Cancel. If you wish to rename the chip, choose the Edit Chips button in the Device dialog box, choose the Rename Chip button, and then type a new name in the New Chip Name field and choose OK.

See also:

Assigning a Pin, Location, or Chip

Deleting an Assignment

MAX+PLUS II Messages

Message Format

Renaming a Chip


Existing pin assignments may not be valid for the new device

CAUSE:	You changed a device assignment in the Device dialog box to a device that has a different pin-out from the previous device. Since your project contains pin assignments for the old device, MAX+PLUS II is warning you that these assignments may not be appropriate for the new device and pin-out, and may cause errors when the project is compiled.

ACTION:	Check the assignments for the chip that corresponds to this device in the Pin/Location/Chip dialog box to ensure that they are appropriate. Refer to Devices & Adapters for more information on pin and logic cell locations for a particular device package.

See also:

Assigning a Pin, Location, or Chip

MAX+PLUS II Messages

Message Format


File with old-style assignments contains a syntax error

CAUSE:	MAX+PLUS II could not convert the old-style assignment and/or configuration information into the new format when you opened a project created with a pre-version 5.0 release of MAX+PLUS II. This message usually occurs because of a syntax error in the specified file.

ACTION:	If the specified file is a TDF, open the file and choose the Save & Check (File menu) to check the file for syntax errors. After you have corrected the errors, choose Convert Obsolete Assignment Format (Assign menu) to restart the conversion process.

See also:

Compiling a Project

Converting an Obsolete Assignment Format


Ignored ACF for this project because it contains syntax errors.
Ignored ACF for this project because it contains syntax errors. To obtain a list of errors, open and save this ACF in the Text Editor. You should correct errors in the ACF before continuing work on the project.

CAUSE:	MAX+PLUS II ignored the specified ACF because it contains syntax errors. MAX+PLUS II is currently using system defaults for all settings, and has ignored all resource and device assignments in the ACF.

ACTION:	To correct the existing ACF, open the file in the Text Editor, choose Save to recheck the syntax, and then use the Message Processor to locate the source(s) of error and warning messages.

See also:

Locating the Source of a Message

MAX+PLUS II Messages

Message Format


Ignored conflicting assignment [for node <name>] to variable <variable> with value <value> -- using last value found in file

CAUSE:	MAX+PLUS II has detected a set of conflicting assignments in the Assignment & Configuration File for the project. MAX+PLUS II will use the final value for this assignment in the ACF.

ACTION:	Use the Message Processor’s Locate button to locate the conflicting assignment. After you remove the conflicting assignment, save the ACF to verify that the file is error-free.

See also:

ACF Format

Locating the Source of a Message

MAX+PLUS II Messages

Message Format


Ignored duplicate assignment [for node <name>] to variable <variable> with value <value>

CAUSE:	MAX+PLUS II has detected a duplicate assignment in the Assignment & Configuration File for the project.

ACTION:	Use the Message Processor’s Locate button to locate the duplicate assignment. After you remove the duplicate, save the ACF to verify that the file is error-free.

See also:

ACF Format

Locating the Source of a Message

MAX+PLUS II Messages

Message Format


Illegal section name <section name>

CAUSE:	MAX+PLUS II has detected an illegal section name in the Assignment & Configuration File for the project.

ACTION:	Use the Message Processor’s Locate button to locate the error(s) in the ACF. After you correct the error(s), save the ACF to verify that the file is error-free.

See also:

ACF Format

Locating the Source of a Message

MAX+PLUS II Messages

Message Format


Illegal text <text> after section keyword <keyword>

CAUSE:	MAX+PLUS II has detected illegal text after the specified section keyword in the Assignment & Configuration File for the project. For example, this error can occur if the DEFAULT_DEVICES keyword, which does not permit identifiers, is followed by a chip or node name.

ACTION:	Use the Message Processor’s Locate button to locate the error(s) in the ACF. After you correct the error(s), save the ACF to verify that the file is error-free.

See also:

ACF Format

Locating the Source of a Message

MAX+PLUS II Messages

Message Format


Illegal value <value> for <variable> variable

CAUSE:	MAX+PLUS II has detected an illegal value for the specified variable in the Assignment & Configuration File for the project.

ACTION:	Use the Message Processor’s Locate button to locate the error(s) in the ACF. After you correct the error(s), save the ACF to verify that the file is error-free.

See also:

ACF Format

Locating the Source of a Message

MAX+PLUS II Messages

Message Format


Illegal variable <name> for <section name> Section

CAUSE:	MAX+PLUS II has detected an illegal variable in the specified section of the Assignment & Configuration File for the project.

ACTION:	Use the Message Processor’s Locate button to locate the error(s) in the ACF. After you correct the error(s), save the ACF to verify that the file is error-free.

See also:

ACF Format

Locating the Source of a Message

MAX+PLUS II Messages

Message Format


Incomplete assignment information -- you must specify a <text>

CAUSE:	You chose the Add or Change button, but you had not entered the specified information which is required to complete the assignment.

ACTION:	Enter the information requested in the message and try again.

See also:

MAX+PLUS II Messages

Message Format


Invalid JTAG user code -- value must be 1-byte hex number between 0 and 7F

CAUSE:	You entered an illegal value in the JTAG User Code box in the FLEX 10K Individual Device Options or FLEX 10K Global Project Device Options dialog box.

ACTION:	Enter a legal JTAG user code value, i.e., a 1-byte hexadecimal number between 0 and 7F.

See also:

MAX+PLUS II Messages

Message Format

Specifying Global Project FLEX 10K Device & Pin Options

Specifying Individual FLEX 10K Device & Pin Options


 All old-style assignments have been successfully converted to new format

CAUSE:	MAX+PLUS II successfully converted the old-style assignment and/or configuration information into the new format when you opened a project created with a pre-version 5.0 release of MAX+PLUS II or when you chose the Convert Obsolete Assignment Format (Assign menu) command. MAX+PLUS II has processed the project’s top-level TDF (if any), .prb file, and <project name>.ini file. As part of this process, MAX+PLUS II comments out obsolete assignment syntax in the TDF, deletes the .prb and <project name>.ini files, and copies the information in the files into the ACF.

ACTION:	No action is required. You are ready to start work on your project!

See also:

Converting an Obsolete Assignment Format

MAX+PLUS II Messages

Message Format


Missing identifier after section keyword <keyword>

CAUSE:	MAX+PLUS II has detected a missing identifier after the specified section keyword in the Assignment & Configuration File for the project. For example, this error can occur if the CHIP keyword, which requires an identifier, is not followed by a chip name.

ACTION:	Use the Message Processor’s Locate button to locate the error(s) in the ACF. After you correct the error(s), save the ACF to verify that the file is error-free.

See also:

ACF Format

Locating the Source of a Message

MAX+PLUS II Messages

Message Format


Missing node name for variable <variable>

CAUSE:	MAX+PLUS II has detected a missing node name for the specified variable in the Assignment & Configuration File for the project. For example, this error can occur if a variable in the Logic Options Section, which assigns logic options to specific nodes, is not preceded by a node name.

ACTION:	Use the Message Processor’s Locate button to locate the error(s) in the ACF. After you correct the error(s), save the ACF to verify that the file is error-free.

See also:

ACF Format

Locating the Source of a Message

MAX+PLUS II Messages

Message Format


 Move or paste canceled -- it would create illegal assignment(s)

CAUSE:	You tried to move or paste one or more selected node(s) and/or pins to an illegal, ambiguous, or unsupported destination. For example, this message can occur if you attempt to drag multiple nodes from an LAB onto a single pin.

ACTION:	Select or copy a different item and try again.

See also:

Assigning a Pin, Location, or Chip

MAX+PLUS II Messages

Message Format


No new information has been entered

CAUSE:	You chose the Add or Change button, but you had not entered any new assignment information in the dialog box.

ACTION:	Enter new assignment information and try again.

See also:

MAX+PLUS II Messages

Message Format


Node name should not be specified for variable <variable>

CAUSE:	A node name has been incorrectly designated for the specified variable in the Assignment & Configuration File for the project. For example, this error can occur if a variable in the Global Project Synthesis/Assignment Options Section, which assigns global logic options, is preceded by a node name.

ACTION:	Use the Message Processor’s Locate button to locate the error(s) in the ACF. After you correct the error(s), save the ACF to verify that the file is error-free.

See also:

ACF Format

Locating the Source of a Message

MAX+PLUS II Messages

Message Format


Number must be an integer [<text>]

CAUSE:	You entered a number that is not an integer or is outside the permitted range of integers specified in the message.

ACTION:	Enter a different integer (within the specified range, if necessary) and try again.

See also:

MAX+PLUS II Messages

Message Format


OK to convert old-style assignments in <filename> into new format and change old assignments into comments?...
OK to convert old-style assignments in <filename> into new format and change old assignments into comments? Choose No to prevent conversion (but assignments will be ignored during compilation).

CAUSE:	You chose the Convert Obsolete Assignment Format command (Assign menu) to reconvert old-style assignment and configuration information in the project’s top-level TDF (if any), .prb file, and <project name>.ini file into the Assignment & Configuration File (.acf) format. During this process, MAX+PLUS II comments out obsolete assignment syntax in the TDF, deletes the .prb and <project name>.ini files, and copies the information in the files into the ACF.

ACTION:	If you wish to convert your assignment and configuration information into the ACF format, choose Yes. To discard all old assignment and configuration information, choose No.

MAX+PLUS II always preserves copies of the original unconverted files with the extension .tdk, .prk, and .ink, respectively.

See also:

Converting an Obsolete Assignment Format

MAX+PLUS II Messages

Message Format


Previous device and new device have similar pin-outs. OK to convert pin assignments from the previous to the new device?

CAUSE:	You changed the device assignment for a chip with the Device dialog box. Since the pin-outs of the old and new devices are similar, MAX+PLUS II is offering to convert (i.e., transfer) the pin assignments from the old device to the new device.

ACTION:	Choose Yes to convert the pin assignments to the new device. Choose No to discard all pin assignments.

See also:

Assigning a Pin, Location, or Chip

Devices & Adapters

MAX+PLUS II Messages

Message Format


Variable <name> in ACF is obsolete -- delete variable and respecify setting with the Compiler’s Fitter Settings command

CAUSE:	MAX+PLUS II has detected an obsolete variable in the project’s Assignment & Configuration File (.acf). This variable may have been made available to you as part of a consultation with Altera Applications or in the read.me file.

ACTION:	Delete the obsolete variable and respecify the setting with the Fitter Settings command (Processing menu).

See also:

MAX+PLUS II Messages

Message Format


You have assigned chips to devices from multiple families. OK to convert all devices not from the current family to AUTO?

CAUSE:	After you assigned devices to multiple different device families, you attempted to close the Device dialog. Since MAX+PLUS II can compile a project only for a single device family, you must change one or more of the device assignments so that all assignments are to devices from the current device family (shown in the Device Family drop-down list box).

ACTION:	Choose OK to automatically convert all device assignments to AUTO devices from the current device family. Choose Cancel to return to the Device dialog box, where you can manually change the assignments.

See also:

Assigning a Device

MAX+PLUS II Messages

Message Format

Partitioning a Project

Specifying Devices for Automatic Device Selection


Your project’s ACF contains syntax errors -- Altera recommends correcting these syntax errors before continuing work on the proj
Your project’s ACF contains syntax errors -- Altera recommends correcting these syntax errors before continuing work on the project

CAUSE:	MAX+PLUS II has detected one or more syntax errors in the Assignment & Configuration File for the project.

ACTION:	Use the Message Processor’s Locate button to locate the error(s) in the ACF. After you correct the error(s), save the ACF to verify that the file is error-free.

See also:

ACF Format

Locating the Source of a Message

MAX+PLUS II Messages

Message Format


Your version of MAX+PLUS II does not include <device/family name> compilation support -- projects created with this device will
Your version of MAX+PLUS II does not include <device/family name> compilation support -- projects created with this device will not compile

CAUSE:	Your version of MAX+PLUS II does not contain compilation support for the device(s) you have currently selected in the Device (Assign menu) dialog box. Although you can assign the device to your project, you will not be able to compile the project for this device until you have purchased compilation support for it.

ACTION:	Select another device for your project, or if you wish to purchase additional compilation support, contact Altera Marketing.

See also:

Assigning a Device

MAX+PLUS II Messages

Message Format


Assignment & Configuration Output File (.aco) Description
Assignment & Configuration Output File (.aco)

An ASCII file (with the extension .aco), generated by the MAX+PLUS II Compiler, that contains the probe, resource, and device assignment information, as well as other configuration information, that corresponds to a Text Design Output File (.tdo) with the same filename.

During compilation, the Compiler generates a TDO File and an ACO File for each device in the current project if you turn on Generate AHDL TDO File. The ACO File, which is based on the original Assignment & Configuration File for the project, provides the assignment and configuration information for the corresponding TDO File. All information in the ACO File is given in ACF Format. The filenames of the TDO File(s) and ACO File(s) are the same as the user-defined chip names for the project; if no chip names exist, the Compiler assigns filenames that are based on the project name. Example

Since one TDO File and one ACO file are generated for each device in a multi-device project, you can split your original project into multiple single-device projects if you wish to lock down the logic in some of the devices. You can then save a single TDO File as a TDF and save the corresponding ACO File as an ACF, edit the file(s), specify the new TDF as the project with Project Name, and recompile the logic for only one device.

The ACO File and TDO File contain new node names that represent the hierarchy of the flattened, optimized project. If the new node names exceed 32 name characters, you must shorten the node names.

If the ACO File was generated for a single-device project, the icon for the file appears in the Hierarchy Display window.

See also:

Hierarchical Node & Symbol Names

Saving a File


Assignment & Configuration File (.acf) Description
Assignment & Configuration File (.acf)

An ASCII file (with the extension .acf) that stores information about probe, resource, and device assignments for a hierarchy tree, as well as configuration information for the Compiler, Simulator, Timing Analyzer, and Programmer. All information that can affect output files containing design information for the current hierarchy tree is controlled by the ACF.

The ACF for the current project is automatically and continuously updated as you enter probe, resource, and device assignments with Assign menu commands or the Floorplan Editor, or change settings for menu commands and on-screen options in the Compiler, Simulator, Timing Analyzer, and Programmer. You can also edit the ACF manually in a Text Editor window. Information in the file is stored in ACF Format.

Only one application can edit the ACF at any one time. If you are manually editing the ACF in a Text Editor window, you must save your edits every time you choose an Assign menu command or switch to the Floorplan Editor. Since manually editing the ACF is most apt to generate errors, Altera recommends entering assignments with Assign menu commands and the Floorplan Editor.

The Compiler uses the resource and device assignments in the ACF to synthesize, partition, and fit the project during compilation. The Compiler incorporates the probe assignments in the file into the Simulator Netlist File (.snf) for the project when you create an SNF for simulation or timing analysis. The Simulator, Timing Analyzer, and Programmer refer to the ACF for information on menu command and on-screen option settings.

The ACF also contains Fitter-generated resource and device assignments after you have back-annotated and saved a project, and is modified when you copy, delete, clear, or ignore assignments. Assignments that are back-annotated are taken from the Fit File for the project.

In pre-version 5.0 releases of MAX+PLUS II, assignment and configuration information was stored in Probe & Resource Assignment (.prb) Files, the <project name>.ini file, and optionally in AHDL TDFs. Assignments in these formats are no longer supported. MAX+PLUS II version 5.0 and higher automatically converts assignment and configuration information in these files to the ACF format when you open a project from an earlier version of MAX+PLUS II.

An Assignment & Configuration Output File (.aco) can be renamed with the extension .acf and used as an ACF in conjunction with a Text Design Output File (.tdo) that has been renamed as a Text Design File (.tdf).

See also:

ACF Format

Clique Assignments

Connected Pin Assignments

Device Assignments

Logic Option Assignments

Pin, Location & Chip Assignments

Probe Assignments

Summary Table of ACF Keywords, Settings & Usage

Timing Assignments


ACF Format

The Assignment & Configuration File (.acf) provides an ASCII format for entering probe, resource, and device assignments for a hierarchy tree, as well as configuration information for the Compiler, Simulator, Timing Analyzer, and Programmer.

An ACF can contain some or all of the sections listed below. Sections are listed in the order in which they are normally used. Many sections can be repeated.

Physical Chip Assignments Section

Auto Device Choices Section

Global Device Options Section

Global Project Synthesis/Assignment Options Section

Global Project Parameters Section

Logic Options Section

Timing Requirement Assignments Section

Clique Assignments Section

Connected Pin Assignments Section

Probe Assignments Section

Ignored Assignments Section

Compiler Processing Configuration Section

Compiler Interfaces Configuration Section

Custom Design Doctor Rules Section

Logic Synthesis Style Definition

Simulator Configuration Section

Timing Analyzer Configuration Section

Other Configuration Section

Internal Information Section

See also:

Comments & Documentation

Summary Table of ACF Keywords, Settings & Usage


Physical Chip Assignments Section (Assignment & Configuration File)

The Physical Chip Assignments Section specifies the logic that is assigned to an individual device. It declares a chip name, the specific or AUTO device to which the chip is assigned, device options for that device, and the logic functions that are assigned to the device. You can assign node, bus, and pin names to specific device pins, logic cells, I/O cells, and embedded cells; and to more general locations including LABs, EABs, rows, columns, or anywhere in the chip.

Example

The Physical Chip Assignments Section stores assignment information entered with the Device, Pin/Location/Chip, Classic & MAX Individual Device Options, FLEX 8000 Individual Device Options, and FLEX 10K Individual Device Options dialog boxes.

The Physical Chip Assignments Section has the following format:

CHIP <chip name>

BEGIN

{ <statement> [<source>] ; }

END ;

The <statements> in the Physical Chip Assignments Section can take one of the following BNF formats. The letter code corresponding to each format appears in the Usage column of the table below.

Code:	Format:

A	<keyword>=<setting>

B	<name> : <keyword>=<setting>

The following guidelines and rules apply to the Physical Chip Assignments Section:

The text following the DEVICE keyword must specify the actual device to which all resource assignments are made. If you do not wish to specify a particular device, you can use the AUTO keyword to indicate that the device should be selected automatically from the range of devices specified in the Auto Device Choices Section of the ACF.

You can make pin assignments with the generic PIN keyword or specify a particular pin type with the INPUT_PIN, OUTPUT_PIN, or BIDIR_PIN keywords. If you use the PIN keyword, the Compiler automatically implements the pin correctly in an input or I/O pin.

You can make assignments to locations internal to the device, such as one or more logic cell(s), embedded cells, LAB(s), EAB(s), row(s), column(s), or anywhere in the chip, with the LOCATION keyword.

If the project is partitioned into multiple devices, the ACF may contain a Physical Chip Assignments Section for each device.

Only one statement of the format <keyword>=<setting> (i.e., usage code A) is permitted for any one keyword in this section. These statements specify global project defaults. In contrast, you can use multiple statements of the format <name> : <keyword>=<setting> (i.e., usage code B), which assign individual nodes, pins, and buses to various locations.

The following table shows the Physical Chip Assignments Section keywords; legal settings; usage code; and the command, dialog box, or on-screen option used to specify the setting in MAX+PLUS II:

Keyword:	Settings:	Usage:	Command/Dialog Box/

On-Screen Option:

DEVICE 	<device name> 	A	Device

| "<device name>"

| AUTO | NULL

PIN	<device pin ID> 	B	Pin/Location/Chip

| COL_<device column ID>

| COL_ANY | ROW_<device row ID>

| ROW_ANY | ANY | NULL

INPUT_PIN	Same as above.	B	Pin/Location/Chip

OUTPUT_PIN	Same as above.	B	Pin/Location/Chip

BIDIR_PIN	Same as above.	B	Pin/Location/Chip

LOCATION	LC<device logic cell ID> 	B	Pin/Location/Chip

| IOC_<device I/O cell ID>

| EC_<device embedded cell ID>

| LAB_<device LAB ID>

| EAB_<device EAB ID>

| COL_<device column ID>

| COL_ANY | ROW_<device row ID>

| ROW_ANY | ANY | NULL

SECURITY_BIT	ON | OFF | DEFAULT | NULL	A	Classic & MAX Individual Device Options

TURBO_BIT	Same as above.	A	Classic & MAX Individual Device Options

USER_CLOCK	Same as above.	A	FLEX 8000 Individual Device Options

FLEX 10K Individual Device Options

AUTO_RESTART	Same as above.	A	FLEX 8000 Individual Device Options

FLEX 10K Individual Device Options

RELEASE_CLEARS	Same as above.	A	FLEX 8000 Individual Device Options

FLEX 10K Individual Device Options

ENABLE_DCLK_OUTPUT	Same as above.	A	FLEX 8000 Individual Device Options

DISABLE_TIME_OUT	Same as above.	A	FLEX 8000 Individual Device Options

ENABLE_JTAG	Same as above.	A	FLEX 8000 Individual Device Options

ENABLE_CHIP_WIDE_RESET	Same as above.	A	FLEX 10K Individual Device Options

ENABLE_CHIP_WIDE_OE	Same as above.	A	FLEX 10K Individual Device Options

ENABLE_INIT_DONE_OUTPUT	Same as above.	A	FLEX 10K Individual Device Options

CONFIG_SCHEME	ACTIVE_SERIAL 	A	FLEX 8000 Individual Device Options

| ACTIVE_PARALLEL_UP

| ACTIVE_PARALLEL_DOWN

| PASSIVE_SERIAL

| PASSIVE_PARALLEL_SYNCHRONOUS

| PASSIVE_PARALLEL_ASYNCHRONOUS

| DEFAULT | NULL

CONFIG_SCHEME_10K	| PASSIVE_SERIAL 	A	FLEX 10K Individual Device Options

| PASSIVE_PARALLEL_SYNCHRONOUS

| PASSIVE_PARALLEL_ASYNCHRONOUS

| DEFAULT | NULL

DATA0_PIN	UNRESERVED

| RESERVED_TRI_STATED	A	FLEX 8000 Individual Device Options

| RESERVED_DRIVES_OUT

| DEFAULT | NULL

nWS_nRS_nCS_CS_PIN	Same as above.	A	FLEX 8000 Individual Device Options

FLEX 10K Individual Device Options

DATA1_TO_DATA7_PIN	Same as above.	A	FLEX 8000 Individual Device Options

FLEX 10K Individual Device Options

RDYnBUSY_PIN	Same as above.	A	FLEX 8000 Individual Device Options

FLEX 10K Individual Device Options

RDCLK_PIN	Same as above.	A	FLEX 8000 Individual Device Options

SDOUT_PIN	Same as above.	A	FLEX 8000 Individual Device Options

ADD0_TO_ADD12_PIN	Same as above.	A	FLEX 8000 Individual Device Options

ADD13_PIN	Same as above.	A	FLEX 8000 Individual Device Options

ADD14_PIN	Same as above.	A	FLEX 8000 Individual Device Options

ADD15_PIN	Same as above.	A	FLEX 8000 Individual Device Options

ADD16_PIN	Same as above.	A	FLEX 8000 Individual Device Options

ADD17_PIN	Same as above.	A	FLEX 8000 Individual Device Options

CLKUSR_PIN	Same as above.	A	FLEX 8000 Individual Device Options

FLEX 10K Individual Device Options

JTAG_USER_CODE	<1-byte hexadecimal number>	A	FLEX 10K Individual Device Options

See also:

ACF Format

Comments & Documentation

Summary Table of ACF Keywords, Settings & Usage


Auto Device Choices Section (Assignment & Configuration File)

The Auto Device Choices Section designates specific devices for the Compiler to use in automatic device selection for the current hierarchy tree. The Compiler refers to the Auto Device Choices Section if you have specified an AUTO device in a Physical Chip Assignments Section or if your project will not fit into all of the assigned devices.

Example

The Auto Device Choices Section stores assignment information entered with the Device and Auto Device Selection dialog boxes.

The Auto Device Choices Section has the following format:

DEFAULT_DEVICES

BEGIN

{ <statement> [<source>] ; }

END ;

The <statements> in the Auto Device Choices Section take the following BNF format. The letter code corresponding to this format appears in the Usage column of the table below.

Code:	Format:

A	<keyword>=<setting>

The following guidelines and rules apply to the Auto Device Choices Section:

You can use the AUTO_DEVICE keyword to specify the device(s) that the Compiler can choose from during compilation. You can specify a particular device, including device package and speed grade information, or use the device family name to specify every device in a device family.

Only one Auto Device Choices Section is permitted.

The following table shows the Auto Device Choices Section keywords; legal settings; usage code; and the command, dialog box, or on-screen option used to specify the setting in MAX+PLUS II:

Keyword:	Settings:	Usage:	Command/Dialog Box/

On-Screen Option:

AUTO_DEVICE	<device name> |<family name> 	A	Auto Device Selection

| "<device name> <device count>"

| NULL

ASK_BEFORE_ADDING_EXTRA_DEVICES	ON | OFF | NULL	A	Auto Device Selection	ADCS

See also:

ACF Format

Comments & Documentation

Summary Table of ACF Keywords, Settings & Usage


Global Device Options Section (Assignment & Configuration File)

The Global Device Options Section specifies the global default device options for all devices used in the current hierarchy tree, including default device and pin options for FLEX 8000 devices. In addition, you can set the percentage of all device pin and/or logic cell resources you wish to remain unused, i.e., reserved, for future use.

Example

The Global Device Options Section stores assignment information entered with the Classic & MAX Global Project Device Options, FLEX 8000 Global Project Device Options, and FLEX 10K Global Project Device Options dialog boxes.

The Global Device Options Section has the following format:

GLOBAL_PROJECT_DEVICE_OPTIONS

BEGIN

{ <statement> [<source>] ; }

END ;

The <statements> in the Global Device Options Section take the following BNF format. The letter code corresponding to this format appears in the Usage column of the table below.

Code:	Format:

A	<keyword>=<setting>

The following guidelines and rules apply to the Global Device Options Section:

The Global Device Options Section specifies defaults that apply only to those devices that have no explicit device option settings. You can override the default settings on a device-by-device basis in the Physical Chip Assignments Sections of the ACF.

Only one Global Device Options Section is permitted.

Only one statement of the format <keyword>=<setting> (i.e., usage code A) is permitted for any one keyword in this section. These statements specify global project device option defaults. In contrast, you can use multiple statements of the format <name> : <keyword>=<setting> (i.e., usage code B), which assign device options to individual nodes, pins, and buses.

The following table shows the Global Device Options Section keywords; legal settings; usage code; and the command, dialog box, or on-screen option used to specify the setting in MAX+PLUS II:

Keyword:	Settings:	Usage:	Command/Dialog Box/

On-Screen Option:

SECURITY_BIT	ON | OFF 	A	Classic & MAX Global Project Device Options

RESERVED_LCELLS_PERCENT	<number>	A	Classic & MAX Global Project Device Options

FLEX 8000 Global Project Device Options

FLEX 10K Global Project Device Options

RESERVED_PINS_PERCENT	<number>	A	Classic & MAX Global Project Device Options

FLEX 8000 Global Project Device Options

FLEX 10K Global Project Device Options

USER_CLOCK	ON | OFF	A	FLEX 8000 Global Project Device Options

AUTO_RESTART	Same as above.	A	FLEX 8000 Global Project Device Options

RELEASE_CLEARS	Same as above.	A	FLEX 8000 Global Project Device Options

ENABLE_DCLK_OUTPUT	Same as above.	A	FLEX 8000 Global Project Device Options

DISABLE_TIME_OUT	Same as above.	A	FLEX 8000 Global Project Device Options

ENABLE_JTAG	Same as above.	A	FLEX 8000 Global Project Device Options

ENABLE_CHIP_WIDE_RESET	Same as above.	A	FLEX 10K Global Project Device Options

ENABLE_CHIP_WIDE_OE	Same as above.	A	FLEX 10K Global Project Device Options

ENABLE_INIT_DONE_OUTPUT	Same as above.	A	FLEX 10K Global Project Device Options

CONFIG_SCHEME	ACTIVE_SERIAL 	A	FLEX 8000 Global Project Device Options

| ACTIVE_PARALLEL_UP	FLEX 10K Global Project Device Options

| ACTIVE_PARALLEL_DOWN

| PASSIVE_SERIAL

| PASSIVE_PARALLEL_SYNCHRONOUS

| PASSIVE_PARALLEL_ASYNCHRONOUS

DATA0_PIN	UNRESERVED 	A	FLEX 8000 Global Project Device Options

| RESERVED_TRI_STATED

| RESERVED_DRIVES_OUT

nWS_nRS_nCS_CS_PIN	Same as above.	A	FLEX 8000 Global Project Device Options

FLEX 10K Global Project Device Options

DATA1_TO_DATA7_PIN	Same as above.	A	FLEX 8000 Global Project Device Options

FLEX 10K Global Project Device Options

RDYnBUSY_PIN	Same as above.	A	FLEX 8000 Global Project Device Options

FLEX 10K Global Project Device Options

RDCLK_PIN	Same as above.	A	FLEX 8000 Global Project Device Options

SDOUT_PIN	Same as above.	A	FLEX 8000 Global Project Device Options

ADD0_TO_ADD12_PIN	Same as above.	A	FLEX 8000 Global Project Device Options

ADD13_PIN	Same as above.	A	FLEX 8000 Global Project Device Options

ADD14_PIN	Same as above.	A	FLEX 8000 Global Project Device Options

ADD15_PIN	Same as above.	A	FLEX 8000 Global Project Device Options

ADD16_PIN	Same as above.	A	FLEX 8000 Global Project Device Options

ADD17_PIN	Same as above.	A	FLEX 8000 Global Project Device Options

CLKUSR_PIN	Same as above.	A	FLEX 8000 Global Project Device Options

FLEX 10K Global Project Device Options

JTAG_USER_CODE	<1-byte hexadecimal number>	A	FLEX 10K Global Project Device Options

See also:

ACF Format

Comments & Documentation

Summary Table of ACF Keywords, Settings & Usage


Global Project Synthesis/Assignment Options Section (Assignment & Configuration File)

The Global Project Synthesis/Assignment Options Section specifies the global default logic synthesis style and other synthesis settings for the current hierarchy tree. This section allows you to specify which global signals the Compiler should create automatically and whether you wish to use multi-level synthesis or standard synthesis. You can also set the Compiler to implement registers in the project in I/O cells and to perform automatic register packing.

Example

The Global Project Synthesis/Assignment Options Section stores information entered with the Global Project Logic Synthesis and Device dialog boxes.

The Global Project Synthesis/Assignment Options Section has the following format:

GLOBAL_PROJECT_SYNTHESIS_ASSIGNMENT_OPTIONS

BEGIN

{ <statement> [<source>] ; }

END ;

The <statements> in the Global Project Synthesis/Assignment Options Section take the following BNF format. The letter code corresponding to this format appears in the Usage column of the table below.

Code:	Format:

A	<keyword>=<setting>

The following guidelines and rules apply to the Global Project Synthesis/Assignment Options Section:

Only one Global Project Synthesis/Assignment Options Section is permitted.

Only one statement of the format <keyword>=<setting> (i.e., usage code A) is permitted for any one keyword in this section. These statements specify global project synthesis defaults. In contrast, you can use multiple statements of the format <name> : <keyword>=<setting> (i.e., usage code B), which assign synthesis styles and settings to individual nodes, pins, and buses.

The following table shows the Global Project Synthesis/Assignment Options Section keywords; legal settings; usage code; and the command, dialog box, or on-screen option used to specify the setting in MAX+PLUS II:

FLEX10K | MAX9000 | FLEX8000 | MAX7000 | MAX5000 | CLASSIC

Keyword:	Settings:	Usage:	Command/Dialog Box/

On-Screen Option:

DEVICE_FAMILY	FLEX10K | MAX9000	A	Device

| FLEX8000 | MAX7000

| MAX5000 | CLASSIC

MULTI_LEVEL_SYNTHESIS	ON | OFF	A	Global Project Logic Synthesis

ONE_HOT_STATE_MACHINE_ENCODING	Same as above.	A	Global Project Logic Synthesis

AUTO_IO_CELL_REGISTERS	Same as above.	A	Global Project Logic Synthesis

AUTO_REGISTER_PACKING	Same as above.	A	Global Project Logic Synthesis

AUTO_OPEN_DRAIN_PINS	Same as above.	A	Global Project Logic Synthesis

AUTO_IMPLEMENT_IN_EAB	Same as above.	A	Global Project Logic Synthesis

AUTO_GLOBAL_CLOCK	Same as above.	A	Global Project Logic Synthesis

AUTO_GLOBAL_CLEAR	Same as above.	A	Global Project Logic Synthesis

AUTO_GLOBAL_PRESET	Same as above.	A	Global Project Logic Synthesis

AUTO_GLOBAL_OE	Same as above.	A	Global Project Logic Synthesis

STYLE	FAST | NORMAL	A	Global Project Logic Synthesis

| WYSIWYG

| <style name>

OPTIMIZE	AREA | DELAY | DEFAULT 	A	Global Project Logic Synthesis

See also:

ACF Format

Comments & Documentation

Summary Table of ACF Keywords, Settings & Usage


Global Project Parameters Section (Assignment & Configuration File)

The Global Project Parameters Section specifies the global default parameters for the current project.

Example

The Global Project Parameters Section stores parameter information entered with the Global Project Parameters dialog box.

The Global Project Parameters Section has the following format:

GLOBAL_PROJECT_Parameters

BEGIN

<parameter name>=<parameter value>

END ;

The following guidelines and rules apply to the Global Project Parameters Section:

Only one Global Project Parameters Section is permitted.

You cannot specify the Define_Family and Style parameters as global project parameters.

See also:

ACF Format

Comments & Documentation

Summary Table of ACF Keywords, Settings & Usage


Logic Options Section (Assignment & Configuration File)

The Logic Options Section assigns logic options and/or a logic synthesis style for one or more individual nodes and/or symbols in the current hierarchy tree.

Example

The Logic Options Section stores assignment information entered with the Logic Options, Individual Logic Options, and Advanced Options dialog boxes.

The Logic Options Section has the following format:

LOGIC_OPTIONS

BEGIN

{ <statement> [<source>] ; }

END ;

The <statements> in the Logic Options Section can take one of the following BNF formats. The letter code corresponding to each format appears in the Usage column of the table below.

Code:	Format:

A	<keyword>=<setting>

B	<name> : <keyword>=<setting>

The following guidelines and rules apply to the Synthesis/Assignment Options Section:

Only one statement of the format <keyword>=<setting> (i.e., usage code A) is permitted for any one keyword in this section. These statements specify global project synthesis defaults. In contrast, you can use multiple statements of the format <name> : <keyword>=<setting> (i.e., usage code B), which assign synthesis styles and settings to individual nodes, pins, and buses.

The following table shows the Logic Options Section keywords; legal settings; usage code; and the command, dialog box, or on-screen option used to specify the setting in MAX+PLUS II:

Keyword:	Settings:	Usage:	Command/Dialog Box/

On-Screen Option:

STYLE	FAST | NORMAL 	B	Logic Options

| WYSIWYG

| <style name> | NULL

CARRY_CHAIN	AUTO | IGNORE 	B	Individual Logic Options

| MANUAL | DEFAULT | NULL

CASCADE_CHAIN	Same as above.	B	Individual Logic Options

MINIMIZATION	FULL | PARTIAL 	B	Individual Logic Options

| DEFAULT | NULL

HIERARCHICAL_SYNTHESIS	ON | OFF | DEFAULT | NULL	B	Individual Logic Options

Ignore_SOFT_Buffers	Same as above.	B	Individual Logic Options

IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL	Same as above.	B	Individual Logic Options

Implement_in_EAB	Same as above.	B	Individual Logic Options

INSERT_ADDITIONAL_LOGIC_CELL	Same as above.	B	Individual Logic Options

IO_CELL_REGISTER	Same as above.	B	Individual Logic Options

PARALLEL_EXPANDERS	Same as above.	B	Individual Logic Options

SLOW_SLEW_RATE	Same as above.	B	Individual Logic Options

TURBO_BIT	Same as above.	B	Individual Logic Options

USE_LPM_FOR_AHDL_OPERATORS	Same as above.	B	Individual Logic Options

XOR_SYNTHESIS	Same as above.	B	Individual Logic Options

DECOMPOSE_GATES	Same as above.	B	Advanced Options

DUPLICATE_LOGIC_EXTRACTION	Same as above.	B	Advanced Options

MULTI_LEVEL_FACTORING	Same as above.	B	Advanced Options

NOT_GATE_PUSH_BACK	Same as above.	B	Advanced Options

REDUCE_LOGIC	Same as above.	B	Advanced Options

REFACTORIZATION	Same as above.	B	Advanced Options

REGISTER_OPTIMIZATION	Same as above.	B	Advanced Options

RESYNTHESIZE_NETWORK	Same as above.	B	Advanced Options

SOFT_BUFFER_INSERTION	Same as above.	B	Advanced Options

SUBFACTOR_EXTRACTION	Same as above.	B	Advanced Options

See also:

ACF Format

Comments & Documentation

Summary Table of ACF Keywords, Settings & Usage


Timing Requirement Assignments Section (Assignment & Configuration File)

The Timing Requirement Assignments Section specifies the global default timing requirements for the current hierarchy tree. You can also use this section to assign timing requirements for one or more individual nodes and/or pins. In addition, the Timing Requirement Assignments Section allows you to specify timing cuts that prevent the Compiler from considering signal paths when it processes the timing requirements for the project.

Example

The Timing Requirement Assignments Section stores assignment information entered with the Timing Requirements, Global Project Timing Requirements, and Device dialog boxes.

The Timing Requirement Assignments Section has the following format:

TIMING_POINT

BEGIN

{ <statement> [<source>] ; }

END ;

The <statements> in the Timing Requirement Assignments Section can take one of the following BNF formats. The letter code corresponding to each format appears in the Usage column of the table below.

Code:	Format:

A	<keyword>=<setting>

B	<name> : <keyword>=<setting>

The following guidelines and rules apply to the Timing Requirement Assignments Section:

Only one Timing Requirement Assignments Section is permitted.

The device name specified after the DEVICE_FOR_TIMING_SYNTHESIS keyword records the device last used during compilation when the Maintain_Stable_Synthesis option is turned on and the project has been back-annotated. This value is not user-editable.

Only one statement of the format <keyword>=<setting> (i.e., usage code A) is permitted for any one keyword in this section. These statements specify global project timing defaults. In contrast, you can use multiple statements of the format <name> : <keyword>=<setting> (i.e., usage code B), which assign timing requirements to individual nodes, pins, and buses.

The following table shows the Timing Requirement Assignments Section keywords; legal settings; usage code; and the command, dialog box, or on-screen option used to specify the setting in MAX+PLUS II:

Keyword:	Settings:	Usage:	Command/Dialog Box/

On-Screen Option:

MAINTAIN_STABLE_SYNTHESIS	ON | OFF | NULL	A	Device

CUT_ALL_BIDIR	Same as above.	A	Global Project Timing Requirements

CUT_ALL_CLEAR_PRESET	Same as above.	A	Global Project Timing Requirements

DEVICE_FOR_TIMING_SYNTHESIS	<device name> 	A	n/a

| "<device name>"

| AUTO | NULL

TPD	<decimal number>	A	Global Project Timing Requirements

[<time unit>] | NULL	B	Timing Requirements

TCO	Same as above.	A	Global Project Timing Requirements

B	Timing Requirements

TSU	Same as above.	A	Global Project Timing Requirements

B	Timing Requirements

FREQUENCY 	Same as above.	A	Global Project Timing Requirements

B	Timing Requirements

CUT	ON | OFF | NULL	B	Timing Requirements

See also:

ACF Format

Comments & Documentation

Summary Table of ACF Keywords, Settings & Usage


Clique Assignments Section (Assignment & Configuration File)

The Clique Assignments Section specifies which logic functions must remain together, regardless of their exact location. Cliques allow you to partition a project so that only a minimum number of signals travel between LABs, rows, and devices, and to ensure that no unnecessary delays exist on critical timing paths.

You can assign logic functions to different types of cliques that ensure that they are implemented in the same LAB, row, or chip. You can also assign a best possible clique that specifies that the clique should be implemented in the smallest possible category of LAB, row, or chip.

Example

The Clique Assignments Section stores assignment information entered with the Clique dialog box.

The Clique Assignments Section has the following format:

CLIQUE <clique name>

BEGIN

{ <statement> [<source>] ; }

END ;

The <statements> in the Clique Assignments Section take the following BNF format. The letter code corresponding to this format appears in the Usage column of the table below.

Code:	Format:

B	<name> : <keyword>=<setting>

The following guidelines and rules apply to the Clique Assignments Section:

All clique names must be unique.

The following table shows the Clique Assignments Section keywords; legal settings; usage code; and the command, dialog box, or on-screen option used to specify the setting in MAX+PLUS II:

Keyword:	Settings:	Usage:	Command/Dialog Box/

On-Screen Option:

CLIQUE	ON | OFF | NULL	B	Clique

See also:

ACF Format

Comments & Documentation

Summary Table of ACF Keywords, Settings & Usage


Connected Pin Assignments Section (Assignment & Configuration File)

The Connected Pin Assignments Section assigns one or more pins in the current hierarchy tree to a connected pin group that specifies which pins are connected together on your circuit board. Connected pin assignments are useful for preparing single- and multi-device projects for timing simulation and linked simulation. They can also have a limited effect on manual partitioning.

You can use external connection pin primitives to prepare multi-device projects for timing simulation and linked simulation. You can also use external connection pin primitives to guide partitioning. If you wish to manually partition a project so that each individual macrofunction is implemented in a different device from the same device family, you can assign each macrofunction to a different chip. You can then use the external connection pin primitives to tie the macrofunctions inputs and outputs together and specify which pins are connected together on your board.

Example

The Connected Pin Assignments Section stores assignment information entered with the Connected Pins dialog box and with connections entered between external connection pin primitives--i.e., INPUTC, OUTPUTC, and BIDIRC--in a top-level Graphic Editor file.

The Connected Pin Assignments Section has the following format:

CONNECTED_PINS <connected pin group name>

BEGIN

{ <statement> [<source>] ; }

END ;

The <statements> in the Connected Pin Assignments Section take the following BNF format. The letter code corresponding to this format appears in the Usage column of the table below.

Code:	Format:

B	<name> : <keyword>=<setting>

The following guidelines and rules apply to the Connected Pin Assignments Section:

If a project contains multiple connected pin groups, the ACF must contain a Connected Pin Assignments Section for each group.

The following table shows the Connected Pin Assignments Section keywords; legal settings; usage code; and the command, dialog box, or on-screen option used to specify the setting in MAX+PLUS II:

Keyword:	Settings:	Usage:	Command/Dialog Box/

On-Screen Option:

PIN	ON | OFF | NULL	B	Connected Pins

INPUT_PIN 	Same as above.	B	Connected Pins

OUTPUT_PIN	Same as above.	B	Connected Pins

BIDIR_PIN 	Same as above.	B	Connected Pins

See also:

ACF Format

Comments & Documentation

Summary Table of ACF Keywords, Settings & Usage


Probe Assignments Section (Assignment & Configuration File)

The Probe Assignments Section attaches a unique probe name to a single input or output node of a primitive or macrofunction.

Example

The Probe Assignments Section stores assignment information entered with the Probe dialog box.

The Probe Assignments Section has the following format:

PROBES

BEGIN

{ <statement> [<source>] ; }

END ;

The <statements> in the Probe Assignments Section take the following BNF format. The letter code corresponding to this format appears in the Usage column of the table below.

Code:	Format:

B	<name> : <keyword>=<setting>

The following guidelines and rules apply to the Probe Assignments Section:

No two signals can have the same probe name.

The following table shows the Probe Assignments Section keywords; legal settings; usage code; and the command, dialog box, or on-screen option used to specify the setting in MAX+PLUS II:

Keyword:	Settings:	Usage:	Command/Dialog Box/

On-Screen Option:

PROBE	<probe name> 	B	Probe

| "<probe name>"

| NULL

The

See also:

ACF Format

Comments & Documentation

Summary Table of ACF Keywords, Settings & Usage


Ignored Assignments Section (Assignment & Configuration File)

The Ignored Assignments Section specifies the resource and/or device assignments that the Compiler should ignore for the current hierarchy tree. You should choose to ignore assignments after an unsuccessful compilation if your project contains assignments but doesnt fit. You can then recompile the project to determine whether the assignments had prevented the project from fitting, and adjust the assignments accordingly.

Example

The Ignored Assignments Section stores assignment information entered with the Ignore Project Assignments dialog box.

The Ignored Assignments Section has the following format:

IGNORED_ASSIGNMENTS

BEGIN

{ <statement> [<source>] ; }

END ;

The <statements> in the Ignored Assignments Section take the following BNF format. The letter code corresponding to this format appears in the Usage column of the table below.

Code:	Format:

A	<keyword>=<setting>

The following guidelines and rules apply to the Ignored Assignments Section:

Only one Ignored Assignments Section is permitted.

Only one statement of the format <keyword>=<setting> (i.e., usage code A) is permitted for any one keyword in this section. These statements specify global project defaults. In contrast, you can use multiple statements of the format <name> : <keyword>=<setting> (i.e., usage code B), which assign option settings to individual nodes, pins, and buses.

When the IGNORE_TIMING_ASSIGNMENTS variable is turned on, the Compiler ignores all timing assignment entered both with Timing Requirements and Global Project Timing Requirements.

When the IGNORE_LC_ASSIGNMENTS is turned on, both logic cell and I/O cell assignments are ignored.

The following table shows the Ignored Assignments Section keywords; legal settings; usage code; and the command, dialog box, or on-screen option used to specify the setting in MAX+PLUS II:

Keyword:	Settings:	Usage:	Command/Dialog Box/

On-Screen Option:

IGNORE_CHIP_ASSIGNMENTS	ON | OFF | NULL	A	Ignore Project Assignments

IGNORE_CLIQUE_ASSIGNMENTS	Same as above.	A	Ignore Project Assignments

IGNORE_DEVICE_ASSIGNMENTS	Same as above.	A	Ignore Project Assignments

IGNORE_LC_ASSIGNMENTS	Same as above.	A	Ignore Project Assignments

IGNORE_LOGIC_OPTION_ASSIGNMENTS	Same as above.	A	Ignore Project Assignments

IGNORE_PIN_ASSIGNMENTS	Same as above.	A	Ignore Project Assignments

IGNORE_TIMING_ASSIGNMENTS	Same as above.	A	Ignore Project Assignments

See also:

ACF Format

Comments & Documentation

Summary Table of ACF Keywords, Settings & Usage


Compiler Processing Configuration Section (Assignment & Configuration File)

The Compiler Processing Configuration Section specifies Compiler configuration information on the Design Doctor utility and the Functional SNF Extractor, Timing SNF Extractor, and Linked SNF Extractor modules. It also specifies Fitter settings, optional Report File sections, and the generation of Text Design Output Files, Assignment & Configuration Output Files and JEDEC Files. The Compiler Processing Configuration Section contains additional information on the type of compilation (i.e., smart or total) being performed by the Compiler.

Example

The Compiler Processing Configuration Section stores configuration settings for commands on the Compilers Processing menu:

Design Doctor	Fitter Settings

Design Doctor Settings	Report File Settings

Functional SNF Extractor	Generate AHDL TDO File

Timing SNF Extractor	Smart Recompile

Optimize Timing SNF	Total Recompile

Linked SNF Extractor	Preserve All Node Name Synonyms

The Compiler Processing Configuration Section has the following format:

COMPILER_PROCESSING_CONFIGURATION

BEGIN

{ <statement> [<source>] ; }

END ;

The <statements> in the Compiler Processing Configuration Section take the following BNF format. The letter code corresponding to this format appears in the Usage column of the table below.

Code:	Format:

A	<keyword>=<setting>

The following guidelines and rules apply to the Compiler Processing Configuration Section:

Only one Compiler Processing Configuration Section is permitted.

Only one statement of the format <keyword>=<setting> (i.e., usage code A) is permitted for any one keyword in this section. These statements specify global project defaults.

The following table shows the Compiler Processing Configuration Section keywords; legal settings; usage code; and the command, dialog box, or on-screen option used to specify the setting in MAX+PLUS II:

Keyword:	Settings:	Usage:	Command/Dialog Box/

On-Screen Option:

DESIGN_DOCTOR	ON | OFF | NULL	A	Design Doctor

DESIGN_DOCTOR_RULES 	EPLD | FLEX | MPLD 	A	Design Doctor Settings

| CUSTOM | NULL

FUNCTIONAL_SNF_EXTRACTOR	ON | OFF | NULL	A	Functional SNF Extractor

TIMING_SNF_EXTRACTOR	Same as above.	A	Timing SNF Extractor

OPTIMIZE_TIMING_SNF	Same as above.	A	Optimize Timing SNF

LINKED_SNF_EXTRACTOR	Same as above.	A	Linked SNF Extractor

FITTER_SETTINGS	NORMAL | ADVANCED	A	Fitter Settings

 | CUSTOM | NULL

NORMAL_LCELL_INSERT	ON | OFF | NULL	A	Fitter Settings

ROW_PINS_LCELL_INSERT	Same as above.	A	Fitter Settings

ROW_PINS_PERCENT	<number> | NULL	A	Fitter Settings

CARRY_OUT_PINS_LCELL_INSERT	ON | OFF | NULL	A	Fitter Settings

EXP_PER_LCELL_PERCENT	<number> | NULL	A	Fitter Settings

FAN_IN_PER_LCELL_PERCENT	Same as above.	A	Fitter Settings

LCELLS_PER_ROW_PERCENT	Same as above.	A	Fitter Settings

RPT_FILE_EQUATIONS	ON | OFF | NULL	A	Report File Settings

RPT_FILE_HIERARCHY	Same as above.	A	Report File Settings

RPT_FILE_LCELL_INTERCONNECT	Same as above.	A	Report File Settings

RPT_FILE_USER_ASSIGNMENTS	Same as above.	A	Report File Settings

GENERATE_AHDL_TDO_FILE	Same as above.	A	Generate AHDL TDO File

SMART_RECOMPILE	Same as above.	A	Smart Recompile

TOTAL_RECOMPILE	Same as above.	A	Total Recompile

PRESERVE_ALL_NODE_NAME_SYNONYMS	Same as above.	A	Preserve All Node Name Synonyms

See also:

ACF Format

Comments & Documentation

Summary Table of ACF Keywords, Settings & Usage


Compiler Interfaces Configuration Section (Assignment & Configuration File)

The Compiler Interfaces Configuration Section specifies Compiler configuration information on the Compiler Netlist Extractor, EDIF Netlist Writer, Verilog Netlist Writer, and VHDL Netlist Writer modules.

Example

The Compiler Interfaces Configuration Section stores configuration settings for commands on the Compilers Interfaces menu:

EDIF Netlist Reader Settings	VHDL Netlist Reader Settings

EDIF Netlist Writer	VHDL Netlist Writer

EDIF Netlist Writer Settings	VHDL Netlist Writer Settings

Verilog Netlist Writer	XNF Netlist Reader Settings

Verilog Netlist Writer Settings

The Compiler Interfaces Configuration Section has the following format:

COMPILER_INTERFACES_CONFIGURATION

BEGIN

{ <statement> [<source>] ; }

END ;

The <statements> in the Compiler Interfaces Configuration Section take the following BNF format. The letter code corresponding to this format appears in the Usage column of the table below.

Code:	Format:

A	<keyword>=<setting>

The following guidelines and rules apply to the Compiler Interfaces Configuration Section:

Only one Compiler Interfaces Configuration Section is permitted.

Only one statement of the format <keyword>=<setting> (i.e., usage code A) is permitted for any one keyword in this section. These statements specify global project defaults. In contrast, you can use multiple statements of the format <name> : <keyword>=<setting> (i.e., usage code B), which assign option settings to individual nodes, pins, and buses.

The following table shows the Compiler Interfaces Configuration Section keywords; legal settings; usage code; and the command, dialog box, or on-screen option used to specify the setting in MAX+PLUS II:

Keyword:	Settings:	Usage:	Command/Dialog Box/

On-Screen Option:

EDIF_INPUT_USE_LMF1	ON | OFF | NULL	A	EDIF Netlist Reader Settings

EDIF_INPUT_LMF1	<filename> | NULL	A	EDIF Netlist Reader Settings

EDIF_INPUT_USE_LMF2	ON | OFF | NULL	A	EDIF Netlist Reader Settings

EDIF_INPUT_LMF2	<filename> | NULL	A	EDIF Netlist Reader Settings

EDIF_INPUT_SHOW_LMF_MAPPING_MESSAGES	ON | OFF | NULL	A	EDIF Netlist Reader Settings

EDIF_INPUT_VCC	<symbolic name> | NULL	A	EDIF Netlist Reader Settings

EDIF_INPUT_GND	Same as above.	A	EDIF Netlist Reader Settings

EDIF_NETLIST_WRITER	ON | OFF | NULL	A	EDIF Netlist Writer

EDIF_OUTPUT_VERSION	200 | 290 | NULL	A	EDIF Netlist Writer Settings

EDIF_OUTPUT_GND	<symbolic name> | NULL	A	EDIF Netlist Writer Settings

EDIF_OUTPUT_VCC	Same as above.	A	EDIF Netlist Writer Settings

EDIF_OUTPUT_DELAY_CONSTRUCTS	PROPERTY 	A	EDIF Netlist Writer Settings

| PORT_PATHDELAYS

| NULL

EDIF_OUTPUT_FORCE_0NS_DELAYS	ON | OFF | NULL	A	EDIF Netlist Writer Settings

EDIF_OUTPUT_INCLUDE_SPECIAL_PRIM	Same as above.	A	EDIF Netlist Writer Settings

EDIF_OUTPUT_MAP_ILLEGAL_CHAR	Same as above.	A	EDIF Netlist Writer Settings

EDIF_OUTPUT_USE_EDC_FILE	Same as above.	A	EDIF Netlist Writer Settings

EDIF_OUTPUT_EDC_FILE	<filename> | NULL	A	EDIF Netlist Writer Settings

VERILOG_NETLIST_WRITER	ON | OFF | NULL	A	Verilog Netlist Writer

VERILOG_OUTPUT_DELAY_CONSTRUCTS	VO_FILE | SDF_2.1 	A	Verilog Netlist Writer Settings

| SDF_1.0

NETLIST_OUTPUT_TIME_SCALE	<decimal number>	A	Verilog Netlist Writer Settings

[<time unit>] | NULL

VHDL_USER_LIB_PHYSICAL_NAMES	<symbolic name> | NULL	A	VHDL Netlist Reader Settings

VHDL_USER_LIB_LOGICAL_NAMES	Same as above.	A	VHDL Netlist Reader Settings

VHDL_NETLIST_WRITER	ON | OFF | NULL	A	VHDL Netlist Writer

VHDL_OUTPUT_DELAY_CONSTRUCTS	VHO_FILE | SDF_2.1 	A	VHDL Netlist Writer Settings

| SDF_1.0

VHDL_GENERATE_CONFIGURATION_DECLARATION	ON | OFF | NULL	A	VHDL Netlist Writer Settings

XNF_EMULATE_TRI_STATE_BUSES	INTERNAL_LOGIC 	A	XNF Netlist Reader Settings

| DEVICE_PINS | NULL

XNF_GENERATE_AHDL_TDX_FILE	ON | OFF | NULL	A	XNF Netlist Reader Settings

XNF_TRANSLATE_INTERNAL_NODE_NAMES	Same as above.	A	XNF Netlist Reader Settings

See also:

ACF Format

Comments & Documentation

Summary Table of ACF Keywords, Settings & Usage


Custom Design Doctor Rules Section (Assignment & Configuration File)

The Custom Design Doctor Rules Section defines the user-definable custom Design Doctor rules.

Example

The Custom Design Doctor Rules Section stores the custom rule information entered with the Design Doctor Settings dialog box:

The Custom Design Doctor Rules Section has the following format:

CUSTOM_DESIGN_DOCTOR_RULES

BEGIN

{ <statement> [<source>] ; }

END ;

The <statements> in the Custom Design Doctor Rules Section take the following BNF format. The letter code corresponding to this format appears in the Usage column of the table below.

Code:	Format:

A	<keyword>=<setting>

The following guidelines and rules apply to the Custom Design Doctor Rules Section:

Only one Custom Design Doctor Rules Section is permitted.

Only one statement of the format <keyword>=<setting> (i.e., usage code A) is permitted for any one keyword in this section. These statements specify global project defaults. In contrast, you can use multiple statements of the format <name> : <keyword>=<setting> (i.e., usage code B), which assign option settings to individual nodes, pins, and buses.

The following table shows the Custom Design Doctor Rules Section keywords; legal settings; usage code; and the command, dialog box, or on-screen option used to specify the setting in MAX+PLUS II:

Keyword:	Settings:	Usage:	Command/Dialog Box/

On-Screen Option:

RIPPLE_CLOCKS	ON | OFF | NULL	A	Design Doctor Settings

GATED_CLOCKS	Same as above.	A	Design Doctor Settings

MULTI_LEVEL_CLOCKS	Same as above.	A	Design Doctor Settings

MULTI_CLOCK_NETWORKS	Same as above.	A	Design Doctor Settings

STATIC_HAZARDS_BEFORE_SYNTHESIS	Same as above.	A	Design Doctor Settings

STATIC_HAZARDS_AFTER_SYNTHESIS	Same as above.	A	Design Doctor Settings

PRESET_CLEAR_NETWORKS	Same as above.	A	Design Doctor Settings

ASYNCHRONOUS_INPUTS	Same as above.	A	Design Doctor Settings

DELAY_CHAINS	Same as above.	A	Design Doctor Settings

RACE_CONDITIONS	Same as above.	A	Design Doctor Settings

EXPANDER_NETWORKS	Same as above.	A	Design Doctor Settings

MASTER_RESET	Same as above.	A	Design Doctor Settings

See also:

ACF Format

Comments & Documentation

Summary Table of ACF Keywords, Settings & Usage


Logic Synthesis Style Definition (Assignment & Configuration File)

Logic Synthesis Style Definitions store the definitions of every logic synthesis style used, past or present, in the current hierarchy tree. You can also create your own logic synthesis styles, using any combination of logic options.

You can apply logic synthesis styles to individual logic function in design files, or to a project as a whole. These styles control how the Compilers Logic Synthesizer module processes the logic for your project.

Example

The Logic Synthesis Style Definition stores style definition information entered with the Define Synthesis Style and Advanced Options dialog boxes.

The Logic Synthesis Style Definition has the following format:

DEFINE_LOGIC_SYNTHESIS_STYLE <style name>.<device family>

BEGIN

{ <statement> [<source>] ; }

END ;

The <statements> in the Logic Synthesis Style Definition take the following BNF format. The letter code corresponding to this format appears in the Usage column of the table below.

Code:	Format:

A	<keyword>=<setting>

The following guidelines and rules apply to the Logic Synthesis Style Definition:

Only one definition of a particular <style name>.<device family> is permitted.

The following table shows the Logic Synthesis Style Definition keywords; legal settings; usage code; and the command, dialog box, or on-screen option used to specify the setting in MAX+PLUS II:

Keyword:	Settings:	Usage:	Command/Dialog Box/

On-Screen Option:

CARRY_CHAIN	AUTO | IGNORE | MANUAL 	A	Define Synthesis Style

CASCADE_CHAIN	Same as above.	A	Define Synthesis Style

CARRY_CHAIN_LENGTH	<number> | NULL	A	Define Synthesis Style

CASCADE_CHAIN_LENGTH	Same as above.	A	Define Synthesis Style

MINIMIZATION	FULL | PARTIAL 	A	Define Synthesis Style

| DEFAULT | NULL

Ignore_SOFT_Buffers	ON | OFF | DEFAULT | NULL	A	Define Synthesis Style

PARALLEL_EXPANDERS	Same as above.	A	Define Synthesis Style

SLOW_SLEW_RATE	Same as above.	A	Define Synthesis Style

TURBO_BIT	Same as above.	A	Define Synthesis Style

USE_LPM_FOR_AHDL_OPERATORS	Same as above.	A	Define Synthesis Style

XOR_SYNTHESIS	Same as above.	A	Define Synthesis Style

DECOMPOSE_GATES	Same as above.	A	Advanced Options

DUPLICATE_LOGIC_EXTRACTION	Same as above.	A	Advanced Options

MULTI_LEVEL_FACTORING	Same as above.	A	Advanced Options

NOT_GATE_PUSH_BACK	Same as above.	A	Advanced Options

REDUCE_LOGIC	Same as above.	A	Advanced Options

REFACTORIZATION	Same as above.	A	Advanced Options

REGISTER_OPTIMIZATION	Same as above.	A	Advanced Options

RESYNTHESIZE_NETWORK	Same as above.	A	Advanced Options

SOFT_BUFFER_INSERTION	Same as above.	A	Advanced Options

SUBFACTOR_EXTRACTION	Same as above.	A	Advanced Options

See also:

ACF Format

Comments & Documentation

Summary Table of ACF Keywords, Settings & Usage


Simulator Configuration Section (Assignment & Configuration File)

The Simulator Configuration Section specifies Simulator configuration information.

Example

The Simulator Configuration Section stores configuration settings for the following commands, fields, and options in the Simulator:

Inputs/Outputs	Oscillation

Use Device	Glitch

Setup/Hold	Start Time

Check Outputs	End Time

The Simulator Configuration Section has the following format:

SIMULATOR_CONFIGURATION

BEGIN

{ <statement> [<source>] ; }

END ;

The <statements> in the Simulator Configuration Section take the following BNF format. The letter code corresponding to this format appears in the Usage column of the table below.

Code:	Format:

A	<keyword>=<setting>

The following guidelines and rules apply to the Simulator Configuration Section:

Only one Simulator Configuration Section is permitted.

Only one statement of the format <keyword>=<setting> (i.e., usage code A) is permitted for any one keyword in this section. These statements specify global project defaults. In contrast, you can use multiple statements of the format <name> : <keyword>=<setting> (i.e., usage code B), which assign option settings to individual nodes, pins, and buses.

The following table shows the Simulator Configuration Section keywords; legal settings; usage code; and the command, dialog box, or on-screen option used to specify the setting in MAX+PLUS II:

Keyword:	Settings:	Usage:	Command/Dialog Box/

On-Screen Option:

SIMULATION_INPUT_FILE	<filename> | NULL	A	Inputs/Outputs (Simulator)

USE_DEVICE	ON | OFF | NULL	A	Use Device

SETUP_HOLD	Same as above.	A	Setup/Hold

CHECK_OUTPUTS	Same as above.	A	Check Outputs

OSCILLATION	Same as above.	A	Oscillation

GLITCH	Same as above.	A	Glitch

OSCILLATION_TIME 	<decimal number> 	A	Oscillation

[<time unit>]

GLITCH_TIME 	Same as above.	A	Glitch

START_TIME	Same as above.	A	Start Time

END_TIME	Same as above.	A	End Time

See also:

ACF Format

Comments & Documentation

Summary Table of ACF Keywords, Settings & Usage


Timing Analyzer Configuration Section (Assignment & Configuration File)

The Timing Analyzer Configuration Section specifies Timing Analyzer configuration information.

Example

The Timing Analyzer Configuration Section stores configuration settings for the following Timing Analyzer commands:

Delay Matrix	Cell Width

Setup/Hold Matrix	Cut Off I/O Pin Feedback

Registered Performance	Cut Off Clear & Preset Paths

Time Restrictions	List Only Longest Path

Auto-Recalculate

The Timing Analyzer Configuration Section has the following format:

TIMING_ANALYZER_CONFIGURATION

BEGIN

{ <statement> [<source>] ; }

END ;

The <statements> in the Timing Analyzer Configuration Section take the following BNF format. The letter code corresponding to this format appears in the Usage column of the table below.

Code:	Format:

A	<keyword>=<setting>

The following guidelines and rules apply to the Timing Analyzer Configuration Section:

Only one Timing Analyzer Configuration Section is permitted.

Only one statement of the format <keyword>=<setting> (i.e., usage code A) is permitted for any one keyword in this section. These statements specify global project defaults. In contrast, you can use multiple statements of the format <name> : <keyword>=<setting> (i.e., usage code B), which assign option settings to individual nodes, pins, and buses.

The following table shows the Timing Analyzer Configuration Section keywords; legal settings; usage code; and the command, dialog box, or on-screen option used to specify the setting in MAX+PLUS II:

Keyword:	Settings:	Usage:	Command/Dialog Box/

On-Screen Option:

LIST_PATH_FREQUENCY	<decimal number>[<time unit>] 	A	Time Restrictions

LIST_PATH_COUNT	<decimal number>	A	Time Restrictions

REGISTERED_PERFORMANCE_OPTIONS	NUMBER_OF_PATHS	A	Time Restrictions

| FREQUENCY_OF_PATHS

INCLUDE_PATHS_LESS_THAN_VALUE	<decimal number>[<time unit>] 	A	Time Restrictions

INCLUDE_PATHS_LESS_THAN	ON | OFF | NULL	A	Time Restrictions

INCLUDE_PATHS_GREATER_THAN_VALUE	<decimal number>[<time unit>] 	A	Time Restrictions

INCLUDE_PATHS_GREATER_THAN	ON | OFF | NULL	A	Time Restrictions

DELAY_MATRIX_OPTIONS	SHOW_ALL_PATHS	A	Time Restrictions

| SHOW_ONLY_LONGEST_PATHS

| SHOW_ONLY_SHORTEST_PATHS

CELL_WIDTH	<decimal number>	A	Cell Width

LIST_0NLY_LONGEST_PATH	ON | OFF | NULL	A	List Only Longest Path

CUT_OFF_CLEAR_AND_PRESET_PATHS	Same as above.	A	Cut Off Clear & Preset Paths

Cut_Off_I/O_Pin_Feedback	Same as above.	A	Cut Off I/O Pin Feedback

AUTO_RECALCULATE	Same as above.	A	Auto-Recalculate

ANALYSIS_MODE	DELAY_MATRIX	A	Delay Matrix

| SETUP_HOLD_MATRIX	Setup/Hold Matrix

| REGISTERED_PERFORMANCE	Registered Performance

See also:

ACF Format

Comments & Documentation

Summary Table of ACF Keywords, Settings & Usage


Other Configuration Section (Assignment & Configuration File)

The Other Configuration Section stores special optional configuration settings for MAX+PLUS II.

The Other Configuration Section has the following format:

OTHER_CONFIGURATION

BEGIN

{ <statement> [<source>] ; }

END ;

The following guidelines and rules apply to the Other Configuration Section:

Only one Other Configuration Section is permitted.

See also:

ACF Format

Comments & Documentation

Summary Table of ACF Keywords, Settings & Usage


Internal Information Section (Assignment & Configuration File)

The Internal Information Section stores information for internal use by various MAX+PLUS II applications. Do not edit or delete this section.

The Internal Information Section has the following format:

INTERNAL_INFO

BEGIN

{ <statement> [<source>] ; }

END ;

See also:

ACF Format

Comments & Documentation

Summary Table of ACF Keywords, Settings & Usage


Comments & Documentation (Assignment & Configuration File)

The following guidelines and rules apply to comments in an Assignment & Configuration File (.acf):

Comments can begin with two dashes (--) and continue to the End-of-Line, i.e., a single-line comment. This type of comment can contain any printable character.

Comments can be placed between /* and */ characters. This type of comment can span multiple lines and can contain any printable character except the /* and */ delimiters.

You can insert comments at any location in the file.


Physical Chip Assignments Section Example

CHIP chiptrip

BEGIN

DEVICE = EPF10K10QC208;

TURBO_BIT = OFF;

SECURITY = ON;

|dir1 	:	LOCATION = COL_ANY;

|time1 	:	LOCATION = ROW_C;

|time0 	:	LOCATION = ROW_C;

|ticket1 :	LOCATION = LAB_A2;

|dir0 	:	LOCATION = LC8_J34;

|accel 	:	INPUT_PIN = AA1;

JTAG_USER_CODE = 6;

CLKUSR = UNRESERVED;

ENABLE_INIT_DONE_OUTPUT = ON;

ENABLE_CHIP_WIDE_OE = ON;

ENABLE_CHIP_WIDE_RESET = ON;

RELEASE_CLEARS = ON;

AUTO_RESTART = ON;

USER_CLOCK = ON;

RDYnBUSY = UNRESERVED;

DATA1_TO_DATA7 = UNRESERVED;

nWS_nRS_nCS_CS = RESERVED_DRIVES_OUT;

END;


Auto Device Choices Section Example

DEFAULT_DEVICES

BEGIN

AUTO_DEVICE = EPF10K100GC503;

AUTO_DEVICE = EPF10K50GC403;

AUTO_DEVICE = EPF10K50GC403ES;

AUTO_DEVICE = EPF10K30GC319;

AUTO_DEVICE = EPF10K30QC240;

AUTO_DEVICE = EPF10K30QC208;

AUTO_DEVICE = EPF10K10QC240;

AUTO_DEVICE = EPF10K10QC208;

AUTO_DEVICE = EPF10K10LC84;

ASK_BEFORE_ADDING_EXTRA_DEVICES = ON;

END;


Global Device Options Section Example

GLOBAL_PROJECT_DEVICE_OPTIONS

BEGIN

RESERVED_LCELLS_PERCENT = 10;

RESERVED_PINS_PERCENT = 10;

JTAG_USER_CODE = 7F;

CONFIG_SCHEME_10K = PASSIVE_SERIAL;

ENABLE_INIT_DONE_OUTPUT = OFF;

ENABLE_CHIP_WIDE_OE = OFF;

ENABLE_CHIP_WIDE_RESET = OFF;

RESERVED_LCELLS_PERCENT = 0;

RESERVED_PINS_PERCENT = 0;

SECURITY_BIT = ON;

USER_CLOCK = OFF;

AUTO_RESTART = OFF;

RELEASE_CLEARS = OFF;

ENABLE_DCLK_OUTPUT = OFF;

DISABLE_TIME_OUT = OFF;

CONFIG_SCHEME = ACTIVE_SERIAL;

ENABLE_JTAG = OFF;

DATA0_PIN = RESERVED_TRI_STATED;

DATA1_TO_DATA7_PIN = UNRESERVED;

nWS_nRS_nCS_CS_PIN = UNRESERVED;

RDYnBUSY_PIN = UNRESERVED;

RDCLK_PIN = UNRESERVED;

SDOUT_PIN = RESERVED_DRIVES_OUT;

ADD0_TO_ADD12_PIN = UNRESERVED;

ADD13_PIN = UNRESERVED;

ADD14_PIN = UNRESERVED;

ADD15_PIN = UNRESERVED;

ADD16_PIN = UNRESERVED;

ADD17_PIN = UNRESERVED;

CLKUSR_PIN = UNRESERVED;

END;


Global Project Synthesis/Assignment Options Section Example

GLOBAL_PROJECT_SYNTHESIS_ASSIGNMENT_OPTIONS

BEGIN

DEVICE_FAMILY = FLEX10K;

OPTIMIZE = 5;

AUTO_IMPLEMENT_IN_EAB = OFF;

AUTO_OPEN_DRAIN_PINS = OFF;

ONE_HOT_STATE_MACHINE_ENCODING = OFF;

AUTO_REGISTER_PACKING = OFF;

MULTI_LEVEL_SYNTHESIS = OFF;

AUTO_GLOBAL_CLOCK = ON;

AUTO_GLOBAL_CLEAR = ON;

AUTO_GLOBAL_PRESET = ON;

AUTO_GLOBAL_OE = ON;

AUTO_IO_CELL_REGISTERS = ON;

STYLE = NORMAL;

END;


Global Project Parameters Section Example

GLOBAL_PROJECT_Parameters

BEGIN

LPM_WIDTH = 3;

LPM_WIDTHAD = 3;

END;


Logic Options Section Example

LOGIC_OPTIONS

BEGIN

|accel	:  XOR_SYNTHESIS = ON;

|accel	:  PARALLEL_EXPANDERS = OFF;

|accel	:  STYLE = FAST;

|dir1 	:	IMPLEMENT_IN_EAB = OFF;

|dir1 	:	INSERT_ADDITIONAL_LOGIC_CELL = ON;

|dir1 	:	HIERARCHICAL_SYNTHESIS = ON;

|dir1 	:	IO_CELL_REGISTER = OFF;

|dir1 	:	IGNORE_SOFT_BUFFERS = ON;

|dir1 	:	USE_LPM_FOR_AHDL_OPERATORS = ON;

|time1	:  SLOW_SLEW_RATE = OFF;

|time1	:  PARALLEL_EXPANDERS = ON;

|time1	:  MINIMIZATION = PART;

END;


Timing Requirements Assignments Section Example

TIMING_POINT

BEGIN

DEVICE_FOR_TIMING_SYNTHESIS = EPF10K10QC208;

MAINTAIN_STABLE_SYNTHESIS = ON;

TPD = null;

TCO = null;

TSU = null;

FREQUENCY = null;

CUT_ALL_BIDIR = ON;

CUT_ALL_CLEAR_PRESET = ON;

"|dir1"	:  TPD = 15ns;

"|at_altera"	:  CUT = ON;

"|time0"	:  FREQUENCY = 10ns;

END;


Clique Assignments Section Example

CLIQUE ticket

BEGIN

    "|ticket0"	:  clique;

    "|ticket1"	:  clique;

    "|ticket2"	:  clique;

    "|ticket3"	:  clique;

END;


Connected Pin Assignments Section Example

CONNECTED_PINS    connect

BEGIN

    "|accel"	:  INPUT_PIN;

    "|at_altera"	:  OUTPUT_PIN;

END;


Probe Assignments Section Example

PROBES

BEGIN

    "|dir0"	:  probe = direct;

    "|dir1"	:  probe = direct;

END;


Ignored Assignments Section Example

IGNORED_ASSIGNMENTS

BEGIN

    IGNORE_CLIQUE_ASSIGNMENTS = OFF;

    IGNORE_LOGIC_OPTION_ASSIGNMENTS = OFF;

    IGNORE_TIMING_ASSIGNMENTS = ON;

    IGNORE_CHIP_ASSIGNMENTS = OFF;

    IGNORE_PIN_ASSIGNMENTS = OFF;

    IGNORE_LC_ASSIGNMENTS = OFF;

    IGNORE_DEVICE_ASSIGNMENTS = OFF;

END ;


Compiler Processing Configuration Section Example

COMPILER_PROCESSING_CONFIGURATION

BEGIN

DESIGN_DOCTOR = ON;

DESIGN_DOCTOR_RULES = EPLD;

TIMING_SNF_EXTRACTOR = ON;

FUNCTIONAL_SNF_EXTRACTOR = OFF;

OPTIMIZE_TIMING_SNF = OFF;

LINKED_SNF_EXTRACTOR = OFF;

FITTER_SETTINGS = CUSTOM;

ROW_PINS_LCELL_INSERT = ON;

CARRY_OUT_PINS_LCELL_INSERT = OFF;

NORMAL_LCELL_INSERT = OFF;

LCELLS_PER_ROW_PERCENT = 100;

FAN_IN_PER_LCELL_PERCENT = 100;

EXP_PER_LCELL_PERCENT = 100;

ROW_PINS_PERCENT = 50;

RPT_FILE_EQUATIONS = ON;

RPT_FILE_HIERARCHY = ON;

RPT_FILE_LCELL_INTERCONNECT = ON;

RPT_FILE_USER_ASSIGNMENTS = ON;

GENERATE_AHDL_TDO_FILE = OFF;

SMART_RECOMPILE = ON;

END;


Compiler Interfaces Configuration Section Example

COMPILER_INTERFACES_CONFIGURATION

BEGIN

VHDL_USER_LIB_PHYSICAL_NAMES = "d:\maxw\code\libw";

VHDL_USER_LIB_LOGICAL_NAMES = libw;

EDIF_OUTPUT_DELAY_CONSTRUCTS = SDF_1.0;

NETLIST_OUTPUT_TIME_SCALE = .01ns;

VHDL_GENERATE_CONFIGURATION_DECLARATION = ON;

VHDL_NETLIST_WRITER = ON;

EDIF_OUTPUT_FORCE_0NS_DELAYS = ON;

EDIF_OUTPUT_INCLUDE_SPECIAL_PRIM = ON;

EDIF_OUTPUT_MAP_ILLEGAL_CHAR = ON;

EDIF_OUTPUT_EDC_FILE = "d:\max2work\chiptrip\.edc";

VERILOG_NETLIST_WRITER = ON;

EDIF_NETLIST_WRITER = ON;

EDIF_INPUT_SHOW_LMF_MAPPING_MESSAGES = ON;

EDIF_INPUT_LMF2 = "d:\max2work\chiptrip\.lmf";

EDIF_INPUT_LMF1 = "d:\max2work\chiptrip\.lmf";

VHDL_OUTPUT_DELAY_CONSTRUCTS = VHO_FILE;

VERILOG_OUTPUT_DELAY_CONSTRUCTS = VO_FILE;

EDIF_OUTPUT_VERSION = 200;

XNF_EMULATE_TRI_STATE_BUSES = INTERNAL_LOGIC;

XNF_TRANSLATE_INTERNAL_NODE_NAMES = ON;

XNF_GENERATE_AHDL_TDX_FILE = ON;

EDIF_INPUT_VCC = VCC;

EDIF_INPUT_GND = GND;

EDIF_OUTPUT_VCC = VCC;

EDIF_OUTPUT_GND = GND;

EDIF_INPUT_USE_LMF1 = OFF;

EDIF_INPUT_USE_LMF2 = OFF;

EDIF_OUTPUT_USE_EDC = OFF;

END;


Custom Design Doctor Rules Section Example

CUSTOM_DESIGN_DOCTOR_RULES

BEGIN

RIPPLE_CLOCKS = ON;

GATED_CLOCKS = ON;

MULTI_LEVEL_CLOCKS = ON;

MULTI_CLOCK_NETWORKS = ON;

STATIC_HAZARDS_BEFORE_SYNTHESIS = ON;

STATIC_HAZARDS_AFTER_SYNTHESIS = OFF;

PRESET_CLEAR_NETWORKS = ON;

ASYNCHRONOUS_INPUTS = ON;

DELAY_CHAINS = ON;

RACE_CONDITIONS = ON;

EXPANDER_NETWORKS = ON;

MASTER_RESET = OFF;

END;


Logic Synthesis Style Definition Section Example

DEFINE_LOGIC_SYNTHESIS_STYLE FAST.FLEX8000

BEGIN

CASCADE_CHAIN = AUTO;

CARRY_CHAIN = AUTO;

MINIMIZATION = FULL;

SLOW_SLEW_RATE = OFF;

XOR_SYNTHESIS = OFF;

TURBO_BIT = OFF;

PARALLEL_EXPANDERS = OFF;

EXPANDER_FACTORING = OFF;

SOFT_BUFFER_INSERTION = ON;

DECOMPOSE_GATES = ON;

REDUCE_LOGIC = ON;

DUPLICATE_LOGIC_EXTRACTION = OFF;

NOT_GATE_PUSH_BACK = ON;

REFACTORIZATION = OFF;

SUBFACTOR_EXTRACTION = OFF;

MULTI_LEVEL_FACTORING = ON;

RESYNTHESIZE_NETWORK = ON;

REGISTER_OPTIMIZATION = ON;

END;


Simulator Configuration Section Example

SIMULATOR_CONFIGURATION

BEGIN

USE_DEVICE = OFF;

SETUP_HOLD = OFF;

CHECK_OUTPUTS = ON;

OSCILLATION = OFF;

OSCILLATION_TIME = 0.0ns;

GLITCH = OFF;

GLITCH_TIME = 0.0ns;

SIMULATION_INPUT_FILE = chiptrip.scf;

START_TIME = 0.0ns;

END_TIME = 800.0ns;

END;


Timing Analyzer Configuration Section Example

TIMING_ANALYZER_CONFIGURATION

BEGIN

LIST_PATH_FREQUENCY = 10MHz;

LIST_PATH_COUNT = 10;

REGISTERED_PERFORMANCE_OPTIONS = NUMBER_OF_PATHS;

INCLUDE_PATHS_LESS_THAN_VALUE = 214.7483647ms;

INCLUDE_PATHS_LESS_THAN = OFF;

INCLUDE_PATHS_GREATER_THAN_VALUE = 0.0ns;

INCLUDE_PATHS_GREATER_THAN = OFF;

DELAY_MATRIX_OPTIONS = SHOW_ALL_PATHS;

CELL_WIDTH = 18;

LIST_ONLY_LONGEST_PATH = ON;

CUT_OFF_CLEAR_AND_PRESET_PATHS = ON;

CUT_OFF_IO_PIN_FEEDBACK = ON;

AUTO_RECALCULATE = OFF;

ANALYSIS_MODE = DELAY_MATRIX;

END;


NULL Keyword (Assignment & Configuration File)
NULL

The NULL keyword indicates an absence of information. A variable with a setting of NULL is ignored, i.e., it is treated as if it is not present in the ACF.


Source String (Assignment & Configuration File)
<source>

The optional <source> for any <statement> in an ACF consists of a text string, enclosed in brackets { }, that indicates the source of the assignment. MAX+PLUS II version 5.0 and higher automatically converts project assignment and configuration information generated by other industry-standard CAE tools, and by earlier versions of MAX+PLUS II, into the ACF format. The <source> information in each statement reflects the original source of the information. The <source> information then changes if you enter a change that affects the statement from within MAX+PLUS II.

MAX+PLUS II recognizes the following source text strings in an ACF:

{cadence}	{prb}

{data_io}	{synopsys}

{edif}	{tdf}

{ini}	{user}

{mentor}	{viewlogic}

For example, when you first open a project created with a pre-version 5.0 release of MAX+PLUS II, assignment and configuration information in the projects ACF is identified with {ini}, {prb}, and {tdf} source text strings, indicating that assignment information was converted from the projects old .prb file, <project name>.ini file , and top-level TDF (if any), respectively.


<setting>

In ACF statements of the format <name> : <keyword>=<setting>, the absence of =<setting> is always interpreted as =ON. For example, <name> :  CARRY_CHAIN is equivalent to <name> :  CARRY_CHAIN=ON.


<name>

Hierarchical node, bus, or pin name.

Legal characters for node, bus, and pin names are A to Z, a to z, 0 to 9, dash (-), and underscore (_). Node and pin names can also contain a slash (/).

Bus names can consist of decimal names (e.g., bus a[4..1]) or sequential names (e.g., a[3..0],dout[6..4],z3). (Bus names are written out as individual nodes.)

Names that contain the slash (/), dash (-), vertical bar (|), colon (:), and/or period (.) characters must be enclosed in double quotation marks (").


<chip name>

A user-defined name for a chip. A chip name can contain up to 32 name characters.


<device name>

A device name refers to an Altera programmable logic device. It can include device package and speed grade information.

Device names that contain the slash (/), dash (-), vertical bar (|), colon (:), and/or period (.) characters must be enclosed in double quotation marks (").

Refer to Devices & Adapters or to Device for information on device names.


<device column ID>

Device column IDs are comprised of digits.

Refer to Devices & Adapters for information on pin, logic cell, embedded cell, LAB, EAB, row, and column numbers for each Altera device.


<device pin ID>

Device pin IDs are comprised of numeric digits or a combination of alphabet letters and digits.

Refer to Devices & Adapters for information on pin, logic cell, embedded cell, LAB, EAB, row, and column numbers for each Altera device.


<device row ID>

Device row IDs are comprised of alphabet letters.

Refer to Devices & Adapters for information on pin, logic cell, embedded cell, LAB, EAB, row, and column numbers for each Altera device.


<device I/O cell ID>

The device I/O cell ID is the number of the pin associated with the I/O cell. The pin number may consist of digits or both digits and letters.

Refer to Devices & Adapters for information on pin, logic cell, embedded cell, LAB, EAB, row, and column numbers for each Altera device.


<device logic cell ID>

The device logic cell ID is the number of the logic cell. In FLEX 8000, FLEX 8000M, MAX 9000, and FLEX 10K devices, the logic cell ID consists of a number from 1 to 8, an underscore, and the row letter and column number of the LAB. In Classic, MAX 5000/EPS464, MAX 7000, and MAX 7000E devices, the logic cell ID may consist of digits or both digits and letters.

Refer to Devices & Adapters for information on pin, logic cell, embedded cell, LAB, EAB, row, and column numbers for each Altera device.


<device LAB ID>

Device LAB IDs are comprised of letters or both letters and digits.

Refer to Devices & Adapters for information on pin, logic cell, embedded cell, LAB, EAB, row, and column numbers for each Altera device.


<device embedded cell ID>

The device embedded cell ID is the number of the pin associated with the embedded cell. The pin number may consist of digits or both digits and letters.

Refer to Devices & Adapters for information on pin, logic cell, embedded cell, LAB, EAB, row, and column numbers for each Altera device.


<device EAB ID>

Device EAB IDs are comprised of letters or both letters and digits.

Refer to Devices & Adapters for information on pin, logic cell, embedded cell, LAB, EAB, row, and column numbers for each Altera device.


<family name>

Legal Settings:

FLEX8000 | MAX7000 | MAX5000 | CLASSIC


<device count>

You can limit the number of a particular device the Compiler can use by including a positive integer after the device name in the AUTO_DEVICE statement.

Legal Settings:

<number> | NULL

The device name and integer must be separated by white space and enclosed in double quotation marks (").


<decimal number>

A positive, non-zero number.


<style name>

A user-defined name for a logic synthesis style. A style name may contain up to 32 name characters.


<number>

A whole, positive, non-zero number.


<clique name>

A user-defined name for a clique. A clique name may contain up to 32 name characters.


<connected pin group name>

A user-defined name for a connected pin group. A connected pin group name may contain up to 32 name characters.


<probe name>

A user-defined name for a probe. A probe name may contain up to 32 name characters.


<filename>

The name of a design file, ancillary file or other file without the extension. A single filename can contain up to 32 name characters, plus a 3-character filename extension. A full pathname plus filename and extension can contain up to 128 characters.

Legal characters for filenames are A to Z, a to z, 0 to 9, dash (-), and underscore (_) .


<symbolic name>

A user-defined name. A symbolic name can contain up to 32 name characters.


<device family>

Legal Settings:

FLEX10K | MAX9000 | FLEX8000 | MAX7000 | MAX5000 | CLASSIC


<parameter name>

An Altera predefined or user-specified name for a parameter. A parameter name can contain up to 32 name characters.


<parameter value>

A parameter value can consist of a decimal, binary, octal, or hexadecimal number; a quoted or unquoted string (e.g., "unsigned"); or a value of <none>.


Summary Table of ACF Keywords, Settings & Usage

Sections in the Assignment & Configuration File (.acf) have the following format:

<statement>

BEGIN

{ <statement> [<source>] ; }

END ;

The <statements> in ACF sections can take one of the following BNF formats. The letter code corresponding to each format appears in the Usage column of the table below.

Code:	Format:

A	<keyword>=<setting>

B	<name> : <keyword>=<setting>

C	<keyword> <name>

D	<keyword>

See also:

ACF Format

Comments & Documentation

Keyword:	Settings:	Usage:	Command/Dialog Box/	ACF Section:

On-Screen Option:

ADD0_TO_ADD12_PIN	UNRESERVED | RESERVED_TRI_STATED 	A	FLEX 8000 Global Project Device Options	Global Device Options Section

| RESERVED_DRIVES_OUT

ADD0_TO_ADD12_PIN	UNRESERVED | RESERVED_TRI_STATED	A	FLEX 8000 Individual Device Options	Physical Chip Assignments Section

| RESERVED_DRIVES_OUT | DEFAULT | NULL

ADD13_PIN	UNRESERVED | RESERVED_TRI_STATED 	A	FLEX 8000 Global Project Device Options	Global Device Options Section

| RESERVED_DRIVES_OUT

ADD13_PIN	UNRESERVED | RESERVED_TRI_STATED	A	FLEX 8000 Individual Device Options	Physical Chip Assignments Section

| RESERVED_DRIVES_OUT | DEFAULT | NULL

ADD14_PIN	UNRESERVED | RESERVED_TRI_STATED 	A	FLEX 8000 Global Project Device Options	Global Device Options Section

| RESERVED_DRIVES_OUT

ADD14_PIN	UNRESERVED | RESERVED_TRI_STATED	A	FLEX 8000 Individual Device Options	Physical Chip Assignments Section

| RESERVED_DRIVES_OUT | DEFAULT | NULL

ADD15_PIN	UNRESERVED | RESERVED_TRI_STATED 	A	FLEX 8000 Global Project Device Options	Global Device Options Section

| RESERVED_DRIVES_OUT

ADD15_PIN	UNRESERVED | RESERVED_TRI_STATED	A	FLEX 8000 Individual Device Options	Physical Chip Assignments Section

| RESERVED_DRIVES_OUT | DEFAULT | NULL

ADD16_PIN	UNRESERVED | RESERVED_TRI_STATED 	A	FLEX 8000 Global Project Device Options	Global Device Options Section

| RESERVED_DRIVES_OUT

ADD16_PIN	UNRESERVED | RESERVED_TRI_STATED	A	FLEX 8000 Individual Device Options	Physical Chip Assignments Section

| RESERVED_DRIVES_OUT | DEFAULT | NULL

ADD17_PIN	UNRESERVED | RESERVED_TRI_STATED 	A	FLEX 8000 Global Project Device Options	Global Device Options Section

| RESERVED_DRIVES_OUT

ADD17_PIN	UNRESERVED | RESERVED_TRI_STATED	A	FLEX 8000 Individual Device Options	Physical Chip Assignments Section

| RESERVED_DRIVES_OUT | DEFAULT | NULL

ANALYSIS_MODE	DELAY_MATRIX	A	Delay Matrix	Timing Analyzer Configuration Section

| SETUP_HOLD_MATRIX	Setup/Hold Matrix

| REGISTERED_PERFORMANCE	Registered Performance

ASK_BEFORE_ADDING_EXTRA_DEVICES	ON | OFF | NULL	A	Auto Device Selection	Auto Device Choices Section

ASYNCHRONOUS_INPUTS	ON | OFF | NULL	A	Design Doctor Settings	Custom Design Doctor Rules Section

AUTO_DEVICE	<device name> | <family name> 	A	Auto Device Selection	Auto Device Choices Section

| "<device name> <device count>" | NULL

AUTO_GLOBAL_CLEAR	ON | OFF	A	Global Project Logic Synthesis 	Global Project Synthesis/Assignment Options Section

AUTO_GLOBAL_CLOCK	ON | OFF	A	Global Project Logic Synthesis 	Global Project Synthesis/Assignment Options Section

AUTO_GLOBAL_OE	ON | OFF	A	Global Project Logic Synthesis 	Global Project Synthesis/Assignment Options Section

AUTO_GLOBAL_PRESET	ON | OFF	A	Global Project Logic Synthesis 	Global Project Synthesis/Assignment Options Section

AUTO_IMPLEMENT_IN_EAB	ON | OFF	A	Global Project Logic Synthesis 	Global Project Synthesis/Assignment Options Section

AUTO_IO_CELL_REGISTERS	ON | OFF	A	Global Project Logic Synthesis 	Global Project Synthesis/Assignment Options Section

AUTO_OPEN_DRAIN_PINS	ON | OFF	A	Global Project Logic Synthesis 	Global Project Synthesis/Assignment Options Section

AUTO_RECALCULATE	ON | OFF | NULL	A	Auto-Recalculate	Timing Analyzer Configuration Section

AUTO_REGISTER_PACKING	ON | OFF	A	Global Project Logic Synthesis 	Global Project Synthesis/Assignment Options Section

AUTO_RESTART	ON | OFF	A	FLEX 8000 Global Project Device Options	Global Device Options Section

FLEX 10K Global Project Device Options

AUTO_RESTART	ON | OFF | DEFAULT | NULL	A	FLEX 8000 Individual Device Options	Physical Chip Assignments Section

FLEX 10K Individual Device Options

BEST_CLIQUE	<clique name> | "<clique name>"	C	Clique	Clique Assignments Section

BIDIR_PIN	<device pin ID> | COL_<device column ID> | COL_ANY 	B	Pin/Location/Chip	Physical Chip Assignments Section

| ROW_<device row ID> | ROW_ANY | ANY | NULL

BIDIR_PIN 	ON | OFF | NULL	B	Connected Pins	Connected Pin Assignments Section

CARRY_CHAIN	AUTO | IGNORE | MANUAL | DEFAULT | NULL	A	Define Synthesis Style	Logic Synthesis Style Definition

CARRY_CHAIN	AUTO | IGNORE | MANUAL | DEFAULT | NULL	B	Individual Logic Options	Logic Options Section

CARRY_CHAIN_LENGTH	<number> | NULL	A	Define Synthesis Style	Logic Synthesis Style Definition

CARRY_OUT_PINS_LCELL_INSERT	ON | OFF | NULL	A	Fitter Settings	Compiler Processing Configuration Section

CASCADE_CHAIN	AUTO | IGNORE | MANUAL | DEFAULT | NULL	A	Define Synthesis Style	Logic Synthesis Style Definition

CASCADE_CHAIN	AUTO | IGNORE | MANUAL | DEFAULT | NULL	B	Individual Logic Options	Logic Options Section

CASCADE_CHAIN_LENGTH	<number> | NULL	A	Define Synthesis Style	Logic Synthesis Style Definition

CELL_WIDTH	<decimal number>	A	Cell Width	Timing Analyzer Configuration Section

CHECK_OUTPUTS	ON | OFF | NULL	A	Check Outputs	Simulator Configuration Section

CHIP	<chip name>	C	Device, Pin/Location/Chip	Physical Chip Assignments Section

CHIP_CLIQUE	<clique name> | "<clique name>"	C	Clique	Clique Assignments Section

CLIQUE	ON | OFF | NULL	B	Clique	Clique Assignments Section

CLKUSR_PIN	UNRESERVED | RESERVED_TRI_STATED 	A	FLEX 8000 Global Project Device Options	Global Device Options Section

| RESERVED_DRIVES_OUT

CLKUSR_PIN	UNRESERVED | RESERVED_TRI_STATED 	A	FLEX 8000 Individual Device Options	Physical Chip Assignments Section

| RESERVED_DRIVES_OUT | DEFAULT | NULL	FLEX 10K Individual Device Options

COMPILER_INTERFACES_CONFIGURATION	n/a	D	n/a	Compiler Interfaces Configuration Section

COMPILER_PROCESSING_CONFIGURATION	n/a	D	n/a	Compiler Processing Configuration Section

CONFIG_SCHEME	ACTIVE_SERIAL | ACTIVE_PARALLEL_UP 	A	FLEX 8000 Global Project Device Options	Global Device Options Section

| ACTIVE_PARALLEL_DOWN | PASSIVE_SERIAL

| PASSIVE_PARALLEL_SYNCHRONOUS

| PASSIVE_PARALLEL_ASYNCHRONOUS

CONFIG_SCHEME	ACTIVE_SERIAL | ACTIVE_PARALLEL_UP 	A	FLEX 8000 Individual Device Options	Physical Chip Assignments Section

| ACTIVE_PARALLEL_DOWN | PASSIVE_SERIAL

| PASSIVE_PARALLEL_SYNCHRONOUS

| PASSIVE_PARALLEL_ASYNCHRONOUS

| DEFAULT | NULL

CONFIG_SCHEME_10K	PASSIVE_SERIAL 	A	FLEX 10K Global Project Device Options	Global Device Options Section

| PASSIVE_PARALLEL_SYNCHRONOUS

| PASSIVE_PARALLEL_ASYNCHRONOUS

CONFIG_SCHEME_10K	PASSIVE_SERIAL 	A	FLEX 10K Individual Device Options	Physical Chip Assignments Section

| PASSIVE_PARALLEL_SYNCHRONOUS

| PASSIVE_PARALLEL_ASYNCHRONOUS

| DEFAULT | NULL

CONNECTED_PINS	<connected pin group name> 	C	Connected Pins	Connected Pin Assignments Section

| "<connected pin group name>"

CUSTOM_DESIGN_DOCTOR_RULES	n/a	D	n/a	Custom Design Doctor Rules Section

CUT	ON | OFF | NULL	B	Timing Requirements	Timing Requirement Assignments Section

CUT_ALL_BIDIR	ON | OFF | NULL	A	Global Project Timing Requirements	Timing Requirement Assignments Section

CUT_ALL_CLEAR_PRESET	ON | OFF | NULL	A	Global Project Timing Requirements	Timing Requirement Assignments Section

CUT_OFF_CLEAR_AND_PRESET_PATHS	ON | OFF | NULL	A	Cut Off Clear & Preset Paths	Timing Analyzer Configuration Section

Cut_Off_I/O_Pin_Feedback	ON | OFF | NULL	A	Cut Off I/O Pin Feedback	Timing Analyzer Configuration Section

DATA0_PIN	UNRESERVED | RESERVED_TRI_STATED 	A	FLEX 8000 Global Project Device Options	Global Device Options Section

| RESERVED_DRIVES_OUT

DATA0_PIN	UNRESERVED | RESERVED_TRI_STATED 	A	FLEX 8000 Individual Device Options	Physical Chip Assignments Section

| RESERVED_DRIVES_OUT | DEFAULT | NULL

DATA1_TO_DATA7_PIN	UNRESERVED | RESERVED_TRI_STATED 	A	FLEX 8000 Global Project Device Options	Global Device Options Section

| RESERVED_DRIVES_OUT	FLEX 10K Global Project Device Options

DATA1_TO_DATA7_PIN	UNRESERVED | RESERVED_TRI_STATED	A	FLEX 8000 Individual Device Options	Physical Chip Assignments Section

| RESERVED_DRIVES_OUT | DEFAULT | NULL	FLEX 10K Individual Device Options

DECOMPOSE_GATES	ON | OFF | DEFAULT | NULL	A	Advanced Options	Logic Synthesis Style Definition

DECOMPOSE_GATES	ON | OFF | DEFAULT | NULL	B	Advanced Options	Logic Options Section

DEFAULT_DEVICES	n/a	D	n/a	Auto Device Choices Section

DEFINE_LOGIC_SYNTHESIS_STYLE	<style name>.<device family>	C	Define Synthesis Style	Logic Synthesis Style Definition

DELAY_CHAINS	ON | OFF | NULL	A	Design Doctor Settings	Custom Design Doctor Rules Section

DELAY_MATRIX_OPTIONS	SHOW_ALL_PATHS | SHOW_ONLY_LONGEST_PATHS	A	Time Restrictions	Timing Analyzer Configuration Section

| SHOW_ONLY_SHORTEST_PATHS

DESIGN_DOCTOR	ON | OFF | NULL	A	Design Doctor	Compiler Processing Configuration Section

DESIGN_DOCTOR_RULES 	EPLD | FLEX | MPLD | CUSTOM | NULL	A	Design Doctor Settings	Compiler Processing Configuration Section

DEVICE 	<device name> | "<device name>" | AUTO | NULL	A	Device	Physical Chip Assignments Section

DEVICE_FOR_TIMING_SYNTHESIS	<device name> | "<device name>" | AUTO | NULL	A	n/a	Timing Requirement Assignments Section

DISABLE_TIME_OUT	ON | OFF	A	FLEX 8000 Global Project Device Options	Global Device Options Section

DISABLE_TIME_OUT	ON | OFF | DEFAULT | NULL	A	FLEX 8000 Individual Device Options	Physical Chip Assignments Section

DUPLICATE_LOGIC_EXTRACTION	ON | OFF | DEFAULT | NULL	A	Advanced Options	Logic Synthesis Style Definition

DUPLICATE_LOGIC_EXTRACTION	ON | OFF | DEFAULT | NULL	B	Advanced Options	Logic Options Section

EDIF_INPUT_GND	<symbolic name> | NULL	A	EDIF Netlist Reader Settings	Compiler Interfaces Configuration Section

EDIF_INPUT_LMF1	<filename> | NULL	A	EDIF Netlist Reader Settings	Compiler Interfaces Configuration Section

EDIF_INPUT_LMF2	<filename> | NULL	A	EDIF Netlist Reader Settings	Compiler Interfaces Configuration Section

EDIF_INPUT_SHOW_LMF_MAPPING_MESSAGES	ON | OFF | NULL	A	EDIF Netlist Reader Settings	Compiler Interfaces Configuration Section

EDIF_INPUT_USE_LMF1	ON | OFF | NULL	A	EDIF Netlist Reader Settings	Compiler Interfaces Configuration Section

EDIF_INPUT_USE_LMF2	ON | OFF | NULL	A	EDIF Netlist Reader Settings	Compiler Interfaces Configuration Section

EDIF_INPUT_VCC	<symbolic name> | NULL	A	EDIF Netlist Reader Settings	Compiler Interfaces Configuration Section

EDIF_NETLIST_WRITER	ON | OFF | NULL	A	EDIF Netlist Writer	Compiler Interfaces Configuration Section

EDIF_OUTPUT_DELAY_CONSTRUCTS	PROPERTY | PORT_PATHDELAYS | NULL	A	EDIF Netlist Writer Settings	Compiler Interfaces Configuration Section

EDIF_OUTPUT_EDC_FILE	<filename> | NULL	A	EDIF Netlist Writer Settings	Compiler Interfaces Configuration Section

EDIF_OUTPUT_FORCE_0NS_DELAYS	ON | OFF | NULL	A	EDIF Netlist Writer Settings	Compiler Interfaces Configuration Section

EDIF_OUTPUT_GND	<symbolic name> | NULL	A	EDIF Netlist Writer Settings	Compiler Interfaces Configuration Section

EDIF_OUTPUT_INCLUDE_SPECIAL_PRIM	ON | OFF | NULL	A	EDIF Netlist Writer Settings	Compiler Interfaces Configuration Section

EDIF_OUTPUT_MAP_ILLEGAL_CHAR	ON | OFF | NULL	A	EDIF Netlist Writer Settings	Compiler Interfaces Configuration Section

EDIF_OUTPUT_USE_EDC_FILE	ON | OFF | NULL	A	EDIF Netlist Writer	Compiler Interfaces Configuration Section

EDIF_OUTPUT_VCC	<symbolic name> | NULL	A	EDIF Netlist Writer Settings	Compiler Interfaces Configuration Section

EDIF_OUTPUT_VERSION	200 | 290 | NULL	A	EDIF Netlist Writer Settings	Compiler Interfaces Configuration Section

ENABLE_CHIP_WIDE_OE	ON | OFF 	A	FLEX 10K Global Project Device Options	Global Device Options Section

ENABLE_CHIP_WIDE_OE	ON | OFF | DEFAULT | NULL	A	FLEX 10K Individual Device Options	Physical Chip Assignments Section

ENABLE_CHIP_WIDE_RESET	ON | OFF 	A	FLEX 10K Global Project Device Options	Global Device Options Section

ENABLE_CHIP_WIDE_RESET	ON | OFF | DEFAULT | NULL	A	FLEX 10K Individual Device Options	Physical Chip Assignments Section

ENABLE_DCLK_OUTPUT	ON | OFF	A	FLEX 8000 Global Project Device Options	Global Device Options Section

ENABLE_DCLK_OUTPUT	ON | OFF | DEFAULT | NULL	A	FLEX 8000 Individual Device Options	Physical Chip Assignments Section

ENABLE_INIT_DONE_OUTPUT	ON | OFF 	A	FLEX 10K Global Project Device Options	Global Device Options Section

ENABLE_INIT_DONE_OUTPUT	ON | OFF | DEFAULT | NULL	A	FLEX 10K Individual Device Options	Physical Chip Assignments Section

ENABLE_JTAG	ON | OFF	A	FLEX 8000 Global Project Device Options	Global Device Options Section

ENABLE_JTAG	ON | OFF | DEFAULT | NULL	A	FLEX 8000 Individual Device Options	Physical Chip Assignments Section

END_TIME	<decimal number>[<time unit>]	A	End Time	Simulator Configuration Section

EXP_PER_LCELL_PERCENT	<number> | NULL	A	Fitter Settings	Compiler Processing Configuration Section

EXPANDER_NETWORKS	ON | OFF | NULL	A	Design Doctor Settings	Custom Design Doctor Rules Section

FAN_IN_PER_LCELL_PERCENT	<number> | NULL	A	Fitter Settings	Compiler Processing Configuration Section

FITTER_SETTINGS	NORMAL | ADVANCED | CUSTOM | NULL	A	Fitter Settings 	Compiler Processing Configuration Section

FREQUENCY 	<decimal number>[<time unit>] | OFF | NULL	A, B	Global Project Timing Requirements	Timing Requirement Assignments Section

Timing Requirements

FUNCTIONAL_SNF_EXTRACTOR	ON | OFF | NULL	A	Functional SNF Extractor	Compiler Processing Configuration Section

GATED_CLOCKS	ON | OFF | NULL	A	Design Doctor Settings	Custom Design Doctor Rules Section

GENERATE_AHDL_TDO_FILE	ON | OFF | NULL	A	Generate AHDL TDO File	Compiler Processing Configuration Section

GENERATE_JEDEC_FILE	ON | OFF | NULL	A	Generate JEDEC File	Compiler Processing Configuration Section

GLITCH	ON | OFF | NULL	A	Glitch	Simulator Configuration Section

GLITCH_TIME 	<decimal number>[<time unit>] 	A	Glitch	Simulator Configuration Section

GLOBAL_PROJECT_DEVICE_OPTIONS	n/a	D	n/a	Global Device Options Section

GLOBAL_PROJECT_PARAMETERS	n/a	D	n/a	Global Project Parameters Section

GLOBAL_PROJECT_SYNTHESIS_ASSIGNMENT_OPTIONS	n/a	D	n/a	Global Project Synthesis/Assignment Options Section

HIERARCHICAL_SYNTHESIS	ON | OFF | DEFAULT | NULL	B	Individual Logic Options	Logic Options Section

IGNORED_ASSIGNMENTS	n/a	D	n/a	Ignored Assignments Section

IGNORE_CHIP_ASSIGNMENTS	ON | OFF | NULL	A	Ignore Project Assignments	Ignored Assignments Section

IGNORE_CLIQUE_ASSIGNMENTS	ON | OFF | NULL	A	Ignore Project Assignments	Ignored Assignments Section

IGNORE_DEVICE_ASSIGNMENTS	ON | OFF | NULL	A	Ignore Project Assignments	Ignored Assignments Section

IGNORE_LC_ASSIGNMENTS	ON | OFF | NULL	A	Ignore Project Assignments	Ignored Assignments Section

IGNORE_LOGIC_OPTION_ASSIGNMENTS	ON | OFF | NULL	A	Ignore Project Assignments	Ignored Assignments Section

IGNORE_PIN_ASSIGNMENTS	ON | OFF | NULL	A	Ignore Project Assignments	Ignored Assignments Section

Ignore_SOFT_Buffers	ON | OFF | DEFAULT | NULL	A	Define Synthesis Style	Logic Synthesis Style Definition

Ignore_SOFT_Buffers	ON | OFF | DEFAULT | NULL	B	Individual Logic Options	Logic Options Section

IGNORE_TIMING_ASSIGNMENTS	ON | OFF | NULL	A	Ignore Project Assignments	Ignored Assignments Section

IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL	ON | OFF | DEFAULT | NULL	B	Individual Logic Options	Logic Options Section

Implement_in_EAB	ON | OFF | DEFAULT | NULL	B	Individual Logic Options	Logic Options Section

INCLUDE_PATHS_GREATER_THAN	ON | OFF | NULL	A	Time Restrictions	Timing Analyzer Configuration Section

INCLUDE_PATHS_GREATER_THAN_VALUE	<decimal number>[<time unit>] 	A	Time Restrictions	Timing Analyzer Configuration Section

INCLUDE_PATHS_LESS_THAN	ON | OFF | NULL	A	Time Restrictions	Timing Analyzer Configuration Section

INCLUDE_PATHS_LESS_THAN_VALUE	<decimal number>[<time unit>] 	A	Time Restrictions	Timing Analyzer Configuration Section

INPUT_PIN	<device pin ID> | COL_<device column ID> | COL_ANY	B	Pin/Location/Chip	Physical Chip Assignments Section

| ROW_<device row ID> | ROW_ANY | ANY | NULL

INPUT_PIN	ON | OFF | NULL	B	Connected Pins	Connected Pin Assignments Section

INSERT_ADDITIONAL_LOGIC_CELL	ON | OFF | DEFAULT | NULL	B	Individual Logic Options	Logic Options Section

IO_CELL_REGISTER	ON | OFF | DEFAULT | NULL	B	Individual Logic Options	Logic Options Section

JTAG_USER_CODE	<1-byte hexadecimal number>	A	FLEX 10K Global Project Device Options	Global Device Options Section

JTAG_USER_CODE	<1-byte hexadecimal number>	A	FLEX 10K Individual Device Options	Physical Chip Assignments Section

LAB_CLIQUE	<clique name> | "<clique name>"	C	Clique	Clique Assignments Section

LCELLS_PER_ROW_PERCENT	<number> | NULL	A	Fitter Settings	Compiler Processing Configuration Section

LINKED_SNF_EXTRACTOR	ON | OFF | NULL	A	Linked SNF Extractor	Compiler Processing Configuration Section

LIST_PATH_COUNT	<decimal number>	A	Time Restrictions	Timing Analyzer Configuration Section

LIST_PATH_FREQUENCY	<decimal number>[<time unit>] 	A	Time Restrictions	Timing Analyzer Configuration Section

LOCATION	LC<device logic cell ID> | IOC<device I/O cell ID> 	B	Pin/Location/Chip	Physical Chip Assignments Section

| EC_<device embedded cell ID> | LAB_<device LAB ID>

| EAB_<device EAB ID> | COL_<device column ID>

| COL_ANY | ROW_<device row ID> | ROW_ANY | ANY | NULL

LOGIC_OPTIONS	n/a	D	n/a	Logic Options Section

MAINTAIN_STABLE_SYNTHESIS	ON | OFF | NULL	A	Device	Timing Requirement Assignments Section

MASTER_RESET	ON | OFF | NULL	A	Design Doctor Settings	Custom Design Doctor Rules Section

MINIMIZATION	FULL | PARTIAL | DEFAULT | NULL	A	Define Synthesis Style	Logic Synthesis Style Definition

MINIMIZATION	FULL | PARTIAL | DEFAULT | NULL	B	Individual Logic Options	Logic Options Section

MULTI_CLOCK_NETWORKS	ON | OFF | NULL	A	Design Doctor Settings	Custom Design Doctor Rules Section

MULTI_LEVEL_CLOCKS	ON | OFF | NULL	A	Design Doctor Settings	Custom Design Doctor Rules Section

MULTI_LEVEL_FACTORING	ON | OFF | DEFAULT | NULL	A	Advanced Options	Logic Synthesis Style Definition

MULTI_LEVEL_FACTORING	ON | OFF | DEFAULT | NULL	B	Advanced Options	Logic Options Section

MULTI_LEVEL_SYNTHESIS	ON | OFF	A	Global Project Logic Synthesis 	Global Project Synthesis/Assignment Options Section

NETLIST_OUTPUT_TIME_SCALE	<decimal number>[<time unit>] | NULL	A	Verilog Netlist Writer Settings	Compiler Interfaces Configuration Section

NORMAL_LCELL_INSERT	ON | OFF | NULL	A	Fitter Settings	Compiler Processing Configuration Section

NOT_GATE_PUSH_BACK	ON | OFF | DEFAULT | NULL	A	Advanced Options	Logic Synthesis Style Definition

NOT_GATE_PUSH_BACK	ON | OFF | DEFAULT | NULL	B	Advanced Options	Logic Options Section

nWS_nRS_nCS_CS_PIN	UNRESERVED | RESERVED_TRI_STATED 	A	FLEX 8000 Global Project Device Options	Global Device Options Section

| RESERVED_DRIVES_OUT	FLEX 10K Global Project Device Options

nWS_nRS_nCS_CS_PIN	UNRESERVED | RESERVED_TRI_STATED 	A	FLEX 8000 Individual Device Options	Physical Chip Assignments Section

| RESERVED_DRIVES_OUT | DEFAULT | NULL	FLEX 10K Individual Device Options

ONE_HOT_STATE_MACHINE_ENCODING	ON | OFF	A	Global Project Logic Synthesis 	Global Project Synthesis/Assignment Options Section

OPTIMIZE	AREA | DELAY | DEFAULT 	A	Global Project Logic Synthesis	Global Project Synthesis/Assignment Options Section

OPTIMIZE_TIMING_SNF	ON | OFF | NULL	A	Optimize Timing SNF	Compiler Processing Configuration Section

OSCILLATION	ON | OFF | NULL	A	Oscillation	Simulator Configuration Section

OSCILLATION_TIME 	<decimal number>[<time unit>] 	A	Oscillation	Simulator Configuration Section

OTHER_CONFIGURATION	n/a	D	n/a	Other Configuration Section

OUTPUT_PIN	<device pin ID> | COL_<device column ID> | COL_ANY 	B	Pin/Location/Chip	Physical Chip Assignments Section

| ROW_<device row ID> | ROW_ANY | ANY | NULL

OUTPUT_PIN	ON | OFF | NULL	B	Connected Pins	Connected Pin Assignments Section

PARALLEL_EXPANDERS	ON | OFF | DEFAULT | NULL	A	Define Synthesis Style	Logic Synthesis Style Definition

PARALLEL_EXPANDERS	ON | OFF | DEFAULT | NULL	B	Individual Logic Options	Logic Options Section

PIN	<device pin ID> | COL_<device column ID> | COL_ANY 	B	Pin/Location/Chip	Physical Chip Assignments Section

| ROW_<device row ID> | ROW_ANY | ANY | NULL

PIN	ON | OFF | NULL	B	Connected Pins	Connected Pin Assignments Section

PRESERVE_ALL_NODE_NAME_SYNONYMS	ON | OFF | NULL	A	Preserve All Node Name Synonyms	Compiler Processing Configuration Section

PRESET_CLEAR_NETWORKS	ON | OFF | NULL	A	Design Doctor Settings	Custom Design Doctor Rules Section

PROBE	<probe name> | "<probe name>" | NULL	B	Probe	Probe Assignments Section

PROBES	n/a	D	n/a	Probe Assignments Section

RACE_CONDITIONS	ON | OFF | NULL	A	Design Doctor Settings	Custom Design Doctor Rules Section

RDCLK_PIN	UNRESERVED | RESERVED_TRI_STATED 	A	FLEX 8000 Global Project Device Options	Global Device Options Section

| RESERVED_DRIVES_OUT

RDCLK_PIN	UNRESERVED | RESERVED_TRI_STATED	A	FLEX 8000 Individual Device Options	Physical Chip Assignments Section

| RESERVED_DRIVES_OUT | DEFAULT | NULL

RDYnBUSY_PIN	UNRESERVED | RESERVED_TRI_STATED 	A	FLEX 8000 Global Project Device Options	Global Device Options Section

| RESERVED_DRIVES_OUT	FLEX 10K Global Project Device Options

RDYnBUSY_PIN	UNRESERVED | RESERVED_TRI_STATED 	A	FLEX 8000 Individual Device Options	Physical Chip Assignments Section

| RESERVED_DRIVES_OUT | DEFAULT | NULL	FLEX 10K Individual Device Options

REDUCE_LOGIC	ON | OFF | DEFAULT | NULL	A	Advanced Options	Logic Synthesis Style Definition

REDUCE_LOGIC	ON | OFF | DEFAULT | NULL	B	Advanced Options	Logic Options Section

REFACTORIZATION	ON | OFF | DEFAULT | NULL	A	Advanced Options	Logic Synthesis Style Definition

REFACTORIZATION	ON | OFF | DEFAULT | NULL	B	Advanced Options	Logic Options Section

REGISTER_OPTIMIZATION	ON | OFF | DEFAULT | NULL	A	Advanced Options	Logic Synthesis Style Definition

REGISTER_OPTIMIZATION	ON | OFF | DEFAULT | NULL	B	Advanced Options	Logic Options Section

REGISTERED_PERFORMANCE_OPTIONS	NUMBER_OF_PATHS | FREQUENCY_OF_PATHS	A	Time Restrictions	Timing Analyzer Configuration Section

RELEASE_CLEARS	ON | OFF	A	FLEX 8000 Global Project Device Options	Global Device Options Section

FLEX 10K Global Project Device Options

RELEASE_CLEARS	ON | OFF | DEFAULT | NULL	A	FLEX 8000 Individual Device Options	Physical Chip Assignments Section

FLEX 10K Individual Device Options

RESERVED_LCELLS_PERCENT	<number> 	A	Global Project Device Options	Global Device Options Section

RESERVED_PINS_PERCENT	<number> 	A	Global Project Device Options	Global Device Options Section

RESYNTHESIZE_NETWORK	ON | OFF | DEFAULT | NULL	A	Advanced Options	Logic Synthesis Style Definition

RESYNTHESIZE_NETWORK	ON | OFF | DEFAULT | NULL	B	Advanced Options	Logic Options Section

RIPPLE_CLOCKS	ON | OFF | NULL	A	Design Doctor Settings	Custom Design Doctor Rules Section

ROW_CLIQUE	<clique name> | "<clique name>"	C	Clique	Clique Assignments Section

ROW_PINS_LCELL_INSERT	ON | OFF | NULL	A	Fitter Settings	Compiler Processing Configuration Section

ROW_PINS_PERCENT	<number> | NULL	A	Fitter Settings	Compiler Processing Configuration Section

RPT_FILE_EQUATIONS	ON | OFF | NULL	A	Report File Settings	Compiler Processing Configuration Section

RPT_FILE_HIERARCHY	ON | OFF | NULL	A	Report File Settings	Compiler Processing Configuration Section

RPT_FILE_LCELL_INTERCONNECT	ON | OFF | NULL	A	Report File Settings	Compiler Processing Configuration Section

RPT_FILE_USER_ASSIGNMENTS	ON | OFF | NULL	A	Report File Settings	Compiler Processing Configuration Section

SDOUT_PIN	UNRESERVED | RESERVED_TRI_STATED 	A	FLEX 8000 Global Project Device Options	Global Device Options Section

| RESERVED_DRIVES_OUT

SDOUT_PIN	UNRESERVED | RESERVED_TRI_STATED 	A	FLEX 8000 Individual Device Options	Physical Chip Assignments Section

| RESERVED_DRIVES_OUT | DEFAULT | NULL

SECURITY_BIT	ON | OFF	A	Global Project Device Options	Global Device Options Section

SECURITY_BIT	ON | OFF | DEFAULT | NULL	A	Classic & MAX Individual Device Options	Physical Chip Assignments Section

SETUP_HOLD	ON | OFF | NULL	A	Setup/Hold	Simulator Configuration Section

SIMULATOR_CONFIGURATION	n/a	D	n/a	Simulator Configuration Section

SIMULATION_INPUT_FILE	<filename> | NULL	A	Inputs/Outputs (Simulator)	Simulator Configuration Section

SLOW_SLEW_RATE	ON | OFF | DEFAULT | NULL	A	Define Synthesis Style	Logic Synthesis Style Definition

SLOW_SLEW_RATE	ON | OFF | DEFAULT | NULL	B	Individual Logic Options	Logic Options Section

SMART_RECOMPILE	ON | OFF | NULL	A	Smart Recompile	Compiler Processing Configuration Section

SOFT_BUFFER_INSERTION	ON | OFF | DEFAULT | NULL	A	Advanced Options	Logic Synthesis Style Definition

SOFT_BUFFER_INSERTION	ON | OFF | DEFAULT | NULL	B	Advanced Options	Logic Options Section

START_TIME	 <decimal number>[<time unit>] 	A	Start Time	Simulator Configuration Section

STATIC_HAZARDS_AFTER_SYNTHESIS	ON | OFF | NULL	A	Design Doctor Settings	Custom Design Doctor Rules Section

STATIC_HAZARDS_BEFORE_SYNTHESIS	ON | OFF | NULL	A	Design Doctor Settings	Custom Design Doctor Rules Section

STYLE	FAST | NORMAL | WYSIWYG | <style name> 	A	Global Project Logic Synthesis 	Global Project Synthesis/Assignment Options Section

STYLE	FAST | NORMAL | WYSIWYG | <style name> | NULL	B	Logic Options	Logic Options Section

SUBFACTOR_EXTRACTION	ON | OFF | DEFAULT | NULL	A	Advanced Options	Logic Synthesis Style Definition

SUBFACTOR_EXTRACTION	ON | OFF | DEFAULT | NULL	B	Advanced Options	Logic Options Section

TCO	<decimal number>[<time unit>] | OFF | NULL	A, B	Global Project Timing Requirements	Timing Requirement Assignments Section

Timing Requirements

TIMING_ANALYZER_CONFIGURATION	n/a	D	n/a	Timing Analyzer Configuration Section

TIMING_POINT	n/a	D	n/a	Timing Requirement Assignments Section

TIMING_SNF_EXTRACTOR	ON | OFF | NULL	A	Timing SNF Extractor	Compiler Processing Configuration Section

TOTAL_RECOMPILE	ON | OFF | NULL	A	Total Recompile	Compiler Processing Configuration Section

TPD	<decimal number>[<time unit>] | NULL	A, B	Global Project Timing Requirements	Timing Requirement Assignments Section

Timing Requirements

TSU	<decimal number>[<time unit>] | OFF | NULL	A, B	Global Project Timing Requirements	Timing Requirement Assignments Section

Timing Requirements

TURBO_BIT	ON | OFF | DEFAULT | NULL	A	Define Synthesis Style	Logic Synthesis Style Definition

TURBO_BIT	ON | OFF | DEFAULT | NULL	A	Classic & MAX Individual Device Options	Physical Chip Assignments Section

TURBO_BIT	ON | OFF | DEFAULT | NULL	B	Individual Logic Options	Logic Options Section

USE_DEVICE	ON | OFF | NULL	A	Use Device	Simulator Configuration Section

USE_LPM_FOR_AHDL_OPERATORS	ON | OFF | DEFAULT | NULL	A	Define Synthesis Style	Logic Synthesis Style Definition

USE_LPM_FOR_AHDL_OPERATORS	ON | OFF | DEFAULT | NULL	B	Individual Logic Options	Logic Options Section

USER_CLOCK	ON | OFF	A	FLEX 8000 Global Project Device Options	Global Device Options Section

FLEX 10K Global Project Device Options

USER_CLOCK	ON | OFF | DEFAULT | NULL	A	FLEX 8000 Individual Device Options	Physical Chip Assignments Section

FLEX 10K Individual Device Options

VERILOG_NETLIST_WRITER	ON | OFF | NULL	A	Verilog Netlist Writer	Compiler Interfaces Configuration Section

VERILOG_OUTPUT_DELAY_CONSTRUCTS	VO_FILE | SDF_2.1 | SDF_1.0 	A	Verilog Netlist Writer Settings	Compiler Interfaces Configuration Section

VHDL_USER_LIB_LOGICAL_NAMES	<symbolic name> | NULL	A	VHDL Netlist Reader Settings	Compiler Interfaces Configuration Section

VHDL_GENERATE_CONFIGURATION_DECLARATION	ON | OFF | NULL	A	VHDL Netlist Writer Settings	Compiler Interfaces Configuration Section

VHDL_NETLIST_WRITER	ON | OFF | NULL	A	VHDL Netlist Writer	Compiler Interfaces Configuration Section

VHDL_OUTPUT_DELAY_CONSTRUCTS	VHO_FILE | SDF_2.1 | SDF_1.0	A	VHDL Netlist Writer Settings	Compiler Interfaces Configuration Section

VHDL_USER_LIB_PHYSICAL_NAMES	<symbolic name> | NULL	A	VHDL Netlist Reader Settings	Compiler Interfaces Configuration Section

XNF_EMULATE_TRI_STATE_BUSES	INTERNAL_LOGIC | DEVICE_PINS | NULL	A	XNF Netlist Reader Settings	Compiler Interfaces Configuration Section

XNF_GENERATE_AHDL_TDX_FILE	ON | OFF | NULL	A	XNF Netlist Reader Settings	Compiler Interfaces Configuration Section

XNF_TRANSLATE_INTERNAL_NODE_NAMES	ON | OFF | NULL	A	XNF Netlist Reader Settings	Compiler Interfaces Configuration Section

XOR_SYNTHESIS	ON | OFF | DEFAULT | NULL	A	Define Synthesis Style	Logic Synthesis Style Definition

XOR_SYNTHESIS	ON | OFF | DEFAULT | NULL	B	Individual Logic Options	Logic Options Section


Select the Appropriate ACF Section (CPAS & PCAS)
Select the Appropriate ACF Section

Choose one of the listed Assignment & Configuration File sections for information on its use of the following keywords:

Keywords:

BIDIR_PIN

INPUT_PIN

OUTPUT_PIN

PIN

ACF Sections:

Connected Pin Assignments Section

Physical Chip Assignments Section

See also:

Comments & Documentation

Summary Table of ACF Keywords, Settings & Usage


Select the Appropriate ACF Section (LOS & LSSD)
Select the Appropriate ACF Section

Choose one of the listed Assignment & Configuration File sections for information on its use of the following keywords:

Keywords:

CARRY_CHAIN	REDUCE_LOGIC

CASCADE_CHAIN	REFACTORIZATION

DECOMPOSE_GATES	REGISTER_OPTIMIZATION

DUPLICATE_LOGIC_EXTRACTION	RESYNTHESIZE_NETWORK

Ignore_SOFT_Buffers	SLOW_SLEW_RATE

MINIMIZATION	SOFT_BUFFER_INSERTION

MULTI_LEVEL_FACTORING	SUBFACTOR_EXTRACTION

NOT_GATE_PUSH_BACK	USE_LPM_FOR_AHDL_OPERATORS

OPTIMIZE	XOR_SYNTHESIS

PARALLEL_EXPANDERS

ACF Sections:

Logic Options Section

Logic Synthesis Style Definition

See also:

Comments & Documentation

Summary Table of ACF Keywords, Settings & Usage


Select the Appropriate ACF Section (gdos & pcas)
Select the Appropriate ACF Section

Choose one of the listed Assignment & Configuration File sections for information on its use of the following keywords:

Keywords:

ADD0_TO_ADD12_PIN	ENABLE_CHIP_WIDE_OE

ADD13_PIN	ENABLE_CHIP_WIDE_RESET

ADD14_PIN	ENABLE_DCLK_OUTPUT

ADD15_PIN	ENABLE_INIT_DONE_OUTPUT

ADD16_PIN	ENABLE_JTAG

ADD17_PIN	JTAG_USER_CODE

AUTO_RESTART	nWS_nRS_nCS_CS_PIN

CLKUSR_PIN	RDCLK_PIN

CONFIG_SCHEME	RDYnBUSY_PIN

CONFIG_SCHEME_10K	RELEASE_CLEARS

DATA0_PIN	SDOUT_PIN

DATA1_TO_DATA7_PIN	USER_CLOCK

DISABLE_TIME_OUT	SECURITY_BIT

ACF Sections:

Global Device Options Section

Physical Chip Assignments Section

See also:

Comments & Documentation

Summary Table of ACF Keywords, Settings & Usage


Select the Appropriate ACF Section (gpsaos & los)
Select the Appropriate ACF Section

Choose one of the following Assignment & Configuration File sections for information on its use of the STYLE keyword:

Global Project Synthesis/Assignment Options Section

Logic Options Section

See also:

Comments & Documentation

Summary Table of ACF Keywords, Settings & Usage


Select the Appropriate ACF Section (los, lssd & pcas)
Select the Appropriate ACF Section

Choose one of the following Assignment & Configuration File sections for information on its use of the TURBO_BIT keyword:

Logic Options Section

Logic Synthesis Style Definition

Physical Chip Assignments Section

See also:

Comments & Documentation

Summary Table of ACF Keywords, Settings & Usage


Select the Appropriate File (BEGIN & END)
Select the Appropriate File

Choose one of the following formats for information on its use of the BEGIN and END keywords:

AHDL Reserved Keywords

ACF Summary Table

See also:

ACF Format

AHDL Help Contents

ACF Comments & Documentation


--------------------BEGINNING OF NON-TRANSLATED TEXT------------------------------------

This file contains FLED and Assign menu commands.

Notes: 	Common popups for Assign menu commands (e.g., Search button) appear before the Device command.

Some Assign menu commands share popups (e.g., Individual and Global Device Options). All shared popups are documented with a note.

--------------------END OF NON-TRANSLATED TEXT-----------------------------------------------


Floorplan Editor Commands
Commands

For Help, choose a command name or dialog box name from the following list. Menu names are not included on the list.

About MAX+PLUS II	Messages

Advanced Options	Minimize

AHDL	More Windows

Archive	Move

Arrange Icons	Name

Auto Device Selection	New Features in This Release

Basic Tools	New Window

Cascade	Next

Classic & MAX Global Project Device Options	Normal Size

Classic & MAX Individual Device Options	Paste

Close ( [image] and [image] menus)	Primitives

Commands	Print

Compiler	Procedures

Copy	Programmer

Current Assignments Floorplan	Project 1, 2, 3, 4...

Cut	Project Archive

Define Synthesis Style	Project Name

Demote Assignments	Project Save & Check

Device View	Project Save & Compile

Devices & Adapters	Project Save & Simulate

Find Next	Project Save, Compile & Simulate

Find Previous	Project Set Project to Current File

Find Text	READ.ME

Fit in Window	Rename Chip

FLEX 10K Global Project Device Options	Restore

FLEX 10K Individual Device Options	Routing Statistics

FLEX 8000 Global Project Device Options	Save & Check

FLEX 8000 Individual Device Options	Save & Compile

Floorplan Editor	Save & Simulate

Floorplan Editor Help Basic Tools	Save Style As

Floorplan Editor Help Commands	Save, Compile & Simulate

Floorplan Editor Help Golden Rules	Search for Help on

Floorplan Editor Help Introduction	Search Node Database

Floorplan Editor Help Procedures	Set Project to Current File

Floorplan Editor Help Shortcuts	Shortcuts

Floorplan Editor Help Table of Contents	Show Moved Nodes in Gray

Full Screen	Show Node Fan-In

Glossary	Show Node Fan-Out

Golden Rules	Show Path

Graphic Editor	Simulator

Hierarchy Display	Size

How to Use Help	Switch To

How to Use MAX+PLUS II Help	Symbol Editor

Individual Logic Options	Table of Contents

Introduction	Text Editor

LAB View	Tile

Last Compilation Floorplan	Timing Analyzer

Macrofunctions	VHDL

MAX+PLUS II Table of Contents	Waveform Editor

Maximize	Zoom In

Maximum Size	Zoom Out

Message Processor


Print Command (Floorplan Editor)
Print Command (File Menu)

Shortcuts

Prints the floorplan in the currently active window.

Click Button 1 on any item in this dialog box for information on that item:

MAX+PLUS II prints the file according to the settings for the current printer, which are specified with Print Setup (File menu).

See also:

Printing a File


Page(s)

Fit Into? % of One Page	Scales the floorplan to fit into a percentage (up to 100%) of one single page.

Fit Into? Pages	Specifies the number of pages (1, 4, or 9) you want to fit the floorplan on. Scales the floorplan to 100%, 200%, 300%, or 400% of the paper size.


Fill Pattern

Color	Prints the floorplan in color on a color printer or in gray-scale shades on a black-and-white printer.

Black & White	Prints the floorplan in black and white.


Print

Page Headers	Prints the filename, date, page count, and project name at the top of each page.

Legend	Prints the Color Legend, which shows the scheme used to display items in the floorplan and fan-out and routing information.


Print dialog box (Floorplan Editor)
Print dialog box

Click Button 1 on any item in this dialog box for information on that item:


Cut Command (Floorplan Editor)
Cut Command (Edit Menu)

Shortcuts

Deletes one or more selected nodes or pins from the Floorplan Editor and places them on the Clipboard. The previous contents of the Clipboard are erased.

Use Paste to place the cut nodes or pins at another location. If you cut an assigned node or pin, it automatically reappears in the Unassigned Nodes & Pins Box. If you cut unassigned node(s) or pin(s) from the Unassigned Nodes & Pins Box, they remain listed in the box until you paste the selection. The contents of the Clipboard can be pasted multiple times.

If you select an assignment bin with multiple assignments and choose Cut, all assignments in that bin are placed on the Clipboard. To cut an individual assignment from an assignment bin, you must first select the assignment in the drop-down list box for the Selected Node(s) & Pin(s) field.

You can use Delete instead of Cut to remove objects from your file without affecting the contents of the Clipboard.

See also:

Copying, Cutting & Pasting Node & Pin Assignments

Selecting a Node, Pin, or Other Object


Copy Command (Floorplan Editor)
Copy Command (Edit Menu)

Shortcuts

Copies one or more selected nodes or pins from the Floorplan Editor and places them on the Clipboard. The previous contents of the Clipboard are erased.

Use Paste to place the copied nodes or pins at another location. The contents of the Clipboard can be pasted multiple times.

If you select an assignment bin with multiple assignments and choose Copy, all assignments in that bin are placed on the Clipboard. To copy an individual assignment from an assignment bin, you must first select the assignment in the drop-down list box for the Selected Node(s) & Pin(s) field.

To avoid making illegal assignments, use Copy only in cases when you need to assign the same pin name or node name to multiple places, e.g., for signals that travel between devices in partitioned projects or for pins that are externally connected on MAX 7000 devices.

After you select Copy, the selected objects remain selected.

See also:

Copying, Cutting & Pasting Node & Pin Assignments

Selecting a Node, Pin, or Other Object


Paste Command (Floorplan Editor)
Paste Command (Edit Menu)

Shortcuts

Places a copy of the Clipboards contents at the selected pin(s), logic cell(s), or assignment bin(s). The Clipboard contains a selection defined with the last Cut or Copy command. The contents of the Clipboard can be pasted multiple times.

You can paste multiple items to assignment bins only. If you paste one or more items to an assignment bin, Paste adds the contents of the Clipboard to any existing assignments.

See also:

Copying, Cutting & Pasting Node & Pin Assignments

Selecting a Node, Pin, or Other Object


View Commands (Floorplan Editor)
View Commands (View Menu)

Allow you to change the display scale of the device in the current window.

Command:	Action:

Fit in Window	Changes the display scale to fit the entire device in the current window. Shortcuts

Zoom In	Increases the scale of the device displayed, showing a smaller portion of the device. Shortcuts

Zoom Out	Reduces the scale of the device displayed, showing a larger portion of the device. Shortcuts

Normal Size	Zooms in or out to display the device at normal (full) size. Shortcuts

Maximum Size	Zooms in to display the device at maximum size. Shortcuts

If objects are selected, the window zooms in and out on the objects. Otherwise, the reference point for zooming is the center of the device.

Zoom In increases the display scale incrementally, eventually reaching the scale provided by Maximum Size. Zoom Out reduces the display scale incrementally to reach the size provided by Fit in Window.

When you choose Zoom Out, some items (e.g., text or pins) in the window may disappear. All items in the file are visible at Normal Size and Maximum Size.

You can use the Full Screen command to expand the Device View or LAB View display by hiding the top half of the Floorplan Editor window.

See also:

Fitting the Floorplan into the Window

Turning Full Screen Viewing On or Off

Zooming In & Out


Full Screen Command (Floorplan Editor)
Full Screen Command (Layout Menu)

Expands the Device View or LAB View display by hiding the top half of the Floorplan Editor window.

When you turn on Full Screen, MAX+PLUS II hides the portion of the window that contains the following items:

Chip Name Field

Color Legend

Selected Node(s) & Pin(s) Field

Unassigned Nodes & Pins Box

Zoom In & Zoom Out Buttons

To switch between different floorplans for the current project, you can choose the Current Assignments Floorplan or Last Compilation Floorplan commands. To change the view of the current floorplan, choose the Device View or LAB View commands, or double-click Button 1 on a blank portion of the current display to switch to the other view.

While in full screen mode, you can also type Esc to turn off the full screen.

See also:

Fitting the Floorplan into the Window

Turning Full Screen Viewing On or Off

Zooming In & Out


Report File Equation Viewer Command (Floorplan Editor)
Report File Equation Viewer Command (Layout Menu)

Displays or hides the Report File Equation Viewer.

When this command is turned on, the Report File Equation Viewer is displayed at the bottom of the Floorplan Editor window.

You can choose one or more items in the floorplan to display their equations, fan-in, and fan-out in the Equation Viewer.

See also:

Viewing Equations in the Floorplan Editor

Showing Node Fan-In or Fan-Out

Showing Paths

Showing Routing Statistics


Device View Command (Floorplan Editor)
Device View Command (Layout Menu)

Shortcuts

Graphically represents the exterior of the current device package, including each individual pin location and pin number. Show me

The Device View display is the default Floorplan Editor display. Routing information and items such as assigned and unassigned pins and logic cells are designated according to the scheme shown in the Color Legend.

You can enter and edit assignments to pins in the Device View display. When you assign a pin name to a specific pin, the pin changes color and the pin name appears adjacent to the pin. For PGA and BGA packages, which are displayed from their bottom view, the pin name and assignment, if any, are displayed next to the pin as balloon text when you place the mouse pointer directly over that pin.

You can zoom in or out to view the device at different scales. At display scales where text is not easily readable, assignments are displayed next to the pins as balloon text when you place the pointer directly over an individual pin.

Double-clicking on the device in the Device View display changes the view to the LAB View display.

See also:

Assigning a Pin, Location, or Chip

Viewing a Device in the Device View or LAB View

Zooming In & Out


LAB View Command (Floorplan Editor)
LAB View Command (Layout Menu)

Shortcuts

Graphically represents the interior and exterior of the current device, including each individual logic cell, I/O cell, and LAB. Show me

The LAB View display shows the LABs in the device labeled by row and column. For some device packages, it also displays individual device pins. Routing information and items such as assigned and unassigned pins and logic cells are designated according to the scheme shown in the Color Legend.

You can enter and edit logic cell and pin assignments in the LAB View display. When you assign a node or pin name to a specific pin, logic cell, or I/O cell, the assigned resource changes color. You can also assign logic functions to one or more pins or logic cells using the Row, Column, LAB (logic cells only) and/or Device Assignment Bins.When you make assignments to a bin, the total number of assignments made to a particular assignment bin appears on the bin itself. Show me

When you place the mouse pointer directly over an assignment bin with a single assignment, the assignment is displayed next to the bin as balloon text. When multiple logic functions are assigned to a bin, the first two items are listed in balloon text, followed by the text etc. if there are additional items. You can then use the drop-down list box in the Selected Node(s) & Pin(s) field to select a specific assignment to edit or delete.

You can zoom in or out to view the LAB(s) in the device at different scales.

Double-clicking on the device in the Device View display changes the view to the LAB View display.

See also:

Assigning a Pin, Location, or Chip

Viewing a Device in the Device View or LAB View

Zooming In & Out


Current Assignments Floorplan Command (Floorplan Editor)
Current Assignments Floorplan Command (Layout Menu)

Shortcuts

Displays floorplan information for current assignments. Show me

If you choose Current Assignments Floorplan, you can display, enter, and edit pin, logic cell, and I/O cell assignments to a device in the current project.

You can also display floorplan information from the last compilation by choosing Last Compilation Floorplan.

See also:

Showing the Floorplan for Current Assignments

Showing the Floorplan for the Last Compilation

Viewing a Device in the Device View or LAB View


Last Compilation Floorplan Command (Floorplan Editor)
Last Compilation Floorplan Command (Layout Menu)

Shortcuts

Displays floorplan information from the last compilation, regardless of whether or not it was successful. Show me

If you choose Last Compilation Floorplan, the Floorplan Editor displays a read-only version of the Fit File information from the most recent project compilation. This option is available only if you have previously compiled the project until the Fitter has generated a Fit File and Report File.

To edit the current fit, you can back-annotate the current fit with Back-Annotate Project and then choose Current Assignments Floorplan to display floorplan information for current assignments.

See also:

Showing the Floorplan for Current Assignments

Showing the Floorplan for the Last Compilation

Viewing a Device in the Device View or LAB View


--------------------BEGINNING OF NON-TRANSLATED TEXT-----------------------------------------------

Note:	Assign menu dialog boxes share the following popups.

--------------------END OF NON-TRANSLATED TEXT-----------------------------------------------


Search

Opens the Search Node Database dialog box, which allows you to find and select one or more node or pin names in the current hierarchy tree.


Top of Hierarchy

Displays the name of the top-level design file in the current hierarchy tree. This filename is displayed in red if the current hierarchy is not the projects hierarchy tree.


Device Command (all applications)
Device Command (Assign Menu)

Assigns one or more chips in the current hierarchy tree to one or more specific devices or to AUTO devices. The Device dialog box also provides access to the Individual Device Options dialog boxes, which allow you to enter device options on a device-by-device basis, and to the Auto Device Selection dialog box.

Click Button 1 on any item in this dialog box for information on that item:

The Device dialog box allows you to assign chips to devices. If your project has multiple chip assignments, or if you choose the Edit Chips button, the expanded Device dialog box opens. Click Button 1 on any item in this dialog box for information on that item:

As an alternative to using the Device command, you can assign devices in the Physical Chip Assignments Section of the ACF for the hierarchy tree.

Be sure to refer to Guidelines for Working with Assignments for absolutely essential information on using all types of resource, probe, and device assignments.

See also:

Assigning a Device

Assigning a Pin, Location, or Chip

Assigning Resources in a Third-Party Design Editor

Devices & Adapters

Fitting & Refitting a Project

Partitioning a Project

Specifying Devices for Automatic Device Selection

Specifying Global Project Classic & MAX Device Options

Specifying Global Project FLEX 10K Device & Pin Options

Specifying Global Project FLEX 8000 Device & Pin Options

Specifying Individual Classic & MAX Device Options

Specifying Individual FLEX 10K Device & Pin Options

Specifying Individual FLEX 8000 Device & Pin Options

Recommended reading:

AB93 (Partitioning a Project with MAX+PLUS II Software)


Device Family; Device dialog box
Device Family

Specifies the device family for the current hierarchy tree. Select a device family to change the device family and to display names of devices in the specified family in the Devices box.

Altera recommends that you explicitly specify the target device family right away when you create a new design file or project so that you can take advantage of family-specific macrofunctions.

When the Compiler processes a project, all devices in the project must be from the same device family; you cannot mix devices from separate device families.

If a project is compiled with the Compilers Linked SNF Extractor module turned on, the device family is ignored. In this type of compilation, the SNFs for multiple individual sub-projects--which can be implemented in different device families--are combined into a top-level super-project that does not use device family information.


Devices; Device dialog box
Devices

Lists all Altera devices in the device family that is currently selected in the Device Family box. In addition, AUTO is listed to provide automatic device selection.

In a multi-device project, you can choose Edit Chips to expand the Device dialog box and assign chips to multiple devices. In the expanded dialog box, selecting a device name or AUTO in the Devices box and choosing Add or Change assigns the selected device to the chip name displayed in the Chip Name box.

If you assign a chip to AUTO, you can choose the Auto Device button to open the Auto Device Selection dialog box, which allows you to specify the range of devices that the Compiler can use when it chooses a device for the chip.

If Show All Packages & Speed Grades is turned on, devices with package type, operating temperature, and speed grade information are included in the list.


Show Only Generic Devices; Device dialog box
Show All Packages & Speed Grades

Lists all supported variations of Altera devices in the device family selected in the Device Family box--including device speed grades, package types, and operating temperatures--in the Devices box.

If this option is turned off, the Devices box displays only generic devices, i.e., those without speed grade, package type, or operating temperature information.


Maintain Stable Synthesis Regardless;Device Dialog box
Maintain Stable Synthesis Regardless of Device or Speed Grade Changes

Maintains stable logic synthesis, including timing assignment-driven synthesis, from one compilation to the next, regardless of whether you change device assignments.

If this option is turned on, back-annotated assignments from a previous compilation are most likely to yield the same results when the project is recompiled. If this option is turned off, the Compiler may change the logic synthesis during the next compilation, particularly if the previous compilation included AUTO devices.


Chip Name;Device dialog box
Chip Name

Specifies the name of a chip to be assigned to a device. The drop-down list box displays all existing chip assignments for the current hierarchy tree.

You can either type a name with up to 32 name characters to create a new chip, or select an existing name from the drop-down list box. For a single-device project, the default chip name is the project name. In a multi-device project, you should not use the project name as one of the chip names. Selecting a device name or AUTO in the Devices box and choosing Add or Change assigns the selected device to the chip name displayed in the Chip Name box.

If you assign a chip to AUTO, you can choose the Auto Device button to open the Auto Device Selection dialog box, which allows you to specify the range of devices that the Compiler can use when it chooses a device for the chip.


Existing Device Assignments;Device dialog box
Existing Device Assignments

Lists the existing device assignments for the current hierarchy tree, as well as the device option settings for each device. Assignments are listed in the order specified with the Sort By option.

You can select an assignment in this box to fill in the Chip Name and Devices boxes to show the current device assignment for a chip. You can then edit the assignment and choose Change to update the Existing Device Assignments box.


Add;Device dialog box
Add/Change

Assigns the chip name displayed in the Chip Name box to the device selected in the Devices box. The new or updated device assignment is listed in the Existing Device Assignments box.

The Add button changes into the Change button if you are editing an existing assignment. You do not need to choose Add or Change if you are editing only one assignment. Choosing OK always saves the current assignment shown in the Devices and Chip Name boxes, as well as all assignments in the Existing Device Assignments box.


Delete;Device dialog box
Delete

Deletes the device assignment selected in the Existing Device Assignments box and its corresponding device options.

Only the device assignment is deleted, the chip name that was assigned to the device is not. If you wish, you can re-select it from the Chip Name box and assign it to a different device.


OK; Device dialog box
OK

Saves all changes and closes the dialog box. If you are editing only one assignment, you do not need to choose Add or Change before choosing OK. Choosing OK always saves the current assignment shown in the Devices and Chip Name boxes, as well as all assignments shown in the Existing Device Assignments box.


Auto Device Selection;Device dialog box
Auto Device

Opens the Auto Device Selection dialog box, which allows you to select specific devices to be used for automatic device selection, i.e., to be used if you have assigned any chips to AUTO.


Device Options; Device dialog box
Device Options

Opens the Individual Device Options dialog box, which allows you to specify device option settings for the device assignment that is currently shown in the Devices and Chip Name boxes. The Individual Device Options dialog box differs depending on the current device family.


Edit Chips;Device dialog box
Edit Chips

Expands the Device dialog box to allow you to view and edit multiple device assignments for the current hierarchy tree.


Rename Chip;Device dialog box
Rename Chip

Opens the Rename Chip dialog box, which allows you to change the name of the current chip.


Sort By;Device dialog box
Sort By

Specifies the order in which device assignments are listed in the Existing Device Assignments box. You can sort assignments alphabetically by Chip Name or Device Name.


Cancel; Device dialog box
Cancel/Close

Closes the dialog box, saving only the assignments listed in the Existing Device Assignments box.

The Cancel button changes into the Close button if you have already saved all changes by choosing Add or Change.


Device dialog box

Click Button 1 on any item in this dialog box for information on that item:


Expanded Device dialog box

Click Button 1 on any item in this dialog box for information on that item:


Auto Device Selection Dialog Box (all applications)
Auto Device Selection Dialog Box (Device Command)

Selects specific devices for the Compiler to use in automatic device selection for the current hierarchy tree.

You open this dialog box by choosing the Auto Device button in the Device dialog box. The settings you specify with the Auto Device Selection dialog box apply to all chips and the corresponding devices that are assigned to AUTO in the Device dialog box.

Click Button 1 on any item in this dialog box for information on that item:

The devices specified with Auto Device Selection are used only in the following cases:

When one or more device assignments assign chip(s) to AUTO device(s) in the Device dialog box. AUTO is also the default if no user-specified chip or device assignments exist.

When the existing devices assigned for the project cannot fit all of the projects logic and additional devices must be added.

MAX+PLUS II cannot partition a project between devices from different device families.

As an alternative to using the Auto Device Selection dialog box, you can specify devices for automatic device selection in the Auto Device Choices Section of the ACF for the hierarchy tree.

See also:

Assigning a Device

Assigning a Pin, Location, or Chip

Fitting & Refitting a Project

Partitioning a Project

Refitting a Project

Specifying Devices for Automatic Device Selection


Device Family

Displays the device family for the project.

If you wish to change the device family, choose Cancel to return to the Device dialog box.


# Allowed

Limited	Specifies a limited number of the currently selected device in the # / Selected Devices box. If you select Limited, you can type an integer between 1 and 99 in the box. During project compilation, the Compiler creates new devices as necessary until this specified maximum number is reached.

Unlimited	Specifies an unlimited number (U) of the currently selected device in the # / Selected Devices box.


Available Devices

Lists the devices available in the current device family.

If you wish to change the device family, choose Cancel to return to the Device dialog box.

If Show All Packages & Speed Grades is turned on, devices with package type, operating temperature, and speed grade information are included in the list.

You can choose => and <= to move selected devices between the Available Devices and # / Selected Devices boxes.


# / Selected Devices

Shows the devices from the current device family selected for automatic device selection and the number allowed (#) of each device. U is displayed for devices that can be used in unlimited numbers.

Selecting a device in the # / Selected Devices box allows you to specify the number of devices allowed with the # Allowed option.

You can choose => and <= to move selected devices between the Available Devices and # / Selected Devices boxes.


=>

Moves selected device(s) from the Available Devices box to the # / Selected Devices box.


<=

Moves selected device(s) from the # / Selected Devices box to the Available Devices box.


Show All Packages & Speed Grades

Lists all supported variations of Altera devices in the current device family--including device speed grades, package types, and operating temperatures--in the Available Devices box.

If this option is turned off, the Available Devices box displays only generic devices, i.e., those without speed grade, package type, or operating temperature information.


Ask Before Adding Extra Devices

Directs the Compiler to ask before adding extra AUTO devices during project fitting.


OK; template for second and third-level dialog boxes
OK

Saves all changes and closes the dialog box. You are returned to the Device dialog box.


Cancel; template for second and third-level dialog boxes
Cancel

Closes the dialog box without saving any changes and returns you to the Device dialog box.


Auto Device Selection dialog box

Click Button 1 on any item in this dialog box for information on that item:


Individual Device Options Dialog Box (all applications)
Individual Device Options Dialog Box

Specifies device option settings for the current device.

You open this dialog box by choosing the Device Options button in the Device dialog box. The settings you specify with the Individual Device Options dialog box apply only to the device and corresponding chip assignment that are currently selected in the Device dialog box.

The Individual Device Options dialog box differs depending on the current device family. Select the appropriate dialog box:

Classic & MAX Individual Device Options

FLEX 8000 Individual Device Options

FLEX 10K Individual Device Options

As an alternative to using the Individual Device Options dialog box, you can assign device option settings in the Physical Chip Assignments Section of the ACF for the hierarchy tree.

Be sure to refer to Guidelines for Working with Assignments for absolutely essential information on using all types of resource, probe, and device assignments.

See also:

Assigning a Device

Assigning a Pin, Location, or Chip

Assigning Resources in a Third-Party Design Editor

Defining a Logic Synthesis Style

Specifying Global Project Classic & MAX Device Options

Specifying Global Project FLEX 10K Device & Pin Options

Specifying Global Project FLEX 8000 Device & Pin Options

Specifying Individual Classic & MAX Device Options

Specifying Individual FLEX 10K Device & Pin Options

Specifying Individual FLEX 8000 Device & Pin Options


--------------------BEGINNING OF NON-TRANSLATED TEXT-----------------------------------------------

The segmented hypergraphics for the three Individual Device Options share the following OK popup.

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OK; Individual Device Options dialog boxes
OK

Saves all changes and closes the dialog box. You are returned to the Device dialog box.

The new or updated device option settings are listed in the Existing Device Assignments box, which appears in the expanded Device dialog box.


Classic & MAX Individual Device Options Dialog Box (all applications)
Classic & MAX Individual Device Options Dialog Box

Specifies the Turbo Bit and Security Bit settings for the current device assignment.

You open this dialog box by choosing the Device Options button in the Device dialog box when the Classic, MAX 5000, MAX 7000, or MAX 9000 device family is currently specified for the project. The settings in this dialog box apply only to the chip and corresponding device assignment that is currently selected in the Device dialog box.

The Classic & MAX Individual Device Options dialog box uses three-way checkboxes to specify options on a device-by-device basis. Click Button 1 on any item in this dialog box for information on that item:

As an alternative to using the Classic & MAX Individual Device Options dialog box, you can assign device option settings in the Physical Chip Assignments Section of the ACF for the hierarchy tree.

1.	You can specify the default Turbo Bit setting for the entire project, which is stored in the projects default logic synthesis style, with Global Project Logic Synthesis. You can specify the default Security Bit setting for the entire project with Classic & MAX Global Project Device Options.

2.	Be sure to refer to Guidelines for Working with Assignments for absolutely essential information on using all types of resource, probe, and device assignments.

See also:

Adjusting the Fit During Compilation

Assigning a Device

Back-Annotating Assignments for a Project

Fitting & Refitting a Project

Specifying Global Project Classic & MAX Device Options

Specifying Individual Classic & MAX Device Options


Turbo Bit; Classic & MAX Individual Device Options dialog box
Turbo Bit

Specifies the Turbo Bit setting for the current chip and corresponding device assignment as on, off, or default.

If you select the default (grayed) setting for the Turbo Bit, the Turbo Bit setting for the current device is determined by the project default, which is part of the project-wide default logic synthesis style specified with Global Project Logic Synthesis.


Security Bit; Classic & MAX Individual Device Options dialog box
Security Bit

Specifies the Security Bit setting for the current chip and corresponding device assignment as on, off, or default.

If you select the default (grayed) setting for the Security Bit, the Security Bit setting for the current device is determined by the project default, which is specified with Classic & MAX Global Project Device Options. You can also turn the Security Bit on or off on a device-by-device basis before or after programming with the Programmers Security Bit option.


Classic & MAX Individual Device Options dialog box

Click Button 1 on any item in this dialog box for information on that item:


FLEX 8000 Individual Device Options Dialog Box (all applications)
FLEX 8000 Individual Device Options Dialog Box

Specifies various device options and pin options for the current FLEX 8000 device.

You open this dialog box by choosing the Device Options button in the Device dialog box when the FLEX 8000 device family is currently specified for the project. The settings in this dialog box apply only to the chip and corresponding device assignment that is currently selected in the Device dialog box.

The FLEX 8000 Individual Device Options dialog box uses three-way checkboxes to specify options on a device-by-device basis. Click Button 1 on any item in this dialog box for information on that item:

As an alternative to using the FLEX 8000 Individual Device Options dialog box, you can specify option settings in the Physical Chip Assignments Section of the ACF for the hierarchy tree.

You can specify the global default FLEX 8000 device and pin option settings for the entire project with the FLEX 8000 Global Project Device Options dialog box, which you can open by choosing the Global Project Device Options command when the FLEX 8000 device family is currently specified for the project.

See also:

Assigning a Device

Combining & Converting SRAM Object Files

Specifying Global Project FLEX 8000 Device & Pin Options

Specifying Individual FLEX 8000 Device & Pin Options

Recommended reading:

AN33 (Configuring FLEX 8000 Devices)

AN38 (Configuring Multiple FLEX 8000 Devices)


User-Supplied Start-Up Clock; FLEX 8000 Individual Device Options dialog box
User-Supplied Start-Up Clock

Specifies the User-Supplied Start-Up Clock setting for the current chip and corresponding device assignment as on, off, or default.

If this option is turned on, it directs the device to use a user-supplied Clock for initialization on the CLKUSR pin. If it is turned off, external circuitry is required to provide the initialization Clock on the DCLK pin in the PS and PPS configuration schemes; in the AS, APU, APD, and PPA configuration schemes, the device uses an internal initialization Clock.

If you select the default (grayed) setting for this option, the User-Supplied Start-Up Clock setting for the current device is determined by the project default, which is specified with the FLEX 8000 Global Project Device Options dialog box.


Auto-Restart Configuration on Frame Error; FLEX 8000 Individual Device Options dialog box
Auto-Restart Configuration on Frame Error

Specifies the Auto-Restart Configuration on Frame Error setting for the current chip and corresponding device assignment as on, off, or default.

If this option is turned on, it directs the device to restart the configuration process automatically if a data frame error is encountered. If it is turned off, you must externally direct the device to restart the configuration process if a frame error occurs.

If you select the default (grayed) setting for this option, the Auto-Restart Configuration on Frame Error setting for the current device is determined by the project default, which is specified with the FLEX 8000 Global Project Device Options dialog box.

This option is available only in the AS, APU, and APD configuration schemes.


Release Clears Before Tri-States; FLEX 8000 Individual Device Options dialog box
Release Clears Before Tri-States

Specifies the Release Clears Before Tri-States setting for the current chip and corresponding device assignment as on, off, or default.

If this option is turned on, it directs the device to release the Clear override on the tri-state buffer before releasing the Output Enable signal on registered logic cells and I/O cells. If it is turned off, the Output Enable signals are released before the Clear overrides.

If you select the default (grayed) setting for this option, the Release Clears Before Tri-States setting for the current device is determined by the project default, which is specified with the FLEX 8000 Device Options dialog box.


User-Supplied Start-Up Clock; FLEX 8000 Individual Device Options dialog box
Enable DCLK Output in User Mode

Specifies the Enable DCLK Output in User Mode setting for the current chip and corresponding device assignment as on, off, or default.

If this option is turned on, it enables the DCLK pin when the device is operating in user mode after device configuration and initialization have been completed. If it is turned off, the DCLK pin is disabled when the device operates in user mode.

If you select the default (grayed) setting for this option, the Enable DCLK Output in User Mode setting for the current device is determined by the project default, which is specified with the FLEX 8000 Global Project Device Options dialog box.

This option is available only in the AS, APU, APD, and PPA configuration schemes.


User-Supplied Start-Up Clock; FLEX 8000 Individual Device Options dialog box
Disable Start-Up Time-Out

Specifies the Disable Start-Up Time-Out setting for the current chip and corresponding device assignment as on, off, or default.

If this option is turned on, it disables the time-out error checking that determines whether CONF_DONE pin goes high within 10 Clock cycles after being released by the device. If it is turned on, the device will continue to wait for CONF_DONE to go high. If this option is turned off, the device drives the nSTATUS pin low at the end of the configuration cycle if the CONF_DONE pin does not go high within 10 Clock cycles.

If you select the default (grayed) setting for this option, the Disable Start-Up Time-Out setting for the current device is determined by the project default, which is specified with the FLEX 8000 Global Project Device Options dialog box.


User-Supplied Start-Up Clock; FLEX 8000 Individual Device Options dialog box
Enable JTAG Support

Specifies the Enable JTAG Support setting for the current chip and corresponding device assignment as on, off, or default.

If this option is turned on, it enables the circuitry for JTAG boundary-scan testing. If it is turned off, JTAG boundary-scan testing is not available.

If you select the default (grayed) setting for this option, the Enable JTAG Support setting for the current device is determined by the project default, which is specified with the FLEX 8000 Global Project Device Options dialog box.


Configuration Scheme; FLEX 8000 Individual Device Options dialog box
Configuration Scheme

Selects Use Global Project Setting, which indicates that the setting will be specified for the project as a whole in the FLEX 8000 Global Project Device Options dialog box, or one of the following FLEX 8000 or FLEX 10K configuration schemes:

AS	APU	APD

PS	PPS	PPA

The FLEX 8000M devices can only be configured using the Active Serial and Passive Serial configuration schemes.

Selecting a configuration scheme displays the recommended settings for the dual-purpose pins in that configuration scheme under Reserve and Tri-State. It has no effect on how the Compiler generates programming file(s) for the project.


Reserve; FLEX 8000 Individual Device Options dialog box
Reserve

Specifies the status for the specified dual-purpose pin on the current chip and corresponding device as reserved (on), not reserved (off), or default.

If Reserve is turned on, the pin is not used as an I/O pin during user mode (i.e., reserved). If Reserve is turned off, the pin is available as an I/O pin during user mode.

If you select the default (grayed) setting for a pin, the setting for that pin is determined by the project default, which is specified with the FLEX 8000 Global Project Device Options dialog box.

Selecting an appropriate configuration scheme in the Configuration Scheme box shows the recommended settings under Reserve for the dual-purpose pins available in that configuration scheme.

Refer to the FLEX 8000 Programmable Logic Device Family Data Sheet for more information on dual-purpose configuration pins.


Tri-State; FLEX 8000 Individual Device Options dialog box
Tri-State

Specifies the status for the specified dual-purpose pins on the current chip and corresponding device as tri-stated (on), allowed to drive a signal (off), or default. Pins can be tri-stated depending on the external circuitry of your board.

If Tri-State is turned on, the pin is kept in a state of high impedance during user mode. If Tri-State turned off, the pin is allowed to drive a signal during user mode.

If you select the default (grayed) setting for a pin, the setting for that pin is determined by the project default, which is specified with the FLEX 8000 Global Project Device Options dialog box.

Selecting an appropriate configuration scheme in the Configuration Scheme box shows the recommended settings under Tri-State for the dual-purpose pins available in that configuration scheme.

Note that <-- is used as the visual indication of the keyboard focus on these checkboxes if you use the keyboard to select items in the dialog box.

Refer to the FLEX 8000 Programmable Logic Device Family Data Sheet for more information on dual-purpose configuration pins.


Not Affected by Configuration Scheme; FLEX 8000 Individual Device Options dialog box
Not Affected by Configuration Scheme

Lists the dual-purpose pins that can be reserved and tri-stated, but which are not affected by the configuration scheme selected in the Configuration Scheme box.

Reserve	Specifies whether the associated pin is reserved in user mode. If Reserve is turned on, the pin is not used as an I/O pin during user mode (i.e., reserved). If Reserve is turned off, the pin is available as an I/O pin during user mode.

Tri-State	Specifies whether the associated pin is tri-stated in user mode. If Tri-State is turned on, the pin is kept in a state of high impedance during user mode. If Tri-State is turned off, the pin is allowed to drive a signal during user mode. Pins can be tri-stated depending on the external circuitry of your board.

If you select the default (grayed) setting for either Reserve or Tri-State, the setting for that pin is determined by the project default, which is specified with the FLEX 8000 Global Project Device Options dialog box.


FLEX 8000 Individual Device Options dialog box

Click Button 1 on any item in this dialog box for information on that item:


FLEX 10K Individual Device Options Dialog Box (all applications)
FLEX 10K Individual Device Options Dialog Box

Specifies various device options and pin options for the current FLEX 10K device.

You open this dialog box by choosing the Device Options button in the Device dialog box when the FLEX 10K device family is currently specified for the project. The settings in this dialog box apply only to the chip and corresponding device assignment that is currently selected in the Device dialog box.

The FLEX 10K Individual Device Options dialog box uses three-way checkboxes to specify options on a device-by-device basis. Click Button 1 on any item in this dialog box for information on that item:

As an alternative to using the FLEX 10K Individual Device Options dialog box, you can specify option settings in the Physical Chip Assignments Section of the ACF for the hierarchy tree.

You can specify the global default FLEX 10K device and pin option settings for the entire project with the FLEX 10K Global Project Device Options dialog box, which you can open by choosing the Global Project Device Options command when the FLEX 10K device family is currently specified for the project.

See also:

Assigning a Device

Combining & Converting SRAM Object Files

Specifying Global Project FLEX 10K Device & Pin Options

Specifying Individual FLEX 10K Device & Pin Options


User-Supplied Start-Up Clock; FLEX 10K Individual Device Options dialog box
User-Supplied Start-Up Clock

Specifies the User-Supplied Start-Up Clock setting for the current chip and corresponding device assignment as on, off, or default.

If this option is turned on, it directs the device to use a user-supplied Clock for initialization on the CLKUSR pin. If it is turned off, external circuitry is required to provide the initialization Clock on the DCLK pin in the PS and PPS configuration schemes; in the AS, APU, APD, and PPA configuration schemes, the device uses an internal initialization Clock.

If you select the default (grayed) setting for this option, the User-Supplied Start-Up Clock setting for the current device is determined by the project default, which is specified with the FLEX 10K Global Project Device Options dialog box.


Auto-Restart Configuration on Frame Error; FLEX 10K Individual Device Options dialog box
Auto-Restart Configuration on Frame Error

Specifies the Auto-Restart Configuration on Frame Error setting for the current chip and corresponding device assignment as on, off, or default.

If this option is turned on, it directs the device to restart the configuration process automatically if a data frame error is encountered. If it is turned off, you must externally direct the device to restart the configuration process if a frame error occurs.

If you select the default (grayed) setting for this option, the Auto-Restart Configuration on Frame Error setting for the current device is determined by the project default, which is specified with the FLEX 10K Global Project Device Options dialog box.

This option is available only in the AS, APU, and APD configuration schemes.


Release Clears Before Tri-States; FLEX 10K Individual Device Options dialog box
Release Clears Before Tri-States

Specifies the Release Clears Before Tri-States setting for the current chip and corresponding device assignment as on, off, or default.

If this option is turned on, it directs the device to release the Clear override on the tri-state buffer before releasing the Output Enable signal on registered logic cells and I/O cells. If it is turned off, the Output Enable signals are released before the Clear overrides.

If you select the default (grayed) setting for this option, the Release Clears Before Tri-States setting for the current device is determined by the project default, which is specified with the FLEX 10K Global Project Device Options dialog box.


Enable Chip-Wide Reset; FLEX 10K Individual Device Options dialog box
Enable Chip-Wide Reset

Specifies the Enable Chip-Wide Reset setting for the current chip and corresponding device assignment as on, off, or default.

If this option is turned on, it directs the device to enable the RESET pin which allows all registers of the device to be reset by an external source. If this option is turned off, the RESET pin is disabled when the device operates in user mode.

If you select the default (grayed) setting for this option, the Enable Chip-Wide Reset  setting for the current device is determined by the project default, which is specified with the FLEX 10K Global Project Device Options dialog box.


Enable Chip-Wide Output Enable; FLEX 10K Individual Device Options dialog box
Enable Chip-Wide Output Enable

Specifies the Enable Chip-Wide Output Enable setting for the current chip and corresponding device assignment as on, off, or default.

If this option is turned on, it directs the device to enable the OE pin when the device is in user mode. If this option is turned off, the OE pin is disabled when the device operates in user mode.

If you select the default (grayed) setting for this option, the Enable Chip-Wide Output Enable setting for the current device is determined by the project default, which is specified with the FLEX 10K Global Project Device Options dialog box.


Enable INIT_DONE Output; FLEX 10K Individual Device Options dialog box
Enable INIT_DONE Output

Specifies the Enable INIT_DONE Output setting for the current chip and corresponding device assignment as on, off, or default.

If this option is turned on, it directs the device to enable the INIT_DONE pin when the device is operating in user mode after device configuration and initialization have been completed. If this option is turned off, the INIT_DONE pin is disabled when the device operates in user mode.

If you select the default (grayed) setting for this option, the Enable INIT_DONE Output  setting for the current device is determined by the project default, which is specified with the FLEX 10K Global Project Device Options dialog box.


Configuration Scheme; FLEX 10K Individual Device Options dialog box
Configuration Scheme

Selects Use Global Project Setting, which indicates that the setting will be specified for the project as a whole in the FLEX 10K Global Project Device Options dialog box, or one of the following FLEX 10K configuration schemes:

PS

PPS

PPA

Selecting a configuration scheme displays the recommended settings for the dual-purpose pins in that configuration scheme under Reserve and Tri-State. It has no effect on how the Compiler generates programming file(s) for the project.


Reserve; FLEX 10K Individual Device Options dialog box
Reserve

Specifies the status for the specified dual-purpose pin on the current chip and corresponding device as reserved (on), not reserved (off), or default.

If Reserve is turned on, the pin is not used as an I/O pin during user mode (i.e., reserved). If Reserve is turned off, the pin is available as an I/O pin during user mode.

If you select the default (grayed) setting for a pin, the setting for that pin is determined by the project default, which is specified with the FLEX 10K Global Project Device Options dialog box.

Selecting an appropriate configuration scheme in the Configuration Scheme box shows the recommended settings under Reserve for the dual-purpose pins available in that configuration scheme.

Refer to the FLEX 10K Programmable Logic Device Family Data Sheet for more information on dual-purpose configuration pins.


Tri-State; FLEX 10K Individual Device Options dialog box
Tri-State

Specifies the status for the specified dual-purpose pins on the current chip and corresponding device as tri-stated (on), allowed to drive a signal (off), or default. Pins can be tri-stated depending on the external circuitry of your board.

If Tri-State is turned on, the pin is kept in a state of high impedance during user mode. If Tri-State turned off, the pin is allowed to drive a signal during user mode.

If you select the default (grayed) setting for a pin, the setting for that pin is determined by the project default, which is specified with the FLEX 10K Global Project Device Options dialog box.

Selecting an appropriate configuration scheme in the Configuration Scheme box shows the recommended settings under Tri-State for the dual-purpose pins available in that configuration scheme.

Note that <-- is used as the visual indication of the keyboard focus on these checkboxes if you use the keyboard to select items in the dialog box.

Refer to the FLEX 10K Programmable Logic Device Family Data Sheet for more information on dual-purpose configuration pins.


Not Affected by Configuration Scheme; FLEX 10K Individual Device Options dialog box
Not Affected by Configuration Scheme

Lists the dual-purpose pins that can be reserved and tri-stated, but which are not affected by the configuration scheme selected in the Configuration Scheme box.

Reserve	Specifies whether the associated pin is reserved in user mode. If Reserve is turned on, the pin is not used as an I/O pin during user mode (i.e., reserved). If Reserve is turned off, the pin is available as an I/O pin during user mode.

Tri-State	Specifies whether the associated pin is tri-stated in user mode. If Tri-State is turned on, the pin is kept in a state of high impedance during user mode. If Tri-State is turned off, the pin is allowed to drive a signal during user mode. Pins can be tri-stated depending on the external circuitry of your board.

If you select the default (grayed) setting for either Reserve or Tri-State, the setting for that pin is determined by the project default, which is specified with the FLEX 10K Global Project Device Options dialog box.


FLEX 10K Individual Device Options dialog box

Click Button 1 on any item in this dialog box for information on that item:


Rename Chip Dialog Box (all applications)
Rename Chip Dialog Box (Device Command)

Changes the name of the current chip.

You open this dialog box by choosing the Rename Chip button in the expanded Device dialog box. The new name specified with the Rename Chip dialog box applies to the chip name that is currently selected in the Device dialog box.

Click Button 1 on any item in this dialog box for information on that item:

The Rename Chip dialog box allows you to rename a chip--and thus transfer all pin and location assignments from the old chip to the new chip--without manually editing the ACF for the project.

If you save a top-level design file to a new name and the current chip names are based on the project name, MAX+PLUS II usually can automatically rename chips, and the Rename Chip dialog box is not needed. The Rename Chip dialog box is useful for renaming chips if your current project contains chip names that are not based on the project name and you wish to save the top-level-design file to a new name. If both projects are in the same directory and you do not rename the chips in one of them, the programming files from one project--whose names are based on chip names--can overwrite the programming files from the other.

As an alternative to using the Rename Chip dialog box, you can rename a chip in the Physical Chip Assignments Section of the ACF for the hierarchy tree.

See also:

Assigning a Device

Assigning a Pin, Location, or Chip

Renaming a Chip


Current Chip Name

Displays the name of the currently selected chip.


New Chip Name

Specifies the name to which you wish to change the currently selected chip.

Type a chip name with up to 32 name characters.


OK; Rename Chip dialog box
OK

Saves all changes and closes the dialog box. You are returned to the Device dialog box. The new chip name is displayed in the Chip Name box and in the Existing Device Assignments box.


Cancel; Rename Chip dialog box
Cancel

Closes the dialog box without saving any changes and returns you to the Device dialog box.


Rename Chip dialog box

Click Button 1 on any item in this dialog box for information on that item:


Pin/Location/Chip Command (all applications)
Pin/Location/Chip Command (Assign Menu)

Shortcuts

Assigns one or more logic functions in the current hierarchy tree to a specific chip, or to a pin or another location within a chip. You can also assign a pin number to an input pin that is not connected to other logic to reserve a pin for future use, and assign two logic functions to a single logic cell to implement register packing.

Click Button 1 on any item in this dialog box for information on that item:

If you have not assigned specific device(s) for the current hierarchy tree with Device, only the Anywhere on this Chip option is available under Chip Resource.

As an alternative to using the Pin/Location/Chip command, you can enter assignments in the Physical Chip Assignments Section of the ACF for the hierarchy tree.

In the Graphic Editor, a pin, location, and/or chip assignment appears on the bottom left corner of a symbol if Show Pins/Location/Chips or Show All is turned on. On pin primitives only, the assignment appears opposite the input or output of the symbol.

Pin/Location/Chip can be used to enter pin and chip assignments on pin primitives in OrCAD Schematic Files. However, you should not enter logic cell, I/O cell, embedded cell, LAB, row, or column assignments in OrCAD Schematic Files with the Pin/Location/Chip command. See Guidelines for Working with OrCAD Schematic Files for more information.

Be sure to refer to Guidelines for Working with Assignments for absolutely essential information on using all types of resource, probe, and device assignments.

See also:

Assigning a Pin, Location, or Chip

Back-Annotating Assignments for a Project

Clearing Assignments for a Project

Copying a Resource Assignment

Deleting an Assignment

Devices & Adapters

Fitting & Refitting a Project

Partitioning a Project

Pin, Location, & Chip Assignments

Selecting a Node, Pin, or Other Object (Floorplan Editor)

Showing Parameters and Probe & Resource Assignments (Graphic Editor)

Recommended reading:

AB93 (Partitioning a Project with MAX+PLUS II Software)


Node Name

Specifies the hierarchical node name or bus name to which the Pin/Location/Chip assignment(s) will be applied.

If you selected a node, bus, or symbol before choosing Pin/Location/Chip, its name is displayed. If you selected more than one node, bus, or symbol, the text **-Multiple Items-** is displayed.

You can choose Search to open the Search Node Database dialog box, which allows you to select a node name from the current hierarchy tree to copy to the Node Name box.


Chip
Chip Name

Specifies the chip name for the node or bus name shown in the Node Name box.

You can either type a name with up to 32 name characters to create a new chip, or select an existing name from the drop-down list box to add the currently selected item(s) to an existing chip.

In a single-device project, the chip name is optional and defaults to the project name. In a multi-device project, the project name should not be used as a chip name.

If you select an existing pin assignment, change the Chip Name or Pin Type, and choose Add, a new assignment is created. The previous assignment is not overwritten and both entries appear in the Existing Pin/Location/Chip Assignments box. This feature is useful for specifying assignments in partitioned projects or if pins are externally connected on MAX 7000 devices. If you simply wish to update the existing assignment, you must delete the old assignment after you add the new assignment.


Pin

Specifies the pin number for the nodeor bus name shown in the Node Name box. This pin number is associated with the chip shown in the Chip Name box and the corresponding device to which it is assigned. The pin number can also include letters for PGA packages and FLEX 8000 devices.

You can type a pin number or select a number from the Pin drop-down list box.

This option is available only if you have assigned a specific device for the current Chip Name with the Device dialog box.

Go to Devices & Adapters for information on pin numbers for all Altera device packages.


Pin Type
Pin Type (Only for Special Cases)

Specifies the type of the current pin. If you have previously compiled the project, MAX+PLUS II automatically displays the pin type as Input, Output, or Bidir. Otherwise, the pin type is shown as Unspecified.

In most cases you do not need to edit the Pin Type and can leave it as Unspecified. You must specify Pin Type in the following cases:

For signals that travel between devices in a multi-device project, you must specify the Pin Type to distinguish the output of one device from the input(s) to other devices. In FLEX 8000 devices, you can also optionally assign the logic cell that feeds a device output to a location.

When an output and input pin on a MAX 7000 device are wired together to drive an Output Enable signal, you must specify the Pin Type to distinguish the output from the input.


LC/IOC/EC

Specifies the logic cell, I/O cell, or embedded cell number for the nodeor bus name shown in the Node Name box. This logic cell, I/O cell, or embedded cell number is associated with the chip shown in the Chip Name box and the corresponding device to which it is assigned. The logic cell number can also include letters for PGA packages, FLEX 8000, or FLEX 10K devices.

You can type or select a logic cell number, I/O cell number, or embedded cell number from the Logic Cell drop-down list box.

This option is available only if you have assigned a specific device for the current Chip Name with the Device dialog box. You can open the Device dialog box by choosing the Assign Device button in this dialog box.

Go to Devices & Adapters for information on logic cell and pin numbers for all Altera device packages.


LAB/EAB

Specifies the LAB or EAB name for the nodeor bus name shown in the Node Name box. This LAB or EAB name is associated with the chip shown in the Chip Name box and the corresponding device to which it is assigned.

You can type a LAB or EAB name or select a name from the LAB drop-down list box.

This option is available only if you have assigned a specific device for the current Chip Name with the Device dialog box. You can open the Device dialog box by choosing the Assign Device button in this dialog box.


Row

Specifies the row name for the nodeor bus name shown in the Node Name box. This row is associated with the chip shown in the Chip Name box and the corresponding FLEX 8000 device to which it is assigned.

You can type a row name or select a name from the Row drop-down list box. You can select ANY to indicate that the selected node can be assigned to any row, pin, or row logic cell.

This option is available only if you have assigned a specific device for the current Chip Name with the Device dialog box. You can open the Device dialog box by choosing the Assign Device button in this dialog box.


Column

Specifies the column number for the nodeor bus name shown in the Node Name box. This column is associated with the chip shown in the Chip Name box and the corresponding FLEX 8000 device to which it is assigned.

You can type a column number or select a number from the Col drop-down list box.

You can select ANY to indicate that the selected node can be assigned to any column pin or column logic cell.

This option is available only if you have assigned a specific device for the current Chip Name with the Device dialog box. You can open the Device dialog box by choosing the Assign Device button in this dialog box.


Anywhere on this Chip

Specifies that the nodeor bus name shown in the Node Name box should be placed anywhere on the current chip. The current chip is shown in the Chip Name box.


Existing Pin/Location/Chip Assignments

Lists the existing pin, location, and chip assignments for the current hierarchy tree. Assignments are listed in the order specified with the Sort By option.

You can select an assignment in this box to fill in the Node Name box, Chip Name box, and the setting under Chip Resource to show the current assignment for the nodeor bus. You can then edit the assignment and choose Change to update the Existing Pin/Location/Chip Assignments box.

If you select an existing pin assignment, change the Chip Name or Pin Type, and choose Add, a new assignment is created. The previous assignment is not overwritten and both entries appear in the Existing Pin/Location/Chip Assignments box. This feature is useful for specifying assignments in partitioned projects or if pins are externally connected on MAX 7000 devices. If you simply wish to update the existing assignment, you must delete the old assignment after you add the new assignment.


Show Buried Assignments

Shows assignments to buried logic cells, including I/O cells, in the Existing Pin/Location/Chip Assignments dialog box.

If Show Buried Assignments is turned off, only pin assignments are shown in the Existing Pin/Location/Chip Assignments dialog box.


Sort By

Specifies the order in which assignments are listed in the Existing Pin/Location/Chip Assignments box. You can sort assignments alphabetically by Node Name or by Assignment. If you select Assignment, nodes are listed in order by pin, logic cell, LAB, row, column, and anywhere on chip assignments.


Add/Change

Assigns the selected nodeor bus name shown in the Node Name box to the resource specified in the Chip Resource box and the chip shown in the Chip Name box. The new or updated assignment is listed in the Existing Pin/Location/Chip Assignments box.

The Add button changes into the Change button if you are editing an existing assignment. You do not need to choose Add or Change if you are editing only one assignment. Choosing OK always saves the current assignment shown under Chip Resource, as well as all assignments in the Existing Pin/Location/Chip Assignments box.

If you select an existing pin assignment, change the Chip Name or Pin Type, and choose Add, a new assignment is created. The previous assignment is not overwritten and both entries appear in the Existing Pin/Location/Chip Assignments box. This feature is useful for specifying assignments in partitioned projects or if pins are externally connected on MAX 7000 devices. If you simply wish to update the existing assignment, you must delete the old assignment after you add the new assignment.


OK

Saves all assignments and closes the dialog box.

If you are editing only one assignment, you do not need to choose Add or Change before choosing OK. Choosing OK always saves the current assignment displayed in the Node Name, Chip Name, and Chip Resource boxes, as well as all assignments shown in the Existing Pin/Location/Chip Assignments box.


Cancel
Cancel/Close

Closes the dialog box, saving only the assignments listed in the Existing Pin/Location/Chip Assignments box.

The Cancel button changes into the Close button if you have already saved all changes by choosing Add or Change.


Delete

Deletes the assignment selected in the Existing Pin/Location/Chip Assignments box.


Assign Device

Opens the Device dialog box, which allows you to assign the chip displayed in the Chip Name box to an Altera device or to AUTO (for automatic device selection).

Go to Devices & Adapters for information on all Altera devices.


Pin/Location/Chip dialog box

Click Button 1 on any item in this dialog box for information on that item:


Search Node Database Dialog Box (all applications)
Search Node Database Dialog Box

Lists nodes in the current project.

Search Node Database allows you to find any node in the compiled project, so that you can select its name and use it to enter an assignment. When you select one or more nodes from the list and choose OK, the selected node(s) are copied to the Node Name box of the next-higher-level Assign menu dialog box.

Until the project has been compiled, only nodes to which assignments have been made can be listed. You must compile the project before all existing nodes can be listed.

Click Button 1 on an item in this dialog box for information on that item:


Node Name; Search Node Database dialog box
Node Name

Specifies a node name or a text string containing wildcard characters. After you have chosen the List button to list names in the Names in Database box, selecting a node name in the Names in Database box copies it to the Node Name box. Selecting multiple names in the Names in Database box changes the text in the Node Name box to **-Multiple Items-**.


List; Search Node Database dialog box
List

Lists nodes in the current project that match the text string specified in the Node Name box and the node types selected under List Nodes of Type.

Until the project has been compiled, only nodes to which assignments have been made can be listed when you choose the List button. You must compile the project before all existing nodes can be listed.


Names in Database; Search Node Database dialog box
Names in Database

Lists nodes in the current project that match the text string specified in the Node Name box and the node types selected under List Nodes of Type.

You must choose List to display the node names. If Show All Node Name Synonyms is turned on, the Names in Database box also lists all possible hierarchical node names for each node that matches the text string in the Node Name box. Synonyms are proceeded by -> in the list.

Selecting one or more names in this box automatically copies the name(s) to the Node Name box. If you select a synonym for a name, the source name, not the synonym, is copied to the Node Name box. You can use area or object-by-object selection to select multiple names. Selecting multiple names changes the text in the Node Name box to **-Multiple Items-**.


List Node of Type; Search Node Database dialog box
List Nodes of Type

Specifies the node types to be listed in the Names in Database box. You can select one or more options or select all types to be listed.

Input	Lists all input nodes in the Names in Database box.

Output	Lists all output nodes in the Names in Database box.

Bidirectional	Lists all bidirectional nodes in the Names in Database box.

Registered	Lists all registered nodes in the Names in Database box.

Combinatorial	Lists all combinatorial nodes in the Names in Database box.

Memory	Lists all embedded cells in the Names in Database box.

All	Turns on all type options, i.e., lists all types of nodes in the Names in Database box. Turning this option off deselects all other Type options.


Show Only Functions Implemented in Logic Cells & Pins; Search Node Database dialog box
Show Only Functions Implemented in Logic Cells & Pins

Shows only the names of logic functions implemented in logic cells and pins in the Names in Database box..

If this option is turned off, all node and pin names are listed, regardless of whether they are implemented in logic cells and pins.


Show All Node Name Synonyms; Search Node Database dialog box
Show All Node Name Synonyms

Shows all possible hierarchical node names for each node or pin in the Names in Database box that match the text string in the Node Name box. Synonyms are preceded by -> in the list.

If this option is turned off, only the true source names for nodes are displayed in the list.

For more information on source names and synonyms, go to Devices & Adapters.


OK; Search Node Database dialog box
OK

Copies the name shown in the Node Name box and closes the Search Node Database dialog box. The copied name automatically appears in the Node Name box of the next-higher-level dialog box, i.e., the Pin/Location/Chip, Timing Requirements, Clique, Logic Options, Probe, or Connected Pins dialog box.


Search Node Database dialog box

Click Button 1 on an item in this dialog box for information on that item:


Timing Requirements Command (all applications)
Timing Requirements Command (Assign Menu)

Shortcuts

Assigns a timing requirement (i.e., enters a timing assignment) for tpd, tco, tsu, fmax, and/or timing cuts to one or more nodes, buses, and/or symbols in the current hierarchy tree.

Click Button 1 on an item in this dialog box for information on that item:

You can also specify global default timing requirements for the current project with Global Project Timing Requirements.

Refer to Guidelines for Timing Assignments for information the types of logic functions that can accept timing assignments and how the Compiler interprets and resolves timing assignments. For information on specific assignments to enter and other techniques to improve speed performance in your MAX+PLUS II projects, go to Guidelines for Achieving Maximum Speed Performance.

As an alternative to using the Timing Requirements command, you can enter timing assignments and timing cuts in the Timing Requirement Assignments Section of the ACF for the hierarchy tree.

In the Graphic Editor, timing assignments appear on the top left corner of a symbol (above any clique assignments) if Show Timing Assignments or Show All is turned on.

You should not enter Timing Requirements assignments for OrCAD Schematic Files. See Guidelines for Working with OrCAD Schematic Files for more information.

1.	Be sure to refer to Guidelines for Working with Assignments for absolutely essential information on using all types of resource, probe, and device assignments.

2.	The Timing Requirements command is used to control compilation. To tag nodes for timing analysis, use the Timing Source, Timing Destination, and Timing Cutoff commands.

See also:

Assigning Individual Timing Requirements

Clearing Assignments for a Project

Copying a Resource Assignment

Deleting an Assignment

Fitting & Refitting a Project

Selecting a Probe or Resource Assignment (Graphic Editor)

Showing Parameters and Probe & Resource Assignments (Graphic Editor)

Specifying Global Project Timing Requirements


Node Name; Timing Requirements dialog box
Node Name

Specifies the hierarchical node name or bus name to which the timing assignments will be applied.

If you selected a node, bus, or symbol before choosing Timing Requirements, its name is displayed. If you selected more than one node or symbol, the text **-Multiple Items-** is displayed.

You can choose Search to open the Search Node Database dialog box, which allows you to select a node name from the current hierarchy tree to copy to the Node Name box.


tpd; Timing Requirements dialog box
tpd

Specifies the maximum acceptable tpd for the node(s) or bus shown in the Node Name box.

The time you enter should be followed immediately (i.e., with no space in between) by a time unit; the default unit is ns.

If you selected multiple items with different existing tpd assignments before choosing Timing Requirements, ???? is displayed in the tpd box. Entering a new tpd assignment will change the tpd for all selected items.


tco; Timing Requirements dialog box
tco

Specifies the maximum acceptable tco for the node(s) shown in the Node Name box.

The time you enter should be followed immediately (i.e., with no space in between) by a time unit; the default unit is ns.

If you selected multiple items with different existing tco assignments before choosing Timing Requirements, ???? is displayed in the tco box. Entering a new tco assignment will change the tco for all selected items.


tsu; Timing Requirements dialog box
tsu

Specifies the maximum acceptable tsu for the node(s) or bus shown in the Node Name box.

The time you enter should be followed immediately (i.e., with no space in between) by a time unit; the default unit is ns.

If you selected multiple items with different existing tsu assignments before choosing Timing Requirements, ???? is displayed in the tsu box. Entering a new tsu assignment will change the tsu for all selected items.


fmax; Timing Requirements dialog box
fmax

Specifies the minimum acceptable fmax for the node(s) or bus shown in the Node Name box.

The time you enter should be followed immediately (i.e., with no space in between) by a time unit; the default unit is mhz.

If you selected multiple items with different existing fmax assignments before choosing Timing Requirements, ???? is displayed in the fmax box. Entering a new fmax assignment will change the fmax for all selected items.


Cut Timing Path; Timing Requirements dialog box
Cut Timing Path

Cuts the connections between the timing path for the node(s) or bus shown in the Node Name box and other nodes in the current hierarchy tree. If this option is turned on, the Compiler will not consider the delay along this path when it processes the timing requirements for the project; the signal path itself is not cut.

Cut Timing Path overrides any tpd, tsu, tco, or fmax assignment for a node.


Existing Timing Requirements; Timing Requirements dialog box
Existing Timing Requirements

Lists existing individual timing assignments for the current hierarchy tree. Assignments are listed in the order specified with the Sort By option.

You can select a timing requirement in this box to fill in the Node Name and Timing Requirements box(es) to show the current timing assignments for a node or bus. You can then edit the timing assignments and choose Change to update the Existing Timing Requirements box.


Sort By;Timing Requirements dialog box
Sort By

Specifies the order in which the timing assignments are listed in the Existing Timing Requirements box. You can sort assignments alphabetically by Node Name or by their timing assignments or timing cuts.

If you select tpd, tsu, tco, or fmax, timing assignments are sorted from fastest to slowest. For example, if tpd is selected, the node(s) with the fastest tpd setting are listed first and nodes with no tpd setting are listed last.


Add;Timing Requirements dialog box
Add/Change

Assigns the tpd, tco, tsu, fmax, and/or timing cuts specified in the Timing Requirements box to the node or bus name shown in the Node Name box. The new or updated timing requirement(s) are listed in the Existing Timing Requirements box.

The Add button changes into the Change button if you are editing an existing timing requirement assignment. You do not need to choose Add or Change if you are editing only one set of assignments for the node(s) or bus shown in the Node Name box. Choosing OK always saves the current assignment(s) shown under Timing Requirements, as well as all assignments in the Existing Timing Requirements box.


Delete;Timing Requirements dialog box
Delete

Deletes the timing assignments of the node selected in the Existing Timing Requirements box.


OK;Timing Requirements dialog box
OK

Saves all timing requirements and closes the dialog box.

If you are editing only one set of assignments for the node(s) or bus shown in the Node Name box, you do not need to choose Add or Change before choosing OK. Choosing OK always saves the current assignment(s) shown under Timing Requirements, as well as all assignments in the Existing Timing Requirements box.


Cancel;Timing Requirements dialog box
Cancel/Close

Closes the dialog box, saving only the assignments listed in the Existing Timing Requirements box.

The Cancel button changes into the Close button if you have already saved all changes by choosing Add or Change.


Timing Requirements dialog box

Click Button 1 on any item in this dialog box for information on that item:


Clique Command (all applications)
Clique Command (Assign Menu)

Shortcuts

Defines one or more selected logic functions as part of a single unit to be fitted into the same LAB, row, or chip.

A clique is a resource assignment that specifies which logic functions must remain together, regardless of their exact location. Cliques allow you to partition a project so that only a minimum number of signals travel between LABs, rows, and devices, and to ensure that no unnecessary delays exist on critical timing paths.

You cannot assign pins to a clique.

If possible, all clique members are assigned to the same LAB. If the clique members will not fit into a single LAB, they are placed in the same row (FLEX 10K, FLEX 8000, and MAX 9000 devices only) or the same device.

After compilation, the Clique Assignments Section of the Report File shows how the Compiler implemented cliques in your project.

Click Button 1 on any item in this dialog box for information on that item:

As an alternative to using the Clique command, you can enter clique assignments in the Clique Assignments Section of the ACF for the hierarchy tree.

In the Graphic Editor, a clique assignment appears on the top left corner of a symbol (below any timing assignments) if Show Cliques or Show All is turned on.

You should not enter clique assignments for OrCAD Schematic Files. See Guidelines for Working with OrCAD Schematic Files for more information.

Be sure to refer to Guidelines for Working with Assignments for absolutely essential information on using all types of resource, probe, and device assignments.

See also:

Assigning a Clique

Back-Annotating Assignments for a Project

Clearing Assignments for a Project

Copying a Resource Assignment

Deleting an Assignment

Fitting & Refitting a Project

Guidelines for Achieving Maximum Speed Performance

Moving a Probe or Resource Assignment

Partitioning a Project

Selecting a Node, Pin, or Other Object (Floorplan Editor)

Showing Parameters and Probe & Resource Assignments

Recommended reading:

AB93 (Partitioning a Project with MAX+PLUS II Software)


Node Name; Clique dialog box
Node Name

Specifies the hierarchical node name  or bus name to which the clique assignments will be applied.

If you selected a node, bus, or symbol before choosing Clique, its name is displayed. If you selected more than one node or symbol, the text **-Multiple Items-** is displayed.

You can choose Search to open the Search Node Database dialog box, which allows you to select a node name from the current hierarchy tree to copy to the Node Name box.


Clique Name;Clique dialog box
Clique Name

Specifies the clique name for the node name(s) shown in the Node Name box.

You can either type a name with up to 32 name characters to create a new clique, or select an existing name from the drop-down list box to add the currently selected item(s) to an existing clique.


Existing Clique Assignments;Clique dialog box
Existing Clique Assignments

Lists the existing clique assignments for the current hierarchy tree. Assignments are listed in the order specified with the Sort By option.

You can select a clique assignment in this box to fill in the Node Name and Clique Name box(es) to show the current clique assignment for a node. You can then edit the clique assignment and choose Change to update the Existing Clique Assignments box.


Sort By;Clique dialog box
Sort By

Specifies the order in which assignments are listed in the Existing Clique Assignments box. You can sort assignments alphabetically by Node Name or Clique Name.


OK;Clique dialog box
OK

Saves all clique assignments and closes the dialog box.

If you are editing only one assignment, you do not need to choose Add or Change before choosing OK. Choosing OK always saves the assignment displayed in the Node Name and Clique Name boxes, as well as al assignments in the Existing Clique Assignments box.


Cancel; Device dialog box
Cancel/Close

Closes the dialog box, saving only the assignments listed in the Existing Clique Assignments box.

The Cancel button changes into the Close button if you have already saved all changes in the Existing Clique Assignments dialog box by choosing Add or Change.


Add/Change;Clique dialog box
Add/Change

Adds the node or bus names shown in the Node Name box to the clique specified in the Clique Name box. The new or updated clique assignment is listed in the Existing Clique Assignments box.

The Add button changes into the Change button if you are editing an existing assignment. If you are editing only one assignment, you do not need to choose Add or Change before choosing OK. Choosing OK always saves the current assignment displayed in the Node Name and Clique Name boxes, as well as all assignments in the Existing Clique Assignments box.


Delete;Clique dialog box.
Delete

Deletes a clique assignment selected in the Existing Clique Assignments box.


Clique dialog box

Click Button 1 on any item in this dialog box for information on that item:


Logic Options Command (all applications)
Logic Options Command (Assign Menu)

Shortcuts

Assigns a logic synthesis style and/or logic options that control how the Compiler synthesizes logic for one or more nodes, buses, and/or symbols in the current hierarchy tree.

Click Button 1 on any item in this dialog box for information on that item:

Each project has a default logic synthesis style that is specified with Global Project Logic Synthesis. The assignments you enter with Logic Options override this default style.

As an alternative to using the Logic Options command, you can enter logic synthesis style and individual logic option assignments in the Logic Options Section of the ACF for the hierarchy tree.

In the Graphic Editor, a logic option or style assignment appears on the bottom right corner of a symbol if Show Logic Options or Show All is turned on.

You should not enter logic option assignments for OrCAD Schematic Files. See Guidelines for Working with OrCAD Schematic Files for more information.

1.	Altera recommends assigning logic synthesis styles rather than individual logic options whenever possible. When both types of assignments are used, the Compiler combines the assignments according to Logic Synthesis Style & Logic Option Rules.

2.	Be sure to refer to Guidelines for Working with Assignments for absolutely essential information on using all types of resource, probe, and device assignments.

3.	Some logic options are not available with standard synthesis.

See also:

Assigning an Individual Logic Option or Synthesis Style

Back-Annotating Assignments for a Project

Clearing Assignments for a Project

Copying a Resource Assignment

Deleting an Assignment

Fitting & Refitting a Project

Selecting a Node, Pin, or Other Object (Floorplan Editor)

Showing Parameters and Probe & Resource Assignments (Graphic Editor)

Specifying Global Project Logic Synthesis Settings

Recommended reading:

AB93 (Partitioning a Project with MAX+PLUS II Software)


--------------------BEGINNING OF NON-TRANSLATED TEXT-----------------------------------------------

The segmented hypergraphics for Logic Options and Global Project Logic Synthsis share the following Define Synthesis Style popup.

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Define Synthesis Style

Opens the Define Synthesis Style dialog box, which allows you to create and edit your own logic synthesis styles to control how the Logic Synthesizer processes the logic for your project.


Node Name;Logic Options dialog box
Node Name

Specifies the hierarchical node name or bus name to which the logic option assignment(s) will be applied.

If you selected a node, bus, or symbol before choosing Logic Options, its name is displayed. If you selected more than one node or symbol, the text **-Multiple Items-** is displayed.

You can choose Search to open the Search Node Database dialog box, which allows you to select a node name from the current hierarchy tree to copy to the Node Name box.


Style

Specifies the logic synthesis style assigned to the node or bus name(s) shown in the Node Name box. The Style drop-down list box lists all Altera-provided and user-defined styles for the current hierarchy tree.

Selecting <none> from the drop-down list box removes any existing style assignment.


Individual Synthesis Options button
Individual Logic Options

Opens the Individual Logic Options dialog box, which allows you to specify individual logic options for the node or bus name(s) shown in the Node Name box.


Existing Logic Option Assignments;Logic Options dialog box
Existing Logic Option Assignments

Lists the existing individual logic option assignments for the current hierarchy tree. Assignments are listed in the order specified with the Sort By option.

You can select a logic option assignment in this box to fill in the Node Name and Style boxes to show the current logic option assignments for a node or bus. You can then edit the logic option assignments and choose Change to update the Existing Logic Option Assignments box.


Sort By;Logic Options dialog box
Sort By

Specifies the order in which the logic option assignments are listed in the Existing Logic Option Assignments box. You can sort assignments alphabetically by Node Name or Logic Option.


Add/Change;Logic Options dialog box
Add/Change

Assigns the logic synthesis style displayed in the Style box to the node or bus name(s) shown in the Node Name box. The new or updated logic option assignment(s) are listed in the Existing Logic Option Assignments box.

The Add button changes into the Change button if you are editing an existing assignment. You do not need to choose Add or Change if you are editing only one assignment. Choosing OK always saves the current assignment shown in the Style box, as well as all assignments in the Existing Logic Option Assignments box.


OK; Logic Options dialog box
OK

Saves all logic option assignments and closes the dialog box.

If you are editing only one assignment, you do not need to choose Add or Change before choosing OK. Choosing OK always saves the current assignment shown in the Style box, as well as all assignments in the Existing Logic Option Assignments box.


Delete;Logic Options dialog box
Delete

Deletes the logic assignment(s) selected in the Existing Logic Option Assignments box.


Cancel; Logic Options dialog box
Cancel/Close

Closes the dialog box, saving only the assignments listed in the Existing Logic Option Assignments box.

The Cancel button changes into the Close button if you have already saved all changes by choosing Add or Change.


Logic Options dialog box

Click Button 1 on any item in this dialog box for information on that item:


Define Synthesis Style Dialog Box (all applications)
Define Synthesis Style Dialog Box

Creates or changes logic synthesis styles.

You open the Define Synthesis Style dialog box by choosing the Define Synthesis Style button in the Logic Options or Global Project Logic Synthesis dialog box. This dialog box allows you to create your own logic synthesis styles, which can be applied to individual logic functions in design files, or to the project as a whole. These styles control how the Compilers Logic Synthesizer module processes the logic for your project.

Define Synthesis Style allows you to create a style that specifies any combination of logic options. The style you create can define the behavior of some or all of the available options. Whether or not you choose to define the behavior of all options should depend on how you plan to use the style:

When you create a style to apply to the project as a whole, you should specify a non-default setting for each option. If you use a default setting in a project-wide style, the Logic Synthesizer substitutes the corresponding setting from the Altera-provided Normal style during compilation.

When you create a style to apply to individual logic functions, you should specify the default setting for all options that are not immediately relevant. If a style contains these default settings, the Compiler uses settings that are specified elsewhere, according to Logic Synthesis Style & Logic Option Rules.

The Define Synthesis Style dialog box uses three-way checkboxes and radio buttons to specify logic options and default settings. Click Button 1 on any item in this dialog box for information on that item:

As an alternative to using the Define Synthesis Style dialog box, you can define synthesis styles in the Logic Synthesis Style Definition of the ACF for the hierarchy tree.

1.	Altera does not recommend editing the settings for the Altera-provided Normal, Fast, and WYSIWYG logic synthesis styles. If you edit the settings in these styles, save the new settings to a different style name.

2.	The predefined Normal, Fast, and WYSIWYG logic synthesis styles in pre-version 5.2 releases of MAX+PLUS II did not include most of the logic options available in multi-level synthesis. To take advantage of all logic options in projects created with earlier versions of MAX+PLUS II, you should choose the Use Default button in the Advanced Options dialog box (accessible from the Define Synthesis Style dialog box) to update the style definitions and thus turn on more of these logic options.

See also:

Assigning an Individual Logic Option or Synthesis Style

Defining a Logic Synthesis Style

Fitting & Refitting a Project

Specifying Global Project Logic Synthesis Settings


Style; Define Synthesis Style dialog box
Style

Specifies the name of the logic synthesis style to edit. You can choose <new> to create a new style. You can also select any existing style, edit it, and save the changes to the same style name or to a new name.

If you select a different style after editing the current style, MAX+PLUS II always asks whether you wish to save the changes.


Device Family; Define Synthesis Style dialog box
For Device Family

Specifies the device family for the selected style in the Style box and its associated logic option settings. The same logic synthesis style name can have different logic option settings for different device families.

Option settings under Family Specific Options are not available if they do not apply to the current device family.


Minimization; Define Synthesis Style dialog box
Minimization

Specifies the Full, Partial, or Default setting for the Minimization logic option.

If you select Default, the Minimization setting is determined by the project-wide default logic synthesis style, which is specified with Global Project Logic Synthesis.


Slow Slew Rate; Define Synthesis Style dialog box
Slow Slew Rate

Specifies the on, off, or default setting for the Slow Slew Rate logic option.

If you select the default (grayed) setting, the Slow Slew Rate setting is determined by the project-wide default logic synthesis style, which is specified with Global Project Logic Synthesis.

This option setting is not available if it does not apply to the device family displayed in the For Device Family box. In addition, this option is ignored if standard synthesis is specified with the Global Project Logic Synthesis command.


XOR Synthesis; Define Synthesis Style dialog box
XOR Synthesis

Specifies the on, off, or default setting for the XOR Synthesis logic option.

If you select the default (grayed) setting, the XOR Synthesis setting is determined by the project-wide default logic synthesis style, which is specified with Global Project Logic Synthesis.

This option setting is not available if it does not apply to the device family displayed in the For Device Family box.


Turbo Bit; Define Synthesis Style dialog box
Turbo Bit

Specifies the on, off, or default setting for the logic cell Turbo Bit logic option.

If you select the default (grayed) setting, the Turbo Bit setting is determined by the project-wide default logic synthesis style, which is specified with Global Project Logic Synthesis.

This option setting is not available if it does not apply to the device family displayed in the For Device Family box.


Parallel Expanders; Define Synthesis Style dialog box
Parallel Expanders

Specifies the on, off, or default setting for the Parallel Expanders logic option.

If you select the default (grayed) setting, the Parallel Expanders setting is determined by the project-wide default logic synthesis style, which is specified with Global Project Logic Synthesis.

This option setting is not available if it does not apply to the device family displayed in the For Device Family box.


Ignore SOFT Buffers; Define Synthesis Style dialog box
Ignore SOFT Buffers

Specifies the on, off, or default setting for the Ignore SOFT Buffers logic option.

If you select the default (grayed) setting, the Ignore SOFT Buffers setting is determined by the project-wide default logic synthesis style, which is specified with Global Project Logic Synthesis.

This option setting is not available if it does not apply to the device family displayed in the For Device Family box.


Use LPM for AHDL Operators; Define Synthesis Style dialog box
Use LPM for AHDL Operators

Specifies the on, off, or default setting for the Use LPM for AHDL Operators logic option.

If you select the default (grayed) setting, the Use LPM for AHDL Operators setting is determined by the project-wide default logic synthesis style, which is specified with Global Project Logic Synthesis.

This option setting is not available if it does not apply to the device family displayed in the For Device Family box.


Cascade Chain; Define Synthesis Style dialog box
Cascade Chain

Specifies the Auto, Manual, Ignore, or Default setting for the Cascade Chain logic option.

If you select Auto, you can limit the maximum length of a cascade chain by typing a whole non-zero number in the Max. Length box. The upper limit on the cascade chain length depends on the resources available in the target device(s) for the project. If you select Default, the Cascade Chain setting is determined by the project-wide default logic synthesis style, which is specified with Global Project Logic Synthesis.

This option setting is not available if it does not apply to the device family displayed in the For Device Family box. In addition, this option is ignored if standard synthesis is specified with the Global Project Logic Synthesis command.


Carry Chain; Define Synthesis Style dialog box
Carry Chain

Specifies the Auto, Manual, Ignore, or Default setting for the Carry Chain logic option.

If you select Auto, you can limit the maximum length of a carry chain by typing a whole non-zero number in the Max. Length box. The upper limit on the carry chain length depends on the resources available in the target device(s) for the project. If you select Default, the Carry Chain setting is determined by the project-wide default logic synthesis style, which is specified with Global Project Logic Synthesis.

This option setting is not available if it does not apply to the device family displayed in the For Device Family box. In addition, this option is ignored if standard synthesis is specified with the Global Project Logic Synthesis command.


Save Style As; Define Synthesis Style dialog box
Save Style As

Opens the Save Style As dialog box, which allows you to save the current logic option settings to a new logic synthesis style name.

You do not need to choose Save Style As to save changes to an existing style.


Delete Style; Define Synthesis Style dialog box
Delete Style

Deletes the logic synthesis style name shown in the Style box.

You cannot delete the <new>, Normal, Fast, or WYSIWYG styles.


OK; template for second and third-level dialog boxes
OK

Saves all changes and closes the dialog box. You are returned to the Logic Options or Global Project Logic Synthesis dialog box.


Cancel; template for second and third-level dialog boxes
Cancel

Closes the dialog box without saving any changes and returns you to the Logic Options or Global Project Logic Synthesis dialog box.


Use Default; Define Synthesis Style dialog box
Use Default

Changes logic option settings to a default state.

If the current style shown in the Style box is an Altera-provided style, Use Default changes all settings to those specified in the predefined Altera settings for the style. If the current style shown in the Style box is a user-defined style, all radio button and three-way checkbox options are set to the default state.


Advanced Options; Define Synthesis Style command
Advanced Options

Opens the Advanced Options dialog box, which allows you to specify the settings for advanced logic options for the current device family.


Define Synthesis Style dialog box

Click Button 1 on any item in this dialog box for information on that item:


Save Style As Dialog Box (all applications)
Save Style As Dialog Box

Saves the current logic option settings entered in the Define Synthesis Style and Advanced Options dialog boxes to a new logic synthesis style style name.

You open the Save Style As dialog box by choosing the Save Style As button in the Define Synthesis Style dialog box.

Click Button 1 on any item in this dialog box for information on that item:

When you save a style, the logic option settings for each different device family, as shown in the Define Synthesis Style and Advanced Options dialog boxes, are saved to the specified style name.

Altera does not recommend editing the logic option settings for the Altera-provided Normal, Fast, and WYSIWYG logic synthesis styles. If you edit the settings in these styles, save the new settings to a different style name.

See also:

Defining a Logic Synthesis Style


Style Name; Save Style As dialog box
Style Name

Specifies the name of the logic synthesis style to be saved. You can type a name with up to 32 name characters in the Style Name box and choose OK to save the current logic option settings to that style name.


OK; template for second and third-level dialog boxes
OK

Saves the logic option settings under the specified logic synthesis style name shown in the Style Name box and returns you to the Define Synthesis Style dialog box.


OK; template for second and third-level dialog boxes
Cancel

Closes the dialog box without saving any changes and returns you to the Define Synthesis Style dialog box.


Save Style As dialog box

Click Button 1 on any item in this dialog box for information on that item:


Advanced Options Dialog Box (all applications)
Advanced Options Dialog Box

Assigns advanced logic options that control how the Compiler synthesizes logic for one or more nodes and/or symbols in the current hierarchy tree.

You open the Advanced Options dialog box by choosing the Advanced Options button in the Define Synthesis Style or Individual Logic Options dialog box.

The behavior of the dialog box depends on when you open it. If you open the Advanced Options dialog box from the Define Synthesis Style dialog box, the option settings you enter are incorporated into the current logic synthesis style. If you open the Advanced Options dialog box from the Individual Logic Options dialog box, the option settings are applied to one or more selected logic functions.

The Advanced Options dialog box uses three-way checkboxes to specify logic options and default settings. Click Button 1 on any item in this dialog box for information on that item:

In most cases, you can obtain good results with the advanced logic option settings provided in the Altera-provided Normal, Fast, and WYSIWYG logic synthesis styles. You should only change the settings for advanced logic options in a style if you have problems with achieving a satisfactory fit for your project.

As an alternative to using the Advanced Options dialog box, you can specify advanced logic options in the Global Project Synthesis/Assignment Options Section of the ACF for the hierarchy tree.

1.	Altera does not recommend editing the logic option settings for the Altera-provided Normal, Fast, and WYSIWYG logic synthesis styles. If you edit the settings in these styles, save the new settings to a different style name.

2.	All advanced logic options are ignored if standard synthesis is specified with the Global Project Logic Synthesis command.

See also:

Assigning an Individual Logic Option or Synthesis Style

Defining a Logic Synthesis Style

Fitting & Refitting a Project

Specifying Global Project Logic Synthesis Settings


SOFT Buffer Insertion; Advanced Options dialog box
SOFT Buffer Insertion

Specifies the on, off, or default setting for the SOFT Buffer Insertion logic option.

If you select the default (grayed) setting, the SOFT Buffer Insertion setting is determined by the project-wide default logic synthesis style, which is specified with Global Project Logic Synthesis.


Decompose Gates; Advanced Options dialog box
Decompose Gates

Specifies the on, off, or default setting for the Decompose Gates logic option.

If you select the default (grayed) setting, the Decompose Gates setting is determined by the project-wide default logic synthesis style, which is specified with Global Project Logic Synthesis.


Reduce Logic; Advanced Options dialog box
Reduce Logic

Specifies the on, off, or default setting for the Reduce Logic logic option.

If you select the default (grayed) setting, the Reduce Logic setting is determined by the project-wide default logic synthesis style, which is specified with Global Project Logic Synthesis.


Duplicate Logic Extraction; Advanced Options dialog box
Duplicate Logic Extraction

Specifies the on, off, or default setting for the Duplicate Logic Extraction logic option.

If you select the default (grayed) setting, the Duplicate Logic Extraction setting is determined by the project-wide default logic synthesis style, which is specified with Global Project Logic Synthesis.


NOT Gate Push-Back; Advanced Options dialog box
NOT Gate Push-Back

Specifies the on, off, or default setting for the NOT Gate Push-Back logic option.

If you select the default (grayed) setting, the NOT Gate Push-Back setting is determined by the project-wide default logic synthesis style, which is specified with Global Project Logic Synthesis.


Refactorization; Advanced Options dialog box
Refactorization

Specifies the on, off, or default setting for the Refactorization logic option.

If you select the default (grayed) setting, the Refactorization setting is determined by the project-wide default logic synthesis style, which is specified with Global Project Logic Synthesis.


Subfactor Extraction; Advanced Options dialog box
Subfactor Extraction

Specifies the on, off, or default setting for the Subfactor Extraction logic option.

If you select the default (grayed) setting, the Subfactor Extraction setting is determined by the project-wide default logic synthesis style, which is specified with Global Project Logic Synthesis.


Multi-Level Factoring; Advanced Options dialog box
Multi-Level Factoring

Specifies the on, off, or default setting for the Multi-Level Factoring logic option.

If you select the default (grayed) setting, the Multi-Level Factoring setting is determined by the project-wide default logic synthesis style, which is specified with Global Project Logic Synthesis.


Resynthesize Network; Advanced Options dialog box
Resynthesize Network

Specifies the on, off, or default setting for the Resynthesize Network logic option.

If you select the default (grayed) setting, the Resynthesize Network setting is determined by the project-wide default logic synthesis style, which is specified with Global Project Logic Synthesis.


Register Optimization; Advanced Options dialog box
Register Optimization

Specifies the on, off, or default setting for the Register Optimization logic option.

If you select the default (grayed) setting, the Register Optimization setting is determined by the project-wide default logic synthesis style, which is specified with Global Project Logic Synthesis.


Use Default; Advanced Options Dialog Box
Use Default

Changes logic option settings to a default state. The action of this button depends on how you opened the Advanced Options dialog box:

If you opened the Advanced Options dialog box from the Define Synthesis Style dialog box, the Use Default button changes as follows:

-	If the current style is a user-defined style, Use Default changes all three-way checkboxes and radio buttons to their default settings.

-	If the current style is the Altera-provided Normal, Fast, or WYSIWYG style, Use Default changes all settings to the predefined settings for that style for the current device family.

If you opened the Advanced Options dialog box from the Individual Logic Options dialog box, the Use Default button changes all logic option settings to the default setting.


OK; Advanced Options dialog box
OK

Temporarily saves changes and closes the dialog box. You are returned to the Define Synthesis Style or Individual Logic Options dialog box. Changes made in the Advanced Options dialog box are saved permanently only if you save the changes to the current logic synthesis style in the Define Synthesis Style dialog box, or if you choose OK in the Individual Logic Options dialog box.


OK; Advanced Options dialog box
Cancel

Closes the dialog box without saving any changes and returns you to the Define Synthesis Style or Individual Logic Options dialog box.


Advanced Options Dialog Box popup
Advanced Options dialog box

Click Button 1 on any item in this dialog box for information on that item:


Individual Logic Options Dialog Box (all applications)
Individual Logic Options Dialog Box

Assigns individual logic options that control how the Compiler synthesizes logic for one or more nodes, buses, and/or symbols in the current hierarchy tree.

You open the Individual Logic Options dialog box by choosing the Individual Logic Options button in the Logic Options dialog box.

The Individual Logic Options dialog box uses three-way checkboxes and radio buttons to specify logic options and default settings. Click Button 1 on any item in this dialog box for information on that item:

As an alternative to using the Individual Logic Options dialog box, you can specify logic options in the Global Project Synthesis/Assignment Options Section of the ACF for the hierarchy tree.

Some logic options are not available with standard synthesis.

See also:

Assigning an Individual Logic Option or Synthesis Style

Back-Annotating Assignments for a Project

Clearing Assignments for a Project

Copying a Resource Assignment

Deleting an Assignment

Fitting & Refitting a Project

Selecting a Node, Pin, or Other Object (Floorplan Editor)

Specifying Global Project Logic Synthesis Settings


Minimization checkbox option
Minimization

Specifies the Full, Partial, or Default setting for the Minimization logic option.


Slow Slew Rate checkbox option
Slow Slew Rate

Specifies the on, off, or default setting for the Slow Slew Rate logic option.


XOR Synthesis checkbox option
XOR Synthesis

Specifies the on, off, or default setting for the XOR Synthesis logic option.


Turbo Bit checkbox option
Turbo Bit

Specifies the on, off, or default setting for the logic cell Turbo Bit logic option.


Hierarchical Synthesis checkbox option
Hierarchical Synthesis

Specifies the on, off, or default setting for the Hierarchical Synthesis logic option.


Implement as Output of Logic Cell checkbox option
Implement as Output of Logic Cell

Specifies the on, off, or default setting for the Implement as Output of Logic Cell logic option.


Insert Additional Logic Cell checkbox option
Insert Additional Logic Cell

Specifies the on, off, or default setting for the Insert Additional Logic Cell logic option.


Parallel Expanders checkbox option
Parallel Expanders

Specifies the on, off, or default setting for the Parallel Expanders logic option.


Ignore SOFT Buffers checkbox option
Ignore SOFT Buffers

Specifies the on, off, or default setting for the Ignore SOFT Buffers logic option.


Use LPM for AHDL Operators checkbox option
Use LPM for AHDL Operators

Specifies the on, off, or default setting for the Use LPM for AHDL Operators logic option.


Implement in EAB checkbox option
Implement in EAB

Specifies the on, off, or default setting for the Implement in EAB logic option.


I/O Cell Register checkbox option
I/O Cell Register

Specifies the on, off, or default setting for the I/O Cell Register logic option.


Cascade Chain

Specifies the Auto, Manual, Ignore, or Default setting for the Cascade Chain logic option.


Carry Chain checkbox option
Carry Chain

Specifies the Auto, Manual, Ignore, or Default setting for the Carry Chain logic option.


OK; Individual Synthesis Options dialog box
OK

Saves all changes and closes the dialog box. You are returned to the Logic Options dialog box. The new or updated logic options settings are listed in the Existing Logic Option Assignments box in the Logic Options dialog box.


OK; Individual Synthesis Options dialog box
Cancel

Closes the dialog box without saving any changes and returns you to the Logic Options dialog box.


Use Default checkbox option
Use Default

Changes all three-way checkboxes and radio buttons to their default settings.


Advanced Options button, Individual Synthesis Options dialog box
Advanced Options

Opens the Advanced Options dialog box, which allows you to specify the settings for advanced logic options.


Individual Logic Options dialog box

Click Button 1 on any item in this dialog box for information on that item:


Probe Command (all applications)
Probe Command (Assign Menu)

Shortcuts

Attaches a unique probe name to a single input or output node of a primitive or macrofunction.

Click Button 1 on any item in this dialog box for information on that item:

As an alternative to using the Probe command, you can assign probes in the Probe Assignments Section of the ACF for the hierarchy tree.

In the Graphic Editor, a probe assignment appears next to a pinstub of the symbol to which it is assigned if Show Probes or Show All is turned on.

You should not enter probe assignments for OrCAD Schematic Files. See Guidelines for Working with OrCAD Schematic Files for more information.

Be sure to refer to Guidelines for Working with Assignments for absolutely essential information on using all types of resource, probe, and device assignments.

See also:

Assigning a Probe

Clearing Assignments for a Project

Deleting an Assignment

Moving a Probe or Resource Assignment

Selecting a Pinstub (Graphic Editor)

Selecting a Node, Pin, or Other Object (Floorplan Editor)

Showing Parameters and Probe & Resource Assignments (Graphic Editor)


Probe Name

Specifies the name of the probe to be assigned to the node name shown in the Node Name box.

You can type a name with up to 32 name characters to create a new probe, or select an existing name from the drop-down list box to move an existing probe to the currently selected node or pinstub.


Node Name

Specifies the hierarchical node name which the probe assignment will replace.

If you selected a node or a symbol pinstub before choosing Probe, its name is displayed. You can choose Search to open the Search Node Database dialog box, which allows you to select a node name from the current hierarchy tree to copy to the Node Name box.


Existing Probe Assignments

Lists the existing probe assignments for the current hierarchy tree. Assignments are listed in the order specified with the Sort By option.

You can select an assignment in this box to fill in the Node Name and Probe Name boxes to show the current probe assignment for a node. You can then edit the assignment and choose Change to update the Existing Probe Assignments box.


Sort By;Probe dialog box
Sort By

Specifies the order in which the probe assignments are listed in the Existing Probe Assignments box. You can sort assignments alphabetically by Node Name or Probe Name.


Add/Change; Probe dialog box
Add/Change

Assigns the probe name displayed in the Probe Name box to the node names shown in the Node Name box. The new or updated probe assignment is listed in the Existing Probe Assignments box.

The Add button changes into the Change button if you are editing an existing probe assignment. You do not need to choose Add or Change if you are editing only one assignment. Choosing OK always saves the current assignment shown in the Probe Name box, as well as all assignments in the Existing Probe Assignments box.


Delete;Probe dialog box
Delete

Deletes the probe assignment selected in the Existing Device Assignments box.

Only the probe assignment is deleted, the node name that was assigned to the probe is not. If you wish, you can assign the node name to a different probe name.


OK; Device dialog box
OK

Saves all probe assignments shown in the Existing Probe Assignments box and closes the dialog box.


Cancel; Device dialog box
Cancel/Close

Closes the dialog box, saving only the assignments listed in the Existing Probe Assignments box.

The Cancel button changes into the Close button if you have already saved all changes in the Existing Probe Assignments dialog box by choosing Add or Change.


Probe dialog box

Click Button 1 on any item in this dialog box for information on that item:


Connected Pins Command (all applications)
Connected Pins Command (Assign Menu)

Shortcuts

Assigns one or more pins in the current hierarchy tree to a connected pin group that specifies which pins are connected together on your circuit board.

Creating connected pin groups with Connected Pins is useful for preparing single- and multi-device projects for timing simulation and linked simulation. Connected pin assignments can also have a limited effect on manual partitioning.

Click Button 1 on any item in this dialog box for information on that item:

As an alternative to using the Connected Pins command, you can specify connected pin assignments in the Connected Pin Assignments Section of the ACF for the hierarchy tree or with the external connection pin primitives--INPUTC, OUTPUTC, and BIDIRC--that are available in Graphic Editor files.

If you compile a project to create a timing SNF, connected pin assignments are required for all inter-device connections. They are not required to indicate inter-device connections if a top-level super-project design file is compiled to create a linked SNF, except in the following cases (which also apply to timing SNFs):

You can tie bidirectional pins together into a bidirectional bus. The Simulator can simulate the behavior of the bidirectional bus and detect logic contention errors.

Global Clock and Output Enable signals can be generated within a project. These signals can be routed through an output pin and back into an appropriate dedicated global input pin.

When you need to implement a global signal and a logic signal on one pin in a device that does not support this capability, two separate pins can be used (one for each signal) and tied together.

You cannot connect pins externally for hardware-assisted functional simulation or functional testing when multiple bidirectional or output pins are tied together.

You can also use connected pin assignments to guide partitioning. If you wish to manually partition a project so that each individual macrofunction is implemented in a different device from the same device family, you can assign each macrofunction to a different chip. You can then use the connected pin assignments to tie the macrofunctions inputs and outputs together and specify which pins are connected together on your board.

You must also make the appropriate chip assignments on the pin primitives. The connected pin assignments change the outcome of partitioning only if the macrofunctions have combinatorial outputs that might otherwise be placed in a different device by logic synthesis. In these cases, the connected pin assignments prevent the Compiler from moving logic to a different chip. If the macrofunctions have combinatorial outputs, as an alternative to using connected pin assignments, you can place LCELL buffers on the combinatorial macrofunction outputs and assign them to the chip that contains the source macrofunction.

1.	If you have already created separate projects that use devices from one or more device families, you can create a top-level super-project that contains instances of each of the individual sub-projects, and use ordinary node connections rather than Connected Pins to indicate board-level interconnections. Connected pin assignments are needed only in the cases described above if a super-project is compiled to create a linked SNF.

2.	Connecting the external connection pinstub of INPUTC, OUTPUTC, and BIDIRC primitives in a Graphic Editor file automatically creates a connected pin group that appears in the Connected Pins dialog box and in the Connected Pin Assignments Section of the ACF for the hierarchy tree.

When you compile a project that has external pin connections, the connected pins are listed in the Multiple Pin Connections Section of the Report File.

See also:

Assigning Connected Pins

Assigning a Pin, Location, or Chip


Connected Pins dialog box

Click Button 1 on any item in this dialog box for information on that item:


Node Name;Logic Options dialog box
Node Name

Specifies the hierarchical node bus, or pin name(s) to be assigned to the connected pin group.

If you selected a node, bus, or symbol before choosing Connected Pins, its name is displayed. If you selected more than one node or symbol, the text **-Multiple Items-** is displayed.

You can choose Search to open the Search Node Database dialog box, which allows you to select a node name from the current hierarchy tree to copy to the Node Name box.


Pin Type
Pin Type (Only for Special Cases)

Specifies the type of the current pin. If you have previously compiled the project, MAX+PLUS II automatically displays the pin type as Input, Output, or Bidir. Otherwise, the pin type is shown as Unspecified.

In most cases you do not need to edit the Pin Type and can leave it as Unspecified. You must specify Pin Type in the following cases:

For signals that travel between devices in a multi-device project, you must specify the Pin Type to distinguish the output of one device from the input(s) to other devices. In FLEX 8000 devices, you can also optionally assign the logic cell that feeds a device output to a location.

When an output and input pin on a MAX 7000 device are wired together to drive an Output Enable signal, you must specify the Pin Type to distinguish the output from the input.


Connected Pin Group; Connected Pins dialog box
Connected Pin Group

Specifies the name of the connected pin group for the node, bus, and pin name(s) shown in the Node Name box.

You can either type a name with up to 32 name characters to create a new connected pin group, or select an existing connected pin group from the drop-down list box to add the currently selected item(s) to an existing group.


Existing Connected Pin Groups; Connected Pins dialog box
Existing Connected Pin Groups

Lists the existing connected pin groups for the current hierarchy tree. Connected pin groups are listed alphabetically by name.

You can select an existing node or bus and its connected pin group assignment in the Existing Connected Pin Groups box to fill in the Node Name and Connected Pin Group boxes to show its current assignments. You can then edit the assignment and choose Change to update the Existing Connected Pin Groups box.


Add/Change; Connected Pins dialog box
Add/Change

Assigns the node or bus name(s) shown in the Node Name box to the connected pin group name displayed in the Connected Pin Group box. The new or updated connected pin group name is listed in the Existing Connected Pin Groups box.

The Add button changes into the Change button if you are editing an existing connected pin group. You do not need to choose Add or Change if you are editing only one assignment. Choosing OK always saves the current assignment shown in the Node Name and Connected Pin Group boxes, as well as all assignments in the Existing Connected Pin Groups box.


Delete;Device dialog box
Delete

Deletes the node, bus, or connected pin group selected in the Existing Connected Pin Groups box.


OK; Device dialog box
OK

Saves all connected pin groups and closes the dialog box.

If you are editing only one assignment, you do not need to choose Add or Change before choosing OK. Choosing OK always saves the assignment displayed in the Node Name, Pin Type (Only for Special Cases), and Connected Pin Group boxes, as well as all assignments in the Existing Connected Pin Groups box.


Cancel; Device dialog box
Cancel/Close

Closes the dialog box, saving only the assignments listed in the Existing Connected Pin Groups box.

The Cancel button changes into the Close button if you have already saved all changes in the Existing Connected Pin Groups dialog box by choosing Add or Change.


Global Project Device Options Command (all applications)
Global Project Device Options Command (Assign Menu)

Specifies the global default device options for all devices used in the current project. This command also specifies the percentage of all device pin and/or logic cell resources in the project to remain unused, i.e., reserved. Device resources can be reserved if you wish to leave additional logic capacity for future use.

The Global Project Device Options dialog box differs depending on the current device family. Select the appropriate dialog box:

Classic & MAX Global Project Device Options

FLEX 8000 Global Project Device Options

FLEX 10K Global Project Device Options

Global Project Device Options specifies defaults that apply only to those devices for which no explicit device option settings are specified. You can override the default settings on a device-by-device basis with one of the following Individual Device Options dialog boxes, which are accessible from the Device dialog box (Assign menu), depending on the current device family:

Classic & MAX Individual Device Options

FLEX 8000 Individual Device Options

FLEX 10K Individual Device Options

As an alternative to using the Global Project Device Options command, you can specify default device options in the Global Device Options Section of the ACF for the hierarchy tree.

The Global Project Device Options command is not available in the Graphic, Symbol, Text, or Waveform Editor if you are editing a file that is not part of the hierarchy tree of the current project.

See also:

Adjusting the Fit During Compilation

Assigning a Device

Back-Annotating Assignments for a Project

Fitting & Refitting a Project

Specifying Global Project Classic & MAX Device Options

Specifying Global Project FLEX 10K Device & Pin Options

Specifying Global Project FLEX 8000 Device & Pin Options

Specifying Individual Classic & MAX Device Options

Specifying Individual FLEX 10K Device & Pin Options

Specifying Individual FLEX 8000 Device & Pin Options


--------------------BEGINNING OF NON-TRANSLATED TEXT-----------------------------------------------

The segmented hypergraphics for the three Global Device Options share the following Reserved Resources popup.

--------------------END OF NON-TRANSLATED TEXT-----------------------------------------------


Reserved Resources

I/O Pins	The percentage of pin resources to reserve. Type an integer between 0 and 99 or use the arrow buttons to select a percentage.

Logic Cells	The percentage of logic cell resources to reserve. Type an integer between 0 and 99 or use the arrow buttons to select a percentage.


Classic & MAX Global Project Device Options Dialog Box (all applications)
Classic & MAX Global Project Device Options Dialog Box

Specifies the global default device options for all Classic, MAX 5000, MAX 7000, or MAX 9000 devices used in the current project.

This dialog box also specifies the percentage of all device pin and/or logic cell resources in the project to remain unused, i.e., reserved. Device resources can be reserved if you wish to leave additional logic capacity for future use.

You open this dialog box by choosing the Global Project Device Options command (Assign menu) when the Classic, MAX 5000, MAX 7000, or MAX 9000 device family is currently specified for the project. The device family is specified with the Device command (Assign menu).

The Classic & MAX Global Project Device Options dialog box specifies defaults that apply only to those devices for which no explicit device option settings are specified. You can override the default settings on a device-by-device basis with the Classic & MAX Individual Device Options dialog box, which is accessible from the Device dialog box.

Click Button 1 on any item in this dialog box for information on that item:

As an alternative to using the Classic & MAX Global Project Device Options dialog box, you can specify default device options in the Global Device Options Section of the ACF for the hierarchy tree.

The Global Project Device Options command and this dialog box are not available in the Graphic, Symbol, Text, or Waveform Editor if you are editing a file that is not part of the hierarchy tree of the current project.

See also:

Adjusting the Fit During Compilation

Assigning a Device

Back-Annotating Assignments for a Project

Fitting & Refitting a Project

Specifying Global Project Classic & MAX Device Options

Specifying Individual Classic & MAX Device Options


Classic & MAX Global Project Device Options dialog box

Click Button 1 on any item in this dialog box for information on that item:


Security Bit

Turns the Security Bit on or off for all devices in the project. This setting applies only to those devices for which no explicit Security Bit setting is specified with the Classic & MAX Individual Device Options dialog box.


FLEX 8000 Global Project Device Options dialog box (all applications)
FLEX 8000 Global Project Device Options Dialog Box

Specifies the global default device options and pin options for all FLEX 8000 devices used in a project. You can specify the project-wide default settings for several FLEX 8000-specific device options, as well as which dual-purpose pins should remain unused after device configuration.

This dialog box also specifies the percentage of all device pin and/or logic cell resources in the project to remain unused, i.e., reserved. Device resources can be reserved if you wish to leave additional logic capacity for future use.

You open this dialog box by choosing the Global Project Device Options command (Assign menu) when the FLEX 8000 device family is currently specified for the project. The device family is specified with the Device command (Assign menu).

The FLEX 8000 Global Project Device Options dialog box specifies defaults that apply only to those devices for which no explicit options are specified. You can override these default settings on a device-by-device basis by specifying FLEX 8000 device and pin options with the FLEX 8000 Individual Device Options dialog box, which is accessible from the Device dialog box.

Click Button 1 on any item in this dialog box for information on that item:

As an alternative to using the FLEX 8000 Global Project Device Options dialog box, you can specify option settings in the Global Device Options Section of the ACF for the hierarchy tree.

The Global Project Device Options command and this dialog box are not available in the Graphic, Symbol, Text, or Waveform Editor if you are editing a file that is not part of the hierarchy tree of the current project.

See also:

Assigning a Device

Combining & Converting SRAM Object Files

Specifying Individual FLEX 8000 Device & Pin Options

Specifying Global Project FLEX 8000 Device & Pin Options

Recommended reading:

AN33 (Configuring FLEX 8000 Devices)

AN38 (Configuring Multiple FLEX 8000 Devices)


FLEX 8000 Global Project Device Options dialog box

Click Button 1 on any item in this dialog box for information on that item:


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The segmented hypergraphics for the FLEX 8000 Global Device Options and FLEX 10K Global Device Options share the popups with the db_kgdo_??? links.

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User-Supplied Start-Up Clock

Directs the device to use a user-supplied Clock for initialization on the CLKUSR pin. If this option is turned off, external circuitry is required to provide the initialization Clock on the DCLK pin in the PS and PPS configuration schemes; in the AS, APU, APD, and PPA configuration schemes, the device uses an internal initialization Clock.


Auto-Restart Configuration on Frame Error

Directs the device to restart the configuration process automatically if a data frame error is encountered. If this option is turned off, you must externally direct the device to restart the configuration process if a frame error occurs.

This option is available only in the AS, APU, and APD configuration schemes.


Release Clears Before Tri-States

Directs the device to release the Clear override on the tri-state buffer before releasing the Output Enable signal on registered logic cells and I/O cells. If this option is turned off, the Output Enable signals are released before the Clear overrides.


Enable DCLK Output in User Mode

Enables the DCLK pin when the device is operating in user mode after device configuration and initialization have been completed. If this option is turned off, the DCLK pin is disabled when the device operates in user mode.

This option is available only in the AS, APU, APD, and PPA configuration schemes.


Disable Start-Up Time-Out

Disables the time-out error checking that determines whether CONF_DONE pin goes high within 10 Clock cycles after being released by the device. If this option is turned on, the device will continue to wait for CONF_DONE to go high. If this option is turned off, the device drives the nSTATUS pin low at the end of the configuration cycle if the CONF_DONE pin does not go high within 10 Clock cycles.


Enable JTAG Support

Enables the circuitry for JTAG boundary-scan testing. If this option is turned off, JTAG boundary-scan testing is not available.


Configuration Scheme

Selects one of the following FLEX 8000 configuration schemes:

AS	APU	APD

PS	PPS	PPA

Selecting a configuration scheme displays the recommended settings for the dual-purpose pins in the specified configuration scheme under Reserve and Tri-State. It has no effect on how the Compiler generates programming file(s) for the project.


Pin

Lists all dual-purpose pin names.

Refer to the FLEX 10K Programmable Logic Device Family Data Sheet or FLEX 8000 Programmable Logic Device Family Data Sheet for more information on dual-purpose configuration pins.


Reserve

Specifies whether the associated dual-purpose pin is used as an I/O pin in user mode.

Selecting an appropriate configuration scheme in the Configuration Scheme box shows the recommended settings under Reserve for the dual-purpose pin(s) available in that configuration scheme.

If this option is turned on, the pin is not used as an I/O pin during user mode. Selecting an appropriate configuration scheme in the Configuration Scheme box shows the recommended settings under Reserve for the dual-purpose pin available in that configuration scheme. Note that <-- is used as the visual indication of the keyboard focus on these checkboxes if you use the keyboard to select items in the dialog box.

Refer to the FLEX 10K Programmable Logic Device Family Data Sheet or FLEX 8000 Programmable Logic Device Family Data Sheet for more information on dual-purpose configuration pins.


Tri-State

Specifies whether the associated dual-purpose pin is tri-stated or allowed to drive out a signal. Pins can be tri-stated depending on the external circuitry of your board.

If this option is turned on, the pin is not used as an I/O pin during user mode. Selecting an appropriate configuration scheme in the Configuration Scheme box shows the recommended settings under Tri-State for the dual-purpose pin available in that configuration scheme. Note that <-- is used as the visual indication of the keyboard focus on these checkboxes if you use the keyboard to select items in the dialog box.

Refer to the FLEX 10K Programmable Logic Device Family Data Sheet or FLEX 8000 Programmable Logic Device Family Data Sheet for more information on dual-purpose configuration pins.


Not Affected by Configuration Scheme

Lists the dual-purpose pin(s) that can be reserved and tri-stated, but which are not affected by the configuration scheme selected in the Configuration Scheme box.

Reserve	Specifies whether the associated pin is reserved in user mode. If Reserve is turned on, the pin is not used as an I/O pin during user mode (i.e., reserved). If Reserve is turned off, the pin is available as an I/O pin during user mode.

Tri-State	Specifies whether the associated pin is tri-stated in user mode. If Tri-State is turned on, the pin is kept in a state of high impedance during user mode. If Tri-State is turned off, the pin is allowed to drive a signal during user mode. Pins can be tri-stated depending on the external circuitry of your board.


FLEX 10K Global Project Device Options dialog box (all applications)
FLEX 10K Global Project Device Options Dialog Box

Specifies the global default device options and pin options for all FLEX 10K devices used in a project. You can specify the project-wide default settings for several FLEX 10K-specific device options, as well as which dual-purpose pins should remain unused after device configuration.

This dialog box also specifies the percentage of all device pin and/or logic cell resources in the project to remain unused, i.e., reserved. Device resources can be reserved if you wish to leave additional logic capacity for future use.

You open this dialog box by choosing the Global Project Device Options command (Assign menu) when the FLEX 10K device family is currently specified for the project. The device family is specified with the Device command (Assign menu).

The FLEX 10K Global Project Device Options dialog box specifies defaults that apply only to those devices for which no explicit options are specified. You can override these default settings on a device-by-device basis by specifying FLEX 8000 device and pin options with the FLEX 10K Individual Device Options dialog box, which is accessible from the Device dialog box.

Click Button 1 on any item in this dialog box for information on that item:

As an alternative to using the FLEX 10K Global Project Device Options dialog box, you can specify option settings in the Global Device Options Section of the ACF for the hierarchy tree.

The Global Project Device Options command and this dialog box are not available in the Graphic, Symbol, Text, or Waveform Editor if you are editing a file that is not part of the hierarchy tree of the current project.

See also:

Assigning a Device

Combining & Converting SRAM Object Files

Specifying Global Project FLEX 10K Device & Pin Options

Specifying Individual FLEX 10K Device & Pin Options

Recommended reading:

AN 59 (Configuring FLEX 10K Devices)


FLEX 10K Global Project Device Options dialog box

Click Button 1 on any item in this dialog box for information on that item:


Enable Chip-Wide Reset

Enables the DEV_CLRn pin which allows all registers of the device to be reset by an external source. If this option is turned off, the DEV_CLRn pin is disabled when the device operates in user mode.


Enable Chip-Wide Output Enable

Enables the DEV_OE pin when the device is in user mode. If this option is turned off, the DEV_OE pin is disabled when the device operates in user mode.


Enable INIT_DONE Output

Enables the INIT_DONE pin when the device is operating in user mode after device configuration and initialization have been completed. If this option is turned off, the INIT_DONE pin is disabled when the device operates in user mode and is available as a user I/O pin.


Configuration Scheme

Selects one of the following FLEX 10K configuration schemes:

PS

PPS

PPA

Selecting a configuration scheme displays the recommended settings for the dual-purpose pins in the specified configuration scheme under Reserve and Tri-State. It has no effect on how the Compiler generates programming file(s) for the project.


JTAG User Code

Enter one hexadecimal byte of information into the device, as an extension of the option register. This byte can be read with the JTAG usercode instruction.


Global Project Parameters Command (all applications)
Global Project Parameters Command (Assign Menu)

Specifies the global default parameters for the current project.

Global Project Parameters specifies defaults that apply only to those symbols for which no explicit parameter settings are specified. You can override the default settings on a symbol-by-symbol basis with the Symbol Editor's Enter Parameters command or the Graphic Editor's Edit Ports/Parameters command.

Click Button 1 on any item in this dialog box for information on that item:

As an alternative to using the Global Project Parameters command you can specify default parameter settings in the Global Project Parameters Section of the ACF for the hierarchy tree.

Global Project Parameters is not available in the Graphic, Symbol, Text, or Waveform Editor if you are editing a file that is not part of the hierarchy tree of the current project.

1.	You cannot specify the Define_Family and Style parameters as global project parameters.

2.	Logic options cannot be assigned global, project-wide default parameter values.

See also:

Customizing a Macrofunction's Ports and Parameters

Entering a Parameter

Specifying Global Project Parameters


Global Project Parameters dialog box

Click Button 1 on any item in this dialog box for information on that item:


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The segmented hypergraphic for the Global Project Parameters dialog box uses the same popups as the SED Enter Parameters dialog box.

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Global Project Timing Requirements Command (all applications)
Global Project Timing Requirements Command (Assign Menu)

Specifies the global default timing for tpd, tco, tsu, and/or fmax for the entire project.

Click Button 1 on an item in this dialog box for information on that item:

You can assign timing requirements that override the Global Project Timing Requirements settings to selected nodes, buses, and/or symbols with the Timing Requirements command.

As an alternative to using the Global Project Timing Requirements command, you can specify timing requirements in the Timing Requirement Assignments Section of the ACF for the hierarchy tree.

Global Project Timing Requirements is not available in the Graphic, Symbol, Text, or Waveform Editor if you are editing a file that is not part of the hierarchy tree of the current project.

1.	Refer to Guidelines for Timing Assignments for information the types of logic functions that can accept timing assignments and how the Compiler interprets and resolves timing assignments. For information on specific assignments to enter and other techniques to improve speed performance in your MAX+PLUS II projects, go to Guidelines for Achieving Maximum Speed Performance.

2.	Be sure to refer to Guidelines for Working with Assignments for absolutely essential information on using all types of resource, probe, and device assignments.

See also:

Assigning Individual Timing Requirements

Clearing Assignments for a Project

Fitting & Refitting a Project

Specifying Global Project Timing Requirements


tpd

Specifies the maximum acceptable global default tpd for the project.

The time you enter should be followed immediately (i.e., with no space in between) by a time unit; the default unit is ns.

The global default tpd assigned with this command is overridden by tpd timing assignments entered with Timing Requirements.


tco

Specifies the maximum acceptable global default tco for the project.

The time you enter should be followed immediately (i.e., with no space in between) by a time unit; the default unit is ns.

The global default tco assigned with this command is overridden by tco timing assignments entered with Timing Requirements.


tsu

Specifies the maximum acceptable global default tsu for the project.

The time you enter should be followed immediately (i.e., with no space in between) by a time unit; the default unit is ns.

The global default tsu assigned with this command is overridden by tsu timing assignments entered with Timing Requirements.


fmax

Specifies the minimum acceptable global default fmax for the project.

The time you enter should be followed immediately (i.e., with no space in between) by a time unit; the default unit is mhz.

The global default fmax assigned with this command is overridden by fmax timing assignments entered with Timing Requirements.


Cut All Bidirectional Feedback Timing Paths

Cuts the feedback connections between the output and input paths of all bidirectional pins in the project. If this option is turned on, the Compiler will not consider the delay along these feedback paths when it processes the timing requirements for the project (the signal paths themselves are not cut).


Cut All Clear & Preset Timing Paths

Cuts the connections between all Preset and Clear signals and the Preset and Clear inputs to flipflops in the project. If this option is turned on, the Compiler will not consider the delay along these paths when it processes the timing requirements for the project (the signal paths themselves are not cut).


Global Project Timing Requirements dialog box

Click Button 1 on any item in this dialog box for information on that item:


Global Project Logic Synthesis Command (all applications)
Global Project Logic Synthesis Command (Assign Menu)

Specifies the default logic synthesis style and other synthesis settings for the current project.

The Global Project Logic Synthesis command also allows you to specify which global signals the Compiler should create automatically, and  whether to set multi-level synthesis or standard synthesis for the current project (MAX device families only). You can also specify global default settings for logic options, such as automatic one-hot encoding, register packing, and open-drain pins.

The Compiler ignores logic options if they are not available for the current device family and/or not user-editable.

Click Button 1 on any item in this dialog box for information on that item:

The logic synthesis style set with Global Project Logic Synthesis applies only to those logic functions for which no explicit logic option settings have been specified with the Logic Options command.

As an alternative to using the Global Project Logic Synthesis command, you can specify global logic synthesis settings the Global Project Synthesis/Assignment Options Section of the ACF for the hierarchy tree.

Be sure to refer to Guidelines for Working with Assignments for absolutely essential information on using all types of types of resource, probe, and device assignments, including logic synthesis style and logic option assignments.

The Compiler can create automatic global signals specified with this command only if the devices for the project have unused global signals after the Compiler has implemented the global signals you have explicitly specified, if any, with the GLOBAL primitive in the design files for the project.

The Global Project Logic Synthesis command is not available in the Graphic, Symbol, Text, or Waveform Editor if you are editing a file that is not part of the hierarchy tree of the current project. The Compilation Settings & Times Section of the Report File records the default logic synthesis style and automatic global signals selected for compilation, as well as the time spent during processing in this module.

See also:

Assigning an Individual Logic Option or Synthesis Style

Defining a Logic Synthesis Style

Fitting & Refitting a Project

Logic Synthesizer

Specifying Global Project Logic Synthesis Settings


 Global Project Logic Synthesis dialog box

Click Button 1 on any item in this dialog box for information on that item:


Global Project Synthesis Style

Specifies the default logic synthesis style for the current project. Altera provides the Normal, Fast, and WYSIWYG styles. The initial default style for a new project is Normal.

The global default logic synthesis style set with Global Project Logic Synthesis applies only to those logic functions for which no explicit logic option settings have been specified with the Logic Options command, i.e., the style is overridden by individual logic option and logic synthesis style assignments.

If you created a project with a pre-version 5.0 release of MAX+PLUS II, the logic option settings from that project also appear as a style called _<project name>, which is the initial default style for the project.


Optimize slider bar; Global Project Logic Synthesis dialog box
Optimize

Specifies the priority setting for the Optimize option. You can move the slider bar to any point between 0 and 10, with 0 giving the highest priority to area and 10 giving the highest priority to speed.

If your MAX+PLUS II system does not include support for timing-driven compilation, all settings between 0 and 9 are interpreted as 0, i.e., giving area the highest priority. You can thus choose only between area and speed.


Multi-Level Synthesis for MAX Devices; Global Project Logic Synthesis dialog box
Multi-Level Synthesis for MAX Devices

Directs the Compiler to use multi-level logic synthesis, which takes advantage of all available logic options, including all options listed in the Define Synthesis Style and Advanced Options dialog boxes. This type of logic synthesis can handle projects with extremely complex logic, without requiring user intervention to achieve a fit.

The Compiler may ignore some logic options if they are not available for the current device family and/or not user-editable.

If this option is turned off, the Compiler uses standard synthesis to compile your project.

This option is user-definable only in MAX device families, for which both multi-level synthesis and standard synthesis are available.


One-Hot State Machine Encoding; Global Project Logic Synthesis dialog box
One-Hot State Machine Encoding

Directs the Compiler to automatically implement one-hot encoding for the entire project.


Automatic I/O Cell Registers; Global Project Logic Synthesis dialog box
Automatic I/O Cell Registers

Allows the Compiler to implement registers in the project in I/O cell registers.

This option is available only for MAX 9000, FLEX 8000, and MAX 7000E devices.


Automatic Register Packing; Global Project Logic Synthesis dialog box
Automatic Register Packing

Allows the Compiler to maximize efficient device usage by placing a combinatorial logic function and a register with a single data input in the same logic cell.

This option is available only for MAX 9000 devices.


Automatic Open-Drain Pins; Global Project Logic Synthesis dialog box
Automatic Open-Drain Pins

Allows the Compiler to implement appropriate pins as open-drain pins.


Automatic Implement in EAB; Global Project Logic Synthesis dialog box
Automatic Implement in EAB

Allows the Compiler to implement purely combinatorial logic functions in an EAB rather than in logic cell(s).

This option is available only for FLEX 10K devices.


Automatic Global; Global Project Logic Synthesis dialog box
Automatic Global

Clock	Allows the Compiler to use a single Clock signal as the global Clock signal for the project.

Clear	Allows the Compiler to use a single Clear signal as the global Clear signal for the project. This option also provides a global Reset signal for a state machine.

Preset	Allows the Compiler to use a single Preset signal as the global Preset signal for the project.

Output Enable	Allows the Compiler to use a single Output Enable signal as the global Output Enable signal for the project.

All	Allows the Compiler to use a single Clock, Clear, Preset, and Output Enable signal as the global Clock, Clear, Preset, and Output Enable signals, respectively, for the project.

These global signals are used in different device families according to global signal availability.

MAX+PLUS II version 6.0 and higher may create more automatic global signals for some devices than earlier versions of MAX+PLUS II. If you have problems with fitting projects that compiled with earlier versions of MAX+PLUS II because of automatic global signal changes, you should turn off the appropriate option under Automatic Global. You can then implement global signals by inserting GLOBAL buffers into your project.


Ignore Project Assignments Command (all applications)
Ignore Project Assignments Command (Assign Menu)

Directs the Compiler to ignore resource and/or device assignments for the project.

You should choose to ignore assignments after an unsuccessful compilation if your project contains assignments but doesnt fit. You can then recompile the project to determine whether the assignments had prevented the project from fitting, and adjust the assignments accordingly.

The Compiler ignores assignments as directed by the Ignore Project Assignments dialog box until the options in the dialog box are changed.

Click Button 1 on any item in this dialog box for information on that item:

As an alternative to using the Ignore Project Assignments dialog box, you can specify assignments to be ignored during compilation in the Ignored Assignments Section of the ACF for the hierarchy tree.

1.	Refer to Guidelines for Timing Assignments for information on how to use timing assignments effectively.

2.	Be sure to refer to Guidelines for Working with Assignments for absolutely essential information on using all types of resource, probe, and device assignments.

See also:

Clearing Assignments for a Project

Deleting an Assignment

Specifying Global Project Timing Requirements


Ignore Project Assignments dialog box

Click Button 1 on any item in this dialog box for information on that item:


Types of Assignments to Ignore During Compile; Ignore Project Assignments dialog box
Types of Assignments to Ignore During Compile

Pin Assignments	Directs the Compiler to ignore all pin assignments, including assignments to rows, columns, and LABs.

Logic Cell Assignments	Directs the Compiles to ignore all logic cell assignments, including assignments to I/O cells, rows, columns, and LABs.

Demote Specific Logic Cell 	Directs the Compiler to reduces assignment(s) made to

Assignments to LAB Assignments	specific logic cells to LAB assignments.

Chip Assignments	Directs the Compiler to ignore all chip assignments.

Clique Assignments	Directs the Compiler to ignore all clique assignments.

Individual Logic Option Assignments	Directs the Compiler to ignore all individual logic option assignments. The default logic synthesis style for a project, which is specified with Global Project Logic Synthesis, is never ignored.

Device Assignments	Directs the Compiler to ignore all device assignments.

Timing Requirements	Directs the Compiler to ignore all timing requirements, including both individual timing assignments entered with Timing Requirements and global timing assignments entered with Global Project Timing Requirements.

All	Directs the Compiler to ignore all assignments.


Demote Assignments Command (Floorplan Editor)
Demote Assignments Command (Assign Menu)

Shortcuts

Reduces the selected pin and/or location assignment(s) to less restrictive assignments so that the Compiler can more freely rearrange the assignments for greater efficiency.

Click Button 1 on any item in this dialog box for information on that item:

The Demote Assignments command allows you to select one or more items with the same type of assignment and demote the current assignments to less restrictive ones, e.g., to demote nodes that are currently assigned to individual logic cells to an LAB assignment bin, or nodes that are assigned to a row bin to anywhere in the device.

You can choose to demote any combination of assignments, including assignments to pins, logic cells, I/O cells, rows, columns, and LABs. If you select multiple items with different types of assignments, they can be demoted to the least common denominator of the selected assignments. For example, if you select all logic cells and LAB bins in a device, all assignments can be demoted to LAB assignments.

 	The Ignore Project Assignments command also provides an option to demote specific logic cell assginment to LAB assignments.

See also:

Assigning a Pin, Location, or Chip

Demoting an Assignment

Fitting & Refitting a Project

Guidelines for Working with Assignments

Selecting a Node, Pin, or Other Object

Recommended reading:

AB93 (Partitioning a Project with MAX+PLUS II Software)


Demote Assignments dialog box

Click Button 1 on any item in this dialog box for information on that item:


Device Assignment Bin

Demotes the assignments of all selected items, including assignments to pins, logic cells, I/O cells, rows, columns, and LABs, to assignments to the Device Assignment Bin, i.e., to anywhere in the device.


Any Column Assignment Bin

Demotes the assignments of all selected items, including assignments to pins, logic cells, I/O cells, rows, columns, and LABs, to assignments to the Any Column Assignment Bin, i.e., to any column in the device.

This option is available only for FLEX 8000, and MAX 9000 devices.


Any Row Assignment Bin

Demotes the assignments of all selected items, including assignments to pins, logic cells, I/O cells, rows, columns, and LABs, to assignments to the Any Row Assignment Bin, i.e., to any row in the device.

This option is available only for FLEX 8000, and MAX 9000 devices.


Column Assignment Bin

Demotes the assignments of all selected items, including assignments to pins, logic cells, I/O cells, rows, columns, and LABs, to assignments to their respective Column Assignment Bin, i.e., assignments in column 1 are placed in the bin for column 1.

This option is available only for FLEX 8000, and MAX 9000 devices.


Row Assignment Bin

Demotes the assignments of all selected items, including assignments to pins, logic cells, I/O cells, rows, columns, and LABs, to assignments to their respective Row Assignment Bin, i.e., assignments in row A are placed in the bin for row A.

This option is available only for FLEX 8000, and MAX 9000 devices.


LAB Assignment Bin

Demotes the assignments of all selected items, including assignments to logic cells, rows, columns, and LABs, to assignments to their respective LAB Assignment Bin, i.e., assignments to individual logic cells in LAB A1 are placed in the bin for LAB A1.


Clear Project Assignments Command (all applications)
Clear Project Assignments Command (Assign Menu)

Removes the specified probe, resource, and device assignments from the Assignment & Configuration File (.acf) for the current project.

Click Button 1 on any item in this dialog box for information on that item:

The Clear Project Assignments command removes assignments from the ACF, regardless of whether they were entered by choosing commands from the Assign menu, or by manual edits to the ACF.

After the selected assignments have been removed, the Existing Assignments-type boxes in the Assign menu dialog boxes show only the remaining assignments that exist in the ACF. In the Graphic Editor, remaining assignments can also be displayed on screen with Show All.

Clear Project Assignments is not available if the project is untitled, if MAX+PLUS II is running a background process, or if you are editing a file in the Graphic, Symbol, Text, or Waveform editor that is not part of the hierarchy tree of the current project.

See also:

Assigning a Clique

Assigning a Device

Assigning an Individual Logic Option or Synthesis Style

Assigning a Pin, Location, or Chip

Assigning a Probe

Assigning Individual Timing Requirements

Clearing Assignments for a Project

Deleting an Assignment

Guidelines for Timing Assignments

Guidelines for Working with Assignments

Recommended reading:

AB93 (Partitioning a Project with MAX+PLUS II Software)


Clear Assignments from .prb File
Clear Assignments from ACF

Pins, Logic Cells & Chips	Clears all pin, logic cell, and chip assignments in the project, including assignments to I/O cells, rows, columns, and LABs.

Pins & Logic Cells	Clears all pin and logic cell assignments in the project, including assignments to I/O cells, rows, columns, and LABs.

Logic Cells	Clears all logic cell assignments in the project, including assignments to I/O cells, rows, columns, and LABs.

Cliques	Clears all clique assignments in the project.

Devices	Clears all device assignments in the project.

Timing Requirements	Clears all timing assignments in the project, including both individual timing assignments entered with Timing Requirements and global timing assignments entered with Global Project Timing Requirements.

Logic Options	Clears all logic option and logic synthesis style assignments in the project.

Probes	Clears all probe assignments in the project.

Connected Pin Groups	Clears all connected pin groups in the project.

All 	Clears all resource, probe, and device assignments in the current project.


Clear Project Assignments dialog box

Click Button 1 on any item in this dialog box for information on that item:


Back-Annotate Project Command (all applications)
Back-Annotate Project Command (Assign Menu)

Copies device, pin, logic cell, and chip assignments in the Fit File generated by the Compiler into the Assignment & Configuration File (.acf) for the project. This process ensures that subsequent compilations produce the same fit.

Since the Fit File is overwritten each time the project is compiled, this command is useful for retaining the current resource and device assignments for future compilations. Changes to the design files, changes to logic synthesis styles, and changes to future releases of MAX+PLUS II can all alter how the Compilers Fitter module places the project into one or more devices, and determine whether future compilations will use the same resource assignments.

Click Button 1 on any item in this dialog box for information on that item:

Altera recommends that you allow the Compiler to choose pin and logic cell assignments until the project is near completion. Allowing the Compiler to make the earlier assignments is most likely to yield a successful fit.

After you back-annotate the project, the Existing Assignments-type boxes in the Assign menu dialog boxes show all assignments that exist in the ACF. In the Graphic Editor, you can also display assignments on screen with Show All.

Back-Annotate Project is not available if no Fit File exists for the current project, the project is untitled, the current file is untitled, the current file is not part of the current project, MAX+PLUS II is currently compiling a project, or if you are editing a file in the Graphic, Symbol, Text, or Waveform Editor that is not part of the hierarchy tree of the current project.

See also:

Back-Annotating Assignments for a Project

Fitting & Refitting a Project

Guidelines for Working with Assignments

Saving a File

Recommended reading:

AB93 (Partitioning a Project with MAX+PLUS II Software)


Back-Annotate to ACF

Chips, Logic Cells, Pins & Devices	Clears all chip, logic cell (including I/O cell), pin, and device assignments from the ACF and replaces them with the chip, logic cell, pin, and device assignments from the Fit File. Connected pin assignments are not affected.

Chips, Pins & Devices	Clears all chip, logic cell (including I/O cell), pin, and device assignments from the ACF and replaces them with the chip, pin, and device assignments from the Fit File. Connected pin assignments are not affected.

Chips	Clears all chip, logic cell (including I/O cell), and pin assignments from the ACF and replaces them with the chip assignments from the Fit File.

Devices	Clears all device assignments from the ACF and replaces them with the device assignments from the Fit File.


Back-Annotate Project dialog box

Click Button 1 on any item in this dialog box for information on that item:


Convert Obsolete Assignment Format Command (all applications)
Convert Obsolete Assignment Format Command (Assign Menu)

Reconverts resource, probe, and device assignments from projects created with pre-version 5.0 releases of MAX+PLUS II into the Assignment & Configuration File (.acf) format.

Built-in backward compatibility in MAX+PLUS II ensures that when you open a project that was created with a pre-version 5.0 release of MAX+PLUS II, all assignment and configuration information that exists in the projects top-level TDF (if any), .prb file, and <project name>.ini file is automatically converted into the ACF format. MAX+PLUS II comments out obsolete assignment syntax in the TDF, and deletes the .prb and <project name>.ini files. MAX+PLUS II always preserves copies of the original unconverted files with the extension .tdk, .prk, and .ink, respectively.

However, if MAX+PLUS II reports a conversion error when opening your project, your assignments may not be fully converted into the ACF format. Convert Obsolete Assignment Format allows you to manually restart the conversion process after you have edited the file(s) to correct the error(s) that caused the automatic conversion to fail.

You should use Convert Obsolete Assignment Format only if MAX+PLUS II reports a conversion error when you first open a project created with a pre-version 5.0 release of MAX+PLUS II. Convert Obsolete Assignment Format will overwrite any new assignments that you have entered with MAX+PLUS II version 5.0 or higher with the assignments from the older TDF, .prb file, and <project name>.ini file.

See also:

Converting an Obsolete Assignment Format


Find Text Command (Floorplan Editor)
Find Text Command (Utilities Menu)

Shortcuts

Searches the current chip for the first occurrence of the specified text. Text can be found both in the current chip and in the Unassigned Nodes & Pins box.

Click Button 1 on any item in this dialog box for information on that item:

After the first occurrence of the search text is found, you can choose Find Next or Find Previous to continue the search. You can also select a different chip in the Chip Name field to search for text in a different chip.

See also:

Finding Text

Viewing a Device in the Device View or LAB View


Pause at End

Specifies whether MAX+PLUS II will pause when it reaches the end of the floorplan and ask whether you wish to continue the search.


Types of Text to Find

Pin & Node Names	Finds the text that occurs in pin and node names.

Pin/LC/IOC Number or 	Finds the text that occurs in the pin, logic cell,

Assignment Bin Name	I/O cell numbers and assignment bin names.

All	Finds all occurrences of the specified search text.


Find Text dialog box (Floorplan Editor)
Find Text dialog box

Click Button 1 on any item in this dialog box for information on that item:


Find Next Command (Floorplan Editor)
Find Next Command (Utilities Menu)

Shortcuts

Finds the next occurrence of the search text specified with Find Text.

See also:

Finding Text


Find Previous Command (Floorplan Editor)
Find Previous Command (Utilities Menu)

Shortcuts

Finds the previous occurrence of the search text specified with Find Text.

See also:

Finding Text


Routing Statistics Command (Floorplan Editor)
Routing Statistics Command (Options Menu)

Shortcuts

Provides routing information for one or more selected pins, logic cells, I/O cells, embedded cells, and/or assignment bins in the current chip.

Click Button 1 on any item in this dialog box for information on that item:

If you choose the Calculate Most Congested Areas button, or if you selected item(s) for which only chip-wide routing statistics are available, the expanded Routing Statistics dialog box opens.

Click Button 1 on any item in this dialog box for information on that item:

1.	Depending on the size of the target chip and the number of resource assignments, it may take several seconds to calculate the most congested areas of the chip.

2.	The routing information displayed with this command is available only for projects compiled with MAX+PLUS II version 5.2 or higher. You must recompile projects created with earlier versions of MAX+PLUS II to view their routing information in the Floorplan Editor.

See also:

Showing Node Fan-In or Fan-Out

Showing Paths

Showing Routing Statistics


Routing Statistics dialog box (Floorplan Editor)
Routing Statistics dialog box

Click Button 1 on any item in this dialog box for information on that item:


Expanded Routing Statistics dialog box (Floorplan Editor)
Expanded Routing Statistics dialog box

Click Button 1 on any item in this dialog box for information on that item:


Name is

Pin or node name assigned to the selected pin, logic cell, I/O cell, or embedded cell, including an individual assignment to a row, column, LAB, or EAB.

If multiple items are selected, the text **-Multiple Items-** is displayed in this field.


Number is

Pin, logic cell, I/O cell, or embedded cell number of the selected item.


LAB/EAB is

Name of the LAB or EAB that contains the selected logic cell(s) or embedded cell(s), or of the selected LAB or EAB assignment bin.


Row is

Letter of the row that contains the selected pin, logic cell, I/O cell, embedded cell, or LAB assignment bin, EAB assignment bin, or row assignment bin.

This information is available for FLEX 10K, FLEX 8000, and MAX 9000 devices only.


Column is

Number of the column that contains the selected pin, logic cell, I/O cell, embedded cell, LAB assignment bin, or column assignment bin.

This information is available for FLEX 10K, FLEX 8000, and MAX 9000 devices only.


Logic Cell/Embedded Cell Fan-In

Number of input signals feeding the input equations of the selected logic cell, embedded cell, or pin.


Logic Cell/Embedded Cell Fan-Out

Number of output signals that are fed by the output equations of the selected logic cell, embedded cell, or pin.


Logic Cell Carry-Out

Indicates (Yes or No) whether or not the selected logic cell feeds a carry chain.

This information is available for FLEX 10K and FLEX 8000 devices only.


Logic Cell Cascade-Out

Indicates (Yes or No) whether or not the selected logic cell feeds a cascade chain.

This information is available for FLEX 10K and FLEX 8000 devices only.


Logic Cell Total Shared Expanders Used

Displays the total number of shared expanders used by the selected logic cell. Usage is displayed both as a ratio and as a percentage of available shared expanders.

This information is available for MAX 5000, MAX 7000, and MAX 9000 devices only.


Depth (Bits)

Displays the depth of the selected embedded cell in bits.

This information is available for FLEX 10K devices only.


LAB Total Shared Expanders Used

Displays the total number of shared expanders used by the selected LAB or the LAB that contains the selected logic cell(s). Usage is displayed both as a ratio and as a percentage of available shared expanders.

This information is available for MAX 5000, MAX 7000, and MAX 9000 devices only.


LAB External Interconnect Used

Shows the number of external signals that enter the LAB. This number does not include carry or cascade signals that feed into the LAB. Usage is displayed both as a ratio and as a percentage of available LAB external interconnections in the device.


Column Interconnect Channels Used

Displays the number of vertical (column) routing paths used in the FastTrack Interconnect that are driven out for each LAB. Usage is displayed both as a ratio and as a percentage of available column interconnections.

This information is available for FLEX 10K, FLEX 8000, and MAX 9000 devices only.


Full Row Interconnect Channels Used

Displays the number of full horizontal (row) routing paths used in the FastTrack Interconnect that are driven out for each LAB. Usage is displayed both as a ratio and as a percentage of available row interconnections.

This information is available for FLEX 10K, FLEX 8000, and MAX 9000 devices only.


Half Row Interconnect Channels Used

Displays the number of half horizontal (row) routing paths used in the FastTrack Interconnect that are driven out for each LAB. Usage is displayed both as a ratio and as a percentage of available row interconnections.

This information is available for FLEX 10K devices only.


Calculate Most Congested Areas

Expands the Routing Statistics dialog box to display information on the most congested LAB, EAB, row, and/or column in the current chip.

Depending on the size of the target device and the number of assignments, it may take several seconds to calculate the most congested areas of the chip.

Row and column information is available for FLEX 10K, FLEX 8000, and MAX 9000 devices only.


Most Congested LAB (or EAB) is:

Name of the LAB or EAB that contains the most external interconnections in the device.


LAB (or EAB) External Interconnect Used

Shows the number of external signals that enter the most congested LAB or EAB in the device. This number does not include carry or cascade signals that feed into the LAB or EAB. Usage is displayed both as a ratio and as a percentage of available LAB or EAB external interconnections in the assigned device.


Most Congested Row is:

Name of the row that uses the most horizontal FastTrack Interconnect routing paths in the device. For FLEX 10K devices, the row name is followed by a label identifying the row as either a full or half row.

This information is available for FLEX 10K, FLEX 8000, and MAX 9000 devices only.


Row Interconnect Channels Used

Displays the number of horizontal (row) FastTrack Interconnect routing paths used in the most congested row in the device. Usage is displayed both as a ratio and as a percentage of available row interconnections.

This information is available for FLEX 10K, FLEX 8000, and MAX 9000 devices only.


Most Congested Column is:

Name of the column (including the EAB) that uses the most vertical FastTrack Interconnect routing paths in the device.

This information is available for FLEX 10K, FLEX 8000, and MAX 9000 devices only.


Column Interconnect Channels Used

Displays the number of vertical (column) FastTrack Interconnect routing paths used in the most congested column in the device. Usage is displayed both as a ratio and as a percentage of available column interconnections.

This information is available for FLEX 10K, FLEX 8000, and MAX 9000 devices only.


Show Node Fan-In & Show Node Fan-Out Commands (Floorplan Editor)
Show Node Fan-In & Show Node Fan-Out Commands (Options Menu)

Shortcuts

Shows routing information by displaying the fan-in to or fan-out from one or more selected logic cells, I/O cells, and/or pins.

When Show Node Fan-In is turned on and you select one or more items in the LAB View display, the Floorplan Editor shows the node source paths as pink lines. These fan-in routing lines feed into the left side of the logic cells or pins.

When Show Node Fan-Out is turned on and you select one or more items in the LAB View display, the Floorplan Editor shows the node destination paths as aqua-blue lines. These fan-out routing lines feed out from the right side of the logic cells or pins.

The fan-in and/or fan-out lines are updated automatically when you move a logic cell, I/O cell, or pin.

You can use these commands separately or together. However, if both commands are turned on, only the fan-out lines are displayed between items with mutual fan-in and fan-out.

Show Node Fan In and/or Show Node Fan Out and the Show Path command (Options menu) cannot be turned on at the same time. When you turn on Show Node Fan In and/or Show Node Fan Out, the Show Path command is automatically turned off, and vice versa.

The routing information displayed with these commands is available only for projects compiled with MAX+PLUS II version 5.2 or higher. You must recompile projects created with earlier versions of MAX+PLUS II to view their routing information in the Floorplan Editor.

See also:

Showing Node Fan-In or Fan-Out

Showing Paths

Showing Routing Statistics

Viewing a Device in the Device View or LAB View


Show Path Command (Floorplan Editor)
Show Path Command (Options Menu)

Shortcuts

Shows the path between selected logic cells, I/O cells, embedded cells, and/or pins that feed one another.

When Show Path is turned on and you select one or more items in the LAB View display that are fed by another selected item, the Floorplan Editor shows the paths between the items as bright blue lines. If you select a single item that fans out to itself, a horizontal blue line is displayed through the item.

The paths are updated automatically when you move a logic cell, I/O cell, embedded cell, or pin.

Show Path and the Show Node Fan In and Show Node Fan Out commands (Options menu) cannot be turned on at the same time. When you turn Show Path on, the other commands are automatically turned off, and vice versa.

The routing information displayed with this command is available only for projects compiled with MAX+PLUS II version 5.2 or higher. You must recompile projects created with earlier versions of MAX+PLUS II to view their routing information in the Floorplan Editor.

See also:

Showing Node Fan-In or Fan-Out

Showing Paths

Showing Routing Statistics

Viewing a Device in the Device View or LAB View


Show Moved Nodes in Gray Command (Floorplan Editor)
Show Moved Nodes in Gray Command (Options Menu)

Shows nodes that have been moved since the last compilation and back-annotation of the project in gray.

When Show Moved Nodes in Gray is turned on, the Floorplan Editor displays the nodes that have been relocated in gray, so that you can easily track the differences between the current assignments and the last compilation fit. If this command is turned off, the original colors of the items, as determined by the Color Legend are used instead.

See also:

Showing Moved Nodes in Gray

Viewing a Device in the Device View or LAB View


New Features in This Release

MAX+PLUS II version 6.0 includes many significant new features. Click Button 1 on one of the following categories for information:

New Device Support	New Editor User Interface	Windows 95 Support

MAX+PLUS II for Workstations	MAX+PLUS II Manager	Graphic & Symbol Editors

Text Editor	Waveform Editor	Floorplan Editor

Megafunctions/LPM	AHDL	VHDL

Compiler	Simulator	Timing Analyzer

Programmer	Third Party Interfaces

New Device Support

MAX+PLUS II version 6.0 includes support for several new devices, including members of Altera’s newest device family, the FLEX 10K family.

Full compilation, simulation, timing analysis, and programming support is available for the following new devices and device packages:

FLEX 10K Device Family:

EPF10K50GC403

Preliminary Device Support:

Compilation, simulation, and timing analysis support is provided for the following devices that will be released in the near future. Programming files will not be generated:

EPM9400RC208

EPM9400RC240

MAX+PLUS II version 6.0 includes programming support for the following devices:

EPC1PC8

EPC1LC20

EPX740LC44

EPX740LC68

EPX780QC132

EPX880LC84

EPX880QC132

EPX8160QC208

For information on all existing device support in MAX+PLUS II, including programming-only support, go to Devices & Adapters.

Windows 95 Support

MAX+PLUS II version 6.0 is now fully compatible with Windows 95.

Applications & Features in MAX+PLUS II for Workstations

MAX+PLUS II for Workstations includes all applications and features that are available in MAX+PLUS II for Windows, except the MAX+PLUS II Programmer.

MAX+PLUS II Programmer support on workstations will be available in an upcoming release of MAX+PLUS II.

The following platform/operating system combinations are supported:

Sun SPARCstation or compatible workstation with SunOS 4.1.2 or higher and OpenWindows 3.0 or higher.

Sun SPARCstation or compatible workstation with Solaris 2.4 or higher.

HP 9000 Series 700 with HP-UX 9.03 or higher and HP-VUE.

IBM RISC System/6000 with AIX 3.2.5 or higher and AIX/Windows 1.2.5 or higher.

New Editor User Interface

All MAX+PLUS II editor applications have a revised user interface that conforms to established Windows standards. Key features of this interface are:

Clicking Button 2 on an object displays a context-sensitive pop-up menu that is used to manipulate the properties of that object.

Buttons on the tool palette select editing modes. MAX+PLUS II version 6.0 will automatically switch modes when appropriate to ease design entry.

The mouse pointer shape is context-sensitive: it changes depending upon the action that will be performed when Button 1 is pressed.

MAX+PLUS II Manager

Project loading has been made faster.

The Preferences command (Options menu) specifies general preferences for your MAX+PLUS II setup, including whether to ask before closing MAX+PLUS II.

The Compiler, Simulator, and Timing Analyzer can be operated from the command line under Windows 95, Windows NT, and all UNIX workstation platforms.

Network licensing is now available under Windows 95 and Windows NT. Contact Altera Marketing for information on implementing network licensing on PC platforms.

Graphic & Symbol Editors

Both the Graphic & Symbol Editors have a revised user interface, as described above in New Editor User Interface.

Both editors support parameterized design: constants and parameters in bus names; parameters on symbols; parameter default values in schematics; optional and inverted ports on mega/macrofunction symbols.

Two-dimensional and tri-state buses are supported.

Text Editor

The Text Editor has a revised user interface, as described above in New Editor User Interface.

The Syntax Coloring command (Options menu) allows the Text Editor to display keywords and other elements of text in a text files such as AHDL TDFs, VHDL Design Files, Vector Files, etc. in different colors to distinguish them from other forms of syntax.

Drag and drop editing is supported. You can move or copy a section of text by dragging it with Button 1. Pressing the Ctrl key while dragging text copies the text.

Selected text can be indented with the Increase Indent command (Edit menu). The reverse action may be performed with the Decrease Indent command.

The Find Matching Delimiter command (Utilities menu) allows you to find the matching section delimiter for character/keyword pairs such as {}, [], (), BEGIN-END, IF-END, CASE-END, and TABLE-END.

Waveform Editor

The Waveform Editor has a completely revised user interface, as described above in New Editor User Interface.

Comments can be entered in the waveform area.

Tool palette buttons are available for many of the common editing commands.

Support for FLEX 10K EABs.

Floorplan Editor

The Floorplan Editor has a revised user interface, as described above in New Editor User Interface.

You can display the logic equation from the Report File for one or more selected cells. You can also traverse the fan-in and fan-out of the cell(s). This functionality is controlled with the Report File Equation Viewer command (Layout menu).

The Show Path command (Options menu) displays the signal path between two or more selected pins and/or logic cells. This feature is useful for tracing critical timing paths from a timing analysis.

Printing is now supported.

Megafunctions/LPM

The Library of Parameterized Modules (LPM) 2.0.1/2.1.0 standard is supported. LPM functions should be used in preference to old-style macrofunctions in implementing your designs: they can provide the most efficient design implementation. The implemenation of LPM functions can be controlled with parameters and logic options.

AHDL

AHDL has been extensively enhanced to support parameterized design. The logic that an AHDL file generates may be completely controlled by a set of parameters. One common example would be to specify the width of a bus or port using a parameter.

Assert Statements may be used to create user error, warning, and information messages that are displayed during compilation.

Enhanced constant processing, including the use of evaluated functions.

AHDL now supports conditional and iterative logic generation with the If Generate and For Generate Statements.

If new the Use LPM for AHDL Operators logic options is applied to an AHDL function, the Compiler will insert the LPM functions lpm_compare and lpm_add_sub to perform comparisons, additions, and subtractions. This feature provides additional control over the way a design is implemented. For example, carry chain adders that use the AHDL "+" operator can be created for FLEX 8000 and FLEX 10K designs.

VHDL

MAX+PLUS II version 6.0 includes support for standard conversion functions.

Within a Process Statement, individual bits of a variable can be clocked.

.

Non-constant indices are now permitted in vectors.

Compiler

Improved FLEX 8000 fitting, particularly with pin assignments.

Improved Compiler error messages.

Enhanced timing-driven compilation with the Optimize option in the Global Project Logic Synthesis dialog box (Assign menu).

Internal tri-state bus support.

Additional Global Project Logic Synthesis command (Assign menu) options are available: One-Hot State Machine Encoding; Automatic Open-Drain Pins; Automatic Implement in EAB; Optimize.

Additional logic options are available: Hierarchical Synthesis; Implement as Output of Logic Cell; Insert Additional Logic Cell; Implement in EAB, Ignore SOFT Buffers, Use LPM for AHDL Operators.

The Compiler can be run from the command line under Windows 95, Windows NT, and all UNIX workstation platforms.

Simulator

Full support for FLEX 10K EABs. EAB contents can be viewed and edited with the Initialize Memory command (Initialize menu).

The Simulator can be run from the command line under Windows 95, Windows NT, and all UNIX workstation platforms.

Timing Analyzer

For Registered Performance analysis, you may specify the number of critical paths to be stored and listed. By default, the Timing Analyzer lists the top 10 critical paths.

Full support for FLEX 10K EABs.

Source, destination, and cutoff node names are now stored in the ACF so that Timing Analyzer settings are saved from one MAX+PLUS II session to another.

The Timing Analyzer may be run from the command line under Windows 95, Windows NT, and all UNIX workstation platforms.

Programmer

Blank-check and programming verification can be skipped to speed up programming with the Programming Options command (Options menu).

One or more FLEX 10K, MAX 9000, and FLASHlogic devices in a JTAG chain can be programmed or configured simultaneously in-system using the BitBlaster. See the Multi-Device JTAG Chain Setup command (JTAG menu).

Third-Party Interfaces

Third-party interfaces are built on the following EDA vendor releases:

-	Cadence 9502

-	Mentor Graphics A.3

-	Synopsys 3.3a

-	Viewlogic 5.32

The previously available Application Notes for interfaces to third-party software have been fully revised and are now available as the following new Software Interface Guides:

-	Cadence & MAX+PLUS II Software Interface Guide

-	Mentor Graphics & MAX+PLUS II Software Interface Guide

-	Synopsys & MAX+PLUS II Software Interface Guide

-	Viewlogic Powerview & MAX+PLUS II Software Interface Guide

Processing of EDIF files is now 2 to 3 times faster.

EDIF 3 0 0 is supported.

Pin buses are now preserved. If an EDIF file compiled by MAX+PLUS II contains input and output pin buses, those buses will be present in the VHDL, Verilog, and EDIF output files.

Delay information for VHDL, Verilog, and EDIF output files can optionally be written to a separate Standard Delay Format (SDF) ver 1.0 or 2.1 output file.

MAX+PLUS II version 6.0 includes support for VITAL version 2.2b or 3.0.

Preservation of original source node names has been enhanced. Under most circumstances, the node names used in the original source files will be present in VHDL, Verilog, and EDIF output files of MAX+PLUS II, provided the nodes have not been removed during synthesis.

Full support for FLEX 10K devices, including EABs.

LPM 2.0.1/2.1.0 is supported in Cadence and Mentor Graphics.


--------------------BEGINNING OF NON-TRANSLATED TEXT-----------------------------------------------

This file contains the following panels:

Getting Information on a File

Retrieving a File

Saving a File

Ensuring Project Reliability

Project Reliability Guidelines

Creating the Default Symbol for a File

Editing the Symbol for a File

Creating a Default Include File

Finding a Node or Symbol

Copying, Cutting & Pasting Text

Deleting Text

Undoing Edits

h2 is redefined with Keep w/next turned on

h2sc is h2 redefined with no space after (instead of 10pt) and Keep w/next turned on

shortcut,sc defined as para with these additions: blue, bold, 7/8 in tab, 10pt after, keep with next

--------------------END OF NON-TRANSLATED TEXT-----------------------------------------------


Getting Information on a File (editor applications)
Getting Information on a File

To get information on a file that is open in the current Graphic, Text, Waveform, or Symbol Editor window:

Open the Info dialog box by choosing Info (File menu) or using a shortcut. The following information is displayed for the file:

Hierarchy path

Filename

Date of the last save

Size (in bytes)

Whether the file has been edited since the last save

See also:

Getting Information on a File (Programmer)


Retrieving a File (editor applications)
Retrieving a File

You can close the current file and open another file in the same window as the current file. Retrieving a file allows you to edit a new file without opening a new window.

To retrieve a file:

1.	Choose Retrieve (File menu). The Retrieve dialog box is displayed.

2.	If necessary, select a different file type under Show in Files List.

3.	If you wish to open a Graphic, Text, and Waveform Editor file with a different extension, select a different extension from the drop-down list box.

4.	Type a name in the File Name box or select a name in the Files box.

5.	Choose OK.

Use the built-in hierarchy traversal features in MAX+PLUS II to move between design files for the current hierarchy tree. To open a lower-level file in a hierarchy, open the top-level file and then use the Hierarchy Display window or Hierarchy Down (File menu) to open the lower-level files. If you choose Open (File menu) or Retrieve to open a lower-level file, it is considered to be the top of a different hierarchy, and resource, device, and probe assignments that you enter are saved only for that hierarchy, not for the project.

See also:

Guidelines for Working with Assignments

Opening a File


Saving a File (editor applications)
Saving a File

MAX+PLUS II offers the following File menu commands for saving a file:

Command:	Action:

Save	Saves the current file under the same filename. (Graphic, Text, Waveform, and Symbol Editors only) Shortcuts

Save As	Saves an untitled file or saves the current file under a different name. (Graphic, Text, Waveform, and Symbol Editors only)

Project Save & Check	Saves all open Compiler input files, including both design files and ancillary files that are Compiler inputs, and checks the current project for errors by submitting it to the Compiler Netlist Extractor and Database Builder modules of the Compiler. Shortcuts

Project Save & Compile	Saves all open Compiler input files in the current project???, opens the Compiler window, and compiles all files that have changed since the last compilation. Shortcuts

Project Save & Simulate	Saves all open Vector Files and SCFs that are specified with the Simulator’s Inputs/Outputs (File menu) command???, opens the Simulator window, and simulates the project. Shortcuts

Project Save, Compile & Simulate	Saves all open Compiler input files in the current project???, saves all open Vector Files and SCFs that are specified with the Simulator’s Inputs/Outputs command, and compiles and simulates the project. Shortcuts

The commands on the Project submenu save

When you save an untitled file or choose Save As, the Save As dialog box for the Graphic, Text, or Waveform Editor opens. To save the file:

1.	If necessary, select a different drive and/or directory.

2.	Type the filename. Filenames can contain up to 32 name characters. If you select the name of an existing file, it will be overwritten. If you type the name of a directory that does not exist, MAX+PLUS II offers to create it for you.

3.	If you wish to save the file without any extension, type a period (.) after the filename. (Available only for Text Editor files.)

4.	If necessary, choose a different extension from the Automatic Extension drop-down list box or type an extension after the filename. Graphic Editor files always have .gdf or .sch extensions. Symbol Editor files always have .sym extensions. Waveform Editor Files always have .wdf or .scf extensions.

5.	Choose OK.

1.	When you use Save As to save a top-level design file to a new name, MAX+PLUS II automatically saves copies of the ACF, Symbol File, Include File, and HIF to the new filename. If the file is an OrCAD Schematic File, MAX+PLUS II also saves a copy of the OrCAD Library File to the new filename.

2.	When you save an OrCAD Schematic File in the Graphic Editor, some information from the original file is lost. Refer to Restrictions on OrCAD Schematic Files in MAX+PLUS II and Guidelines for Working with OrCAD Schematic Files for important information on working with OrCAD Schematic Files.

See also:

Renaming a Macrofunction in the Current Project


Ensuring Project Reliability (editor applications)
Ensuring Project Reliability

Altera strongly recommends that you use the Compiler’s Design Doctor utility to check your project for potentially unreliable logic before implementing it in one or more devices.

To ensure project reliability:

1.	When creating a design file, observe the design recommendations given in the Project Reliability Guidelines, as well as the guidelines given in the following topics:

File Type:	Guidelines:

EDIF Input File	EDIF Interface Information

GDF	Graphic Editor Golden Rules

OrCAD Schematic File	Graphic Editor Golden Rules

OrCAD Interface Information

Restrictions on OrCAD Schematic Files in MAX+PLUS II

Guidelines for Working with OrCAD Schematic Files

TDF	AHDL Golden Rules

How to Use AHDL

Text Editor Golden Rules

VHDL Design File	VHDL Golden Rules

How to Use VHDL

Text Editor Golden Rules

WDF	Creating a Waveform Design File

Waveform Editor Golden Rules

XNF File	Xilinx Interface Information

2.	Analyze the project as described in Checking Project Reliability with the Design Doctor.

3.	Edit your design files as needed.

Additional information on how to implement a particular type of design logic may be available in a document listed under Recommended Reading.

See also:

Project Reliability Checklist


Project Reliability Guidelines (editor applications)
Project Reliability Guidelines

The following categories of design guidelines are provided to help you identify and correct potential logic and timing irregularities in your MAX+PLUS II project. The Compiler's Design Doctor utility uses design rules that are based on these guidelines during project analysis.

Asynchronous Inputs	Master Reset

Clock Configurations	Preset & Clear Configurations

Delay Chains	Race Conditions

Expander Networks	Static Hazards

Altera strongly recommends that you use the Compiler's Design Doctor utility to check your project for potentially unreliable logic before implementing it in one or more devices.

The following MAX+PLUS II Help topics provide additional information that will help you create reliable projects:

File Type:	Guidelines:

EDIF Input File	EDIF Interface Information

GDF	Graphic Editor Golden Rules

OrCAD Schematic File	Graphic Editor Golden Rules

OrCAD Interface Information

OrCAD Interface Information

Restrictions on OrCAD Schematic Files in MAX+PLUS II

TDF	AHDL Golden Rules

How to Use AHDL

Text Editor Golden Rules

VHDL Design File	VHDL Golden Rules

How to Use VHDL

Text Editor Golden Rules

WDF	Creating a Waveform Design File

Waveform Editor Golden Rules

XNF File	Xilinx Interface Information

See also:

Checking Project Reliability with the Design Doctor

Ensuring Project Reliability

Project Reliability Checklist

Recommended reading:

AB89 (Minimizing Output Switching Noise in Altera EPLDs)

AB91 (External Clock Sources for Altera EPLDs)

AB94 (Solutions to Design Timing Problems for Altera EPLDs)

AB100 (Understanding Classic, MAX 5000 & MAX 7000 Timing)

AB143 (Understanding FLEX 8000 Timing)

AB144 (Understanding MAX 9000 Timing)

AN22 (Designing with AHDL)

AN26 (EPLD/MPLD Design Guidelines)

AN28 (Waveform Design Entry)

AN42 (Metastability in Altera Devices)


Creating the Default Symbol for a File (editor applications)
Creating the Default Symbol for a File

To create or update a default symbol that represents the current design file:

1.	If you are creating a symbol for an EDIF Input File or a VHDL Design File, you may need to first specify EDIF or VHDL conversion information with the Compiler’s EDIF Netlist Reader Settings or VHDL Netlist Reader Settings command (Interfaces menu), then switch back to the EDIF Input File or VHDL Design File.

2.	Choose Create Default Symbol (File menu).

3.	If you have edited the file, you are asked whether you wish to save the changes. Choose OK to save the edits, or No to discard the edits before creating the symbol.

Create Default Symbol updates (overwrites) the Symbol File that represents the current design file. If the Symbol File had been edited manually, the manual edits are overwritten. If the file is untitled, the Save As (File menu) dialog box opens automatically.

If the file is a text-based design file, Create Default Symbol also executes the syntax-checking portion of the Compiler Netlist Extractor module of the Compiler. If any errors are found, a Message Processor window opens automatically and lists the errors in the file.

Refer to Guidelines for Working with OrCAD Schematic Files for important information on editing symbols in OrCAD Schematic Files.

See also:

Compiling EDIF Input Files

Editing the Symbol for a File

Switching Between MAX+PLUS II Applications

Updating a Symbol in a Graphic Editor File


Editing the Symbol for a File (editor applications)
Editing the Symbol for a File

To edit the symbol that represents the current design file:

1.	Choose Edit Symbol (File menu). A Symbol Editor window opens and displays the Symbol File that represents the current design file.

2.	Edit the symbol.

3.	Choose Save (File menu) to save changes to the symbol or choose Save As (File menu) to save it under a different name.

4.	In the appropriate Graphic Editor file(s), choose Update Symbol (Symbol menu) to update the appearance of the symbol.

1.	A Symbol File must have the same name as the design file it represents.

2.	If you wish to use the graphics from an Altera-provided primitive or macrofunction symbol in one of your own symbols, you must use the Copy and Paste commands (Edit menu) to copy and paste the graphics into your Symbol File. You cannot use Save As to save an Altera-provided Symbol File to another name.

3.	Refer to Guidelines for Working with OrCAD Schematic Files for important information on editing symbols in OrCAD Schematic Files.

See also:

Creating the Default Symbol for a File

Updating a Symbol in a Graphic Editor File


Creating a Default Include File (editor applications)
Creating a Default Include File

To create or update an Include File that represents the current design file:

1.	If you are creating an Include File for an EDIF Input File or a VHDL Design File, you may need to first specify EDIF or VHDL conversion information with the Compiler’s EDIF Netlist Reader Settings or VHDL Netlist Reader Settings command (Interfaces menu), then switch back to the EDIF Input File or VHDL Design File.

2.	Choose Create Default Include File (File menu).

3.	If you have edited the file, you are asked whether you wish to save the changes. Choose OK to save the edits, or No to discard the edits before creating the Include File.

Create Default Include File updates (overwrites) any existing Include File that represents the current design file. If the file is untitled, the Save As (File menu) dialog box opens automatically.

If the file is a text-based design file, Create Default Include File also executes the syntax-checking portion of the Compiler Netlist Extractor module of the Compiler. If any errors are found, a Message Processor window opens automatically and lists the errors in the file.

See also:

Compiling EDIF Input Files

Compiling VHDL Design Files (Compiler)

Include Statement (AHDL)

Include Statement & Include File Rules (AHDL)

Switching Between MAX+PLUS II Applications


Finding Nodes & Symbols in Design Files (editor applications)
Finding Nodes & Symbols in Design Files

To find a node, pin, symbol, or probe anywhere in the current hierarchy tree:

1.	(Optional) Select a single symbol, pin name, node name, or probe. This step is required for some of the shortcuts available in step 2.

2.	Open the Find Node in Design File dialog box by choosing Find Node in Design File (Utilities menu) or using a shortcut.

3.	If you did not select an item in step 1, type a net (symbol) ID number, hierarchical node name, or probe name in the Node Name or Symbol ID box. If you selected a name in step 1, it is displayed in the box.

4.	Choose OK.

or:

1.	Select a single symbol, pin name, node name, or probe.

2.	Choose a shortcut to immediately find the selected item.

MAX+PLUS II opens (or brings to the front) the design file that contains the specified item and highlights it.

See also:

Finding Nodes & Pins in the Floorplan Editor

Hierarchical Node & Symbol Name Syntax

Selecting an Object

Selecting Text


Finding Nodes & Pins in the Floorplan Editor

You can search for one or more nodes or other logic functions--including pins, symbols, and file icons--anywhere in the floorplan for the current project to view their current implementation or assignments. This feature gives you a graphical view of the implementation or assignments of any logic function of interest.

To find one or more nodes and/or pins:

1.	(Optional) Set up your preferred environment for finding and viewing nodes and pins in the Floorplan Editor in one or more of the following ways. Othewise, nodes and pins are located in the view last displayed in the Floorplan Editor:

Choose Current Assignments Floorplan or Last Compilation Floorplan (Layout menu) to determine the floorplan that is displayed.

Choose Device View or LAB View (Layout menu) to specify how you wish to view the information in the floorplan.

If you wish to check a particular chip in a multi-device project, select its name in the Floorplan Editor’s Chip Name field.

(Optional) Turn on Show Path or either or both of the Show Node Fan-In and Show Node Fan-Out commands (Options menu) to show additional signal path information.

2.	(Optional) Select one or more symbols, pin names, or node names in any MAX+PLUS II editor window or select one or more file icons in the Hierarchy Display window. You can use area or object-by-object selection. This step is required for some of the shortcuts available in step 3.

3.	Open the Find Node in Floorplan dialog box by choosing Find Node in Floorplan (Utilities menu) or using a shortcut.

4.	If you did not select any item(s) in step 2, type a net (symbol) ID number, hierarchical node name, or probe name in the Node Name or Symbol ID box. If you selected a name in step 2, it is displayed in the box.

5.	Choose OK. MAX+PLUS II opens (or brings to the front) the floorplan that contains the specified item(s) and highlights them. If your project is implemented in multiple devices, messages are displayed indicating which other chips contain the specified items.

6.	If necessary, select a different chip name in the Chip Name field and repeat steps 2 through 5.

See also:

Finding Nodes & Symbols in Design Files

Hierarchical Node & Symbol Name Syntax

Selecting a File Icon or Name (Hierarchy Display)

Selecting an Object (Graphic Editor)

Selecting Text


Copying, Cutting & Pasting Text (editor applications)
Copying, Cutting & Pasting Text

You can copy, cut, and paste text with menu commands or the keyboard in the Graphic, Text, Waveform, and Symbol Editors.

To copy and paste text:

1.	Select the text to copy.

2.	Choose Copy (Edit menu) or use a shortcut.

3.	Move the cursor to the desired insertion point or select the text to replace.

4.	Choose Paste (Edit menu) or use a shortcut.

To cut and paste text:

1.	Select the text to cut.

2.	Choose Cut (Edit menu) or use a shortcut.

3.	Move the cursor to the desired insertion point or select the text to replace.

4.	Choose Paste or use a shortcut.

Text can be cut and pasted into different MAX+PLUS II files and into different types of text fields. For example, a pin name from a GDF can be pasted into a TDF. An object can be pasted only if it is compatible with the target file format.

If you paste a column of text at the beginning or middle of a text file in the Text Editor, the column is inserted into the file at the insertion point and into subsequent lines. Each line of text in the column is pasted into an existing line (if any). Existing text is not moved down to the end of the column.

See also:

Deleting Text

Selecting Text


Deleting Text (editor applications)
Deleting Text

You can delete text with menu commands or the keyboard in the Graphic, Text, Waveform, and Symbol Editors. In other MAX+PLUS II applications, you can use only the keyboard to delete text, because all text is entered and edited in dialog boxes or because no Edit menu is available.

To delete text or objects with commands, select the text you wish to delete, then choose one of the following Edit menu commands:

Command:	Action:

Cut 	Deletes the selected text from the file and places it on the Clipboard. The contents of the Clipboard can be pasted in the same file or in another file. Shortcuts

Delete 	Deletes the selected text from the file without storing it on the Clipboard. Shortcuts

or:

To delete text with the keyboard, select the text you wish to delete, then press one of the following keys:

Key:	Action:

Backspace	Deletes the character to the left of the insertion point. If text is selected, the text is deleted.

Del	Deletes the character to the right of the insertion point. If text is selected, the text is deleted.

Text can be cut and pasted into different MAX+PLUS II files and into different types of text fields. For example, a pin name from a GDF can be pasted into a TDF. An object can be pasted only if it is compatible with the target file format.

See also:

Copying, Cutting & Pasting Text

Selecting Text


Undoing Edits (editor applications)
Undoing Edits

To undo your last action:

Choose Undo (Edit menu) or use a shortcut.

You cannot undo actions that do not affect the contents of the document, such as scrolling and saving a file. If Undo is not available, the command is dimmed.


-----------------BEGINNING OF NON-TRANSLATED TEXT---------------------------------

This file contains messages from:

maxmsgs

gedmsgs

tedmsgs

wedmsgs

hrwmsgs

-----------------END OF NON-TRANSLATED TEXT---------------------------------


Can’t delete text: <text>

CAUSE:	You have attempted to delete text in a field or have left a text field empty. This field cannot be left blank.

ACTION:	Type at least one character into the text field.

See also:

MAX+PLUS II Messages

Message Format


Can’t find last edit

CAUSE:	You chose Find Last Edit (Utilities menu) to find the last change to the current file, but the file has not been edited.

ACTION:	No action is required.

See also:

MAX+PLUS II Messages

Message Format


Can’t find node or symbol: <text>

CAUSE:	You chose the Locate or Locate All button in the Message Processor, or the Find Node in Design File or Find Node in Floorplan command (Utilities menu), and the specified node name, probe name, or symbol (net) ID number is either incorrect or does not exist in the current file or floorplan. This message may also occur if the name you specified for Find Node in Design File contained wildcard characters, which are not supported.

ACTION:	If you received this message while using the Find Node in Design File or Find Node in Floorplan Editor command, ensure that you typed the correct symbol ID number or node name (and hierarchy path if the node is in a lower-level file). You can avoid errors of this type if you select a symbol or a name instead of typing a name in the dialog box. If you cannot find the specified node in the Floorplan Editor, it may indicate that the node does not exist in the compiled project, i.e., that the node has been eliminated by logic synthesis.

See also:

Finding Text

Finding Nodes & Pins in the Floorplan Editor

Finding Nodes & Symbols in Design Files

Hierarchical Node & Symbol Name Syntax

Locating the Source of a Message

MAX+PLUS II Messages

Message Format


Can’t find text: <text>

CAUSE:	You chose the Search & Replace or Find Text command (Utilities menu) and specified search text that does not exist in the current file or floorplan.

ACTION:	Ensure that the specified search text is typed correctly. Both Find Text and Search & Replace allow you to use wildcard characters. You may also need to change the other options in the dialog box, such as Whole Word, to help you find the search text. If this error occurred in the Floorplan Editor and the project contains multiple chips, you may have to choose a different chip name in the Chip Name field of the Floorplan Editor window, then try to locate the search text again.

See also:

Finding Text

Finding & Replacing Text

MAX+PLUS II Messages

Message Format


Enter or choose a text size between <number> and <number>

CAUSE:	You typed a text size in the Text Size box in the Graphic Editor toolbar or the Text Editor toolbar that is not supported by MAX+PLUS II.

ACTION:	Type a text size between the specified numbers or simply choose a text size either from the Text Size drop-down list box in the toolbar or from the Graphic Editor Text Size submenu or Text Editor Text Size submenu commands.

See also:

Changing the Text Size (Graphic Editor)

Changing the Text Size (Text Editor)

MAX+PLUS II Messages

Message Format


Choose a text size of 7, 10, or 12 -- Altera font is not available in other sizes
Enter or choose a text size of 7, 10, or 12 -- Altera font is not available in other sizes

CAUSE:	You typed a text size in the Text Size box in the Graphic Editor toolbar that is not available in the Altera font.

ACTION:	Choose a supported text size for the Altera font either from the Text Size drop-down list box in the toolbar or from the Graphic Editor’s Text Size submenu commands.

See also:

Changing the Text Size (Graphic Editor)

MAX+PLUS II Messages

Message Format


Font <name> is not supported

CAUSE:	You typed a font name in the Font box in the Graphic Editor toolbar or the Text Editor toolbar that is not supported by MAX+PLUS II.

ACTION:	Type another font name or simply select a font either from the Font drop-down list box in the toolbar or from the Graphic Editor Font submenu or Text Editor Font submenu commands. If you type a font name, it must exactly match the font name shown in the Font submenu or Font drop-down list box.

See also:

Changing the Font (Graphic Editor)

Changing the Font (Text Editor)

MAX+PLUS II Messages

Message Format


Reached beginning of file. Continue search at end?

CAUSE:	Because you turned on Pause at End and selected Up as the direction when searching the file, MAX+PLUS II has paused at the beginning of the file and is asking whether you wish to continue the search from the end of the file back up to the starting point for the search.

ACTION:	Choose Yes to continue the search or choose No to end it.

See also:

Finding Text

Finding & Replacing Text

MAX+PLUS II Messages

Message Format


Reached end of file. Continue search at beginning?

CAUSE:	Because you turned on Pause at End and selected Down as the direction when searching the file, MAX+PLUS II has paused at the end of the file and is asking whether you wish to continue the search from the beginning of the file back down to the starting point for the search.

ACTION:	Choose Yes to continue the search or choose No to end it.

See also:

Finding Text

Finding & Replacing Text

MAX+PLUS II Messages

Message Format


Save changes to <filename>?

CAUSE:	You tried to close a file that has been edited since the last save.

ACTION:	Choose Yes to save all changes before closing the file, No to close the file without saving, or Cancel to keep the file open.

See also:

MAX+PLUS II Messages

Message Format


Save changes to assignments in <filename>?

CAUSE:	You tried to close a file in which only the probe, resource, and/or device assignments have been edited since the last save. This message may occur for files that you have not opened if you have cleared or back-annotated assignments with the Clear Project Assignments or Back-Annotate Project commands (Assign menu).

ACTION:	Choose Yes to save assignment changes before closing the file, No to close the file without saving assignment changes, or Cancel to keep the file open.

See also:

Back-Annotating Assignments for a Project

Clearing Assignments for a Project

MAX+PLUS II Messages

Message Format


Save all changes to <filename>?

CAUSE:	You tried to close a file that has been edited since the last save. Both text and/or graphics, as well as probe, resource, and/or device assignments have been edited since the last save.

ACTION:	Choose Yes to save all changes before closing the file, No to close the file without saving, or Cancel to keep the file open.

See also:

MAX+PLUS II Messages

Message Format


Search complete

CAUSE:	You chose the Search & Replace or Find Text command (Utilities menu) to find a string of text. All occurrences of the search text have been reported to you.

ACTION:	No action is required.

See also:

Finding Text

Finding & Replacing Text

MAX+PLUS II Messages

Message Format


Too many clocks or timers

CAUSE:	You have opened too many clocks or timers (16) in Windows. MAX+PLUS II applications need a Windows timer/clock mechanism to scroll properly.

ACTION:	Close at least one clock or timer to allow MAX+PLUS II to scroll properly.

See also:

MAX+PLUS II Messages

Message Format


Text size <number> is not available in the <name> font

CAUSE:	You typed a text size in the Text Size box in the Text Editor toolbar that is not available for the current font.

ACTION:	Choose a supported text size for the font either from the Text Size drop-down list box in the toolbar or from the Text Editor’s Text Size submenu commands.

See also:

Changing the Text Size (Text Editor)

MAX+PLUS II Messages

Message Format


-----BEGINNING OF NON-TRANSLATED TEXT-----

Messages from e2cmsgs.msg that are documented elsewhere (not in this file):

FE2C_FET_CANT_OPEN_FILE	glmess.mac

FE2C_FET_CANT_WRITE_FILE	glmess.mac

FE2C_FET_OUT_OF_MEMORY	glmess.mac

WE2C_WT_CANT_OPEN_FILE	glmess.mac

FE2C_FET_BAD_LMF_FILE	comess.mac

FE2C_FET_BAD_EDF_FILE	comess.mac

EE2C_ET_YACC_ERROR	comess.mac

EE2C_ET_SYNTAX_BAD_PORT	comess.mac

EE2C_ET_SYNTAX_BAD_KEYWORD	comess.mac

EE2C_ET_SYNTAX_BAD_PRM	comess.mac

EE2C_ET_SYNTAX_BAD_EDF_ID	comess.mac

EE2C_ET_SYNTAX_BAD_ID	comess.mac

EE2C_ET_SYNTX_BAD_EDF_STOK	comess.mac

WE2C_WT_EDF_BAD_MACRO_FUNC_NAME	hrmess.msc

The following s2emsgs.msg messages are not documented in this file:

ws2e_wt_cant_open_cmd_file	glmess.mac

fs2e_fet_out_of_memory	glmess.mac

ws2e_wt_comment_end_missing	ahdlmess.mac

fs2e_fet_cant_write_file	glmess

fs2e_fet_pgm_limit_reached	glmess

ss2e_wt_cant_open_file	glmess

ss2e_wt_cant_format_to_buffer	glmess

Where are these?

ee2c_et_syntax_keyword_error

ee2c_et_syntax_illegal_prim

ee2c_et_syntax_illegal_port

ee2c_et_syntx_illegal_edf_id

ee2c_et_syntax_id_err

ee2c_et_syntax_edf_stokn_err

The following messages from E2CMSGS.MSG are not used:

ME2C_MT_FILES_GENERATED

WE2C_WT_BAD_FILE

WE2C_WT_BAD_PART_NAME

WE2C_WT_BAD_SECURITY

WE2C_WT_BAD_TURBO

WE2C_WT_CFG_BAD_EXP_MEM_VALUE

WE2C_WT_EDF_BAD_DESIGN_DEF1

WE2C_WT_EDF_BAD_INSTNCE_DEF1

WE2C_WT_EDF_SRC_MAPPED_OUT

WE2C_WT_EMM_ERROR

WE2C_WT_EMM_OUT_OF_MEMORY

WE2C_WT_LMF_NO_VCC_GND

WE2C_WT_MULT_GND_OPTION

WE2C_WT_MULT_VCC_OPTION

Messages beginning with FE2C_FET_

     except for FE2C_FET_PGM_LIMIT_REACHED	(in this .mac file)

FE2C_FET_BAD_FILE_PATH	(in this .mac file)

FE2C_FET_PARSER_ERROR	?where--may be needs to be doc'd?

-----END OF NON-TRANSLATED TEXT-----


CellRef must include libraryRef when used in design definition

CAUSE:	The design definition in your EDIF Input File contains a cellRef construct that is not accompanied by a libraryRef construct.

ACTION:	In general, it is better to correct only the source design file rather than the EDIF Input File. If you prefer to edit the EDIF Input file, make sure that it conforms to the format for EDIF version 2 0 0 or 2 9 0. If necessary, refer to your EDIF manual.

See also:

MAX+PLUS II Messages

Message Format


EDIF cell <name> already has LMF mapping so contents construct has been ignored

CAUSE:	A cell in an EDIF Input File has a mapping in an LMF, so the contents section of that cell was ignored by the Compiler.

ACTION:	No action is required. If you do not wish to receive this message during future compilations, remove the contents section of cells that have LMF mappings.

See also:

Library Mapping File Format

MAX+PLUS II Messages

Message Format

Recommended reading:

AB96 (Generating Library Mapping Files)


EDIF cell <name> differs from LMF declaration

CAUSE:	A cell in an EDIF Input File does not match the EDIF cell declared in the LMF, i.e., the ports do not have the same names or number. A CNF will therefore be generated for the cell.

ACTION:	Make sure that the EDIF cell in your LMF has the same definition as the EDIF cell in your EDIF Input File if you want to substitute a MAX+PLUS II function for the cell.

See also:

Library Mapping File Format

MAX+PLUS II Messages

Message Format

Preserving Net & Instance Names in EDIF Input Files

Recommended reading:

AB96 (Generating Library Mapping Files)


EDIF cell or port<name> has LMF mapping
EDIF cell [or port] <name> has LMF mapping

CAUSE:	A cell or port in an EDIF Input File has an LMF mapping.

ACTION:	No action is required.

See also:

MAX+PLUS II Messages

Message Format

Recommended reading:

AB96 (Generating Library Mapping Files)


EDIF cell <name> has multiple mappings ­ only the first mapping is accepted (others are ignored)
EDIF cell <name> has multiple mappings -- only the first mapping is accepted (others are ignored)

CAUSE:	A cell in an EDIF Input File has multiple mappings in one of the LMFs you submitted to the Compiler. The Compiler is ignoring all but the first mapping of the cell.

ACTION:	A cell should be mapped only once in all LMFs. However, if you are sure all mappings of the cell are identical, no action is required.

See also:

Library Mapping File Format

MAX+PLUS II Messages

Message Format

Recommended reading:

AB96 (Generating Library Mapping Files)


EDIF Input File is too large to be processed

CAUSE:	An EDIF Input File was too large for the Compiler to process.

ACTION:	Partition the original design file or your EDIF Input File(s) into smaller parts. Try using more hierarchy levels in the project.

See also:

Patitioning a Project

MAX+PLUS II Messages

Message Format


EDIF <text> signal name not specified ­ defaulting to <text>
EDIF VCC [or GND] signal name not specified -- defaulting to <text>

CAUSE:	You did not specify a value in the EDIF Netlist Reader dialog box for the global high or low signal used in EDIF Input Files. The Compiler is using GND or VCC as the default.

ACTION:	If your EDIF Input File uses an identifier other than GND or VCC, change the entries in the EDIF Netlist Reader dialog box and recompile the project.

See also:

Compiling EDIF Input Files

MAX+PLUS II Messages

Message Format


Ignored definition of <construct name> <construct>

CAUSE:	The Compiler cannot find a design or instance definition in an EDIF Input File, the construct is not defined, or the construct has an illegal definition. The construct was ignored.

ACTION:	In general, it is better to correct only the source design file rather than the EDIF Input File. If you prefer to edit the EDIF Input File, be sure to define the construct before using it. Also, make sure that it conforms to the format for EDIF version 2 0 0 or 2 9 0. If necessary, consult your EDIF manual.

See also:

MAX+PLUS II Messages

Message Format


Ignored illegal alias -- <alias>

CAUSE:	You used the same alias more than once in an EDIF Command File, so the Compiler ignored the alias.

ACTION:	Change the duplicate alias name in your EDIF Command File.

See also:

EDIF Command File Format

MAX+PLUS II Messages

Message Format


Ignored illegal command: <command>

CAUSE:	An EDIF Command File contains an illegal command, so the Compiler ignored the command.

ACTION:	Use a legal command.

See also:

EDIF Command File Format

MAX+PLUS II Messages

Message Format


Ignored missing or illegal EDIF <text> [defaulting to <text>]

CAUSE:	The first <text> in this message indicates that there is a missing or illegal EDIF identifier, EDIF level (only 0 is allowed), or EDIF keyword level (only 0 or 1 is allowed) in an EDIF Command File. The Compiler will default to 0 in the case of a missing or illegal EDIF level or keyword level.

ACTION:	Make sure that your EDIF level is 0, the EDIF keyword level is 0 or 1, or that you are using a legal EDIF identifier. For further information, consult the Electronic Design Interchange Format Version 2 0 0 manual.

See also:

EDIF Command File Format

MAX+PLUS II Messages

Message Format


Ignored redefinition of <construct name> [<construct>] [property]

CAUSE:	A cell, design, instance, library, net, port, etc. construct in an EDIF Input File was defined twice. Or a pin, logic cell, chip, clique, or logic option assignment was defined twice in the EDIF Input File. These constructs and properties can only be defined once in an file.

ACTION:	In general, it is better to correct only the source design file rather than the EDIF Input File. If you prefer to edit the EDIF Input File, ensure that constructs and properties with the same name have unique definitions and that the file conforms to the format for EDIF version 2 0 0 or 2 9 0. Consult your EDIF manual if necessary.

See also:

Assigning Resources in a Third-Party Design Editor

MAX+PLUS II Messages

Message Format

Recommended reading:

AN29 (Cadence Concept & MAX+PLUS II Logic Design)

AN30 (Viewlogic Workview PLUS & MAX+PLUS II Logic Design)

AN32 (Mentor Graphics & MAX+PLUS II Logic Design)

AN34 (Synopsys & MAX+PLUS II Logic Design)

AN37 (Viewlogic Powerview & MAX+PLUS II Logic Design)


Ignored redundant portRef

CAUSE:	You listed a port reference twice in an EDIF Input File.

ACTION:	In general, it is better to correct only the source design file rather than the EDIF Input File. If you prefer to edit the EDIF Input File, you must remove the redundant reference.

See also:

MAX+PLUS II Messages

Message Format


Illegal extension [<extension>] ­ use only <extension>
Illegal extension [<extension>] -- use only <extension>

CAUSE:	You entered a filename extension other than .edf for an EDIF Input File or .lmf for a Library Mapping File.

ACTION:	You must use the correct .edf or .lmf extension as specified in the message.

See also:

Compiling EDIF Input Files

MAX+PLUS II Messages

Message Format


Illegal file path or path too long: <pathname>

CAUSE:	You used a pathname that was incorrect or too long (over 256 characters).

ACTION:	Ensure that the pathname is correct. If the pathname is too long, eliminate some of your intermediate directories or move the EDIF Input File to a subdirectory with a shorter name.

See also:

MAX+PLUS II Messages

Message Format


Illegal global <text> specification
Illegal global <text> specification (<text>)

CAUSE:	You entered an illegal name for the global VCC or GND signal in the EDIF Netlist Reader dialog box.

ACTION:	Ensure that the global VCC or GND signals specified are the same ones that your EDIF netlist writer uses in the EDIF Input File.

See also:

Compiling EDIF Input Files

MAX+PLUS II Messages

Message Format


Illegal GND or VCC signal name <name> -- defaulting to <signal name>
 Illegal GND [or VCC] signal name <name> -- defaulting to signal <name>

CAUSE:	You choose EDIF Netlist Reader and entered an illegal VCC or GND signal name

ACTION:	Ensure you enter the correct equivalent string token for GND or VCC.

See also:

Compiling EDIF Input Files

MAX+PLUS II Messages

Message Format


Ignored illegal name <name> in instance rename construct -- using identifier <name>

CAUSE:	The current EDIF Input File contains an instance rename construct, but the renamed string is illegal in MAX+PLUS II. Therefore, MAX+PLUS II has substituted the specified EDIF <identifier>.

ACTION:	If you do not wish to use the specified EDIF <identifier>, change the name. In general, you should correct only the source design file rather than the EDIF Input File. If you prefer to edit the EDIF Input File, make sure that the renamed string for the instance rename construct contains no more than 32 name characters. If necessary, consult your EDIF manual.

See also:

EDIF 2 0 0 Constructs Interpreted by MAX+PLUS II

EDIF 2 9 0 Constructs Interpreted by MAX+PLUS II

MAX+PLUS II Messages

Message Format


Ignored illegal name <name> in net rename construct -- using identifier <name>

CAUSE:	The current EDIF Input File contains a net rename construct, but the renamed string is illegal in MAX+PLUS II. Therefore, MAX+PLUS II has substituted the specified EDIF <identifier>.

ACTION:	If you do not wish to use the specified EDIF <identifier>, change the name. In general, you should correct only the source design file rather than the EDIF Input File. If you prefer to edit the EDIF Input File, make sure that the renamed string for the net rename construct is a name that contains no more than 32 name characters. If necessary, consult your EDIF manual.

See also:

EDIF 2 0 0 Constructs Interpreted by MAX+PLUS II

EDIF 2 9 0 Constructs Interpreted by MAX+PLUS II

MAX+PLUS II Messages

Message Format


Illegal port direction <direction> ­ defaulting to INPUT
Illegal port direction <direction> -- defaulting to INPUT

CAUSE:	You have an illegal port direction, i.e., a direction other than INPUT, OUTPUT, or INOUT, for a port in an EDIF Input File.

ACTION:	In general, it is better to correct only the source design file rather than the EDIF Input File. If you prefer to edit the EDIF Input File, make sure that all port directions are either INPUT, OUTPUT, or INOUT. If necessary, consult your EDIF manual.

See also:

Assigning Resources in a Third-Party Design Editor

MAX+PLUS II Messages

Message Format

Specifying Port Directions in EDIF Input Files

Recommended reading:

AN29 (Cadence Concept & MAX+PLUS II Logic Design)

AN30 (Viewlogic Workview PLUS & MAX+PLUS II Logic Design)

AN32 (Mentor Graphics & MAX+PLUS II Logic Design)

AN34 (Synopsys & MAX+PLUS II Logic Design)

AN37 (Viewlogic Powerview & MAX+PLUS II Logic Design)


Illegal port direction ­ mapping is ignored
Illegal port direction -- mapping is ignored

CAUSE:	You specified the wrong direction for one or more ports in the mapping of a MAX+PLUS II primitive in an LMF.

ACTION:	Change the primitive mapping.

See also:

Library Mapping File Format

MAX+PLUS II Messages

Message Format

Specifying Port Directions in EDIF Input Files

Recommended reading:

AB96 (Generating Library Mapping Files)

AN29 (Cadence Concept & MAX+PLUS II Logic Design)

AN30 (Viewlogic Workview PLUS & MAX+PLUS II Logic Design)

AN32 (Mentor Graphics & MAX+PLUS II Logic Design)

AN34 (Synopsys & MAX+PLUS II Logic Design)

AN37 (Viewlogic Powerview & MAX+PLUS II Logic Design)


 Input removed by mapping

CAUSE:	In an LMF, you have mapped an MAX+PLUS II function input to GND or VCC,and the mapping removed the input.

ACTION:	If you intend to map the MAX+PLUS II function input to GND or VCC, no action is required. Otherwise, ensure that the input is correctly mapped in the LMF.

See also:

Library Mapping File Format

Mapping Unequal Numbers of Inputs & Outputs

MAX+PLUS II Messages

Message Format

Recommended reading:

AB96 (Generating Library Mapping Files)

AN29 (Cadence Concept & MAX+PLUS II Logic Design)

AN30 (Viewlogic Workview PLUS & MAX+PLUS II Logic Design)

AN32 (Mentor Graphics & MAX+PLUS II Logic Design)

AN34 (Synopsys & MAX+PLUS II Logic Design)

AN37 (Viewlogic Powerview & MAX+PLUS II Logic Design)


Line is too long - has over <number> characters
Line is too long -- has over <number> characters

CAUSE:	The specified line in a text file has too many characters.

ACTION:	Check the file for errors and insert return or newline characters to break up the line, as appropriate.

See also:

MAX+PLUS II Messages

Message Format


MAX+PLUS II II cell <name> differs from previous declaration ­ only the first mapping is accepted (others are ignored)
MAX+PLUS II cell <name> differs from previous declaration -- only the first mapping is accepted (others are ignored)

CAUSE:	A MAX+PLUS II function in an LMF is declared repeatedly, but the definitions of the function differ, i.e., the function has different names or numbers of ports. The Compiler ignored all but the first mapping.

ACTION:	Make sure that all MAX+PLUS II functions that are used repeatedly are defined identically in all LMFs.

See also:

Library Mapping File Format

MAX+PLUS II Messages

Message Format


MAX+PLUS II II primitive port does not exist ­ mapping is ignored
MAX+PLUS II primitive port <name> does not exist -- mapping is ignored

CAUSE:	You specified a non-existent primitive port in an LMF mapping.

ACTION:	Change the primitive mapping.

See also:

Library Mapping File Format

MAX+PLUS II Messages

Message Format

Recommended reading:

AB96 (Generating Library Mapping Files)


Mismatched number of ports in LMF mapping and EDIF cell ­ mapping is ignored
Mismatched number of ports in LMF mapping and EDIF cell -- mapping is ignored

CAUSE:	The ports in an LMF mapping are not in a one-to-one correspondence, i.e., the number of inputs or outputs in the MAX+PLUS II function does not match the number of inputs or outputs in the EDIF cell.

ACTION:	Make sure that all LMF pairs of FUNCTION_RETURNS statements have a one-to-one port correspondence.

See also:

Library Mapping File Format

Mapping Unequal Numbers of Inputs & Outputs

MAX+PLUS II Messages

Message Format

Recommended reading:

AB96 (Generating Library Mapping Files)


Missing or illegal <construct>Ref <name> <construct> definition

CAUSE:	You have used a cell, instance, library, port, etc. construct in an EDIF Input File that does not exist or has an illegal definition. The reference was ignored by the Compiler.

ACTION:	You probably did not define the construct before using it. In general, it is better to correct only the source design file rather than the EDIF Input File. If you want to edit the EDIF Input File, ensure that your EDF conforms to the format for EDIF version 2 0 0 or 2 9 0. Refer to your EDIF manual if necessary.

See also:

Assigning Resources in a Third-Party Design Editor

EDIF Constructs Interpreted by MAX+PLUS II

MAX+PLUS II Messages

Message Format


Missing port direction ­ defaulting to INPUT
Missing port direction -- defaulting to INPUT

CAUSE:	You did not specify a port direction for a port in an EDIF Input File.

ACTION:	In general, it is better to correct only the source design file rather than the EDIF Input File. If you prefer to edit the EDIF Input File, make sure that all port directions are either INPUT, OUTPUT, or INOUT. Refer to your EDIF manual if necessary.

See also:

MAX+PLUS II Messages

Message Format

Specifying Port Directions in EDIF Input Files


Net has <text>

CAUSE:	The <text> of this message indicates that you specified either multiple sources or no source for a Net construct in an EDIF Input File. Nets must have one and only one source.

ACTION:	In general, it is better to correct only the source design file rather than the EDIF Input File. If you prefer to edit the EDIF Input File, make sure that the Net construct has only one source. Refer to your EDIF manual if necessary.

See also:

Library Mapping File Format

MAX+PLUS II Messages

Message Format

Preserving Net & Instance Names in EDIF Input Files


Not all MAX+PLUS II II primitive ports are mapped ­ mapping is ignored
Not all MAX+PLUS II primitive ports are mapped -- mapping is ignored

CAUSE:	You did not list all the ports in the mapping of a MAX+PLUS II primitive in an LMF.

ACTION:	Change the primitive mapping.

See also:

Library Mapping File Format

MAX+PLUS II Messages

Message Format


Only EDIF level 0 is allowed ­ ignored <text> definition
Only EDIF level 0 is allowed -- ignored <text> definition

CAUSE:	You specified an EDIF level other than 0 in an EDIF Input File or library definition.

ACTION:	Change the EDIF level to 0 and be sure to use only EDIF level 0 constructs in your EDIF Input file.

See also:

MAX+PLUS II Messages

Message Format


 Only EDIF Version 2 0 0 or 2 9 0 is allowed -- ignored <text> EDIF definition

CAUSE:	You specified an EDIF version other than 2 0 0 or 2 9 0 in an EDIF Input File.

ACTION:	Use only EDIF Version 2 0 0 or 2 9 0 in your EDIF Input file. In general, it is better to correct only the source design file rather than the EDIF Input File. Refer to your EDIF manual if necessary.

See also:

MAX+PLUS II Messages

Message Format


Only GENERIC CellType is allowed ­ ignored <cell name> cell definition
Only GENERIC cellType is allowed -- ignored <cell name> cell definition

CAUSE:	You specified a cellType other than GENERIC in a cell definition in an EDIF Input File.

ACTION:	In general, it is better to correct only the source design file rather than the EDIF Input File. If you prefer to edit the EDIF Input File, change all cells in your EDF to cellType GENERIC. Refer to your EDIF manual if necessary.

See also:

EDIF Constructs Interpreted by MAX+PLUS II

MAX+PLUS II Messages

Message Format


Only NETLIST ViewType is allowed ­ ignored <view name> view definition
Only NETLIST ViewType is allowed -- ignored <view name> view definition

CAUSE:	You specified a ViewType other than NETLIST in a view definition in an EDIF Input File.

ACTION:	Ensure that your EDIF netlist writer uses the NETLIST ViewType. If it does not, you must use another EDIF netlist writer before you can use the MAX+PLUS II Compiler.

See also:

EDIF Constructs Interpreted by MAX+PLUS II

MAX+PLUS II Messages

Message Format


 Output tied to VCC/GND for <signal name> -- mapping is ignored

CAUSE:	You have specified the default of an MAX+PLUS II function output in an LMF as GND or VCC. Only MAX+PLUS II function inputs can have the default set to GND or VCC.

ACTION:	Ensure the outputs are mapped to the appropriate ports. Or you can ignore extra MAX+PLUS II function outputs by inserting a pair of double quotation marks (") in the EDIF FUNCTION-RETURNS statement to indicate that the corresponding MAX+PLUS II port is ignored.

See also:

Library Mapping File Format

Mapping Unequal Numbers of Inputs & Outputs

MAX+PLUS II Messages

Message Format

Recommended reading:

AB96 (Generating Library Mapping Files)


Processing EDIF Input File <filename> ...

CAUSE:	The Compiler is processing the specified EDIF Input File.

ACTION:	No action is required.

See also:

MAX+PLUS II Messages

Message Format


Processing Library Mapping File <filename> ...

CAUSE:	The Compiler is processing the specified LMF.

ACTION:	No action is required.

See also:

MAX+PLUS II Messages

Message Format


 Source <name> removed by mapping

CAUSE:	In an LMF, you have specified that an output of a MAX+PLUS II function should be ignored. However, a corresponding source cell in the workstation function exists.

ACTION:	Ensure that the MAX+PLUS II function output is mapped correctly in the LMF.

See also:

Library Mapping File Format

Mapping Unequal Numbers of Inputs & Outputs

MAX+PLUS II Messages

Message Format

Recommended reading:

AB96 (Generating Library Mapping Files)


Too many/few arguments for command: <command>

CAUSE:	The specified command in an EDIF Command File is followed by too many or too few arguments and has been ignored.

ACTION:	Change the command to the correct format.

See also:

EDIF Command File Format

MAX+PLUS II Messages

Message Format


VCC/GND must be specified for <signal name> -- mapping is ignored
 VCC/GND must be specified for <node name> -- mapping is ignored

CAUSE:	A MAX+PLUS II function in an LMF has more inputs than an equivalent third-party function. These inputs must be tied to GND or VCC.

ACTION:	Ensure that the extra inputs are mapped in the LMF. Map the extra inputs to GND or VCC by including the EDIF string token for GND or VCC enclosed in double quotation marks (" ") in the LMF.

See also:

Library Mapping File Format

Mapping Unequal Numbers of Inputs & Outputs

MAX+PLUS II Messages

Message Format

Recommended reading:

AB96 (Generating Library Mapping Files)


Retrieve Command (editor applications)
Retrieve Command (File Menu)

Closes the current file and opens another file in the same window as the current file, automatically starting the appropriate MAX+PLUS II editor and making the file the top of the current hierarchy.

Retrieve allows you to edit a new file without opening a new window. If you have edited the current file, MAX+PLUS II asks if you wish to save the changes.

Click Button 1 on any item in this dialog box for information on that item:

Use the built-in hierarchy traversal features in MAX+PLUS II to move between design files for the current hierarchy tree. To open a lower-level file in a hierarchy, open the top-level file and then use the Hierarchy Display window or Hierarchy Down (File menu) to open the lower-level files. If you choose Open or Retrieve (File menu) to open a lower-level file, it is considered to be the top of a different hierarchy, and resource, device, and probe assignments that you enter are saved only for that hierarchy, not for the project.

See also:

Guidelines for Working with Assignments

Opening a File

Retrieving a File


Retrieve dialog box

Click Button 1 on any item in this dialog box for information on that item:


Close Command (editor applications)
Close Command (File Menu)

Shortcuts

Closes the current active file window.

If you have edited the file, MAX+PLUS II asks if you wish to save the changes. If the file is untitled, the Save As dialog box (File menu) opens automatically.

After the file is closed, the next active window is displayed.

See also:

Closing a File

Exiting from MAX+PLUS II


Save Command (editor applications)
Save Command (File Menu)

Shortcuts

Saves changes to the current file. The file is saved to the current filename and extension, as shown in the title bar.

If the file is untitled, the Save As dialog box (File menu) opens automatically.

Use Save to update a file on disk with your most recent changes. Use Save As to save a copy of a file under a new name or in a different directory, without affecting the file that is already on disk.

When you save an OrCAD Schematic File in the Graphic Editor, some information from the original file is lost. Refer to Restrictions on OrCAD Schematic Files in MAX+PLUS II and Guidelines for Working with OrCAD Schematic Files for important information on working with OrCAD Schematic Files.

See also:

Project Save & Check Command

Project Save & Compile Command

Project Save & Simulate Command

Project Save, Compile & Simulate Command

Saving a File


Save As dialog box

Click Button 1 on any item in this dialog box for information on that item:


--------------------BEGINNING OF NON-TRANSLATED TEXT-----------------------------------------------

the L keyword MAX File Save & Check should really be in the kefixits panel for unavailable toolbar buttons. But, MAX+PLUS II software so we will put it here for 4.0 release.

--------------------END OF NON-TRANSLATED TEXT-----------------------------------------------


Project Save & Check Command (all applications)
Project Save & Check Command (File Menu)

Shortcuts

Saves and partially compiles the current project by submitting it to the Compiler Netlist Extractor and Database Builder modules of the Compiler.

Project Save & Check saves all open files, including both design files and ancillary files that are Compiler inputs, in the current MAX+PLUS II session, regardless of whether they are part of the current project.

The Compiler Netlist Extractor and Database Builder check the project files for basic errors; update the hierarchy tree in the Hierarchy Display window; and creates a Node Database File for the project.

If the current active window contains an untitled file, the Save As dialog box (File menu) opens automatically.

If any errors are found, a Message Processor window opens automatically and lists the errors in the project. If the files are free of syntax errors, one or more CNFs and a HIF are created.

Project Save & Check is not available if the project is untitled or if MAX+PLUS II is running a background process.

All node and pin names in the Node Database File created by Project Save & Check can be viewed and selected in the Search Node Database dialog box. However, only pin names in the Node Database File appear and are assignable in the Floorplan Editor window. To assign buried nodes in the Floorplan Editor, you must fully compile the project.

See also:

Compiling a Project

Project Save & Compile Command

Project Save & Simulate Command

Project Save, Compile & Simulate Command

Save Command

Saving a File


Info Command (editor applications)
Info Command (File Menu)

Shortcuts

Displays information on the current file.

Click Button 1 on any item in this dialog box for information on that item:


File Name is

Shows the name of the current file.


Date Last Saved is

Shows the date and time that the current file was last saved.


File Size on Disk is

Shows the size of the current file in bytes.


Unsaved Edits in File?

Shows whether the current file contains any edits that have not been saved.


OK (Info command)
OK

Closes the dialog box.


Info dialog box

Click Button 1 on any item in this dialog box for information on that item:


Create Default Symbol Command (editor applications)
Create Default Symbol Command (File Menu)

Creates a new symbol that represents the current design file.

Create Default Symbol updates (overwrites) the Symbol File that represents the current file.

If the file is a text-based design file, Create Default Symbol also executes the syntax-checking portion of the Compiler Netlist Extractor module of the Compiler. If any errors are found, a Message Processor window opens automatically and lists the errors in the file.

This command is not available if the current file is untitled, if the current file is not a design file, or if MAX+PLUS II is running a background process.

1.	When you create a default symbol for an EDIF Input File or a VHDL Design File, you may need to first specify EDIF conversion information with the Compiler’s EDIF Netlist Reader Settings or VHDL Netlist Reader Settings command (Processing menu).

2.	Refer to Guidelines for Working with OrCAD Schematic Files for important information on editing symbols in OrCAD Schematic Files.

See also:

Compiling a Project

Compiling EDIF Input Files (Compiler)

Compiling VHDL Design Files (Compiler)

Creating the Default Symbol for a File

Editing the Symbol for a File


Edit Symbol Command (editor applications)
Edit Symbol Command (File Menu)

Opens a Symbol Editor window and the Symbol File containing the symbol that represents the current design file.

The Symbol Editor allows you to edit the symbol that represents the current file, for example, to move a pinstub to a different position, or to add or delete a parameter.

To create a default symbol or overwrite a manually edited symbol for the current file, choose Create Default Symbol (File menu).

If you wish to use the graphics from an Altera-provided primitive symbol in one of your own symbols, you must use the Copy and Paste commands (Edit menu) to copy and paste the graphics into your Symbol File. You cannot use Save As (File menu) to save a primitive’s Symbol File to another name.

Edit Symbol is available only if the current file has been saved with a filename extension that identifies it as a design file and if a Symbol File already exists for the current file.

Refer to Guidelines for Working with OrCAD Schematic Files for important information on editing symbols in OrCAD Schematic Files.

See also:

Creating the Default Symbol for a File

Editing the Symbol for a File


Create Default Include File Command (editor applications)
Create Default Include File Command (File Menu)

Creates a new AHDL Include File containing a Function Prototype that represents the current design file.

Create Default Include File updates (overwrites) the Include File that represents the current file.

If the file is a text-based design file, Create Default Include File also executes the syntax-checking portion of the Compiler Netlist Extractor module of the Compiler. If any errors are found, a Message Processor window opens automatically and lists the errors in the file.

This command is not available if the current file is untitled, if the current file is not a design file, or if MAX+PLUS II is running a background process.

When you create a default Include File for an EDIF Input File or a VHDL Design File, you may need to first specify EDIF conversion information with the Compiler’s EDIF Netlist Reader Settings or VHDL Netlist Reader Settings command (Processing menu).

See also:

Compiling a Project

Compiling EDIF Input Files

Compiling VHDL Design Files

Creating a Default Include File

Include Statement (AHDL)

Include Statement & Include File Rules (AHDL)


Undo Command (editor applications)
Undo Command (Edit Menu)

Shortcuts

Reverses the last action that changed the current file.

The Undo command name reflects your last edit. For example, if your last edit was Cut (Edit menu), the command is shown as Undo Cut.

After you undo an edit, Undo on the menu changes to Undo Undo, so that the undo can also be canceled.

Some actions, such as scrolling and saving a file, cannot be undone. If Undo is not available, the command is dimmed.

See also:

Undoing Edits


Delete Command (editor applications)
Delete Command (Edit Menu)

Shortcuts

Deletes the selected item(s) from the current file without storing it on the Clipboard.

To remove a selection from the file and store a copy of it on the Clipboard, use Cut (Edit menu).

See also:

Deleting a Node or Group (Waveform Editor)

Deleting a Waveform (Waveform Editor)

Deleting an Assignment

Deleting an Object (Graphic Editor)

Deleting Text

Deleting a Parameter (Graphic Editor)


Find Node in Design File Command
Find Node in Design File Command (Utilities Menu)

Shortcuts

Finds a single node, another logic function, or probe anywhere in the current hierarchy of design files.

Click Button 1 on any item in this dialog box for information on that item:

MAX+PLUS II opens (or brings to the front) the design file that contains the specified node, symbol, or probe and highlights it.

See also:

Finding Nodes & Pins in the Floorplan Editor

Finding Nodes & Symbols in Design Files

Hierarchical Node & Symbol Names

Hierarchical Node & Symbol Name Syntax


Node Name or Symbol ID; find node in design file
Node Name or Symbol ID

Specifies the name of a node, logic function, or probe to be found in the current hierarchy tree. If you selected a name before choosing Find Node in Design File, it is displayed as the default.

You can enter a hierarchical node name, a net (symbol) ID, or a probe name. This name is automatically appended to the hierarchy path for the current design file, as shown in the dialog box. You can also enter an absolute path or relative path to specify a different hierarchical level in the current hierarchy tree.


Find Node in Design File dialog box

Click Button 1 on any item in this dialog box for information on that item:


Find Node in Floorplan Command
Find Node in Floorplan Command (Utilities Menu)

Shortcuts

Finds one or more nodes or other logic function(s) in the floorplan for the current project.

Click Button 1 on any item in this dialog box for information on that item:

MAX+PLUS II opens (or brings to the front) the Floorplan Editor, and highlights the logic cell(s), I/O cell(s), and/or pin(s) where the function is implemented. Find Node in Floorplan locates the specified item(s) in whichever type of floorplan is currently displayed in the Floorplan Editor window. For example, if the Floorplan Editor is already displaying the floorplan of the current assignments for the project, Find Node in Floorplan locates and highlights the specified item(s) in the current assignments; if the Floorplan Editor is already displaying the floorplan for the project’s last compilation, this command locates the specified items in the floorplan for the last compilation.

1.	Find Node in Floorplan finds nodes and other logic functions in one chip at a time. To locate an item in a different chip in a multi-device project, select its name in the Floorplan Editor’s Chip Name field before choosing Find Node in Floorplan.

2.	Find Node in Floorplan finds nodes and other logic functions only if they have been implemented in a device. If a node is not assigned to a physical location on the device, i.e., if it is listed in the Unassigned Nodes & Pins box, you can use the Floorplan Editor’s Find Text command (Utilities menu) to find it.

See also:

Finding Nodes & Pins in the Floorplan Editor

Finding Nodes & Symbols in Design Files

Hierarchical Node & Symbol Names

Hierarchical Node & Symbol Name Syntax


Node Name or Symbol ID; find node in floorplan
Node Name or Symbol ID

Specifies the name of a node or other logic function to be found in the floorplan for the current project. If you selected a name, symbol, or file icon before choosing Find Node in Floorplan, it is displayed as the default. If you selected multiple items before choosing this command, the text **-Multiple Items-** is displayed.

You can enter a hierarchical node name or a net (symbol) ID. This name is automatically appended to the hierarchy path for the current design file.


Find Node in Floorplan dialog box

Click Button 1 on any item in this dialog box for information on that item:


Find Last Edit Command (editor applications)
Find Last Edit Command (Utilities Menu)

Moves the insertion point to the location of the previous edit.

If you last edited text in the Text Editor, the insertion point is moved to the beginning of the edited text. If you last edited an object in the Graphic Editor or a waveform in the Waveform Editor, the window scrolls to the location of the edit and the edited object or waveform is highlighted. If you last deleted text, an object, or a waveform, the window scrolls to the location of the deletion.


Analyze Timing Command (editor applications)
Analyze Timing Command (Utilities Menu)

Runs the Timing Analyzer in the current timing analysis mode.

Analyze Timing automatically opens the Timing Analyzer window and shows the results of the analysis. The current analysis mode is defined as the mode that was last selected in the Timing Analyzer, i.e., selected with the Delay Matrix, Setup/Hold Matrix,or Registered Performance command (Analysis menu).

See also:

Running a Timing Analysis


Timing Analysis Source Command (editor applications)
Timing Analysis Source Command (Utilities Menu)

Shortcuts

Tags or untags a single selected node in the Text Editor or one or more selected nodes in the Graphic, Waveform, or Floorplan Editor as source node(s) for timing analysis, and cancels default timing tagging for source nodes performed by the Timing Analyzer.

In the Text Editor, you select a single node name before choosing Timing Analysis Source. In the Waveform Editor, you can select one or more nodes and groups; in the Graphic Editor, you can select nodes, buses, and/or symbols; in the Floorplan Editor, you can select nodes that have been assigned to logic cells, I/O cells, and pins. You can also tag nodes as timing analysis sources with the Timing Analyzer’s own Timing Analysis Source command, which opens a dialog box that shows all non-default tagged source nodes in the project.

The Timing Analyzer analyzes the project’s timing characteristics on the basis of the Time Restrictions command (Options menu) and the cutoff, source and destination nodes selected with Timing Analysis Cutoff, Timing Source, and Timing Analysis Destination. If you do not tag source and destination nodes, default timing tagging is used.

After tagging source and destination nodes, you can choose Analyze Timing (Utilities menu) to run the Timing Analyzer. The Timing Analyzer window opens automatically and shows the results of the analysis.

Timing Analysis Source is available only if a timing SNF exists for the current project.

The Timing Analysis Source, Timing Analysis Destination, Timing Analysis Cutoff, and Clear All Timing Analysis Tags commands are used only for post-compilation timing analysis. To enter timing assignments that affect compilation, use the Timing Requirements and Global Project Timing Requirements commands (Assign menu).

See also:

Clearing Timing Analysis Tags

Creating a Timing Simulator Netlist File

Running a Timing Analysis

Tagging Timing Analysis Cutoff Nodes

Tagging Timing Analysis Source & Destination Nodes

Recommended reading:

AB94 (Solutions to Design Timing Problems for Altera EPLDs)

AB100 Understanding Classic, MAX 5000 & MAX 7000 Timing

AB143 (Understanding FLEX 8000 Timing)

AB144 (Understanding MAX 9000 Timing)

AN42 (Metastability in Altera Devices)


Timing Analysis Destination Command (editor applications)
Timing Analysis Destination Command (Utilities Menu)

Shortcuts

Tags or untags a single selected node in the Text Editor or one or more selected nodes in the Graphic or Waveform Editor in the current file as destination node(s) for timing analysis, and cancels all default timing tagging for destination nodes performed by the Timing Analyzer.

In the Text Editor, you select a single node name before choosing Timing Analysis Destination. In the Waveform Editor, you can select one or more nodes and groups; in the Graphic Editor, you can select nodes, buses, and/or symbols; in the Floorplan Editor, you can select nodes that have been assigned to logic cells, I/O cells, and pins. You can also tag nodes as timing destinations with the Timing Analyzer’s own Timing Analysis Destination command, which opens a dialog box that shows all non-default tagged destination nodes in the project.

The Timing Analyzer analyzes the project’s timing characteristics on the basis of the Time Restrictions command (Options menu) and the cutoff, source and destination nodes selected with Timing Analysis Cutoff, Timing Analysis Source, and Timing Analysis Destination. If you do not tag source and destination nodes, default timing tagging is used.

After tagging source and destination nodes, you can choose Analyze Timing (Utilities menu) to run the Timing Analyzer. The Timing Analyzer window opens automatically and shows the results of the analysis.

Timing Analysis Source is available only if a timing SNF exists for the current project.

The Timing Analysis Source, Timing Analysis Destination, Timing Analysis Cutoff, and Clear All Timing Analysis Tags commands are used only for post-compilation timing analysis. To enter timing assignments that affect compilation, use the Timing Requirements and Global Project Timing Requirements commands (Assign menu).

See also:

Clearing Timing Analysis Tags

Creating a Timing Simulator Netlist File

Running a Timing Analysis

Tagging Timing Analysis Cutoff Nodes

Tagging Timing Analysis Source & Destination Nodes

Recommended reading:

AB94 (Solutions to Design Timing Problems for Altera EPLDs)

AB143 (Understanding FLEX 8000 Timing)

AB144 (Understanding MAX 9000 Timing)

AN42 (Metastability in Altera Devices)


Timing Analysis Cutoff Command (editor applications)
Timing Analysis Cutoff Command (Utilities Menu)

Shortcuts

Tags or untags a single selected node in the Text Editor or one or more selected nodes in the Graphic or Waveform Editor in the current file as a cutoff node for timing analysis.

In the Text Editor, you select a single node name before choosing Timing Analysis Cutoff. In the Waveform Editor, you can select one or more nodes and groups; in the Graphic Editor, you can select nodes, buses, and/or symbols; in the Floorplan Editor, you can select nodes that have been assigned to logic cells, I/O cells, and pins. You can also tag nodes as timing sources with the Timing Analyzer’s own Timing Analysis Cutoff command, which opens a dialog box that shows all cutoff nodes in the project.

The Timing Analyzer analyzes the project’s timing characteristics on the basis of the Time Restrictions command and the cutoff, source and destination nodes selected with Timing Analysis Cutoff, Timing Analysis Source, and Timing Analysis Destination. If you do not tag source and destination nodes, default timing tagging is used.

After tagging cutoff, source, and destination nodes, you can choose Analyze Timing (Utilities menu) to run the Timing Analyzer. The Timing Analyzer window opens automatically and shows the results of the analysis.

Timing Analysis Cutoff is available only if a timing SNF exists for the current project.

The Timing Analysis Source, Timing Analysis Destination, Timing Analysis Cutoff, and Clear All Timing Analysis Tags commands are used only for post-compilation timing analysis. To enter timing assignments that affect compilation, use the Timing Requirements and Global Project Timing Requirements commands (Assign menu).

See also:

Clearing Timing Analysis Tags

Creating a Timing Simulator Netlist File

Running a Timing Analysis

Tagging Timing Analysis Cutoff Nodes

Tagging Timing Analysis Source & Destination Nodes

Recommended reading:

AB94 (Solutions to Design Timing Problems for Altera EPLDs)

AB143 (Understanding FLEX 8000 Timing)

AB144 (Understanding MAX 9000 Timing)

AN42 (Metastability in Altera Devices)


Clear All Timing Analysis Tags Command (editor applications)
Clear All Timing Analysis Tags Command (Utilities Menu)

Clears all source, destination, and cutoff tags specified with the Timing Analysis Source, Timing Analysis Destination, and Timing Analysis Cutoff commands, and returns to default timing tagging.

All source, destination, and cutoff nodes are displayed in the Timing Analyzer’s Timing Analysis Source, Timing Analysis Destination, and Timing Analysis Cutoff dialog boxes (Node menu). Source and destination nodes are also displayed in the Timing Analyzer’s Delay Matrix or Setup/Hold Matrix.

The Timing Source, Timing Destination, Timing Cutoff, and Clear All Timing Tags commands are used only for post-compilation timing analysis. To enter timing assignments that affect compilation, use the Timing Requirements and Global Project Timing Requirements commands (Assign menu).

See also:

Clearing Timing Analysis Tags

Running a Timing Analysis

Tagging Timing Analysis Cutoff Nodes

Tagging Timing Analysis Source & Destination Nodes

Recommended reading:

AB94 (Solutions to Design Timing Problems for Altera EPLDs)

AB143 (Understanding FLEX 8000 Timing)

AB144 (Understanding MAX 9000 Timing)

AN42 (Metastability in Altera Devices)


----------------------BEGINNING OF NON-TRANSLATED TEXT--------------------------------------------------

This file contains the panel for each application's toolbar. The panel is duplicated for each application; the only thing that differs in the panels is the segmented hypergraphic of the toolbar for that application and the text that is substituted for the we, WED, and WED.

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Toolbar (Waveform Editor)
Toolbar

Displays buttons and drop-down list boxes that allow you to execute commands quickly.

The toolbar is displayed below the menu bar in the MAX+PLUS II window. You can choose a toolbar button or select an option from a toolbar drop-down list box as a shortcut to enter commands or get context-sensitive help in the Waveform Editor. All commands that you can enter from the toolbar are also available with menu commands or mouse/keyboard shortcuts.

The tools available in the toolbar vary according to the current MAX+PLUS II application. Tools that are available in multiple applications are grouped together.

In some MAX+PLUS II applications, the tool palette on the left side of the window also contains buttons that provide shortcuts for menu commands.

Click Button 1 on any item in the toolbar for information on that item:

If you point to an item in the toolbar when the status bar is turned on, the status bar displays a brief description of the function of that item.

You can turn the toolbar on and off with Preferences (Options menu).

In some MAX+PLUS II applications, not all toolbar buttons and list boxes on the standard toolbar are visible if you run MAX+PLUS II with your computer screen in VGA mode: some items are "beyond" the right-hand edge of the screen. In higher-resolution screen modes (e.g., SuperVGA), all toolbar items are visible.

MAX+PLUS II provides an alternate toolbar, which contains a useful subset of toolbar buttons, that can be used on VGA screens. For information on switching between the standard and alternate toolbars, go to Setting MAX+PLUS II Preferences.

See also:

Getting Context-Sensitive Help

Shortcuts

Setting MAX+PLUS II Preferences


----------------------BEGINNING OF NON-TRANSLATED TEXT--------------------------------------------------

The following panel is used for the popup that appears when you are in Help and click on a dimmed button in the segmented hypergraphic of the toolbar. The panel that appears if you click on a dimmed button in MAX+PLUS II with the context-sensitive Help pointer is similar, but is not duplicated. That panel is stored in the file kefixits.mac/rtf.

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Unavailable Toolbar Button (Waveform Editor)
Unavailable Toolbar Button

This button is not available (and is always dimmed) on the Waveform Editor toolbar.


----------------------BEGINNING OF NON-TRANSLATED TEXT--------------------------------------------------

This file contains the panel for each application's toolbar. The panel is duplicated for each application; the only thing that differs in the panels is the segmented hypergraphic of the toolbar for that application and the text that is substituted for the te, TED, and TED.

----------------------END OF NON-TRANSLATED TEXT--------------------------------------------------


Toolbar (Text Editor)
Toolbar

Displays buttons and drop-down list boxes that allow you to execute commands quickly.

The toolbar is displayed below the menu bar in the MAX+PLUS II window. You can choose a toolbar button or select an option from a toolbar drop-down list box as a shortcut to enter commands or get context-sensitive help in the Text Editor. All commands that you can enter from the toolbar are also available with menu commands or mouse/keyboard shortcuts.

The tools available in the toolbar vary according to the current MAX+PLUS II application. Tools that are available in multiple applications are grouped together.

In some MAX+PLUS II applications, the tool palette on the left side of the window also contains buttons that provide shortcuts for menu commands.

Click Button 1 on any item in the toolbar for information on that item:

If you point to an item in the toolbar when the status bar is turned on, the status bar displays a brief description of the function of that item.

You can turn the toolbar on and off with Preferences (Options menu).

In some MAX+PLUS II applications, not all toolbar buttons and list boxes on the standard toolbar are visible if you run MAX+PLUS II with your computer screen in VGA mode: some items are "beyond" the right-hand edge of the screen. In higher-resolution screen modes (e.g., SuperVGA), all toolbar items are visible.

MAX+PLUS II provides an alternate toolbar, which contains a useful subset of toolbar buttons, that can be used on VGA screens. For information on switching between the standard and alternate toolbars, go to Setting MAX+PLUS II Preferences.

See also:

Getting Context-Sensitive Help

Shortcuts

Setting MAX+PLUS II Preferences


----------------------BEGINNING OF NON-TRANSLATED TEXT--------------------------------------------------

The following panel is used for the popup that appears when you are in Help and click on a dimmed button in the segmented hypergraphic of the toolbar. The panel that appears if you click on a dimmed button in MAX+PLUS II with the context-sensitive Help pointer is similar, but is not duplicated. That panel is stored in the file kefixits.mac/rtf.

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Unavailable Toolbar Button (Text Editor)
Unavailable Toolbar Button

This button is not available (and is always dimmed) on the Text Editor toolbar.


----------------------BEGINNING OF NON-TRANSLATED TEXT--------------------------------------------------

This file contains the panel for each application's toolbar. The panel is duplicated for each application; the only thing that differs in the panels is the segmented hypergraphic of the toolbar for that application and the text that is substituted for the ta, TAN, and TAN.

----------------------END OF NON-TRANSLATED TEXT--------------------------------------------------


Toolbar (Timing Analyzer)
Toolbar

Displays buttons and drop-down list boxes that allow you to execute commands quickly.

The toolbar is displayed below the menu bar in the MAX+PLUS II window. You can choose a toolbar button or select an option from a toolbar drop-down list box as a shortcut to enter commands or get context-sensitive help in the Timing Analyzer. All commands that you can enter from the toolbar are also available with menu commands or mouse/keyboard shortcuts.

The tools available in the toolbar vary according to the current MAX+PLUS II application. Tools that are available in multiple applications are grouped together.

In some MAX+PLUS II applications, the tool palette on the left side of the window also contains buttons that provide shortcuts for menu commands.

Click Button 1 on any item in the toolbar for information on that item:

If you point to an item in the toolbar when the status bar is turned on, the status bar displays a brief description of the function of that item.

You can turn the toolbar on and off with Preferences (Options menu).

In some MAX+PLUS II applications, not all toolbar buttons and list boxes on the standard toolbar are visible if you run MAX+PLUS II with your computer screen in VGA mode: some items are "beyond" the right-hand edge of the screen. In higher-resolution screen modes (e.g., SuperVGA), all toolbar items are visible.

MAX+PLUS II provides an alternate toolbar, which contains a useful subset of toolbar buttons, that can be used on VGA screens. For information on switching between the standard and alternate toolbars, go to Setting MAX+PLUS II Preferences.

See also:

Getting Context-Sensitive Help

Shortcuts

Setting MAX+PLUS II Preferences


----------------------BEGINNING OF NON-TRANSLATED TEXT--------------------------------------------------

The following panel is used for the popup that appears when you are in Help and click on a dimmed button in the segmented hypergraphic of the toolbar. The panel that appears if you click on a dimmed button in MAX+PLUS II with the context-sensitive Help pointer is similar, but is not duplicated. That panel is stored in the file kefixits.mac/rtf.

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Unavailable Toolbar Button (Timing Analyzer)
Unavailable Toolbar Button

This button is not available (and is always dimmed) on the Timing Analyzer toolbar.


----------------------BEGINNING OF NON-TRANSLATED TEXT--------------------------------------------------

This file contains the panel for each application's toolbar. The panel is duplicated for each application; the only thing that differs in the panels is the segmented hypergraphic of the toolbar for that application and the text that is substituted for the su, MAX, and MAX.

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Toolbar (MAX+PLUS II Manager)
Toolbar

Displays buttons and drop-down list boxes that allow you to execute commands quickly.

The toolbar is displayed below the menu bar in the MAX+PLUS II window. You can choose a toolbar button or select an option from a toolbar drop-down list box as a shortcut to enter commands or get context-sensitive help in the MAX+PLUS II Manager. All commands that you can enter from the toolbar are also available with menu commands or mouse/keyboard shortcuts.

The tools available in the toolbar vary according to the current MAX+PLUS II application. Tools that are available in multiple applications are grouped together.

In some MAX+PLUS II applications, the tool palette on the left side of the window also contains buttons that provide shortcuts for menu commands.

Click Button 1 on any item in the toolbar for information on that item:

If you point to an item in the toolbar when the status bar is turned on, the status bar displays a brief description of the function of that item.

You can turn the toolbar on and off with Preferences (Options menu).

In some MAX+PLUS II applications, not all toolbar buttons and list boxes on the standard toolbar are visible if you run MAX+PLUS II with your computer screen in VGA mode: some items are "beyond" the right-hand edge of the screen. In higher-resolution screen modes (e.g., SuperVGA), all toolbar items are visible.

MAX+PLUS II provides an alternate toolbar, which contains a useful subset of toolbar buttons, that can be used on VGA screens. For information on switching between the standard and alternate toolbars, go to Setting MAX+PLUS II Preferences.

See also:

Getting Context-Sensitive Help

Shortcuts

Setting MAX+PLUS II Preferences


----------------------BEGINNING OF NON-TRANSLATED TEXT--------------------------------------------------

The following panel is used for the popup that appears when you are in Help and click on a dimmed button in the segmented hypergraphic of the toolbar. The panel that appears if you click on a dimmed button in MAX+PLUS II with the context-sensitive Help pointer is similar, but is not duplicated. That panel is stored in the file kefixits.mac/rtf.

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Unavailable Toolbar Button (MAX+PLUS II Manager)
Unavailable Toolbar Button

This button is not available (and is always dimmed) on the MAX+PLUS II Manager toolbar.


----------------------BEGINNING OF NON-TRANSLATED TEXT--------------------------------------------------

This file contains the panel for each application's toolbar. The panel is duplicated for each application; the only thing that differs in the panels is the segmented hypergraphic of the toolbar for that application and the text that is substituted for the si, SIM, and SIM.

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Toolbar (Simulator)
Toolbar

Displays buttons and drop-down list boxes that allow you to execute commands quickly.

The toolbar is displayed below the menu bar in the MAX+PLUS II window. You can choose a toolbar button or select an option from a toolbar drop-down list box as a shortcut to enter commands or get context-sensitive help in the Simulator. All commands that you can enter from the toolbar are also available with menu commands or mouse/keyboard shortcuts.

The tools available in the toolbar vary according to the current MAX+PLUS II application. Tools that are available in multiple applications are grouped together.

In some MAX+PLUS II applications, the tool palette on the left side of the window also contains buttons that provide shortcuts for menu commands.

Click Button 1 on any item in the toolbar for information on that item:

If you point to an item in the toolbar when the status bar is turned on, the status bar displays a brief description of the function of that item.

You can turn the toolbar on and off with Preferences (Options menu).

In some MAX+PLUS II applications, not all toolbar buttons and list boxes on the standard toolbar are visible if you run MAX+PLUS II with your computer screen in VGA mode: some items are "beyond" the right-hand edge of the screen. In higher-resolution screen modes (e.g., SuperVGA), all toolbar items are visible.

MAX+PLUS II provides an alternate toolbar, which contains a useful subset of toolbar buttons, that can be used on VGA screens. For information on switching between the standard and alternate toolbars, go to Setting MAX+PLUS II Preferences.

See also:

Getting Context-Sensitive Help

Shortcuts

Setting MAX+PLUS II Preferences


----------------------BEGINNING OF NON-TRANSLATED TEXT--------------------------------------------------

The following panel is used for the popup that appears when you are in Help and click on a dimmed button in the segmented hypergraphic of the toolbar. The panel that appears if you click on a dimmed button in MAX+PLUS II with the context-sensitive Help pointer is similar, but is not duplicated. That panel is stored in the file kefixits.mac/rtf.

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Unavailable Toolbar Button (Simulator)
Unavailable Toolbar Button

This button is not available (and is always dimmed) on the Simulator toolbar.


----------------------BEGINNING OF NON-TRANSLATED TEXT--------------------------------------------------

This file contains the panel for each application's toolbar. The panel is duplicated for each application; the only thing that differs in the panels is the segmented hypergraphic of the toolbar for that application and the text that is substituted for the pr, PGM, and PGM.

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Toolbar (Programmer)
Toolbar

Displays buttons and drop-down list boxes that allow you to execute commands quickly.

The toolbar is displayed below the menu bar in the MAX+PLUS II window. You can choose a toolbar button or select an option from a toolbar drop-down list box as a shortcut to enter commands or get context-sensitive help in the Programmer. All commands that you can enter from the toolbar are also available with menu commands or mouse/keyboard shortcuts.

The tools available in the toolbar vary according to the current MAX+PLUS II application. Tools that are available in multiple applications are grouped together.

In some MAX+PLUS II applications, the tool palette on the left side of the window also contains buttons that provide shortcuts for menu commands.

Click Button 1 on any item in the toolbar for information on that item:

If you point to an item in the toolbar when the status bar is turned on, the status bar displays a brief description of the function of that item.

You can turn the toolbar on and off with Preferences (Options menu).

In some MAX+PLUS II applications, not all toolbar buttons and list boxes on the standard toolbar are visible if you run MAX+PLUS II with your computer screen in VGA mode: some items are "beyond" the right-hand edge of the screen. In higher-resolution screen modes (e.g., SuperVGA), all toolbar items are visible.

MAX+PLUS II provides an alternate toolbar, which contains a useful subset of toolbar buttons, that can be used on VGA screens. For information on switching between the standard and alternate toolbars, go to Setting MAX+PLUS II Preferences.

See also:

Getting Context-Sensitive Help

Shortcuts

Setting MAX+PLUS II Preferences


----------------------BEGINNING OF NON-TRANSLATED TEXT--------------------------------------------------

The following panel is used for the popup that appears when you are in Help and click on a dimmed button in the segmented hypergraphic of the toolbar. The panel that appears if you click on a dimmed button in MAX+PLUS II with the context-sensitive Help pointer is similar, but is not duplicated. That panel is stored in the file kefixits.mac/rtf.

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Unavailable Toolbar Button (Programmer)
Unavailable Toolbar Button

This button is not available (and is always dimmed) on the Programmer toolbar.


----------------------BEGINNING OF NON-TRANSLATED TEXT--------------------------------------------------

This file contains the panel for each application's toolbar. The panel is duplicated for each application; the only thing that differs in the panels is the segmented hypergraphic of the toolbar for that application and the text that is substituted for the mp, MSG, and MSG.

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Toolbar (Message Processor)
Toolbar

Displays buttons and drop-down list boxes that allow you to execute commands quickly.

The toolbar is displayed below the menu bar in the MAX+PLUS II window. You can choose a toolbar button or select an option from a toolbar drop-down list box as a shortcut to enter commands or get context-sensitive help in the Message Processor. All commands that you can enter from the toolbar are also available with menu commands or mouse/keyboard shortcuts.

The tools available in the toolbar vary according to the current MAX+PLUS II application. Tools that are available in multiple applications are grouped together.

In some MAX+PLUS II applications, the tool palette on the left side of the window also contains buttons that provide shortcuts for menu commands.

Click Button 1 on any item in the toolbar for information on that item:

If you point to an item in the toolbar when the status bar is turned on, the status bar displays a brief description of the function of that item.

You can turn the toolbar on and off with Preferences (Options menu).

In some MAX+PLUS II applications, not all toolbar buttons and list boxes on the standard toolbar are visible if you run MAX+PLUS II with your computer screen in VGA mode: some items are "beyond" the right-hand edge of the screen. In higher-resolution screen modes (e.g., SuperVGA), all toolbar items are visible.

MAX+PLUS II provides an alternate toolbar, which contains a useful subset of toolbar buttons, that can be used on VGA screens. For information on switching between the standard and alternate toolbars, go to Setting MAX+PLUS II Preferences.

See also:

Getting Context-Sensitive Help

Shortcuts

Setting MAX+PLUS II Preferences


----------------------BEGINNING OF NON-TRANSLATED TEXT--------------------------------------------------

The following panel is used for the popup that appears when you are in Help and click on a dimmed button in the segmented hypergraphic of the toolbar. The panel that appears if you click on a dimmed button in MAX+PLUS II with the context-sensitive Help pointer is similar, but is not duplicated. That panel is stored in the file kefixits.mac/rtf.

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Unavailable Toolbar Button (Message Processor)
Unavailable Toolbar Button

This button is not available (and is always dimmed) on the Message Processor toolbar.


----------------------BEGINNING OF NON-TRANSLATED TEXT--------------------------------------------------

This file contains the panel for each application's toolbar. The panel is duplicated for each application; the only thing that differs in the panels is the segmented hypergraphic of the toolbar for that application and the text that is substituted for the hr, HRW, and HRW.

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Toolbar (Hierarchy Display)
Toolbar

Displays buttons and drop-down list boxes that allow you to execute commands quickly.

The toolbar is displayed below the menu bar in the MAX+PLUS II window. You can choose a toolbar button or select an option from a toolbar drop-down list box as a shortcut to enter commands or get context-sensitive help in the Hierarchy Display. All commands that you can enter from the toolbar are also available with menu commands or mouse/keyboard shortcuts.

The tools available in the toolbar vary according to the current MAX+PLUS II application. Tools that are available in multiple applications are grouped together.

In some MAX+PLUS II applications, the tool palette on the left side of the window also contains buttons that provide shortcuts for menu commands.

Click Button 1 on any item in the toolbar for information on that item:

If you point to an item in the toolbar when the status bar is turned on, the status bar displays a brief description of the function of that item.

You can turn the toolbar on and off with Preferences (Options menu).

In some MAX+PLUS II applications, not all toolbar buttons and list boxes on the standard toolbar are visible if you run MAX+PLUS II with your computer screen in VGA mode: some items are "beyond" the right-hand edge of the screen. In higher-resolution screen modes (e.g., SuperVGA), all toolbar items are visible.

MAX+PLUS II provides an alternate toolbar, which contains a useful subset of toolbar buttons, that can be used on VGA screens. For information on switching between the standard and alternate toolbars, go to Setting MAX+PLUS II Preferences.

See also:

Getting Context-Sensitive Help

Shortcuts

Setting MAX+PLUS II Preferences


----------------------BEGINNING OF NON-TRANSLATED TEXT--------------------------------------------------

The following panel is used for the popup that appears when you are in Help and click on a dimmed button in the segmented hypergraphic of the toolbar. The panel that appears if you click on a dimmed button in MAX+PLUS II with the context-sensitive Help pointer is similar, but is not duplicated. That panel is stored in the file kefixits.mac/rtf.

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Unavailable Toolbar Button (Hierarchy Display)
Unavailable Toolbar Button

This button is not available (and is always dimmed) on the Hierarchy Display toolbar.


----------------------BEGINNING OF NON-TRANSLATED TEXT--------------------------------------------------

This file contains the panel for each application's toolbar. The panel is duplicated for each application; the only thing that differs in the panels is the segmented hypergraphic of the toolbar for that application and the text that is substituted for the ge, GED, and GED.

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Toolbar (Graphic & Symbol Editors)
Toolbar

Displays buttons and drop-down list boxes that allow you to execute commands quickly.

The toolbar is displayed below the menu bar in the MAX+PLUS II window. You can choose a toolbar button or select an option from a toolbar drop-down list box as a shortcut to enter commands or get context-sensitive help in the Graphic & Symbol Editors. All commands that you can enter from the toolbar are also available with menu commands or mouse/keyboard shortcuts.

The tools available in the toolbar vary according to the current MAX+PLUS II application. Tools that are available in multiple applications are grouped together.

In some MAX+PLUS II applications, the tool palette on the left side of the window also contains buttons that provide shortcuts for menu commands.

Click Button 1 on any item in the toolbar for information on that item:

If you point to an item in the toolbar when the status bar is turned on, the status bar displays a brief description of the function of that item.

You can turn the toolbar on and off with Preferences (Options menu).

In some MAX+PLUS II applications, not all toolbar buttons and list boxes on the standard toolbar are visible if you run MAX+PLUS II with your computer screen in VGA mode: some items are "beyond" the right-hand edge of the screen. In higher-resolution screen modes (e.g., SuperVGA), all toolbar items are visible.

MAX+PLUS II provides an alternate toolbar, which contains a useful subset of toolbar buttons, that can be used on VGA screens. For information on switching between the standard and alternate toolbars, go to Setting MAX+PLUS II Preferences.

See also:

Getting Context-Sensitive Help

Shortcuts

Setting MAX+PLUS II Preferences


----------------------BEGINNING OF NON-TRANSLATED TEXT--------------------------------------------------

The following panel is used for the popup that appears when you are in Help and click on a dimmed button in the segmented hypergraphic of the toolbar. The panel that appears if you click on a dimmed button in MAX+PLUS II with the context-sensitive Help pointer is similar, but is not duplicated. That panel is stored in the file kefixits.mac/rtf.

----------------------END OF NON-TRANSLATED TEXT--------------------------------------------------


Unavailable Toolbar Button (Graphic & Symbol Editors)
Unavailable Toolbar Button

This button is not available (and is always dimmed) on the Graphic & Symbol Editors toolbar.


----------------------BEGINNING OF NON-TRANSLATED TEXT--------------------------------------------------

This file contains the panel for each application's toolbar. The panel is duplicated for each application; the only thing that differs in the panels is the segmented hypergraphic of the toolbar for that application and the text that is substituted for the fe, FED, and FED.

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Toolbar (Floorplan Editor)
Toolbar

Displays buttons and drop-down list boxes that allow you to execute commands quickly.

The toolbar is displayed below the menu bar in the MAX+PLUS II window. You can choose a toolbar button or select an option from a toolbar drop-down list box as a shortcut to enter commands or get context-sensitive help in the Floorplan Editor. All commands that you can enter from the toolbar are also available with menu commands or mouse/keyboard shortcuts.

The tools available in the toolbar vary according to the current MAX+PLUS II application. Tools that are available in multiple applications are grouped together.

In some MAX+PLUS II applications, the tool palette on the left side of the window also contains buttons that provide shortcuts for menu commands.

Click Button 1 on any item in the toolbar for information on that item:

If you point to an item in the toolbar when the status bar is turned on, the status bar displays a brief description of the function of that item.

You can turn the toolbar on and off with Preferences (Options menu).

In some MAX+PLUS II applications, not all toolbar buttons and list boxes on the standard toolbar are visible if you run MAX+PLUS II with your computer screen in VGA mode: some items are "beyond" the right-hand edge of the screen. In higher-resolution screen modes (e.g., SuperVGA), all toolbar items are visible.

MAX+PLUS II provides an alternate toolbar, which contains a useful subset of toolbar buttons, that can be used on VGA screens. For information on switching between the standard and alternate toolbars, go to Setting MAX+PLUS II Preferences.

See also:

Getting Context-Sensitive Help

Shortcuts

Setting MAX+PLUS II Preferences


----------------------BEGINNING OF NON-TRANSLATED TEXT--------------------------------------------------

The following panel is used for the popup that appears when you are in Help and click on a dimmed button in the segmented hypergraphic of the toolbar. The panel that appears if you click on a dimmed button in MAX+PLUS II with the context-sensitive Help pointer is similar, but is not duplicated. That panel is stored in the file kefixits.mac/rtf.

----------------------END OF NON-TRANSLATED TEXT--------------------------------------------------


Unavailable Toolbar Button (Floorplan Editor)
Unavailable Toolbar Button

This button is not available (and is always dimmed) on the Floorplan Editor toolbar.


----------------------BEGINNING OF NON-TRANSLATED TEXT--------------------------------------------------

This file contains the panel for each application's toolbar. The panel is duplicated for each application; the only thing that differs in the panels is the segmented hypergraphic of the toolbar for that application and the text that is substituted for the co, CMP, and CMP.

----------------------END OF NON-TRANSLATED TEXT--------------------------------------------------


Toolbar (Compiler)
Toolbar

Displays buttons and drop-down list boxes that allow you to execute commands quickly.

The toolbar is displayed below the menu bar in the MAX+PLUS II window. You can choose a toolbar button or select an option from a toolbar drop-down list box as a shortcut to enter commands or get context-sensitive help in the Compiler. All commands that you can enter from the toolbar are also available with menu commands or mouse/keyboard shortcuts.

The tools available in the toolbar vary according to the current MAX+PLUS II application. Tools that are available in multiple applications are grouped together.

In some MAX+PLUS II applications, the tool palette on the left side of the window also contains buttons that provide shortcuts for menu commands.

Click Button 1 on any item in the toolbar for information on that item:

If you point to an item in the toolbar when the status bar is turned on, the status bar displays a brief description of the function of that item.

You can turn the toolbar on and off with Preferences (Options menu).

In some MAX+PLUS II applications, not all toolbar buttons and list boxes on the standard toolbar are visible if you run MAX+PLUS II with your computer screen in VGA mode: some items are "beyond" the right-hand edge of the screen. In higher-resolution screen modes (e.g., SuperVGA), all toolbar items are visible.

MAX+PLUS II provides an alternate toolbar, which contains a useful subset of toolbar buttons, that can be used on VGA screens. For information on switching between the standard and alternate toolbars, go to Setting MAX+PLUS II Preferences.

See also:

Getting Context-Sensitive Help

Shortcuts

Setting MAX+PLUS II Preferences


----------------------BEGINNING OF NON-TRANSLATED TEXT--------------------------------------------------

The following panel is used for the popup that appears when you are in Help and click on a dimmed button in the segmented hypergraphic of the toolbar. The panel that appears if you click on a dimmed button in MAX+PLUS II with the context-sensitive Help pointer is similar, but is not duplicated. That panel is stored in the file kefixits.mac/rtf.

----------------------END OF NON-TRANSLATED TEXT--------------------------------------------------


Unavailable Toolbar Button (Compiler)
Unavailable Toolbar Button

This button is not available (and is always dimmed) on the Compiler toolbar.


-----BEGINNING OF NON-TRANSLATED TEXT-----

These are messages for the Design Doctor message file DRCMSGS.MSG.

-----END OF NON-TRANSLATED TEXT-----


Can’t find master Reset pin -- [using pin <name>]
Can’t find master Reset pin [-- using pin <name>]

CAUSE:	Within your project, there is no single input pin that resets a majority of flipflops either directly or through some enabling logic. If a pin is assigned as a master Reset, the specified pin is a factor in the logic that enables the majority of the flipflops. This configuration is unreliable there is no guarantee that all flipflops will be initialized, all counters will be cleared, or all state machines will be forced to a known state.

ACTION:	If your project does not have a master Reset, consider adding one. If a master Reset pin exists, consider simplifying the logic that enables the signal at the flipflop’s Preset input.

See also:

Master Reset Guidelines

MAX+PLUS II Messages

Message Format

Project Reliability Guidelines


Clock signal <net ID number> is driven by state machine <name>

CAUSE:	A state machine is driving the Clock signal. This configuration is unreliable because logic synthesis may replace the state machine with combinatorial logic that depends on several flipflops. If the flipflops are not synchronized, glitches may occur.

ACTION:	Use a global Clock wherever possible. Insert a flipflop that has a Clock Enable input (i.e., DFFE, JKFFE, SRFFE, or TFFE) between the state machine logic and the specified Clock signal. Feed the driving logic into the flipflop’s Clock Enable input and use the fliplop’s output to drive the Clock signal. For an example of good design practice, see Multi-Clock Network Example.

See also:

Clock Configuration Guidelines

MAX+PLUS II Messages

Message Format

Project Reliability Guidelines


Complex combinatorial logic drives <text> node (ID <net ID number>) -- <text> etc
Complex combinatorial logic drives <text> node (ID <net ID number>) -- <text> should be driven by a pin or a single logic primitive

CAUSE:	Complex combinatorial logic is driving the Clock, Clear, or Preset signal. A control signal of this type should either be generated by a single input pin, generated by a single input pin that is enabled by a single logic primitive function of other input pins.

ACTION:	Replace the driving logic with a flipflop that enables an input pin. If the specified signal is a Clock signal, replace the flipflop that is being driven by the network with a flipflop that has a Clock Enable input (i.e., DFFE, JKFFE, SRFFE, or TFFE). Feed the driving logic into the flipflop’s Clock Enable input and drive the flipflop’s Clock signal with a global Clock. For examples of good design practice, see Gated Clock Examples, Multi-Level Clock Example, and Preset & Clear Configuration Examples.

See also:

Clock Configuration Guidelines

MAX+PLUS II Messages

Message Format

Preset & Clear Configuration Guidelines

Project Reliability Guidelines


Design Doctor has given the project a clean bill of health for the <name> Rules set
Design Doctor has given the project a clean bill of health based on the <name> Rules set

CAUSE:	The Design Doctor has finished analyzing the project with the specified set of rules and found no violations of those rules.

ACTION:	No action is required.

See also:

MAX+PLUS II Messages

Message Format

Project Reliability Guidelines


Design Doctor has issued <number> warnings
Design Doctor has issued <number> warning messages with <name> Rules [during project compilation]

CAUSE:	The Design Doctor has finished analyzing the project based on the specified set of rules and has issued the specified number of warning messages.

ACTION:	You may wish to modify your project to eliminate any warning messages. See Project Reliability Guidelines for help with creating a reliable project. Use the Message Processor to locate the source(s) of the warning messages. Otherwise, no action is required.

See also:

Locating a Source of a Message

MAX+PLUS II Messages

Message Format


Design Doctor has not examined the project

CAUSE:	The project has not yet been analyzed by the Design Doctor.

ACTION:	If you wish to analyze your project with the Design Doctor, choose the Start button in the Compiler window to begin compilation.

See also:

MAX+PLUS II Messages

Message Format

Project Reliability Guidelines


Design Doctor is currently examining the project

CAUSE:	The Design Doctor analysis and project compilation are currently in progress.

ACTION:	Choose OK and wait for the Design Doctor analysis and compilation to finish.

See also:

MAX+PLUS II Messages

Message Format

Project Reliability Guidelines


Expander flipflop detected at primitive <net ID number>

CAUSE:	An expander flipflop such as the Altera-provided EXPDFF macrofunction exists in your project. You should only use these expander flipflops after all dedicated flipflop and latch resources in the device (i.e., logic cells and peripheral registers) have been used.

ACTION:	If dedicated flipflop and latch resources are available in the device, replace the expander flipflop with a DFF primitive. Otherwise, no action is required.

See also:

Expander Network Guidelines

MAX+PLUS II Messages

Message Format

Project Reliability Guidelines


Expander latch detected at primitive <net ID number>

CAUSE:	An expander latch such as EXPLATCH, NANDLTCH, or NORLTCH exists in your project. You should only use these macrofunctions after all dedicated flipflop and latch resources in the device (i.e., logic cells and peripheral registers) have been used.

ACTION:	If dedicated flipflop and latch resources are available in the device, replace the expander latch with a LATCH primitive. Otherwise, no action is required.

See also:

Expander Network Guidelines

MAX+PLUS II Messages

Message Format

Project Reliability Guidelines


Flipflop(s) and logic drive <text> node (ID <net ID number>)

CAUSE:	The Clock, Clear, or Preset signal is driven by a function of one or more flipflop(s) and input pin(s). This multi-Clock network configuration is unreliable and glitches may occur because the flipflops do not change states simultaneously.

ACTION:	Use a global Clock wherever possible. If the specified signal is a Clock signal, replace the flipflop that is being driven by the network with a flipflop that has a Clock Enable input (i.e., DFFE, JKFFE, SRFFE, or TFFE). Feed the driving logic into the flipflop’s Clock Enable input and drive the flipflop’s Clock signal with a global Clock. If the specified signal is a Clear or Preset signal, insert a flipflop between the driving logic and the specified Clear or Preset signal. Feed the driving logic into the data input of a flipflop and drive the Clear or Preset signal with the flipflop’s output. For an example of good design practice, see Multi-Clock Network Example.

See also:

Clock Configuration Guidelines

MAX+PLUS II Messages

Message Format

Project Reliability Guidelines


Flipflop <net ID number> receives data that is synchronized by another Clock at flipflop <net ID number>

CAUSE:	The logic driving the data input of flipflop is a function of one or more flipflops that are synchronized by a different Clock signal. This multi-Clock network configuration is unreliable because the two Clock signals may be independent of each other, producing setup time violations.

ACTION:	Use a global Clock wherever possible. Otherwise, insert another flipflop between the driving logic and the specified flipflop. Synchronize this new flipflop with the same Clock signal used for the flipflop being driven. For an example of good design practice, see Multi-Clock Network Example.

See also:

Clock Configuration Guidelines

MAX+PLUS II Messages

Message Format

Project Reliability Guidelines


Input pin <name> asynchronously drives multiple flipflops that are synchronized to Clock <net ID number>
Input pin <name> asynchronously drives multiple flipflops that are synchronized to Clock <net ID number> -- synchronize the input to Clock <net ID number>

CAUSE:	The signal from the specified input pin fans out to two or more flipflops that are synchronized by the specified Clock. This asynchronous input configuration is unreliable since the input may not always meet the setup and hold time requirements of the flipflops. This message may occur for TTL macrofunctions from the MAX+PLUS II Macrofunction Library.

ACTION:	Ensure that the input signal is synchronized to the Clock either external or internal to the device. To synchronize the input signal to the internal device Clock, insert a flipflop between the input pin and the network of flipflops. Synchronize the new flipflop with the specified Clock signal. For examples of good design practice, see Asynchronous Input Examples.

See also:

Asynchronous Input Guidelines

Clock Configuration Guidelines

MAX+PLUS II Messages

Message Format

Project Reliability Guidelines


[Inverting] delay chain detected starting at primitive <net ID number> feeds primitive <net ID number>

CAUSE:	A delay chain exists in your project. This logic configuration is unreliable because the structure relies on the internal delay times of the device to modify the setup and hold time requirements of a flipflop or creates an asynchronous pulse generator.

ACTION:	Remove the delay chain. You can also add logic to create synchronous pulse generators or to synchronize inputs to a flipflop with a global Clock to ensure that setup time requirements are met. For examples of good design practice, see Delay Chain Examples.

See also:

Delay Chain Guidelines

MAX+PLUS II Messages

Message Format

Project Reliability Guidelines


Logic for Clear signal <net ID number> should enable master Reset
Logic that drives Clear signal <net ID number> should enable master Reset pin <pin name> -- not pin <name>

CAUSE:	The logic that drives the specified Clear signal is an enabling gate for another input pin. However, the pin that is being enabled is not the master Reset pin for the project.

ACTION:	Modify the logic so that the specified input pin is part of the enabling logic for the master Reset pin, or add the master Reset pin to the logic for the Reset signal.

See also:

Master Reset Guidelines

MAX+PLUS II Messages

Message Format

Preset & Clear Configuration Guidelines

Project Reliability Guidelines


Logic for primitive <net ID number> contains a static <1 or 0> hazard
Logic that drives primitive <net ID number> contains a static <1 or 0> hazard when <text> and primitive <net ID number> changes -- hazard found <text> logic synthesis

[Conditions -- <text>]

CAUSE:	A static hazard exists for the specified primitive when the specified conditions for the node(s) and primitive occur. If several nodes are involved in the hazard condition, the node names and logic levels are given in a list of conditions that follows the main message text. This hazard may have been found in the logic before, after, or both before and after logic synthesis.

ACTION:	Add logic that covers the reported condition. For example, if there is a static 1 hazard when B=0, C=1, and D changes, then a term of !B * C added to the equation will cover the hazard. However, such additional redundant logic will be removed by logic synthesis unless the Minimization logic option is turned off.

See also:

Assigning a Logic Option

MAX+PLUS II Messages

Message Format

Project Reliability Guidelines

Static Hazard Guidelines


Logic that drives primitive <name> is too complex to analyze for static hazards
Logic that drives primitive <net ID number> is too complex to analyze for static hazards

CAUSE:	The logic that drives the specified primitive is too complex for the  Design Doctor to analyze. The logic may have too many nested gates, inputs, or sum-of-products expressions. This message may also occur if available memory is insufficient to continue the Design Doctor’s static hazard analysis.

ACTION:	Simplify the logic that drives the specified primitive, i.e., try to reduce the number of nested gates, inputs, or sum-of-product expressions in the logic. (Using SOFT and/or LCELL primitives in the logic will not reduce its size for Design Doctor analysis. Although these primitives allow the Compiler during logic synthesis to reduce the number of unique inputs that drive a node, the Design Doctor ignores them.) Add flipflops to synchronize signals in the logic. Temporarily close other Windows programs to make enough memory available to run MAX+PLUS II and do not run other programs in the background. You may be able to free up more memory by exiting Windows and then restarting Windows and MAX+PLUS II. You can also add more memory to your computer.

See also:

MAX+PLUS II Messages

Message Format

Project Reliability Guidelines


Multi-level logic drives <text> node (ID <net ID number>)

CAUSE:	The logic driving the Clock, Clear, or Preset signal consists of combinatorial logic with two or more gates. This multi-level Clock configuration is unreliable because of possible static hazards.

ACTION:	The logic driving the signal should consist of no more than a single gate. Reduce the complexity of the logic. If the specified signal is a Clock signal, replace the flipflop that is being driven by the network with a flipflop that has a Clock Enable input (i.e., DFFE, JKFFE, SRFFE, or TFFE). Feed the driving logic into the flipflop’s Clock Enable input and drive the flipflop’s Clock signal with a global Clock. For examples of good design practice, see Gated Clock Examples, Multi-Level Clock Example, and Preset & Clear Configuration Examples.

See also:

Clock Configuration Guidelines

MAX+PLUS II Messages

Message Format

Preset & Clear Configuration Guidelines

Project Reliability Guidelines

Static Hazard Guidelines


Multiple flipflops drive <text> node (ID <net ID number>)

CAUSE:	The Clock, Clear, or Preset signal is driven by a network of two or more flipflops. This multi-Clock network configuration is unreliable and glitches may occur because the flipflops do not change states simultaneously or the delay paths from the flipflops are not equal.

ACTION:	Use a global Clock wherever possible. If the specified signal is a Clock signal, replace the flipflop that is being driven by the network with a flipflop that has a Clock Enable input (i.e., DFFE, JKFFE, SRFFE, or TFFE). Feed the driving logic into the flipflop’s Clock Enable input and drive the flipflop’s Clock signal with a global Clock. If the specified signal is a Clear or Preset signal, insert a flipflop between the driving logic and the specified Clear or Preset signal. Feed the driving logic into the data input of a flipflop and drive the Clear or Preset signal with the flipflop’s output. For an example of good design practice, see Multi-Clock Network Example.

See also:

Clock Configuration Guidelines

MAX+PLUS II Messages

Message Format

Project Reliability Guidelines


A race condition exists for flipflop <net ID number> on <node name>, driven by primitive <net ID number>
Race condition exists for flipflop <net ID number> on <node name> -- driven by primitive <net ID number>

CAUSE:	A race condition exists for the specified flipflop’s input. A race condition is unreliable because the flipflop input depends on the level of its output, and a glitch may occur when the output changes its logic level.

ACTION:	Change the logic to remove the flipflop’s dependence on its own output. For an example of good design practice, see Race Condition Example.

See also:

MAX+PLUS II Messages

Message Format

Project Reliability Guidelines

Race Condition Guidelines


Ripple Clock detected starting with flipflop <net ID number>

CAUSE:	The Design Doctor has found a network of flipflops that form a ripple Clock. This Clock configuration is not reliable because a ripple Clock introduces a large skew between clocking of the flipflops in the ripple chain, and can stretch out the worst-case setup time, hold time, and Clock-to-output delays for a project. Therefore, this Clock configuration can slow down the actual system speed.

ACTION:	Convert the network of flipflops into a synchronous counter that relies on a global Clock. For examples of good design practice, see Ripple Clock Examples.

See also:

Clock Configuration Guidelines

Counter Macrofunctions

MAX+PLUS II Messages

Message Format

Project Reliability Guidelines


Ripple-clocked logic drives primitive <net ID number>

CAUSE:	The primitive is driven by the output of a set of flipflops that form a ripple Clock. This ripple Clock configuration is unreliable because the flipflops may not change states synchronously.

ACTION:	Convert the ripple-clocked set of flipflops into a synchronous counter that relies on a global Clock. For examples of good design practice, see Ripple Clock Examples.

See also:

Clock Configuration Guidelines

Counter Macrofunctions

MAX+PLUS II Messages

Message Format

Project Reliability Guidelines


Unknown combinatorial feedback structure detected at primitive <net ID number>

CAUSE:	A network of cross-coupled logic cannot be identified. This logic is creating a latch, flipflop, or delay, and is not an Altera-provided primitive or macrofunction. You should only use the expander flipflop and expander latch macrofunctions provided in the MAX+PLUS II Macrofunction Library. In addition, you should only use these expander flipflop and expander latch macrofunctions after all dedicated flipflop and latch resources in the device (i.e., logic cells and peripheral registers) have been used.

ACTION:	If dedicated flipflop and latch resources are available in the device and the logic was a latch or flipflop function, replace it with LATCH or DFF primitive. If all dedicated resources have already been used, replace the logic with either an equivalent Altera-macrofunctions such as EXPDFF and EXPLATCH. If this message occurs for a delay structure, redesign the network so that it does not depend on internal timing parameters. For an example of a good design alternative to a delay chain, see Delay Chain Examples.

See also:

Expander Network Guidelines

MAX+PLUS II Messages

Message Format

Project Reliability Guidelines


Unknown combinatorial flipflop detected at primitive <net ID number>

CAUSE:	A flipflop structure exists in your project and is based on expander latches that are not Altera-provided macrofunction. You should only use the expander latch macrofunctions provided in the MAX+PLUS II Macrofunction Library. In addition, you should only use these expander latch macrofunctions after all dedicated flipflop and latch resources in the device (i.e., logic cells and peripheral registers) have been used.

ACTION:	If dedicated flipflop and latch resources are available in the device, replace the expander flipflop with a DFF primitive. If all dedicated resources have already been used, replace the flipflop structure with an equivalent Altera-provided macrofunction such as EXPDFF.

See also:

Expander Network Guidelines

MAX+PLUS II Messages

Message Format

Project Reliability Guidelines


Unknown combinatorial latch detected at primitive <net ID number>

CAUSE:	An expander latch exists in your project and is not an Altera-provided macrofunction. You should only use the expander latch macrofunctions provided in the MAX+PLUS II Macrofunction Library. In addition, you should only use these expander latch macrofunctions after all dedicated flipflop and latch resources in the device (i.e., logic cells and peripheral registers) have been used.

ACTION:	If dedicated flipflop and latch resources are available in the device, replace the expander latch with a LATCH primitive. If all dedicated resources have already been used, replace the latch structure with an equivalent Altera-provided macrofunction such as EXPLATCH, NANDLTCH, or NORLTCH.

See also:

Expander Network Guidelines

MAX+PLUS II Messages

Message Format

Project Reliability Guidelines


-----BEGINNING OF NON-TRANSLATED TEXT-----

Topic	Filename

Checking Project Reliability w/ the D. Doctor	DOCTOR

Design Doctor command	DOCTOR

Design Doctor utility (basic tool)	ODOCTOR

Ensuring Project Reliability procedure	EDPRO

Messages	DRMESS

Project Reliability Guideline Examples	DOCTOR (2/24/94)

Project Reliability Guideline Index	EDPRO

Project Reliability Guidelines	DOCTOR

-----END OF NON-TRANSLATED TEXT-----


Checking Project Reliability with the Design Doctor (Compiler)
Checking Project Reliability with the Design Doctor

The Compiler’s Design Doctor utility allows you to check the reliability of your project against one or more selected design rules. The Design Doctor provides predefined sets of design rules to analyze projects that will be implemented in EPLDs, FLEX 8000 devices, or MPLDs. You can also create your own set of design rules for the Design Doctor analysis.

To check the reliability of a project during compilation:

1.	Turn on the Design Doctor command. The Design Doctor icon appears under the Logic Synthesizer module box.

2.	Choose Design Doctor Settings. The Design Doctor Settings dialog box is displayed.

3.	Select one of the following sets of design rules under Design Rules:

Select EPLD Rules to analyze a project that will be implemented in EPLDs.

Select FLEX Rules to analyze a project that will be implemented in FLEX 8000 devices.

Select MPLD Rules to analyze a project based on all available design rules. This stringent analysis must be used for projects that will be implemented in MPLDs.

Select Custom Rules to analyze a project based on a customized selection of design rules.

4.	(Optional) To customize the set of rules:

a.	Choose Advanced Options to open the expanded Design Doctor Settings dialog box and view the currently selected individual design rules. If Custom is selected under Design Rules, any previously-defined custom settings will be displayed. If EPLD Rules, FLEX Rules, or MPLD Rules is selected under Design Rules, the default settings for that set of design rules are displayed. If you then change these settings, the selection under Design Rules changes to Custom. However, if you turn on the same combination of individual rules as those in the EPLD Rules, FLEX Rules, or MPLD Rules option, that option is turned on.

b.	Turn on one or more of the following individual design-rule checking options:

Ripple Clocks	Preset/Clear Networks

Gated Clocks	Asynchronous Inputs

Multi-Level Clocks	Delay Chains

Multi-Clock Networks	Race Conditions

Before Synthesis	Expander Networks

After Synthesis	Master Reset

5.	To begin compilation and Design Doctor analysis, choose the Start button in the Compiler window or the Project Save & Compile command in any MAX+PLUS II application.

To check the status of the Design Doctor analysis, you can double-click Button 1 on the Design Doctor icon in the Compiler window.

See also:

Compiling a Project

Ensuring Project Reliability

Project Reliability Checklist

Project Reliability Guidelines


Ripple Clocks option

A Design Doctor option that checks a project for ripple clocking, i.e., a clocking configuration in which the Q output of one flipflop drives the Clock input to another flipflop.

Ripple clocking is commonly used to create a counter. It is unreliable if logic depends on the state of multiple flipflops within the logic that forms the ripple Clock.


Gated Clocks option

A Design Doctor option that checks a project for a gated Clock that violates one or more of the following Clock Configuration Guidelines:

The logic driving the Clock must consist of a single AND or OR gate.

Only one input to the logic gate should act as the actual Clock.


Multi-Level Clocks option

A Design Doctor option that checks a project for clocking configurations in which combinatorial logic that feeds a Clock expands beyond one level, i.e., beyond a single AND or OR gate.


Multi-Clock Networks option

A Design Doctor option that checks a project for the use of two or more Clocks within a single device.


Static Hazards options (Before Synthesis and/or After Synthesis)

Design Doctor options that check a project for static hazards in purely combinatorial networks and for logic that feeds the secondary inputs (control signals) of a flipflop or a state machine.

Since logic containing static hazards can exist in the project’s original design files or can be introduced during logic synthesis and minimization, the Design Doctor can check for static hazard violations before and/or after logic synthesis.


Preset/Clear Networks option

A Design Doctor option that checks a project for potentially unreliable Preset and Clear signal configurations, i.e., logic that violates one or more of the following Preset & Clear Configuration Guidelines:

The ideal Preset or Clear configuration is to use a global signal driven directly from a device pin.

A master Reset pin should feed the Preset or Clear input of every flipflop in the project.

For a gated Preset or Clear signal, a single pin or flipflop should act as the source of the Preset or Clear, while all other signals act as address or control signals.

Address or control signals must remain stable while the Preset or Clear signal is active.


Asynchronous Inputs option

A Design Doctor option that checks a project for any input pin that is not synchronized to the device Clock and which also drives multiple flipflops or which drives pure combinatorial logic that in turn drives multiple flipflops. An input pin that feeds a purely combinatorial network is not subject to this check, unless the network feeds a data input or Clock Enable input of a flipflop.

Since asynchronous inputs cannot always meet the setup and hold time requirements of the flipflops they feed, they can cause reliability problems such as race conditions.


Delay Chains option

A Design Doctor option that checks a project for logic that contains a series of LCELL or EXP primitives used to create an intentional delay or asynchronous pulse.

A delay chain is unreliable because the best-case delay of an LCELL or EXP primitive cannot be guaranteed. This configuration also increases the sensitivity of the design to operating conditions.


Race Conditions option

A Design Doctor option that checks a project for logic in which flipflops that depend on their own output for their secondary inputs, i.e., flipflops that generate their own Clear and/or Preset signals.

All race conditions can potentially cause glitches and unpredictable results.


Expander Networks option

A Design Doctor option that checks a project for cross-coupled logic that is used to create additional latches or flipflops in a device, including cross-coupled logic that uses expander product terms in Altera-provided macrofunctions such as EXPDFF, EXPLATCH, NANDLATCH, and NORLTCH

Cross-coupled logic can be unreliable and should only be implemented with the EXPDFF, EXPLATCH, NANDLTCH, or NORLATCH macrofunctions. In addition, these macrofunctions should be used only after all dedicated flipflop and latch resources in a device are used.


Master Reset option

A Design Doctor option that checks a project for a board-level master Reset signal that clears every flipflop. If a master Reset does not exist, the Design Doctor also attempts to isolate a common pin that resets all or the majority of registers in the project either directly or through some enabling logic.

A warning is issued when the Design Doctor cannot locate a master Reset pin in the project or when the Design Doctor has selected a pin as the master Reset.


Design Doctor dialog box
Design Doctor Settings dialog box


Design Doctor expanded dialog box
Expanded Design Doctor Settings dialog box


Asynchronous Input Guidelines (Project Reliability Guidelines)
Asynchronous Input Guidelines

Many designs require synchronized communications between asynchronously clocked systems. Ideally, a system should be designed to be synchronous so that all signal transitions within and generated by the system use an edge of a global Clock as a reference. Synchronous systems also require synchronously-clocked inputs to avoid race conditions, setup time and hold time violations, and other logic problems. It is desirable to synchronize external inputs with each system’s local Clock to ensure that operation and mean-time-between-failure requirements for the composite system(s) are met.

By definition, asynchronous inputs cannot always meet the setup and hold time requirements of the flipflops they feed. Therefore, asynchronous inputs can cause an incorrect value to be clocked into a flipflop, or cause a flipflop to enter a metastable state in which its output is not recognized as a 1 or a 0. If not properly handled, metastability can lead to serious system reliability problems.

To avoid metastability problems, you should never allow an asynchronous signal to fan out to more than one flipflop within a device. For examples of good design practice, see Asynchronous Input Examples.

The Design Doctor command offers an Asynchronous Inputs design-checking option that can be used to analyze your project.

See also:

Checking Project Reliability with the Design Doctor

Ensuring Project Reliability

Project Reliability Checklist

Project Reliability Guidelines

Race Condition Guidelines


Clock Configuration Guidelines (Project Reliability Guidelines)
Clock Configuration Guidelines

Reliable clocking is critical to the successful operation of any digital design, regardless of whether it is constructed with discrete logic, programmable logic, or full-custom silicon. A poorly designed Clock configuration may lead to erratic behavior when extreme temperature, voltage, or fabrication process variations occur.

Altera recommends using a global Clock wherever possible. However, if implementing a single global Clock in your project is not possible or practical, you may use another Clock configuration such as a gated Clock. Other types of Clock configurations such as ripple Clocks, multi-level Clocks, multi-Clock network, or state machine-driven Clocks are potentially unreliable and should not be used.

The Design Doctor command offers Ripple Clocks, Gated Clocks, Multi-Level Clocks, and Multi-Clock Networks design-checking options that can be used to analyze your project. These design rules are based on the following guidelines.

Global Clocks

Global (or synchronous) Clocks are the simplest and most predictable Clocks for a project. With a truly synchronous system, a single master Clock, driven by an input pin, clocks every flipflop in the project. You should use global Clocks in your projects whenever possible. A global Clock can be implemented with the GLOBAL primitive or with the Automatic Global Clock option in the Compiler’s Global Project Logic Synthesis dialog box.

Altera devices feature a global Clock pin that can be connected directly to every register in the device. These global Clocks provide the fastest Clock-to-output delay for the device. For an example of reliable global clocking, see Global Clock Example.

Gated Clocks

Altera devices feature product-term logic array Clocks that allow arbitrary functions to clock individual flipflops. However, when you use an array Clock, you must analyze the Clock function carefully to prevent glitches.

An array Clock is commonly used to construct a gated Clock. Gated Clocks are often associated with microprocessor interfaces that use address lines as gates for a write strobe. In general, however, a gated Clock exists whenever a flipflop is clocked by a combinatorial function.

Gated Clocks can be just as reliable as global Clocks if the following conditions are met:

Only one input to the logic gate should act as the actual Clock.

The logic driving the Clock must consist of a single AND or OR gate.

For examples of good design practice, see Gated Clock Examples.

Multi-Level Clocks

Multi-level Clocks exist when the combinatorial logic generating a gated Clock expands beyond one level (i.e., beyond a single AND or OR gate), and make it difficult to verify the project’s reliability. Static hazards that are not apparent without extensive prototyping or simulation may exist.

You should not use multiple levels of combinatorial logic to clock flipflops in your projects.

You can remove the hazards that may exist in multi-level logic. For example, you can try inserting redundant logic into the project. However, the MAX+PLUS II Compiler may remove this logic during logic synthesis, making it difficult to verify whether the hazard has actually been removed. Therefore, you should find a different way to implement the function instead. For an example of a good design alternative, see Multi-Level Clock Example.

Ripple Clocks

A ripple Clock is a Clock configuration in which the Q output of one flipflop drives the Clock input to another flipflop. Although ripple Clocks can be just as reliable as global Clocks, a glitch may occur if the output of one or more flipflops in a ripple chain feeds into combinatorial logic. Ripple Clocks can also complicate the timing calculations associated with a circuit. A ripple Clock introduces a large skew between the clocking of the flipflops in a ripple chain, and can stretch out the worst-case setup time, hold time, and Clock-to-output delays for a circuit, slowing down the actual system speed.

Synchronous counters are often preferable to ripple counters because they have a faster Clock-to-output time and require the same number of logic cells. For examples of good design alternatives, see Ripple Clock Examples.

Multi-Clock Networks

Many applications require the use of multiple Clocks within a single device. Common examples are designs that interface between two asynchronous microprocessors, or between a microprocessor and an asynchronous communications channel. These applications introduce additional timing constraints due to the setup and hold time requirements between the Clock signals.

Multi-Clock systems may also require synchronization of some asynchronous signals. For an example of a good design alternative, see Multi-Clock Network Example.

See also:

Asynchronous Input Guidelines

Checking Project Reliability with the Design Doctor

Ensuring Project Reliability

Project Reliability Checklist

Project Reliability Guidelines

Static Hazard Guidelines


Delay Chain Guidelines (Project Reliability Guidelines)
Delay Chain Guidelines

A delay chain is a series of LCELL or EXP primitives used to create an intentional delay or asynchronous pulse. The delay of these elements varies with temperature, power supply voltage, and device fabrication process, possibly producing a race condition and an unreliable circuit. For an example of a good design alternative, see Delay Chain Examples.

Never rely on delay chains for pin-to-pin or internal delays.

The Design Doctor command offers a Delay Chains design-checking option that can be used to analyze your project.

See also:

Checking Project Reliability with the Design Doctor

Ensuring Project Reliability

Project Reliability Checklist

Project Reliability Guidelines

Race Condition Guidelines


Expander Network Guidelines (Project Reliability Guidelines)
Expander Network Guidelines

MAX 5000 and MAX 7000 devices contain expander product terms that you can use to create additional latches or flipflops in a device. However, using these resources to create expander latches or expander flipflops is not recommended. If you must create additional latches or flipflops, you should observe the following guidelines:

Use expander product terms only after all dedicated latches and flipflops in the device have been used.

Use only the EXPDFF, EXPLATCH, NANDLTCH, and NORLTCH macrofunctions provided with the MAX+PLUS II Macrofunction Library; do not create your own cross-coupled structures. Avoid tying multiple EXPDFF, EXPLATCH, NANDLTCH, and NORLTCH macrofunctions together. Multiple instances of these macrofunctions should always be separated by LCELL primitives.

The Design Doctor command offers an Expander Networks design-checking option that can be used to analyze your project.

See also:

Checking Project Reliability with the Design Doctor

Ensuring Project Reliability

Project Reliability Checklist

Project Reliability Guidelines


Master Reset Guidelines (Project Reliability Guidelines)
Master Reset Guidelines

Although Altera EPLDs and FLEX 8000 devices have built-in Power-On Reset (POR) circuitry that usually causes all flipflops to be cleared before use, Altera MPLDs do not. If you intend to convert your EPLD- or FLEX 8000-based project into an MPLD, you should not rely on this feature. To ensure proper operation, your project should use a board-level (i.e., master) Reset signal to clear every flipflop.

Flipflops can also be cleared with a global Clear signal, which can be implemented with the GLOBAL primitive or with the Automatic Global Clear option in the Compiler’s Global Project Logic Synthesis dialog box. A global signal is used in different device families according to global signal availability.

If a master Reset is not available, you must ensure that the system initializes all flipflops before they are used. Therefore, all data flipflops should be clocked, all counters should be cleared (synchronously or asynchronously), and all state machines should be forced to a known state.

The Design Doctor command offers a Master Reset design-checking option that can be used to analyze your project.

See also:

Checking Project Reliability with the Design Doctor

Ensuring Project Reliability

Preset & Clear Configuration Guidelines

Project Reliability Checklist

Project Reliability Guidelines


Preset & Clear Configuration Guidelines (Project Reliability Guidelines)
Preset & Clear Configuration Guidelines

Preset and Clear signals demand the same careful consideration as Clocks, because they are also sensitive to race conditions and similar design hazards. The following guidelines will help to ensure reliable logic in your projects:

As with Clock signals, the best Preset or Clear configuration uses a global signal that is driven directly from a device pin. A global Preset or Clear signal can be implemented with a GLOBAL primitive or with the Automatic Global Clock option in the Compiler’s Global Project Logic Synthesis dialog box.

Altera recommends that you use a single master Reset pin that feeds the Preset or Clear of every flipflop in the project.

If you use a gated Preset or Clear, a single pin or flipflop should act as the source of the Preset or Clear, while all other signals act as address or control signals.

Address or control signals must remain stable while the Preset or Clear is active.

The Design Doctor command offers a Preset/Clear Networks design-checking option that can be used to analyze your project. For examples of good design practice, see Preset & Clear Configuration Examples.

See also:

Checking Project Reliability with the Design Doctor

Clock Configuration Guidelines

Ensuring Project Reliability

Master Reset Guidelines

Project Reliability Checklist

Project Reliability Guidelines

Race Condition Guidelines


Race Condition Guidelines (Project Reliability Guidelines)
Race Condition Guidelines

A race condition exists in a project when a signal follows two or more combinatorial logic paths to a common circuit element. You should never design circuits in which reliable operation depends on a predictable skew between two different signal paths.

The most serious race condition occurs when a flipflop depends on its output for some other control logic, namely Clock, Clear, Preset, and Clock Enable. For an example of a good design alternative, see Race Condition Example.

The Design Doctor command offers a Race Conditions design-checking option that can be used to analyze your project.

See also:

Checking Project Reliability with the Design Doctor

Ensuring Project Reliability

Preset & Clear Configuration Guidelines

Project Reliability Checklist

Project Reliability Guidelines


Static Hazard Guidelines (Project Reliability Guidelines)
Static Hazard Guidelines

A static hazard occurs when a change in an input logic level causes an output level to momentarily change levels or experience a "glitch" For an example of good design practice, see Multi-Level Clock Example.

If the Design Doctor command’s Before Synthesis and/or After Synthesis options for detecting static hazards are turned on when a project is analyzed, warnings are issued for logic that contains static hazards. The Design Doctor can check for static hazards both before and after logic synthesis, since static hazards may occur in the original design files or may be introduced during logic synthesis. The Design Doctor only checks for static hazards in purely combinatorial networks and in logic that feeds the control signals of a flipflop or state machine.

The Design Doctor command offers both Before Synthesis and After Synthesis design-checking options for detecting static hazards that can be used to analyze your project.

See also:

Checking Project Reliability with the Design Doctor

Ensuring Project Reliability

Project Reliability Checklist

Project Reliability Guidelines


Project Reliability Checklist (Project Reliability Guidelines)
Project Reliability Checklist

This list is a basic checklist of reliability issues that should be addressed before your project is implemented in one or more devices.

This checklist is only a summary of some of the design rules discussed in Project Reliability Guidelines and should be used in conjunction with those guidelines.

Project Reliability Checklist

Ensure Clock, Preset, and Clear configurations are free of glitches. See Clock Configuration and Preset & Clear Configuration Guidelines.

Never use Clocks consisting of more than one level of combinatorial logic. See Multi-Level Clocks in Clock Configuration Guidelines.

Carefully calculate setup times and hold times for multi-Clock systems. See Multi-Clock Systems in Clock Configuration Guidelines.

Synchronize signals between flipflops in multi-Clock systems when the setup and hold time requirements cannot be met. See Multi-Clock Systems in Clock Configuration Guidelines.

Use the MAX+PLUS II Simulator and Timing Analyzer to check setup and hold times.

Ensure that Preset and Clear signals do not contain race conditions. See Preset & Clear Configuration Guidelines and Race Condition Guidelines.

Ensure that no other internal race conditions exist. See Race Condition Guidelines.

Register all glitch-sensitive outputs.

Synchronize all asynchronous inputs. See Asynchronous Input Guidelines.

Never rely on delay chains for pin-to-pin or internal delays. See Delay Chain Guidelines.

Do not rely on Power-On Reset. Use a master Reset pin to clear all flipflops. See Master Reset Guidelines

Remove any stuck states from state machines or synchronous logic. See Recovering from Illegal States.

Do not create your own cross-coupled structures. Instead, use the EXPDFF, EXPLATCH, NORLTCH, and NANDLTCH macrofunctions provided in the MAX+PLUS II Macrofunction Library. See Expander Network Guidelines.

Avoid tying multiple EXPDFF, EXPLATCH, NANDLTCH, and NORLTCH macrofunctions together. Multiple instances of these macrofunctions should always be separated by LCELL primitives. See Expander Network Guidelines.

See also:

Checking Project Reliability with the Design Doctor

Detecting Setup & Hold Violations (Simulator)

Ensuring Project Reliability

Running a Timing Analysis


Asynchronous Input Examples (Project Reliability Guidelines)
Asynchronous Input Examples

The following examples illustrate asynchronous inputs and possible design alternatives.

Figure 1 shows a binary counter with an asynchronous signal controlling the Enable input (ENA). When the Enable input violates the setup or hold time constraint of the counter, each bit of the counter may behave erratically. One bit may count up while another bit holds, causing the counter to enter an invalid state. In addition, any one of the bits may become metastable, creating problems in other portions of the circuit.

Figure 1. Binary Counter with Asynchronous Enable

Synchronizing the Enable signal with an extra flipflop removes the reliability problem by guaranteeing that the counter’s setup time will not be violated. Figure 2 shows one method of synchronization. Although the synchronizing flipflop may still experience metastability, it should stabilize before the next Clock edge. In general, to avoid metastability problems in a device, you should never have an asynchronous signal fan out to more than one flipflop within a device.

Figure 2. Binary Counter with One Synchronizing Flipflop

An alternative method of synchronizing an asynchronous input is shown in Figure 3. The input a_en drives the Clock of a flipflop with the data input tied to VCC. This circuit is useful for detecting asynchronous events that may be shorter than the duration of the Clock period.

Figure 3. Binary Counter with Two Synchronizing Flipflops

If asychronous signals are used as inputs to any registered function (such as state machines, controllers, counters, etc.), setup and hold time violations may occur. These violations can cause invalid data to be clocked into the function, or place the function in a metastable state. Figure 4 shows a state machine with asynchronous inputs.

Figure 4. State Machine with Asynchronous Inputs

Figure 5 shows how input registers can be to the state machine in Figure 4 to ensure that the setup and hold time requirements are met. Although the additional registers are still exposed to possible setup and hold violations, the state registers are prevented from going into a metastable state, and the state machine does not enter an undefined state.

Figure 5. State Machine with Additional Latching

See also:

Asynchronous Input Guidelines

Project Reliability Checklist

Project Reliability Guidelines


Global Clock Example (Project Reliability Guidelines)
Global Clock Example

Figure 1 shows an example of a global Clock implemented in a MAX 5000 device. The GLOBAL primitive implements the global Clock for the Clock pin. The timing waveforms in Figure 1 reveal that inputs d[1..3], which form the data input to the flipflop, are subject to a setup and hold time constraint with respect to clk. Setup and hold time requirements are given in individual device data sheets or can be calculated with the MAX+PLUS II Timing Analyzer.

Figure 1. Global Clock Example

Figure 2 shows an example that connects a global Clock (CLK) to a flipflop. The functionality for this design file is the same as Figure 1.

Figure 2. Global Clock Example

SUBDESIGN example

(

clk	: INPUT;

d[3..1]	: INPUT;

out	: OUTPUT;

)

VARIABLE

ff	: DFF;

BEGIN

ff.clk = GLOBAL(clk);

ff.d   = d1 & d2 & d3;

out    = ff.q;

END;

The clk input signal is connected to the in input of the GLOBAL primitive. The output of the GLOBAL primitive is then connected to the Clock of each flipflop.

Global signals are ignored for devices that do not support them.

See also:

Clock Configuration Guidelines

Project Reliability Checklist

Project Reliability Guidelines

Running a Timing Analysis


Gated Clock Examples (Project Reliability Guidelines)
Gated Clock Examples

The following examples illustrate reliable gated Clock configurations. Examples of unreliable gated Clocks and design alternatives are also provided.

Figures 1 and 2 show examples of reliable gated Clocks. In Figure 1, an AND gate produces the gated Clock; Figure 2 uses an OR gate. In these examples, pins nwr and nwe are considered to be the Clock pins and pins add[0..3] are address pins. The data to both flipflops is generated by random logic from signals d[1..n].

Figure 1. AND-Gate Clock

Figure 2. OR-Gate Clock

The waveforms in Figures 1 and 2 show the relevant setup and hold time requirements. The address signals for both projects must be stable while the Clock is active (nwr is active low and nwe is active high). If the address signals fail to remain stable for the time indicated, a glitch may appear at the Clock, causing the flipflop to change state incorrectly. Data pins d[1..n], on the other hand, must meet the standard setup and hold time requirements for the active edges of nwr and nwe.

You can often improve the reliability of a project by converting gated Clocks to global Clocks. Figure 3 shows how you can redesign the circuit in Figure 1 with a global Clock. The address signals now control the Clock Enable input to a DFFE. When ENA is high, the value at the D input clocks into the flipflop; when ENA is low, the current value is maintained.

Figure 3. AND-Gate Clock Converted to Global Clock

The timing waveforms of the redesigned circuit in Figure 3 show that the address signals do not need to be stable while nwr is active. Instead, they only need to meet the same setup and hold time requirements as the data pins.

Figure 4 shows an example of an unreliable gated Clock. The rco signal, generated from a 3-bit synchronous up counter, is used to clock a flipflop. However, multiple flipflops are ANDed to form a Clock, violating one of the requirements for reliable gated Clocks. None of the flipflops that generate the rco signal can be considered the actual Clock signal, since all flipflops change at approximately the same time. Thus, the rco signal may experience a glitch as the counter counts from 3 to 4, as shown in the timing waveforms in Figure 4.

Figure 4. Unreliable Gated Clock

Figure 5 shows a reliable, globally-clocked version of the unreliable counter circuit in Figure 4. The rco signal controls the Clock Enable input to DFFE. No additional logic cells are required for this change.

Figure 5. Unreliable Gated Clock Converted to Global Clock

See also:

Clock Configuration Guidelines

Project Reliability Checklist

Project Reliability Guidelines

Race Condition Example

Race Condition Guidelines


Multi-Level Clock Example (Project Reliability Guidelines)
Multi-Level Clock Example

The following example illustrates an unreliable multi-level Clock configuration and a possible design alternative.

Figure 1 shows a simple example of a multi-level Clock that contains a static hazard. The Clock is the output of a multiplexer controlled by the pin sel. The inputs to the multiplexer are a Clock (clk) and a divide-by-two version of the same Clock (div2). The timing waveforms in Figure 1 show that a static hazard exists when the sel signal changes while both Clocks are a logical 1. The severity of the hazard depends on the operating conditions.

Figure 1. Multi-Level Clock with Static Hazard

You can remove the static hazards from multi-level logic. For example, you can try inserting redundant logic into the project. However, the MAX+PLUS II Compiler may remove this logic during logic synthesis, making it difficult to verify whether a static hazard has actually been removed. Therefore, you should find a different way to implement the function instead.

Figure 2 shows alternative single-level clock configuration for the circuit in Figure 1. Here the sel pin and the div2 signal are used to control the Clock Enable input of a DFFE flipflop, rather than the Clock pin of the flipflop. No additional logic cells are required for this circuit.

Figure 2. Single-Level Clock with No Static Hazard

Different systems require different approaches to removing multi-level Clocks. Contact Altera Applications for assistance.

See also:

Clock Configuration Guidelines

Project Reliability Checklist

Project Reliability Guidelines

Race Condition Example

Race Condition Guidelines

Static Hazard Guidelines


Ripple Clock Examples (Project Reliability Guidelines)
Ripple Clock Examples

The following examples illustrate unreliable ripple Clock configurations and possible design alternatives.

Ripple Clocks often occur when a ripple counter is constructed from toggle flipflops, with the output of one flipflop clocking the input of the next. See Figure 1.

Figure 1. Ripple Clock

Synchronous counters are often preferable to ripple counters because they have a faster Clock-to-output time and require the same number of logic cells. Figure 2 shows the circuit in Figure 1 converted to a synchronous counter with global clocking. This implementation requires the same number of logic cells and has a faster Clock-to-output time. The MAX+PLUS II Macrofunction Library offers a wide variety of synchronous counter macrofunctions.

Figure 2. Ripple Clock Converted to Global Clock

Figure 3 shows another example of ripple clocking. The Clock period of the circuit in Figure 3 depends on the time it takes for the change in the least significant bit of the counter to propagate through to the most significant bit. This period depends on the size of the counter. Therefore, as ripple counters grow, system speeds decrease. In general, you should use a synchronous counter whenever possible.

Figure 3. Another Ripple Clock

When the ripple counter in Figure 3 is redesigned for synchronous operation, as shown in Figure 4, the system speed is determined by the setup and hold times of the registers, rather than the number of bits in the counter. Without requiring additional resources, the synchronous implementation improves the speed of the counter, and eliminates the possibility of invalid count values.

Figure 4. Synchronous Counter

See also:

Clock Configuration Guidelines

Project Reliability Checklist

Project Reliability Guidelines

Race Condition Example

Race Condition Guidelines


Multi-Clock Network Example (Project Reliability Guidelines)
Multi-Clock Network Example

The following example illustrates an unreliable multi-Clock configuration and a possible design alternative.

Figure 1 shows an example of a multi-Clock system.The clk_a input is used to clock reg_a; clk_b is used to clock reg_b. Because reg_a drives the combinatorial logic that goes to reg_b, clk_a has setup and hold time requirements with respect to clk_b. However, since reg_b does not drive the logic feeding reg_a, there is no setup time requirement on the leading edge of clk_b with respect to clk_a. Also, there is no setup time requirement on the relative falling edges of clk_a and clk_b because the falling edges do not affect the flipflops.

Figure 1. Multi-Clock System

In circuits that have two independent Clocks, such as in Figure 1, it is impossible to ensure that the setup and hold times between them are met. In such cases, you must synchronize the circuit. Figure 2 shows how the reg_a values are synchronized with clk_b before they are used. A new flipflop, reg_c, is clocked by clk_b, which ensures that its outputs will meet the setup time of reg_b. However, this approach delays the output by one Clock cycle and uses an extra logic cell.

Figure 2. Multi-Clock System with Synchronized Register Output

See also:

Clock Configuration Guidelines

Project Reliability Checklist

Project Reliability Guidelines

Race Condition Example

Race Condition Guidelines


Delay Chain Examples (Project Reliability Guidelines)
The following illustrations show how EXP and LCELL primitives can be misused to create an intentional delay chain.

The circuit in Figure 1 attempts to vary the setup, hold, and Clock-to-output specifications of the flipflops. However, the best-case delay of a logic cell or expander product term cannot be guaranteed. These delays only increase the circuit’s sensitivity to operating conditions and decrease its reliability.

Figure 1. Misused LCELL & EXP Primitives

Figure 2 shows an attempt to create an asynchronous pulse generator with EXP primitives.

Figure 2. Unreliable Timing-Dependent Asynchronous Pulse Generator

Figure 3 shows a reliable alternative to the function in Figure 2.

Figure 3. Synchronous Pulse Generator

See also:

Delay Chain Guidelines

Project Reliability Checklist

Project Reliability Guidelines


Preset & Clear Configuration Examples (Project Reliability Guidelines)
Preset & Clear Configuration Examples

Figures 1 through 4 show examples of acceptable Preset and Clear configurations. You should never generate Clear and Preset signals with multi-level logic or with single-level logic that contains a race condition. The Preset and Clear configurations should also meet the Clock Configuration Guidelines.

Figure 1. Legal  Pin Clear Configuration

Figure 2. Legal  Register Clear Configuration

Figure 3. Legal  Gated Clear Configuration

Figure 4. Legal  Asynchronous Load

Figures 5 and 6 show examples of asynchronous and synchronous Clear configurations.

Figure 5. Asynchronous Clear

Figure 6. Synchronous Clear

See also:

Preset & Clear Configuration Guidelines

Project Reliability Checklist

Project Reliability Guidelines

Race Condition Example

Race Condition Guidelines


Race Condition Example (Project Reliability Guidelines)
Race Condition Example

The following example illustrates a race condition and a possible design alternative.

Figure 1 shows a common example of a race condition in an asynchronous pulse generator. The circuit is not reliable because there is no guarantee that the pulse from reg_a will be long enough to meet the minimum pulse-width requirements elsewhere in the circuit. Instead, you should use a synchronous pulse generator, as shown in Figure 2. In Figure 2, two flipflops are used to create a pulse from a high-frequency Clock.

Figure 1. Asynchronous Pulse Generator with a Race Condition

Figure 2. Synchronous Pulse Generator

See also:

Clock Configuration Guidelines

Preset & Clear Configuration Guidelines

Project Reliability Checklist

Race Condition Guidelines


Compiler Basic Tools;
Basic Tools

Buttons

Start

Stop & Stop/Show Status

Input Files

Altera Design File (.adf)

Assignment & Configuration File (.acf)

ACF Format

EDIF Command File (.edc)

EDIF Command File Format

EDIF Input File (.edf)

Fit File (.fit)

Graphic Design File (.gdf)

Hierarchy Interconnect File (.hif)

Include File (.inc)

Library Mapping File (.lmf)

Library Mapping File Format

OrCAD Library File (.lib)

OrCAD Schematic File (.sch)

State Machine File (.smf)

Symbol File (.sym)

Text Design File (.tdf)

Text Design File Format

VHDL Design Files

Waveform Design File (.wdf)

Xilinx Netlist Format File (.xnf)

MAX+PLUS II Initialization Files

maxplus2.ini File

Modules & Utilities

Compiler Netlist Extractor

Database Builder

Logic Synthesizer

Design Doctor

Partitioner

Fitter

Functional SNF Extractor

Timing SNF Extractor

Linked SNF Extractor

EDIF Netlist Writer

Verilog Netlist Writer

VHDL Netlist Writer

Assembler

Output Files

Assignment & Configuration File (.acf)

ACF Format

Assignment & Configuration Output File (.aco)

Compiler Netlist File (.cnf)

EDIF Output File (.edo)

Fit File (.fit)

Hexadecimal (Intel-Format) File (.hex)

Hierarchy Interconnect File (.hif)

JEDEC File (.jed)

Programmer Object File (.pof)

Report File (.rpt)

Report File Format

Serial Bitstream File (.sbf)

Simulator Netlist File (.snf)

SRAM Object File (.sof)

Standard Delay Format Output File (.sdo)

Symbol File (.sym)

Tabular Text File (.ttf)

Text Design Export File (.tdx)

Text Design Output File (.tdo)

Verilog Output File (.vo)

VHDL Output File (.vho)

VHDL Memory Output File (.vmo)

Probe, Resource & Device Assignments

Clique Assignments

Connected Pin Assignments

Device Assignments

Guidelines for Timing Assignments

Logic Option Assignments

Pin, Location & Chip Assignments

Probe Assignments

Timing Assignments

Status Bar & Toolbar

Status Bar

Toolbar

Widgets

File Icons

Hourglass

Module Boxes

Progress Bar


Start Button (Compiler)
Start Button

Begins compiling the current project. Show me

Compilation is performed on the basis of the settings specified with the following menu commands:

Command:	Action:

Design Doctor	Activates or deactivates the Design Doctor, and specifies the set of rules to use for design-rule checking.

Global Project Logic Synthesis	Specifies a default logic synthesis style and the types of global signals for the Compiler to create automatically for the project.

Functional SNF Extractor	Activates or deactivates the Functional SNF Extractor, which generates a functional SNF.

Timing SNF Extractor	Activates or deactivates the Timing SNF Extractor, which generates a timing SNF.

Optimize Timing SNF	Activates or deactivates the dynamic models feature that optimizes the timing SNF created by the Timing SNF Extractor.

Automatic LCELL Insertion	Activates or deactivates the feature that automatically inserts LCELL buffers to achieve a fit.

Report File	Specifies sections to include in the Report File.

Generate JEDEC File	Activates or deactivates the feature that creates JEDEC Files in addition to POFs and/or SOFs when a project compiles successfully.

Total Recompile	Activates or deactivates the feature that completely recompiles all design files in the project.

Global Project Device Options	Specifies the default device options for all devices.

EDIF Netlist Reader Settings	Specifies ancillary files and options for the EDIF Netlist Reader to use in compiling EDIF Input Files.

EDIF Netlist Writer	Activates or deactivates the EDIF Netlist Writer.

EDIF Netlist Writer Settings	Specifies the ancillary files and options to be used to generate EDIF Output Files.

Verilog Netlist Writer Settings	Activates or deactivates the Verilog Netlist Writer, which generates a Verilog Output File.

VHDL Netlist Writer Settings	Activates or deactivates the VHDL Netlist Writer, which generates a VHDL Output File.

The Compiler runs as a background process. During compilation, you can locate the source(s) of and get help on any error or warning messages displayed in the Message Processor window, or edit files in a MAX+PLUS II editor application.

You can also start the Compiler by choosing Project Save & Compile (File menu) in any MAX+PLUS II application. You can stop the Compiler by choosing Stop.

See also:

Compiling a Project

Locating the Source of a Message

Starting & Stopping the Compiler

Totally Recompiling a Project


Stop & Stop/Show Status Buttons (Compiler)
Stop & Stop/Show Status Buttons

Stops the compilation. Show me

After you choose Stop, if you choose the Start button, the Compiler recompiles the project from the beginning. However, Compiler Netlist Extractor warning messages may not be redisplayed unless you turn on Total Recompile (File menu) before recompiling.

When the Compiler is attempting to partition and/or fit the project, the Stop button changes into the Stop/Show Status button. Show me

When you choose Stop/Show Status, the Compiler displays the Partitioner/Fitter Status dialog box, which displays the current status of fitting and partitioning and allows you to stop the compilation and/or generate a Report File.

See also:

Starting & Stopping the Compiler

Totally Recompiling a Project


Altera Design File (.adf) Description
Altera Design File (.adf)

An ASCII text file (with the extension .adf) originally created for use with Altera’s A+PLUS software.

The ADF uses a netlist format and Boolean equations to describe design logic. The ADF is also the output of the LogiCaps schematic capture program and the A+PLUS State Machine Converter.

The Compiler automatically compiles ADFs. In addition, an A+PLUS LEF can be renamed with the extension .adf and processed by the Compiler.

An ADF can be used to define all logic in a project,or can be used to define a bottom-level file in a hierarchical project. MAX+PLUS II automatically creates a Symbol File that represents an ADF when you first compile the file or when you choose Create Default Symbol (File menu). This symbol and the logic it represents can be incorporated into a GDF.

You can also use ADF logic in an AHDL TDF by including a Function Prototype and inserting an instance of the macrofunction into the TDF. You can also automatically generate a default Include File that contains a Function Prototype for an ADF with Create Default Include File (File menu).

The following guidelines apply when you compile ADFs with MAX+PLUS II:

Unspecified Clock inputs are treated as synchronous (global) Clock inputs in A+PLUS but are treated as array (asynchronous) Clock inputs in MAX+PLUS II. To ensure that you obtain the same fit when you compile an ADF with MAX+PLUS II, edit the original design file by inserting a GLOBAL (SCLK) buffer at the unspecified Clock inputs, re-create the ADF (if necessary), then compile with MAX+PLUS II. Example

The MAX+PLUS II Compiler does not recognize pin, logic cell, chip, or device assignments made in an an ADF. You must make these assignments with Assign menu commands or in the Floorplan Editor.

CONF and COIF primitives in ADFs are converted into OUTPUT, TRI, and SOFT primitives in MAX+PLUS (DOS). When ADFs are converted with MAX+PLUS II, the SOFT primitives are changed to LCELL primitives instead. If this change prevents the project from fitting, Altera recommends that you convert ADFs to TDFs, either manually editing the files, or by creating an LEF with A+PLUS and using the LEF2AHDL Converter.

MAX+PLUS II considers ADFs to be case-insensitive. If you use case-sensitive node and/or pin names in ADFs, you may need to modify your files.

The ADF format is supported for backward compatibility with A+PLUS. You should create all new text-based design files in AHDL.

The file icon for each ADF that is part of the current hierarchy tree appears in the Hierarchy Display window.

See also:

Assigning a Device

Assigning a Pin, Location, or Chip

Creating a Default Include File

Creating & Using Custom Macrofunctions (AHDL)

Creating the Default Symbol for a File

Entering a Symbol

Primitives


Example: Inserting a GLOBAL Buffer in an ACF

Delete the following lines in the ACF:

NETWORK:

   CLK1 = INP (CLK1)

And replace them with the following lines:

NETWORK:

   CLK1NODE = INP (CLK1PIN)

   CLK1 = GLOBAL (CLK1NODE)


Fit File (.fit) Description
Fit File (.fit)

An ASCII text file (with the extension .fit) that records the pin, buried logic cell, chip, and device assignments for a MAX+PLUS II project. All external pin connections for a single-device project, which are needed for simulation and functional testing, are also recorded.

The Fit File is generated by the Partitioner and updated by the Fitter. The Compiler overwrites the Fit File during each compilation, whether it is successful or not. Back-annotation preserves the assignments in the Fit File.

The Floorplan Editor uses the Fit File to display a non-editable (read-only) view of the fitting results of the last compilation.

The icon for a Fit File with the same filename as the top-level design file in the current hierarchy tree appears in the Hierarchy Display window.

1.	You should never edit the Fit File. If you wish to edit the assignments for a project, back-annotate the assignments with Back-Annotate Project (File menu) and edit them with the Device and Pin/Location/Chip commands (Assign menu).

2.	Compiler-generated pin names that contain the tilde (~) character may appear in the Fit File for a project. The tilde character is reserved for Compiler-generated names only, you cannot use it in your own pin, node, and group (bus) names.

See also:

Adjusting the Fit During Compilation

Back-Annotating Assignments for a Project

Fitting & Refitting a Project


Report File (.rpt) Description
Report File (.rpt)

An ASCII text file (with the extension .rpt) that shows how the project is implemented in one or more devices, including partitioning, resource usage, inputs, outputs, and project timing. The Report File is generated by the Fitter module of the Compiler.

You can use the Report File Settings command (File menu) to include the following optional Report File sections: user resource and probe assignments, pin connections, file hierarchy, logic cell interconnections, and minimized equations.

You can double-click Button 1 on the Report File icon in the Compiler window to open a Text Editor window with the Report File for the current project. Provided that compilation has proceeded as far as the Fitter module, the Report File is generated regardless of whether fitting is successful.

The icon for a Report File with the same filename as the top-level design file in the current hierarchy tree appears in the Hierarchy Display window.

See also:

Report File Format

Setting Report File Options


State Machine File (.smf) Description
State Machine File (.smf)

An ASCII text file (with the extension .smf) originally created for use with Altera’s A+PLUS or SAM+PLUS software.

The SMF uses a netlist format, Boolean equations, state machines, and truth tables to describe design logic. A small difference exists between an SMF from SAM+PLUS and an SMF from A+PLUS. The Clock Subsection, which is optional in SAM+PLUS, is required in an SMF that is processed with MAX+PLUS II.

The Compiler automatically compiles SMFs. During compilation, an SMF is first converted into an ADF, which is then converted into a CNF.

An SMF can be used to define all logic in a project,or can be used to define a bottom-level file in a hierarchical project. MAX+PLUS II automatically creates a Symbol File that represents an SMF when you first compile the file or when you choose Create Default Symbol (File menu). This symbol and the logic it represents can be incorporated into a GDF.

You can also use SMF logic in an AHDL TDF by creating a Function Prototype and inserting an instance of the macrofunction into the TDF. You can also automatically generate a default Include File that contains a Function Prototype for an SMF with Create Default Include File (File menu).

1.	This file format is supported for backward compatibility with A+PLUS and SAM+PLUS. You should create all new text-based design files in AHDL.

2.	MAX+PLUS II considers ADFs to be case-insensitive. If you use case-sensitive node and/or pin names in ADFs, you may need to modify your files.

The file icon for each SMF that is part of the current hierarchy tree appears in the Hierarchy Display window.

See also:

Creating a Default Include File

Creating & Using Custom Macrofunctions (AHDL)

Creating the Default Symbol for a File


Compiler Netlist Extractor Module (Compiler)
Compiler Netlist Extractor

The Compiler module that converts each design file in a project (or each cell of an EDIF Input File) into a separate binary CNF. The filename(s) of the CNF(s) are based on the project name. Example

The Compiler Netlist Extractor also creates one or more HIFs that document the hierarchical connections between design files, and graphical Symbol Files (if they have not already been created) that contain symbols which can be used in GDFs.

This module contains a built-in EDIF Netlist Reader, VHDL Netlist Reader, and XNF Netlist Reader and converters that translate ADFs and SMFs for use with MAX+PLUS II. The EDIF Netlist Reader also includes built-in support for the LPM.

During netlist extraction, this module checks each design file for problems such as duplicate node names, missing inputs and outputs, and outputs that are tied together.

If the project has been compiled before, the Compiler Netlist Extractor creates new CNFs and HIFs only for those files that have changed since the last compilation, unless Total Recompile (File menu) is turned on. The CNFs and the HIFs are then passed to the Database Builder module for further processing. In addition, if you have not manually edited the Symbol File for a text-based design file, the Compiler Netlist Extractor automatically updates it to reflect changes to the inputs and outputs in the design file that the symbol represents.

The Compiler Netlist Extractor module also creates the Fitter Input File, a temporary file used during compilation. The Compilation Settings & Times Section of the Report File records the time spent during processing in this module during project compilation.

See also:

Compiler Netlist File (.cnf)

Compiling a Project

Hierarchy Interconnect File (.hif)

Library of Parameterized Modules Support

Symbol File (.sym)

Totally Recompiling a Project


Database Builder Module (Compiler)
Database Builder

The Compiler module that builds a single, fully flattened project database that integrates all the design files in a project hierarchy.

The Database Builder uses the HIFs to link the CNFs that describe the project. Based on the HIF data, the Database Builder copies each CNF into the project database. Each CNF is inserted into the database as many times as it is used within the original hierarchical project. The database thus preserves the electrical connectivity of the project.

The Compiler uses this database for the remainder of project processing. Each subsequent Compiler module updates the database until it contains the fully optimized project. In the beginning, the database contains only the original netlists; at the end, it contains a fully minimized, fitted project, which the Assembler uses to create one or more files for device programming.

As it creates the database, the Database Builder examines the logical completeness and consistency of the project, and checks for boundary connectivity and syntactical errors (e.g., a node without a source or destination). Most errors are detected and can be easily corrected at this stage of project processing.

The Compilation Settings & Times Section of the Report File records the time spent during processing in this module during project compilation.


Logic Synthesizer Module (Compiler)
Logic Synthesizer

The Compiler module that synthesizes the logic in a project’s design files.

Using the database created by the Database Builder, the Logic Synthesizer calculates Boolean equations for each input to a primitive and minimizes the logic according to your specifications.

For projects that use JK or SR flipflops, the Logic Synthesizer checks each case to determine whether a D or T flipflop will implement the project more efficiently. D or T flipflops are substituted where appropriate, and the resulting equations are minimized accordingly.

The Logic Synthesizer also synthesizes equations for flipflops to implement state registers of state machines. An equation for each state bit is optimally implemented with either a D or T flipflop. If no state bit assignments have been made, or if an incomplete set of state bit assignments has been created, the Logic Synthesizer automatically creates a set of state bits to encode the state machine. These encodings are chosen to minimize the resources used.

The Logic Synthesizer then uses a rule-based expert system to group the project requirements for I/O pins, tri-state buffers, and register resources into individual logic cell-sized units. In addition, in device architectures with shareable expander product terms, the numbers of logic cells and expander product terms are balanced to use resources efficiently. As part of the logic minimization and optimization process, logic and nodes in the project may be changed or removed.

Throughout logic synthesis, the Logic Synthesizer detects and reports errors such as illegal combinatorial feedback and tri-state buffer outputs wired together ("wired ORs").

Customizing Logic Synthesis

The Logic Synthesizer allows you to customize two basic types of logic synthesis: multi-level synthesis and standard synthesis. Multi-level synthesis offers up to 20 different individual logic synthesis options. Standard synthesis offers a limited subset of these options. You can use logic synthesis styles to specify combinations of logic options or specify individual logic options. You can apply these styles and logic options to individual logic functions within your project’s design files and to individual devices within a multi-device project. In addition, you can define a default logic synthesis style for the project as a whole.

The Logic Synthesizer provides additional logic synthesis options that are independent of multi-level synthesis and standard synthesis. You can direct the Logic Synthesizer to automatically select global signals for Clock, Clear (or Reset), Preset, and/or Output Enable signals in the project. You can also allow the Logic Synthesizer to automatically place logic in the I/O cell registers of projects that use FLEX 8000, MAX 7000E, or MAX 9000 devices. These options can be specified in the project’s design files and/or with the Global Project Logic Synthesis command (Assign menu).

The Compilation Settings & Times Section of the Report File records the default logic synthesis style and automatic global signals selected for compilation, as well as the time spent during processing in this module.

See also:

Assigning a Logic Option

Defining a Logic Synthesis Style

Design Doctor

GLOBAL Primitive

Specifying Global Project Logic Synthesis Settings


Design Doctor Utility (Compiler)
Design Doctor

The Compiler utility that checks each design file in a project for poor design practices that may cause reliability problems when the project is implemented in one or more devices.

The Design Doctor is activated only if you turn on the Design Doctor command (Processing menu). This utility runs in conjunction with Logic Synthesizer and analyzes the project’s database with a set of design rules. Throughout the analysis, the Design Doctor issues warning messages if the logic violates the currently selected design rules.

The available design rules in the Design Doctor are based on the Project Reliability Guidelines. These rules check for reliable Clock, Preset, and Clear configurations; a master Reset; and potentially unreliable conditions such as expander networks, delay chains, race conditions, and asynchronous inputs.

You can also set up the Design Doctor to check for static hazards before and after logic synthesis. Although logic synthesis may eliminate some logic that produces static hazards, any warnings that are issued after logic synthesis indicate potential reliability problems.

The Design Doctor offers three predefined sets of design rules. The EPLD Rules and FLEX Rules are used to analyze projects that will be implemented in either EPLDs or in FLEX 8000 or FLEX 10Kdef_flex10k devices. The MPLD Rules provides a more stringent set of design rules that are used to analyze projects that will be implemented in MPLDs. You can also customize your own set of design rules that the Design Doctor uses for analysis.

When the Design Doctor command is turned on, the Design Doctor icon appears in the Compiler window under the Logic Synthesizer module box. You can double-click Button 1 on the icon to display a message that summarizes the current status of the Design Doctor analysis. A project that is free of warning messages--based on a specific set of design rules--is given a "clean bill of health."

The Compilation Settings & Times Section of the Report File records the rule set selected for compilation, as well as the time spent during processing in this utility.

See also:

Checking Project Reliability with the Design Doctor

Ensuring Project Reliability


Partitioner Module (Compiler)
Partitioner

The Compiler module that partitions the logic in a project among multiple devices from the same device family. Partitioning occurs if you have created two or more chips in the project’s design files or if the project cannot fit into a single device.

The Partitioner is activated only if you have specified multiple devices or automatic device selection for the project, or if the project does not fit into the specified device(s). This module splits the database updated by the Logic Synthesizer into different parts that correspond to each device. A project is partitioned along logic cell boundaries, with a minimum number of pins used for inter-device communication.

Partitioning can be totally automatic, partially user-specified, or fully user-controlled. You can guide partitioning with clique, chip, and device assignments. You can enter these assignments with the Floorplan Editor or with the Device, Clique, and Pin/Location/Chip commands (Assign menu).

If the project is too large to fit into the devices you specified, the Partitioner creates new chips as necessary. These new chips are of type AUTO. You can control which devices the Partitioner creates with the Auto Device Selection dialog box. You can also reserve a certain percentage of the target device(s) (i.e., save resources for future logic expansion) with the Global Project Device Options command (Assign menu).

The Partitioner can run repeatedly during compilation. The Compilation Settings & Times Section of the Report File records the time spent during processing in this module during project compilation.

See also:

Assigning a Clique

Assigning a Device

Assigning a Pin, Location, or Chip

Specifying Devices for Automatic Device Selection

Partitioning a Project


Fitter Module (Compiler)
Fitter

The Compiler module that fits the logic of a project into one or more devices.

Using the database updated by the Partitioner, the Fitter matches the logic requirements of the project with the available resources of one or more devices. It assigns each logic function to the best logic cell location and selects appropriate interconnection paths and pin assignments.

The Fitter attempts to match any resource assignments made in design files with the resources on the device. If it cannot find a fit, the Fitter allows you to override some or all of your assignments or terminate compilation.

The Fitter module generates a Fit File that documents pin, buried logic cell, chip, clique, and device assignments made by the Fitter module in the last successful compilation. Each time the project compiles successfully, the Fit File is overwritten. You can back-annotate the assignments in the file to preserve them in future compilations.

Regardless of whether a fit is achieved, the Fitter generates a Report File that shows how the project is implemented in one or more devices. You can specify whether to include optional sections in the Report File with the Report File Settings command (Processing menu).

The Fitter can run repeatedly during compilation. The Compilation Settings & Times Section of the Report File records the time spent during processing in this module during project compilation.

See also:

Adjusting the Fit During Compilation

Back-Annotating Assignments for a Project

Fitting & Refitting a Project

Report File Format

Setting Report File Options

Specifying Global Project Security Bit and Reserved Resource Settings


Functional SNF Extractor Module (Compiler)
Functional SNF Extractor

The Compiler module that creates a functional SNF containing the logic information required for functional simulation.

The Functional SNF Extractor is turned on with the Functional SNF Extractor command (Processing menu). It cannot be turned on at the same time as the Timing SNF Extractor.

When you choose to generate a functional SNF, only the Compiler Netlist Extractor, Database Builder, and Functional SNF Extractor modules run, shortening the processing time.

Since the functional SNF is created before logic synthesis, partitioning, and fitting are performed, it includes all nodes in the original design files for the project. (In a timing SNF, some nodes have been synthesized away.) Functional testing is also available with the functional SNF for a single-device project.

When the Functional SNF Extractor is turned on, the only commands available on the Interfaces and Processing menus are EDIF Netlist Reader Settings, Smart Recompile, and Total Recompile.

See also:

Creating a Functional Simulator Netlist File

Functional Simulation Mode (Simulator)

Simulator Netlist File (.snf)


Timing SNF Extractor Module (Compiler)
Timing SNF Extractor

The Compiler module that creates a timing SNF containing the logic and timing information required for timing simulation, delay prediction, and timing analysis.

The Timing SNF Extractor is turned on with the Timing SNF Extractor command (Processing menu). It is also turned on automatically when you turn on the EDIF Netlist Writer command (Interfaces menu). The Timing SNF Extractor cannot be turned on at the same time as the Functional SNF Extractor.

A timing SNF describes the fully optimized circuit after all logic synthesis and fitting have been completed. Regardless of whether a project is partitioned into multiple devices, the timing SNF describes a project as a whole. Therefore, timing simulation and timing analysis (including delay prediction) are available only for the project as a whole. Neither timing simulation nor functional testing is available for individual devices in a multi-device project. Functional testing is available only for a single-device project.

A timing SNF is not created until a project compiles without any errors. The Timing SNF Extractor can run repeatedly during compilation. The Compilation Settings & Times Section of the Report File records the time spent during processing in this module during project compilation.

See also:

Creating a Timing Simulator Netlist File

Running a Timing Analysis

Simulator Netlist File (.snf)

Timing Simulation Mode (Simulator)


Linked SNF Extractor Module (Compiler)
Linked SNF Extractor

The Compiler module that creates a linked SNF containing timing and/or functional information for several projects.

The Linked SNF Extractor is turned on with the Linked SNF Extractor command (Processing menu). It cannot be turned on at the same time as the  Timing SNF Extractor or the Functional SNF Extractor.

A linked SNF is created by compiling a super-project that consists of a top-level design file that contains symbols or instances representing multiple individual projects. These symbols or instances represent existing functional, timing, or linked SNFs for each sub-project, not actual design files.

If the Linked SNF Extractor is turned on when you compile a super-project, the Compiler creates a linked SNF that combines the timing and/or functional information for each project, allowing you to perform a board-level simulation. If a linked SNF contains timing information only, you can also use it to run a timing analysis.

A linked SNF contains all the information in each sub-project’s SNF, i.e., data from functional,  timing, and linked SNFs. A super-project can also be used as a sub-project in another super-project. A linked SNF cannot be created until all sub-projects compile without any errors.

The sub-projects can be targeted for different device families. If the Linked SNF Extractor is turned on, the Compiler effectively ignores the device family for the super-project.

When you choose to generate a linked SNF, only the Compiler Netlist Extractor, Database Builder, and Linked SNF Extractor modules run, shortening the processing time.

When the Linked SNF Extractor is turned on, the only commands available on the Interfaces and Processing menus are EDIF Netlist Reader Settings, Smart Recompile, and Total Recompile.

The Compilation Settings & Times Section of the Report File shows whether the Linked SNF Extractor was turned on or off during project compilation.

See also:

Combining Multiple Projects for Simulation

File Structure Requirements for Multi-Project Simulation

Linked Simulation Mode (Simulator)

Simulator Netlist File (.snf)


EDIF Netlist Writer Module
EDIF Netlist Writer

The Compiler module that creates one or more EDIF Output Files. It can also generate one or more optional SDF Output Files.

EDIF Output Files contain the logic and timing information for the optimized project and can be used with industry-standard simulators. An EDIF Output File is generated for each device in a project.

You can turn on the EDIF Netlist Writer with the EDIF Netlist Writer command (Interfaces menu). This command also turns on the Timing SNF Extractor. You can choose EDIF Netlist Writer Settings (Interfaces menu) to specify the configuration options the EDIF Netlist Writer uses to generate EDIF Output Files and optional SDF Output Files.

The EDIF Netlist Writer can run repeatedly during compilation. It does not create EDIF Output Files or SDF Output Files until the project compiles without any errors.

The Compilation Settings & Times Section of the Report File records the time spent during processing in this module during project compilation.

See also:

Creating EDIF Output Files


Verilog Netlist Writer Module
Verilog Netlist Writer

The Compiler module that creates one or more Verilog Output Files. It can also generate one or more optional SDF Output Files.

You can turn on the Verilog Netlist Writer module with the Verilog Netlist Writer command (Interfaces menu). You can choose Verilog Netlist Writer Settings (Interfaces menu) to specify the configuration options the Verilog Netlist Writer uses to generate Verilog Output Files and optional SDF Output Files.

The Verilog Netlist Writer can run repeatedly during compilation. It does not create Verilog Output Files or SDF Output Files until the project compiles without any errors.

The Compilation Settings & Times Section of the Report File records the time spent during processing in this module during project compilation.

See also:

Creating Verilog Output Files


VHDL Netlist Writer Module
VHDL Netlist Writer

The Compiler module that creates one or more VHDL Output Files. It can also generate one or more optional SDF Output Files.

You can turn on the VHDL Netlist Writer module with the VHDL Netlist Writer command (Interfaces menu). You can choose VHDL Netlist Writer Settings (Interfaces menu) to specify the configuration options the VHDL Netlist Writer uses to generate VHDL Output Files and optional SDF Output Files.

The VHDL Netlist Writer can run repeatedly during compilation. It does not create VHDL Output Files or SDF Output Files until the project compiles without any errors.

The Compilation Settings & Times Section of the Report File records the time spent during processing in this module during project compilation.

See also:

Creating VHDL Output Files


Assembler Module (Compiler)
Assembler

The Compiler module that creates one or more programming files for programming the device(s) for a project.

The Assembler module completes project processing by converting the Fitter’s device, logic cell, and pin assignments into a programming image for the device(s), in the form of one or more POFs, SOFs, and/or JEDEC Files. POFs and JEDEC Files are always generated; SOFs are also generated if the project uses FLEX 8000 devices. After compilation, you can also use SOFs to create different types of files for configuring FLEX 8000 devices with Combine Programming Files (File menu).

The programming files can then be processed by the MAX+PLUS II Programmer and the MPU hardware to produce working devices. Several other programming hardware manufacturers also provide programming support for Altera devices.

The Assembler can run repeatedly during compilation to generate each programming file. Programming files are not created until a project compiles without errors. The Compilation Settings & Times Section of the Report File records the time spent during processing in this module during project compilation.

See also:

Combining & Converting SRAM Object Files

Configuring a FLEX 8000 Device with the FLEX Download Cable

Programming a Device


Compiler Netlist File (.cnf) Description (Compiler)
Compiler Netlist File (.cnf)

A binary file (with the extension .cnf) that contains the logic and connectivity data for a design file.

The Compiler Netlist Extractor generates a CNF for each design file in a MAX+PLUS II project. The filename(s) of the CNF(s) are based on the project name. Example

You can double-click Button 1 on the CNF icon in the Compiler window to open the top-level design file for the current project.

See also:

Compiling a Project

Totally Recompiling a Project


Example:CMP-Assigned Name for the EDIF Output File
If multiple Compiler Netlist Files are generated, they are uniquely identified by a sequence number appended to the project name, e.g., if the project name is proj, the first file is proj.cnf, the second is proj(1).edo, the third is proj(2).cnf, etc.

If you’re using MAX+PLUS II on a PC and the project name has more than 8 characters, MAX+PLUS II will truncate the filename if necessary to include the numerical index characters and maintain the 8-character filename length. MAX+PLUS II creates a maxplus2.idx file that maps the original filenames to the 8-character filenames. If you use a project name with 8 characters or less, the numerical index characters are appended to it.


Hierarchy Interconnect File (.hif) Description
Hierarchy Interconnect File (.hif)

A file (with the extension .hif) that records the hierarchical connections between the design files of a project.

The Compiler Netlist Extractor generates an HIF for each design file in a project.

You should never edit the HIF.

See also:

Compiling a Project

Totally Recompiling a Project


File Icons (Compiler)
File Icons

Represent design files and ancillary files used and generated by the Compiler. Show me

File icons representing the Compiler Netlist File, Report File, Simulator Netlist File, EDIF Output File, Verilog Output File, VHDL Output File, Programmer Object File, SRAM Object File, and JEDEC File appear underneath the module boxes for the modules that generate them during project compilation.

Double-clicking Button 1 on a file icon yields the following results:

Icon:	Action:

Opens the top-level design file of the project in the appropriate Graphic, Text, or Waveform Editor window.

Opens the Report File in a Text Editor window.

Loads the functional SNF or timing SNF and opens the Simulator window.

Opens the EDIF Output File in a Text Editor window.

Opens the Verilog Output File in a Text Editor window.

Opens the VHDL Output File in a Text Editor window.

Opens the Verilog Output File plus other output file(s) in multiple Text Editor windows. The other output files are an EDIF Output File and/or a VHDL Output File, depending on the modules that were turned on during compilation.

Opens the VHDL Output File plus other output file(s) in multiple Text Editor windows. The other output files are an EDIF Output File and/or a Verilog Output File, depending on the modules that were turned on during compilation.

Loads the POF and opens the Programmer window.

Loads the POF and opens the Programmer window.

Loads the POF and opens the Programmer window.


Hourglass (Compiler)
Hourglass

Shows that the Compiler is processing a project. Show me

Sand trickles down through the hourglass and it flips over and starts again while a project is being compiled.


Module Boxes (Compiler)
Module Boxes

Change color to show when a project is being processed by a particular module during compilation. After a module has successfully finished processing, a file icon may appear underneath it. Show me

The Compiler includes the following modules:

Compiler Netlist Extractor

Database Builder

Logic Synthesizer

Partitioner

Fitter

Functional SNF Extractor

Timing SNF Extractor

Linked SNF Extractor

EDIF Netlist Writer

Verilog Netlist Writer

VHDL Netlist Writer

Assembler

See also:

Design Doctor


Progress Bar (Compiler)
Progress Bar

Shows how much of the current compilation has been completed. Show me

After you choose the Start button or the Project Save & Compile command, the progress bar changes color to show how much of the compilation has been completed. When the progress bar reaches 100%, the compilation is finished. You may then compile another project.

If the compilation is unsuccessful, the progress bar stops changing color, and a Message Processor window that lists all error and warning messages is displayed.


Compiler Index
Compiler Help Contents

Introduction

Basic Tools

Commands

Procedures

Golden Rules

Shortcuts

Messages

Glossary


Compiler--Context-Sensitive Help
Compiler Context-Sensitive Help

Context-sensitive help is provided for all Compiler commands, dialog boxes, and messages, and the following basic tools:

Buttons

Start

Stop

Stop/Show Status

Input & Output Files

Compiler Netlist File (.cnf)

EDIF Output File (.edo)

Fit File (.fit)

Programmer Object File (.pof)

Report File (.rpt)

Simulator Netlist File (.snf)

Verilog Output File (.vo)

VHDL Output File (.vho)

Modules & Utilities

Compiler Netlist Extractor

Database Builder

Logic Synthesizer

Design Doctor

Partitioner

Fitter

Functional SNF Extractor

Timing SNF Extractor

EDIF Netlist Writer

Verilog Netlist Writer

VHDL Netlist Writer

Assembler

Widgets

Hourglass

Progress Bar

For information on other basic tools, see Compiler Basic Tools.

See also:

Getting Context-Sensitive Help


Compiler Introduction
Introduction

The MAX+PLUS II Compiler is a highly automated design processor that transforms design files into output files for device programming, simulation, and timing analysis. More than a simple design processor, the Compiler is the heart of the MAX+PLUS II development system. Show me

The Compiler links the design entry and auxiliary applications--the Graphic, Text, Waveform, Symbol, and Floorplan Editors--to post-processing applications such as the Timing Analyzer, Simulator, and Programmer. You can also compile design files created with other industry-standard CAE tools that generate EDIF files, VHDL files, OrCAD Schematic Files, TDFs, and XNF Files. Operating in tandem with the MAX+PLUS II Message Processor, the Compiler allows you to interactively locate and correct design file errors as they are detected during project compilation.

How Does the Compiler Work?

When you start the Compiler, it begins a series of processes that ultimately creates one or more programming files. While the Compiler can compile a project with minimal assistance, it also allows you to customize processing for a particular project. The Compiler gives you the freedom to experiment with a variety of processing options.

The Compiler first extracts information that defines the hierarchical connections between design files, then checks the overall project for errors. After it creates an organizational map of your project, it combines all design files into a fully flattened database for fast and efficient processing.

The Compiler applies a range of techniques to increase the efficiency of your project and minimize device resource usage. The optional Design Doctor utility checks project logic reliability both before and after logic synthesis.

If a project is too large to fit into a single device, the Compiler partitions it among multiple devices from the same device family, either automatically or according to your specifications. The Fitter generates a customizable Report File that details resource usage and describes how the project will be implemented in one or more device(s). You can also configure the Compiler to generate a variety of output files, including netlist files for timing simulation, functional simulation, multi-project simulation, and timing analysis; Text Design Output Files; and EDIF, Verilog, and VHDL files for third-party simulators.

Finally, the Compiler generates one or more files for device programming. You can open output files or start post-processing applications by simply double-clicking Button 1 on the output file icons that appear in the Compiler window.

Where to Start

Altera offers a variety of information to help you compile projects with the MAX+PLUS II Compiler:

On-Line Help

On-line help supplies complete reference and how-to information on using the MAX+PLUS II Compiler.

Compiler Help Contents provides access to all on-line Compiler Help.

Compiler Golden Rules summarizes essential rules and guidelines for using the Compiler.

Recommended Reading

Additional Altera publications help you understand MAX+PLUS II and the Compiler. The following application notes and briefs are relevant to using the Compiler.

AB60 (Estimating a Design Fit)

AB77 (Fitting Complex Designs in MAX 5000 EPLDs)

AB93 (Partitioning a Project with MAX+PLUS II Software)

See also:

How to Use MAX+PLUS II Help

Third-Party Interfaces Introduction


Compiler Golden Rules
Golden Rules

The following golden rules will help you use the Compiler effectively:

To obtain a new fit for your project that is not based on the user-defined resource and device assignments in the design files, turn off all checkboxes in the Ignore Project Assignments dialog box and recompile your project.

For a faster editing and simulation cycles, turn on Functional SNF Extractor to generate only a functional SNF. When this command is turned on, only the Compiler Netlist Extractor, Database Builder, and Functional SNF Extractor modules are used to process your project. The project is not synthesized or fitted, and programming file(s) are not generated.

For faster editing near the end of a design cycle (e.g., when you are adjusting only the pin, location, and device assignments for a project), turn on Smart Recompile to generate extra database files that accelerate future compilations. The Compiler can then skip any modules that are not required.

To redisplay all Compiler Netlist Extractor warning messages from previous compilations, turn on Total Recompile before recompiling your project.

Double-click Button 1 on the output file icons that appear after compilation to automatically open output files or post-processing applications.

Use the Design Doctor to check the reliability of your project logic during compilation. Follow Project Reliability Guidelines to create reliable projects.

The Altera-provided default logic synthesis styles have different settings for different device families to ensure that each architecture is used most efficiently. When you use an Altera-provided style, the settings for that style will change when you change the device family. After changing the device family, check the new style settings to ensure that they conform to your needs.

Don’t edit a Fit File or copy it into the ACF for the project. If you wish to edit the assignments for a project, first back-annotate the assignments with Back-Annotate Project and edit them with the Assign menu commands or the Floorplan Editor.

General MAX+PLUS II Golden Rules

When you start work on a new design file, name is as the current project with Project Name right away so that you can compile it easily. You can always change the project name later.

Use the built-in hierarchy traversal features in MAX+PLUS II to move between design files for the current hierarchy. To open a lower-level file in a hierarchy, open the top-level file and then use the Hierarchy Display window or Hierarchy Down to open the lower-level files. If you choose Open or Retrieve to open a lower-level file, it is considered to be the top of a different hierarchy tree, and resource, device, and probe assignments that you enter are saved only for that hierarchy, not for the project.

When you create an ancillary file for a project, the icon for the file will appear in the Hierarchy Display if you use the same filename as the project.

Don’t edit any MAX+PLUS II system files, including HIFs, maxplus2.idx files, or the maxplus2.ini file.

Use the Save As command if you wish to rename a design file or an ancillary file. Don’t rename design files from outside of MAX+PLUS II system (e.g., from DOS or with the Windows File Manager).

When you have completed a project, use Project Archive to ensure that you save a complete backup copy of all project files that will not be affected by future edits or deletions.


Compiler Shortcuts
Shortcuts

The following list provides shortcuts for Compiler commands:

Command:	Shortcut:

Context-Sensitive Help	Shift+F1 or

Cascade	Shift+F5

Close	Alt+F4

Compiler

Exit MAX+PLUS II	Alt+F4 or double-click Button 1 on the Application Control Menu box

Floorplan Editor

Hierarchy Display

Hierarchy Project Top	Ctrl+T or double-click Button 1 on the CNF file icon or

New

Next	Ctrl+F6

Open	Ctrl+O or double-click Button 1 on the FIT, RPT, EDO, VO, VHO, VO+..., or VHO+... icon to open the corresponding file(s) or

Programmer	Double-click Button 1 on the POF, POF/SOF, or POF/JED icon or

Project Name	Ctrl+J or

Project Save & Compile	Ctrl+L or

Project Save & Simulate	Ctrl+Shift+L or

Simulator	Double-click Button 1 on the SNF icon or

Switch To	Ctrl+Esc

Timing Analyzer

Tile	Shift+F4

See also:

Guidelines for Workstation Help Users

Selecting Text

Showing the Toolbar


-----BEGINNING OF NON-TRANSLATED TEXT-----

11/30/93: Note to Adrienne: the annotated file popups for the flex 8000 device options need to be updated with the edits I gave you for those popups in compcom.

11/30/93: The following annotated file popups do not appear to be used (i.e., searching for them in the file yielded no result):

co_files_rpt_respinreq

co_files_rpt_lcnumber

co_files_rpt_labname

co_files_rpt_interconlc

co_files_rpt_interconpin

co_files_rpt_interconsym

co_files_rpt_intername

co_files_rpt_pininput

co_files_rpt_115

co_files_rpt_116

co_files_rpt_117

co_files_rpt_118

co_files_rpt_119

co_files_rpt_120

11/30/93: Annotated file popups need to be checked against panels to be sure that they are up to date. A panel may have been edited but the corresponding popup may not have gotten edited:

----END OF NON-TRANSLATED TEXT-----


Annotated Report File: Classic, MAX 5000, & MAX 7000 Devices
Annotated Report File: Classic, MAX 5000 & MAX 7000 Devices

Project Information                                    d:\rptfile\maxproj.rpt

MAX+plus II Compiler Report File

Version 5.0

Compiled: 08/01/94 15:16:33

***** Project compilation was successful

Title: DESIGN NAME

Company: Altera

Designer: Joe Engineer

Rev: A

Date: 9:50a 07-15-1994

** DEVICE SUMMARY **

Chip/                     Input   Output   Bidir         Shareable

POF       Device          Pins    Pins     Pins    LCs   Expanders  % Utilized

MAXPROJ   EPM7096          6        13       0      35      26          36 %

User Pins:                 6        13       0

Project Information                                    d:\rptfile\maxproj.rpt

** PROJECT COMPILATION MESSAGES **

Warning: Ignored unnecessary INPUT pin 'unused2'

Warning: Ignored unnecessary INPUT pin 'unused1'

Project Information                                    d:\rptfile\maxproj.rpt

** MULTIPLE PIN CONNECTIONS **

For node name 'out1'

For node name 'in1'

Connect: {MAXPROJ@48, MAXPROJ@15}

Project Information                                    d:\rptfile\maxproj.rpt

** PIN/LOCATION/CHIP ASSIGNMENTS **

                  Actual

    User       Assignments

Assignments   (if different)      Node Name

MAXPROJ@84                        CLOCK

MAXPROJ@75                        cmpen

MAXPROJ@LC85                      |control5:75|Q0~2

MAXPROJ@LC78                      |control5:75|Q0

MAXPROJ@LC79                      |control5:75|Q1

MAXPROJ@LC73   MAXPROJ@LC77       |control5:75|Q2~2

MAXPROJ@LC77   MAXPROJ@LC73       |control5:75|Q2

MAXPROJ@LC70                      |dice_gen:79|DIEA0

MAXPROJ@LC80                      |dice_gen:79|DIEA1

MAXPROJ@LC66                      |dice_gen:79|DIEA2

MAXPROJ@LC68                      |dice_gen:79|DIEB0

MAXPROJ@LC74                      |dice_gen:79|DIEB1

MAXPROJ@LC76                      |dice_gen:79|DIEB2

MAXPROJ@LC94                      |dice_gen:79|74374:23|:13

MAXPROJ@LC93                      |dice_gen:79|74374:23|:14

MAXPROJ@LC91                      |dice_gen:79|74374:23|:15

MAXPROJ@LC95                      |dice_gen:79|74374:23|:16

MAXPROJ@62                        D1_1_7

MAXPROJ@57                        D1_2_6

MAXPROJ@71                        D1_3_5

MAXPROJ@70                        D1_4

MAXPROJ@69                        D2_1_7

MAXPROJ@60                        D2_2_6

MAXPROJ@45                        D2_3_5

MAXPROJ@44                        D2_4

MAXPROJ@LC87                      |eval_box:74|POINT

MAXPROJ@LC90                      |eval_box:74|8faddb:45|SUM1

MAXPROJ@LC92                      |eval_box:74|8faddb:45|SUM2

MAXPROJ@LC96                      |eval_box:74|8faddb:45|SUM3

MAXPROJ@LC82                      |eval_box:74|8faddb:45|SUM4

MAXPROJ@15                        in1

MAXPROJ@74                        LOSER

MAXPROJ@48                        out1

MAXPROJ@16                        RESET

MAXPROJ@58                        Reset_out

MAXPROJ@2                         ROLL_1

MAXPROJ@1                         ROLL_2

MAXPROJ@83                        SAMPLE

MAXPROJ@LC71                      |sync3:78|Debounce~1

MAXPROJ@LC75                      |sync3:78|Debounce~2

MAXPROJ@73                        WINNER

Project Information                                    d:\rptfile\maxproj.rpt

** CLIQUE ASSIGNMENTS **

CLIQUE "fast1"  placed in chip "MAXPROJ", LAB F

    |eval_box:74|POINT

    |eval_box:74|8faddb:45|SUM3

    |eval_box:74|8faddb:45|SUM4

    |eval_box:74|8faddb:45|SUM1

    |eval_box:74|8faddb:45|SUM2

** PROBE ASSIGNMENTS **

Probe Name                       Primitive/Macrofunction

DIE_B1                           |dsamp2:69|7404:60|:34.Q

DIE_B2                           |dsamp2:69|7404:60|:35.Q

DIE_B3                           |dsamp2:69|7404:60|:36.Q

POINT                            |sync3:78|:47.OUT

Project Information                                    d:\rptfile\maxproj.rpt

** STATE MACHINE ASSIGNMENTS **

|control5:75|Control: MACHINE

        OF BITS (

           |control5:75|Q2,

           |control5:75|Q1,

           |control5:75|Q0

        ) WITH STATES (

                  WAIT_ROLL = B"000",

                 CHECK_ROLL = B"010",

                 WAIT_POINT = B"100",

                CHECK_POINT = B"011",

                       LOST = B"001",

                        WON = B"101"

);

|sync3:78|Debounce: MACHINE

        OF BITS (

           |sync3:78|Debounce~2,

           |sync3:78|Debounce~1

        )

        WITH STATES (

                       Wait = B"00",

                    Rolling = B"10",

                       Done = B"01"

);

Project Information                                    d:\rptfile\maxproj.rpt

** FILE HIERARCHY **

|control5:75|

|dice_gen:79|

|dice_gen:79|74163:39|

|dice_gen:79|74163:38|

|dice_gen:79|74374:23|

|dice_gen:79|8fadd:28|

|eval_box:74|

|eval_box:74|7485ns:43|

|eval_box:74|8faddb:45|

|eval_box:74|encode2:46|

|sync3:78|

|dsamp2:69|

|dsamp2:69|7404:60|

|dsamp2:68|

|dsamp2:68|7404:60|

Device-Specific Information:                         d:\rptfile\maxproj.rpt

MAXPROJ

***** Logic for device 'MAXPROJ' compiled without errors.

Device: EPM7096

Turbo: ON

Security: OFF

Pin-Out Diagram

                R  R  R  R        R  R                    R  R        R  R

                E  E  E  E        E  E                    E  E        E  E

                S  S  S  S        S  S     R  R     S     S  S        S  S

                E  E  E  E        E  E     O  O  C  A     E  E        E  E  c

                R  R  R  R     N  R  R     L  L  L  M     R  R  N     R  R  m

                V  V  V  V  G  .  V  V  V  L  L  O  P  G  V  V  .  V  V  V  p

                E  E  E  E  N  C  E  E  C  _  _  C  L  N  E  E  C  C  E  E  e

                D  D  D  D  D  .  D  D  C  1  2  K  E  D  D  D  .  C  D  D  n

              -----------------------------------------------------------------_

            /  11 10  9  8  7  6  5  4  3  2  1 84 83 82 81 80 79 78 77 76 75   |

  RESERVED | 12                                                              74 | LOSER

       VCC | 13                                                              73 | WINNER

  RESERVED | 14                                                              72 | GND

       in1 | 15                                                              71 | D1_3_5

     RESET | 16                                                              70 | D1_4

  RESERVED | 17                                                              69 | D2_1_7

  RESERVED | 18                                                              68 | RESERVED

       GND | 19                                                              67 | RESERVED

  RESERVED | 20                                                              66 | VCC

  RESERVED | 21                                                              65 | RESERVED

  RESERVED | 22                           EPM7096                            64 | RESERVED

  RESERVED | 23                                                              63 | RESERVED

  RESERVED | 24                                                              62 | D1_1_7

  RESERVED | 25                                                              61 | RESERVED

       VCC | 26                                                              60 | D2_2_6

  RESERVED | 27                                                              59 | GND

  RESERVED | 28                                                              58 | Reset_out

  RESERVED | 29                                                              57 | D1_2_6

  RESERVED | 30                                                              56 | RESERVED

  RESERVED | 31                                                              55 | RESERVED

       GND | 32                                                              54 | RESERVED

           |_  33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53  _|

             ------------------------------------------------------------------

                R  R  R  R  R  V  N  R  R  G  V  D  D  N  G  o  R  R  R  R  V

                E  E  E  E  E  C  .  E  E  N  C  2  2  .  N  u  E  E  E  E  C

                S  S  S  S  S  C  C  S  S  D  C  _  _  C  D  t  S  S  S  S  C

                E  E  E  E  E     .  E  E        4  3  .     1  E  E  E  E

                R  R  R  R  R        R  R           _           R  R  R  R

                V  V  V  V  V        V  V           5           V  V  V  V

                E  E  E  E  E        E  E                       E  E  E  E

                D  D  D  D  D        D  D                       D  D  D  D

N.C. = Not Connected.

VCC = Dedicated power pin, which MUST be connected to VCC.

GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.

RESERVED = Unused I/O pin, which MUST be left unconnected.

Device-Specific Information:                             d:\rptfile\maxproj.rpt

MAXPROJ

** RESOURCE USAGE **

                                               Shareable    External

Logic Array Block    Logic Cells   I/O Pins    Expanders    Interconnect

A:     LC1 - LC16     0/16(  0%)   2/10( 20%)   0/16(  0%)   0/36(  0%)

B:    LC17 - LC32     0/16(  0%)   0/10(  0%)   0/16(  0%)   0/36(  0%)

C:    LC33 - LC48     0/16(  0%)   0/10(  0%)   0/16(  0%)   0/36(  0%)

D:    LC49 - LC64     3/16( 18%)   3/10( 30%)   2/16( 12%)   7/36( 19%)

E:    LC65 - LC80    16/16(100%)   4/10( 40%)  16/16(100%)  22/36( 61%)

F:    LC81 - LC96    16/16(100%)   6/10( 60%)  13/16( 81%)  21/36( 58%)

Total dedicated input pins used:                 4/   4 (100%)

Total I/O pins used:                            15/  60 ( 25%)

Total logic cells used:                         35/  96 ( 36%)

Total shareable expanders used:                 26/  96 ( 27%)

Total Turbo logic cells used:                   35/  96 ( 36%)

Total shareable expanders not available (n/a):   5/  96 (  5%)

Total input pins required:                       6

Total output pins required:                     13

Total bidirectional pins required:               0

Total logic cells required:                     35

Total flipflops required:                       15

Total shareable expanders in database:          26

Synthesized logic cells:                         2/  96 (  2%)

Device-Specific Information:                             d:\rptfile\maxproj.rpt

MAXPROJ

** INPUTS **

                                     Shareable

                                     Expanders      Fan-In    Fan-Out

 Pin     LC  LAB  Primitive       Total Shared n/a INP  FBK  OUT  FBK  Name

  84      -   -       INPUT         0      0   0    0    0    0   11   CLOCK

  15    (3)  (A)      INPUT         0      0   0    0    0    0    1   in1

  16    (1)  (A)      INPUT         0      0   0    0    0    0    7   RESET

   2      -   -       INPUT         0      0   0    0    0    0    5   ROLL_1

   1      -   -       INPUT         0      0   0    0    0    0    5   ROLL_2

  83      -   -       INPUT         0      0   0    0    0    0    8   SAMPLE

s = Synthesized pin or logic cell

t = Turbo logic cell

+ = Synchronous flipflop

! = NOT gate push-back

r = Fitter-inserted logic cell

Device-Specific Information:                             d:\rptfile\maxproj.rpt

MAXPROJ

** OUTPUTS **

                                     Shareable

                                     Expanders     Fan-In   Fan-Out

 Pin     LC  LAB  Primitive      Total Shared n/a INP  FBK  OUT  FBK   Name

  75     89    F     OUTPUT   t     0      0   0    0    3   0    0    cmpen

  62     72    E     OUTPUT   t     0      0   0    1    4   0    1    D1_1_7 (|dsamp2:68|:55)

  57     65    E     OUTPUT   t     0      0   0    1    4   0    1    D1_2_6 (|dsamp2:68|:54)

  71     84    F     OUTPUT   t     1      0   0    1    4   0    1    D1_3_5 (|dsamp2:68|:53)

  70     83    F     OUTPUT   t     1      0   0    1    4   0    1    D1_4 (|dsamp2:68|:56)

  69     81    F     OUTPUT   t     0      0   0    1    4   0    1    D2_1_7 (|dsamp2:69|:55)

  60     69    E     OUTPUT   t     0      0   0    1    4   0    1    D2_2_6 (|dsamp2:69|:54)

  45     51    D     OUTPUT   t     1      0   0    1    4   0    1    D2_3_5 (|dsamp2:69|:53)

  44     49    D     OUTPUT   t     1      0   0    1    4   0    1    D2_4 (|dsamp2:69|:56)

  74     88    F     OUTPUT   t     0      0   0    0    3   0    0    LOSER

  48     53    D     OUTPUT   t     0      0   0    1    0   0    0    out1

  58     67    E     OUTPUT   t     0      0   0    1    0   0    0    Reset_out

  73     86    F     OUTPUT   t     0      0   0    0    3   0    0    WINNER

s = Synthesized pin or logic cell

t = Turbo logic cell

+ = Synchronous flipflop

! = NOT gate push-back

r = Fitter-inserted logic cell

Device-Specific Information:                             d:\rptfile\maxproj.rpt

MAXPROJ

** BURIED LOGIC **

                                     Shareable

                                     Expanders     Fan-In    Fan-Out

 Pin     LC  LAB  Primitive      Total Shared n/a INP  FBK  OUT  FBK   Name

   -     85    F       SOFT s t     1      0   1    0    9    0    1    |control5:75|Q0~2

   -     78    E       DFFE   t     9      0   0    2   13    0   13    |control5:75|Q0

   -     79    E       DFFE   t     0      0   0    2    4    0   13    |control5:75|Q1

 (67)    77    E       SOFT s t     1      0   1    1   11    0    1    |control5:75|Q2~2

 (63)    73    E       DFFE   t     6      0   1    2   10    0   12    |control5:75|Q2

 (61)    70    E       TFFE   t     0      0   0    2    0    0   18    |dice_gen:79|DIEA0 (|dice_gen:79|74163:39|:34)

 (68)    80    E       TFFE   t     0      0   0    2    3    0   16    |dice_gen:79|DIEA1 (|dice_gen:79|74163:39|:35)

   -     66    E       TFFE   t     0      0   0    2    3    0   14    |dice_gen:79|DIEA2 (|dice_gen:79|74163:39|:36)

   -     68    E       TFFE   t     0      0   0    2    0    0   18    |dice_gen:79|DIEB0 (|dice_gen:79|74163:38|:34)

   -     74    E       TFFE   t     0      0   0    2    3    0   16    |dice_gen:79|DIEB1 (|dice_gen:79|74163:38|:35)

 (65)    76    E       TFFE   t     0      0   0    2    3    0   14    |dice_gen:79|DIEB2 (|dice_gen:79|74163:38|:36)

 (80)    94    F       DFFE   t     0      0   0    0    5    0    1    |dice_gen:79|74374:23|:13

   -     93    F       DFFE   t     3      1   1    0    7    0    1    |dice_gen:79|74374:23|:14

 (76)    91    F       DFFE   t     3      3   0    0    9    0    1    |dice_gen:79|74374:23|:15

   -     95    F       DFFE   t     2      2   0    0    9    0    1    |dice_gen:79|74374:23|:16

   -     87    F      LCELL   t     5      0   1    0   11    0    1    |eval_box:74|POINT (|eval_box:74|:47)

   -     90    F       SOFT   t     0      0   0    0    2    0    1    |eval_box:74|8faddb:45|SUM1 (|eval_box:74|8faddb:45|:137)

 (77)    92    F       SOFT   t     0      0   0    0    4    0    1    |eval_box:74|8faddb:45|SUM2 (|eval_box:74|8faddb:45|:136)

 (81)    96    F       SOFT   t     3      3   0    0    6    0    1    |eval_box:74|8faddb:45|SUM3 (|eval_box:74|8faddb:45|:135)

   -     82    F       SOFT   t     2      2   0    0    6    0    1    |eval_box:74|8faddb:45|SUM4 (|eval_box:74|8faddb:45|:134)

   -     71    E       DFFE   t     0      0   0    4    2    0    5    |sync3:78|Debounce~1

 (64)    75    E       DFFE   t     0      0   0    4    2    0    5    |sync3:78|Debounce~2

s = Synthesized pin or logic cell

t = Turbo logic cell

+ = Synchronous flipflop

! = NOT gate push-back

r = Fitter-inserted logic cell

Device-Specific Information:                             d:\rptfile\maxproj.rpt

MAXPROJ

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'D':

        +----- LC51 D2_3_5

        | +--- LC49 D2_4

        | | +- LC53 out1

        | | |

LC      | | | | A B C D E F | Name

LC51 -> * - - | - - - * - - | D2_3_5

LC49 -> - * - | - - - * - - | D2_4

Pin

84   -> - - - | - - - - * - | CLOCK

15   -> - - * | - - - * - - | in1

2    -> - - - | - - - - * - | ROLL_1

1    -> - - - | - - - - * - | ROLL_2

83   -> * * - | - - - * * * | SAMPLE

LC68 -> * * - | - - - * * * | |dice_gen:79|DIEB0

LC74 -> * * - | - - - * * * | |dice_gen:79|DIEB1

LC76 -> * * - | - - - * * * | |dice_gen:79|DIEB2

* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.

- = The logic cell or pin is not an input to the logic cell (or LAB).

Device-Specific Information:                             d:\rptfile\maxproj.rpt

MAXPROJ

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'E':

        +------------------------------- LC78 |control5:75|Q0

        | +----------------------------- LC79 |control5:75|Q1

        | | +--------------------------- LC77 |control5:75|Q2~2

        | | | +------------------------- LC73 |control5:75|Q2

        | | | | +----------------------- LC70 |dice_gen:79|DIEA0

        | | | | | +--------------------- LC80 |dice_gen:79|DIEA1

        | | | | | | +------------------- LC66 |dice_gen:79|DIEA2

        | | | | | | | +----------------- LC68 |dice_gen:79|DIEB0

        | | | | | | | | +--------------- LC74 |dice_gen:79|DIEB1

        | | | | | | | | | +------------- LC76 |dice_gen:79|DIEB2

        | | | | | | | | | | +----------- LC72 D1_1_7

        | | | | | | | | | | | +--------- LC65 D1_2_6

        | | | | | | | | | | | | +------- LC69 D2_2_6

        | | | | | | | | | | | | | +----- LC67 Reset_out

        | | | | | | | | | | | | | | +--- LC71 |sync3:78|Debounce~1

        | | | | | | | | | | | | | | | +- LC75 |sync3:78|Debounce~2

        | | | | | | | | | | | | | | | |

LC      | | | | | | | | | | | | | | | | | A B C D E F | Name

LC78 -> * * * * - - - - - - - - - - - - | - - - - * * | |control5:75|Q0

LC79 -> * * * * - - - - - - - - - - - - | - - - - * * | |control5:75|Q1

LC77 -> - - - * - - - - - - - - - - - - | - - - - * - | |control5:75|Q2~2

LC73 -> * - * * - - - - - - - - - - - - | - - - - * * | |control5:75|Q2

LC70 -> * - * * * * * - - - * * - - - - | - - - - * * | |dice_gen:79|DIEA0

LC80 -> * - * * - * * - - - * * - - - - | - - - - * * | |dice_gen:79|DIEA1

LC66 -> * - * * - * * - - - * * - - - - | - - - - * * | |dice_gen:79|DIEA2

LC68 -> * - * * - - - * * * - - * - - - | - - - * * * | |dice_gen:79|DIEB0

LC74 -> * - * * - - - - * * - - * - - - | - - - * * * | |dice_gen:79|DIEB1

LC76 -> * - * * - - - - * * - - * - - - | - - - * * * | |dice_gen:79|DIEB2

LC72 -> - - - - - - - - - - * - - - - - | - - - - * - | D1_1_7

LC65 -> - - - - - - - - - - - * - - - - | - - - - * - | D1_2_6

LC69 -> - - - - - - - - - - - - * - - - | - - - - * - | D2_2_6

LC71 -> * * * - - - - - - - - - - - * * | - - - - * - | |sync3:78|Debounce~1

LC75 -> * * * - - - - - - - - - - - * * | - - - - * - | |sync3:78|Debounce~2

Pin

84   -> * * - * * * * * * * - - - - * * | - - - - * - | CLOCK

16   -> * * * * - - - - - - - - - * * * | - - - - * - | RESET

2    -> - - - - * * * - - - - - - - * * | - - - - * - | ROLL_1

1    -> - - - - - - - * * * - - - - * * | - - - - * - | ROLL_2

83   -> - - - - - - - - - - * * * - - - | - - - * * * | SAMPLE

LC85 -> * - - - - - - - - - - - - - - - | - - - - * - | |control5:75|Q0~2

LC87 -> * - - - - - - - - - - - - - - - | - - - - * - | |eval_box:74|POINT

* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.

- = The logic cell or pin is not an input to the logic cell (or LAB).

Device-Specific Information:                             d:\rptfile\maxproj.rpt

MAXPROJ

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'F':

        +------------------------------- LC89 cmpen

        | +----------------------------- LC85 |control5:75|Q0~2

        | | +--------------------------- LC94 |dice_gen:79|74374:23|:13

        | | | +------------------------- LC93 |dice_gen:79|74374:23|:14

        | | | | +----------------------- LC91 |dice_gen:79|74374:23|:15

        | | | | | +--------------------- LC95 |dice_gen:79|74374:23|:16

        | | | | | | +------------------- LC84 D1_3_5

        | | | | | | | +----------------- LC83 D1_4

        | | | | | | | | +--------------- LC81 D2_1_7

        | | | | | | | | | +------------- LC87 |eval_box:74|POINT

        | | | | | | | | | | +----------- LC90 |eval_box:74|8faddb:45|SUM1

        | | | | | | | | | | | +--------- LC92 |eval_box:74|8faddb:45|SUM2

        | | | | | | | | | | | | +------- LC96 |eval_box:74|8faddb:45|SUM3

        | | | | | | | | | | | | | +----- LC82 |eval_box:74|8faddb:45|SUM4

        | | | | | | | | | | | | | | +--- LC88 LOSER

        | | | | | | | | | | | | | | | +- LC86 WINNER

        | | | | | | | | | | | | | | | |

LC      | | | | | | | | | | | | | | | | | A B C D E F | Name

LC94 -> - - - - - - - - - * - - - - - - | - - - - - * | |dice_gen:79|74374:23|:13

LC93 -> - - - - - - - - - * - - - - - - | - - - - - * | |dice_gen:79|74374:23|:14

LC91 -> - - - - - - - - - * - - - - - - | - - - - - * | |dice_gen:79|74374:23|:15

LC95 -> - - - - - - - - - * - - - - - - | - - - - - * | |dice_gen:79|74374:23|:16

LC84 -> - - - - - - * - - - - - - - - - | - - - - - * | D1_3_5

LC83 -> - - - - - - - * - - - - - - - - | - - - - - * | D1_4

LC81 -> - - - - - - - - * - - - - - - - | - - - - - * | D2_1_7

LC90 -> - - - - - - - - - * - - - - - - | - - - - - * | |eval_box:74|8faddb:45|SUM1

LC92 -> - - - - - - - - - * - - - - - - | - - - - - * | |eval_box:74|8faddb:45|SUM2

LC96 -> - - - - - - - - - * - - - - - - | - - - - - * | |eval_box:74|8faddb:45|SUM3

LC82 -> - - - - - - - - - * - - - - - - | - - - - - * | |eval_box:74|8faddb:45|SUM4

Pin

84   -> - - - - - - - - - - - - - - - - | - - - - * - | CLOCK

2    -> - - - - - - - - - - - - - - - - | - - - - * - | ROLL_1

1    -> - - - - - - - - - - - - - - - - | - - - - * - | ROLL_2

83   -> - - - - - - * * * - - - - - - - | - - - * * * | SAMPLE

LC78 -> * * * * * * - - - * - - - - * * | - - - - * * | |control5:75|Q0

LC79 -> * * * * * * - - - * - - - - * * | - - - - * * | |control5:75|Q1

LC73 -> * * * * * * - - - * - - - - * * | - - - - * * | |control5:75|Q2

LC70 -> - * * * * * * * - - * * * * - - | - - - - * * | |dice_gen:79|DIEA0

LC80 -> - * - * * * * * - - - * * * - - | - - - - * * | |dice_gen:79|DIEA1

LC66 -> - * - - * * * * - - - - * * - - | - - - - * * | |dice_gen:79|DIEA2

LC68 -> - * * * * * - - * - * * * * - - | - - - * * * | |dice_gen:79|DIEB0

LC74 -> - * - * * * - - * - - * * * - - | - - - * * * | |dice_gen:79|DIEB1

LC76 -> - * - - * * - - * - - - * * - - | - - - * * * | |dice_gen:79|DIEB2

* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.

- = The logic cell or pin is not an input to the logic cell (or LAB).

Device-Specific Information:                             d:\rptfile\maxproj.rpt

MAXPROJ

** EQUATIONS **

CLOCK    : INPUT;

in1      : INPUT;

RESET    : INPUT;

ROLL_1   : INPUT;

ROLL_2   : INPUT;

SAMPLE   : INPUT;

 cmpen   = LCELL( _EQ001 $  GND);

  _EQ001 = !_LC073 &  _LC078 &  _LC079;

% D1_1_7   = _LC072 %

% D1_1_7   = |dsamp2:68|1AND7 %

 D1_1_7  = LCELL( _EQ002 $  VCC);

  _EQ002 = !_LC066 & !_LC070 & !_LC080 &  SAMPLE

         # !D1_1_7 & !_LC066 & !_LC070 & !_LC080

         # !D1_1_7 & !SAMPLE;

% D1_2_6   = _LC065 %

% D1_2_6   = |dsamp2:68|2AND6 %

 D1_2_6  = LCELL( _EQ003 $  GND);

  _EQ003 =  _LC066 &  _LC070 & !_LC080 &  SAMPLE

         #  D1_2_6 &  _LC066 &  _LC070 & !_LC080

         #  D1_2_6 & !SAMPLE;

% D1_3_5   = _LC084 %

% D1_3_5   = |dsamp2:68|3AND5 %

 D1_3_5  = LCELL( _EQ004 $  GND);

  _EQ004 = !_LC066 &  _LC070 &  _LC080 &  _X001

         #  _LC066 & !_LC080 &  _X001

         #  D1_3_5 & !SAMPLE;

  _X001  = EXP(!D1_3_5 & !SAMPLE);

% D1_4     = _LC083 %

% D1_4     = |dsamp2:68|DOT4 %

 D1_4    = LCELL( _EQ005 $  GND);

  _EQ005 = !_LC066 & !_LC070 &  _LC080 &  _X002

         # !_LC070 & !_LC080 &  _X002

         #  D1_4 & !SAMPLE;

  _X002  = EXP(!D1_4 & !SAMPLE);

% D2_1_7   = _LC081 %

% D2_1_7   = |dsamp2:69|1AND7 %

 D2_1_7  = LCELL( _EQ006 $  VCC);

  _EQ006 = !_LC068 & !_LC074 & !_LC076 &  SAMPLE

         # !D2_1_7 & !_LC068 & !_LC074 & !_LC076

         # !D2_1_7 & !SAMPLE;

% D2_2_6   = _LC069 %

% D2_2_6   = |dsamp2:69|2AND6 %

 D2_2_6  = LCELL( _EQ007 $  GND);

  _EQ007 =  _LC068 & !_LC074 &  _LC076 &  SAMPLE

         #  D2_2_6 &  _LC068 & !_LC074 &  _LC076

         #  D2_2_6 & !SAMPLE;

% D2_3_5   = _LC051 %

% D2_3_5   = |dsamp2:69|3AND5 %

 D2_3_5  = LCELL( _EQ008 $  GND);

  _EQ008 =  _LC068 &  _LC074 & !_LC076 &  _X003

         # !_LC074 &  _LC076 &  _X003

         #  D2_3_5 & !SAMPLE;

  _X003  = EXP(!D2_3_5 & !SAMPLE);

% D2_4     = _LC049 %

% D2_4     = |dsamp2:69|DOT4 %

 D2_4    = LCELL( _EQ009 $  GND);

  _EQ009 = !_LC068 &  _LC074 & !_LC076 &  _X004

         # !_LC068 & !_LC074 &  _X004

         #  D2_4 & !SAMPLE;

  _X004  = EXP(!D2_4 & !SAMPLE);

 LOSER   = LCELL( _EQ010 $  GND);

  _EQ010 = !_LC073 &  _LC078 & !_LC079;

 out1    = LCELL( in1 $  GND);

 Reset_out = LCELL(!RESET $  GND);

 WINNER  = LCELL( _EQ011 $  GND);

  _EQ011 =  _LC073 &  _LC078 & !_LC079;

%  synthesized logic cells %

%  |control5:75|Q0~2  from file "control5.tdf" line 13, column 16 %

_LC085   = LCELL( _EQ012 $  GND);

  _EQ012 = !_LC066 & !_LC068 & !_LC073 & !_LC074 & !_LC076 & !_LC078 &

              _LC079 & !_LC080

         # !_LC066 &  _LC068 & !_LC070 & !_LC074 &  _LC076 &  _LC078 &

              _LC079 & !_LC080

         # !_LC066 & !_LC068 &  _LC070 & !_LC074 &  _LC076 &  _LC078 &

              _LC079 & !_LC080

         #  _LC066 &  _LC068 & !_LC070 & !_LC074 & !_LC076 &  _LC078 &

              _LC079 & !_LC080

         #  _LC066 & !_LC068 &  _LC070 & !_LC074 & !_LC076 &  _LC078 &

              _LC079 & !_LC080;

%  |control5:75|Q0  from file "control5.tdf" line 13, column 16 %

_LC078   = DFFE( _EQ013 $  VCC,  CLOCK, !RESET,  VCC,  VCC);

  _EQ013 = !_LC085 &  _X005 &  _X006 &  _X007 &  _X008 &  _X009 &  _X010 &

              _X011 &  _X012 &  _X013;

  _X005  = EXP(!_LC066 &  _LC068 & !_LC070 & !_LC073 &  _LC074 & !_LC076 &

              _LC079 &  _LC080);

  _X006  = EXP(!_LC066 & !_LC068 &  _LC070 & !_LC073 &  _LC074 & !_LC076 &

              _LC079 &  _LC080);

  _X007  = EXP( _LC066 &  _LC068 & !_LC073 & !_LC074 &  _LC076 & !_LC078 &

              _LC079 & !_LC080);

  _X008  = EXP( _LC068 & !_LC070 & !_LC073 & !_LC074 & !_LC078 &  _LC079 &

             !_LC080);

  _X009  = EXP(!_LC068 &  _LC070 & !_LC073 & !_LC074 & !_LC078 &  _LC079 &

             !_LC080);

  _X010  = EXP( _LC071 &  _LC073 & !_LC075 & !_LC078 & !_LC079);

  _X011  = EXP( _LC073 &  _LC078 &  _LC079);

  _X012  = EXP( _LC078 &  _LC079 &  _LC087);

  _X013  = EXP( _LC078 & !_LC079 & !RESET);

%  |control5:75|Q1  from file "control5.tdf" line 13, column 16 %

_LC079   = DFFE( _EQ014 $  GND,  CLOCK, !RESET,  VCC,  VCC);

  _EQ014 =  _LC071 & !_LC075 & !_LC078 & !_LC079;

%  synthesized logic cells %

%  |control5:75|Q2~2  from file "control5.tdf" line 13, column 16 %

_LC077   = LCELL( _EQ015 $  GND);

  _EQ015 =  _LC078 & !_LC079 &  RESET

         #  _LC071 & !_LC075 & !_LC078 & !_LC079

         #  _LC066 &  _LC068 &  _LC070 & !_LC073 & !_LC074 &  _LC076 &

             !_LC078 & !_LC080

         # !_LC066 & !_LC068 &  _LC070 & !_LC073 & !_LC074 &  _LC076 &

              _LC078 & !_LC080

         # !_LC066 &  _LC068 & !_LC070 & !_LC073 & !_LC074 &  _LC076 &

              _LC078 & !_LC080;

%  |control5:75|Q2  from file "control5.tdf" line 13, column 16 %

_LC073   = DFFE( _EQ016 $  _EQ017,  CLOCK, !RESET,  VCC,  VCC);

  _EQ016 = !_LC066 & !_LC068 &  _LC070 & !_LC073 &  _LC074 & !_LC076 &

             !_LC077 &  _LC078 &  _LC080 &  _X014 &  _X015 &  _X016 &  _X017 &

              _X018

         # !_LC066 &  _LC068 & !_LC070 & !_LC073 &  _LC074 & !_LC076 &

             !_LC077 &  _LC078 &  _LC080 &  _X014 &  _X015 &  _X016 &  _X017 &

              _X018;

  _X014  = EXP( _LC066 & !_LC068 &  _LC070 & !_LC073 & !_LC074 & !_LC076 &

              _LC078 & !_LC080);

  _X015  = EXP( _LC066 &  _LC068 & !_LC070 & !_LC073 & !_LC074 & !_LC076 &

              _LC078 & !_LC080);

  _X016  = EXP(!_LC066 & !_LC070 & !_LC073 & !_LC074 & !_LC076 & !_LC078 &

             !_LC080);

  _X017  = EXP(!_LC066 & !_LC068 & !_LC073 & !_LC074 & !_LC076 & !_LC078 &

             !_LC080);

  _X018  = EXP(!_LC073 & !_LC079);

  _EQ017 = !_LC077 &  _X014 &  _X015 &  _X016 &  _X017 &  _X018;

% |dice_gen:79|DIEA0 = |dice_gen:79|74163:39|:34 %

_LC070   = TFFE( ROLL_1,  CLOCK,  VCC,  VCC,  VCC);

% |dice_gen:79|DIEA1 = |dice_gen:79|74163:39|:35 %

_LC080   = TFFE( _EQ018,  CLOCK,  VCC,  VCC,  VCC);

  _EQ018 = !_LC066 &  _LC070 & !_LC080 &  ROLL_1

         #  _LC070 &  _LC080 &  ROLL_1;

% |dice_gen:79|DIEA2 = |dice_gen:79|74163:39|:36 %

_LC066   = TFFE( _EQ019,  CLOCK,  VCC,  VCC,  VCC);

  _EQ019 = !_LC066 &  _LC070 &  _LC080 &  ROLL_1

         #  _LC066 &  _LC070 &  ROLL_1;

% |dice_gen:79|DIEB0 = |dice_gen:79|74163:38|:34 %

_LC068   = TFFE( ROLL_2,  CLOCK,  VCC,  VCC,  VCC);

% |dice_gen:79|DIEB1 = |dice_gen:79|74163:38|:35 %

_LC074   = TFFE( _EQ020,  CLOCK,  VCC,  VCC,  VCC);

  _EQ020 =  _LC068 & !_LC074 & !_LC076 &  ROLL_2

         #  _LC068 &  _LC074 &  ROLL_2;

% |dice_gen:79|DIEB2 = |dice_gen:79|74163:38|:36 %

_LC076   = TFFE( _EQ021,  CLOCK,  VCC,  VCC,  VCC);

  _EQ021 =  _LC068 &  _LC074 & !_LC076 &  ROLL_2

         #  _LC068 &  _LC076 &  ROLL_2;

%  |dice_gen:79|74374:23|:13  %

_LC094   = DFFE( _LC068 $  _LC070,  _EQ022,  VCC,  VCC,  VCC);

  _EQ022 = !_LC073 & !_LC078 &  _LC079;

%  |dice_gen:79|74374:23|:14  %

_LC093   = DFFE( _EQ023 $  GND,  _EQ024,  VCC,  VCC,  VCC);

  _EQ023 =  _LC068 &  _LC070 &  _LC074 &  _LC080

         #  _LC068 &  _LC070 & !_LC074 & !_LC080

         # !_LC070 &  _X019 &  _X020

         # !_LC068 &  _X019 &  _X020;

  _X019  = EXP( _LC074 &  _LC080);

  _X020  = EXP(!_LC074 & !_LC080);

  _EQ024 = !_LC073 & !_LC078 &  _LC079;

%  |dice_gen:79|74374:23|:15  %

_LC091   = DFFE( _EQ025 $  _EQ026,  _EQ027,  VCC,  VCC,  VCC);

  _EQ025 =  _LC068 &  _LC070 &  _X020

         #  _LC074 &  _LC080;

  _EQ026 =  _X021 &  _X022;

  _X021  = EXP(!_LC066 & !_LC076);

  _X022  = EXP( _LC066 &  _LC076);

  _EQ027 = !_LC073 & !_LC078 &  _LC079;

%  |dice_gen:79|74374:23|:16  %

_LC095   = DFFE( _EQ028 $  GND,  _EQ029,  VCC,  VCC,  VCC);

  _EQ028 =  _LC068 &  _LC070 &  _X020 &  _X021

         #  _LC074 &  _LC080 &  _X021

         #  _LC066 &  _LC076;

  _EQ029 = !_LC073 & !_LC078 &  _LC079;

% |eval_box:74|POINT = |eval_box:74|:47 %

_LC087   = LCELL( _EQ030 $  _EQ031);

  _EQ030 = !_LC073 &  _LC078 &  _LC079 &  _LC090 & !_LC094 &  _X023 &  _X024 &

              _X025 &  _X026

         # !_LC073 &  _LC078 &  _LC079 & !_LC090 &  _LC094 &  _X023 &  _X024 &

              _X025 &  _X026

         # !_LC073 &  _LC078 &  _LC079 &  _LC092 & !_LC093 &  _X023 &  _X024 &

              _X025 &  _X026

         # !_LC073 &  _LC078 &  _LC079 & !_LC092 &  _LC093 &  _X023 &  _X024 &

              _X025 &  _X026;

  _X023  = EXP( _LC091 & !_LC096);

  _X024  = EXP(!_LC091 &  _LC096);

  _X025  = EXP( _LC082 & !_LC095);

  _X026  = EXP(!_LC082 &  _LC095);

  _EQ031 = !_LC073 &  _LC078 &  _LC079 &  _X023 &  _X024 &  _X025 &  _X026;

% |eval_box:74|8faddb:45|SUM1 = |eval_box:74|8faddb:45|:137 %

_LC090   = LCELL( _LC068 $  _LC070);

% |eval_box:74|8faddb:45|SUM2 = |eval_box:74|8faddb:45|:136 %

_LC092   = LCELL( _EQ032 $  _LC080);

  _EQ032 =  _LC068 &  _LC070 & !_LC074

         # !_LC070 &  _LC074

         # !_LC068 &  _LC074;

% |eval_box:74|8faddb:45|SUM3 = |eval_box:74|8faddb:45|:135 %

_LC096   = LCELL( _EQ033 $  _EQ034);

  _EQ033 =  _LC068 &  _LC070 &  _X020

         #  _LC074 &  _LC080;

  _EQ034 =  _X021 &  _X022;

% |eval_box:74|8faddb:45|SUM4 = |eval_box:74|8faddb:45|:134 %

_LC082   = LCELL( _EQ035 $  GND);

  _EQ035 =  _LC068 &  _LC070 &  _X020 &  _X021

         #  _LC074 &  _LC080 &  _X021

         #  _LC066 &  _LC076;

%  |sync3:78|Debounce~1  %

_LC071   = DFFE( _EQ036 $  GND,  CLOCK,  RESET,  VCC,  VCC);

  _EQ036 = !_LC071 &  _LC075 & !ROLL_1 & !ROLL_2;

%  |sync3:78|Debounce~2  %

_LC075   = DFFE( _EQ037 $  VCC,  CLOCK,  RESET,  VCC,  VCC);

  _EQ037 = !_LC075 & !ROLL_1 & !ROLL_2

         # !_LC071 & !ROLL_1 & !ROLL_2;

%

    Shareable expanders that are duplicated in multiple LABs:

    (none)

%

Project Information                                      d:\rptfile\maxproj.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands

Design Doctor                          = off

Logic Synthesis:

   Default Synthesis Style             = Normal

     Logic option settings in 'NORMAL' style for 'MAX7000' family

      MINIMIZATION                     = full

      PARALLEL_EXPANDERS               = off

      SLOW_SLEW_RATE                   = off

      SOFT_BUFFER_INSERTION            = off

      TURBO_BIT                        = on

      XOR_SYNTHESIS                    = on

   Other logic synthesis settings:

      Automatic Global Clock           = off

      Automatic Global Clear           = off

      Automatic Global Preset          = off

      Automatic Global Output Enable   = off

      Automatic I/O Cell Registers     = off

Default Timing Specifications: None

Cut All Bidirectional Feedback Timing Paths = on

Cut All Clear & Preset Timing Paths    = on

Ignore Timing Assignments              = off

Functional SNF Extractor               = off

Linked SNF Extractor                   = off

Timing SNF Extractor                   = on

Optimize Timing SNF                    = off

Generate JEDEC Files                   = off

Generate AHDL TDO File                 = off

Automatic LCELL Insertion              = off

Smart Recompile                        = off

Total Recompile                        = off

Interface Menu Commands

EDIF Netlist Writer                    = off

Verilog Netlist Writer                 = off

VHDL Netlist Writer                    = off

Compilation Times -----------------

   Compiler Netlist Extractor          00:00:03

   Database Builder                    00:00:09

   Logic Synthesizer                   00:00:19

   Partitioner                         00:00:01

   Fitter                              00:00:05

   Timing SNF Extractor                00:00:09

   Assembler                           00:00:01

   ­­­­­­­­­­­­­­­­­­­­­­­­­­          ­­­­­­­­

  Total Time                           00:00:38

See also:

Annotated Report File: FLEX 8000 Devices


Annotated Report File: FLEX 8000 Devices

Project Information                                    d:\rptfile\flexproj.rpt

MAX+plus II Compiler Report File

Version 5.0

Compiled: 07/28/94 15:14:52

***** Project compilation was successful

Title: DESIGN NAME

Company: Altera

Designer: Joe Engineer

Rev: A

Date: 4:15p 07-15-1994

** DEVICE SUMMARY **

Chip/                  Input     Output    Bidir          Shareable

POF        Device      Pins      Pins      Pins     LCs   Expanders   % Utilized

flexproj  EPF81188       5        13         0      66       0             6  %

User Pins:               5        13         0

** PROJECT COMPILATION MESSAGES **

Warning: Ignored unnecessary input pin 'unused1'

Warning: Ignored unnecessary input pin 'unused2'

Warning: Ignored unnecessary input pin 'in1'

Warning: Can't merge logic fed by CARRY primitive '|eval_box:74|8faddb:45|:189' into a single logic cell -- LCELL inserted automatically

Warning: Can't merge logic fed by CARRY primitive '|eval_box:74|8faddb:45|:197' into a single logic cell -- LCELL inserted automatically

Warning: JTAG boundary-scan testing is not supported in 'EPF81188'

Warning: Can't provide tpd of 30.0 ns from "SAMPLE" to "D1_1_7". Current tpd is 31.6 ns.

Warning: Can't provide tpd of 30.0 ns from "SAMPLE" to "D1_4". Current tpd is 30.8 ns.

Warning: Can't provide tpd of 30.0 ns from "SAMPLE" to "D2_1_7". Current tpd is 31.6 ns.

Warning: Can't provide tpd of 30.0 ns from "SAMPLE" to "D2_4". Current tpd is 31.1 ns.

Warning: Can't provide tco of 10.0 ns from "CLOCK" to "cmpen". Current tco is 22.5 ns.

** PROJECT TIMING-DRIVEN COMPILATION MESSAGES **

Warning: Can't provide tco of 10.0 ns from "CLOCK" to "cmpen". Current tco is 20.9 ns.

Warning: Found ripple clock -- warning messages and Report File information on tco, tsu, and fmax may be inaccurate

** CLIQUE ASSIGNMENTS **

CLIQUE "fast1"  placed in chip "flexproj", row B, multiple LABS

    |eval_box:74|POINT

    |eval_box:74|~48~1

    |eval_box:74|8faddb:45|~197~1

    |eval_box:74|8faddb:45|~189~2

    |eval_box:74|7~2

    |eval_box:74|7

    |eval_box:74|7~1

    |eval_box:74|~48~2

    |eval_box:74|~48~3

Project Information                                      d:\rptfile\flexproj.rpt

** PROBE ASSIGNMENTS **

Probe Name                       Primitive/Macrofunction

DIE_B1                           |dice_gen:79|74163:39|:34.Q

DIE_B2                           |dice_gen:79|74163:39|:35.Q

DIE_B3                           |dice_gen:79|74163:39|:36.Q

POINT                            |eval_box:74|:47.OUT

Project Information                                      d:\rptfile\flexproj.rpt

** STATE MACHINE ASSIGNMENTS **

|control5:75|Control: MACHINE

        OF BITS (

           |control5:75|Control~3,

           |control5:75|Control~2,

           |control5:75|Control~1,

           |control5:75|Q2,

           |control5:75|Q1,

           |control5:75|Q0

        )

        WITH STATES (

                       WAIT_ROLL = B"000000",

                      CHECK_ROLL = B"110000",

                      WAIT_POINT = B"101000",

                     CHECK_POINT = B"100100",

                            LOST = B"100010",

                             WON = B"100001"

);

|sync3:78|Debounce: MACHINE

        OF BITS (

           |sync3:78|Debounce~2,

           |sync3:78|Debounce~1

        )

        WITH STATES (

                            Wait = B"00",

                         Rolling = B"10",

                            Done = B"01"

);

Project Information                                      d:\rptfile\flexproj.rpt

** FILE HIERARCHY **

|control5:75|

|dice_gen:79|

|dice_gen:79|74163:39|

|dice_gen:79|74163:38|

|dice_gen:79|74374:23|

|dice_gen:79|8fadd:28|

|eval_box:74|

|eval_box:74|7485ns:43|

|eval_box:74|8faddb:45|

|eval_box:74|encode2:46|

|sync3:78|

|dsamp2:69|

|dsamp2:69|7404:60|

|dsamp2:68|

|dsamp2:68|7404:60|

Device-Specific Information:                             d:\rptfile\flexproj.rpt

flexproj

***** Logic for device 'flexproj' compiled without errors.

Device: EPF81188ES

FLEX 8000 Configuration Scheme: Active Serial

FLEX 8000 Options:

    User-Supplied Start-Up Clock                 = ON

    Auto-Restart Configuration on Frame Errors   = ON

    Release Clears Before Tri-States             = ON

    Enable DCLK Output in User Mode              = ON

    Disable Start-Up Time-Out                    = ON

    Enable JTAG Support                          = OFF

Pin-Out Diagram

            -------------------------------------------------------

           |   1  2  3  4  5  6  7  8  9 10 11 12 13 14 15 16 17   |

           |U  o  o  o  o  o  o  o  o  o  o  o  o  o  o  o  o  o  U|

           |T  o  o  o  o  o  o  o  o  o  o  o  o  o  o  o  o  o  T|

           |R  o  o  o  o  o  o  o  o  o  o  o  o  o  o  o  o  o  R|

           |P  o  o  o  o  o  o  o  o  o  o  o  o  o  o  o  o  o  P|

           |N  o  o  o  o        o  o  o  o  o        o  o  o  o  N|

           |M  o  o  o  o  o                       o  o  o  o  o  M|

           |L  o  o  o  o  o                       o  o  o  o  o  L|

           |K  o  o  o  o  o                       o  o  o  o  o  K|

           |J  o  o  o  o  o                       o  o  o  o  o  J|

           |H  o  o  o  o  o                       o  o  o  o  o  H|

           |G  o  o  o  o  o                       o  o  o  o  o  G|

           |F  o  o  o  o  o                       o  o  o  o  o  F|

           |E  o  o  o  o        o  o  o  o  o        o  o  o  o  E|

           |D  o  o  o  o  o  o  o  o  o  o  o  o  o  o  o  o  o  D|

           |C  o  o  o  o  o  o  o  o  o  o  o  o  o  o  o  o  o  C|

           |B  o  o  o  o  o  o  o  o  o  o  o  o  o  o  o  o  o  B|

           |A  o  o  o  o  o  o  o  o  o  o  o  o  o  o  o  o  o  A|

           |   1  2  3  4  5  6  7  8  9 10 11 12 13 14 15 16 17   |

            -------------------------------------------------------

                                    EPF81188

                                  Bottom View

   A1 GND       C6 RESERVED E15 RESERVED J14 RESERVED  N8 VCC      R15 RESERVED

   A2 +DATA0    C7 RESERVED E16 SAMPLE   J15 RESERVED  N9 GND      R16 RESERVED

   A3 RESERVED  C8 RESERVED E17 ROLL_1   J16 RESERVED N10 VCC      R17 GND

   A4 RESERVED  C9 RESERVED  F1 D1_4     J17 RESERVED N11 GND       T1 RESERVED

   A5 RESERVED C10 RESERVED  F2 RESERVED  K1 RESERVED N14 GND       T2 RESERVED

   A6 RESERVED C11 RESERVED  F3 ROLL_2    K2 RESERVED N15 RESERVED  T3 RESERVED

   A7 RESERVED C12 RESERVED  F4 D2_2_6    K3 RESERVED N16 RESERVED  T4 RESERVED

   A8 RESERVED C13 RESERVED  F5 VCC       K4 GND      N17 RESERVED  T5 RESERVED

   A9 RESERVED C14 ^nSP     F13 VCC       K5 VCC       P1 RESERVED  T6 RESERVED

  A10 RESERVED C15 RESERVED F14 RESERVED K13 VCC       P2 RESERVED  T7 RESERVED

  A11 RESERVED C16 RESERVED F15 D1_1_7   K14 GND       P3 RESERVED  T8 RESERVED

  A12 RESERVED C17 GND      F16 D1_2_6   K15 RESERVED  P4 RESERVED  T9 RESERVED

  A13 RESERVED  D1 RESERVED F17 RESERVED K16 RESERVED  P5 RESERVED T10 RESERVED

  A14 RESERVED  D2 D2_4      G1 RESERVED K17 RESERVED  P6 RESERVED T11 RESERVED

  A15 RESERVED  D3 Reset_ou  G2 RESERVED  L1 RESERVED  P7 RESERVED T12 RESERVED

  A16 RESERVED  D4 RESERVED  G3 ^CONF_DO  L2 RESERVED  P8 RESERVED T13 RESERVED

  A17 RESERVED  D5 out1      G4 GND       L3 ^nSTATUS  P9 RESERVED T14 RESERVED

   B1 D2_3_5    D6 GND       G5 GND       L4 VCC      P10 RESERVED T15 RESERVED

   B2 RESERVED  D7 RESERVED G13 GND       L5 GND      P11 RESERVED T16 RESERVED

   B3 RESERVED  D8 RESERVED G14 GND      L13 GND      P12 VCC      T17 RESERVED

   B4 RESERVED  D9 RESERVED G15 ^MSEL0   L14 VCC      P13 RESERVED  U1 VCC

   B5 RESERVED D10 RESERVED G16 RESERVED L15 ^MSEL1   P14 RESERVED  U2 RESERVED

   B6 RESERVED D11 RESERVED G17 RESERVED L16 RESERVED P15 RESERVED  U3 RESERVED

   B7 RESERVED D12 RESERVED  H1 RESERVED L17 RESERVED P16 RESERVED  U4 RESERVED

   B8 RESERVED D13 RESERVED  H2 RESERVED  M1 RESERVED P17 RESERVED  U5 RESERVED

   B9 RESERVED D14 cmpen     H3 RESERVED  M2 RESERVED  R1 GND       U6 RESERVED

  B10 RESERVED D15 WINNER    H4 VCC       M3 RESERVED  R2 RESERVED  U7 RESERVED

  B11 RESERVED D16 LOSER     H5 VCC       M4 RESERVED  R3 RESERVED  U8 RESERVED

  B12 RESERVED D17 RESERVED H13 VCC       M5 VCC       R4 ^nCONFIG  U9 RESERVED

  B13 RESERVED  E1 RESET    H14 VCC      M13 VCC       R5 RESERVED U10 RESERVED

  B14 RESERVED  E2 CLOCK    H15 RESERVED M14 RESERVED  R6 RESERVED U11 RESERVED

  B15 RESERVED  E3 D1_3_5   H16 RESERVED M15 RESERVED  R7 RESERVED U12 RESERVED

  B16 RESERVED  E4 VCC      H17 RESERVED M16 RESERVED  R8 RESERVED U13 RESERVED

  B17 D2_1_7    E7 GND       J1 RESERVED M17 RESERVED  R9 RESERVED U14 RESERVED

   C1 GND       E8 VCC       J2 RESERVED  N1 RESERVED R10 RESERVED U15 RESERVED

   C2 RESERVED  E9 GND       J3 RESERVED  N2 RESERVED R11 RESERVED U16 RESERVED

   C3 RESERVED E10 VCC       J4 RESERVED  N3 RESERVED R12 RESERVED U17 RESERVED

   C4 ^DCLK    E11 GND       J5 GND       N4 GND      R13 RESERVED

   C5 RESERVED E14 VCC      J13 GND       N7 GND      R14 VCC

N.C. = Not Connected.

VCC = Dedicated power pin, which MUST be connected to VCC.

GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.

RESERVED = Unused I/O pin, which MUST be left unconnected.

^ = Dedicated configuration pin.

+ = Reserved configuration pin, which will be tri-stated during user mode.

* = Reserved configuration pin, which drives out in user mode.

PDn = Power Down pin.

# = JTAG Boundary Scan Testing Pin.

Device-Specific Information:                             d:\rptfile\flexproj.rpt

FLEXPROJ

** RESOURCE USAGE **

Logic               Column        Row

Array               Interconnect  Interconnect          Clear/    External

Block   Logic Cells Driven        Driven        Clocks  Preset    Interconnect

B1      6/8( 75%)    0/8(  0%)    5/8( 62%)      1/2    1/2       8/24( 33%)

B2      6/8( 75%)    0/8(  0%)    3/8( 37%)      1/2    1/2       4/24( 16%)

B3      6/8( 75%)    0/8(  0%)    3/8( 37%)      1/2    1/2       4/24( 16%)

B4      8/8(100%)    0/8(  0%)    2/8( 25%)      1/2    1/2      12/24( 50%)

B5      8/8(100%)    0/8(  0%)    5/8( 62%)      0/2    0/2       9/24( 37%)

B6      7/8( 87%)    0/8(  0%)    3/8( 37%)      0/2    0/2      10/24( 41%)

B7      7/8( 87%)    0/8(  0%)    3/8( 37%)      1/2    1/2       9/24( 37%)

B8      6/8( 75%)    0/8(  0%)    3/8( 37%)      1/2    2/2      12/24( 50%)

B9      1/8( 12%)    0/8(  0%)    1/8( 12%)      0/2    0/2       1/24(  4%)

B10     1/8( 12%)    0/8(  0%)    1/8( 12%)      0/2    0/2       3/24( 12%)

B11     1/8( 12%)    0/8(  0%)    1/8( 12%)      1/2    1/2       4/24( 16%)

B12     1/8( 12%)    0/8(  0%)    1/8( 12%)      1/2    1/2       4/24( 16%)

B13     1/8( 12%)    0/8(  0%)    1/8( 12%)      0/2    0/2       3/24( 12%)

B14     1/8( 12%)    0/8(  0%)    1/8( 12%)      1/2    1/2       2/24(  8%)

B15     1/8( 12%)    0/8(  0%)    1/8( 12%)      1/2    1/2       2/24(  8%)

B16     1/8( 12%)    0/8(  0%)    1/8( 12%)      0/2    0/2       4/24( 16%)

B17     1/8( 12%)    0/8(  0%)    1/8( 12%)      0/2    0/2       2/24(  8%)

B18     1/8( 12%)    0/8(  0%)    1/8( 12%)      0/2    0/2       2/24(  8%)

B19     1/8( 12%)    0/8(  0%)    1/8( 12%)      0/2    0/2       2/24(  8%)

B20     1/8( 12%)    0/8(  0%)    1/8( 12%)      0/2    0/2       4/24( 16%)

Total dedicated input pins used:                 0/   4 (  0%)

Total I/O pins used:                            19/ 180 ( 10%)

Total logic cells used:                         66/1008 (  6%)

Total input pins required:                       5

Total input registers required:                  0

Total output pins required:                     13

Total output registers required:                 0

Total buried I/O cell registers required:        0

Total bidirectional pins required:               0

Total reserved pins required                     1

Total logic cells required:                     66

Total flipflops required:                       18

Total logic cells in carry chains:              15

Total number of carry chains                     4

Total logic cells in cascade chains              0

Total number of cascade chains                   0

Synthesized logic cells:                        27/1008 (  2%)

Logic Cell Counts

         01  02  03  04  05  06  07  08  09  10  11  12  13  14  15  16  17  18  19  20  21  Total

 A:      0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0      0

 B:      6   6   6   8   8   7   7   6   1   1   1   1   1   1   1   1   1   1   1   1   0     66

 C:      0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0      0

 D:      0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0      0

 E:      0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0      0

 F:      0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0      0

Total:   6   6   6   8   8   7   7   6   1   1   1   1   1   1   1   1   1   1   1   1   0

Device-Specific Information:                             d:\rptfile\flexproj.rpt

FLEXPROJ

** INPUTS **

                                         Fan-In    Fan-Out

 Pin      LC  Row  Col  Primitive       INP  FBK  OUT  FBK  Name

  E2      -    B    --      INPUT         0    0   0   14   CLOCK

  E1      -    B    --      INPUT         0    0   0   11   RESET

 E17      -    B    --      INPUT         0    0   0    6   ROLL_1

  F3      -    B    --      INPUT         0    0   0    6   ROLL_2

 E16      -    B    --      INPUT         0    0   0   14   SAMPLE

Code:

s = Synthesized pin or logic cell

+ = Synchronous flipflop

/ = Slow slew-rate output

! = NOT gate push-back

r = Fitter-inserted logic cell

Device-Specific Information:                             d:\rptfile\flexproj.rpt

FLEXPROJ

** OUTPUTS **

       Fed By                            Fan-In    Fan-Out

 Pin     LC   Row  Col  Primitive       INP  FBK  OUT  FBK   Name

 D14      -    A    --     OUTPUT         0    1   0    0    cmpen

 F15      -    B    --     OUTPUT         0    1   0    0    D1_1_7

 F16      -    B    --     OUTPUT         0    1   0    0    D1_2_6

  E3      -    B    --     OUTPUT         0    1   0    0    D1_3_5

  F1      -    C    --     OUTPUT         0    1   0    0    D1_4

 B17      -    A    --     OUTPUT         0    1   0    0    D2_1_7

  F4      -    B    --     OUTPUT         0    1   0    0    D2_2_6

  B1      -    A    --     OUTPUT         0    1   0    0    D2_3_5

  D2      -    B    --     OUTPUT         0    1   0    0    D2_4

 D16      -    B    --     OUTPUT         0    1   0    0    LOSER

  D5      -    A    --     OUTPUT         0    0   0    0    out1

  D3      -    A    --     OUTPUT         0    1   0    0    Reset_out

 D15      -    A    --     OUTPUT         0    1   0    0    WINNER

Code:

s = Synthesized pin or logic cell

+ = Synchronous flipflop

/ = Slow slew-rate output

! = NOT gate push-back

r = Fitter-inserted logic cell

Device-Specific Information:                             d:\rptfile\flexproj.rpt

FLEXPROJ

** BURIED LOGIC **

                                         Fan-In     Fan-Out

 Pin     LC   Row  Col  Primitive       INP  FBK   OUT  FBK   Name

   -      8    B    17       AND2         0    2    0   10    |control5:75|CHECK_ROLL

   -      4    B    08        DFF         2    3    0    2    |control5:75|Control~1

   -      1    B    07        DFF         2    3    0    1    |control5:75|Control~2

   -      7    B    07        DFF         2    3    0    1    |control5:75|Control~3

   -      2    B    11        DFF         2    2    0    8    |control5:75|Q0

   -      2    B    07        DFF         2    3    0    3    |control5:75|Q1

   -      2    B    12        DFF         2    2    0    6    |control5:75|Q2

   -      5    B    07       AND2 s       0    3    0    1    |control5:75|WAIT_ROLL~1

   -      2    B    05        OR2         0    4    0    2    |control5:75|:65

   -      3    B    04        OR2 s       0    2    0    2    |control5:75|~73~1

   -      7    B    06        OR2 s       0    2    0    2    |control5:75|~73~2

   -      4    B    06        OR2         0    4    0    4    |control5:75|:73

   -      6    B    06       AND2         0    3    0    1    |control5:75|:74

   -      3    B    08       AND2         0    3    0    2    |control5:75|:81

   -      5    B    05        OR2         0    4    0    2    |control5:75|:86

   -      6    B    08       AND2         0    3    0    2    |control5:75|:92

   -      4    B    07        OR2 s       0    4    0    2    |control5:75|~109~1

   -      2    B    08        OR2 s       0    3    0    2    |control5:75|~109~2

   -      6    B    07        OR2         0    4    0    2    |control5:75|:109

   -      8    B    16        OR2 s       0    4    0    1    |control5:75|~119~1

   -      2    B    06        OR2 s       0    4    0    2    |control5:75|~119~2

   -      3    B    06       AND2 s       0    3    0    5    |control5:75|~119~3

   -      5    B    20        OR2 s       0    4    0    1    |control5:75|~119~4

   -      3    B    07        OR2 s       1    2    0    1    |control5:75|~121~1

   -      3    B    15        DFF         2    0    0    1    |dice_gen:79|DIEA0 (|dice_gen:79|74163:39|:34)

   -      2    B    03        DFF         1    1    0    1    |dice_gen:79|DIEA1 (|dice_gen:79|74163:39|:35)

   -      3    B    03        DFF         2    1    0    1    |dice_gen:79|DIEA2 (|dice_gen:79|74163:39|:36)

   -      3    B    14        DFF         2    0    0    1    |dice_gen:79|DIEB0 (|dice_gen:79|74163:38|:34)

   -      3    B    02        DFF         1    1    0    1    |dice_gen:79|DIEB1 (|dice_gen:79|74163:38|:35)

   -      4    B    02        DFF         2    1    0    1    |dice_gen:79|DIEB2 (|dice_gen:79|74163:38|:36)

   -      5    B    02        OR2         1    2    0    1    |dice_gen:79|:32

   -      4    B    03        OR2         1    2    0   11    |dice_gen:79|:40

   -      1    B    04        DFF         0    3    0   13    |dice_gen:79|74374:23|:13

   -      6    B    01        DFF         0    3    0   16    |dice_gen:79|74374:23|:14

   -      7    B    01        DFF         0    3    0   11    |dice_gen:79|74374:23|:15

   -      8    B    01        DFF         0    1    0   13    |dice_gen:79|74374:23|:16

   -      6    B    03        OR2 s       1    3    0   16    |dsamp2:68|DOT4~1 (|dsamp2:68|:56)

   -      5    B    03      LATCH         1    1    0    1    |dsamp2:68|DOT4 (|dsamp2:68|:56)

   -      3    B    05        OR2 s       1    3    0    1    |dsamp2:68|1AND7~1 (|dsamp2:68|:55)

   -      8    B    05      LATCH         1    1    0    1    |dsamp2:68|1AND7 (|dsamp2:68|:55)

   -      6    B    10      LATCH         1    2    0    1    |dsamp2:68|2AND6 (|dsamp2:68|:54)

   -      2    B    01        OR2 s       1    3    0    1    |dsamp2:68|3AND5~1 (|dsamp2:68|:53)

   -      1    B    01      LATCH         1    1    0    1    |dsamp2:68|3AND5 (|dsamp2:68|:53)

   -      2    B    19       AND2 s       0    2    0    1    |dsamp2:68|~47~1

   -      6    B    02        OR2 s       1    3    0    1    |dsamp2:69|DOT4~1 (|dsamp2:69|:56)

   -      1    B    02      LATCH         1    1    0    1    |dsamp2:69|DOT4 (|dsamp2:69|:56)

   -      4    B    05        OR2 s       1    3    0    1    |dsamp2:69|1AND7~1 (|dsamp2:69|:55)

   -      1    B    05      LATCH         1    1    0    1    |dsamp2:69|1AND7 (|dsamp2:69|:55)

   -      3    B    13      LATCH         1    2    0    1    |dsamp2:69|2AND6 (|dsamp2:69|:54)

   -      5    B    06        OR2 s       1    3    0    1    |dsamp2:69|3AND5~1 (|dsamp2:69|:53)

   -      1    B    06      LATCH         1    1    0    1    |dsamp2:69|3AND5 (|dsamp2:69|:53)

   -      4    B    18        OR2 s       0    2    0    1    |dsamp2:69|~47~1

   -      7    B    04      LCELL         0    4    0    1    |eval_box:74|POINT (|eval_box:74|:47)

   -      5    B    01        OR2 s       0    2    0    1    |eval_box:74|7~1 (|eval_box:74|encode2:46|:122)

   -      7    B    05        OR2 s       0    4    0    1    |eval_box:74|7~2 (|eval_box:74|encode2:46|:122)

   -      6    B    05        OR2         0    3    0    1    |eval_box:74|7 (|eval_box:74|encode2:46|:122)

   -      2    B    04       SOFT s       0    0    0    1    |eval_box:74|8faddb:45|~189~2

   -      4    B    04       SOFT s       0    2    0    1    |eval_box:74|8faddb:45|~197~1

   -      6    B    04        OR2 s       0    4    0    1    |eval_box:74|~48~1

   -      8    B    04        OR2 s       0    4    0    1    |eval_box:74|~48~2

   -      5    B    04        OR2 s       0    3    0    1    |eval_box:74|~48~3

   -      3    B    09      LCELL s       1    0    0    2    Reset_out~1

   -      5    B    08        DFF         4    1    0    4    |sync3:78|Debounce~1

   -      1    B    08        DFF         4    0    0    1    |sync3:78|Debounce~2

   -      5    B    01      CARRY         0    2    0    5    |dice_gen:79|8fadd:28|:189

   -      6    B    01      CARRY         0    3    0    3    |dice_gen:79|8fadd:28|:197

   -      7    B    01      CARRY         0    3    0    1    |dice_gen:79|8fadd:28|:205

   -      3    B    02      CARRY         1    2    0    4    |dice_gen:79|74163:38|:99

   -      2    B    02      CARRY         1    1    0    2    |dice_gen:79|74163:38|:100

   -      2    B    03      CARRY         1    2    0    1    |dice_gen:79|74163:39|:99

   -      1    B    03      CARRY         1    1    0    1    |dice_gen:79|74163:39|:100

   -      2    B    04       SOFT s       0    0    0    1    |eval_box:74|8faddb:45|~189~1

   -      1    B    04      CARRY         0    3    0    1    |eval_box:74|8faddb:45|:189

   -      3    B    04      CARRY         0    2    0    2    |eval_box:74|8faddb:45|:197

   -      4    B    04      CARRY         0    2    0    1    |eval_box:74|8faddb:45|:205

Code:

s = Synthesized pin or logic cell

+ = Synchronous flipflop

/ = Slow slew-rate output

! = NOT gate push-back

r = Fitter-inserted logic cell

Device-Specific Information:                             d:\rptfile\flexproj.rpt

FLEXPROJ

** FASTTRACK INTERCONNECT UTILIZATION **

Row FastTrack Interconnect:

        FastTrack

Row     Interconnect    Input Pins      Output Pins    Bidir Pins

A:       0/168(  0%)    0/16(  0%)      6/16( 37%)     0/16(  0%)

B:      41/168( 24%)    5/16( 31%)      6/16( 37%)     0/16(  0%)

C:       0/168(  0%)    0/16(  0%)      1/16(  6%)     0/16(  0%)

D:       0/168(  0%)    0/16(  0%)      0/16(  0%)     0/16(  0%)

E:       0/168(  0%)    0/16(  0%)      0/16(  0%)     0/16(  0%)

F:       0/168(  0%)    0/16(  0%)      0/16(  0%)     0/16(  0%)

Column FastTrack Interconnect:

         Fastrack

Column   Interconnect   Input Pins     Output Pins     Bidir Pins

01:      0/16(  0%)     0/4(  0%)      1/4( 25%)       0/4(  0%)

02:      0/16(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)

03:      0/16(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)

04:      0/16(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)

05:      0/16(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)

06:      0/16(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)

07:      0/16(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)

08:      0/16(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)

09:      0/16(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)

10:      0/16(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)

11:      0/16(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)

12:      0/16(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)

13:      0/16(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)

14:      0/16(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)

15:      0/16(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)

16:      0/16(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)

17:      0/16(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)

18:      0/16(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)

19:      0/16(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)

20:      0/16(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)

21:      0/16(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)

Device-Specific Information:                             d:\rptfile\flexproj.rpt

FLEXPROJ

** CLOCK SIGNALS **

Type     Fan-out    Name

INPUT       14      CLOCK

LCELL       10      |control5:75|CHECK_ROLL

Device-Specific Information:                             d:\rptfile\flexproj.rpt

FLEXPROJ

 ** CLEAR SIGNALS **

Type     Fan-out    Name

INPUT       11      RESET

Device-Specific Information:                             d:\rptfile\flexproj.rpt

FLEXPROJ

** CARRY CHAINS **

Type             Member Length    Member Name: SUM, (CARRY)

ARITHMETIC             1          |eval_box:74|8faddb:45|~189~2, (|eval_box:74|8faddb:45|~189~1)

ARITHMETIC             2          |eval_box:74|8faddb:45|~197~1, (|eval_box:74|8faddb:45|:197)

ARITHMETIC             3                                         (|eval_box:74|8faddb:45|:205)

NORMAL                 4          |eval_box:74|~48~3

ARITHMETIC             1          |dice_gen:79|8fadd:28|~189~1, (|dice_gen:79|8fadd:28|:189)

ARITHMETIC             2          |dice_gen:79|8fadd:28|~197~1, (|dice_gen:79|8fadd:28|:197)

NORMAL                 3          |dice_gen:79|74374:23|:16

Device-Specific Information:                             d:\rptfile\flexproj.rpt

FLEXPROJ

** EQUATIONS **

CLOCK    : INPUT;

RESET    : INPUT;

ROLL_1   : INPUT;

ROLL_2   : INPUT;

SAMPLE   : INPUT;

cmpen    =  _LC2_B12;

D1_1_7   =  _LC8_B5;

D1_2_6   =  _LC6_B10;

D1_3_5   =  _LC1_B1;

D1_4     =  _LC5_B3;

D2_1_7   =  _LC1_B5;

D2_2_6   =  _LC3_B13;

D2_3_5   =  _LC1_B6;

D2_4     =  _LC1_B2;

LOSER    =  _LC2_B7;

out1     =  VCC;

Reset_out =  _LC3_B9;

%  synthesized logic cells %

%  Reset_out~1  %

_LC3_B9  = LCELL(!RESET);

WINNER   =  _LC2_B11;

%  |control5:75|CHECK_ROLL  from file "control5.tdf" line 16, column 7 %

_LC8_B17 = LCELL( _EQ001);

  _EQ001 =  _LC1_B7 & !_LC2_B11;

%  |control5:75|Control~1  from file "control5.tdf" line 12, column 3 %

_LC4_B8  = DFF( _EQ002,  CLOCK, !RESET,  VCC);

  _EQ002 =  _LC5_B20

         # !_LC2_B11 &  _LC4_B8 & !_LC6_B7;

%  |control5:75|Control~2  from file "control5.tdf" line 12, column 3 %

_LC1_B7  = DFF( _EQ003,  CLOCK, !RESET,  VCC);

  _EQ003 =  _LC1_B7 & !_LC2_B11 & !_LC6_B7

         #  _LC5_B7;

%  |control5:75|Control~3  from file "control5.tdf" line 12, column 3 %

_LC7_B7  = DFF( _EQ004,  CLOCK, !RESET,  VCC);

  _EQ004 = !_LC3_B7 &  _LC7_B7

         #  _LC2_B11 & !_LC3_B7

         # !_LC3_B7 &  _LC6_B7;

%  |control5:75|Q0  from file "control5.tdf" line 13, column 16 %

_LC2_B11 = DFF( _EQ005,  CLOCK, !RESET,  VCC);

  _EQ005 =  _LC2_B8

         #  _LC2_B11 & !_LC6_B7;

%  |control5:75|Q1  from file "control5.tdf" line 13, column 16 %

_LC2_B7  = DFF( _EQ006,  CLOCK, !RESET,  VCC);

  _EQ006 =  _LC2_B7 & !_LC6_B7

         #  _LC5_B5

         #  _LC6_B6;

%  |control5:75|Q2  from file "control5.tdf" line 13, column 16 %

_LC2_B12 = DFF( _EQ007,  CLOCK, !RESET,  VCC);

  _EQ007 =  _LC3_B8

         #  _LC2_B12 & !_LC6_B7;

%  synthesized logic cells %

%  |control5:75|WAIT_ROLL~1  from file "control5.tdf" line 15, column 7 %

_LC5_B7  = LCELL( _EQ008);

  _EQ008 = !_LC2_B11 &  _LC5_B8 & !_LC7_B7;

%  |control5:75|:65  from file "control5.tdf" line 38, column 14 %

_LC2_B5  = LCELL( _EQ009);

  _EQ009 = !_LC7_B5 &  _LC8_B16

         #  _LC3_B14 &  _LC3_B15 &  _LC8_B16

         # !_LC3_B14 & !_LC3_B15 &  _LC8_B16;

%  synthesized logic cells %

%  |control5:75|~73~1  from file "control5.tdf" line 41, column 19 %

_LC3_B4  = LCELL( _EQ010);

  _EQ010 =  _LC3_B2

         #  _LC2_B3;

%  synthesized logic cells %

%  |control5:75|~73~2  from file "control5.tdf" line 41, column 19 %

_LC7_B6  = LCELL( _EQ011);

  _EQ011 = !_LC3_B14

         # !_LC3_B15;

%  |control5:75|:73  from file "control5.tdf" line 41, column 19 %

_LC4_B6  = LCELL( _EQ012);

  _EQ012 = !_LC3_B3 & !_LC3_B4 & !_LC4_B2 &  _LC7_B6

         #  _LC3_B3 & !_LC3_B4 &  _LC4_B2 & !_LC7_B6;

%  |control5:75|:74  from file "control5.tdf" line 40, column 6 %

_LC6_B6  = LCELL( _EQ013);

  _EQ013 =  _LC2_B5 &  _LC4_B6 &  _LC8_B17;

%  |control5:75|:81  from file "control5.tdf" line 49, column 6 %

_LC3_B8  = LCELL( _EQ014);

  _EQ014 = !_LC2_B11 &  _LC4_B8 &  _LC5_B8;

%  |control5:75|:86  from file "control5.tdf" line 55, column 5 %

_LC5_B5  = LCELL( _EQ015);

  _EQ015 =  _LC2_B12 & !_LC3_B14 &  _LC3_B15 &  _LC7_B5

         #  _LC2_B12 &  _LC3_B14 & !_LC3_B15 &  _LC7_B5;

%  |control5:75|:92  from file "control5.tdf" line 57, column 6 %

_LC6_B8  = LCELL( _EQ016);

  _EQ016 =  _LC2_B12 &  _LC6_B5 &  _LC7_B4;

%  synthesized logic cells %

%  |control5:75|~109~1  from file "control5.tdf" line 12, column 3 %

_LC4_B7  = LCELL( _EQ017);

  _EQ017 =  _LC5_B20

         #  _LC3_B7

         #  _LC5_B7

         #  _LC3_B8;

%  synthesized logic cells %

%  |control5:75|~109~2  from file "control5.tdf" line 12, column 3 %

_LC2_B8  = LCELL( _EQ018);

  _EQ018 =  _LC6_B8

         # !_LC2_B5 &  _LC8_B17;

%  |control5:75|:109  from file "control5.tdf" line 12, column 3 %

_LC6_B7  = LCELL( _EQ019);

  _EQ019 =  _LC5_B5

         #  _LC6_B6

         #  _LC2_B8

         #  _LC4_B7;

%  synthesized logic cells %

%  |control5:75|~119~1  from file "control5.tdf" line 17, column 7 %

_LC8_B16 = LCELL( _EQ020);

  _EQ020 =  _LC5_B1

         #  _LC4_B18

         #  _LC2_B3

         # !_LC3_B3;

%  synthesized logic cells %

%  |control5:75|~119~2  from file "control5.tdf" line 17, column 7 %

_LC2_B6  = LCELL( _EQ021);

  _EQ021 = !_LC4_B2 & !_LC7_B6

         # !_LC3_B3 & !_LC7_B6

         #  _LC4_B2 &  _LC7_B6

         #  _LC3_B3 &  _LC7_B6

         #  _LC3_B4;

%  synthesized logic cells %

%  |control5:75|~119~3  from file "control5.tdf" line 17, column 7 %

_LC3_B6  = LCELL( _EQ022);

  _EQ022 =  _LC2_B6 &  _LC8_B16 &  _LC8_B17;

%  synthesized logic cells %

%  |control5:75|~119~4  from file "control5.tdf" line 17, column 7 %

_LC5_B20 = LCELL( _EQ023);

  _EQ023 =  _LC3_B6 &  _LC6_B5

         #  _LC2_B12 &  _LC6_B5 & !_LC7_B4;

%  synthesized logic cells %

%  |control5:75|~121~1  from file "control5.tdf" line 15, column 7 %

_LC3_B7  = LCELL( _EQ024);

  _EQ024 =  _LC2_B11 &  RESET

         #  _LC2_B7 &  RESET;

% |dice_gen:79|DIEA0 = |dice_gen:79|74163:39|:34 %

_LC3_B15 = DFF( _EQ025,  CLOCK,  VCC,  VCC);

  _EQ025 = !_LC3_B15 &  ROLL_1

         #  _LC3_B15 & !ROLL_1;

% |dice_gen:79|DIEA1 = |dice_gen:79|74163:39|:35 %

_LC2_B3  = DFF( _EQ026 &  _LC4_B3,  CLOCK,  VCC,  VCC);

  _EQ026 =  _LC1_B3_CARRY & !_LC2_B3

         # !_LC1_B3_CARRY &  _LC2_B3;

% |dice_gen:79|DIEA2 = |dice_gen:79|74163:39|:36 %

_LC3_B3  = DFF( _EQ027,  CLOCK,  VCC,  VCC);

  _EQ027 = !_LC2_B3_CARRY &  _LC3_B3 & !ROLL_1

         # !_LC2_B3_CARRY &  _LC3_B3 & !_LC3_B15

         #  _LC2_B3_CARRY & !_LC3_B3;

% |dice_gen:79|DIEB0 = |dice_gen:79|74163:38|:34 %

_LC3_B14 = DFF( _EQ028,  CLOCK,  VCC,  VCC);

  _EQ028 = !_LC3_B14 &  ROLL_2

         #  _LC3_B14 & !ROLL_2;

% |dice_gen:79|DIEB1 = |dice_gen:79|74163:38|:35 %

_LC3_B2  = DFF( _EQ029,  CLOCK,  VCC,  VCC);

  _EQ029 =  _LC2_B2_CARRY & !_LC3_B2 &  _LC5_B2

         # !_LC2_B2_CARRY &  _LC3_B2 &  _LC5_B2;

% |dice_gen:79|DIEB2 = |dice_gen:79|74163:38|:36 %

_LC4_B2  = DFF( _EQ030,  CLOCK,  VCC,  VCC);

  _EQ030 = !_LC3_B2_CARRY &  _LC4_B2 & !ROLL_2

         # !_LC3_B2_CARRY & !_LC3_B14 &  _LC4_B2

         #  _LC3_B2_CARRY & !_LC4_B2;

%  |dice_gen:79|8fadd:28|:189  %

_LC5_B1_CARRY = CARRY( _EQ031);

  _EQ031 =  _LC3_B14 &  _LC3_B15;

%  |dice_gen:79|8fadd:28|:197  %

_LC6_B1_CARRY = CARRY( _EQ032);

  _EQ032 =  _LC2_B3 &  _LC3_B2

         #  _LC3_B2 &  _LC5_B1_CARRY

         #  _LC2_B3 &  _LC5_B1_CARRY;

%  |dice_gen:79|8fadd:28|:205  %

_LC7_B1_CARRY = CARRY( _EQ033);

  _EQ033 =  _LC3_B3 &  _LC4_B2

         #  _LC4_B2 &  _LC6_B1_CARRY

         #  _LC3_B3 &  _LC6_B1_CARRY;

%  |dice_gen:79|:32  %

_LC5_B2  = LCELL( _EQ034);

  _EQ034 = !_LC4_B2

         # !ROLL_2

         # !_LC3_B14;

%  |dice_gen:79|:40  %

_LC4_B3  = LCELL( _EQ035);

  _EQ035 = !ROLL_1

         # !_LC3_B15

         # !_LC3_B3;

%  |dice_gen:79|74163:38|:99  %

_LC3_B2_CARRY = CARRY( _EQ036);

  _EQ036 =  _LC2_B2_CARRY &  _LC3_B2;

%  |dice_gen:79|74163:38|:100  %

_LC2_B2_CARRY = CARRY( _EQ037);

  _EQ037 =  _LC3_B14 &  ROLL_2;

%  |dice_gen:79|74163:39|:99  %

_LC2_B3_CARRY = CARRY( _EQ038);

  _EQ038 =  _LC1_B3_CARRY &  _LC2_B3;

%  |dice_gen:79|74163:39|:100  %

_LC1_B3_CARRY = CARRY( _EQ039);

  _EQ039 =  _LC3_B15 &  ROLL_1;

%  |dice_gen:79|74374:23|:13  %

_LC1_B4  = DFF( _EQ040,  _LC8_B17,  VCC,  VCC);

  _EQ040 = !_LC3_B14 &  _LC3_B15

         #  _LC3_B14 & !_LC3_B15;

%  |dice_gen:79|74374:23|:14  %

_LC6_B1  = DFF( _EQ041,  _LC8_B17,  VCC,  VCC);

  _EQ041 = !_LC2_B3 &  _LC3_B2 & !_LC5_B1_CARRY

         #  _LC2_B3 &  _LC3_B2 &  _LC5_B1_CARRY

         #  _LC2_B3 & !_LC3_B2 & !_LC5_B1_CARRY

         # !_LC2_B3 & !_LC3_B2 &  _LC5_B1_CARRY;

%  |dice_gen:79|74374:23|:15  %

_LC7_B1  = DFF( _EQ042,  _LC8_B17,  VCC,  VCC);

  _EQ042 = !_LC3_B3 &  _LC4_B2 & !_LC6_B1_CARRY

         #  _LC3_B3 &  _LC4_B2 &  _LC6_B1_CARRY

         #  _LC3_B3 & !_LC4_B2 & !_LC6_B1_CARRY

         # !_LC3_B3 & !_LC4_B2 &  _LC6_B1_CARRY;

%  |dice_gen:79|74374:23|:16  %

_LC8_B1  = DFF( _LC7_B1_CARRY,  _LC8_B17,  VCC,  VCC);

%  synthesized logic cells %

% |dsamp2:68|DOT4~1 = |dsamp2:68|:56 %

_LC6_B3  = LCELL( _EQ043);

  _EQ043 = !_LC2_B3 & !_LC3_B15 &  SAMPLE

         # !_LC3_B3 & !_LC3_B15 &  SAMPLE;

% |dsamp2:68|DOT4 = |dsamp2:68|:56 %

_LC5_B3  = LCELL( _EQ044);

  _EQ044 =  _LC6_B3

         #  _LC5_B3 & !SAMPLE;

%  synthesized logic cells %

% |dsamp2:68|1AND7~1 = |dsamp2:68|:55 %

_LC3_B5  = LCELL( _EQ045);

  _EQ045 =  _LC3_B15 &  SAMPLE

         #  _LC2_B3 &  SAMPLE

         #  _LC3_B3 &  SAMPLE;

% |dsamp2:68|1AND7 = |dsamp2:68|:55 %

_LC8_B5  = LCELL( _EQ046);

  _EQ046 =  _LC3_B5

         #  _LC8_B5 & !SAMPLE;

% |dsamp2:68|2AND6 = |dsamp2:68|:54 %

_LC6_B10 = LCELL( _EQ047);

  _EQ047 =  _LC2_B19 &  _LC3_B15 &  SAMPLE

         #  _LC6_B10 & !SAMPLE;

%  synthesized logic cells %

% |dsamp2:68|3AND5~1 = |dsamp2:68|:53 %

_LC2_B1  = LCELL( _EQ048);

  _EQ048 =  _LC2_B3 & !_LC3_B3 &  _LC3_B15 &  SAMPLE

         # !_LC2_B3 &  _LC3_B3 &  SAMPLE;

% |dsamp2:68|3AND5 = |dsamp2:68|:53 %

_LC1_B1  = LCELL( _EQ049);

  _EQ049 =  _LC2_B1

         #  _LC1_B1 & !SAMPLE;

%  synthesized logic cells %

%  |dsamp2:68|~47~1  %

_LC2_B19 = LCELL( _EQ050);

  _EQ050 = !_LC2_B3 &  _LC3_B3;

%  synthesized logic cells %

% |dsamp2:69|DOT4~1 = |dsamp2:69|:56 %

_LC6_B2  = LCELL( _EQ051);

  _EQ051 = !_LC3_B14 & !_LC4_B2 &  SAMPLE

         # !_LC3_B2 & !_LC3_B14 &  SAMPLE;

% |dsamp2:69|DOT4 = |dsamp2:69|:56 %

_LC1_B2  = LCELL( _EQ052);

  _EQ052 =  _LC6_B2

         #  _LC1_B2 & !SAMPLE;

%  synthesized logic cells %

% |dsamp2:69|1AND7~1 = |dsamp2:69|:55 %

_LC4_B5  = LCELL( _EQ053);

  _EQ053 =  _LC3_B14 &  SAMPLE

         #  _LC4_B2 &  SAMPLE

         #  _LC3_B2 &  SAMPLE;

% |dsamp2:69|1AND7 = |dsamp2:69|:55 %

_LC1_B5  = LCELL( _EQ054);

  _EQ054 =  _LC4_B5

         #  _LC1_B5 & !SAMPLE;

% |dsamp2:69|2AND6 = |dsamp2:69|:54 %

_LC3_B13 = LCELL( _EQ055);

  _EQ055 =  _LC3_B14 & !_LC4_B18 &  SAMPLE

         #  _LC3_B13 & !SAMPLE;

%  synthesized logic cells %

% |dsamp2:69|3AND5~1 = |dsamp2:69|:53 %

_LC5_B6  = LCELL( _EQ056);

  _EQ056 =  _LC3_B2 &  _LC3_B14 & !_LC4_B2 &  SAMPLE

         # !_LC3_B2 &  _LC4_B2 &  SAMPLE;

% |dsamp2:69|3AND5 = |dsamp2:69|:53 %

_LC1_B6  = LCELL( _EQ057);

  _EQ057 =  _LC5_B6

         #  _LC1_B6 & !SAMPLE;

%  synthesized logic cells %

%  |dsamp2:69|~47~1  %

_LC4_B18 = LCELL( _EQ058);

  _EQ058 = !_LC4_B2

         #  _LC3_B2;

% |eval_box:74|POINT = |eval_box:74|:47 %

_LC7_B4  = LCELL( _EQ059);

  _EQ059 =  _LC2_B12 &  _LC5_B4 &  _LC6_B4 &  _LC8_B4;

%  synthesized logic cells %

% |eval_box:74|7~1 = |eval_box:74|encode2:46|:122 from file "encode2.tdf" line 26, column 33 %

_LC5_B1  = LCELL( _EQ060);

  _EQ060 =  _LC3_B14 &  _LC3_B15

         # !_LC3_B14 & !_LC3_B15;

%  synthesized logic cells %

% |eval_box:74|7~2 = |eval_box:74|encode2:46|:122 from file "encode2.tdf" line 26, column 33 %

_LC7_B5  = LCELL( _EQ061);

  _EQ061 =  _LC2_B3 &  _LC3_B2 & !_LC3_B3 & !_LC4_B2

         # !_LC2_B3 & !_LC3_B2 & !_LC3_B3 &  _LC4_B2

         # !_LC2_B3 & !_LC3_B2 &  _LC3_B3 & !_LC4_B2;

% |eval_box:74|7 = |eval_box:74|encode2:46|:122 from file "encode2.tdf" line 26, column 33 %

_LC6_B5  = LCELL( _EQ062);

  _EQ062 = !_LC7_B5

         #  _LC3_B14 &  _LC3_B15

         # !_LC3_B14 & !_LC3_B15;

%  synthesized logic cells %

%  |eval_box:74|8faddb:45|~189~1  %

_LC2_B4_CARRY = CARRY( _LC1_B4_CARRY);

%  synthesized logic cells %

%  |eval_box:74|8faddb:45|~189~2  %

_LC2_B4  = LCELL( _LC1_B4_CARRY);

%  |eval_box:74|8faddb:45|:189  %

_LC1_B4_CARRY = CARRY( _EQ063);

  _EQ063 =  _LC3_B14 &  _LC3_B15;

%  synthesized logic cells %

%  |eval_box:74|8faddb:45|~197~1  %

_LC4_B4  = LCELL( _LC3_B4_CARRY);

%  |eval_box:74|8faddb:45|:197  %

_LC3_B4_CARRY = CARRY( _EQ064);

  _EQ064 =  _LC2_B3 &  _LC3_B2

         #  _LC2_B4_CARRY &  _LC3_B2

         #  _LC2_B3 &  _LC2_B4_CARRY;

%  |eval_box:74|8faddb:45|:205  %

_LC4_B4_CARRY = CARRY( _EQ065);

  _EQ065 =  _LC3_B3 &  _LC4_B2

         #  _LC3_B4_CARRY &  _LC4_B2

         #  _LC3_B3 &  _LC3_B4_CARRY;

%  synthesized logic cells %

%  |eval_box:74|~48~1  %

_LC6_B4  = LCELL( _EQ066);

  _EQ066 = !_LC3_B3 & !_LC4_B2 & !_LC4_B4 & !_LC7_B1

         #  _LC3_B3 & !_LC4_B2 &  _LC4_B4 & !_LC7_B1

         #  _LC3_B3 &  _LC4_B2 & !_LC4_B4 & !_LC7_B1

         # !_LC3_B3 &  _LC4_B2 &  _LC4_B4 & !_LC7_B1

         # !_LC3_B3 &  _LC4_B2 & !_LC4_B4 &  _LC7_B1

         #  _LC3_B3 &  _LC4_B2 &  _LC4_B4 &  _LC7_B1

         #  _LC3_B3 & !_LC4_B2 & !_LC4_B4 &  _LC7_B1

         # !_LC3_B3 & !_LC4_B2 &  _LC4_B4 &  _LC7_B1;

%  synthesized logic cells %

%  |eval_box:74|~48~2  %

_LC8_B4  = LCELL( _EQ067);

  _EQ067 = !_LC2_B3 & !_LC2_B4 & !_LC3_B2 & !_LC6_B1

         #  _LC2_B3 &  _LC2_B4 & !_LC3_B2 & !_LC6_B1

         #  _LC2_B3 & !_LC2_B4 &  _LC3_B2 & !_LC6_B1

         # !_LC2_B3 &  _LC2_B4 &  _LC3_B2 & !_LC6_B1

         # !_LC2_B3 & !_LC2_B4 &  _LC3_B2 &  _LC6_B1

         #  _LC2_B3 &  _LC2_B4 &  _LC3_B2 &  _LC6_B1

         #  _LC2_B3 & !_LC2_B4 & !_LC3_B2 &  _LC6_B1

         # !_LC2_B3 &  _LC2_B4 & !_LC3_B2 &  _LC6_B1;

%  synthesized logic cells %

%  |eval_box:74|~48~3  %

_LC5_B4  = LCELL( _EQ068);

  _EQ068 = !_LC1_B4 & !_LC4_B4_CARRY &  _LC5_B1 & !_LC8_B1

         #  _LC1_B4 & !_LC4_B4_CARRY & !_LC5_B1 & !_LC8_B1

         # !_LC1_B4 &  _LC4_B4_CARRY &  _LC5_B1 &  _LC8_B1

         #  _LC1_B4 &  _LC4_B4_CARRY & !_LC5_B1 &  _LC8_B1;

%  |sync3:78|Debounce~1  %

_LC5_B8  = DFF( _EQ069,  CLOCK,  RESET,  VCC);

  _EQ069 =  _LC1_B8 & !ROLL_1 & !ROLL_2;

%  |sync3:78|Debounce~2  %

_LC1_B8  = DFF( _EQ070,  CLOCK,  RESET,  VCC);

  _EQ070 =  ROLL_2

         #  ROLL_1;

Project Information                                    d:\rptfile\flexprog.rpt

** TIMING ASSIGNMENTS **

                         User       Actual

Type  Location        Assignment    Value     Status   Critical Path

tpd   <default>          30.0 ns    21.1 ns            RESET to Reset_out

tpd   <default>          30.0 ns    31.6 ns   Failed   SAMPLE to D1_1_7

tpd   <default>          30.0 ns    22.7 ns            SAMPLE to D1_2_6

tpd   <default>          30.0 ns    29.7 ns            SAMPLE to D1_3_5

tpd   <default>          30.0 ns    30.8 ns   Failed   SAMPLE to D1_4

tpd   <default>          30.0 ns    31.6 ns   Failed   SAMPLE to D2_1_7

tpd   <default>          30.0 ns    22.3 ns            SAMPLE to D2_2_6

tpd   <default>          30.0 ns    28.1 ns            SAMPLE to D2_3_5

tpd   <default>          30.0 ns    31.1 ns   Failed   SAMPLE to D2_4

tco   cmpen              10.0 ns    22.5 ns   Failed   CLOCK to cmpen, through register |control5:75|Q2

fmax  <default>        10.00 MHz  13.04 MHz            CLOCK to register DIE_B1 to register |control5:75|Q2

Project Information                                        d:\rptfile\flexproj.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands

Design Doctor                          = off

Logic Synthesis:

   Default Synthesis Style             = Normal

      Logic option settings in 'Normal' style for 'FLEX8000' family

      CARRY_CHAIN                      = manual

      CASCADE_CHAIN                    = manual

      DECOMPOSE_GATES                  = on

      DUPLICATE_LOGIC_EXTRACTION       = on

      MINIMIZATION                     = full

      MULTI-LEVEL_FACTORING            = on

      NOT_GATE_PUSH-BACK               = off

      REDUCE_LOGIC                     = off

      REFACTORIZATION                  = on

      REGISTER_OPTIMIZATIONS           = off

      RESYNTHESIZE_NETWORK             = on

      SLOW_SLEW_RATE                   = off

      SUBFACTOR_EXTRACTION             = on

   Other logic synthesis settings:

      Automatic Global Clock           = off

      Automatic Global Clear           = off

      Automatic Global Preset          = off

      Automatic Global Output Enable   = off

      Automatic I/O Cell Registers     = off

Default Timing Specifications:

   tpd                                 = 30ns

   fmax                                = 10MHz

Cut All Bidirectional Feedback Timing Paths = on

Cut All Clear & Preset Timing Paths    = on

Ignore Timing Assignments              = off

Functional SNF Extractor               = off

Linked SNF Extractor                   = off

Timing SNF Extractor                   = on

Optimize Timing SNF                    = off

Generate JEDEC Files                   = off

Generate AHDL TDO File                 = off

Automatic LCELL Insertion              = off

Smart Recompile                        = off

Total Recompile                        = off

Interface Menu Commands

EDIF Netlist Writer                    = off

Verilog Netlist Writer                 = off

VHDL Netlist Writer                    = off

Compilation Times -----------------

   Compiler Netlist Extractor          00:00:02

   Database Builder                    00:00:09

   Logic Synthesizer                   00:00:09

   Partitioner                         00:00:02

   Fitter                              00:00:33

   Timing SNF Extractor                00:00:04

   Assembler                           00:00:35

   ­­­­­­­­­­­­­­­­­­­­­­­­­­          ­­­­­­­­

   Total Time                          00:01:34

See also:

Annotated Report File: Classic, MAX 5000 & MAX 7000 Devices


The following section contains popups for the annotated report file.


--------------------------------------------------------------------------------------------------------------------

----------------------------------Device Summary------------------------------

--------------------------------------------------------------------------------------------------------------------


Chip/POF

List the names of all chip assignments in the project.


Device

Lists the names of each device to which a chip is assigned.


FLEX 8000 Configuration Scheme

Shows the specified FLEX 8000 configuration scheme.


Input Pins

Shows how many input pins in each device are used by the project.


Output Pins

Shows how many output pins in each device are used by the project.


Bidir Pins

Shows how many bidirectional pins in each device are used by the project.


LC

Shows how many logic cells in each device are used by the project.


Shareable Expanders

Shows how many shareable expanders in each device are used by the project (MAX 5000 and MAX 7000 devices only).


% Utilized

Shows the percentage of resources that are used in each device. This number is based on the logic cell count.


Total-----------this popup not in report file; link removed

Lists the totals for Input, Output, and Bidir (bidirectional) Pins, LCs (logic cells), and EXPs (expander product terms). This line appears if the project is partitioned among multiple devices.


User Pins

Lists the total number of user-created pins for Input, Output, and Bidir (bidirectional) Pins, i.e., the total number of pins minus the pins created for inter-device connections. This line always appears if the project is partitioned among multiple devices.


Project Compilation Messages

Lists all warning and error messages (except device-specific messages) generated during compilation. Device-specific warning and error messages appear in the Error Summary Section for each device in the Report File.


Project Timing-Driven Compilation Messages

Lists all timing assignment warning and error messages (except device-specific messages) generated during compilation. Device-specific warning and error messages appear in the Error Summary Section for each device in the Report File.


Auto Global Signals

Lists the node names chosen for any global Clock, Clear, Preset, and Output Enable signals specified with the Global Project Logic Synthesis command.


Multiple Pin Connections

Lists which pins must be connected if the project is partitioned, or if pins must be connected together on a single device. This section also lists pin connections specified with the Connected Pins command or with the INPUTC, OUTPUTC, and BIDIRC primitives in a GDF. This section is omitted if no pins must be connected.


Pin/Location/Chip Assignments

Lists the user-defined and actual pin , logic cell, and chip assignments in the project’s design files.


User Assignments

Lists the chips, pins, and logic cells to which you have assigned nodes.


Actual Assignments (if different)

Lists the chips, pins, and logic cells to which the Compiler has assigned nodes if they differ from your own assignments.


Node Name

Lists the nodes that are assigned to chips, pins, or logic cells.


Clique Assignments

Lists user-defined cliques and the nodes assigned to cliques in the project’s design files. This section may also list the chip and LAB to which the clique is assigned.


Probe Assignments

Lists probe names and the primitive or macrofunction input or output to which they have been assigned in the project’s design files. The input and output names are shown as hierarchical node names.


Probe Name

Lists all probes defined in the project’s design files.


Primitive/Macrofunction

Lists the primitive or macrofunction input or output to which each probe is assigned in hierarchical node name syntax.


State Machine Assignments

Reports state machine assignments made by the Logic Synthesizer for WDFs or AHDL TDFs.

The values of the state bits for each state are reported in the AHDL State Machine Declaration format. This section is omitted if no files in the project contain state machines.


File Hierarchy

Lists the hierarchical names of macrofunctions in the project.


--------------------------------------Device-Specific Information----------------------


Device

Shows the device selected for implementing a chip. The corresponding chip name appears immediately below the Device-Specific Information heading.

Example:

Device-Specific Information:                             d:\rptfile\maxproj.rpt

MAXPROJ

***** Logic for device 'MAXPROJ' compiled without errors.

Device: EPM7096

Turbo: OFF

Security: OFF


FLEX 8000 Option(s)

Shows which FLEX 8000 device options are turned on or off for the current device.


User-Supplied Start-Up Clock

Directs the device to use a user-supplied configuration Clock for initialization on the CLKUSR pin. If this option is turned off, external circuitry is required to provide the initialization Clock on the DCLK pin in the PS and PPS configuration schemes; in the AS, APU, APD, and PPA configuration schemes, the device uses an internal initialization Clock.


Auto-Restart Configuration on Frame Error

Directs the device to restart the configuration process automatically if a data frame error is encountered. If this option is turned off, you must externally direct the device to restart the configuration process if a frame error occurs.

This option is available only in the AS, APU, and APD configuration schemes.


Release Clears Before Tri-States

Directs the device to release the Clear override on the tri-state buffer before releasing the Output Enable signal on registered logic cells and I/O cell registers. If this option is turned off, the Output Enable signals are released before the Clear overrides.


Enable DCLK Output in User Mode

Enables the DCLK pin when the device is operating in user mode after device configuration and initialization have been completed. If this option is turned off, the DCLK pin is disabled when the device operates in user mode.

This option is available only in the AS, APU, APD, and PPA configuration schemes.


Disable Start-Up Time-Out

Disables the time-out error checking that determines whether CONF_DONE pin goes high within 10 Clock cycles after being released by the device. If this option is turned on, the device will continue to wait for CONF_DONE to go high. If this option is turned off, the device drives the nSTATUS pin low at the end of the configuration cycle if the CONF_DONE pin does not go high within 10 Clock cycles.


Enable JTAG Support

Specifies the Enable JTAG Support setting for the current chip and corresponding device assignment as on, off, or default.

If this option is turned on, it enables the circuitry for JTAG boundary-scan testing. If it is turned off, JTAG boundary-scan testing is not available.

If you select the default setting for this option, the Enable JTAG Support setting for the current device is determined by the project default, which is specified with the FLEX 8000 Device Options dialog box.


Turbo Bit

Indicates whether the Turbo Bit is turned on or off for the current device.


Security

Indicates whether the Security Bit is turned on or off for the current device.


Error Summary

Lists all Fitter-generated error messages that apply to the target device. This section appears in the Report File only if the Fitter generates errors when trying to fit the project.


Pin-Out Diagram

The pin-out shows the signals assigned to each pin, pins that must be tied to VCC or GND, and reserved pins that must be left unconnected so they are available to be reprogrammed if the project changes. All named pins must be wired as shown in the pin-out diagram to implement the logic correctly in the programmed device.

For FLEX 8000 devices, pin names preceded by a plus (+) represent reserved dual-purpose pins that are tri-stated during user mode. Similarly, pin names preceded by an asterisk (*) represent dual-purpose pins that drive out in user mode and those preceded by a caret (^) represent dedicated configuration pins.

Code:	Definition:

N.C. 	Not Connected.

VCC 	Dedicated power pin, which must be connected to VCC.

GND 	Dedicated ground pin or unused dedicated input, which must be connected to GND.

RESERVED	Unused I/O pin, which must be left unconnected.


------------------------------------Resource Usage---------------------------------------


Resource Usage

Provides a concise description of how the device uses available resources.

The first part of this section includes a table that shows the number of logic cells, I/O pins (including dedicated input pins), shareable expanders used in each LAB, and external interconnect, expressed as both a ratio and a percentage of the resources available in the target device. If the target device contains multiple LABs and a PIA, each LAB’s connections to the PIA are listed. External interconnections are also shown.

For FLEX 8000 devices, in addition to the number of logic cells and external interconnect, column tracks driven and row tracks driven are shown as both a ratio and a percentage of the resources available in the target device. Clock and Clear/Preset signals are displayed as ratios.

The second part of this section summarizes overall resource utilization.

The first four lines show the number of dedicated input pins, I/O pins, and logic cells that were used to implement the logic in the target device, expressed as both a ratio and a percentage of the resources available. If the logic did not fit, a 0 is shown in these categories.

The remaining lines show how many input pins, input pins connected to I/O cell registers, output pins, output pins connected to I/O cell registers, bidirectional pins, logic cells, flipflops, and synthesized logic cells are needed (after logic synthesis) to implement the logic. These statistics are given regardless of whether or not the logic fits in the device.

If a device does not include a particular resource, related statistics are not included in the Report File.


Logic Array Block

Lists all Logic Array Blocks in a device. The specific logic cells contained within each LAB are also displayed.


Logic Cells

Shows the number of logic cells used in each LAB. Usage is displayed as both a ratio and a percentage of the resources available in the assigned device.


I/O Pins

Shows the number of I/O pins used in each LAB. Usage is displayed as both a ratio and a percentage of the resources available in the assigned device.


Shareable Expanders

Shows the number of shareable expanders used in each LAB. Usage is displayed as both a ratio and a percentage of the resources available in the assigned device.


External Interconnect

Shows the number of external signals that enter the LAB. This number does not include carry or cascade signals that feed into the LAB. Usage is displayed as both a ratio and a percentage of the resources available in the assigned device.


Total dedicated input pins used

Displays the total number of dedicated input pins used to implement the logic in the assigned device. Usage is displayed as both a ratio and a percentage of available resources.


Total I/O pins used

Displays the total number of I/O pins used to implement the logic in the assigned device. Usage is displayed as both a ratio and a percentage of available resources.


Total logic cells used

Displays the total number of logic cells used to implement the logic in the assigned device. Usage is displayed as both a ratio and a percentage of available resources.


Total shareable expanders used

Displays the total number of shareable expanders used to implement the logic in the target device. Usage is displayed as both a ratio and a percentage of resources available. This feature applies only to MAX 5000, MAX 7000, and MAX 7000E devices.


Total turbo logic cells used

Displays the total number of logic cells for which the logic cell Turbo Bit was turned on. Usage is displayed as both a ratio and a percentage of available resources. This feature applies only to MAX 7000 and MAX 7000E devices.


Total shareable expanders not available (n/a)

Displays the total number of shareable expanders that are not available (i.e., expanders that are used as standard product terms). Usage is displayed as both a ratio and a percentage of available resources. This feature applies only to MAX 5000, MAX 7000, and MAX 7000E devices.


Total input pins required

Displays how many input pins are needed, after logic synthesis, to implement the logic. This statistic is given regardless of whether or not the logic fits into the device.


Total output pins required

Displays how many output pins are needed, after logic synthesis, to implement the logic. This statistic is given regardless of whether or not the logic fits into the device.


Total bidirectional pins required

Displays how many output bidirectional pins are needed, after logic synthesis, to implement the logic. This statistic is given regardless of whether or not the logic fits in the device.


Total logic cells required

Displays how many logic cells are needed, after logic synthesis, to implement the logic. This statistic is given regardless of whether or not the logic fits into the device.


Total reserved pins required

Displays how many reserved pins are needed, after logic synthesis, to implement the logic. A pin is required to be reserved if the Reserve option is turned on for it in the Global Project FLEX 8000 Device Options or FLEX 8000 Individual Device Options dialog box.

This statistic is given regardless of whether or not the logic fits into the device.


Total flipflops required

Displays how many flipflops are needed, after logic synthesis, to implement the logic. This statistic is given regardless of whether or not the logic fits into the device.


Total shareable expanders in database

Displays how many shareable expanders are needed, after logic synthesis, to implement the logic. This statistic is given regardless of whether or not the logic fits into the device. This feature applies only to MAX 5000, MAX 7000, and MAX 7000E devices.


Synthesized logic cells

Displays the number of synthesized logic cells that were created to balance the number of shareable expanders used in the device. This feature applies only to MAX 5000, MAX 7000, and MAX 7000E devices.


-------------------------------Resource Usage (FLEX 8000)-----------------------------------


Logic Array Block

Lists all Logic Array Blocks in which at least one logic cell is used.


Column Interconnect Driven

Displays the number of vertical (column) routing paths used in the FastTrack Interconnect that are driven out for each LAB. Usage is displayed as both a ratio and a percentage of available resources.


Row Interconnect Driven

Displays the number of horizontal (row) routing paths used in the FastTrack Interconnect that are driven out for each LAB. Usage is displayed as both a ratio and a percentage of available resources.


Clocks

Displays the number of Clock signals used in an LAB.


Clear/Preset

Displays the number of Clear and Preset signals used in an LAB.


Total input registers required

Displays the number of I/O cell registers required as inputs to the device. Input I/O cell registers synchronize input pin changes to Clock signals.


Total buried I/O cell registers required

Displays the number of buried I/O cell register required as outputs of the device.


Total output registers required

Displays the number of I/O cell registers required as outputs of the device.


Total reserved pins required

Displays the number of reserved pins required for the device. A pin is required to be reserved if the Reserve option is turned on for it in the Global Project FLEX 8000 Device Options or FLEX 8000 Individual Device Options dialog box.

This statistic is given regardless of whether or not the logic fits into the device.


Logic Cell Counts

Displays the number of logic cells used in each LAB of the device. Total logic cells used by the project are given by row and by column.


Total logic cells in carry chains

Displays the number of logic cells that are used in carry chains for the project.


Total logic cells in cascade chains

Displays the number of logic cells that are used in cascade chains for the project.


Total number of cascade chains

Displays the total number of cascade chains for the project.


Total number of cascade chains

Displays the total number of carry chains for the project.


-------------------------------------FastTrack Interconnect Utilization (FLEX 8000)--------------------------------


FastTrack Interconnect Utilization

Provides a concise description of how the FLEX 8000 device uses available device resources.

The first part of this section includes a table that shows all horizontal FastTrack Interconnect paths and I/O pins (including bidirectional pins) by row. Resource usage is displayed as both a ratio and a percentage of resources available in the target device.

The second part of this section displays all vertical FastTrack Interconnect paths and I/O pins (including bidirectional pins) by column.


Row

Displays the row letter of the horizontal FastTrack Interconnect.


FastTrack Interconnect

Displays the number of horizontal (row) FastTrack Interconnect routing paths used by the LAB. Usage is displayed as both a ratio and a percentage of the resources available in the device.


Input Pins

Displays the number of input pins that feed the LAB. Usage is displayed as both a ratio and a percentage of the resources available in the device.


Output Pins

Displays the number of output pins fed by the LAB. Usage is displayed as both a ratio and a percentage of the resources available in the device.


Bidir Pins

Displays the number of bidirectional pins that feed or are fed by the LAB. Usage is displayed as both a ratio and a percentage of the resources available in the device.


Column FastTrack Interconnect


Column

Displays the column number of the vertical FastTrack Interconnect.


FastTrack Interconnect

Displays the number of vertical (column) FastTrack Interconnect routing paths used by the LAB. Usage is displayed as both a ratio and a percentage of the resources available in the device.


-------------------------------------Clock Signals section (FLEX 8000)--------------------------------


Clock Signals

Displays all Clock signal paths by type and lists their fan-outs and signal names.


Type

Lists the type of Clock signal.


Fan-Out

Lists the number of fan-outs from the Clock signal.


Name

Displays the Clock signal name.


-------------------------------------Clear Signals section (FLEX 8000)--------------------------------


Clear Signals

Displays all Clear signal paths by type and lists their fan-outs and signal names.


Type

Lists the type of Clear signal.


Fan-Out

Lists the number of fan-outs from the Clear signal.


Name

Displays the Clear signal name.


-------------------------------------Carry Chains section (FLEX 8000)--------------------------------


Carry Chains

Displays all carry chains paths by the type and number of each member of the carry chain. Both the SUM and CARRY path names are displayed.


Type

Lists the type of carry chains.


Member Length

Lists the length of each member of the carry chain.


Member Number: SUM (CARRY)

Lists the path for each member of the carry chain: the SUM portion is shown without parenthesis and the CARRY portion is shown with parenthesis.


--------------Inputs, Outputs, Buried Logic------------------------


Inputs

Lists all inputs to the device.


Outputs

Lists all outputs of the device.


Buried Logic

Lists all buried logic in the device.


Pin

Shows the pin assigned to the node or pin listed under Name.


LC

Shows the logic cell number assigned to the node or pin listed under Name.


LAB

Shows the LAB assigned to the node or pin listed under Name.


Primitive

Shows the name of the primitive associated with the node or pin listed under Name. Various symbols may appear after this primitive name:

+	A name followed by a plus symbol (+) indicates that the Clock input to the primitive (i.e., a flipflop or latch) is a global signal.

s	A SOFT primitive name followed by an s indicates that the Logic Synthesizer added the primitive to balance the number of logic cell and shareable expanders used by the device. (If your Report File contains many of these synthesized SOFT buffers, you may be able to improve device utilization by inserting SOFT buffers into your design files.)

s	An INPUT primitive name followed by an s means that the Partitioner created the input when the project was partitioned.

t	A name followed by a t indicates that the logic cell Turbo Bit is turned on for the node in a MAX 7000 or MAX 7000E device.

g	A name followed by a g indicates that the primitive is assigned to a global logic cell in an EP1810 Classic device.

/	A name followed by a / indicates that the output pin has been set to a slow slew rate in a FLEX 8000 or MAX 7000E device.

If MAX+PLUS II creates a logic cell for parallel expanders, the term PEXP appears in the Primitive column.


Shareable Expanders

Lists the number of Total, Shared, and n/a shareable expanders used. The Total figure indicates how many expanders are used in the logic cell associated with the node. The Shared figure indicates how many of these expanders are also shared with (i.e., used in) another logic cell. The n/a figure shows the number of expanders that are not available (e.g., expanders that are used as standard product terms).


Fan-In

Lists the number of fan-ins -- the number of inputs (INP) from dedicated input and/or I/O pins, and the number of feedbacks (FBK) from other logic cells, that feed the logic cell associated with the pin.


Fan-Out

Lists the number of fan-outs -- the number of outputs (OUT) from dedicated output and/or I/O pins, and the number of feedbacks (FBK) from other logic cells, that feed the logic cell associated with the pin.


Name

Shows the pin name (or buried logic cell node name) assigned by the user. If bidirectional pins have been used (i.e., with dual I/O feedback), the pin name is shown in both the Inputs and Outputs Sections. For PEXP primitives, a name is created. Another name may be added in parentheses; the two names will be synonymous.


-----------------------------Inputs, Outputs, Buried Logic FLEX 8000 ------------------


Fed By LC

Displays the location of the logic cell that feeds the output. This logic cell can be either either be the associated I/O cell registers logic cell or another logic cell within an LAB.


Row

Shows the row letter assigned to the node listed under Name.


Col

Shows the column number assigned to the node listed under Name.


----------------------------------------Logic Cell Interconnections--------------------------------------


Logic Cell Interconnections

Displays logic connectivity in a device by showing all logic cells and pins that feed individual logic cells. Logic cell interconnections are provided for each LAB.


LC <number>

Logic cell number in the current LAB.


A B C D E F etc.

Names of all LABs available in the device.


LCell

Logic cell number that feeds the logic cell(s) in the current LAB.

If the number is enclosed in parentheses ( ), the logic cell is buried.


Pin

Pin number that feeds the logic cell(s) in the current LAB.


*, -, @

Symbols indicating which logic cells are fed by the node. A node is considered to feed a logic cell if it feeds a D, T, SR, or JK flipflop or a latch; or the clrn, prn, oe, ena (clock), ena (latch), or clk input.


Name

Name of the input or output node associated with the pin or logic cell that feeds the logic cell(s) in the current LAB.


Logic Array Block "D"

Name of the LAB for which logic connectivity is displayed.


-------------------------------------------------Equations------------------------------------------------------------


Equations

Lists the minimized equations, expressed with pin names, probe names, and hierarchical node names, for all logic in the project. Since logic synthesis minimizes the logic required to implement a project, redundant or unneeded logic in the original design files may not appear in the Report File.

An equation can have any of the following formats:

<Q output> = DFF(<D input>, <Clock>, <Clear>, <Preset>);

<Q output> = DFFE(<D input>, <Clock>, <Clear>, <Preset>, <Clock Enable>);

<Q output> = TFF(<T input>, <Clock>, <Clear>, <Preset>);

<Q output> = TFFE(<T input>, <Clock>, <Clear>, <Preset>, <Clock Enable>);

<Q output> = LATCH(<D input>, <Latch Enable>);

<pin name> = TRI(<input>, <Output Enable>);

<pin name> = _LC<name>;

_LC<name> = LCELL(<input>);

_LC<name>_CARRY = CARRY(<input>);

_X<number> = EXP(<expression>);

<symbol> = <expression>;

The equations use AHDL Arithmetic Operators in Boolean Expressions.


<pin name>: Input

List of all input pins used in the device.


 % D1 1 7 = |dsamp2:68|1AND7 %

Full hierarchical pathname for the source.D1 1 7


 _LC081 = LCELL (_EQ002 $ VCC )

Logic cell number 81 has inputs EQ002 XOR VCC


 Equation Components & Operators

Equation 2 is defined by the following components and logic operators:

Equation Components:

_MC<number>	Represents a node that has been assigned to the specified logic cell number.

_X<number>	Represents a node that has been assigned to an expander product term.

_N<number>	Represents a node that the Fitter could not assign to either a pin or a logic cell.

_EQ<number>	Represents another equation in this section.

Equation Logic Operators

&	AND operator.

!	NOT operator.

#	OR operator.

$	XOR (exclusive-OR) operator.


% Synthesized Logic Cell %

Equations for logic cells synthesized by the Compiler are preceded by % Synthesized Logic Cell % .


%_MC<number> borrows parallel expanders from _MC<number> (_MC<number>) %

Identifies logic cells that borrow parallel expanders from adjacent logic cells.


%_MC<number> lends parallel expanders to _MC<number> %

Identifies logic cells that lend parallel expanders to adjacent logic cells.


Timing Assignments

Lists each type of timing assignments and the nodes to which they have been assigned in the project’s design files.


Compilation Settings & Times

Lists the settings for commands on the Compiler’s Processing and Interfaces menus, the total time required to compile the project, and compilation times for individual Compiler modules and utilities.


Compilation Times

Lists the total time required to compile the project and compilation times for individual Compiler modules.


-------------------------------------------------Timing Assignments------------------------------------------------------------


Type

Lists the type of timing assignments specified: tpd, tco, tsu, and/or fmax.


Location

Lists the node for which the timing assignments is specified. If you specified a default timing assignment for the entire project, <default> appears in this column.


User Assignments

Lists the timing specifcations you have assigned for the specified nodes.


Actual Value

Lists the actual timing value acheived during compilation.


Status

Shows the timing status. If the timing specifications were met, nothing appears in this column. If the timing specifications were not met, the word "Failed" appears in this column.


Critical Path

Shows the critical timing path for the node listed under Location.


-----BEGINNING OF NON-TRANSLATED TEXT-----

keep this note:

some options in the Adjusting a Fit proc. say they are only for FLEX 8000 or FLEX 10K devices (we dont usually say that, but...)

auto lcell insertion:

add lcells between user-assigned input pins and the logic they feed

add lcells between logic and user-assigned output pins

when the user-defined pin assignments cannot otherwise be implemented. inserting lcells helps to separate the device input or output from the desired project logic, thereby giving the Compiler more flexibility in implementing the project. alternate:? reduces the routing requirements so that an input needs to feed only one destination rather than multiple destinations.

2nd para: ...only if user-defined pin assignments would...

4ht para:...you may wish to instead remove pin and logic cell assignments and turn on Ignore...

general change: user-defined resource assignments -> user-defined pin assignments

-----END OF NON-TRANSLATED TEXT-----


Compiler Procedures
Procedures

Assignments & Compiler Configuration Settings

Assigning a Clique

Assigning a Device

Assigning a Pin, Location, or Chip

Assigning a Probe

Assigning an Individual Logic Option or Synthesis Style

Assigning Connected Pins

Assigning Individual Timing Requirements

Bank-Annotating Assignments for a Project

Clearing Assignments for a Project

Converting an Obsolete Assignment Format

Copying a Resource Assignment

Defining a Logic Synthesis Style

Deleting an Assignment

Guidelines for Working with Assignments

Ignoring Project Assignments during Compilation

Logic Synthesis Style & Logic Option Rules

Searching the Node Database

Specifying Devices for Automatic Device Selection

Specifying Global Project FLEX 8000 Device & Pin Options

Specifying Global Project Logic Synthesis Settings

Specifying Global Project Security Bit & Reserved Resource Settings

Specifying Global Project Timing Requirements

Specifying Individual Device Security & Turbo Bit Options

Specifying Individual FLEX 8000 Device & Pin Options

File Management

Creating a New File

Opening a File

Fitting

Adjusting the Fit During Compilation

Checking the Partitioner & Fitter Status During Compilation

Fitting & Refitting a Project

Specifying Fitter Settings

Hierarchy

Navigating the Hierarchy

Updating the Hierarchy

Input & Output Files

Combining & Converting SRAM Object Files

Combining Multiple Projects for Simulation

Compiling EDIF Input Files

Compiling OrCAD Schematic Files

Compiling Xilinx Netlist Format Files

Compiling VHDL Design Files

Creating a Functional Simulator Netlist File

Creating a Timing Simulator Netlist File

Creating an AHDL TDO File

Creating EDIF Output Files

Creating Verilog Output Files

Creating VHDL Output Files

Setting Report File Options

MAX+PLUS II Management

Changing Colors in MAX+PLUS II

Closing a MAX+PLUS II Application

Creating & Using a Local Copy of the maxplus2.ini File

Entering an Authorization Code

Exiting from MAX+PLUS II

Specifying a User Library

Starting MAX+PLUS II Applications

Switching Between MAX+PLUS II Applications

Messages

Getting Help on a Message

Locating the Source of a Message

Project Management

Archiving a Project

Changing the Project Name

Checking Project Reliability with the Design Doctor

Combining Multiple Projects for Simulation

Partitioning a Project

Automatic Partitioning

Guiding the Partitioner

Viewing the Results of Partitioning

Renaming a Macrofunction in the Current Project

Running the Compiler

Compiling a Project

Compiling a Project with Smart Recompile

Starting & Stopping the Compiler

Totally Recompiling a Project

Text

Selecting Text

See also:

Third-Party Interfaces Help Contents


Adjusting the Fit During Compilation (Compiler)
Adjusting the Fit During Compilation

During a compilation, the Compiler allows you to adjust the fit of a project if it does not fit with the resource assignments or other compilation settings that you have entered.

You can allow the Compiler to ignore certain user resource assignments, reassign chips that were assigned to specific devices to AUTO, add extra devices, and to use resources that were previously reserved. The Compiler can be directed to ignore all pin assignments or you can specify exactly which pin assignments to ignore.

You can also allow the Compiler to insert LCELL buffers (i.e., insert logic cells) if they are needed to achieve a fit when user-defined pin assignments would otherwise prevent the project from fitting. Inserting an LCELL buffer gives the Compiler more flexibility to fit the project by helping to separate pin inputs and outputs from the project logic. The Compiler can be directed to insert LCELL buffers automatically or you can specify exactly which pins should have LCELL buffers inserted.

If the Compiler is unable to fit a project, it displays a message that asks whether you wish to modify some of your assignments. If you choose No, the Compiler terminates compilation and generates a Report File. If you choose Yes, the Override User Assignments dialog box is displayed.

To adjust the fit of a project with the Override User Assignments and Edit Pin Assignments & LCELLs dialog boxes:

1.	Read the message in the Error Message box.

2.	Find out more about the message by choosing Help on Message. MAX+PLUS II Help provides guidance on specific actions to take to adjust the fit.

3.	If you wish, turn on one or more of the following options:

Under OK to Ignore, turn on Cliques, Chips/Pins/Buried LCs, All Pins/All Buried LCs, Minimal Pins/All Buried LCs, or Buried LCs to ignore assignments made in the project’s design files.

Under OK to Ignore, turn on Reserved Resources to ignore the percentage of reserved device resources that was specified with Global Project Device Options (Assign menu).

Turn on Auto LCELL Insertion to allow the Compiler to automatically insert LCELL buffers.

Turn on Add Extra Devices as Needed to add any additional devices needed to fit the project.

Turn on Change to Auto Device Selection to treat all chips that you assigned to specific devices as if they are assigned to AUTO.

4.	If you wish to open the Edit Pin Assignments & LCELLs dialog box, choose the Edit Pin Assignments & LCELLs button.

a.	In the Edit Pin Assignments & LCELLs dialog box, select one or more lines in the multi-column list box and choose one of the following alternatives:

If you wish to ignore a logic cell for the selected Pin Name, turn the Insert LCELL checkbox option on. If you turn this option on, an x appears in the Insert LCELL column of the multi-column list box. This option is available only if Ignore Pin Assignment is turned off.

If you wish to ignore an existing user-defined pin assignment for the selected Pin Name, turn the Ignore Pin Assignment checkbox option on. If you turn this option on, an x appears in the Ignore Pin Assignment column of the multi-column list box.

Altera recommends that you either insert an LCELL buffer or ignore the pin assignment for each pin that is causing problems with fitting.

b.	If necessary, repeat step 4a to edit additional pin assignments and logic cells.

c.	Choose OK to return to the Override User Assignments dialog box.

5.	Choose OK in the Override User Assignments dialog box.

The Compiler continues compilation and attempts to fit the project again with the changes you have specified. If the Compiler still cannot fit the project, it reissues the message that asks whether you wish to modify some of your assignments, and allows you to adjust the fit again to enter additional changes.

If you modify your resource assignments with the Override User Assignments and/or Edit Pin Assignments & LCELLs dialog boxes, the project’s design files are not automatically updated with the new assignments. To update them, you must back-annotate the assignments after compilation is completed.

Be sure to refer to Guidelines for Working with Assignments for absolutely essential information on using all types of resource, probe, and device assignments.

See also:

Assigning a Clique

Assigning a Device

Assigning a Pin, Location, or Chip

Back-Annotating Assignments for a Project

Fitting & Refitting a Project

Partitioning a Project

Specifying Devices for Automatic Device Selection

Specifying Global Project Security Bit & Reserved Resource Settings


Checking the Partitioner & Fitter Status During Compilation (Compiler)
Checking the Partitioner & Fitter Status During Compilation

During a compilation, the Compiler allows you to check the fit of a project.

To check the fitting status during compilation, follow these steps:

1.	Choose the Stop/Show Status button in the Compiler window. The Stop button changes into the Stop/Show Status button appears in place of when the Fitter and Partitioner modules of the Compiler are processing the project.

The Partitioner Fitter Status dialog box is displayed, listing all chips in the project and their fitting status.

2.	Choose the Stop Compilation button to stop the compilation completely. After you choose Stop Compilation, you can choose the Start button to recompile the project from the beginning. However, Compiler Netlist Extractor warning messages may not be redisplayed unless you turn on Total Recompile (Processing menu) before recompiling.

or:

Choose the Continue Compilation button to continue project compilation.

or:

Choose the Stop After This Attempt button to allow the Fitter to complete the current fitting attempt. If the fitting attempt is successful, the Compiler continues project compilation. If the fitting attempt is unsuccessful, the Compiler stops compiling the project and generates a Report File.

or:

Choose the Stop & Generate Report File button to stop the current fitting attempt and generate a Report File.

See also:

Adjusting the Fit During Compilation

Partitioning a Project


Fitting & Refitting a Project (Compiler)
Fitting & Refitting a Project

You can use a variety of techniques to implement your project successfully in Altera device(s). The following help topics provide information on steps you can take to create a project that will fit successfully the first time:

Guidelines for Working with Assignments provides absolutely essential information on using all types of resource, probe, and device assignments, including logic synthesis style and logic option assignments.

Guidelines for First-Time Project Fitting describes steps you can take to help ensure a successful fit during the first compilation for a project.

If your project does not fit after the first compilation, follow these suggestions:

If the Compiler indicates that your project uses too many resources to fit into the current device(s), you should select larger device(s) or allow the Compiler to automatically assign devices or re-partition the project. For additional information, go to:

Assigning a Device

Partitioning a Project

Specifying Devices for Automatic Device Selection

If the Report File indicates that the target device(s) have enough resources to implement your project, but the project does not fit, you may need to change the resource assignments, the logic synthesis and fitting settings, and/or change the project logic. For suggestions on how to change these aspects of a project, go to:

Classic, MAX 5000, MAX 7000 & MAX 9000 Device "No Fit" Refitting Suggestions

FLEX 8000 and FLEX 10K Device "No Fit" Refitting Suggestions

 	If the preceding "No Fit" suggestions do not lead you to a successful fit, and the project uses a high proportion of the available logic cells, you may need to change the resource assignments, the logic synthesis and fitting settings, and/or change the project logic. For suggestions on how to change these aspects of a project, go to:

Reducing Logic Cell Usage in Classic, MAX 5000, MAX 7000 & MAX 9000 Devices

Reducing Logic Cell Usage in FLEX 8000 and FLEX 10K Devices

 	If your project fits, but lacks the speed that you require, you may need to change the resource assignments, the logic synthesis and fitting settings, and/or change the project logic. For suggestions on how to change these aspects of a project, go to Guidelines for Achieving Maximum Speed Performance.


Guidelines for First-Time Project Fitting (Compiler)
Guidelines for First-Time Project Fitting

The following golden rules will help you improve project fitting:

Be sure to refer to Guidelines for Working with Assignments for absolutely essential information on using all types of resource, probe, and device assignments, including logic synthesis style and logic option assignments.

Specify some of the device’s I/O pins or logic cells to be reserved resources to allow additional logic capacity for future use. Specify a percentage for the I/O Pins or Logic Cells options under Reserved Resources in the Global Project Device Options dialog box (Assign menu). Altera recommends the following settings:

Family:	Logic Cells:	Pins:

Classic	  0%	  0%

MAX 5000	10%	20%

MAX 7000	10%	20%

MAX 9000	20%	20%

FLEX 8000	20%	20%

FLEX 10K	20%	20%

Altera strongly recommends that you allow the Compiler to choose pin, logic cell, and I/O cell assignments until the project is near completion. Allowing the Compiler to make the earlier assignments is most likely to yield a successful fit. Later, you can back-annotate the assignments and edit them if necessary.

Implement global Clock and Clear signals by feeding a pin-driven dedicated input signal through a GLOBAL buffer. You can also allow the Compiler to choose global signals automatically by turning on the Clock and Clear options under Automatic Global in the Global Project Logic Synthesis dialog box (Assign menu).

(MAX 7000 and MAX 9000 devices) Use parallel expanders for speed-critical paths only. You can turn the Parallel Expanders logic option off in the default logic synthesis style for the project with the Define Synthesis Style dialog box (Assign menu), which is available through the Global Project Logic Synthesis dialog box. To re-apply the Parallel Expanders logic option to individual logic functions on speed-critical paths, set the option in the Individual Logic Options dialog box (Assign menu), which is available from the Logic Options dialog box (Assign menu). You should also ensure that the Turbo Bit logic option is turned on for speed-critical paths.

(FLEX 8000 and FLEX 10K devices) Use carry chains for speed-critical paths only. You can set the Carry Chain logic option to Ignore in the default logic synthesis style for the project with the Define Synthesis Style dialog box, which is available through the Global Project Logic Synthesis dialog box. You can also set Max. Auto Length for the Carry Chain option to a smaller number in the Define Synthesis Style dialog box. To re-apply the Manual or Auto setting to individual logic functions on speed-critical paths, set the option in the Individual Logic Options dialog box, which is available from the Logic Options dialog box.

If your project does not fit successfully during its first compilation, go to Fitting & Refitting a Project for additional help.

See also:

Adjusting the Fit During Compilation

Back-Annotating Assignments for a Project

Clearing Assignments for a Project

Specifying Fitter Settings


FLEX 8000 Device "No Fit" Refitting Suggestions
FLEX 8000 & FLEX 10K Device "No Fit" Refitting Suggestions

If the Report File indicates that the target device(s) have enough resources to implement your FLEX 8000 or FLEX 10K project, but the project does not fit, try the following steps:

1.	Get help on each Message Processor message that appears when you compile your project, follow the suggested action, and recompile the project:

a.	Select the message by clicking Button 1 on it or by clicking the left or right side of the Message button to scroll through the messages.

b.	Choose the Help on Message button.

2.	If you have not already done so, refer to Guidelines for First-Time Project Fitting for suggestions.

3.	Turn on the Automatic I/O Cell Registers option in the Global Project Logic Synthesis  dialog box (Assign menu). This option allows the Compiler to use I/O cell registers to implement logic when appropriate, thereby making more logic cells available for other signals.

4.	If you are willing to discard any buried logic cell assignments, use the Override User Assignments and Edit Pin Assignments & LCELLs dialog boxes that appear during compilation if you indicate that you wish to modify your assignments. You can also demote assignments with the Floorplan Editor’s Demote Assignments command (Assign menu), or direct the Compiler to ignore logic cell assignments with Ignore Project Assignments (Assign menu). You can also delete some or all user-defined resource and device assignments with Clear Project Assignments or Pin/Location/Chip (Assign menu). See Deleting an Assignment for more information.

5.	If you are willing to discard some or all of your pin assignments, use the Override User Assignments and Edit Pin Assignments & LCELLs dialog boxes that appear during compilation if you indicate that you wish to modify your assignments. You can also demote assignments with the Floorplan Editor’s Demote Assignments command, or direct the Compiler to ignore logic cell assignments with Ignore Project Assignments. You can also delete some or all user-defined resource and device assignments with Clear Project Assignments or Pin/Location/Chip. See Deleting an Assignment for more information. If you cannot change your pin assignments, skip to the next step.

6.	Choose Fitter Settings (Processing menu) and select the Advanced Try Harder/Longer Compilation Fitting option. You can manually re-enter successful Fitter settings as Custom Fitting settings to preserve them in subsequent compilations, as described in Specifying Fitter Settings.

7.	If you must retain your current pin assignments, you can break chains of CARRY and CASCADE buffers used in the project’s design files into 4- or 5-logic cell lengths by inserting LCELL buffers, or allow the Compiler to ignore CARRY and CASCADE buffers with one of two methods:

a.	Change the definition of the default logic synthesis style for the project with the Define Synthesis Style dialog box so that the Cascade Chain and Carry Chain options are set to Ignore, or change the default logic synthesis style to Normal with the Global Project Logic Synthesis command (Assign menu). In the pre-defined Altera settings for the Normal style, the Cascade Chain and Carry Chain options are set to Ignore.

b.	For each CARRY or CASCADE buffer in the top-level design file or each macrofunction that contains CARRY and CASCADE buffers, including Altera-provided family-specific macrofunctions, apply an individual logic option setting of CARRY_CHAIN=IGNORE or CASCADE_CHAIN=IGNORE. If the project fits after these changes, you can then try removing the Ignore setting on selected logic functions to increase the speed of the project.

8.	Reduce the fan-out of input, output, and buried signals listed in the Inputs, Outputs, and Buried Logic sections of the Report File. To reduce the fan-outs, duplicate the signals by creating one or more copies of the original signal, then feed each signal to a different portion of the project logic. You must also turn off the Register Optimization and Duplicate Logic Extraction logic options for the original signal and all copies with the Advanced Options dialog box, which is available from the Individual Logic Options dialog box that can be opened from the Logic Options dialog box (Assign menu). Otherwise, the Compiler may combine the original signal with the copy or copies.

9.	If the preceding "No Fit" suggestions do not lead you to a successful fit and if the project uses a high proportion of the available logic cells, you can try additional steps to reduce logic cell usage, as described in Reducing Logic Cell Usage in FLEX 8000 & FLEX 10K Devices.

10.	Simplify the logic in the project.

11.	If you require additional assistance, contact Altera Applications.

See also:

Adjusting the Fit During Compilation

Back-Annotating Assignments for a Project

Clearing Assignments for a Project

Fitting & Refitting a Project

Specifying Fitter Settings


Classic, MAX 5000, MAX 7000 & MAX 9000 Device "No Fit" Refitting Suggestions

If the Report File indicates that the target device(s) have enough resources to implement your Classic, MAX 5000, MAX 7000, or MAX 9000 project, but the project does not fit, try the following steps:

1.	Get help on each Message Processor message that appears when you compile your project, follow the suggested action, and recompile the project:

a.	Select the message by clicking Button 1 on it or by clicking the left or right side of the Message button to scroll through the messages.

b.	Choose the Help on Message button.

2.	If you have not already done so, refer to Guidelines for First-Time Project Fitting for suggestions.

3.	(MAX 5000, MAX 7000, and MAX 9000 devices) Turn on the Multi-Level Synthesis option in the Global Project Logic Synthesis dialog box (Assign menu).

4.	If you are willing to discard any buried logic cell assignments, use the Override User Assignments and Edit Pin Assignments & LCELLs dialog boxes that appear during compilation if you indicate that you wish to modify your assignments. You can also demote assignments with the Floorplan Editor’s Demote Assignments command (Assign menu), or direct the Compiler to ignore logic cell assignments with Ignore Project Assignments (Assign menu). You can also delete some or all user-defined resource and device assignments with Clear Project Assignments or Pin/Location/Chip (Assign menu). See Deleting an Assignment for more information.

5.	If you are willing to discard some or all of your pin assignments, use the Override User Assignments and Edit Pin Assignments & LCELLs dialog boxes that appear during compilation if you indicate that you wish to modify your assignments. You can also demote assignments with the Floorplan Editor’s Demote Assignments command, or direct the Compiler to ignore logic cell assignments with Ignore Project Assignments. You can also delete some or all user-defined resource and device assignments with Clear Project Assignments or Pin/Location/Chip. See Deleting an Assignment for more information. If you cannot change your pin assignments, skip to the next step.

6.	(MAX 9000 devices) Turn on the Automatic I/O Cell Registers option in the Global Project Logic Synthesis  dialog box (Assign menu) . This option allows the Compiler to use I/O cell registers to implement logic when appropriate, thereby making more logic cells available for other signals.

7.	Try each of the following combinations of Fitter Settings (Processing menu) and Global Project Logic Synthesis (Assign menu) settings in order. After each step, you should recompile the project to see if the fit is successful. If you still experience fitting problems, go on to the next step.

Custom Fitting

Order	Multi-Level 	Advanced Try 	Fan-In per 	Row Pins with

Synthesis 	Harder/Longer 	Logic Cell 	Fan-Out Greater than

Compilation Fitting	% of the Logic Cells

1

2

3	90%	50%

4	80	50

5	70	50

6	60	50

7	90	10

8	80	10

9	70	10

10	60	10

8.	Reduce the fan-out of input, output, and buried signals listed in the Inputs, Outputs, and Buried Logic sections of the Report File. To reduce the fan-outs, duplicate the signals by creating one or more copies of the original signal, then feed each signal to a different portion of the project logic. You must also turn off the Register Optimization and Duplicate Logic Extraction logic options for the original signal and all copies with the Advanced Options dialog box, which available from the Individual Logic Options dialog box that can be opened from the Logic Options dialog box (Assign menu) . Otherwise, the Compiler may combine the original signal with the copy or copies.

9.	If the preceding "No Fit" suggestions do not lead you to a successful fit and if the project uses a high proportion of the available logic cells, you can try additional steps to reduce logic cell usage, as described in Reducing Logic Cell Usage in Classic, MAX 5000, MAX 7000 & MAX 9000 Devices.

10.	Simplify the logic in the project.

11.	If you require additional assistance, contact Altera Applications.

See also:

Adjusting the Fit During Compilation

Back-Annotating Assignments for a Project

Clearing Assignments for a Project

Fitting & Refitting a Project

Specifying Fitter Settings


Reducing Logic Cell Usage in Classic, MAX 5000, MAX 7000 & MAX 9000 Devices

If your project does not fit after you have followed the Classic, MAX 5000, MAX 7000 & MAX 9000 Device "No Fit" Suggestions and the project uses a high proportion of the available logic cells, you may need to change the resource assignments, the logic synthesis and fitting settings, and/or change the project logic to use fewer logic cells. You can try several techniques for reducing logic cell usage:

Although these techniques can reduce logic cell usage, in some cases they will make your project more difficult to fit.

1.	(MAX 9000 devices) Turn on the Automatic I/O Cell Registers option in the Global Project Logic Synthesis dialog box (Assign menu) . This option allows the Compiler to use I/O cell registers to implement logic when appropriate, thereby making more logic cells available for other signals.

2.	(MAX 5000, MAX 7000, and MAX 9000 devices) Turn on the Multi-Level Synthesis option in the Global Project Logic Synthesis dialog box.

3.	Choose Fitter Settings (Processing menu) and choose the Customize button to open the expanded Fitter Settings dialog box and display all settings. Select Custom Fitting, then specify a larger number (i.e., greater than 100%) for the Expanders per Logic Cell option.

4.	Specify a smaller number for the Fan-In per Logic Cell option in the expanded Fitter Settings dialog box.

5.	Select Fast as the Global Project Synthesis Style--i.e., the default logic synthesis style for the project--in the Global Project Logic Synthesis  dialog box. The Altera-provided Fast style for each device family is tailored to provide speed optimization, which can somethimes have the effect of reducing logic cell usage.

In MAX 7000 and MAX 9000 projects, the Parallel Expanders logic option is turned on in this style. As an alternative to using the Fast logic synthesis style, you can turn Parallel Expanders on in the current default logic synthesis style for your project. You can change the style definition with the Define Synthesis Style dialog box (Assign menu) , which is available through the Global Project Logic Synthesis dialog box.

6.	Simplify the logic in the project.

7.	If you require additional assistance, contact Altera Applications.

See also:

Adjusting the Fit During Compilation

Back-Annotating Assignments for a Project

Clearing Assignments for a Project

Fitting & Refitting a Project

Specifying Fitter Settings


Reducing Logic Cell Usage in FLEX 8000 & FLEX 10K Devices

If your project does not fit after you have followed the FLEX 8000 Device "No Fit" Suggestions and the project uses a high proportion of the available logic cells, you may need to change the resource assignments, the logic synthesis and fitting settings, and/or change the project logic to use fewer logic cells. You can try several techniques for reducing logic cell usage:

Although these techniques can reduce logic cell usage, in some cases they will make your project more difficult to fit.

1.	Turn on the Automatic I/O Cell Registers option in the Global Project Logic Synthesis dialog box (Assign menu) . This option allows the Compiler to use I/O cell registers to implement logic when appropriate, thereby making more logic cells available for other signals.

2.	Select Fast as the Global Project Synthesis Style--i.e., the default logic synthesis style for the project--in the Global Project Logic Synthesis  dialog box. The Altera-provided Fast style for each device family is tailored to provide speed optimization.

In FLEX 8000 and FLEX 10K projects, two of the logic options in this style, Carry Chain and Cascade Chain, are set to Auto. As an alternative to using the Fast logic synthesis style, you can set these logic options to Auto in the current default logic synthesis style for your project. You can change the style definition with the Define Synthesis Style dialog box  (Assign menu), which is available through the Global Project Logic Synthesis dialog box.

3.	Simplify the logic in the project.

4.	If you require additional assistance, contact Altera Applications.

See also:

Adjusting the Fit During Compilation

Back-Annotating Assignments for a Project

Clearing Assignments for a Project

Specifying Fitter Settings


Guidelines for Achieving Maximum Speed Performance

If your project fits, but lacks the speed that you require, try the following techniques for increasing the speed.

The suggestions given here may work differently for different cases. Therefore, for all suggestions that do not include the use of timing assignments, you should try each suggestion individually, then combine any that increase the speed. For steps that include the use of timing assignments, try each step in order.

1.	Change your project logic to replace array (gated) Clock and Clear signals with faster global Clock and Clear signals.

2.	Specify a device with a faster speed grade. Turn on Show All Packages & Speed Grades in the Device dialog box  (Assign menu) to display all speed grade options. Select a device with a faster speed grade from the Devices box.

You can also select AUTO in the Device dialog box to allow the Compiler to automatically select a device or partition the project among multiple devices. To ensure that faster devices are allowed for automatic partitioning, choose the Auto Device button in the Device dialog box to open the Automatic Device Selection dialog box. Make sure that faster devices are listed in the # / Selected Devices box. See Specifying Devices for Automatic Device Selection for more information. Go to Devices & Adapters and choose a device family selection guide for speed grade information.

Partitioned projects are more likely to experience pin-out and logic distribution changes than non-partitioned projects.

3.	If your MAX+PLUS II system includes timing-driven compilation support, specify default timing for the project as a whole with Global Project Timing Requirements (Assign menu). You can enter one or more of the available timing assignments, but you are not required to specify all of them. The fmax assignment is usually the most important factor in determining speed performance. Specify realistic, acceptable overall performance to obtain the best results: impossibly small delays and/or an impossibly high Clock frequency hinder the Compiler’s ability to meet your timing requirements.

Refer to Guidelines for Timing Assignments for information on which types of logic functions can use timing assignments, and how the Compiler interprets timing assignments.

4.	If feedback or Preset and Clear timing paths are not relevant to achieving the desired speed performance, turn on the Cut All Bidirectional Feedback Timing Paths and Cut All Preset & Clear Timing Paths options in the Global Project Timing Requirements dialog box.

5.	Enter individual timing assignments on input pins and the input function of bidirectional pins with Timing Requirements (Assign menu). You should assign timing for speed-critical paths (i.e., faster than the project default) as well as for slow paths (i.e., slower than the project default): both types of information will help the Compiler achieve your performance goals.

6.	Cut paths on non-critical nodes with the Timing Requirements command’s Cut Timing Path option.

7.	Enter individual timing assignments on output pins, TRI buffers (i.e., the output function of bidirectional pins), and registers.

8.	Select Fast as the Global Project Synthesis Style--i.e., the default logic synthesis style for the project--in the Global Project Logic Synthesis  dialog box  (Assign menu). The Altera-provided Fast style for each device family is tailored to provide speed optimization.

-	In FLEX 8000  and FLEX 10K projects, two of the logic options in this style, Carry Chain and Cascade Chain, are set to Auto. As an alternative to using the Fast logic synthesis style, you can set these logic options to Auto in the current default logic synthesis style for your project. You can change the style definition with the Define Synthesis Style dialog box (Assign menu), which is available through the Global Project Logic Synthesis dialog box.

-	In MAX 7000 and MAX 9000 projects, the Parallel Expanders logic option is turned on. As an alternative to using the Fast logic synthesis style, you can turn Parallel Expanders on in the current default logic synthesis style for your project. You can change the style definition with the Define Synthesis Style dialog box, which is available through the Global Project Logic Synthesis dialog box.

9.	(MAX 5000, MAX 7000, and MAX 9000 devices) Turn on the Multi-Level Synthesis option in the Global Project Logic Synthesis dialog box.

10.	Assign appropriate individual logic functions to cliques with Clique (Assign menu). To easily create a clique containing the logic cells on a critical path:

a.	Run the Timing Analyzer in the Registered Performance mode (Analysis menu).

b.	Choose List Paths.

c.	In the Message Processor window, select a message for a critical speed path, turn on the Locate in Floorplan Editor option, and choose the Locate All button.

The Floorplan Editor opens automatically and selects all logic cells that implement the critical path.

d.	Without deselecting any of the logic cells, choose Clique and assign all items to a single clique.

11.	(MAX 5000, MAX 7000, and MAX 9000 devices) Choose Fitter Settings (Processing menu) and choose the Customize button to open the expanded Fitter Settings dialog box and display all settings. Select Custom Fitting, then specify a larger number (i.e., greater than 100%) for the Expanders per Logic Cell option.

12.	If you require additional assistance, contact Altera Applications.

See also:

Adjusting the Fit During Compilation

Assigning a Clique

Assigning an Individual Logic Option or Synthesis Style

Assigning Individual Timing Requirements

Back-Annotating Assignments for a Project

Clearing Assignments for a Project

Specifying Fitter Settings

Specifying Global Project Logic Synthesis Settings

Specifying Global Project Timing Requirements


Specifying Fitter Settings (Compiler)
Specifying Fitter Settings

The Compiler always refits a project when you recompile after changing the project logic or its resource or device assignments in the design files.

You can control the refitting process with the Fitter Settings dialog box  (Processing menu). These options guide the Fitter in determining when to insert LCELL buffers (i.e., logic cells) automatically or to use other options to achieve a fit. However, inserting LCELL buffers in a project increases its logic cell usage and slows its performance. If you want the Fitter to perform minimal automatic LCELL insertion, you should select the Normal Fitting option, which is the default Fitter setting. If you want the Fitter to refrain from inserting LCELLs automatically, you must select the Custom Fitting option, choose the Customize button, and turn off all options listed under Auto Logic Cell Insertion Options.

Go to Fitting & Refitting a Project for suggestions on how to make your project fit successfully.

To specify Fitter settings, follow these guidelines:

1.	Choose Fitter Settings. The Fitter Settings dialog box is displayed.

2.	Select one of the following options:

Select Normal Fitting to direct the Compiler to insert LCELL buffers automatically into a project if user-defined resource and device assignments would otherwise prevent a project from fitting. This setting is the default for new projects.

Select Advanced Try Harder/Longer Compilation Fitting to direct the Compiler to cycle through a predefined suite of different Fitter settings to attempt to find a fit. This option directs the Compiler to insert LCELL buffers automatically if they are needed to achieve a fit, in a more aggressive fashion than the Normal Fitting option. You may wish to turn on this option if you want to allow the Compiler to run for a longer period of time (e.g., overnight) while attempting a fit. If you select this option and fitting is successful, you can manually specify the successful settings for Custom Fitting to accelerate future recompilations, as described later in this Help topic.

Select Custom Fitting to use previously defined custom settings or to define new settings.

3.	To display and/or customize previously-defined custom or default settings, choose the Customize button to open the expanded Fitter Settings dialog box and display all settings. Select Custom Fitting, then specify the appropriate options:

Under Auto Logic Cell Insertion Options, turn on one or more of the following options:

-	Turn on Normal to direct the Compiler to insert LCELL buffers automatically if user-defined resource and device assignments would otherwise prevent the project from fitting with the current pin assignments.

-	Turn on Row Pins with Fan-Out Greater than % of the Logic Cells per Row to direct the Compiler to direct the Compiler to insert LCELL buffers automatically if row pins that have a fan-out greater than the specified percentage of the logic cells per row would otherwise prevent the project from fitting with the current pin assignments.

-	Turn on Output Pins Fed by Carry Chains to direct the Compiler to insert LCELL buffers automatically if an output pin that is fed by a carry chain would otherwise prevent the project from fitting with the current pin assignments.

Under Other Options, specify one or more of the following options:

-	Specify the number of expander product terms allowed for logic cells, relative to the default percentage for the device family, for Expanders per Logic Cell. A higher percentage directs the Compiler to use additional expanders.

-	Specify the signal fan-in allowed per logic cell, relative to the default percentage for the device family, for Fan-In per Logic Cell. A higher percentage limits the maximum fan-in to a logic cell by inserting LCELL buffers.

-	Specify the number of the logic cells allowed per row, relative to the default percentage for the device family, for Logic Cells per Row.

4.	Choose OK.

5.	To begin compilation, choose the Start button in the Compiler window or the Project Save & Compile command (File menu) in any MAX+PLUS II application.

If fitting is successful with the Advanced Try Harder/Longer Compilation Fitting option, you can manually specify the successful settings from the compilation as Custom Fitting settings to accelerate future recompilations:

1.	Refer to the Error Summary Section of the of the <project name>.rpt file to determine the successful settings. The Error Summary Section of the Report File shows which Fitter settings were used during project compilation.

2.	Choose Fitter Settings. The Fitter Settings dialog box is displayed.

3.	Choose the Customize button to open the expanded Fitter Settings dialog box and display all settings. Select Custom Fitting.

4.	Enter the settings described in the <project name>.rpt file.

5.	Choose OK.

See also:

Adjusting the Fit During Compilation

Back-Annotating Assignments for a Project

Clearing Assignments for a Project

Fitting & Refitting a Project


Compiling EDIF Input Files (Compiler)
Compiling EDIF Input Files

EDIF Input Files in a project are automatically compiled by the Compiler. You can specify a specific CAE tool vendor to use the default EDIF Netlist Reader settings for that vendor, or you can specify custom settings.

You can also specify the global high and low signal names used in a project’s EDIF Input Files if they are not VCC and GND.

To compile EDIF Input Files:

1.	If necessary, change the project name with Project Name  (File menu).

2.	Choose EDIF Netlist Reader Settings (Interfaces menu). The EDIF Netlist Reader Settings dialog box is displayed.

3.	Select a vendor name from the Vendor drop-down list box to select the default EDIF Netlist Reader settings for that vendor.

or:

Select Custom from the Vendor drop-down list box to accept previously-defined custom settings or to define new settings.

4.	If you wish to use and/or customize previously-defined custom or default settings, choose the Customize button to expand the EDIF Netlist Reader Settings dialog box and display all settings. If Custom is selected in the Vendor drop-down list box, any previously-defined custom settings will be displayed. If a specific vendor name is selected in the Vendor drop-down list box, the default settings for that vendor appear under Signal Names and Library Mapping Files. If you then change these settings, the selection in the Vendor drop-down list box changes to Custom.

a.	Under Library Mapping Files, turn on the LMF #1 checkbox and type a filename in the text box following it, or select a name from the Files box. You can type a filename with up to 32 name characters in the LMF #1 box or select a filename in the Files box. If necessary, specify another LMF name in the LMF #2 box.

b.	Under Signal Names, type a name with up to 20 name characters in the VCC or GND text box if your EDIF Input File(s) use a name other than VCC or GND for the global high or low signal.

5.	Choose OK.

6.	To begin compilation, choose the Start button in the Compiler window or the Project Save & Compile command (File menu) in any MAX+PLUS II application.

The Compiler Netlist Extractor generates a CNF, HIF, and Symbol File for every cell in an EDIF Input File except for primitive cells (i.e., cells without contents constructs) or cells that are mapped to MAX+PLUS II primitives or macrofunctions in an LMF.

1.	If you transfer an EDIF Input File from a workstation to a PC running Windows 3.1 for compilation, the filename may be truncated to 8 characters. You must then either rename the file with its previous longer filename from within MAX+PLUS II, or edit the file to change any instances of the filename to the new, truncated name. To rename the file from within MAX+PLUS II, open the file with the truncated name in the Text Editor and save it to its previous longer filename. However, if your file transfer software inserts characters into the truncated name that are not legal MAX+PLUS II name characters, you may need to first rename the file from Windows 3.1 or DOS before you can open it in the Text Editor.

2	External libraries in EDIF Input Files are handled in the same way as regular EDIF libraries by the MAX+PLUS II Compiler. Because cells from external libraries have no contents, no CNFs are generated for them.

The following procedures describe steps you may need to take within your industry-standard CAE tool before importing an EDIF file into MAX+PLUS II:

Assigning Resources in a Third-Party Design Editor

Preserving Net & Instance Names in EDIF Input Files

Specifying Port Directions In EDIF Input Files

Using MAX+PLUS II Buffer & Expander Primitives in a Third-Party Design Editor

See also:

Changing the Project Name

EDIF 2 0 0 Constructs Interpreted by MAX+PLUS II

EDIF 3 0 0 Constructs Interpreted by MAX+PLUS II

Library of Parameterized Modules Support

Library Mapping File Format

Resource Assignments in EDIF Input Files

Recommended reading:

Cadence & MAX+PLUS II Software Interface Guide

Synopsys & MAX+PLUS II Software Interface Guide

Mentor Graphics & MAX+PLUS II Software Interface Guide

Viewlogic Powerview & MAX+PLUS II Software Interface Guide

AN30 (Viewlogic Workview PLUS & MAX+PLUS II Logic Design)

AB96 (Generating Library Mapping Files)

AB97 (Integrating EDIF with AHDL Files in Hierarchical Projects)

AB99 (Design Flow between Workstations & PCs)


Compiling OrCAD Schematic Files (Compiler)
Compiling OrCAD Schematic Files

The Compiler automatically compiles OrCAD Schematic Files in a project, provided that they adhere to the guidelines in Guidelines for Working with OrCAD Schematic Files. MAX+PLUS II uses the orcad.lmf file to map OrCAD symbols to MAX+PLUS II macrofunctions and primitives.

Altera strongly recommends saving a top-level OrCAD Schematic File in a project as a GDF with Save As (File menu) before compiling. Significant restrictions apply to using OrCAD Schematic Files in MAX+PLUS II. Refer to Restrictions on OrCAD Schematic Files in MAX+PLUS II for detailed information.

To compile OrCAD Schematic Files:

1.	When you are using OrCAD, create a single OrCAD Library File that contains the libraries of all symbols used in the project’s OrCAD Schematic Files.

2.	At the operating system prompt, create a new project directory and copy the OrCAD Schematic Files to this directory to avoid overwriting the original design files.

3.	At the operating system prompt, copy the OrCAD Library File to the project directory.

or:

In MAX+PLUS II, choose User Libraries (Options menu) and specify the directory that contains the OrCAD Library File as a user library.

4.	If necessary, change the project name in MAX+PLUS II with  Project Name (File menu).

5.	To begin compilation, choose the Start button in the Compiler window or the Project Save & Compile command (File menu) in any MAX+PLUS II application.

See also:

Changing the Project Name

Opening a File

Specifying a User Library


Compiling XNF Files (Compiler)
Compiling XNF Files

Xilinx Netlist Format Files in a project are automatically compiled by the Compiler, provided that they adhere to the guidelines in File Structure Requirements for XNF Files.

To compile XNF Files:

1.	If necessary, change the project name with Project Name (File menu).

2.	Choose XNF Netlist Reader Settings (Interfaces menu). The XNF Netlist Reader Settings dialog box is displayed.

3.	Under Tri-State Bus Emulation, select one of the following options:

Use Internal Logic specifies that tri-state buses should be emulated using internal multiplexer logic. This option helps conserve external pins.

Use Device Pins specifies that tri-state buses should be emulated using external pins (to simplify logic).

4.	If you wish to translate Xilinx internal node names to MAX+PLUS II-compatible names that consist of a four-digit number preceded by "N~," such as N~0001, N~0002, etc., turn on Translate Internal Node Names into N~<number> Format . If this option is turned off, MAX+PLUS II truncates the Xilinx internal node names to a maximum of 32 name characters and substitutes a tilde (~) for any character that is not a legal name character in MAX+PLUS II.

5.	If you wish to generate a Text Design Export File that is equivalent to the current XNF, turn on the Generate Text Design Export File (.tdx) option.

6.	Choose OK.

7.	To begin compilation, choose the Start button in the Compiler window or the Project Save & Compile command (File menu) in any MAX+PLUS II application.


Compiling VHDL Design Files (Compiler)
Compiling VHDL Design Files

The Compiler automatically compiles VHDL Design Files in a project. To determine which VHDL constructs are supported by MAX+PLUS II, refer to MAX+PLUS II VHDL Support. You should also follow the guidelines in VHDL Golden Rules before compiling a VHDL Design File with MAX+PLUS II.

To compile VHDL Design Files:

1.	If necessary, change the project name with Project Name or Project Set Project to Current File (File menu).

2.	If your project uses custom, user-defined design libraries, go through the following steps:

a.	Choose VHDL Netlist Reader Settings (Interfaces menu). The VHDL Netlist Reader Settings dialog box is displayed.

b.	Enter the logical name of your custom design library in the Library Name box.

c.	Choose the directory that contains your design library from the Directories box or type a directory name in the Directory Name box.

d.	Choose Add to add the design library to the Existing Libraries box.

e.	Repeat steps a through d as necessary for additional libraries .

f.	Choose OK to save all changes.

3.	To begin compilation, choose the Start button in the Compiler window or the Project Save & Compile command (File menu) in any MAX+PLUS II application.

When you compile (analyze) a VHDL Design File that does not contain an Architecture Body (e.g., a file that contains only packages), the compilation stops automatically because the file does not contain an Architecture Body. However, if the file contains only packages, the packages will be analyzed correctly and you can then successfully compile a different design that uses those packages.

See also:

Changing the Project Name

Opening a File


Creating AHDL Text Design Output Files (Compiler)
Creating AHDL Text Design Output Files

You can create one or more Text Design Output File(s) that contains that contains the AHDL equivalent of the fully optimized logic for a device in the project. When you create one or more TDO File(s), the Compiler also creates one or more Assignment & Configuration Output File(s).

A TDO File contains the fully optimized logic for a single device. You can save a TDO File as a Text Design File, edit it, specify as it as the project with Project Name (File menu), and recompile the project (You must also save the ACO File as an Assignment & Configuration File if you wish to preserve the assignments for the device). TDO Files facilitate back-annotation and preserve the existing logic synthesis in the project. In a multi-device project, TDO Files also allow you to "lock down" the design and pin-out of each device in the project.

To create one or more TDO File(s) for the project:

1.	Turn on Generate AHDL TDO File (Processing menu).

2.	To begin compilation, choose the Start button in the Compiler window or the Project Save & Compile command (File menu) in any MAX+PLUS II application.

The filenames of the TDO File(s) and ACO File(s) are the same as the user-defined chip name(s) for the project; if no chip names exist, the Compiler assigns filenames that are based on the project name. Example


Creating EDIF Output Files (Compiler)
Creating EDIF Output Files

You can create one or more EDIF Output Files for your project to use with simulators from other manufacturers. You can also use an EDIF Command File to customize EDIF Output Files for a particular third-party environment.

To create EDIF Output Files:

1.	Turn on the EDIF Netlist Writer command (Processing menu) to turn on the EDIF Netlist Writer module. The EDIF Netlist Writer module box appears in the Compiler window.

2.	Choose EDIF Netlist Writer Settings (Processing menu). The EDIF Netlist Writer Settings dialog box is displayed:

a.	Select EDIF 2 0 0 or EDIF 3 0 0 under EDIF Version.

b.	Select a vendor name from the Vendor drop-down list box to select the default EDIF Netlist Writer settings for that vendor.

or:

Select Custom from the Vendor drop-down list box to accept previously-defined custom settings or to define new settings.

c.	If you wish to display and/or customize previously-defined custom or default settings, choose the Customize button to expand the EDIF Netlist Writer Settings dialog box and display all settings. If Custom is selected in the Vendor drop-down list box, any previously-defined custom settings will be displayed. If a specific vendor name is selected in the Vendor drop-down list box, the default settings for that vendor appear in this dialog box. If you then change these settings, the selection in the Vendor drop-down list box changes to Custom.

i.	Under Signal Names, type a name with up to 20 name characters in the VCC or GND text box if your EDIF Input File(s) use a name other than VCC or GND for the global high or low signal.

ii.	Under Delay Constructs Written To, select EDIF Output File (.edo) to direct the Compiler to include delay information in the EDIF Output File, or select SDF Output File (.sdo) Ver 2.1 or SDF Output File (.sdo) Ver 1.0 to save the delay information to a separate SDF Output File.

iii.	If you wish to map the vertical bar (|), tilde (~), and colon (:) characters in MAX+PLUS II hierarchical node names to the legal EDIF characters z, x, and _ (underscore), respectively, in EDIF Output Files, turn on Map Illegal EDIF Characters.

iv.	Turn on Include Special Primitives to include the optional FILTER and RISEFALL primitives in the EDIF Output File.

v.	If you wish to set all propagation delays to 0 ns, turn on Force 0 ns Delays.

vi.	In the Time Scale box, specify time units to to be used when representing timing delays in each EDIF Output File.

vii.	If you wish to specify an EDIF Command File, turn on EDIF Command File and type the name of the file in the box or select a name from the Files box.

d.	Choose OK.

7.	To begin compilation, choose the Start button in the Compiler window or the Project Save & Compile command (File menu) in any MAX+PLUS II application.

If the project compiles successfully, the Compiler creates an EDIF Output File and an optional SDF Output File for each device in a project. The filenames of the EDIF Output File(s) are the same as the user-defined chip name(s) for the project; if you have not assigned chip names, the Compiler assigns names that are based on the project name. Example

See also:

EDIF Command File Format

Hierarchical Node & Symbol Names

Library Mapping File Format

Recommended reading:

Cadence & MAX+PLUS II Software Interface Guide

Mentor Graphics & MAX+PLUS II Software Interface Guide

Synopsys & MAX+PLUS II Software Interface Guide

Viewlogic Powerview & MAX+PLUS II Software Interface Guide

AN30 (Viewlogic Workview PLUS & MAX+PLUS II Logic Design)

AB96 (Generating Library Mapping Files)

AB99 (Design Flow between Workstations & PCs)


Creating Verilog Output Files (Compiler)
Creating Verilog Output Files

You can create a Verilog Output File in the Compiler to use as an input file for any simulator that can read Verilog netlist files.

To create a Verilog Output File:

1.	Turn on the Verilog Netlist Writer command (Interfaces menu). The Verilog Netlist Writer module box appears in the Compiler window.

2.	Choose Verilog Netlist Writer Settings (Interfaces menu). The Verilog Netlist Writer Settings dialog box is displayed:

a.	Under Write Delay Constructs To, select Verilog Output File (.vo) to direct the Compiler to include delay information in the Verilog Output File, or select SDF Output File (.sdo) Ver 2.1 or SDF Output File (.sdo) Ver 1.0 to save the delay information to a separate SDF Output File.

b.	If desired, specify a time scale in the Time Scale box.

c.	Choose OK to accept the changes and close the dialog box.

3.	To begin compilation, choose the Start button in the Compiler window or the Project Save & Compile command (File menu) in any MAX+PLUS II application.

If the project compiles successfully, the Compiler creates a Verilog Output File and an optional SDF Output File  for each device in a project. The filenames of the Verilog Output File(s) are the same as the user-defined chip name(s) for the project; if you have not assigned chip names, the Compiler assigns names that are based on the project name. Example

Recommended reading:

Cadence & MAX+PLUS II Software Interface Guide

Mentor Graphics & MAX+PLUS II Software Interface Guide

Synopsys & MAX+PLUS II Software Interface Guide

Viewlogic Powerview & MAX+PLUS II Software Interface Guide

AN30 (Viewlogic Workview PLUS & MAX+PLUS II Logic Design)


Creating VHDL Output Files (Compiler)
Creating VHDL Output Files

You can create a VHDL Output File in the Compiler to use as an input file for any simulator that can read VHDL netlist files.

To create a VHDL Output File:

1.	Turn on the VHDL Netlist Writer command  (Interfaces menu). The VHDL Netlist Writer module box appears in the Compiler window.

2.	Choose VHDL Netlist Writer Settings (Interfaces menu). The VHDL Netlist Writer Settings dialog box is displayed:

a.	Under Write Delay Constructs To, select VHDL Output File (.vho) to direct the Compiler to include delay information in the VHDL Output File(s), or select SDF Output File (.sdo) Ver 2.1 or SDF Output File (.sdo) Ver 1.0 to save the delay information to separate SDF Output File(s).

b.	If desired, turn on Generate Configuration Declaration to include a Configuration Declaration in each VHDL Output File that is generated.

c.	Choose OK to accept the changes and close the dialog box.

3.	To begin compilation, choose the Start button in the Compiler window or the Project Save & Compile command (File menu) in any MAX+PLUS II application.

If the project compiles successfully, the Compiler creates a VHDL Output File and an optional SDF Output File for each device in a project. The filenames of the VHDL Output File(s) are the same as the user-defined chip name(s) for the project; if you have not assigned chip names, the Compiler assigns names that are based on the project name. Example

Recommended reading:

Cadence & MAX+PLUS II Software Interface Guide

Mentor Graphics & MAX+PLUS II Software Interface Guide

Synopsys & MAX+PLUS II Software Interface Guide

Viewlogic Powerview & MAX+PLUS II Software Interface Guide

AN30 (Viewlogic Workview PLUS & MAX+PLUS II Logic Design)


Creating a Functional Simulator Netlist File (Compiler)
Creating a Functional Simulator Netlist File

You can create a functional SNF during compilation to use as an input file for the Simulator.

Since the functional SNF is created before logic synthesis, partitioning, and fitting are performed, it includes all nodes in the original design files for the project. (In a timing SNF, some nodes have been synthesized away.)

To create a functional SNF for the current project:

1.	Turn on Functional SNF Extractor (Processing menu). The Functional SNF Extractor module box appears in the Compiler window.

2.	To begin compilation, choose the Start button in the Compiler window or the Project Save & Compile command (File menu) in any MAX+PLUS II application.

The Compiler creates a functional SNF only if the project is processed successfully, i.e., without errors.

See also:

Creating a Timing Simulator Netlist File

Functional Simulation Mode (Simulator)


Creating a Timing Simulator Netlist File (Compiler)
Creating a Timing Simulator Netlist File

You can create a timing SNF during compilation to use as an input file for the Simulator and Timing Analyzer.

A timing SNF describes the fully optimized circuit after all logic synthesis and fitting have been completed. You can perform timing simulation and timing analysis (including delay prediction) with the timing SNF for a project. Functional testing is also available with the timing SNF for a single-device project.

If your project contains large sections of combinatorial logic, an optimized timing SNF can significantly reduce the time required for simulation. An optimized timing SNF contains dynamic models that replace sections of combinatorial logic during the simulation process. An optimized timing SNF provides the same functional and timing information as a non-optimized timing SNF. It also increases the speed of a timing analysis.

To create a timing SNF for the current project:

1.	Turn on Timing SNF Extractor (Processing menu). The Timing SNF Extractor module box appears in the Compiler window.

2.	If you wish to have the Compiler replace sections of combinatorial logic with dynamic models in the Timing SNF, turn on Optimize Timing SNF (Processing menu).

3.	To begin compilation, choose the Start button in the Compiler window or the Project Save & Compile command (File menu) in any MAX+PLUS II application.

The Compiler creates a timing SNF only if the project compiles successfully.

See also:

Creating a Functional Simulator Netlist File

Simulator Netlist File (.snf)

Timing Simulation Mode (Simulator)


Setting Report File Options (Compiler)
Setting Report File Options

You can specify whether or not to include optional sections of the Report File that is generated when a project is compiled. More detailed Report Files can help you to locate errors in a project that does not compile successfully.

To include optional sections:

1.	Choose Report File Settings (Processing menu). The Report File Settings dialog box is displayed.

2.	Turn on one or more of the following options:

Turn on User Assignments to include the Pin/LC/Chip Assignments, Probe Assignments, and Clique Assignments Sections.

Turn on File Hierarchy to include the File Hierarchy Section.

Turn on Logic Cell Interconnections to include the Logic Cell Interconnections Section.

Turn on Equations to include the Equations Section.

Turn on All to include all optional sections.

3.	Choose OK.

4.	To begin compilation, choose the Start button in the Compiler window or the Project Save & Compile command (File menu) in any MAX+PLUS II application.

See also:

Report File Format


Compiling a Project with Smart Recompile (Compiler)
Compiling a Project with Smart Recompile

You can direct the Compiler to save all database information to database files, which may allow the Compiler to recompile a project more quickly in subsequent compilations.

To generate expanded database files that support fast recompilations:

1.	Turn on Smart Recompile (Processing menu).

2.	To begin compilation, choose the Start button in the Compiler window or the Project Save & Compile command (File menu) in any MAX+PLUS II application.

The first compilation after you turn on Smart Recompile requires more time than a normal compilation, because the Compiler may take extra time to save all the database information. However, after the Compiler saves the database information, future compilations can be much faster. Depending on the changes you have made to your project, the Compiler can skip some of its modules during processing. During a "smart" recompilation, the Compiler always determines which modules are required to process the project based on the changes you have made to your project since the last compilation, then skips any modules that are not required.

1.	When the Compiler skips a module during a smart recompilation, the Message Processor does not redisplay any messages that the skipped module issued during the last compilation.

2.	Turning on Smart Recompile uses much more disk space than normal compilation, to store the database files.

3.	If you make any changes to the logic of your design, the Compiler must use all modules during processing.

See also:

Compiling a Project

Fitting & Refitting a Project

Starting & Stopping the Compiler


Starting & Stopping the Compiler (Compiler)
Starting & Stopping the Compiler

You can start the Compiler if it is not already running and stop it at any time. After you start the Compiler, you can watch a project compile or work in another application during compilation. If you stop the Compiler and start it again, the project is recompiled from the beginning.

To start the Compiler:

Choose the Start button in the Compiler window to compile the project currently saved to disk. If you have made changes to any design files or related ancillary files, you are asked if you wish to save the changes before beginning. (Unsaved edits are not lost, but are not used in the compilation.)

or:

Choose the Project Save & Compile command (File menu) in any MAX+PLUS II application to first save edits to currently open files, then compile the project.

To stop the Compiler:

Choose the Stop button in the Compiler window.

or:

Choose the Stop/Show Status button in the Compiler window. The Stop button changes into the Stop/Show Status button appears in place of when the Fitter and Partitioner modules of the Compiler are processing the project.

The Partitioner Fitter Status dialog box is displayed, listing all chips in the project and their fitting status.

If you stop and restart the Compiler, warning messages generated by the Compiler Netlist Extractor during the previous compilation are not redisplayed unless you turn on Total Recompile (Processing menu) before recompiling.

See also:

Checking the Partitioner & Fitter Status During Compilation

Compiling a Project

Compiling a Project with Smart Recompile

Totally Recompiling a Project


Totally Recompiling a Project (Compiler)
Totally Recompiling a Project

You can totally recompile a project to re-create all CNFs and HIFs and redisplay warning messages generated by the Compiler Netlist Extractor. You may also need to totally recompile a project if you have used Change File Type (File menu) in the Hierarchy Display.

To totally recompile a project:

1.	Turn on Total Recompile (Processing menu).

2.	To begin compilation, choose the Start button in the Compiler window or the Project Save & Compile command (File menu) in any MAX+PLUS II application.

Total Recompile is turned off automatically when you close the Compiler window or change the project name.

See also:

Compiling a Project

Fitting & Refitting a Project

Starting & Stopping the Compiler


Preserving All Node Name Synonymns (Compiler)
Preserving All Node Name Synonyms

You can preserve all node name synonyms in the Node Database File for the project.

To preserve node name synonymns:

Turn on Preserve All Node Name Synonyms (Processing menu).


-----BEGINNING OF NON-TRANSLATED TEXT-----

Messages in cmpmsgs.msg that are documented elsewhere (not in this file):

QCMP_OK_TO_CLOSE	simess.mac

SCMP_CORRUPT_PARTINFO 	glmess.mac

All syntax error messages have been moved to GLMESS.MAC

There is no list here of the messages from other .msg files that are documented in this file because most of the messages in this file are from other files!

from Tamlyn: I tried adding ENI_NODE_MISSING_SOURCE twice to the L footnote because it keeps coming up in the help comparison list.

The following SMPMSGS.MSG messages are not documented in this file:

MSMP_RESET_REQUIRED	COMESS.MAC

MSMP_RESET_STATE	not documented--is it used?

The following NE_MSGS.MSG messages are not documented in this file:

FNE_CANT_OPEN_FILE	GLMESS.MAC

FNE_DESIGN_TOO_COMPLEX	COMESS.MAC

FNE_GED_ERROR	GLMESS.MAC

need to edit ne_msgs.msg to have same wording as next msg:

-----END OF NON-TRANSLATED TEXT-----


Can’t make equation

CAUSE:	An attempt to synthesize a state machine has failed. The project's logic is too complex, so the Compiler could not perform logic synthesis.

ACTION:	Simplify your logic.

See also:

MAX+PLUS II Messages

Message Format


Can’t save & check <filename>  -- its extension conflicts with the top-level design file of the current project. etc.
 Can’t save & check <filename>  -- its extension conflicts with the top-level design file of the current project. Use the Hierarchy Display’s Change File Type command to change the extension of the top-level design file

CAUSE:	You chose the Save & Check command (File menu) to save and check the specified file. However, the filename extension conflicts with the currect project’s top-level file extension.

ACTION:	Choose the Change File Type command (File menu) and change the top-level filename and extension to the desired name.

See also:

Changing the File Type

MAX+PLUS II Messages

Message Format

Selecting a File Icon or Name


Clock pin cannot be used as an I/O pin
Clock pin cannot be used as an I/O pin [<text>]

CAUSE:	In your EP610 or EP910 project, you have used the device Clock pin as a general input signal. However, in these devices, the Clock pin on the device is dedicated for synchronous clock input and cannot be used for logic input signals.

ACTION:	If you wish to use a Classic device, place everything driven by the signal into an EP1810 device, split the signal into two--one global and one for logic. Otherwise, change to a different device family, use different pin assignments, or allow the Fitter to make pin assignments.

See also:

Assigning a Pin, Location, or Chip

MAX+PLUS II Messages

Message Format


Compiling project with user-specified timing assignments

CAUSE:	Your project contains timing assignments entered with the Timing Requirements and/or Global Project Timing Requirements (Assign menu).

ACTION:	No action is required.

See also:

Assigning Individual Timing Requirements

MAX+PLUS II Messages

Message Format

Specifying Global Project Timing Requirements


Compiler auto device family was changed from <name> to <name> to agree with Device command setting
Device family was changed from <name> to <name> to agree with Device command setting

CAUSE:	The device family specified with the DEVICE_FAMILY variable in the Other Configuration Section of the ACF differs from the family specified in the Physical Chip Assignments Section of the ACF or with the Device command (Assign menu). MAX+PLUS II has changed the device family to agree with the family specified in the Physical Chip Assignments Section of the ACF or with the Device command.

ACTION:	No action is required. If you wish to use a different device family, use the Device command to change the device family.

See also:

Assigning a Device

MAX+PLUS II Messages

Message Format

Specifying Devices for Automatic Device Selection


Duplicate node [or pin] name: <pin/node name> [(ID <net ID number> and <net ID number>)]
Duplicate node [or pin] name: <node/pin name> [(ID <net ID number> and <net ID number>)]

CAUSE:	Two or more nodes, input pins, output pins, or bidirectional pins have the same name in a design file,.

ACTION:	Ensure that all node and pin names within a single design file have unique name characters.

See also:

Locating the Source of a Message

MAX+PLUS II Messages

Message Format


Duplicate state name: <name>

CAUSE:	The same state name is used in two or more state machines within a single design file.

ACTION:	Ensure that all state names are unique within a single design file.

See also:

MAX+PLUS II Messages

Message Format


 File is read-only but <text>

CAUSE:	The specified CNF is read-only, but is either from an earlier version of MAX+PLUS II or is older than the source design file. The file must be re-created to be up-to-date.

ACTION:	Remove the write protection from the file, and recompile the project. If you are using MAX+PLUS II on a network, you may need to ask the network administrator to change the write permission on the file.

See also:

MAX+PLUS II Messages

Message Format


Ignored timing assignments -- these assignments are available only for the FLEX 8000 or FLEX 10K device family
Ignored timing assignments -- these assignments are available only for the FLEX 8000 and FLEX 10K device families

CAUSE:	Your project contains timing assignments entered with the Timing command (Assign menu) in the Graphic, Text, or Waveform Editor and/or the Default Timing command (Assign menu) in the Compiler, but the project is assigned to a device family other than the FLEX 8000 or FLEX 10K device family. You can only enter timing assignments for FLEX 8000 projects.

ACTION:	No action is required. To avoid this message, either delete the timing assignments or assign the project the FLEX 8000 or FLEX 10K device family. Refer to Guidelines for Timing Assignments for information on how to use timing assignments effectively.

See also:

Assigning Individual Timing Requirements

MAX+PLUS II Messages

Message Format

Specifying Global Timing Requirements


Illegal combinatorial feedback for <node name>

CAUSE:	While expanding an equation for the specified node name, the Compiler detected combinatorial feedback that was not fed through an LCELL, SOFT, or EXP primitive.

ACTION:	Insert an LCELL, SOFT, or EXP primitive.

See also:

MAX+PLUS II Messages

Message Format


Include File generation canceled: <number> errors; <number> warnings
Include File generation canceled

<number> errors

<number> warnings

CAUSE:	You chose Stop in the Compiler, which canceled the Create Default Include File command (File menu) before the Compiler had finished creating an Include File.

ACTION:	No action is required. Use the Message Processor to locate the source(s) of any error or warning messages.

See also:

Creating a Default Include File

Locating the Source of a Message

MAX+PLUS II Messages

Message Format


Include File generation was successful: <number> errors; <number> warnings
Include File generation was successful

<number> errors

<number> warnings

CAUSE:	Create Default Include File (File menu) was successful, and has generated an Include File that represents the design file.

ACTION:	No action is required. Use the Message Processor to locate the source(s) of any warning messages.

See also:

Creating a Default Include File

Locating the Source of a Message

MAX+PLUS II Messages

Message Format


Include File generation was unsuccessful: <number> errors; <number> warnings
Include File generation was unsuccessful

<number> errors

<number> warnings

CAUSE:	Create Default Include File (File menu) was unsuccessful because the design file had errors.

ACTION:	Use the Message Processor to locate the source(s) of error and warning messages.

See also:

Creating a Default Include File

Locating the Source of a Message

MAX+PLUS II Messages

Message Format


JEDEC Files cannot be created for <device name> devices

CAUSE:	A JEDEC File cannot be used to program one of the devices used in your project. Therefore, the Compiler created only a POF or SOF for your project.

ACTION:	Specify a JEDEC File to program only the EPM5016, EPM5032, and Classic devices (EP330, EP610, EP910, and EP1810). For all other devices, a POF or SOF is required for programming with the MAX+PLUS II Programmer.

See also:

MAX+PLUS II Messages

Message Format


MAX+PLUS II is currently <text>. OK to stop the <application name>?

CAUSE:	While a MAX+PLUS II background process was running, you tried to close the specified MAX+PLUS II application, exit from MAX+PLUS II entirely, or change the project name.

ACTION:	Choose OK if you wish to stop the current task and close the specified application, exit from MAX+PLUS II, or change the project name. Choose Cancel if you wish MAX+PLUS II to continue the current task and cancel the command.

See also:

Changing the Project Name

Closing a MAX+PLUS II Application

Exiting from MAX+PLUS II

MAX+PLUS II Messages

Message Format


Node <name> (ID <net ID number>) missing source
Node <name> [(ID <net ID number>)] missing source

CAUSE:	A node is connected to one or more destinations but does not have a source. This error can also occur if you have not correctly named a node that is connected to a bus in a Graphic Editor file.

ACTION:	Connect the node to the output of a logic function. If you wish to use the default unconnected input to a macrofunction, make sure that nothing is connected to the input of the macrofunction. Refer to Pin & Node Names and Bus Names for information on naming nodes and buses in Graphic Editor files.

See also:

MAX+PLUS II Messages

Message Format


Primitive <node name> is stuck at GND

CAUSE:	The primitive’sprimary (data) or secondary inputs have caused its output to always be GND, or the output of the EXP or SOFT primitive associated with the specified node name feeds back to itself positively. Therefore, the node will always be stuck at GND. This condition may be the result of logic synthesis having optimized the project.

ACTION:	Check the design files for errors.

See also:

MAX+PLUS II Messages

Message Format


Project compilation canceled: <number> errors; <number> warnings
Project compilation canceled

<number> errors

<number> warnings

CAUSE:	You chose Stop in the Compiler or an ancillary file that was required to complete the compilation is missing, so compilation stopped before it was completed. This message can also occur when you compile (analyze) a VHDL Design File that does not contain an Architecture Body (e.g., a file that contains only packages).

ACTION:	No action is required. You can restart compilation from the beginning with Project Save & Compile (File menu) or with the Compiler’s Start button. If you get this message when compiling a VHDL Design File and the file contains only packages, the packages will be analyzed correctly and you can then successfully compile a different design that uses those packages.

See also:

MAX+PLUS II Messages

Message Format


Project compilation was successful: <number> errors; <number> warnings
Project compilation was successful

[<number> errors]

[<number> warnings]

CAUSE:	Your project compiled successfully. If you compiled with Functional SNF Extractor (Processing menu) turned on, the Compiler has created a functional SNF otherwise, the Compiler has generated a POF or SOF for device programming. The Compiler may also have generated other output files based on whether Timing SNF Extractor (Processing menu), EDIF Netlist Writer (Interfaces menu), VHDL Netlist Writer (Interfaces menu), and Verilog Netlist Writer (Interfaces menu) are turned on.

ACTION:	No action is required. You can functionally simulate the project if the Compiler created a functional SNF. You can program a device if the Compiler created a POF or SOF. Other post-compilation activities depend on the types of output files generated during compilation. Use the Message Processor to locate the source(s) of any warning messages.

See also:

Creating a Functional Simulator Netlist File

Creating a Timing Simulator Netlist File

Creating a Verilog Output File

Creating a VHDL Output File

Creating EDIF Output Files

Creating JEDEC Files

MAX+PLUS II Messages

Message Format

Programming a Device


Project compilation was unsuccessful: <number> errors; <number> warnings
Project compilation was unsuccessful

<number> errors

<number> warnings

CAUSE:	Compilation was completed as far as possible, but the project had one or more errors.

ACTION:	Use the Message Processor to locate the source(s) of error and warning messages.

See also:

Locating the Source of a Message

MAX+PLUS II Messages

Message Format


Project has not changed since last compilation

CAUSE:	You attempted to recompile a project with Smart Recompile (Processing menu) turned on. During a "smart" recompilation, the Compiler always determines which modules are required to process the changes made to the project since the last compilation, then skips any modules that are not required. You have not made any significant changes to design files or the ACF since the last compilation (e.g., Simulator settings are ignored), so the Compiler determined that recompilation was not necessary.

ACTION:	No action is required. If you wish to recompile the project--even though no compilation is necessary--turn off Smart Recompile, then choose the Start button again.

See also:

Compiling a Project

MAX+PLUS II Messages

Message Format

Recompiling a Project with Smart Recompile

Starting & Stopping the Compiler

Totally Recompiling a Project


Smart recompilation skipped the <module name> because it is not required

CAUSE:	You compiled a project with Smart Recompile (Processing menu) turned on. During a "smart" recompilation, the Compiler always determines which modules are required to process the changes made to the project since the last compilation, then skips any modules that are not required. Since you have not made any changes to design files or the ACF that affect the specified module, the Compiler has skipped this module during processing, thereby reducing compilation time.

ACTION:	No action is required. If you wish to recompile the project with all modules--even though it is not necessary--turn off Smart Recompile, then choose the Start button again.

See also:

Compiling a Project

MAX+PLUS II Messages

Message Format

Recompiling a Project with Smart Recompile

Starting & Stopping the Compiler


Switching from "smart" recompile to normal compile -- can’t <text> file <filename>

CAUSE:	You attempted to compile a project with Smart Recompile (Processing menu) turned on. However, the Compiler could not read or write the specified file, so it has reverted back to normal compilation. The file may be write-protected or the disk may be full. Or, you may have tried to save to a filename of an existing file that is open and/or part of the current hierarchy tree.

ACTION:	No action is required. If you wish to attempt a smart recompilation again, first ensure that the file or disk is not write-protected and that the file or disk is not corrupted. In DOS, you can try using the chkdsk /f command to check your disk for errors. If the disk is full, delete some of the files to create disk space or save the file to a different disk. Save files only to filenames that are not part of the current hierarchy tree or that are not already open.

See also:

Compiling a Project

MAX+PLUS II Messages

Message Format

Recompiling a Project with Smart Recompile

Starting & Stopping the Compiler


Can’t update Report File <filename> with information from "smart" recompile -- etc.
Can’t update Report File <filename> with information from "smart" recompile -- restart the compilation to re-create the Report File

CAUSE:	You attempted to compile a project with Smart Recompile (Processing menu) turned on. However, the Compiler was not able to update the Report File, either because you edited the Report File, or because an I/O error occurred.

ACTION:	Choose the Start button again to recompile the project and re-generate a Report File.

See also:

Compiling a Project

MAX+PLUS II Messages

Message Format

Recompiling a Project with Smart Recompile

Starting & Stopping the Compiler


Project too complex [<text>]

CAUSE:	The project contains too many hierarchy levels and/or too many primitives and/or macrofunctions, the logic is too complex, or MAX+PLUS II is out of memory or stack space. The <text> of the message often indicates the exact source of the problem.

ACTION:	To simplify logic, add or remove LCELL and SOFT buffers, implement registers and latches with register and latch primitives instead of shareable expanders, or partition the project into multiple devices.

If a hierarchy problem exists, flatten the subdesigns to reduce the number of hierarchical interconnections, or check for infinite recursions (i.e., a macrofunction that is "calling itself" as a result of incorrect parameters).

If there are too many symbols or instances, create more levels of hierarchy so that no one file has too many primitives or macrofunctions.

To free up more system memory, close other programs running in the background, or try restarting Windows and MAX+PLUS II.

If a project is too complex to be linked, create more levels of hierarchy in the specified design file and then link the individual files.

See also:

MAX+PLUS II Messages

Message Format

Partitioning a Project

Primitives

Recommended reading:

AB93 (Partitioning a Project with MAX+PLUS II Software)


Reset state is <state name> in machine <name>

CAUSE:	You supplied a Reset signal a state machine so the machine begins at the specified reset state after a reset.

ACTION:	No action is required.

See also:

MAX+PLUS II Messages

Message Format


Save & Check canceled: <number> errors; <number> warnings
Save & Check canceled

<number> errors

<number> warnings

CAUSE:	You chose Stop in the Compiler, which canceled the Save & Check command (File menu) before the Compiler had finished checking the design file.

ACTION:	No action is required. Use the Message Processor to locate the source(s) of any error or warning messages.

See also:

Locating the Source of a Message

MAX+PLUS II Messages

Message Format


Save & Check was successful: <number> errors; <number> warnings
Save & Check was successful

<number> errors

<number> warnings

CAUSE:	Save & Check (File menu) was successful, finding no errors in the current design file.

ACTION:	No action is required. Use the Message Processor to locate any warning messages.

See also:

Locating the Source of a Message

MAX+PLUS II Messages

Message Format


Save & Check was unsuccessful: <number> errors; <number> warnings
Save & Check was unsuccessful

<number> errors

<number> warnings

CAUSE:	Save & Check (File menu) was completed as far as possible, but the design file had one or more errors.

ACTION:	Use the Message Processor to locate the source(s) of error and warning messages in the file.

See also:

Locating the Source of a Message

MAX+PLUS II Messages

Message Format


User state bit assignments are not unique for state machine <name>
State bit assignments are not unique for state machine <name>

CAUSE:	You have manually assigned the same state bit pattern to two or more states or assigned some but not all state bits for the states in the machine. To make each assignment unique, the Compiler automatically appends bits.

ACTION: 	No action is required.

See also:

Assigning State Machine Bits & Values (AHDL)

MAX+PLUS II Messages

Message Format


State <name> in state machine <name> is never exited

CAUSE:	You have entered a state in a state machine that can never be left once it is reached.

ACTION:	If you intended for the state machine to be able to exit from the state, modify the design file.

See also:

Implementing a State Machine (AHDL)

MAX+PLUS II Messages

Message Format

Recovering from Illegal States (AHDL)

Specifying State Transitions (AHDL)


State machine <name> must be reset to guarantee proper operation

CAUSE:	The initial state in your project contains non-zero state bits. It must be explicitly reset so that the logic commences at the Reset state. This condition may occur as a result of logic synthesis if NOT Gate Push-Back has inverted a state bit that feeds an output pin.

ACTION:	Reset the state bits to an initial condition. In a TDF, use the Reset port (i.e., .reset) of the state machine; in a WDF, specify the name of the Reset input to the state machine node with Enter Node (Node menu).

See also:

Changing the Node Type, I/O Type, Secondary Inputs, or Default Value (Waveform Editor)

MAX+PLUS II Messages

Message Format

Setting Clock, Reset, & Enable Signals

State Machines (AHDL)


Symbol generation canceled: <number> errors; <number> warnings
Symbol generation canceled

<number> errors

<number> warnings

CAUSE:	You chose Stop in the Compiler, which canceled the Create Default Symbol command (File menu) before the Compiler had finished processing the current design file to create a corresponding Symbol File.

ACTION:	No action is required. Use the Message Processor to locate the source(s) of any error or warning messages.

See also:

Creating the Default Symbol for a File

Locating the Source of a Message

MAX+PLUS II Messages

Message Format


Symbol generation was successful: <number> errors; <number> warnings
Symbol generation was successful

<number> errors

<number> warnings

CAUSE:	Create Default Symbol (File menu) was successful, and has generated a Symbol File that represents the design file.

ACTION:	No action is required. You may use the symbol in a GDF.. Use the Message Processor to locate the source(s) of any warning messages.

See also:

MAX+PLUS II Messages

Message Format


Symbol generation was unsuccessful: <number> errors; <number> warnings
Symbol generation was unsuccessful

<number> errors

<number> warnings

CAUSE:	Create Default Symbol (File menu) was unsuccessful because the design file had errors.

ACTION:	Use the Message Processor to locate the source(s) of error and warning messages.

See also:

Creating the Default Symbol for a File

Locating the Source of a Message

MAX+PLUS II Messages

Message Format


Unreachable state <name> in state machine <name>

CAUSE:	The specified state cannot be reached through any state transition, i.e., it can’t be entered at all except with a hardware system error.

ACTION:	Remove the offending state from the state machine, or rewrite the state machine. You may wish to use the WHEN OTHERS clause in an AHDL Case Statement to capture all illegal state transitions in a state machine.

See also:

Creating a Waveform Design File (Waveform Editor)

State Machines

MAX+PLUS II Messages

Message Format


-----BEGINNING OF NON-TRANSLATED TEXT-----

11/30/93: The following annotated file popups do not appear to be used (i.e., searching for them in the file yielded no result):

co_files_rpt_respinreq

co_files_rpt_lcnumber

co_files_rpt_labname

co_files_rpt_interconlc

co_files_rpt_interconpin

co_files_rpt_interconsym

co_files_rpt_intername

co_files_rpt_pininput

co_files_rpt_115

co_files_rpt_116

co_files_rpt_117

co_files_rpt_118

co_files_rpt_119

co_files_rpt_120

11/30/93: Annotated file popups need to be checked against panels to be sure that they are up to date. A panel may have been edited but the corresponding popup may not have gotten edited:

----END OF NON-TRANSLATED TEXT-----


Report File--Context-Sensitive Help
Report File Context-Sensitive Help

Context-sensitive help is available for the following Report File sections. When a Report File is open, you can choose a section title with the Help pointer to get help on that section.

Auto Global Signals

Buried Logic

Clique Assignments

Compilation Settings & Times

Device Summary

Equations

Error Summary

FastTrack Interconnect Utilization

File Hierarchy

Inputs

Logic Cell Interconnections

Multiple Pin Connections

Outputs

Pin/Location/Chip Assignments

Probe Assignments

Project Compilation Messages

Project Timing-Driven Compilation Messages

Resource Usage

State Machine Assignments

See also:

Getting Context-Sensitive Help

Report File (.rpt) Description

Report File Format


Report File Format

The Report File (with the extension .rpt) is an ASCII text file that shows how a project is implemented in one or more devices, including information on project partitioning, resource usage, and inputs, outputs, and buried logic. The Report File is generated by the Fitter.

The Report File is divided into two types of information. Most project information, i.e., information on the project as a whole, is listed first. Device-specific information follows the project information, and is repeated for each device used in the project. At the end of the Report File is a list of project compilation times for all Compiler modules and utilities.

Project Information

-	Device Summary Section

-	Project Compilation Messages Section

-	Project Timing-Driven Compilation Messages Section

-	Auto Global Signals Section

-	Multiple Pin Connections Section

-	Pin/Location/Chip Assignments Section

-	Clique Assignments Section

-	Probe Assignments Section

-	State Machine Assignments Section

-	File Hierarchy Section

-	Timing Assignments Section

-	Compilation Settings & Times Section

Device-Specific Information (including pin-outs)

-	Error Summary Section

-	Resource Usage Section

-	Inputs Section

-	Outputs Section

-	Buried Logic Section

-	Logic Cell Interconnections Section

-	FastTrack Interconnect Utilization Section (FLEX 8000 devices only)

-	Clock Signals Section

-	Clear Signals Section

-	Carry Chains Section

-	Equations Section

See also:

Assigning a Device

Back-Annotating Assignments for a ProjectSetting Report File Options


Project Information (Report File)

The first line of a Report File, following the copyright notice, contains one of the following summary statements:

Project compilation was successful

or:

Project compiled with errors

The first statement indicates that the project contains no errors and that you can program the target device(s). The second statement indicates that the project’s design files must be corrected and recompiled before you can program a device.

This statement is followed by the information that is included in a GDF Title Block or TDF Title Statement.

The following sections appear after the summary statement and title information:

Device Summary Section

Project Compilation Messages Section

Project Timing-Driven Compilation Messages Section

Auto Global Signals Section

Multiple Pin Connections Section

Pin/Location/Chip Assignments Section

Clique Assignments Section

Probe Assignments Section

Timing Assignments Section

State Machine Assignments Section

File Hierarchy Section

Compilation Settings & Times Section

See also:

Back-Annotating Assignments for a Project

Assigning Connected Pins

Device-Specific Information (Report File)

Report File Format


Device-Specific Information (Report File)

The first line of each group of device-specific information contains one of the following statements:

Logic for device <chip name> compiled without errors

or:

Logic for device <chip name> contains errors--see ERROR SUMMARY

This statement is followed by device assignment and device option information for the device.

Next, a pin-out diagram of the target device shows both used and unused pins. For example:

                                          R  R

                                          E  E

                                          S  S

                     a              c     E  E

               d  d  c              l     R  R

               i  i  c  V  G  G  G  o  G  V  V

               r  r  e  C  N  N  N  c  N  E  E

               0  1  l  C  D  D  D  k  D  D  D

             -----------------------------------_

           /   6  5  4  3  2  1 44 43 42 41 40   |

    reset |  7                                39 | RESERVED

   enable |  8                                38 | RESERVED

at_altera |  9                                37 | RESERVED

      GND | 10                                36 | time5

  ticket2 | 11                                35 | VCC

  ticket1 | 12          EPM7032LC44           34 | time6

  ticket3 | 13                                33 | time0

 RESERVED | 14                                32 | time4

      VCC | 15                                31 | RESERVED

 RESERVED | 16                                30 | GND

  ticket0 | 17                                29 | time7

          |_  18 19 20 21 22 23 24 25 26 27 28  _|

            ------------------------------------

               R  R  R  R  G  V  R  t  t  t  R

               E  E  E  E  N  C  E  i  i  i  E

               S  S  S  S  D  C  S  m  m  m  S

               E  E  E  E        E  e  e  e  E

               R  R  R  R        R  3  2  1  R

               V  V  V  V        V           V

               E  E  E  E        E           E

               D  D  D  D        D           D

N.C. = Not Connected.

VCC = Dedicated power pin, which MUST be connected to VCC.

GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.

RESERVED = Unused I/O pin, which MUST be left unconnected.

GND and VCC represent dedicated ground and power pins and unused input pins. These pins must be connected to GND or VCC; they should never be left floating.

RESERVED represents unused I/O pins. These pins must be left unconnected. They are available for future use and may be reprogrammed if the project changes.

All named pins must be wired as shown in the pin-out diagram to implement the logic correctly on the programmed device.

Pin names preceded by an asterisk (*) represent reserved dual-purpose pins that drive out in user mode. (FLEX 8000 and FLEX 10K devices only)

Pin names preceded by a plus (+) represent reserved dual-purpose pins that are tri-stated during user mode. (FLEX 8000 and FLEX 10K devices only)

Pin names preceded by a caret (^) represent dedicated configuration pins. (FLEX 8000 and FLEX 10K devices only)

Pins labeled with an at symbol (@) are assigned for JTAG boundary-scan testing.

Pins labeled with a # symbol are dual-purpose pins used for device configuration and I/O.

Pins labeled PDn appear only on EPM7032V devices, and are used to control power-saving mode.

Pin and other resource assignments made by the Fitter may change if you change the design file(s). To retain the current assignments for future use, you must back-annotate them to the original design files for the project.

For information on the resources available in a particular device, refer to the individual device data sheets or to Devices & Adapters. Data sheet information will help you choose resource assignments that will enable the Fitter to find a satisfactory fit for your project.

The following sections appear after the summary statement, device information, and pin-out diagram:

Error Summary Section

Resource Usage Section

Inputs Section

Outputs Section

Buried Logic Section

Logic Cell Interconnections Section

FastTrack Interconnect Utilization Section (FLEX 8000, MAX 9000, and FLEX 10K devices only)

Equations Section

See also:

Assigning Connected Pins

Back-Annotating Assignments for a Project

Project Information (Report File)

Report File Format


Select the Appropriate Summary Section (Report File)

For help, choose a section:

Device Summary

Error Summary


Select the Appropriate Assignments Section (Report File)

For help, choose a section:

Clique Assignments

Pin/Location/Chip Assignments

Probe Assignments Section

State Machine Assignments


Device Summary Section (Report File)

Summarizes information about devices used in a project under the following column headings:

Heading:	Description:

Chip/POF	Lists the names of all chip assignments used in the project.

Device	Lists the names of the devices to which chips are assigned.

Input Pins	Shows how many input pins in each device are used by the project.

Output Pins	Shows how many output pins in each device are used by the project.

Bidir Pins	Shows how many bidirectional pins in each device are used by the project.

LCs	Shows how many logic cells in each device are used by the project.

Shareable Expanders	Shows how many shareable expanders are in the device. This number is based on the number of shareable expanders used in a device.

% Utilized	Shows the percentage of resources that are used in each device. This number is based on the logic cell count.

The following example shows the Device Summary for MAX 7000 and MAX 9000 devices:

** DEVICE SUMMARY **

Chip/              Input   Output   Bidir         Shareable

POF       Device   Pins    Pins     Pins     LCs  Expanders  % Utilized

MAXPROJ   EPM7096   6        13       0      35      26          36 %

User Pins:          6        13       0

The following example shows the Device Summary for FLEX 8000 and FLEX 10K devices:

** DEVICE SUMMARY **

Chip/                     Input Output Bidir  Memory  Memory  	 LCs

POF       Device          Pins  Pins   Pins   Bits % Utilized  LCs  % Utilized

chiptrip  EPF10K50GC403    6      13     0    0         0  %    79       2  %

User Pins:                 6      13     0

If the project is partitioned among multiple devices, the following lines are added:

Total	Lists the totals for Input Pins, Output Pins, Bidir Pins, LCs (logic cells), and Shareable Expanders (expander product terms).

User Pins	Shows the total number of user-created pins for Input Pins, Output Pins, and Bidir Pins, i.e., the total pins minus the pins created for inter-device connections.

If you have reserved resources with the Global Project Device Options command (Assign menu), the following lines appear last in this section:

User-reserved pins: <number>

User-reserved logic cells: <number>

See also:

Hierarchical Node & Symbol Names


Project Compilation Messages Section (Report File)

Lists all warning and error messages (except device-specific messages) generated during compilation. Device-specific warning and error messages appear in the Error Summary Section for each device in the project. For example:

** PROJECT COMPILATION MESSAGES **

Warning: Ignored unnecessary INPUT pin 'unused2'

Warning: Ignored unnecessary INPUT pin 'unused1'

If Total Recompile (Processing menu) was not turned on when the project was compiled, Compiler Netlist Extractor warnings from previous compilations are not included in the Project Compilation Messages Section.

See also:

Getting Help on a Message

Locating the Source of a Message

MAX+PLUS II Messages

Totally Recompiling a Project


Project Timing-Driven Compilation Messages Section (Report File)

Lists all timing assignment warning and error messages (except device-specific messages) generated during compilation. Device-specific warning and error messages appear in the Error Summary Section for each device in the project. For example:

** PROJECT TIMING-DRIVEN COMPILATION MESSAGES **

Warning: Can't provide tco of 10.0 ns from "CLOCK" to "cmpen". Current tco is 20.9 ns.

Warning: Found ripple clock -- warning messages and Report File information on tco, tsu, and fmax may be inaccurate

See also:

Getting Help on a Message

Locating the Source of a Message

MAX+PLUS II Messages


Select the Appropriate Compilation Section (Report File)

For help, choose a section:

Project Compilation Messages Section

Project Timing-Driven Compilation Messages Section

Compilation Settings & Times Section


Auto Global Signals Section (Report File)

Lists the node names chosen for any global Clock, Clear, Preset, and Output Enable signals specified with the Global Project Logic Synthesis command (Assign menu). For example:

** AUTO GLOBAL SIGNALS **

INFO: Signal 'CLOCK' chosen for auto global Clock

This section is omitted if the Compiler has not automatically assigned any global signals.

See also:

GLOBAL Primitive

Hierarchical Node & Symbol Names

Specifying Global Project Logic Synthesis Settings


Multiple Pin Connections Section (Report File)

Shows which pins must be connected if the project is partitioned or, in certain cases, where global signals are used. This section also lists inter-device connections requested with the Connected Pins command (Assign menu) or with INPUTC, OUTPUTC, and BIDIRC primitives in a GDF. For example:

** MULTIPLE PIN CONNECTIONS **

For node name 'out1'

For node name 'in1'

Connect: {MAXPROJ@48,   MAXPROJ@15}

This section has the following BNF format:

For Node Name "<node name>"

Connect:	{<chip name1> @ <pin number>,

<chip name2> @ <pin number>,...}

The Multiple Pin Connections Section is omitted if no pins must be connected.

See also:

Assigning Connected Pins

Hierarchical Node & Symbol Names


Pin/Location/Chip Assignments Section (Report File)

Lists the user-defined pin, logic cell, and chip assignments in the project’s design files. For example:

** PIN/LC/CHIP ASSIGNMENTS **

                  Actual

    User       Assignments

Assignments   (if different)     Node Name

chiptrip@9       chiptrip@4       accel

chiptrip@9                        at_altera

chiptrip@LC3                      |auto_max:1|q1

chiptrip@LC17                     |auto_max:1|q2

chiptrip@LC4                      |auto_max:1.speed_too_fast

chiptrip@LC16                     |auto_max:1|street_map~1

chiptrip@LC1                      |auto_max:1|street_map~2

chiptrip@LC21                     |auto_max:1|street_map~3

chiptrip@LC18                     |auto_max:1|street_map~4

chiptrip@LC2                      |auto_max:1|street_map~5

chiptrip@43                       clock

chiptrip@6                        dir0

Information is provided under the following headings:

Heading:	Description:

User Assignments	Shows the chips, pins, and logic cells to which you have assigned nodes.

Actual Assignments	Shows the chips, pins, and logic cells to which the Compiler has assigned nodes (if different from your assignments).

Node Name	Lists the nodes that are assigned to chips, pins, or logic cells.

Assignments are listed in the following BNF format:

<chip name> @ <pin number>

| <chip name> @ LC<logic cell number>

This section is omitted when the project contains no user-assigned chips, pins, or logic cells. You can specify whether or not to include this Report File section with the User Assignments option in the Report File dialog box (Processing menu).

See also:

Hierarchical Node & Symbol Names

Pin, Location & Chip Assignments

Setting Report File Options


-----BEGINNING OF NON-TRANSLATED TEXT-----

NOTE: To show actual assignments in the following example, you must enter them manually (they are not automatically generated in the Report File we use).

The best way to do this is to take to adjacent user assignments from the User Assignments column and copy them to the Actual Assignments column, then reverse them.

Example

Before: The following excerpt does not show actual assignments

                  Actual

    User       Assignments

Assignments   (if different)      Node Name

MAXPROJ@LC73                      |control5:75|Q2~2

MAXPROJ@LC77                      |control5:75|Q2

After: The following excerpt shows actual assignments that have been entered manually

                  Actual

    User       Assignments

Assignments   (if different)      Node Name

MAXPROJ@LC73   MAXPROJ@LC77       |control5:75|Q2~2

MAXPROJ@LC77   MAXPROJ@LC73       |control5:75|Q2

----END OF NON-TRANSLATED TEXT-----


Clique Assignments Section (Report File)

Lists user-defined cliques and the nodes assigned to cliques in the project’s design files. This section may also list the chip and the LAB or row to which the clique is assigned. For example:

** CLIQUE ASSIGNMENTS **

CLIQUE "fast1"  placed in chip "MAXPROJ", LAB F

    |eval_box:74|POINT

    |eval_box:74|8faddb:45|SUM3

    |eval_box:74|8faddb:45|SUM4

    |eval_box:74|8faddb:45|SUM1

    |eval_box:74|8faddb:45|SUM2

This section is omitted when the project contains no clique assignments. You can also specify whether or not to include this Report File section with the User Assignments option in the Report File dialog box (Processing menu).

See also:

Clique Assignments

Hierarchical Node & Symbol Names

Setting Report File Options


Probe Assignments Section (Report File)

Lists each probe name and the logic function input or output to which it has been assigned in the project’s design files.. For example:

** PROBE ASSIGNMENTS **

Probe Name       Primitive/Macrofunction

DIE_B1           |dsamp2:69|7404:60|:34.Q

DIE_B2           |dsamp2:69|7404:60|:35.Q

DIE_B3           |dsamp2:69|7404:60|:36.Q

POINT            |sync3:78|:47.OUT

This section is omitted if the project contains no probes. You can also specify whether or not to include this Report File section with the User Assignments option in the Report File dialog box (Processing menu).

See also:

Hierarchical Node & Symbol Names

Probe Assignments

Setting Report File Options


Timing Assignments Section (Report File)

Shows the timing results achieved for each type of timing assignment and the nodes to which they have been assigned in the project’s design files. For example:

** TIMING ASSIGNMENTS **

                         User       Actual

Type  Location        Assignment    Value     Status   Critical Path

tpd   <default>          30.0 ns    21.1 ns            RESET to Reset_out

tpd   <default>          30.0 ns    31.6 ns   Failed   SAMPLE to D1_1_7

tpd   <default>          30.0 ns    22.7 ns            SAMPLE to D1_2_6

tpd   <default>          30.0 ns    29.7 ns            SAMPLE to D1_3_5

tpd   <default>          30.0 ns    30.8 ns   Failed   SAMPLE to D1_4

tpd   <default>          30.0 ns    31.6 ns   Failed   SAMPLE to D2_1_7

tpd   <default>          30.0 ns    22.3 ns            SAMPLE to D2_2_6

tpd   <default>          30.0 ns    28.1 ns            SAMPLE to D2_3_5

tpd   <default>          30.0 ns    31.1 ns   Failed   SAMPLE to D2_4

tco   cmpen              10.0 ns    22.5 ns   Failed   CLOCK to cmpen, through register |control5:75|Q2

fmax  <default>        10.00 MHz  13.04 MHz            CLOCK to register DIE_B1 to register |control5:75|Q2

This section is omitted if the project does not contain timing assignments.

Heading:	Description:

Type	Lists the type of timing assignment specified, i.e., tpd, tco, tsu, and/or fmax.

Location	Lists the node for which the timing assignment is specified. If you specified a default timing assignment for the entire project, <default> appears in this column.

User Assignments	Lists the timing specifications you have assigned for the specified nodes.

Actual Value	Lists the actual timing value achieved after compilation.

Status	Shows the timing status. If the timing specifications were not met, the word Failed appears in this column.

Critical Path	Shows the critical timing path for the node in the Location column.

See also:

Hierarchical Node & Symbol Names

Timing Assignments


State Machine Assignments Section (Report File)

Reports state machine assignments made by the Logic Synthesizer for WDFs or AHDL TDFs. For example:

** STATE MACHINE ASSIGNMENTS **

|control5:75|Control: MACHINE

        OF BITS (

           |control5:75|Q2,

           |control5:75|Q1,

           |control5:75|Q0

        )

        WITH STATES (

                       WAIT_ROLL = B"000",

                      CHECK_ROLL = B"010",

                      WAIT_POINT = B"100",

                     CHECK_POINT = B"011",

                            LOST = B"001",

                             WON = B"101"

);

|sync3:78|Debounce: MACHINE

        OF BITS (

           |sync3:78|Debounce~2,

           |sync3:78|Debounce~1

        )

        WITH STATES (

                            Wait = B"00",

                         Rolling = B"10",

                            Done = B"01"

);

The values of the state bits for each state of a state machine are reported in the AHDL State Machine Declaration format. This section is omitted if the project does not contain state machines.

See also:

Creating a Waveform Design File

Hierarchical Node & Symbol Names

Implementing State Machines (AHDL)


File Hierarchy Section (Report File)

Shows the hierarchical node or symbol names of each megafunction and macrofunction in a project. For example:

** FILE HIERARCHY **

|control5:75|

|dice_gen:79|

|dice_gen:79|74163:39|

|dice_gen:79|74163:38|

|dice_gen:79|74374:23|

|dice_gen:79|8fadd:28|

|eval_box:74|

|eval_box:74|7485ns:43|

|eval_box:74|8faddb:45|

|eval_box:74|encode2:46|

|sync3:78|

|dsamp2:69|

|dsamp2:69|7404:60|

|dsamp2:68|

|dsamp2:68|7404:60|

You may need to use a hierarchical node or symbol name in the following circumstances:

When you search for a node or symbol in the MAX+PLUS II Graphic, Text, or Waveform Editor with the Find Node in Design File command (Utilities menu).

When you create a Command File for use with the MAX+PLUS II Simulator, or an SCF or Vector File for use with the MAX+PLUS II Simulator or Programmer.

You can replace hierarchical node names in the project by entering probes in design files.

You can specify whether or not to include this Report File section with the File Hierarchy option in the Report File dialog box (Processing menu).

See also:

Assigning a Probe

Hierarchical Node & Symbol Names

Setting Report File Options


Error Summary Section (Report File)

Lists all Fitter-generated error messages that apply to the device. For example:

** ERROR SUMMARY **

Error: Logic Array Block E requires too many (19/16) shareable expanders

These messages are also listed in the MAX+PLUS II Message Processor window. The Error Summary Section appears in the Report File only if the Fitter detected errors in the project’s design files.

Only Fitter error messages appear in the Error Summary Section of the Report File. Warning and error messages pertaining to the entire project appear in the Project Compilation Messages Section and in the Message Processor window. Some warning messages from previous compilations may not be regenerated. To redisplay all warning messages for the project, turn on Total Recompile (Processing menu) before recompiling a project.

See also:

Hierarchical Node & Symbol Names

MAX+PLUS II Messages


Resource Usage Section (Report File)

Provides a concise description of how the device uses available resources.

The first part of this section includes a table that shows the number of logic cells, I/O pins (including dedicated input pins), shareable expanders used in each LAB, and external interconnect, expressed as both a ratio and a percentage of the resources available in the target device. If the target device contains multiple LABs and a PIA, each LAB’s connections to the PIA are listed. External interconnections for MAX 9000 devices are also shown.

For FLEX 8000 devices, in addition to the number of logic cells and external interconnect, column tracks driven and row tracks driven are shown as both a ratio and a percentage of the resources available in the target device. Clock and Clear/Preset signals are displayed as ratios.

Logic                Column       Row

Array                Interconnect Interconnect         Clear/     External

Block   Logic Cells  Driven       Driven       Clocks  Preset   Interconnect

A1       8/ 8(100%)   7/ 8( 87%)   8/ 8(100%)    1/2    0/2       1/22(  4%)

B2       7/ 8( 87%)   4/ 8( 50%)   2/ 8( 25%)    0/2    0/2      12/22( 54%)

B3       5/ 8( 62%)   3/ 8( 37%)   0/ 8(  0%)    0/2    0/2       8/22( 36%)

C4       1/ 8( 12%)   1/ 8( 12%)   0/ 8(  0%)    0/2    0/2       3/22( 13%)

For devices containing Embedded Array Blocks, a table shows the Embedded Cells, external interconnect, column tracks driven, and row tracks driven in each Embedded Array Block as both a ratio and a percentage of the resources available in the target device. Clock and Read/Write enable signals are displayed as ratios.

Embedded             Column       Row

Array     Embedded   Interconnect Interconnect         Read/      External

Block     Cells      Driven       Driven       Clocks  Write    Interconnect

A37      8/8 (100%)   1/8 ( 12%)   7/8 ( 87%)    1/2    1/1      17/22( 77%)

B37      8/8 (100%)   0/8 (  0%)   8/8 (100%)    1/2    1/1       9/22( 40%)

C37      8/8 (100%)   6/8 ( 75%)   2/8 ( 25%)    1/2    1/1       9/22( 40%)

The second part of this section summarizes overall resource utilization:

The first portion of this section, shown below, shows the number of dedicated input pins, I/O pins, logic cells, shareable expanders, and Embedded Array Blocks that were used to implement the logic in the target device, expressed as both a ratio and a percentage of the resources available. If the logic did not fit, a 0 is shown in these categories.

Total dedicated input pins used:                 4/4    (100%)

Total I/O pins used:                            15/56   ( 26%)

Total logic cells used:                         36/320  ( 11%)

Total shareable expanders used:                 10/320  (  3%)

The following two lines show the ratio and percentage of logic cells for which the logic cell Turbo Bit was turned on, and the number of shareable expanders that are not available, e.g., expanders that are used as standard product terms.

Total Turbo logic cells used:                   37/320  ( 11%)

Total shareable expanders not available (n/a):   5/320  (  1%)

The following lines show how many input pins, output pins, bidirectional pins, flipflops, logic cells, and shareable expanders are needed (after logic synthesis) to implement the logic. For FLEX 8000 and FLEX 10K devices, this information also shows the number of input and output registers and reserved pins required. These statistics are given regardless of whether or not the logic fits in the device. If the logic required the implementation of carry and cascade chains, statistics are given listing the number of logic cells in carry chains, the number of carry chains and their lengths, the number of logic cells in cascade chains, and the number of cascade chains. Additionally the number of single pin Clock Enable and Output Enable signals used is also listed.

Total input pins required:                       6

Total input registers required:                  0

Total output pins required:                     13

Total output registers required:                 0

Total buried I/O cell registers required:        0

Total bidirectional pins required:               0

Total logic cells required:                     36

Total flipflops required:                       24

Total shareable expanders in database:          10

Total packed registers required:                 1

Total logic cells in carry chains:              14

Total number of carry chains:                    2

Total number of carry chains of length  1-8 :    2

Total logic cells in cascade chains:             0

Total number of cascade chains:                  0

Total single-pin Clock Enables required:         0

Total single-pin Output Enables required:        0

The next line shows the number of logic cells that were created to balance the number of shareable expanders used in the device. The Logic Synthesizer converts shareable expanders into logic cells (and vice versa) to use device resources efficiently. These converted logic cells are called "synthesized logic cells." If your project requires large numbers of synthesized logic cells, you may be able to improve device utilization by inserting SOFT buffers into your design files.

Synthesized logic cells:                         0/ 320 (  0%)

The final portion of this section shows the logic cell allocation by row and column.

Logic Cell Counts

Column:  01  02  03  04  05  Total

 A:      0   0   0   6   0      6

 B:      0   8   0   0   0      8

 C:     11   0   0   0   0     11

 D:      0   0  11   0   0     11

Total:  11   8  11   6   0     36

If a device does not include a particular resource, related statistics are not included in the Report File.

See also:

Hierarchical Node & Symbol Names

Implementing LCELL & SOFT Primitives

Recommended reading:

AB60 (Estimating a Design Fit)

AB77 (Fitting Complex Designs for MAX 5000 EPLDs)


Inputs, Outputs & Buried Logic Sections (Report File)

Lists the inputs, outputs, and buried logic for the device.

The following example shows the Inputs Section for a FLEX 10K device:

** INPUTS **

                                                    Fan-In    Fan-Out

 Pin     LC     EC   Row  Col  Primitive    Code     INP  FBK  OUT  FBK  Name

AU21      -     -    -    --      INPUT               0    0    0   11  accel

 A19      -     -    -    --      INPUT               0    0    0    0  clock

AU19      -     -    -    --      INPUT               0    0    0   16  dir0

 A17      -     -    -    --      INPUT               0    0    0   17  dir1

 J37      -     -    C    --      INPUT               0    0    0    8  enable

 A21      -     -    -    --      INPUT               0    0    0   11  reset

Code:

s = Synthesized pin or logic cell

+ = Synchronous flipflop

/ = Slow slew-rate output

! = NOT gate push-back

r = Fitter-inserted logic cell

@ = Uses single-pin Clock Enable

& = Uses single-pin Output Enable

The following example shows the Outputs Section for a FLEX 10K device:

** OUTPUTS **

       Fed By Fed By                                Fan-In    Fan-Out

 Pin     LC     EC   Row  Col  Primitive    Code     INP  FBK  OUT  FBK  Name

  G7      -     -    A    --     OUTPUT               0    1    0    0  at_altera

 H32      -     -    A    --     OUTPUT               0    1    0    0  ticket0

  G5      -     -    A    --     OUTPUT               0    1    0    0  ticket1

  F4      -     -    A    --     OUTPUT               0    1    0    0  ticket2

  C3      -     -    A    --     OUTPUT               0    1    0    0  ticket3

  M2      -     -    C    --     OUTPUT               0    1    0    0  time0

 N33      -     -    C    --     OUTPUT               0    1    0    0  time1

 L37      -     -    C    --     OUTPUT               0    1    0    0  time2

 L35      -     -    C    --     OUTPUT               0    1    0    0  time3

 M32      -     -    C    --     OUTPUT               0    1    0    0  time4

 N31      -     -    C    --     OUTPUT               0    1    0    0  time5

 M36      -     -    C    --     OUTPUT               0    1    0    0  time6

 M34      -     -    C    --     OUTPUT               0    1    0    0  time7

Code:

s = Synthesized pin or logic cell

+ = Synchronous flipflop

/ = Slow slew-rate output

! = NOT gate push-back

r = Fitter-inserted logic cell

@ = Uses single-pin Clock Enable

& = Uses single-pin Output Enable

The following example shows the Buried Logic Section for a FLEX 10K device:

** BURIED LOGIC **

                                    Shareable

                                    Expanders  Fan-In    Fan-Out

Pin   LC  LAB  Primitive     Total Shared n/a INP  FBK   OUT  FBK    Name

  -   85   F     SOFT   s t    1      0   1    0    9     0    1    |control5:75|Q0~2

  -   78   E     DFFE     t    9      0   0    2   13     0   13    |control5:75|Q0

  -   79   E     DFFE     t    0      0   0    2    4     0   13    |control5:75|Q1

(67)  77   E     SOFT   s t    1      0   1    1   11     0    1    |control5:75|Q2~2

(63)  73   E     DFFE     t    6      0   1    2   10     0   12    |control5:75|Q2

(61)  70   E     TFFE     t    0      0   0    2    0     0   18    |dice_gen:79|DIEA0 (|dice_gen:79|74163:39|:34)

(68)  80   E     TFFE     t    0      0   0    2    3     0   16    |dice_gen:79|DIEA1 (|dice_gen:79|74163:39|:35)

  -   66   E     TFFE     t    0      0   0    2    3     0   14    |dice_gen:79|DIEA2 (|dice_gen:79|74163:39|:36)

  -   68   E     TFFE     t    0      0   0    2    0     0   18    |dice_gen:79|DIEB0 (|dice_gen:79|74163:38|:34)

  -   74   E     TFFE     t    0      0   0    2    3     0   16    |dice_gen:79|DIEB1 (|dice_gen:79|74163:38|:35)

(65)  76   E     TFFE     t    0      0   0    2    3     0   14    |dice_gen:79|DIEB2 (|dice_gen:79|74163:38|:36)

(80)  94   F     DFFE     t    0      0   0    0    5     0    1    |dice_gen:79|74374:23|:13

  -   93   F     DFFE     t    3      1   1    0    7     0    1    |dice_gen:79|74374:23|:14

(76)  91   F     DFFE     t    3      3   0    0    9     0    1    |dice_gen:79|74374:23|:15

  -   95   F     DFFE     t    2      2   0    0    9     0    1    |dice_gen:79|74374:23|:16

s = Synthesized pin or logic cell

t = Turbo logic cell

+ = Synchronous flipflop

Information is provided under the following headings:

Heading:	Description:

Pin	Shows the pin assigned to the node name.

LCell	Shows the logic cell number assigned to the node name.

LAB	Shows the LAB assigned to the node name.

Primitive	Shows the name of the primitive associated with the node.

In the Inputs or Outputs Section, primitive names correspond to the following conditions :

OUTPUT:	The node is an output pin fed by combinatorial logic.

TRI:	The node is an output pin fed by combinatorial logic that passes through a TRI buffer.

FF:	The node is either an output pin fed by registered logic or an input pin that feeds a flipflop implemented in an I/O cell register.

TRI/FF:	The node is an output pin fed by registered logic that passes through a TRI buffer.

INPUT:	The node is an input pin.

BIDIR:	The node is a bidirectional pin.

In the Buried Logic Section, primitive names correspond to the primitive that generates the node.

Various symbols may appear after this primitive name:

+	A name followed by a plus symbol (+) indicates that the Clock input to the primitive (i.e., a flipflop or latch) is a global signal.

s	A SOFT primitive name followed by an s indicates that the Logic Synthesizer added the primitive to balance the number of logic cells and shareable expanders used by the device. (If your Report File contains many of these synthesized SOFT buffers, you may be able to improve device utilization by inserting SOFT buffers into your design files.)

s	An INPUT primitive name followed by an s means that the Partitioner created the input when the project was partitioned.

t	A name followed by a t indicates that the logic cell Turbo Bit is turned on for the node in a MAX 7000 device.

g	A name followed by a g indicates that the primitive is assigned to a global logic cell in an EP1810 Classic device.

/	A name followed by / indicates that the output pin has been set to a slow slew rate.

!	A name followed by ! indicates that the logic cell has undergone NOT-gate Push Back during logic synthesis.

r	A name followed by an r indicates that the fitter inserted this logic cell to help routing.

p	A name followed by a p indicates that the this cell was chosen for register packing (MAX 9000 and FLEX 10K only).

@	A name followed by @ indicates that this cell is the source of a single-pin Clock Enable signal (FLEX 10K only).

&	A name followed by & indicates that this cell is the source of a single-pin Output Enable signal (FLEX 10K only).

If MAX+PLUS II creates a logic cell for parallel expanders, the term PEXP appears in the Primitive column.

Shareable

Expanders	Shows the number of Total, Shared, and n/a shareable expanders used. The Total column indicates how many expanders are used in the logic cell associated with the node. The Shared column indicates how many of these expanders are also shared with (i.e., used in) another logic cell. The n/a column shows the number of expanders that are not available (e.g., expanders that are used as standard product terms).

Fan-In	Shows the number of fan-ins -- the number of inputs (INP) from dedicated input and/or I/O pins and the number of feedbacks (FBK) from other logic cells that feed the logic cell associated with the pin.

Fan-Out	Shows the number of fan-outs -- the number outputs (OUT) to dedicated input and/or I/O pins and the number of feedbacks (FBK) to other logic cells that are fed by the logic cell associated with the pin.

Name	Shows the pin name (or buried logic cell node name) assigned by the user. If bidirectional pins have been used (i.e., with dual I/O feedback), the pin name is shown in both the Inputs and Outputs Sections. For PEXP primitives, a name is created. Another name may be added in parentheses; the two names will be synonymous.

See also:

Hierarchical Node & Symbol Names

Implementing LCELL & SOFT Primitives (AHDL)

Recommended reading:

AB77 (Fitting Complex Designs in MAX 5000 EPLDs)


Select the Appropriate Logic Section (Report File)

For help, choose a section:

Logic Cell Interconnections Section

Buried Logic Section


Logic Cell Interconnections Section (Report File)

Details the connectivity of the logic in the device by showing all logic cells and pins that feed each logic cell in the device.

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'A':

                             Logic cells placed in LAB 'A'

        +------------------- LC6 at_altera

        | +----------------- LC3 |auto_max:1|q1

        | | +--------------- LC16 |auto_max:1|street_map~1

        | | | +------------- LC1 |auto_max:1|street_map~2

        | | | | +----------- LC2 |auto_max:1|street_map~5

        | | | | | +--------- LC4 |auto_max:1.speed_too_fast

        | | | | | | +------- LC12 ticket0

        | | | | | | | +----- LC8 ticket1

        | | | | | | | | +--- LC7 ticket2

        | | | | | | | | | +- LC9 ticket3

        | | | | | | | | | |

        | | | | | | | | | |   Other LABs fed by signals

        | | | | | | | | | |   that feed LAB 'A'

LC      | | | | | | | | | | | A B |     Logic cells that feed LAB 'A':

LC6  -> * * * * * * * * * * | * * | <-- at_altera

LC3  -> * * * - - * - - - - | * * | <-- |auto_max:1|q1

LC16 -> * * * * * * * * * * | * - | <-- |auto_max:1|street_map~1

LC1  -> - - * * * * * * * * | * * | <-- |auto_max:1|street_map~2

LC2  -> - - * * * * * * * * | * * | <-- |auto_max:1|street_map~5

LC12 -> - - - - - - * * * * | * - | <-- ticket0

LC8  -> - - - - - - - * * * | * - | <-- ticket1

LC7  -> - - - - - - - - * * | * - | <-- ticket2

* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.

- = The logic cell or pin is not an input to the logic cell (or LAB).

This section is not included in Report Files for FLEX 8000, MAX 9000, and FLEX 10K devices, which have a FastTrack Interconnect Utilization Section.

For devices that contain multiple LABs, the inputs to logic cells are broken down into separate tables for each LAB.

The table headings consists of the logic cell numbers (prefixed with LC) in the "current" LAB, and the names of all LABs (e.g., A through P), available in the device.

Each row in the cross-reference lists three types of information:

The logic cell or pin number that feeds the logic cell(s) in the current LAB. If this number is enclosed in parentheses (), the logic cell is buried.

A row of symbols indicating which logic cells are fed by the node. A node is considered to feed a logic cell if it feeds any input to a D, T, SR, or JK flipflop or a latch; the Output Enable or data input of a tri-state buffer, or any combinatorial function when the logic cell is used for combinatorial logic only. Nodes that are used as global Clock, Clear, Preset, or Output Enable are not listed; these nodes have separate dedicated routing resources.

These symbols are defined as follows:

Symbol:	Description:

*	The logic cell or pin is an input to the logic cell (or LAB) through the PIA.

@	The input pin or logic cell feeds the logic cell (or LAB) using direct interconnect.

-	The logic cell or pin is not an input to the logic cell (or LAB).

The name of the input or output node associated with the pin or logic cell that feeds the logic cell(s) in the current LAB.

In Report Files for devices with multiple LABs, the first group of rows lists logic cells in the current LAB. A blank line separates this group from the pin and logic cell inputs from other LABs.

You can specify whether or not to include this Report File section with the Logic Cell Interconnections option in the Report File dialog box (Processing menu).

See also:

Hierarchical Node & Symbol Names

Setting Report File Options


FastTrack Interconnect Utilization Section (Report File)

Provides a concise description of how the FLEX 8000, MAX 9000, or FLEX 10K device uses available device resources.

The first part of this section shows all horizontal FastTrack Interconnect paths and I/O pins (including bidirectional pins) by row. Resource usage is displayed as both a ratio and a percentage of resources available in the target device. For example:

** FASTTRACK INTERCONNECT UTILIZATION **

Row FastTrack Interconnect:

         FastTrack

Row     Interconnect    Input Pins     Output Pins     Bidir Pins

A:       0/168(  0%)    0/16(  0%)      6/16( 37%)     0/16(  0%)

B:      41/168( 24%)    5/16( 31%)      6/16( 37%)     0/16(  0%)

C:       0/168(  0%)    0/16(  0%)      1/16(  6%)     0/16(  0%)

D:       0/168(  0%)    0/16(  0%)      0/16(  0%)     0/16(  0%)

E:       0/168(  0%)    0/16(  0%)      0/16(  0%)     0/16(  0%)

F:       0/168(  0%)    0/16(  0%)      0/16(  0%)     0/16(  0%)

The second part of this section displays all vertical FastTrack Interconnect paths and I/O pins (including bidirectional pins) by column. For example:

Column FastTrack Interconnect:

         FastTrack

Column  Interconnect    Input Pins     Output Pins     Bidir Pins

01:      0/16(  0%)     0/4(  0%)      1/4( 25%)       0/4(  0%)

02:      0/16(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)

03:      0/16(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)

04:      0/16(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)

05:      0/16(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)

06:      0/16(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)


Clock Signals Section (Report File)

Displays all Clock signal paths by type and lists their fan-outs and signal names. For example:

** CLOCK SIGNALS **

Type     Fan-out    Name

INPUT       14      CLOCK

LCELL       10      |control5:75|CHECK_ROLL


Clear Signals Section (Report File)

Displays all Clear signal paths by type and lists their fan-outs and signal names. For example:

 ** CLEAR SIGNALS **

Type     Fan-out    Name

INPUT       11      RESET


Carry Chains Section (Report File)

Displays all carry chain paths by the type and number of each member of the carry chain. Both the SUM and CARRY path names are displayed. For example:

** CARRY CHAINS **

Type             Member Length    Member Name: SUM, (CARRY)

ARITHMETIC             1          |eval_box:74|8faddb:45|~189~2, (|eval_box:74|8faddb:45|~189~1)

ARITHMETIC             2          |eval_box:74|8faddb:45|~197~1, (|eval_box:74|8faddb:45|:197)

ARITHMETIC             3                                         (|eval_box:74|8faddb:45|:205)

NORMAL                 4          |eval_box:74|~48~3

ARITHMETIC             1          |dice_gen:79|8fadd:28|~189~1, (|dice_gen:79|8fadd:28|:189)

ARITHMETIC             2          |dice_gen:79|8fadd:28|~197~1, (|dice_gen:79|8fadd:28|:197)

NORMAL                 3          |dice_gen:79|74374:23|:16


Equations Section (Report File)

Contains the minimized equations for all logic in the project.

Signal names in the equations are given as pin, hierarchical node, and probe names.

The Equations Section begins with a list of all input pins that are used in the device, and then shows the equations. The equations, which represent the results of extensive logic synthesis, are provided for your reference. Since logic synthesis minimizes the logic required to implement a project, redundant or unneeded logic in the original design files may not appear in the Report File.

An equation can have any of the following formats:

<Q output> = DFF(<D input>, <Clock>, <Clear>, <Preset>);

<Q output> = DFFE(<D input>, <Clock>, <Clear>, <Preset>, <Clock Enable>);

<Q output> = TFF(<T input>, <Clock>, <Clear>, <Preset>);

<Q output> = TFFE(<T input>, <Clock>, <Clear>, <Preset>, <Clock Enable>);

<Q output> = LATCH(<D input>, <Latch Enable>);

<pin name> = TRI(<input>, <Output Enable>);

<pin name> = _LC<name>;

_LC<name> = LCELL(<input>);

_LC<name>_CARRY = CARRY(<input>);

_X<number> = EXP(<expression>);

<symbol> = <expression>;

Equations include the following components:

Component:	Description:

_LC<name>	Represents a node that has been assigned to the specified logic cell number.

_X<number>	Represents a node that has been assigned to an expander product term.

_N<number>	Represents a node that the Fitter could not assign to either a pin or a logic cell.

_EQ<number>	Represents another equation in this section.

_IOE_<name>	Represents a node that has been assigned to a specific I/O register.

CASCADE(<input>)	Represents a CASCADE buffer that has been inserted by the Logic Synthesizer.

GLOBAL(<input>)	Represents a signal from a dedicated input pin that does not pass through the logic array before performing its specified function.

&	AND operator.

!	NOT operator.

#	OR operator.

$	XOR (exclusive OR) operator.

Each equation is preceded by comments describing the node name, the node source if from a TDF, the equation name, location, and type. For example:

-- Node name is 'at_altera' = '|auto_max:1|q0' from file "auto_max.tdf" line 13, column 21

-- Equation name is 'at_altera', type is output

 at_altera = DFFE( _EQ001 $  GND, GLOBAL( clock), !reset,  VCC,  VCC);

  _EQ001 =  accel & !dir0 & !dir1 &  _LC016

         # !dir0 & !dir1 &  _LC003

         #  at_altera;

Comments have the following BNF format:

-- Node name is '[<user-assigned node name> ' = ]'<hierarchical node name>' [from file "<filename.tdf>" line <number>, column <number>]

-- Equation name is '<equation name>' type is [input | output | bidir | memory | buried]

The Equations Section may also include one or more of the following comments:

Equations for synthesized logic cells (shown as Synthesized in the Buried Logic Section) are preceded with the following comment:

% synthesized logic cells %

Logic cells that borrow parallel expanders from adjacent logic cells are preceded by one of the following comments:

% _LC<number> borrows parallel expanders from _LC<number> [_LC<number>] %

or:

% _LC<number> borrows parallel expanders %

Logic cells that lend parallel expanders to adjacent logic cells are preceded with the following comment:

% _LC<number> lends parallel expanders to _LC<number> %

Report files for devices containing a PIA list shareable expanders that have been duplicated in multiple LABs, as shown in the following comment. If this section is extremely long, contact Altera Applications for assistance in optimizing your project.

%

Shareable expanders that are duplicated in multiple LABs:

_X<number> occurs in LABs <LAB names>

%

You can specify whether or not to include this Report File section with the Equations option in the Report File dialog box (Processing menu).

See also:

Hierarchical Node & Symbol Names

Setting Report File Options


Compilation Settings & Times Section (Report File)

Lists the settings for commands on the Compiler’s Processing and Interfaces menus, the total time required to compile the project, and compilation times for individual Compiler modules and utilities. Example

Information is listed under the following headings:

Heading:	Menu Command:

Processing Menu Commands	Design Doctor Settings (Shows the rules set selected for the analysis)

Functional SNF Extractor

Linked SNF Extractor

Timing SNF Extractor

Optimize Timing SNF

Generate AHDL TDO File

Fitter Settings

Smart Recompile	Total Recompile

Interfaces Menu Commands	EDIF Netlist Writer

Verilog Netlist Writer

VHDL Netlist Writer

Assign Menu Commands	Global Project Logic Synthesis (Shows the default logic synthesis style, the logic option settings within that style, and automatic global signal and other options)

Global Project Timing Requirements

Compiler Module/Utility:

Compilation Times	Compiler Netlist Extractor, including EDIF Netlist Reader/XNF Netlist Reader/VHDL Netlist Reader

Database Builder

Logic Synthesizer

Design Doctor

Partitioner

Fitter

Timing SNF Extractor

Functional SNF Extractor

Assembler

Memory Allocated	Shows the greatest amount of memory allocated during compilation.

The Compilation Settings and Times Section is appended to the Report File after the Assembler has finished generating programming file(s) for the project.


Compilation Settings & Times Section Example

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands

------------------------

Design Doctor                             = on

   Rules                                  = EPLD Rules

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore

      CARRY_CHAIN                         = 32

      CASCADE_CHAIN                       = ignore

      CASCADE_CHAIN                       = 2

      DECOMPOSE_GATES                     = on

      DUPLICATE_LOGIC_EXTRACTION          = on

      MINIMIZATION                        = full

      MULTI_LEVEL_FACTORING               = on

      NOT_GATE_PUSH_BACK                  = on

      REDUCE_LOGIC                        = on

      REFACTORIZATION                     = on

      REGISTER_OPTIMIZATION               = on

      RESYNTHESIZE_NETWORK                = on

      SLOW_SLEW_RATE                      = off

      SUBFACTOR_EXTRACTION                = on

      IGNORE_SOFT_BUFFERS                 = on

   Other logic synthesis settings:

      Automatic Global Clock              = on

      Automatic Global Clear              = on

      Automatic Global Preset             = on

      Automatic Global Output Enable      = on

      Automatic I/O Cell Registers        = on

      Automatic Register Packing          = on

      Automatic Open-Drain Pins           = on

      Automatic Implement in EAB          = on

      One-Hot State Machine Encoding      = on

      Optimize                            = 5

Default Timing Specifications:

   tpd                                    = 55ns

Cut All Bidir Feedback Timing Paths       = on

Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off

Timing SNF Extractor                      = on

Optimize Timing SNF                       = off

Generate AHDL TDO File                    = on

Fitter Settings                           = ADVANCED

Smart Recompile                           = on

Total Recompile                           = off

Interface Menu Commands

-----------------------

EDIF Netlist Writer                       = off

Verilog Netlist Writer                    = off

VHDL Netlist Writer                       = off

Compilation Times

-----------------

   Compiler Netlist Extractor             00:00:02

   Database Builder                       00:00:02

   Logic Synthesizer                      00:00:05

   Partitioner                            00:00:02

   Fitter                                 00:00:38

   Timing SNF Extractor                   00:00:03

   Assembler                              00:00:27

   Design Doctor                          00:00:01

   --------------------------             --------

   Total Time                             00:01:20

Memory Allocated

-----------------

Peak memory allocated during compilation  = 18,378K


Compiler Commands
Commands

<application name> Help Basic Tools

<application name> Help Commands

<application name> Help Golden Rules

<application name> Help Introduction

<application name> Help Procedures

<application name> Help Shortcuts

<application name> Help Table of Contents

About MAX+PLUS II

Advanced Options

AHDL

Archive

Arrange Icons

Authorization Code

Auto Device Selection

Back-Annotate Project

Basic Tools

Cascade

Classic & MAX Global Project Device Options

Classic & MAX Individual Device Options

Clear Project Assignments

Clique

Close ( [image] and [image] menus)

Color Palette

Combine Programming Files

Commands

Compiler

Connected Pins

Convert Obsolete Assignment Format

Define Synthesis Style

Delete File

Design Doctor Settings

Design Doctor

Device

Devices & Adapters

EDIF Netlist Reader Settings

EDIF Netlist Writer Settings

EDIF Netlist Writer

ES Site License Authorization Request

Exit MAX+PLUS II

Fitter Settings

FLEX 10K Global Project Device Options

FLEX 10K Individual Device Options

FLEX 8000 Global Project Device Options

FLEX 8000 Individual Device Options

Floorplan Editor

Functional SNF Extractor

Generate AHDL TDO File

Global Project Device Options

Global Project Logic Synthesis

Global Project Timing Requirements

Glossary

Golden Rules

Graphic Editor

Hierarchy Display

Hierarchy Project Top

How to Use Help

How to Use MAX+PLUS II Help

Ignore Project Assignments

Individual Logic Options

Introduction

Linked SNF Extractor

Logic Options

Macrofunctions

MAX 7000S Global Project Device Options

MAX 7000S Individual Device Options

MAX+PLUS II Registration

MAX+PLUS II Table of Contents

Maximize

Message Processor

Messages

Minimize

More Windows

Move

Name

New Features in This Release

New Window

New

Next

Open

Optimize Timing SNF

Override User Assignments Dialog Box

Partitioner/Fitter Status Dialog Box

Pin/Location/Chip

Preferences

Preserve All Node Name Synonyms

Primitives

Probe

Procedures

Programmer

Project 1, 2, 3, 4...

Project Archive

Project Name

Project Save & Check

Project Save & Compile

Project Save & Simulate

Project Save, Compile & Simulate

Project Set Project to Current File

READ.ME

Rename Chip

Report File Settings

Restore

Save & Check

Save & Compile

Save & Simulate

Save Style As

Save, Compile & Simulate

Search for Help on

Search Node Database

Set Project to Current File

Shortcuts

Show Status Bar

Show Toolbar

Simulator

Size

Smart Recompile

Switch To

Symbol Editor

Table of Contents

Text Editor

Tile Horizontally

Tile Vertically

Timing Analyzer

Timing Requirements

Timing SNF Extractor

Total Recompile

User Libraries

Verilog Netlist Writer Settings

Verilog Netlist Writer

VHDL Netlist Reader Settings

VHDL Netlist Writer Settings

VHDL Netlist Writer

VHDL

Waveform Editor

XNF Netlist Reader Settings


Design Doctor Command (Compiler)
Design Doctor Command (Processing Menu)

Turns the Design Doctor on or off.

When the Design Doctor command is turned on, the Design Doctor icon appears in the Compiler window below the Logic Synthesizer module box. You can double-click Button 1 on this icon to display a message that summarizes the current status of the Design Doctor analysis. A project that is free of warning messages--based on a specific set of design rules--is given a "clean bill of health."

You can choose Design Doctor Settings (Processing menu) to specify the set of design rules that the Design Doctor uses for project reliability analysis. These design rules are based on the Project Reliability Guidelines.

The Compilation Settings & Times Section of the Report File records the rule set selected for compilation, as well as the processing time used by this utility during compilation.

See also:

Checking Project Reliability with the Design Doctor

Ensuring Project Reliability

Project Reliability Checklist


Design Doctor Settings Command (Compiler)
Design Doctor Settings Command (Processing Menu)

Specifies the set of design rules that the Design Doctor uses for project reliability analysis. These design rules are based on the Project Reliability Guidelines.

Click Button 1 on any item in this dialog box for information on that item:

If you choose the Advanced Options button, the expanded Design Doctor Settings dialog box opens. Click Button 1 on any item in this dialog box for information on that item:

When the Design Doctor command (Processing menu) is turned on, the Design Doctor icon appears in the Compiler window below the Logic Synthesizer module box. You can double-click Button 1 on this icon to display a message that summarizes the current status of the Design Doctor analysis. A project that is free of warning messages--based on a specific set of design rules--is given a "clean bill of health."

The Compilation Settings & Times Section of the Report File records the rule set selected for compilation, as well as the processing time used by this utility during compilation.

See also:

Checking Project Reliability with the Design Doctor

Ensuring Project Reliability

Project Reliability Checklist


Design Rules

EPLD Rules	Turns on all design rule options except Static Hazards, After Synthesis, Asynchronous Inputs, and Master Reset. EPLD Rules is used to analyze a project that will be implemented EPLDs. This set of rules is the default selection for new projects.

FLEX Rules	Turns on all design rule options except Static Hazards, After Synthesis and Master Reset. FLEX Rules is used to analyze a project that will be implemented in FLEX 8000 or FLEX 10K devices.

MPLD Rules	Turns on all design rule options. This stringent set of rules is used to analyze a project that will be implemented in MPLDs.

Custom Rules	Turns on a combination of design rule options you have selected in the expanded Design Doctor dialog box.

If you select the EPLD Rules, FLEX Rules, or MPLD Rules settings, then choose the Advanced Options button and change a setting, the Custom Rules setting is automatically selected for Design Rules.


Advanced Options

Expands the current dialog box to display all design rule options.


Clocks

Ripple Clock	Checks for ripple Clock configurations.

Gated Clock	Checks for gated Clock configurations in which either the logic driving the Clock does not consist of a single AND or OR gate, or more than one input to the logic gate acts as the actual Clock.

Multi-Level Clocks	Checks for multi-level Clock configurations.

Multi-Clock Networks	Checks for multi-Clock networks.


Static Hazards

Before Synthesis	Checks the project before logic synthesis for static hazards in combinatorial networks and in logic that feeds the secondary inputs of a flipflop or state machine.

After Synthesis	Checks the project after logic synthesis for static hazards in combinatorial networks and in logic that feeds the secondary inputs of a flipflop or state machine.


Preset/Clear Networks

Checks for Preset and Clear configurations that violate the Preset & Clear Configuration Guidelines.


Asynchronous Inputs

Checks for any asynchronous input pin that drives more than one flipflop or drives pure combinatorial logic that in turn drives multiple flipflops. An input pin that feeds a purely combinatorial network is not subject to this check, unless the network feeds a data input or Clock Enable input of a flipflop.


Delay Chains

Checks for delay chains.


Race Conditions

Checks for flipflops that depend on their own outputs for their secondary inputs, which can cause race conditions.


Expander Networks

Checks for the presence of expander networks.


Master Reset

Checks for the presence of a board-level master Reset signal that clears every flipflop in the project. If a master Reset does not exist, the Design Doctor attempts to identify a common pin that resets all or the majority of flipflops in the project.


Design Rule Settings in EPLD, FLEX, and MPLD Rules

EPLD Rules	FLEX Rules	MPLD Rules

Clocks

Ripple Clock

Gated Clock

Multi-Level Clocks

Multi-Clock Networks

Static Hazards

Before Synthesis

After Synthesis

Other Rules

Preset/Clear Network

Asynchronous Inputs

Delay Chains

Race Conditions

Expander Networks

Master Reset


Functional SNF Extractor Command (Compiler)
Functional SNF Extractor Command (Processing Menu)

Turns the Functional SNF Extractor on or off.

When you turn the Functional SNF Extractor command on, the Functional SNF Extractor module box appears in the Compiler window. If the project compiles successfully, a functional SNF is created, and overwrites any existing functional or timing SNF with the same name.

Since creating a functional SNF uses only the Compiler Netlist Extractor, Database Builder, and Functional SNF Extractor modules, all other module boxes disappear from the Compiler window until you turn Functional SNF Extractor off. In addition, when Functional SNF Extractor is turned on, the only commands available on the Interfaces and Processing menus are EDIF Netlist Reader Settings, Smart Recompile, and Total Recompile. Turning Functional SNF Extractor or Linked SNF Extractor (Processing menu) on also temporarily disables the Timing SNF Extractor module.

The Compilation Settings & Times Section of the Report File records the processing time used by this module during compilation.

See also:

Creating a Functional Simulator Netlist File

Functional Simulation Mode (Simulator)

Simulator Netlist File (.snf)


Timing SNF Extractor Command (Compiler)
Timing SNF Extractor Command (Processing Menu)

Turns the Timing SNF Extractor on or off.

When you turn the Timing SNF Extractor command on, the Timing SNF Extractor module box appears in the Compiler window. If the project compiles successfully, a timing SNF is created, and overwrites any existing timing or functional SNF with the same name.

This command is turned on automatically if you specify timing assignments for the project, default timing assignments with the Global Project Timing Requirements command (Assign menu), or if you turn on the EDIF Netlist Writer command (Interfaces menu).

Timing SNF Extractor is dimmed and the module is turned off if you turn on the Functional SNF Extractor or Linked SNF Extractor command (Processing menu). After you turn Functional SNF Extractor off, Timing SNF Extractor returns to its previous on or off state.

The Compilation Settings & Times Section of the Report File records the processing time used by this module during compilation.

See also:

Creating EDIF Output Files

Creating a Timing Simulator Netlist File

Simulator Netlist File (.snf)

Timing Simulation Mode (Simulator)


Linked SNF Extractor Command (Compiler)
Linked SNF Extractor Command (Processing Menu)

Turns the Linked SNF Extractor on or off.

When turn the Linked SNF Extractor command on, the Linked SNF Extractor module box appears in the Compiler window. If the super-project compiles successfully, a linked SNF is created, and overwrites any existing linked, functional, or timing SNF with the same name.

Since creating a linked SNF uses only the Compiler Netlist Extractor, Database Builder, and Linked SNF Extractor modules, all other module boxes disappear from the Compiler window until you turn Linked SNF Extractor off. In addition, when Linked SNF Extractor is turned on, the only commands available on the Interfaces and Processing menus are EDIF Netlist Reader Settings, Smart Recompile, and Total Recompile. Turning Linked SNF Extractor on also temporarily disables the Functional SNF Extractor and Timing SNF Extractor modules.

The Compilation Settings & Times Section of the Report File shows whether this command was turned on or off during project compilation.

See also:

Combining Multiple Projects for Simulation

File Structure Requirements for Multi-Project Simulation

Linked Simulation Mode (Simulator)

Simulator Netlist File (.snf)


Optimize Timing SNF Command (Compiler)
Optimize Timing SNF Command (Processing Menu)

Turns the optimizing feature of the Timing SNF Extractor on or off.

When you compile a project with Optimize Timing SNF turned on, the Compiler replaces sections of combinatorial logic in the timing SNF being generated with dynamic models. Each dynamic model represents a particular type of combinatorial logic. During simulation, the Simulator can refer to a dynamic model, instead of interpreting all the logic in a combinatorial network. If your project contains large sections of combinatorial logic, an optimized timing SNF can significantly reduce the time required for simulation.

An optimized timing SNF provides the same functional and timing information as a non-optimized timing SNF. It also increases the speed of a timing analysis.

Optimize Timing SNF is available only if the Timing SNF Extractor command (Processing menu) is turned on.

Optimized timing SNFs generated with earlier versions of MAX+PLUS II do not work in the MAX+PLUS II Simulator. You must recompile the project with the current version of MAX+PLUS II to use an optimized timing SNF in the Simulator.

The Compilation Settings & Times Section of the Report File records the processing time used by this module during compilation.

See also:

Creating a Timing Simulator Netlist File

Simulator Netlist File (.snf)


Fitter Settings Command (Compiler)
Fitter Settings Command (Processing Menu)

Specifies options for the Fitter and Logic Synthesizer to use in compiling a project. These options guide the Fitter in determining when to insert LCELL buffers (i.e., logic cells) automatically or to use other options to achieve a fit.

Click Button 1 on any item in this dialog box for information on that item:

If you choose the Customize button, the expanded Fitter Settings dialog box opens. Click Button 1 on any item in this dialog box for information on that item:

Many of the Fitter settings improve project fitting through automatic LCELL insertion. However, inserting LCELL buffers in a project increases its logic cell usage and slows its performance. If you want the Fitter to perform minimal automatic LCELL insertion, you should select the Normal Fitting option, which is the default Fitter setting. If you want the Fitter to refrain from inserting LCELLs automatically, you must select the Custom Fitting option, choose the Customize button, and turn off all options listed under Auto Logic Cell Insertion Options.

The automatic LCELL insertion Fitter settings are different from the SOFT Buffer Insertion logic option in that SOFT Buffer Insertion adds SOFT buffers during logic synthesis to help simplify the logic in your project, whereas the automatic LCELL insertion Fitter settings simply add LCELL buffers during fitting to help achieve a successful fit.

This command is available only if the Functional SNF Extractor and Linked SNF Extractor commands (Processing menu) are turned off. The Error Summary Section of the Report File shows which Fitter settings were used during project compilation.

1.	Be sure to refer to Guidelines for Working with Assignments for absolutely essential information on using all types of types of resource, probe, and device assignments, including logic synthesis style and logic option assignments.

2.	If you use the Advanced Try Harder/Longer Compilation Fitting option, you can manually re-enter successful Fitter settings as Custom Fitting settings to preserve them in subsequent compilations, as described in Specifying Fitter Settings.

See also:

Clearing Assignments for a Project

Fitting & Refitting a Project

Specifying Devices for Automatic Device Selection


Normal Fitting (Auto Logic Cell Insertion Only)

Directs the Compiler to insert LCELL buffers automatically into a project if user-defined resource and device assignments would otherwise prevent a project from fitting. If no user-defined resource or device assignments exist, no LCELLs are inserted. This setting is the default for new projects.

Although this option does improve project fitting, inserting LCELL buffers in a project increases its logic cell usage and slows its performance. If you want the Fitter to refrain from inserting any LCELLs automatically, you must select the Custom Fitting option, choose the Customize button, and turn off all options listed under Auto Logic Cell Insertion Options.


Advanced Try Harder/Longer Compilation Fitting (Auto Logic Cell Insertion Plus Other Options)

Directs the Compiler to cycle through a predefined suite of different Fitter settings to attempt to find a fit. This option directs the Compiler to insert LCELL buffers automatically into a project if they are needed to achieve a fit in a more agressive fashion than the Normal Fitting option. It also directs the Compiler to use additional fitting options. Selecting this option can reduce fitting problems, but fitting may take longer than if the Normal Fitting option is selected. In addition, inserting LCELL buffers in a project increases its logic cell usage and slows its performance.

This option affects only FLEX 8000, FLEX 10K and MAX 9000 devices.

You may wish to turn on this option if you want to allow the Compiler to run for a longer period of time (e.g., overnight) while attempting a fit.


Custom Fitting

Directs the Compiler to use previously defined custom Fitter settings or to define new settings. To display all settings, choose the Customize button to display the expanded Fitter Settings dialog box.

Altera recommends contacting Altera Applications for assistance with all Custom Fitting options.


Customize

Opens the expanded Fitter Settings dialog box, which allows you to set custom options that control automatic logic cell insertion and other options that the Compiler can use to achieve a fit.


Auto Logic Cell Insertion Options

Normal	Directs the Compiler to insert LCELL buffers automatically if user-defined resource and device assignments would otherwise prevent the project from fitting with the current pin assignments.

Row Pins with Fan-Out Greater Than

% of the Logic Cells per Row	Directs the Compiler to insert LCELL buffers automatically if row pins that have a fan-out greater than the specified percentage of logic cells per row would otherwise prevent the project from fitting with the current pin assignments. You can specify a percentage of 0% to 100%. LCELL buffers are inserted just after the pins.

Output Pins Fed by Carry Chains	Directs the Compiler to insert LCELL buffers automatically if an output pin that is fed by a carry chain would otherwise prevent the project from fitting with the current pin assignments.

Altera recommends contacting Altera Applications for assistance with all Custom Fitting options.


Other Options (As a % of Device Family Default)

Each device family has different default values for the following options. The Compiler multiplies the percentages you enter by the defaults for the device family that is selected for the current project.

Expanders per Logic Cell (0% to 1000%)	Specifies the percentage of expander product terms allowed per logic cell, relative to the default value for the device family. A higher percentage directs the Compiler to use additional expanders.

Fan-In per Logic Cell (10% to 200%)	Specifies the maximum percentage of signal fan-in allowed for logic cells, relative to the default value for the device family. This option applies to multi-level synthesis only. A higher percentage limits the maximum fan-in to a logic cell by inserting LCELL buffers.

Logic Cells per Row (0% to 100%)	Specifies the percentage of logic cells allowed per row, relative to the default value for the device family. If you have a project in which many logic cells are packed into a few rows, but the remainder of the device is less heavily used, you can limit the number of logic cells allowed in each row. This technique can help redistribute the project logic within the device. For example, fitting problems can occur when a project has a high ratio of inputs to logic cells. The Compiler has a built-in feature that attempts to balance an evenly distributed number of logic cells per row versus the speed achieved by fitting the project logic into the device as compactly as possible. You can control this balance by limiting the number of logic cells allowed in each row.

Increasing the percentage of each of these options decreases the likelihood of a successful fit, and vice versa.

Altera recommends contacting Altera Applications for assistance with all Custom Fitting options.


Fitter Settings dialog box

Click Button 1 on any item in this dialog box for information on that item:


Expanded Fitter Settings dialog box

Click Button 1 on any item in this dialog box for information on that item:


Report File Settings Command (Compiler)
Report File Settings Command (Processing Menu)

Specifies optional sections to be included in the Report File, which is created by the Fitter when a project is compiled.

Click Button 1 on any item in this dialog box for information on that item:

This command is available only if the Functional SNF Extractor and Linked SNF Extractor commands (Processing menu) are turned off.

See also:

Report File Format

Setting Report File Options


Report File Settings dialog box

Click Button 1 on any item in this dialog box for information on that item:


Optional Report File Sections

User Assignments	Includes the Pin/Location/Chip Assignments, Probes, and Clique Assignments sections in the Report File.

File Hierarchy	Includes the File Hierarchy Section in the Report File

Logic Cell Interconnections	Includes the Logic Cell Interconnections Section in the Report File.

Equations	Includes the Equations Section in the Report File.

All	Includes all optional sections in the Report File. This option is turned on by default.


Generate AHDL TDO File Command (Compiler)
Generate AHDL TDO File Command (Processing Menu)

Creates one or more AHDL Text Design Output Files, as well as one or more Assignment & Configuration Output Files, when a project compiles successfully.

A TDO File contains the fully optimized logic for a single device. You can save a TDO File as a Text Design File, edit it, specify as it as the project with Project Name (File menu), and recompile the project. (You must also save the ACO File as an Assignment & Configuration File if you wish to preserve the assignments for the device.)

The TDO File contains new node names that represent the flattened hierarchy. If the new node names exceed 32 name characters, you must shorten  the node names before you compile.

The filenames of the TDO File(s) and ACO File(s) are the same as the user-defined chip name(s) for the project; if no chip names exist, the Compiler assigns filenames that are based on the project name. For a multi-device project, MAX+PLUS II also generates a top-level TDO File that is uniquely identified by "_t" appended to the the project name. Example

See also:

AHDL Help Contents

Creating AHDL Text Design Output Files


Smart Recompile Command (Compiler)
Smart Recompile Command (Processing Menu)

Directs the Compiler to save database information for the current project to database files during the next compilation, which may improve the speed of future compilations. The first compilation after you turn on Smart Recompile requires more time than a normal compilation, because the Compiler may take extra time to save all the database information. However, after the Compiler saves the database information, future compilations can be much faster. During a "smart" recompilation, the Compiler always determines which modules are required to process the project based on the changes you have made to your project since the last compilation, then skips any modules that are not required.

For example, if you compile a project with Smart Recompile turned on, and then change only a pin assignment, the next time you compile the project the Compiler starts compilation at the Fitter module. The Compiler Netlist Extractor, Database Builder, and Logic Synthesizer modules are skipped, so the resulting compilation time will be considerably shorter than a normal compilation.

1.	When the Compiler skips a module during a smart recompilation, the Message Processor does not redisplay any messages that the skipped module issued during the last compilation.

2.	Turning on Smart Recompile uses much more disk space than normal compilation, to store the database files.

3.	If you make any changes to the logic of your design, the Compiler must use all modules during processing.

See also:

Compiling a Project

Recompiling a Project with Smart Recompile

Starting & Stopping the Compiler

Totally Recompiling a Project


Total Recompile Command (Compiler)
Total Recompile Command (Processing Menu)

Directs the Compiler to completely recompile all design files

When you compile a project after turning on Total Recompile, the Compiler re-creates all CNFs and HIFs, and redisplays warning messages generated by the Compiler Netlist Extractor. If a project is compiled with Total Recompile turned off, warning messages generated by the Compiler Netlist Extractor during previous compilations are not redisplayed.

Total Recompile is turned off automatically each time you close the Compiler window or change the project name. The Compilation Settings & Times Section of the Report File shows whether this command was turned on or off during project compilation.

See also:

Compiling a Project

Starting & Stopping the Compiler

Totally Recompiling a Project


Preserve All Node Name Synonyms Command (Compiler)
Preserve All Node Name Synonyms Command (Processing Menu)

Preserves all node name synonyms in the Node Database File for the project.

If the Preserve All Node Name Synonyms command is turned off, node name synonyms will not be added to the Node Database File, so the Node Database File will contain only one node name per node. However, all user-defined node names will be included in the Node Database File.

See also:

Preserving All Node Name Synonyms


EDIF Netlist Reader Settings Command (Compiler)
EDIF Netlist Reader Settings Command (Interfaces Menu)

Specifies Library Mapping Files and options for the Compiler Netlist Extractor to use in compiling EDIF Input Files.

Click Button 1 on any item in this dialog box for information on that item:

If you choose the Customize button, the expanded EDIF Netlist Reader Settings dialog box opens. Click Button 1 on any item in this dialog box for information on that item:

See also:

Compiling EDIF Input Files

EDIF 2 0 0 Constructs Interpreted by MAX+PLUS II

EDIF 3 0 0 Constructs Interpreted by MAX+PLUS II

Library of Parameterized Modules Support

Library Mapping File Format

Recommended reading:

AB96 (Generating Library Mapping Files)


EDIF Netlist Reader Settings Dialog Box (Compiler)
EDIF Netlist Reader Settings dialog box

Click Button 1 on any item in this dialog box for information on that item:


Expanded EDIF Netlist Reader Settings Dialog Box (Compiler)
Expanded EDIF Netlist Reader Settings dialog box

Click Button 1 on any item in this dialog box for information on that item:


Vendor

Specifies the CAE tool vendor you are using to create your EDIF Input File. If you select a specific vendor name, the Compiler selects the default EDIF Netlist Reader settings for that vendor. If you select Custom, you can define your own EDIF Netlist Reader settings or use customized settings you have defined previously.

You can choose the Customize button to display and edit all EDIF Netlist Reader settings:

If you have selected a specific vendor name for Vendor, the default VCC and GND settings for that vendor are shown under Signal Names and the Altera-provided LMF for that vendor is shown in the LMF #1 box under Library Mapping Files. If you change any of these settings, the Vendor box automatically displays the Custom option.

If you have selected the Custom option for Vendor, you can define new settings for the GND and VCC options under Signal Names and the LMF #1 and LMF #2 options under Library Mapping Files. You can also change any custom settings you had defined previously.

The current setting under Vendor is preserved when you compile a new project.


Customize

Expands the current dialog box to display all EDIF Netlist Reader settings.


Show LMF Mapping Messages

Displays extensive information messages in the Message Processor and Report File that show the progress of LMF mapping during compilation.


Library Mapping Files

Specifies up to two Altera-provided or custom LMFs for the Compiler to use when compiling EDIF Input Files. Click Button 1 on the LMF #1 or LMF #2 checkbox to turn on the option.

You can type a filename in the LMF #1 or LMF #2 box, or select a name in the Files box to copy it to the LMF #1 or LMF #2 box. If a vendor name is selected under Vendor, the Altera-provided LMF for that vendor is listed for LMF #1. If Custom is selected under Vendor, and you had previously specified LMFs, the LMF name(s) will be listed in the LMF #1 and LMF #2 boxes. You can also type a text string that contains wildcard characters in the LMF #1 or LMF #2 box, then choose OK to update the contents of the Files box with the filenames that match the new text string.


Signal Names

VCC 	Specifies the global high signal used in the project’s EDIF Input File(s). The default name is either VCC or the name typically used by the vendor that is specified in the Vendor box. Type a signal name with up to 20 name characters.

GND 	Specifies the global low signal used in the project’s EDIF Input File(s). The default name is either GND or the name typically used by the vendor that is specified in the Vendor box. Type a signal name with up to 20 name characters.


Directories; list box
Directories

Lists all available disk drives and all subdirectories of the current directory.

You can type a different absolute or relative pathname in the LMF #1 or LMF #2 box and choose OK or double-click Button 1 on a name in the Directories box to change the current directory.


Files; for opening/selecting files
Files

Lists all files in the current directory that match the text string in the LMF #1 or LMF #2 box.

Selecting a filename in the Files box copies it to the LMF #1 or LMF #2 box. You can also type a text string that includes wildcard characters in the LMF #1 or LMF #2 box, then choose OK to update the contents of the Files box with the filenames of the files that match the new text string.


EDIF Netlist Writer Command (Compiler)
EDIF Netlist Writer Command (Interfaces Menu)

Turns the EDIF Netlist Writer module on or off. When the EDIF Netlist Writer is on, it generates one or more EDIF Output Files that can be used with third-party simulators.

You can choose EDIF Netlist Writer Settings (Interfaces menu) to specify the configuration options the EDIF Netlist Writer uses to generate EDIF Output Files.

The filenames of the EDIF Output File(s) and optional SDF Output File(s) are the same as the user-defined chip name(s) for the project; if no chip names exist, the Compiler assigns filenames that are based on the project name. For a multi-device project, MAX+PLUS II also generates a top-level EDIF Output File that is uniquely identified by "_t" appended to the the project name. Example

Turning this command on automatically turns on the Timing SNF Extractor command (Processing menu).

The Compilation Settings & Times Section of the Report File records the processing time used by this module during compilation.

When the EDIF Netlist Writer is turned on, the EDIF Netlist Writer module box appears in the Compiler window.

See also:

Creating EDIF Output Files


EDIF Netlist Writer Settings Command (Compiler)
EDIF Netlist Writer Settings Command (Interfaces Menu)

Specifies EDIF conversion options and EDIF Command Files for the Compiler to use in generating EDIF Output Files.

Click Button 1 on any item in this dialog box for information on that item:

If you choose the Customize button, the expanded EDIF Netlist Writer Settings dialog box opens. Click Button 1 on any item in this dialog box for information on that item:

The filenames of the EDIF Output File(s) and optional SDF Output File(s)  are the same as the user-defined chip name(s) for the project; if no chip names exist, the Compiler assigns filenames that are based on the project name. For a multi-device project, MAX+PLUS II also generates a top-level EDIF Output File that is uniquely identified by "_t" appended to the the project name. Example

See also:

Creating EDIF Output Files

EDIF Command File Format

Hierarchical Node & Symbol Names

Primitives in Simulator Netlist Files & EDIF Output Files


EDIF Netlist Writer Dialog Box (Compiler)
EDIF Netlist Writer Settings dialog box

Click Button 1 on any item in this dialog box for information on that item:


EDIF Netlist Writer Dialog Box (Compiler)
Expanded EDIF Netlist Writer Settings dialog box

Click Button 1 on any item in this dialog box for information on that item:


Vendor

Specifies the target CAE tool vendor for the EDIF Output File(s). If you select a specific vendor name, the Compiler selects the default EDIF Netlist Writer settings for that vendor. If you select Custom, you can define your own EDIF Netlist Writer settings or use customized settings you have defined previously.

You can choose the Customize button to display and edit all EDIF Netlist Writer settings:

If you have selected a specific vendor name for Vendor, the default EDIF Netlist Writer settings for that vendor are shown. If you change any of these settings, the Vendor box automatically displays the Custom option.

If you have selected the Custom option for Vendor, you can define new settings for the GND and VCC options under Signal Names and the LMF #1 and LMF #2 options under Library Mapping Files. You can also change any custom settings you had defined previously.

The current setting under Vendor is preserved when you compile a new project.


Customize

Expands the current dialog box to display all EDIF Netlist Writer options.


EDIF Version

EDIF 2 0 0 	Specifies that the EDIF Output File(s) should be generated in EDIF 2 0 0 format.

EDIF 3 0 0	Specifies that the EDIF Output File(s) should be generated in EDIF 3 0 0 format.


Signal Names

VCC 	Specifies the global high signal to be used in the project EDIF Output File(s). The default name is either VCC or the name typically used by the vendor name displayed in the Vendor box. Type a signal name with up to 20 name characters.

GND 	Specifies the global low signal to be used in a project’s EDIF Output File(s). The default name is either GND or the name typically used by the vendor name displayed in the Vendor box. Type a signal name with up to 20 name characters.


Map Illegal EDIF Characters

Maps the vertical bar (|), tilde (~), and colon (:) characters in MAX+PLUS II hierarchical node names to the legal EDIF characters z, x, and underscore (_), respectively, in EDIF Output Files.


Include Special Primitives

Includes the optional FILTER and RISEFALL primitives in the EDIF Output File(s) for the project.

If your simulation tool supports the RISEFALL primitive, you should turn Include Special Primitives on, especially in MAX 7000 projects. The RISEFALL primitive supports the non-turbo aspects of MAX 7000 devices. If your simulation tool does not support the RISEFALL primitive, you should turn Include Special Primitives off; however, without the RISEFALL primitive your simulation results may be inaccurate.


Force 0 ns Delays

Sets all delays in the EDIF Output File to zero ns. You should turn this option on if you want to use the EDIF Output File for functional simulation in a third-party environment.


EDIF Command File

Specifies an EDIF Command File for the Compiler to use in customizing EDIF Output File(s) for a particular third-party environment.

You can type a filename in the EDIF Command File box or select a name in the Files box to copy it to the EDIF Command File box. You can also type a text string that contains wildcard characters in the EDIF Command File box, then choose OK to update the contents of the Files box with the filenames that match the new text string.


Directories

Lists all available disk drives and all subdirectories of the current directory.

You can type a different absolute or relative pathname in the EDIF Command File box and choose OK or double-click Button 1 on a name in the Directories box to change the current directory.


Files; for opening/selecting files
Files

Lists all files in the current directory that match the text string in the EDIF Command File box.

Selecting a filename in the Files box copies it to the EDIF Command File box. You can also type a text string that includes wildcard characters in the EDIF Command File box, then choose OK to update the contents of the Files box with the filenames of the files that match the new text string.


Write Delay Constructs To

EDIF Output File (.vho)	Directs the Compiler to include delay constructs in the EDIF Output File.

SDF Output File (.sdo) Ver 2.1	Directs the Compiler to write delay constructs in a separate SDF Output File in SDF version 2.1 format.

SDF Output File (.sdo) Ver 1.0	Directs the Compiler to write delay constructs in a separate SDF Output File in SDF version 1.0 format.


Time Scale

Directs the Compiler to represent timing delays with the specified time units in each EDIF Output File. The value for the Time Scale option may be between 0.001 ns and 10ns, and should be a multiple of 10.


Verilog Netlist Writer Command (Compiler)
Verilog Netlist Writer Command (Interfaces Menu)

Turns the Verilog Netlist Writer module on or off and generates a Verilog Output File for use with any simulator that can read Verilog netlist files.

You can choose Verilog Netlist Writer Settings (Interfaces menu) to specify the configuration options the Verilog Netlist Writer uses to generate Verilog Output Files.

The filenames of the Verilog Output File(s) and optional SDF Output File(s) are the same as the user-defined chip name(s) for the project; if no chip names exist, the Compiler assigns filenames that are based on the project name. For a multi-device project, MAX+PLUS II also generates a top-level Verilog Output File that is uniquely identified by "_t" appended to the the project name. Example

The Compilation Settings & Times Section of the Report File records the processing time used by this module during compilation.

When the Verilog Netlist Writer is turned on, the Verilog Netlist Writer module box appears in the Compiler window.

See also:

Creating Verilog Output Files


Verilog Netlist Writer Settings Command (Compiler)
Verilog Netlist Writer Settings Command (Interfaces Menu)

Specifies Verilog conversion options for the Compiler to use in generating Verilog Output Files.

Click Button 1 on any item in this dialog box for information on that item:

The filenames of the Verilog Output File(s) and optional SDF Output File(s) are the same as the user-defined chip name(s) for the project; if no chip names exist, the Compiler assigns filenames that are based on the project name. For a multi-device project, MAX+PLUS II also generates a top-level Verilog Output File that is uniquely identified by "_t" appended to the the project name. Example

See also:

Creating Verilog Output Files


Write Delay Constructs To

Verilog Output File (.vo)	Directs the Compiler to include delay constructs in the Verilog Output File.

SDF Output File (.sdo) Ver 2.1	Directs the Compiler to write delay constructs in a separate SDF Output File in SDF version 2.1 format.

SDF Output File (.sdo) Ver 1.0	Directs the Compiler to write delay constructs in a separate SDF Output File in SDF version 1.0 format.


Time Scale

Directs the Compiler to represent timing delays with the specified time units in each Verilog Output File. The value for the Time Scale option may be between 0.001 ns and 10ns, and should be a multiple of 10.


VHDL Netlist Writer Settings Dialog Box (Compiler)
Verilog Netlist Writer Settings dialog box (Interfaces Menu)

Click Button 1 on any item in this dialog box for information on that item:


VHDL Netlist Reader Settings Command (Compiler)
VHDL Netlist Reader Settings Command (Interfaces Menu)

Specifies one or more custom user-defined VHDL design libraries for the current project.

VHDL Netlist Reader Settings allows you to specify the location of custom design libraries that are referenced in Library Clauses in the VHDL Design File(s) in your project. MAX+PLUS II automatically uses MAX+PLUS II Packages to compile VHDL-based projects.

If you wish to specify a custom design library that contains only packages, you must compile the file containing it before you can use it as a design library. For more information, see Compiling VHDL Design Files.

Click Button 1 on any item in this dialog box for information on that item:

See also:

Specifying a User Library


Library Name

Specifies the logical name of a user-defined VHDL design library.

Type the name of a design library in the Library Name box, using the same name that is given in the Library Clause in the VHDL Design File(s) in your project. To edit an existing library name, select it in the Existing Libraries box to display the library and corresponding directory names in the Library Name and Directory Name boxes.


Directory Name

Specifies the name of the directory that contains a user-defined VHDL design library.

You can type an absolute or relative pathname in the Directory Name box or select an existing directory name in the Directories box to copy it to the Directory Name box.


Existing Libraries

Lists all existing user-defined VHDL design libraries for the current project and their corresponding directories. During compilation, the Compiler searches for design libraries in these directories.


Add

Adds the user-defined VHDL design library name specfied in the Library Name and Directory Name boxes to the list of libraries in the Existing Libraries box.


Delete

Deletes the selected VHDL design library name from the Existing Libraries box.


VHDL Netlist Writer Command (Compiler)
VHDL Netlist Writer Command (Interfaces Menu)

Turns the VHDL Netlist Writer module on or off. When the VHDL Netlist Writer is on, it generates a VHDL Output Files that can be used with any simulator that can read VHDL netlist files.

You can choose VHDL Netlist Writer Settings (Interfaces menu) to specify the configuration options the VHDL Netlist Writer uses to generate VHDL Output Files.

The filenames of the VHDL Output File(s) and optional SDF Output File(s) are the same as the user-defined chip name(s) for the project; if no chip names exist, the Compiler assigns filenames that are based on the project name. For a multi-device project, MAX+PLUS II also generates a top-level VHDL Output File that is uniquely identified by "_t" appended to the the project name. Example

The Compilation Settings & Times Section records the processing time used by this module during compilation.

When VHDL Netlist Writer is turned on, the VHDL Netlist Writer module box appears in the Compiler window.

See also:

Creating VHDL Output Files


VHDL Netlist Writer Settings Command (Compiler)
VHDL Netlist Writer Settings Command (Interfaces Menu)

Specifies options for the Compiler to use in generating VHDL Output Files.

Click Button 1 on any item in this dialog box for information on that item:

The filenames of the VHDL Output File(s) and optional SDF Output File(s) are the same as the user-defined chip name(s) for the project; if no chip names exist, the Compiler assigns filenames that are based on the project name. For a multi-device project, MAX+PLUS II also generates a top-level VHDL Output File that is uniquely identified by "_t" appended to the the project name. Example

See also:

Creating VHDL Output Files


Write Delay Constructs To

VHDL Output File (.vho)	Directs the Compiler to include propagation delay constructs in the VHDL Output File(s).

SDF Output File (.sdo) Ver 2.1	Directs the Compiler to omit timing information from the VHDL Output File(s) and to instead write delay constructs in a separate SDF Output File in SDF version 2.1 format.

SDF Output File (.sdo) Ver 1.0	Directs the Compiler to omit timing information from the VHDL Output File(s) and to instead write delay constructs in a separate SDF Output File in SDF version 1.0 format.


Generate Configuration Declaration

Directs the Compiler to include a Configuration Declaration in each VHDL Output File.


VHDL Netlist Writer Settings Dialog Box (Compiler)
VHDL Netlist Writer Settings dialog box

Click Button 1 on any item in this dialog box for information on that item:


XNF Netlist Reader Settings Command (Compiler)
XNF Netlist Reader Settings Command (Interfaces Menu)

Specifies options for the Compiler Netlist Extractor to use in compiling Xilinx Netlist Format Files.

Before importing an XNF File into MAX+PLUS II, you must follow the guidelines in File Structure Requirements for XNF Files.

Click Button 1 on any item in this dialog box for information on that item:

See also:

Changing the File Type

Changing the Project Name

Compiling XNF Files


XNF Netlist Reader Settings Dialog Box (Compiler)
XNF Netlist Reader Settings dialog box

Click Button 1 on any item in this dialog box for information on that item:


Tri-State Bus Emulation

Use Internal Logic 	Emulates tri-state buses using internal multiplexer logic. Selecting this option reduces external pin usage, but can create complex logic that can cause fitting problems.

Use Device Pins 	Emulates tri-state buses using external device pins. Selecting this option simplifies logic, but can increase the use of pins that must be externally connected.


Translate Internal Node Names into N~<number> Format

Translates internal node names into MAX+PLUS II-compatible names of the format N~XXXX, where "XXXX" represents a 4-digit number (e.g., N~0001, N~0002). Pin names are always preserved.

If this option is turned off, MAX+PLUS II preserves original node names but truncates internal node names that are longer than 32 name characters. Any character in an XNF File node name that is not a legal name character in MAX+PLUS II is translated into a tilde (~).


Generate AHDL Text Design Export File (.tdx)

Generates Text Design Export Files that are equivalent to each XNF File used in the project. If this option is turned on, the Compiler attempts to generate a Text Design Export File, even if there are errors during compilation. However, some errors will prevent Text Design Export File generation.

You can rename a top-level Text Design Export File as a TDF and specify it as the top-level design file with Change File Type (File menu), and then compile the TDF instead of the XNF File. You can also rename the Text Design Export File generated for a lower-level XNF File and use Change File Type to replace all XNF Files in a project hierarchy with TDFs.


----BEGINNING OF NON-TRANSLATED TEXT-----

Bitmaps for Compiler

Logic Synthesis

Report File

Auto Device Selection

Device Options

Reserve Resources

EDIF Netlist Reader

EDIF Netlist Writer

Design Doctor	not in this file

MAX+PLUS II Compiler (for intro)

Combine Programming Files (File menu---to be added)

Override User Assignments (to be added) 7/31

FLEX 8000 Device Options (to be added)---fdevopts.bmp

----END OF NON-TRANSLATED TEXT-----


Compiler Window (intro)
Compiler Window


Compiler Window (1)
Compiler Window


Compiler Window (2)
Compiler Window


Compiler Window (3)
Compiler Window


Compiler Window (4)
Compiler Window


Partitioner/Fitter Status Dialog Box (Compiler)
Partitioner/Fitter Status Dialog Box

Displays the current status of partitioning and fitting, as well as the resources required for the project so that you can decide whether to continue or halt the compilation.

The Partitioner/Fitter Status dialog box appears if you choose the Stop/Show Status button during project compilation.

Click Button 1 on any item in this dialog box for information on that item:

See also:

Checking the Partitioner & Fitter Status During Compilation

Partitioning a Project


Chip

Lists the names of the chips in your project.


Device

Lists the devices to which chips are assigned.


Pins (required/available)

Lists the number of pins required for the chip assignment and the number of pins available.


Logic Cells (required/available)

Lists the number of logic cells required for the chip assignment and the number of logic cells available.


Status

Displays the fitting status of the chip.

Fits	The chip fits successfully in the assigned device.

Attempting to Fit	The Compiler’s Fitter module is currently trying to fit the chip.

Fitting Not Yet Attempted	The Fitter has not yet attempted to fit the chip.

Does Not Fit	The chip does not fit successfully in the assigned device. If the project is being partitioned among multiple devices, the Compiler attempts to fit the chip in another device.


Current Chip

Displays the name of the chip that the Fitter is currently processing.


Current Fitting Attempt

Displays the number of the latest fitting attempt for the current chip.


Stop Compilation

Stops the compilation. After you choose Stop Compilation, you can choose the Start button to recompile the project from the beginning. However, Compiler Netlist Extractor warning messages may not be redisplayed unless you turn on Total Recompile (Processing menu) before recompiling.


Continue Compilation

Continues project compilation.


Stop After This Attempt

Allows the Fitter to complete the current fitting attempt. If the fitting attempt is successful, the Compiler continues project compilation. If the fitting attempt is unsuccessful, the Compiler stops compiling the project and generates a Report File.


Stop & Create Report File

Directs the Fitter to stop the current fitting attempt and generates a Report File.


Current Compiler Action

Directs the Fitter to stop the current fitting attempt and generates a Report File.


Edit Pin Assignments & LCELLs Dialog Box (Compiler)
Edit Pin Assignments & LCELLs Dialog Box

Deactivates individual user-defined pin assignments and/or inserts or removes individual LCELL buffers (i.e., logic cells) during compilation.

You open the Edit Pin Assignments & LCELLs dialog box by choosing the Edit Pin Assignments & LCELLs button in the Override User Assignments dialog box dialog box that appears during compilation.

The Edit Pin Assignments & LCELLs dialog box allows you to selectively ignore one or more pin assignments. If you wish to retain a pin assignment, it allows you to insert an LCELL buffer that helps to separate the input or output from the project logic, thereby giving the Compiler more flexibility to achieve a fit with the existing pin assignment.

Click Button 1 on any item in this dialog box for information on that item:

Altera recommends that you either insert an LCELL buffer or ignore the pin assignment for each pin that is causing problems with fitting.

If you modify your resource assignments with the Override User Assignments and/or Edit Pin Assignments & LCELLs dialog boxes, the project’s design files are not automatically updated with the new assignments. To update them, you must back-annotate the assignments after compilation is completed.

Be sure to refer to Guidelines for Working with Assignments for absolutely essential information on using all types of resource, probe, and device assignments.

See also:

Adjusting the Fit During Compilation

Back-Annotating Assignments for a Project

Fitting & Refitting a Project


Edit Pin Assignments & LCELLs dialog box (Compiler)
Edit Pin Assignments & LCELLs dialog box

Click Button 1 on any item in this dialog box for information on that item:


Edit Pin Assignments & LCELLS list box

Insert LCELL	Shows whether a logic cell has already been allocated for the corresponding pin name listed under Pin Name. An x in the Insert LCELL column indicates that a logic cell is allocated for the pin. An x may appear in this column either if you have explicitly allocated a logic cell with this dialog box, or if you turned the Fitter Settings command (Processing menu) on before compiling the project.

To add a logic cell for the selected pin(s) without an x in this column, turn on the Insert LCELL checkbox option. To remove a logic cell for the selected pin(s) with an x in this column, turn off the Insert LCELL checkbox option.

Ignore Pin Assignment	Shows whether you have chosen to ignore the corresponding assignment listed under User Pin Assignment. An x in this column indicates that a user-defined pin assignment can be ignored.

To ignore pin assignment(s) for the selected pin(s) without an x in this column, turn on the Ignore Pin Assignment checkbox option. To use pin assignment(s) for the selected pin(s) with an x in this column, turn off Ignore Pin Assignment checkbox option.

User Pin Assignment	Shows the user-defined pin assignment for the corresponding Pin Name that was entered in a design file for the project.

I/O Type	Shows the I/O type of the corresponding pin name listed under Pin Name.

Pin Name	Shows the name of a pin that has a user-defined pin assignment in a design file for the project.

You can select a single line in this list box to edit pin assignments individually, or select multiple lines to edit multiple assignments at the same time.


Insert LCELL

Inserts or removes a logic cell for the selected pin(s) in the multi-column list box.

This option is available only if Ignore Pin Assignment is turned off.


Ignore Pin Assignment

Specifies whether the selected user pin assignment(s) should be retained or ignored.

This option is available only if Insert LCELL is turned off.


OK

Temporarily saves all pin and logic cell assignment changes, closes the dialog box, and returns you to the Override User Assignments dialog box. To permanently save all pin and logic cell assignment changes, choose OK in the Override User Assignments dialog box.


Cancel

Cancels all changes and returns you to the Override User Assignments dialog box.


Override User Assignments Dialog Box (Compiler)
Override User Assignments Dialog Box

Allows you to modify some of your user assignments to enable the Compiler to fit the project. If the Compiler is unable to fit a project, it displays a message that asks whether you wish to modify some of your assignments. If you choose No, the Compiler terminates compilation and generates a Report File. If you choose Yes, the Override User Assignments dialog box is displayed.

Click Button 1 on any item in this dialog box for information on that item:

After you choose OK, Compiler continues compilation and attempts to fit the project again with the changes you have specified. If the Compiler still cannot fit the project, it reissues the message that asks whether you wish to modify some of your assignments, and allows you to adjust the fit again to enter additional changes.

If you modify your resource assignments with the Override User Assignments dialog box, the project’s design files are not automatically updated with the new assignments. To update them, you must back-annotate the assignments after compilation is completed.

Be sure to refer to Guidelines for Working with Assignments for absolutely essential information on using all types of resource, probe, and device assignments.

See also:

Assigning a Clique

Assigning a Device

Assigning a Pin, Location, or Chip

Back-Annotating Assignments for a Project

Fitting & Refitting a Project

Partitioning a Project

Specifying Devices for Automatic Device Selection

Specifying Global Project Security Bit and Reserved Resource Settings


Override User Assignments Dialog Box (Compiler)
Override User Assignments dialog box

Click Button 1 on any item in this dialog box for information on that item:


Error Message

Shows an error message that describes why the Compiler can’t fit the project. You can choose Help On Message to display help on the likely cause(s) and suggested corrective action(s).


OK to Ignore

Cliques	Directs the Compiler to ignore all user-defined clique assignments.

Chips/Pins/Buried LCs	Directs the Compiler to ignore all user-defined chip, pin, and buried logic cellassignments.

All Pins/All Buried LCs	Directs the Compiler to ignore all user-defined pin and buried logic cell assignments.

Minimal Pins/All Buried LCs	Directs the Compiler to ignore as few user-defined pin assignments as possible and all buried logic cell assignments. (Available only for FLEX 8000 and FLEX 10K devices)

Buried LCs	Directs the Compiler to ignore all user-defined buried logic cell assignments.

Reserved Resources	Directs the Compiler to ignore the user-defined percentage of device pin and logic cell resources reserved with Global Project Device Options (Assign menu).


Help on Message

Displays information on the condition(s) that may have caused the message cause and suggested corrective action(s) in MAX+PLUS II Help.


Edit Pin Assignments & LCELLs

Opens the Edit Pin Assignments & LCELLs dialog box, which allows you to insert and remove individual LCELL buffers and to specify which individual pin assignments can be ignored during the remainder of the compilation.

This button is available only if you have not turned on the All Pins/All Buried LCs or Chips/Pins/Buried LCs option under OK to Ignore and if the current project uses FLEX 8000 or FLEX 10K devices.


Normal LCELL Insertion

Directs the Compiler to insert LCELL buffers automatically if they are needed to achieve a fit when user-defined pin assignments would otherwise prevent the project from fitting. Turning this option has the same effect as turning on the Normal Fitting (Auto Logic Cell Insertion Only) option in the Fitter Settings dialog box before starting the compilation.


Add Extra Devices as Needed

Directs the Compiler to add any additional devices needed to fit the project. This option is available only if you turned on the Ask Before Adding Extra Devices option in the Auto Device Selection dialog box before beginning the compilation. Otherwise, the Compiler automatically adds any devices required to fit the project.


Change to Auto Device Selection

Directs the Compiler to treat all chips that are assigned to specific devices as if they are assigned to AUTO.


AHDL Help Contents

The Altera Hardware Description Language (AHDL) is a high-level modular language for entering text-based designs. AHDL is described in the following sections:

Introduction	Introduces basic AHDL features.

How To Use AHDL	Describes how to develop a design in AHDL and offers suggestions for creating successful designs. Altera recommends that you read the topics in this section sequentially.

Elements	Describes the basic elements of a TDF. These elements are used in the behavioral statements described in Design Structure.

Design Structure	Describes all behavioral statements and sections used in AHDL.

Syntax	Describes the BNF syntax for all AHDL statements and sections.

Style Guide	Provides guidelines for formatting TDFs and VHDL Design Files to improve readability and avoid errors.

Golden Rules	Summarizes essential rules and guidelines that will help you use AHDL effectively.

See also:

Macrofunctions

Megafunctions (???link)

Primitives

Project Reliability Guidelines


AHDL Introduction
Introduction

The Altera Hardware Description Language (AHDL) is a high-level, modular language that is completely integrated into the MAX+PLUS II system. It is especially well suited for complex combinatorial logic, group operations, state machines, truth tables, and the creation of parameterized designs. You can use the MAX+PLUS II Text Editor or another text editor to create AHDL TDFs. You can then compile and simulate the TDFs and use them to program Altera devices. In addition, the MAX+PLUS II Compiler can generate AHDL Text Design Export Files and Text Design Output Files that can be saved as TDFs and re-used as design files.

How Does AHDL Work?

AHDL statements and elements are powerful, versatile, and easy to use. You can create entire hierarchical projects with AHDL, or mix AHDL TDFs with other types of design files in a hierarchical project. In addition, AHDL TDFs may be parameterized.

Although you can use any ASCII text editor to create AHDL designs, the MAX+PLUS II Text Editor allows you to take advantage of features available only in MAX+PLUS II while you enter, compile, and debug an AHDL design.

AHDL designs are easily incorporated into a design hierarchy. In the Text Editor, you can automatically create a symbol that represents a TDF and incorporate it into a GDF. Similarly, you can incorporate custom functions, and over 300 Altera-provided megafunctions and macrofunctions, including LPM functions, into any TDF. Altera provides Include Files for all functions shipped with MAX+PLUS II.

You can use Assign menu commands or an Assignment & Configuration File (.acf) to make resource and device assignments to allocate device resources for AHDL TDFs. You can also check AHDL syntax or perform a full compilation to debug and process your project. Any errors can be automatically located by the Message Processor and highlighted in the Text Editor window.

Where to Start

Altera offers a variety of information to help you create designs with AHDL.

On-Line Help

On-line help supplies complete reference and how-to information on using AHDL to create designs.

AHDL Help Contents provides access to all on-line AHDL Help.

AHDL Golden Rules summarizes essential rules and guidelines for designing with AHDL.

How To Use AHDL describes how to develop a design in AHDL and offers suggestions for creating successful designs. Altera recommends that you read the topics in this section sequentially.

Recommended Reading

Additional Altera publications help you understand MAX+PLUS II and AHDL. The following application notes and briefs are relevant to using AHDL:

AB9 (Asynchronous Latches in Classic, MAX & STG EPLDs)

AB60 (Estimating a Design Fit)

AB77 (Fitting Complex Designs in MAX 5000 EPLDs)

AB82 (Emulating Internal Buses in Classic, MAX & STG EPLDs)

AB86 (Designing & Simulating Bidirectional Buses with MAX+PLUS II Software)

AB88 (Optimizing Counter Design for Altera EPLDs)

AB92 (Simulating Internal Nodes with MAX+PLUS II Software)

AB93 (Partitioning a Project with MAX+PLUS II Software)

AB94 (Solutions to Design Timing Problems for Altera EPLDs)

AN22 (Designing with AHDL)

AN26 (EPLD/MPLD Design Guidelines)

Specific design applications that include AHDL are also available:

AB27 (EP1810 Classic EPLD as a Bar Code Decoder)

AB84 (DMA Controller with the EPM5064 MAX EPLD)

AB87 (Troubleshooting Functional Problems in EPLDs)

AB95 (Designing Phase-Locked Loops with Altera EPLDs)

AB97 (Integrating EDIF Files with AHDL Files in Hierarchical Projects)

AB99 (Design Flow between Workstations & PCs)

AB111 (Accumulators in FLEX 8000 Devices)

AB113 (Equality Comparators in FLEX 8000 Devices)

AB114 (Full Comparators in FLEX 8000 Devices)

AB118 (Ripple-Carry Adders in FLEX 8000 Devices)

AB126 (Subtractors in FLEX 8000 Devices)

AB131 (State Machine Encoding)

AB135 (Ripple-Carry Gray Code Counters in FLEX 8000 Devices)

AN16 (Integrating PAL, GAL & PLA Devices with the EPM5032 MAX EPLD)

AN17 (Integrating an Intelligent I/O Subsystem with a Single EPM5130 MAX EPLD)

AN20 (Fast Bus Controllers with the EPM5016 MAX EPLD)

AN21 (Designing a FIFO Controller with an EPM5064 MAX EPLD)

AN25 (Controlling Complex CCD Imaging Systems with the EPS464 STG EPLD)

AN27 (Implementing EISA Interfaces with MAX EPLDs)

AN29 (Cadence & MAX+PLUS II Logic Design)

AN30 (Viewlogic Workview PLUS & MAX+PLUS II Logic Design)

AN32 (Mentor Graphics & MAX+PLUS II Logic Design)

AN37 (Viewlogic Powerview & MAX+PLUS II Logic Design)

AN38 (Configuring Multiple FLEX 8000 Devices)

See also:

How to Use MAX+PLUS II Help

Text Editor Introduction


AHDL Golden Rules
Golden Rules

The following golden rules will help you use AHDL effectively:

Use the Text Editor’s Syntax Coloring command (Options menu) to help you identify typographical errors and different sections of AHDL code.

Follow the formatting and naming guidelines described in the AHDL & VHDL Style Guide to improve readability and avoid errors.

Although AHDL is not case-sensitive, Altera recommends that you follow the capitalization rules in the AHDL & VHDL Style Guide  to improve readability.

Use constants and evaluated functions, which are created in Constant and Define Statements, to improve readability and to avoid errors.

You do not need to create AHDL Function Prototypes for primitives. However, you can redefine primitives with a Function Prototype Statement to change the calling order of inputs in your TDF.

Do not use nested If Then Statements when a Case Statement  can be used instead.

When you use the MAX+PLUS II Text Editor to create a TDF, each line can be up to 255 characters long. However, the ideal line length is the number of characters your screen can accommodate. Press Enter to end a line.

You can start new lines wherever white space (i.e., blank lines, tabs, and spaces) is allowed, without any effect on meaning. White space is allowed between major AHDL constructs.

Keywords, names, and numbers must be separated by the appropriate symbols or operators, and one or more spaces.

Comments must be enclosed in percent symbols (%). A comment can include any character except %, since the MAX+PLUS II Compiler ignores everything between the percent symbols. Comments enclosed in percent symbols cannot be nested .

VHDL-style comments (- -) can be nested within %-style comments. If you use VHDL-style comments for documentation-type comments, you can use the %-style comments to exclude sections of code from compilation (i.e., "comment out" sections of code).

When connecting a primitive to another primitive, you must use only "legal" interconnections; not all primitives may connect to all other primitives. For a list of legal interconnections for primitives, see Primitive/Port Interconnections.

Do not create your own cross-coupled structures; use only the EXPDFF, EXPLATCH, INPLTCH, NANDLTCH, and NORLTCH macrofunctions provided with MAX+PLUS II. (These macrofunctions are not optimized for FLEX 8000 and FLEX 10K architectures.) Avoid tying multiple instances of EXPDFF, EXPLATCH, INPLTCH, NANDLTCH, and NORLTCH macrofunctions together. Multiple instances of these macrofunctions should always be separated by LCELL primitives.

General Design Entry Golden Rules

You should use Altera-provided primitives and AHDL logical operators rather than the equivalent LPM functions in most cases: they are much more convenient to instantiate. For example, if you wish to load a register on a specific rising edge of the global Clock, Altera recommends that you use the Clock Enable input of one of the DFFE, TFFE, JKFFE, or SRFFE Enable-type flipflops to control when the register is loaded.

Use LPM megafunctions (???link???) rather than equivalent old-style macrofunctions in most cases: the former are more convenient to instantiate and easier to modify if your design changes.

Use the  Design Doctor to check the reliability of your project logic during compilation. Follow Project Reliability Guidelines to create reliable projects.

Do not attempt to create your own logic functions to implement RAM or ROM: use Altera-provided megafunctions (???link) instead.

When you start a new design file, specify the target device family with Device right away, so that you can take advantage of family-specific macrofunctions. If you do not specify a device family, the family for the current project is assumed.

Use the Design Doctor to check the reliability of your project logic during compilation. Follow Project Reliability Guidelines to create reliable projects.

General MAX+PLUS II Golden Rules

When you start work on a new design file, name it as the current project with Project Set Project to Current File or Project Name (File menu)  right away so that you can compile it easily. You can always change the project name later.

Use the built-in hierarchy traversal features in MAX+PLUS II to move between design files for the current hierarchy tree. To open a lower-level file in a hierarchy, open the top-level file and then use the Hierarchy Display window or Hierarchy Down (File menu) to open the lower-level files. If you choose Open or Retrieve (File menu) to open a lower-level file, that file is considered to be the top of a different hierarchy tree, and resource, device, and probe assignments that you enter are saved only for that hierarchy, not for the project.

When you create an editable ancillary file for a project, the icon for the file will appear in the Hierarchy Display if you use the same filename as the project.

Don’t edit any MAX+PLUS II system files, including HIFs, TOK files, maxplus2.idx files, or the maxplus2.ini file.

Use the Save As command (File menu) if you wish to rename a design file or an ancillary file. Do not rename design files from outside of the MAX+PLUS II system (e.g., from DOS or with the Windows File Manager).

When you have completed a project, use Project Archive (File menu) to save a complete backup copy of all project files that will not be affected by future edits or deletions.


Context-Sensitive Help for AHDL Operators, Comparators, Keywords & Identifiers

The punctuation symbol (character) or keyword you clicked on is not part of AHDL. Context-sensitive help is available for the following types of AHDL keywords, identifiers and characters:

Arithmetic Operators in Boolean Expressions

Arithmetic Expressions

Comparators

Logical Operators

Macrofunctions

Megafunctions??????

Primitives

Reserved Identifiers

Reserved Keywords

Symbols

For information on other AHDL elements, see Elements. For information on Text Editor basic tools, see Text Editor Basic Tools.

See also:

Getting Context-Sensitive Help


AHDL & VHDL Style Guide

This style guide provides suggestions for formatting TDFs and VHDL Design Files to improve readability and thus avoid errors. These are recommendations only and are not required for your TDFs and VHDL Design Files to compile successfully. Examples that illustrate guidelines are provided.

You can use the Text Editor’s Syntax Coloring command (Options menu) to identify typographical errors and different sections of AHDL code. Go to Using Syntax Coloring in Text Files for more information.

Comments & Documentation

General Style Guidelines

Indentation Guidelines (AHDL)

Naming Conventions

White Space


Comments & Documentation (AHDL & VHDL)
Comments & Documentation

Describe the design at the beginning of the TDF or VHDL Design File with a substantial comment in natural language. Specifically, describe the ports and function of the design.

Use comments where appropriate to document the file. These comments should provide relevant information about the corresponding statement, and should be updated along with the file.

Do not duplicate a statement as a comment.

With Duplication:	Without Duplication:

IF clear THEN	IF clear THEN

% load q[] with 0 %	q[] = 0;

q[] = 0;	END IF;

END IF;

Place a comment either directly above the section it describes at the same indentation level, or aligned with other comments to the right of the lines of code.

Leave one blank space between documentation text and the percent symbol (%) for AHDL-style comments or two dashes (--) for VHDL-style comments. Align the opening and closing symbols for easy readability. (VHDL Design Files do not support AHDL-style comments.)

Unformatted:	Formatted:

%Leave one blank space between%   % Leave one blank space between %

%the percent symbol and the%      % the percent symbol and the    %

%documenting text. Line up%       % documenting text. Line up     %

%opening and closing percent%     % opening and closing percent   %

%symbols for easy readability.%   % symbols for easy readability. %

(AHDL only) VHDL-style comments can be nested within %-style comments. If you use VHDL-style comments (--) for documentation-type comments, you can then use the %-style comments to exclude sections of code from compilation (i.e., "comment out" sections of code).

See also:

General Style Guidelines

Indentation Guidelines (AHDL)

Naming Conventions

White Space


General Style Guidelines (AHDL & VHDL)
General Style Guidelines

All keywords, device names, constants, and primitives should be entered in capital letters; all other text should be lowercase, including filenames, megafunctions, and macrofunctions.

Unformatted:	Formatted:

case tap is	CASE tap IS

when test_logic_reset =>	WHEN test_logic_reset =>

if !tms then	IF !tms THEN

tap = run_test/idle;	tap = run_test/idle;

end if;	END IF;

when run_test/idle =>	WHEN run_test/idle =>

if tms then	IF tms THEN

tap = select_dr_scan;	tap = select_dr_scan;

end if;	END IF;

when select_dr_scan =>	WHEN select_dr_scan =>

if tms then	IF tms THEN

tap = select_ir_scan;	tap = select_ir_scan;

else	ELSE

tap = capture_dr;	tap = capture_dr;

end if;	END IF;

...	...

end case;	END CASE;

Either list all input and output ports on the same line, or enter : INPUT; (AHDL) or : IN (VHDL) after each line of inputs and : OUTPUT; (AHDL) or : OUT (VHDL) after each line of outputs. With this formatting style, all ports are clearly labeled.

Lines should not be longer than the width of the screen. If necessary, move part of a line to the next line and indent it. The Text Editor provides the Auto-Indent command (Options menu), and the Increase Indent and Decrease Indent commands (Edit menu), to help you indent text easily.

(AHDL only) Place opening and closing parentheses of the Subdesign Section and of Parameters Statements on a separate line to easily distinguish inputs and outputs. This formatting style also allows you to add and edit signal and parameter names easily.

Unformatted:	Formatted:

SUBDESIGN s (i1, i2, i3: INPUT;	SUBDESIGN s

o1, o2, o3: OUTPUT;)	(

BEGIN	i1, i2, i3 : INPUT;

...	o1, o2, o3 : OUTPUT;

END;	)

BEGIN

...

END;

(AHDL only) Do not use quoted symbolic names if you can use unquoted names.

Unformatted:	Formatted:

VARIABLE	VARIABLE

tap: MACHINE WITH STATES (	tap: MACHINE WITH STATES (

'Test-Logic-Reset',	test_logic_reset,

'Run-Test/Idle',	run_test_idle,

'Select-DR-Scan',	select_dr_scan,

'Capture-DR',	capture_dr,

'Shift-DR',	shift_dr,

'Exit1-DR',	exit1_dr,

'Pause-DR',	pause_dr,

'Exit2-DR',	exit2_dr,

'Update-DR',	update_dr,

'Select-IR-Scan',	select_ir_scan,

'Capture-IR',	capture_ir,

'Shift-IR',	shift_ir,

'Exit1-IR',	exit1_ir,

'Pause-IR',	pause_ir,

'Exit2-IR',	exit2_ir,

'Update-IR');	update_ir);

(AHDL only) Follow the indentation guidelines under Indentation Guidelines.

See also:

Comments & Documentation

Indenting Text

Naming Conventions

Quoted & Unquoted Names

White Space


Indentation Guidelines (AHDL)
Indentation Guidelines

This section illustrates recommended indentation of AHDL sections and statements.

Parameters Statement, Subdesign Section, and Logic Section Indentation:

PARAMETERS

(

   % parameter %

% parameter %

);

SUBDESIGN

(

% inputs  %

% outputs %

% bidirs  %

)

BEGIN

% statement %

% statement %

END;

If Then Statement Indentation:

IF expression1 THEN

% statement %

% statement %

ELSIF expression2 THEN

% statement %

% statement %

ELSE

% statement %

% statement %

END IF;

Use a similar style for If Generate and For Generate statements.

Case Statement Indentation:

CASE expression IS

WHEN constant1 =>

% statement %

% statement %

WHEN constant2 =>

% statement %

% statement %

WHEN constant3 =>

% statement %

% statement %

WHEN OTHERS =>

% statement %

% statement %

END CASE;

or:

CASE expression IS

WHEN constant1	=>	% statement %

WHEN constant2	=>	% statement %

WHEN constant3	=>	% statement %

WHEN OTHERS	=>	% statement %

END CASE;

Truth Table Statement Indentation:

TABLE

ss,	inputs[]	=>	outputs[],	ss;

s0,	B"xxxxx0"	=>	B"000001",	s1;

s1,	B"xxxx01"	=>	B"000011",	s2;

s2,	B"xxx011"	=>	B"000111",	s3;

s3,	B"xx0111"	=>	B"001111",	s4;

s4,	B"x01111"	=>	B"011111",	s5;

s5,	B"011111"	=>	B"111111",	s0;

END TABLE;

Variable Section & State Machine Declaration Indentation:

VARIABLE

ss: MACHINE WITH STATES (s0, s1, s2, s3);

tt: MACHINE

    OF BITS (q[3..0])

    WITH STATES (

 t0 = B"0001",

 t1 = B"0010",

 t2 = B"0100",

 t3 = B"1000");

Assert Statement Indentation:

ASSERT condition

   REPORT "message"

      % message variables %

   SEVERITY ERROR;

You can use the Text Editor's Auto-Indent command (Options menu), and Increase Indent and Decrease Indent commands (Edit menu), to help you indent text easily.

See also:

Comments & Documentation

General Style Guidelines

Indenting Text

Naming Conventions

White Space


Naming Conventions (AHDL & VHDL)
Naming Conventions

All symbolic names and identifiers should be meaningful and completely understandable, and should reflect the purpose or action of the function.

Ambiguous Name:	Unambiguous Name:

direction	up

access_mode	access_memory

Active-low signals should be specified with a clear and consistent notation. The notations shown below are supported in MAX+PLUS II design files. You should choose one notation and use it throughout a project.

/write  (not available in VHDL)

nchip_enable

resetn

Use underscores to separate "words" in symbolic and simple names.

Unformatted:	Formatted:

regload	reg_load

idleio	idle_io

goidle	go_idle

CSYNCPREEQJ	CSYNC_PRE_EQ_J

Do not use abbreviations unless they are obvious.

Ambiguous Name:	Unambiguous Name:

c	clk

clrg	clear_reg

sb	sync_bit

sm	select_mem

rdrm	refresh_dram

f	forward

r	reverse

(AHDL only) The Title Statement should include a short, descriptive name for the design.

TITLE "NTSC Waveform Generator";

Replace numbers with constants to provide meaningful names and a visual reference for all numbers. Only use 0 and 1 (AHDL) or '0' and '1' (VHDL) in the code.

CONSTANT TERMINAL_COUNT = 103;

See also:

Comments & Documentation

General Style Guidelines

Indentation Guidelines (AHDL)

White Space


White Space (AHDL & VHDL)
White Space

Use white space (blank lines, spaces, and tabs) around logical groups.

Do not place extra spaces before semicolons (;) commas (,), closing double quotation marks ("), or closing parentheses ()), or after opening double quotation marks (") or opening parentheses (().

Unformatted:	Formatted:

DFF ( d , clk , clrn , pren );	DFF(d, clk, clrn, prn);

Use tabs and spaces to align colons, truth table entries, etc.

Unformatted:	Formatted:

in1, clk : INPUT;	in1, clk	: INPUT;

out1, out2, out3 : OUTPUT;	out1, out2, out3 	: OUTPUT;

bus[8..1] : BIDIR	bus[8..1] 	: BIDIR

Leave a blank space before an opening parenthesis to separate it from a keyword.

Unformatted:	Formatted:

OF BITS(q[3..0])	OF BITS (q[3..0])

Place one blank space before and after operators and comparators (unless you are aligning signal names).

Unformatted:	Formatted:

enable = !a3&a2&a1&a0;	enable = !a3 & a2 & a1 & a0;

enable = (a[]==B"0111");	enable = (a[] == B"0111");

See also:

Comments & Documentation

General Style Guidelines

Indentation Guidelines (AHDL)

Naming Conventions


Recommended File Structure (AHDL)
Recommended File Structure

The following statements are listed in the order in which they appear in a TDF:

Title Statement

Include Statement

Parameters Statement

Constant Statement

Define Statement

Function Prototype Statement

Options Statement

Subdesign Section

Variable Section

-	Instance Declaration

-	Node Declaration

-	Register Declaration

-	State Machine Declaration

-	Machine Alias Declaration

-	If Generate Statement

Logic Section

-	Defaults Statement

-	Assert Statement

-	Boolean Equations

-	Boolean Control Equations

-	Case Statement

-	For Generate Statement

-	If Then Statement

-	If Generate Statement

-	In-Line Logic Function Reference

-	Truth Table Statement

AHDL is a concurrent language. All behavior specified in the Logic Section of a TDF is evaluated at the same time rather than sequentially. Equations that assign multiple values to the same AHDL node or variable are logically connected (ORed if the node or variable is active high, ANDed if it is active low).

A TDF must contain a Subdesign Section and a Logic Section. It can optionally contain a single Variable Section, Options Statement, Title Statement, and Defaults Statement; and one or more Include, Parameters, Constant, Define, and Function Prototype Statements.

The last entries in a TDF are the Subdesign Section, Variable Section (optional), and Logic Section, which together comprise the behavioral description of the TDF.

See also:

Inserting an AHDL Template (Text Editor)

Using Default Constant Values


Text Design File (.tdf) Description
Text Design File (.tdf)

An ASCII text with the extension .tdf) created with the MAX+PLUS II Text Editor or another standard text editor. The TDF contains design logic that is defined with AHDL.

A TDF can contain any combination of Boolean equations, truth tables, state machines, and group operations. TDFs can also be parameterized.

You can easily incorporate Altera-provided primitives and both Altera-provided and user-defined megafunctions and macrofunctions, including LPM functions, into a TDF. You can use a mega- or macrofunction by creating a Function Prototype and inserting an instance of the function into the TDF. You can also use this method to incorporate TDF logic in another TDF. Some Altera-provided primitives can also be expressed as logical operators in Boolean expressions. You can also automatically generate a default Include File that contains a Function Prototype for any design file with Create Default Include File (File menu).

A single TDF can be used to define all logic in a project, or can be incorporated at any hierarchy level in a hierarchical project. MAX+PLUS II automatically creates a Symbol File that represents any design file when you choose Create Default Symbol (File menu). This symbol and the logic it represents can be incorporated into a GDF.

You can create a super-project TDF containing instances that represent multiple individual sub-projects. In this type of TDF, the instances represent the SNFs for each individual sub-project, not the actual design file. You can compile the super-project to create a linked SNF that combines the timing and functional SNF information for each sub-project. This SNF allows you to perform a board-level-type simulation. For more information on super-project TDFs, refer to the guidelines in File Structure Requirements for Multi-Project Simulation.

In pre-version 5.0 releases of MAX+PLUS II, you could use AHDL statements to enter resource and device assignments. In MAX+PLUS II version 5.0 and higher, all assignment information is stored in the Assignment & Configuration File (.acf) for the project, which you can edit with Assign menu commands, the Floorplan Editor, or in a Text Editor window. Assignments in TDFs are automatically converted into the ACF format.

The MAX+PLUS II Compiler can also generate two output files in AHDL format. The XNF Netlist Reader optionally generates a Text Design Export File, and the Fitter optionally generates a Text Design Output File. These files can be saved as TDFs and used to replace the original design files with AHDL logic.

The file icon for each TDF that is part of the current hierarchy tree appears in the Hierarchy Display window.

See also:

AHDL Help Contents

Compiling XNF Files

Creating AHDL Text Design Output Files

Converting an Obsolete Assignment Format

Creating a Default Include File

Creating & Using Custom Macrofunctions (AHDL)

Creating the Default Symbol for a File

Text Design File Format

Using Altera MAX+PLUS II Unparameterized Macrofunctions (AHDL)

Creating & Using Parameterized Macrofunctions (AHDL) (???new title???link???)


Text Design File Format

The Text Design File is an ASCII text file (with the extension .tdf), created in AHDL. You can enter a TDF with the MAX+PLUS II Text Editor or any standard text editor.

AHDL is described in the following sections:

Introduction	Introduces basic AHDL features.

How To Use AHDL	Describes how to develop a design in AHDL and offers suggestions for creating successful designs. Altera recommends that you read the topics in this section sequentially.

Elements	Describes the basic elements of a TDF. These elements are used in the behavioral statements described in Design Structure.

Design Structure	Describes all behavioral statements and sections used in AHDL.

Syntax	Describes the BNF syntax for all AHDL statements and sections.

Style Guide	Provides guidelines for formatting TDFs and VHDL Design Files to improve readability and avoid errors.

Golden Rules	Summarizes essential rules and guidelines that will help you use AHDL effectively.

See also:

Macrofunctions

Megafunctions(??? link)

Primitives

Project Reliability Guidelines


Include File (.inc) Description
Include File (.inc)

An ASCII text file (with the extension .inc) that can be imported into a TDF with an AHDL Include Statement.

The contents of the Include File replace the Include Statement that calls the file. Include Files usually contain Function Prototype or Constant Statements.

Each Altera-provided megafunction and macrofunction has an Include File that contains its Function Prototype:

The Include Files for megafunctions are located in the \maxplus2\max2lib\mega_lpm directory created during installation.

The Include Files for macrofunctions are located in the \maxplus2\max2inc directory created during installation.

When you have a design file open in a Graphic, Text, or Waveform Editor window, you can choose Create Default Include File (File menu) to automatically generate an Include File that contains a default Function Prototype for the design file. You can also manually create an Include File with the MAX+PLUS II Text Editor or a standard text editor in non-document mode.

When you compile a project, the Compiler searches your computer’s directories for Include Files in the following order:

1.	The project directory.

2.	Any user libraries specified with User Libraries (Options menu).

3.	The \maxplus2\max2lib\mega_lpm and \maxplus2\max2inc directories created during installation.

If you change a TDF that includes an Include File, you can use Project Save & Check (File menu) or fully recompile the project to update the project’s hierarchy tree.

The file icon for an Include File with the same filename as the top-level design file in the current hierarchy tree appears in the Hierarchy Display window.

See also:

Creating a Default Include File

Creating & Using Custom Macrofunctions (AHDL)

Include Statement & Include File Rules

Using Altera MAX+PLUS II Unparameterized Macrofunctions (AHDL)

Creating & Using Parameterized Macrofunctions (AHDL) (???new title and ???link???)


AHDL Syntax
Syntax

Lexical Elements

Syntax Groups & Lists

Major AHDL Constructs

Title Statement

Constant Statement

Define Statement

Parameters Statement

Function Prototype Statement

Include Statement

Options Statement

Assert Statement

Subdesign Section

Variable Section

State Machine Declaration

Machine Alias Declaration

Logic Section

Boolean Equations

Boolean Control Equations

Case Statement

Defaults Statement

If Then Statement

If Generate Statement

For Generate Statement

In-Line Logic Function Reference

Truth Table Statements

Ports

Groups

See also:

Obsolete AHDL Statements


AHDL Lexical Elements BNF Syntax (AHDL)
Lexical Elements

The following lexical elements are used in AHDL:

<bit>

<comment>

<comment char>

<decimal number>

<design name>

<digit>

<filename>

<letter>

<name char>

<number>

<port name>

<quoted name char>

<radix>

<radix-tagged number>

<string>

<string char>

<symbolic name>

See also:

AHDL Syntax

Major AHDL Constructs


<radix> Syntax (AHDL)
<radix> Syntax

The AHDL lexical element <radix> has the following syntax:

<radix> ::= B | Q | H | O | X | b | q | h | o | x


<radix-tagged number> Syntax (AHDL)
<radix-tagged number> Syntax

The AHDL lexical element <radix-tagged number> has the following syntax:

<radix-tagged number> ::= <radix> " <bit> { <bit> }"


<bit> Syntax (AHDL)
<bit> Syntax

The AHDL lexical element <bit> has the following syntax:

<bit> ::= <letter> | <digit>


<comment char> Syntax (AHDL)
<comment char> Syntax

The AHDL lexical element <comment char> has the following syntax:

<comment char> ::= <any char except %>


<comment> Syntax (AHDL)
<comment> Syntax

The AHDL lexical element <comment> has the following syntax:

<comment> ::= %	{ <comment char> } %

| -- { <comment char> } <end of line>


<decimal number> Syntax (AHDL)
<decimal number> Syntax

The AHDL lexical element <decimal number> has the following syntax:

<decimal number> ::= <digit>:1:10


<design name> Syntax (AHDL)
<design name> Syntax

The AHDL lexical element <design name> has the following syntax:

<design name> ::= <filename>


<digit> Syntax (AHDL)
<digit> Syntax

The AHDL lexical element <digit> has the following syntax:

<digit> ::= 0 | 1 | ... | 9


<filename> Syntax (AHDL)
<filename> Syntax

The AHDL lexical element <filename> has the following syntax:

<filename> ::= (<name char>):1:32 | ' (<quoted name char>):1:32 '


<letter> Syntax (AHDL)
<letter> Syntax

The AHDL lexical element <letter> has the following syntax:

<letter> ::= A | ... | Z | a | ... | z


<name char> Syntax (AHDL)
<name char> Syntax

The AHDL lexical element <name char> has the following syntax:

<name char> ::= <letter> | <digit> | _


<number> Syntax (AHDL)
<number> Syntax

The AHDL lexical element <number> has the following syntax:

<number> ::= <decimal number> | <radix-tagged number>


<port name> Syntax (AHDL)
<port name> Syntax

The AHDL lexical element <port name> has the following syntax:

<port name> ::= (<name char> | /):1:32 | ' (<quoted name char> | /):1:32 '


<quoted name char> Syntax (AHDL)
<quoted name char> Syntax

The AHDL lexical element <quoted name char> has the following syntax:

<quoted name char> ::= <name char> | -


<string char> Syntax (AHDL)
<string char> Syntax

The AHDL lexical element <string char> has the following syntax:

<string char> ::= <any char except " and newline>


<string> Syntax (AHDL)
<string> Syntax

The AHDL lexical element <string> has the following syntax:

<string> ::= "{ <string char> }"


<identifier> Syntax (AHDL)
<identifier> Syntax

The AHDL lexical element <identifier> has the following syntax:

<identifier> ::= (<name char>):1:32


<symbolic name> Syntax (AHDL)
<symbolic name> Syntax

The AHDL lexical element <symbolic name> has the following syntax:

<symbolic name> ::= (<name char> | /):1:32 | ' (<quoted name char> | /):1:32 '

Unquoted symbolic names cannot consist only of numbers.


Major AHDL Constructs BNF Syntax (AHDL)
Major AHDL Constructs

<AHDL file>

<AHDL statement>

<statements>

<statement>

<title statement>

<constant def>

<evaluated function def>

<include statement>

<input list>

<options statement>

<output list>

<primitive>

<prototype>

<subdesign>

See also:

AHDL Lexical Elements

Boolean Equation Syntax

Case Statement Syntax

Defaults Statement Syntax

If Then Statement Syntax

Inserting an AHDL Template

Subdesign Section Syntax

Truth Table Statement Syntax


<AHDL file> Syntax (AHDL)
<AHDL file> Syntax

The AHDL construct <AHDL file> has the following BNF syntax:

<AHDL file> ::=

<AHDL statement>

{ <AHDL statement> }


<AHDL statement> Syntax (AHDL)
<AHDL statement> Syntax

The AHDL construct <AHDL statement> has the following BNF syntax:

<AHDL statement> ::=

<title>

|	<include statement>

|	<constant def>

|	<define statement>

|	<parameters???>

|	<prototype>

|	<options statement>

|	<subdesign section>


<statements> and <statement> Syntax (AHDL)
<statements> and <statement> Syntax

The AHDL constructs <statements> and <statement> have the following BNF syntax:

<statements> ::=

<statement>

{<statement>}

<statement> ::=

<boolean equation>

|	<case statement>

|	<defaults statement>

|	<if then statement>

|	<if generate statement>

|	<for generate statement>

|	<assert statement>

|	<table statement>


<prototype> Syntax (AHDL)
<prototype> Syntax

The AHDL construct <prototype> has the following BNF syntax:

<prototype> ::=

<unparameterized prototype> | <parameterized prototype>

<unparameterized prototype> ::=

FUNCTION <subdesign> ( <input list> )

{ WITH ( <parameter list> ) }  [ RETURNS ( <output list> ) ] ;

|	FUNCTION <primitive> ( <input list> )

{ WITH ( <parameter list> ) }

RETURNS ( <output list> );


<subdesign> Syntax (AHDL)
<subdesign> Syntax

The AHDL construct <subdesign> has the following BNF syntax:

<subdesign> ::=

<design name>


<primitive> Syntax (AHDL)
<primitive> Syntax

The AHDL construct <primitive> has the following BNF syntax:

<primitive> ::=

<symbolic name>


<input list> Syntax (AHDL)
<input list> Syntax

The AHDL construct <input list> has the following BNF syntax:

<input list> ::=

<prototype group> { , <prototype group> }


<output list> Syntax (AHDL)
<output list> Syntax

The AHDL construct <output list> has the following BNF syntax:

<input list> ::=

<prototype group> { , <prototype group> }


???Title???<parameter declaration> Syntax

The AHDL construct <parameter declaration> has the following BNF syntax:

<parameter declaration > ::=

<parameter> = <string> | <expression>


???Title???<parameter list> Syntax

The AHDL construct <parameter list> has the following BNF syntax:

<parameter list> ::=

<parameter> { , <parameter list> }


Title Statement BNF Syntax (AHDL)
Title Statement Syntax

The Title Statement has the following BNF syntax:

<title> ::=

TITLE <string>;

See also:

Inserting an AHDL Template


Include Statement BNF Syntax (AHDL)
Include Statement Syntax

The Include Statement has the following BNF syntax:

<include statement> ::=

INCLUDE <filename>;

1.	The Include File specified in the Include Statement must have the extension .inc and cannot contain a pathname.

2.	In the UNIX workstation environment, filenames are case-sensitive. Therefore, the case of the filename in an Include Statement must match the case of the Include File name.

See also:

Inserting an AHDL Template

Recommended File Structure


Constant Statement BNF Syntax (AHDL)
Constant Statement Syntax

The Constant Statement has the following BNF syntax:

<constant def> ::=

CONSTANT <symbolic name> = <expression>;

See also:

Inserting an AHDL Template

Using Constants & Evaluated Functions


Define Statement BNF Syntax (AHDL)
Define Statement Syntax

The Define Statement has the following BNF syntax:

<evaluated function def> ::=

DEFINE <symbolic name> ( <arguments list> ) =

<expression>;

<arguments list> ::=

<symbolic name> { , <symbolic name> }

See also:

Inserting an AHDL Template

Using Constants & Evaluated Functions


Assert Statement BNF Syntax (AHDL)
Parameters Statement Syntax

The Parameters Statement has the following BNF syntax:

<parameters statement> ::=

PARAMETERS ( <parameter list> );

<parameter list> ::=

<symbolic name> [ = <expression>> ]

{ , <symbolic name> [ = <expression> ] }

See also:

Inserting an AHDL Template

Parameters


Function Prototype Statement BNF Syntax (AHDL)
Function Prototype Statement Syntax

The Function Prototype Statement has the following BNF syntax:

<function prototype> ::=

<unparameterized prototype> | <parameterized prototype>

<unparameterized prototype> ::=

FUNCTION <subdesign> ( <input list> )

RETURNS ( <output list> );

|	FUNCTION <primitive> ( <input list> )

RETURNS ( <output list> );

<parameterized prototype> ::=

FUNCTION <subdesign> ( <input list> )

WITH ( <parameter list> )

RETURNS ( <output list> );

See also:

Importing & Exporting State Machines

Inserting an AHDL Template

Recommended File Structure


Options Statement BNF Syntax (AHDL)
Options Statement Syntax

The Options Statement has the following BNF syntax:

<options statement> ::=

OPTIONS BIT0 = (ANY | LSB | MSB)

See also:

Inserting an AHDL Template

Recommended File Structure


Assert Statement BNF Syntax (AHDL)
Assert Statement Syntax

The Assert Statement has the following BNF syntax:

<assert statement> ::=

ASSERT <assert expression>

REPORT <string> [ <message variable> {, <message variable>} ]

[ SEVERITY <severity> ]

[ HELP_ID <identifier> ] ;

<assert expression> ::=

<expression> | ( <expression> )

<message variable> ::=

<symbolic name>

<expression>

<severity> ::=

INFO | WARNING | ERROR

The HELP_ID and the <identifier> that follows is are reserved for interal Altera use. You cannot use HELP_ID in your own design files.


Subdesign Section BNF Syntax (AHDL)
Subdesign Section Syntax

The Subdesign Section has the following BNF syntax:

<subdesign section> ::=

SUBDESIGN <design name>

(

<signal list> ;

{ <signal list> ; }

)

<signal list> ::=

<port list> : <port type>

<port type> ::=

INPUT [ = VCC | = GND ]

|	OUTPUT

|	BIDIR [ = VCC | = GND ]

|	MACHINE INPUT

|	MACHINE OUTPUT

See also:

Importing & Exporting State Machines

Inserting an AHDL Template

Recommended File Structure


Variable Section BNF Syntax (AHDL)
Variable Section Syntax

The Variable Section has the following BNF syntax:

<variable section> ::=

VARIABLE

<port list> : <variable type> ;

{ <port list> : <variable type> ; }

<variable type> ::=

NODE

TRI_STATE_NODE

|	<subdesign>

|	<primitive>

|	<state machine>

|	<machine alias>

<state machine> ::=

MACHINE [ OF BITS <bits> ] WITH STATES ( <state> { , <state> } )

<state> ::=

<symbolic name> [ = <state value> ]

<state value> ::=

<number>

|	<symbolic name>

<machine alias> ::=

<symbolic name> : MACHINE;

1.	A machine alias declaration does not specify state bits or state names. This information is imported via the Subdesign Section through a MACHINE INPUT port from a file higher in the project hierarchy, or through a Function Prototype from a file lower in the project hierarchy.

2.	The Variable Section can also include If Generate Statements. See If Generate Statement Syntax.

See also:

Assigning State Machine Bits & Values

Implementing State Machines

Importing & Exporting State Machines

Inserting an AHDL Template

Recommended File Structure

Recovering from Illegal States

State Machines (AHDL)


Logic Section BNF Syntax (AHDL)
Logic Section Syntax

The Logic Section has the following BNF syntax

BEGIN

<statements>

END;

<statements> ::=

<statement>

{ <statement> }

<statement> ::=

<defaults statement>

|	<boolean equation>

|	<boolean control equation>

|	<case statement>

|	<if then statement>

|	<if generate statement>

|	<for generate statement>

|	<assert statement>

|	<truth table statement>

See also:

Inserting an AHDL Template

Recommended File Structure


Boolean Equation BNF Syntax (AHDL)
Boolean Equation Syntax

Boolean equations have the following BNF syntax:

<boolean equation> ::=

<group> = <rgroup>;

See also:

Boolean Expressions

Boolean Operator & Comparator Priorities

Comparators

Implementing Boolean Expressions & Equations

Inserting an AHDL Template

Logical Operators


Boolean Control Equation BNF Syntax (AHDL)
Boolean Control Equation Syntax

Boolean control equations have the following BNF syntax:

<symbolic name>.clk = <rgroup>;

[<symbolic name>.reset = <rgroup>;]

[<symbolic name>.ena = <rgroup>;]

The <symbolic name> in a Boolean control equation must be declared as in a State Machine Declaration in the Variable Section.

See also:

Implementing State Machines

Inserting an AHDL Template

Setting Clock, Reset & Enable Signals


Case Statement BNF Syntax (AHDL)
Case Statement Syntax

The Case Statement has the following BNF syntax:

<case statement> ::=

CASE <rgroup> IS

WHEN <choices> => <statements>

{ WHEN <choices> => <statements> }

[ WHEN OTHERS => <statements> ]

END CASE;

<choices> ::=

<constant group> { , <constant group> }

See also:

Inserting an AHDL Template

Recommended File Structure

Recovering from Illegal States


Defaults Statement BNF Syntax (AHDL)
Defaults Statement Syntax

The Defaults Statement has the following BNF syntax:

<defaults statement> ::=

DEFAULTS

<default def> ;

{ <default def> ; }

END DEFAULTS;

<default def> ::=

<group> = <constant group>

The Defaults Statement must be the first statement in the Logic Section.

See also:

Inserting an AHDL Template

Recommended File Structure

Recovering from Illegal States

Using Default Values for Variables


If Then Statement BNF Syntax (AHDL)
If Then Statement Syntax

The If Then Statement has the following BNF syntax:

<if then statement> ::=

IF <rgroup> THEN

<statements>

{ ELSIF <rgroup> THEN

<statements> }

[ ELSE <rgroup> THEN

<statements> ]

END IF;

See also:

Inserting an AHDL Template

Recommended File Structure


If Then Statement BNF Syntax (AHDL)
If Generate Statement Syntax

The If Generate Statement has the following BNF syntax:

<if generate statement> ::=

IF <expression> GENERATE

<statements>

{ ELSE

<statements> }

END GENERATE;

See also:

Inserting an AHDL Template

Recommended File Structure


???Title??? For Generate Statement Syntax

The For Generate Statement has the following BNF syntax:

<for generate statement> ::=

FOR (<name char>):1:32 IN <expression> TO <expression> GENERATE

<statements>

END GENERATE;

See also:

Inserting an AHDL Template

Recommended File Structure


In-Line Logic Function Reference BNF Syntax (AHDL)
In-Line Logic Function Reference Syntax

Within a Boolean equation, an in-line megafunction or macrofunction reference has the following BNF syntax:

need megafunction???need RETURNS clause???

<mega- or macrofunction> ( <rgroup list>) [ WITH ( <parameter list> ) ]

An in-line primitive reference within a Boolean equation has the following BNF syntax:

<primitive> ( <rgroup list> )

See also:

In-Line Logic Function Reference

Inserting an AHDL Template

Recommended File Structure

Using Altera MAX+PLUS II Unparameterized Macrofunctions

Variable Section Description

Variable Section Syntax


Truth Table Statement BNF Syntax (AHDL)
Truth Table Statement Syntax

The Truth Table Statement has the following BNF syntax:

<table statement> ::=

TABLE <inputs> => <outputs> ;

<input values> => <output values> ;

{ <input values> => <output values> ; }

END TABLE;

<inputs> ::=

<rgroup> { , <rgroup> }

<outputs> ::=

<lgroup> { , <lgroup> }

<input values> ::=

<constant group> { , <constant group> }

<output values> ::=

<constant group> { , <constant group> }

See also:

Assigning State Machine Bits & Values

Creating Decoders

Inserting an AHDL Template

Recommended File Structure

State Machines with Asynchronous Outputs

State Machines with Synchronous Outputs

Truth Table Statement Rules


Port Syntax (AHDL)
Port Syntax

A port that is an input or output of the current file is declared in the following format within the Subdesign Section:

<port name> : <port type> [ = <default port value> ]

<port type> ::=

INPUT

|	OUTPUT

|	BIDIR

|	MACHINE INPUT

|	MACHINE OUTPUT

<default port value> ::=

VCC

|	GND

Port names that are inputs and outputs of an instance of a primitive or macrofunction are used in the following format:

<instance name>.<port name>

<instance name> ::=

<symbolic name>

See also:

Ports


Group Syntax (AHDL)
Group Syntax

Groups can be declared with the following three notations:

1.	A <decimal group name> consists of a symbolic name followed by a range of decimal numbers enclosed in brackets, e.g., a[4..1]. Only one range is allowed after a symbolic name. Range delimiters can also consist of arithmetic expressions or constants declared in Constant Statements. The syntax of this notation is as follows:

<decimal group name> ::=

<symbolic name> [ <range>]

Once the group has been defined, [ ] is a shorthand way of specifying the entire range. Example

A single decimal number can also be used in place of a range, e.g., a[5]. However, this notation signifies a single symbolic name, not a group, and is equivalent to the name a5.

2.	A <sequential group name> consists of a list of symbolic names, ports, or numbers separated by commas and enclosed in parentheses, e.g., (a, b, c). Decimal group names can also be listed within the parentheses. Example

The syntax of this notation is as follows:

<sequential group name> ::= ( <rgroup list>)

<rgroup list> ::=

[ <rgroup>>] { , [ <rgroup> ] }

This notation is useful for specifying the the ports of an instance of a function that is declared in an Instance Declaration. Example

3.	A <dual-range group name> of the form a[j..k][l..m] consists of three parts: a symbolic name or port name, followed by  two ranges of integers enclosed in brackets, e.g., [j..k][l..m]. The symbolic  or port name, together with the longest number of digits in each range, cannot exceed  32 characters

The representation a[j..k][l..m] for j > k and l > m is equivalent to the sequential group representation (aj_[l..m], aj-1_[l..m],...ak_[l..m]). These representations are  also equivalent to (aj_l, aj_l-1, aj_l-2, ...aj_m, aj-1_l, aj-1_l-1, aj-1_l-2, ...aj-1_m,...ak_m). Example

The syntax of this notation is as follows:

<dual range group name> ::=

<symbolic name>[ <range>][ <range>] ??????

The dual-range group notation is useful for specifying groups of buses, and.designs having two-dimensional topologies.

See also:

Groups


Syntax Groups & Lists (AHDL)
Syntax Groups & Lists

<constant group>

<constant group list>

<dot group>

<dot group list>

<expression>

<lgroup>

<lgroup list>

<macrofunction>

<port group>

<port list>

<primitive>

<prototype group>

<range>

<range delimiter>

<rgroup>

<rgroup list>

See also:

AHDL Lexical Elements


<constant group> Syntax (AHDL)
<constant group> Syntax

<constant group> ::=

<symbolic name>

|	<number>

|	VCC

|	GND

|	( <constant group list> )


<constant group list> Syntax (AHDL)
<constant group list> Syntax

<constant group list> ::=

[ <constant group>] { , [ <constant group> ] }


<dot group list> and <dot group> Syntax (AHDL)
<dot group list> and <dot group> Syntax

<dot group list> ::=

[ <dot group> ] { , [ <dot group> ] }

<dot group> ::=

<port name>

|	<symbolic name> [ ]

|	<symbolic name> [ <range> ]

|	( <dot group list> )


<expression> Syntax (AHDL)
<expression> Syntax

<expression> ::=

<decimal number>

|	<symbolic name>

|	<radix-tagged number>

|	+<expression>

|	-<expression>

|	<expression> + <expression>

|	<expression> - <expression>

|	! <expression>

|	<expression> ^ <expression>

|	<expression> MOD <expression>

|	<expression> DIV <expression>

|	LOG2(<expression>)

|	CEIL(<expression>)

|	FLOOR(<expression>)

|	<expression> * <expression>

|	<symbolic name> ( <expression list> )???

|	<expression> # <expression>

|	<expression> OR <expression>

|	<expression> !# <expression>

|	<expression> NOR <expression>

|	<expression> & <expression>

|	<expression> AND <expression>

|	<expression> !& <expression>

|	<expression> NAND <expression>

|	<expression> $ <expression>

|	<expression> XOR <expression>

|	<expression> !$ <expression>

|	<expression> XNOR <expression>

|	<expression> == <expression>

|	<expression> != <expression>

|	<expression> >= <expression>

|	<expression> > <expression>

|	<expression> <= <expression>

|	<expression> < <expression>

|	<expression> ? <expression>


<lgroup> Syntax (AHDL)
<lgroup> Syntax

<lgroup> ::=

<lgroup> . <dot group>l

|	<symbolic name>

|	<symbolic name> [ ]

|	<symbolic name> [ <range> ]

|	! <lgroup>

|	( <lgroup list>)


<lgroup list> Syntax (AHDL)
<lgroup list> Syntax

<lgroup list> ::=

[ <lgroup>] { , [ <lgroup> ] }


<port group> Syntax (AHDL)
<port group> Syntax

<port group> ::=

<symbolic name>

|	<symbolic name> [ <range> ]


<port list> Syntax (AHDL)
<port list> Syntax

<port list> ::=

<port group> { , <port group> }


<prototype group> Syntax (AHDL)
<prototype group> Syntax

<prototype group> ::=

<port group>

|	MACHINE <symbolic name>


<range> Syntax (AHDL)
<range> Syntax

<range> ::=

<range delimiter>..<range delimiter>


<range delimiter> Syntax (AHDL)
<range delimiter> Syntax

<range delimiter> ::=

<expression>

|	<symbolic name>

|	<decimal number>


<rgroup> Syntax (AHDL)
<rgroup> Syntax

<rgroup> ::=

<rgroup> . <dot group>	|	<rgroup> # <rgroup>

|	! <rgroup>	|	<rgroup> !# <rgroup>

|	<number>	|	<rgroup> & <rgroup>

|	<symbolic name> 	|	<rgroup> !& <rgroup>

|	<symbolic name> [ ]	|	<rgroup> $ <rgroup>

|	<symbolic name> [ <range> ]	|	<rgroup> !$ <rgroup>

|	VCC	|	<rgroup> + <rgroup>

|	GND	|	<rgroup> - <rgroup>

|	<rgroup> == <rgroup>	|	- <rgroup>

|	<rgroup> >= <rgroup>	|	+ <rgroup>

|	<rgroup> > <rgroup>	|	<subdesign> ( <rgroup list> )

|	<rgroup> <= <rgroup>	|	<primitive> ( <rgroup list> )

|	<rgroup> < <rgroup>	|	( <rgroup list> )

|	<rgroup> != <rgroup>


<rgroup list> Syntax (AHDL)
<rgroup list> Syntax

<rgroup list> ::=

[ <rgroup> ] { , [ <rgroup> ] }


How to Use AHDL

Copying Examples from Help

Inserting an AHDL Template

Creating AHDL Text Design Output Files

Using Numbers

Using Constants & Evaluated Functions

Combinatorial Logic

Implementing Boolean Expressions & Equations

Declaring Nodes

Defining Groups

Implementing Conditional Logic

If Then Statement Logic

Case Statement Logic

If Then Statement vs. Case Statement

Creating Decoders

Using Default Values for Variables

Implementing Active-Low Logic

Implementing Bidirectional Pins

Implementing Tri-State Buses

Sequential Logic

Declaring Registers

Declaring Registered Outputs

Creating Counters

State Machines (AHDL)

Implementing State Machines

Setting Clock, Reset & Enable Signals

Assigning State Machine Bits & Values

State Machines with Synchronous Outputs

State Machines with Asynchronous Outputs

Recovering from Illegal States

Implementing a Hierarchical Project

Using Altera-Provided Unparameterized Functions

Using Altera-Provided Parameterized Functions

Using Custom Megafunctions & Macrofunctions

Importing & Exporting State Machines

Implementing LCELL & SOFT Primitives

Implementing RAM & ROM

Naming a Boolean Operator or Comparator

Using Iteratively Generated Logic

Using Conditionally Generated Logic

Using the Assert Statement


Using Numbers (AHDL)
Using Numbers

Numbers are used to specify constant values in Boolean expressions and equations, arithmetic expressions, and parameter values. AHDL supports all combinations of decimal, binary, octal, and hexadecimal numbers.

The decode1.tdf file shown below is an address decoder that generates an active-high chip enable when the address is 370 Hex.

SUBDESIGN decode1

(

   address[15..0] : INPUT;

   chip_enable    : OUTPUT;

)

BEGIN

   chip_enable = (address[15..0] == H"0370");

END;

In this sample file, the decimal numbers 15 and 0 are used to specify bits of the address bus. The hexadecimal number H"0370" specifies the address that is decoded.

See also:

Numbers in AHDL

Parameters Statement

Using Constants & Evaluated Functions


Using Constants & Evaluated Functions (AHDL)
Using Constants & Evaluated Functions

You can use a constant in an AHDL file to give a descriptive name to a number or text string. Similarly, you can use an evaluated function to give a descriptive name to an arithmetic expression. This name, which can be used throughout a file, can be more informative and readable than the number, string, or arithmetic expression. For example, the numeric constant UPPER_LIMIT is more informative than the number 130.

Constants and evaluated functions are especially useful if the same number, text string, or arithmetic expression is repeated several times in a file: if it changes, only the Constant or Define Statement needs to be changed. In AHDL, constants are implemented with Constant Statements, and evaluated functions are implemented with Define Statements.

The decode2.tdf file shown below has the same functionality as decode1.tdf (shown in Using Numbers), but uses the constant IO_ADDRESS instead of the number H"0370".

CONSTANT IO_ADDRESS = H"0370";

SUBDESIGN decode2

(

   a[15..0] : INPUT;

   ce       : OUTPUT;

)

BEGIN

   ce = (a[15..0] == IO_ADDRESS);

END;

You can define constants and evaluated functions with arithmetic expressions. Constants and evaluated functions can also be defined with previously defined constants, evaluated functions, or parameters. Examples

The Compiler evaluates arithmetic operators in arithmetic expressions and reduces them to numerical values. No logic is generated for these expressions.

The strcmp.tdf file shown below defines the constant FAMILY and uses it in an Assert Statement to check whether the current device family is FLEX 8000.

PARAMETERS

(

DEVICE_FAMILY     % DEVICE_FAMILY is a predefined Altera parameter %

);

CONSTANT FAMILY = "FLEX8000";

SUBDESIGN strcmp

(

   a : INPUT;

   b : OUTPUT;

)

BEGIN

   IF (DEVICE_FAMILY == FAMILY) GENERATE

      ASSERT

         REPORT "Detected compilation for FLEX8000 family"

         SEVERITY INFO;

      b = a;

   ELSE GENERATE

      ASSERT

         REPORT "Detected compilation for % family"

            DEVICE_FAMILY

         SEVERITY ERROR;

      b = a;

   END GENERATE;

END;

The minport.tdf file shown below defines the evaluated function MAX, which ensures a minimum port width in the Subdesign Section:

PARAMETERS (WIDTH);

DEFINE MAX(a,b) = (a > b) ? a : b;

SUBDESIGN minport

(

   dataA[MAX(WIDTH,0)..0] : INPUT;

   dataB[MAX(WIDTH,0)..0] : OUTPUT;

)

BEGIN

   dataB[] = dataA[];

END;

See also:

Quoted & Unquoted Names

Using Default Values for Variables

Using Numbers


Constants defined with arithmetic expressions and previously defined constants
In the following example, the constant foo is defined with an arithmetic expression and the constant foo_plus_one is defined with the previously defined constant foo:

CONSTANT foo = 1 + 2 DIV 3 + LOG2(256);

CONSTANT foo_plus_one = foo + 1;

In the following example, the evaluated function CEILING_ADD is defined on the basis of the previously defined evaluated function MAX:

DEFINE MAX(a,b) = (a > b) ? a : b;

DEFINE CEILING_ADD(a,b) = MAX(a,b) + 1;


Combinatorial Logic (AHDL)
Combinatorial Logic

Logic is combinatorial if outputs at a specified time are a function only of the inputs at that time. Combinatorial logic is implemented in AHDL with Boolean expressions and equations, truth tables, and a variety of megafunctions and macrofunctions. Examples of combinatorial logic functions include decoders, multiplexers, and adders.

Information on combinatorial logic is available in the following topics:

Implementing Boolean Expressions & Equations

Declaring Nodes

Defining Groups

Implementing Conditional Logic

-	If Then Statement Logic

-	Case Statement Logic

-	If Then Statement vs. Case Statement

Creating Decoders

Using Default Values for Variables

Implementing Active-Low Logic

Implementing Bidirectional Pins

Implementing Tri-State Buses

See also:

Sequential Logic

Using Conditionally Generated Logic

Using Iteratively Generated Logic


Implementing Boolean Expressions & Equations (AHDL)
Implementing Boolean Expressions & Equations

Boolean expressions are sets of nodes, numbers, constants, and other Boolean expressions, separated by operators and/or comparators, and optionally grouped with parentheses. A Boolean equation sets a node or group equal to the value of a Boolean expression.

The boole1.tdf file shown below shows two simple Boolean expressions that represent two logic gates.

SUBDESIGN boole1

(

   a0, a1, b  : INPUT;

   out1, out2 : OUTPUT;

)

BEGIN

   out1 = a1 & !a0;

   out2 = out1 # b;

END;

In this sample file, the out1 output is driven by the logical AND of a1 and the inverse of a0, and the out2 output is driven by the logical OR of out1 and b. Since these equations are evaluated concurrently, their order in the file is not important.

See also:

Boolean Equations

Boolean Expressions

Declaring Nodes

Defining Groups


Declaring Nodes (AHDL)
Declaring Nodes

A node, which is declared with a Node Declaration in the Variable Section, can be used to hold the value of an intermediate expression.

Node Declarations are especially useful when a Boolean expression is used repeatedly. The Boolean expression can be replaced with a descriptive node name, which is easier to read.

The boole2.tdf file shown below contains the same logic as boole1.tdf (shown in Implementing Boolean Expressions & Equations), but has only one output.

SUBDESIGN boole2

(

   a0, a1, b   : INPUT;

   out         : OUTPUT;

)

VARIABLE

   a_equals_2  : NODE;

BEGIN

   a_equals_2 = a1 & !a0;

   out = a_equals_2 # b;

END;

This file declares the node a_equals_2 and assigns the value of the expression a1 & !a0 to it. Using nodes can save device resources when the node is used in several expressions.

Both ordinary nodes (NODE keyword) and tri-state nodes (TRI_STATE_NODE keyword) can be used. NODE and TRI_STATE_NODE differ in that multiple assignments to them yield different results:

Multiple assignments to nodes of type NODE tie the signals together by wired-AND or wired-OR functions. The default values for variables declared in Defaults Statements determine the behavior: a VCC default produces a wired-AND function; a GND default produces a wired-OR function.

Multiple assignments to a TRI_STATE_NODE tie the signals to the same node.

If only one variable is assigned to a TRI_STATE_NODE, it is treated as NODE.

See also:

Defining Groups

Implementing Tri-State Buses


Defining Groups (AHDL)
Defining Groups

A group, which can include up to 256 members (or "bits"), is treated as a collection of nodes and acted upon as one unit. A group name can be specified with a single-range group name, dual-range group name, or sequential group name format.

In Boolean equations, a group can be set equal to a Boolean expression, another group, a single node, VCC, GND, 1, or 0. In each case, the value of the group is different. The Options Statement can be used to specify whether the lowest numbered bit of the group will be the MSB, the LSB, or either.

Once a group has been defined, [] is a shorthand way of specifying an entire range. For example, a[4..1] can also be denoted by a[]; similarly, b[5..4][3..2] can be represented by b[][].

The group1.tdf file shows simple Boolean expressions that define multiple groups.

OPTIONS BIT0 = MSB;

CONSTANT MAX_WIDTH = 1+2+3-3-1;  % MAX_WIDTH = 2 %

SUBDESIGN group1

(

   a[1..2], use_exp_in[1+2-2..MAX_WIDTH]    : INPUT;

   d[1..2], use_exp_out[1+2*2-4..MAX_WIDTH] : OUTPUT;

   dual_range[5..4][3..2]                   : OUTPUT;

)

BEGIN

   d[] = a[] + B"10";

   use_exp_out[] = use_exp_in[];

   dual_range[][] = VCC;

END;

In this example, the Options Statement is used to specify that the rightmost bit of each group will be the MSB, and a 1 (decimal) is added to group a[]. If 00 is applied to input a[], then the result of this sample program will be d[] == 1 (decimal). The groups use_exp_in[] and use_exp_out[] show how constants and arithmetic expressions can be used to delimit group ranges.

The following examples show legal groups:

When a group is set equal to another group of the same size, each member on the right is assigned to the member on the left that corresponds in position. Example

When a group is set equal to a single node, all bits of the group are connected to the node. Example

When a group is set equal to VCC or GND, all bits of the group are connected to that value. Example

When a group is set equal to 1 (decimal), only the LSB of the group is connected to the value VCC. All other bits in the group are connected to GND. Example

When a group is set equal to another group of a different size, the number of bits in the group on the left side of the equation must be evenly divisible by the number of bits in the group on the right side of the equation. The bits on the left side of the equation are mapped to the right side of the equation, in order. Example

See also:

Arithmetic Expressions

Boolean Equation Rules

Declaring Nodes

Groups

Implementing Boolean Expressions & Equations

Using Default Values for Variables


Example: Defining Groups 1
In the following example, each bit in the first group is connected to the corresponding bit in the second group. Bit d2 is connected to bit q8, d1 to q7, and d0 to q6:

d[2..0] = q[8..6]

In the following example, each bit in the first group is connected to the corresponding bit in the second group. Bit d1_1 is connected to bit q10, bit d1_0 to q9, bit d0_1 to q8, and bit d0_0 to q7:

d[1..0][1..0] = q[10..7]


Example: Defining Groups 2
In the following example, d2, d1, and d0 are all connected to n:

d[2..0] = n


Example: Defining Groups 3
In the following example, d2, d1, and d0 are all connected to VCC:

d[2..0] = VCC


Example: Defining Groups 4
In the following example, only d0 is connected to VCC; the value 1 (decimal) is sign-extended to B"001".

d[2..0] = 1


Implementing Conditional Logic (AHDL)
Implementing Conditional Logic

Conditional logic chooses among different behaviors depending on the values of the logic inputs. If Then and Case Statements are ideal for implementing conditional logic:

If Then Statements evaluate one or more Boolean expressions, then describe the behavior for different values of the expressions.

Case Statements list alternatives that are available for each value of an expression. They evaluate the expression, then select a course of action on the basis of the value of the expression.

Information on conditional logic is available in the following topics:

If Then Statement Logic

Case Statement Logic

If Then Statement vs. Case Statement

Conditional logic implemented with If Then and Case Statements should not be confused with logic that is generated conditionally in an If Generate Statement. Logic that is generated conditionally is not necessarily conditional logic.

See also:

Declaring Nodes

Defining Groups

Implementing Boolean Expressions & Equations

Using Conditionally Generated Logic

Using Iteratively Generated Logic


If Then Statement Logic (AHDL)
If Then Statement Logic

The priority.tdf file shown below shows a priority encoder that converts the level of the highest-priority active input into a value. It generates a 2-bit code that indicates the highest-priority input driven by VCC.

SUBDESIGN priority

(

   low, middle, high   : INPUT;

   highest_level[1..0] : OUTPUT;

)

BEGIN

   IF high THEN

      highest_level[] = 3;

   ELSIF middle THEN

      highest_level[] = 2;

   ELSIF low THEN

      highest_level[] = 1;

   ELSE

      highest_level[] = 0;

   END IF;

END;

In this example, the inputs high, middle, and low are evaluated to determine whether they are driven by VCC. The If Then Statement activates the equations that follow the active IF or ELSE clause, e.g., if high is driven by VCC, highest_level[] is 3.

If more than one input is driven by VCC, the If Then Statement evaluates the priority of the inputs, which is determined by the order of the IF and ELSIF clauses (the first clause has the highest priority). In priority.tdf, high has the highest priority, middle has the next highest priority, and low has the lowest priority. The If Then Statement activates the equations that follow the highest-priority IF or ELSE clause that is true.

If none of the inputs are driven by VCC, the equations following the ELSE keyword are activated.

See also:

Case Statement

Case Statement Logic

Declaring Nodes

Defining Groups

If Then Statement vs. Case Statement

Implementing Boolean Expressions & Equations


Case Statement Logic (AHDL)
Case Statement Logic

The decoder.tdf file shown below is a 2-bit-to-4-bit decoder. It converts two binary code inputs into a "one-hot" code.

SUBDESIGN decoder

(

code[1..0]	: INPUT;

out[3..0]	: OUTPUT;

)

BEGIN

CASE code[] IS

WHEN 0 => out[] = B"0001";

WHEN 1 => out[] = B"0010";

WHEN 2 => out[] = B"0100";

WHEN 3 => out[] = B"1000";

END CASE;

END;

In this example, the input group code[1..0] has the value 0, 1, 2, or 3. The equation following the appropriate => symbol in the Case Statement is activated. For example, if code[] is 1, out1 is set to B"0010". Since the values of the expression are all different, only one WHEN clause can be active at one time.

See also:

Creating Decoders

Declaring Nodes

Defining Groups

If Then Statement

If Then Statement Logic

If Then Statement vs. Case Statement

Implementing Boolean Expressions & Equations


If Then Statement vs. Case Statement (AHDL)
If Then Statement vs. Case Statement

If Then and Case Statements are similar. In some cases, you can use either statement to achieve the same results. The following example shows the same operation expressed in both If Then and Case Statement formats:

If Then Statement:	Case Statement:

CASE a[] IS

IF a[] == 0 THEN	WHEN 0 =>

y = c & d;	y = c & d;

ELSIF a[] == 1 THEN	WHEN 1 =>

y = e & f;	y = e & f;

ELSIF a[] == 2 THEN	WHEN 2 =>

y = g & h;	y = g & h;

ELSIF a[] == 3 THEN	WHEN 3 =>

y = i;	y = i;

ELSE 	WHEN OTHERS =>

y = GND;	y = GND;

END IF;	END CASE;

Important differences exist between If Then and Case Statements:

Any kind of Boolean expression can be used in an If Then Statement. Each expression following an IF or ELSIF clause may be unrelated to the other expressions in the statement. In a Case Statement, however, a single Boolean expression is compared to a constant in each WHEN clause.

Using the ELSIF clause can result in logic that is too complex for the MAX+PLUS II Compiler, because each successive ELSIF clause must still test that the preceding IF/ELSIF clauses are false. The following example shows how the Compiler interprets an If Then Statement. If a and b are complex expressions, then the inversion of each expression is likely to be even more complex.

If Then Statement:	Compiler Interpretation:

IF a THEN	IF a THEN

c = d;	c = d;

END IF;

ELSIF b THEN	IF !a & b THEN

c = e;	c = e;

END IF;

ELSE 	IF !a & !b THEN

c = f;	c = f;

END IF;	END IF;

See also:

Case Statement Logic

Declaring Nodes

Defining Groups

If Then Statement Logic

Implementing Boolean Expressions & Equations


Creating Decoders (AHDL)
Creating Decoders

A decoder contains combinatorial logic that interprets input patterns and converts them to output values. In AHDL, you can use a Truth Table Statement or the lpm_compare or lpm_decode functions to create a decoder.

The 7segment.tdf file shown below is a decoder that specifies logic for patterns of light-emitting diodes (LEDs). The LEDs are illuminated in a seven-segment display to show the hexadecimal numbers 0 to 9 and the letters A to F.

%   -a-                            %

% f|   |b                          %

%   -g-                            %

% e|   |c                          %

%   -d-                            %

%                                  %

% 0 1 2 3 4 5 6 7 8 9 A b C d E F  %

%                                  %

SUBDESIGN 7segment

(

   i[3..0]             : INPUT;

   a, b, c, d, e, f, g : OUTPUT;

)

BEGIN

   TABLE

      i[3..0] => a, b, c, d, e, f, g;

      H"0"    => 1, 1, 1, 1, 1, 1, 0;

      H"1"    => 0, 1, 1, 0, 0, 0, 0;

      H"2"    => 1, 1, 0, 1, 1, 0, 1;

      H"3"    => 1, 1, 1, 1, 0, 0, 1;

      H"4"    => 0, 1, 1, 0, 0, 1, 1;

      H"5"    => 1, 0, 1, 1, 0, 1, 1;

      H"6"    => 1, 0, 1, 1, 1, 1, 1;

      H"7"    => 1, 1, 1, 0, 0, 0, 0;

      H"8"    => 1, 1, 1, 1, 1, 1, 1;

      H"9"    => 1, 1, 1, 1, 0, 1, 1;

      H"A"    => 1, 1, 1, 0, 1, 1, 1;

      H"B"    => 0, 0, 1, 1, 1, 1, 1;

      H"C"    => 1, 0, 0, 1, 1, 1, 0;

      H"D"    => 0, 1, 1, 1, 1, 0, 1;

      H"E"    => 1, 0, 0, 1, 1, 1, 1;

      H"F"    => 1, 0, 0, 0, 1, 1, 1;

   END TABLE;

END;

In this example, the output pattern for all 16 possible input patterns of i[3..0] is described in the Truth Table Statement.

The decode3.tdf file shown below is an address decoder for a generalized 16-bit microprocessor system.

SUBDESIGN decode3

(

   addr[15..0], m/io         : INPUT;

   rom, ram, print, sp[2..1] : OUTPUT;

)

BEGIN

   TABLE

      m/io, addr[15..0]           => rom, ram,   print, sp[];

      1,    B"00XXXXXXXXXXXXXX"   => 1,   0,     0,     B"00";

      1,    B"100XXXXXXXXXXXXX"   => 0,   1,     0,     B"00";

      0,    B"0000001010101110"   => 0,   0,     1,     B"00";

      0,    B"0000001011011110"   => 0,   0,     0,     B"01";

      0,    B"0000001101110000"   => 0,   0,     0,     B"10";

   END TABLE;

END;

In this example, thousands of possible input patterns exist, so it is impractical to specify all of them in the Truth Table Statement. Instead, you can use an X (don’t care) logic level to indicate that the output does not depend on the input corresponding to the position of the X characters. For example, in the first line of the TABLE statement, rom would be high for all 16,384 input patterns of addr[15..0] that start with 00. Therefore, you only need to specify the common portion of the input pattern (i.e., 00), then use X characters for the rest of the input pattern. With don’t care inputs, your project may require fewer device resources.

When you use X (don’t care) characters to specify a bit pattern, you must ensure that the pattern cannot assume the value of another bit pattern in the truth table. AHDL assumes that only one condition in a truth table is true at a time; therefore, overlapping bit patterns may cause unpredictable results.

The decode4.tdf file shown below uses the lpm_decode function to achieve the same functionality as decode1.tdf (described in Using Numbers).

INCLUDE "lpm_decode.inc";

SUBDESIGN decode4

(

   address[15..0]   : INPUT;

   chip_enable      : OUTPUT;

)

BEGIN

   chip_enable = lpm_decode(.data[]=address[])

      WITH (LPM_WIDTH=16, LPM_DECODES=2^10)

      RETURNS (.eq[H"0370"]);

END;

See also:

Implementing Conditional Logic


Using Default Values for Variables (AHDL)
Using Default Values for Variables

You can define a default value for a node or group that is used when the value of the node or group is not specified elsewhere in the file. AHDL also allows you to assign the value of a node or group more than once in a single file. If these multiple assignments conflict, the default value is used to resolve the conflict. When no defaults are specified, the default value is GND.

You can use the AHDL Defaults Statement to specify default values for variables used in Truth Table, If Then, and Case Statements. For example, since the Logic Synthesizer automatically connects all AHDL truth table outputs to GND when no truth table input conditions are satisfied, you can use one or more Defaults Statements to drive truth table outputs to VCC instead.

You should not confuse default values for variables with default values for ports that are assigned in the Subdesign Section.

The default1.tdf file shown below evaluates inputs and chooses one of five ASCII codes based on the inputs.

SUBDESIGN default1

(

   i[3..0]          : INPUT;

   ascii_code[7..0] : OUTPUT;

)

BEGIN

   DEFAULTS

      ascii_code[] = B"00111111"; % ASCII question mark "?" %

   END DEFAULTS;

   TABLE

      i[3..0] => ascii_code[];

      B"1000" => B"01100001"; % "a" %

      B"0100" => B"01100010"; % "b" %

      B"0010" => B"01100011"; % "c" %

      B"0001" => B"01100100"; % "d" %

   END TABLE;

END;

When an input pattern matches one of the patterns shown on the left side of the Truth Table Statement, the table’s outputs are set to the corresponding pattern on the right. If the input pattern does not match any pattern on the left side, the outputs default to B"00111111", i.e., nodes ascii_code[5..0] are driven to VCC while nodes ascii_code[7..6] are connected to GND.

The default2.tdf file shown below illustrates how conflicts arise when a single node is assigned more than one value, and how these conflicts are resolved by AHDL.

SUBDESIGN default2

(

   a, b, c                      : INPUT;

   select_a, select_b, select_c : INPUT;

   wire_or, wire_and            : OUTPUT;

)

BEGIN

   DEFAULTS

      wire_or = GND;

      wire_and = VCC;

   END DEFAULTS;

   IF select_a THEN

      wire_or = a;

      wire_and = a;

   END IF;

   IF select_b THEN

      wire_or = b;

      wire_and = b;

   END IF;

   IF select_c THEN

      wire_or = c;

      wire_and = c;

   END IF;

END;

In this example, wire_or is set to the values of a, b, or c, depending on the values of the select_a, select_b, and select_c signals. If none of these signals is VCC, then wire_or defaults to GND.

If more than one of the select_a, select_b, or select_c signals are VCC, wire_or is set to the logical OR of the corresponding input values. For example, if select_a and select_b are VCC, wire_or is set to the logical OR of a and b.

The wire_and signal works in the same way, except that it defaults to VCC when none of the "select" signals is VCC, and is set to the logical AND of the corresponding input values when more than one of the signals is VCC.

Go to Node Declaration for information on how AHDL resolves conflicts when a node is assigned more than one value.

See also:

Implementing Boolean Expressions & Equations


Implementing Active-Low Logic (AHDL)
Implementing Active-Low Logic

An active-low signal becomes active when its value is GND. Active-low signals can be useful for controlling memory, peripheral, and microprocessor chips.

The daisy.tdf file shown below is a module of a daisy-chain arbitration circuit. This module makes requests for bus access to the preceding module in the daisy chain. It receives requests for bus access from itself and from the next module in the chain. Bus access is granted to the highest-priority module that requests it.

SUBDESIGN daisy

(

/local_request	: INPUT;

/local_grant	: OUTPUT;

/request_in	: INPUT;	% from lower priority  %

/request_out	: OUTPUT;	% to higher priority   %

/grant_in	: INPUT;	% from higher priority %

/grant_out	: OUTPUT;	% to lower priority    %

)

BEGIN

DEFAULTS

/local_grant	= VCC;	% active-low output	%

/request_out	= VCC;	% signals should default	%

/grant_out	= VCC;	% to VCC	%

END DEFAULTS;

IF /request_in == GND # /local_request == GND THEN

/request_out = GND;

END IF;

IF /grant_in == GND THEN

IF /local_request == GND THEN

/local_grant = GND;

ELSIF /request_in == GND THEN

/grant_out = GND;

END IF;

END IF;

END;

All signals in this file are active low. Altera recommends that you choose a node-naming scheme that clearly indicates active-low signal names--e.g., an initial "n" or a slash (/)--and use it consistently. A slash is not an operator, but is simply part of the signal name.

If Then Statements are used to determine whether modules are active, i.e., whether the signal equals GND. If a signal is active, the equations following the appropriate If Then Statement are activated. The Defaults Statement specifies that a signal is assigned to VCC when it is not active.

See also:

Naming a Boolean Operator or Comparator

Using Default Values for Variables


Implementing Bidirectional Pins (AHDL)
Implementing Bidirectional Pins

MAX+PLUS II allows I/O pins in Altera devices to be configured as bidirectional pins. Bidirectional pins can be specified with a BIDIR port that is connected to the output of a TRI primitive. The signal between the pin and the TRI primitive is a bidirectional signal that can be used to drive other logic in the project.

The bus_reg2.tdf file shown below implements a register that samples the value found on a tri-state bus. It can also drive the stored value back to the bus.

SUBDESIGN bus_reg2

(

   clk : INPUT;

   oe  : INPUT;

   io  : BIDIR;

)

VARIABLE

   dff_out : NODE;

BEGIN

   dff_out = DFF(io, clk, ,);

   io = TRI(dff_out, oe);

END;

The bidirectional io signal, driven by TRI, is used as the d input to a D flipflop (DFF). Commas are used as placeholders for the clrn and prn ports, which default to the inactive state.

You can also connect a bidirectional pin from a lower-level TDF to a top-level pin. The bidirectional output port of the subdesign should be connected to a bidirectional pin at the top level of the hierarchy. The Function Prototype for the lower-level TDF should include the bidirectional pin in the RETURNS clause. The bidir1.tdf file shown below includes four instances of the bus_reg2 function shown above.

FUNCTION bus_reg2 (clk, oe) RETURNS (io);

SUBDESIGN bidir1

(

   clk, oe  : INPUT;

   io[3..0] : BIDIR;

)

BEGIN

   io0 = bus_reg2(clk, oe);

   io1 = bus_reg2(clk, oe);

   io2 = bus_reg2(clk, oe);

   io3 = bus_reg2(clk, oe);

END;

See also:

Declaring Registers

Implementing Tri-State Buses

Ports

Using Default Values for Variables


Implementing Tri-State Buses (AHDL)
Implementing Tri-State Buses

TRI primitives that drive OUTPUT or BIDIR ports have an Output Enable input for placing the pin output in a high-impedance state in which it behaves as if it is not connected to the circuit.

You can create a tri-state bus by connecting TRI primitives and BIDIR or OUTPUT ports together with a node of type TRI_STATE_NODE. The control circuitry must ensure that at most one output is enabled (i.e., not in a high-impedance state) at any given time. This enabled output can transmit low (0) and high (1) logic levels onto the bus.

The tri_bus.tdf file shown below implements a tri-state bus using a TRI_STATE_NODE-type node created in a Node Declaration:

SUBDESIGN tri_bus

(

   in[3..1], oe[3..1] : INPUT;

   out1               : OUTPUT;

)

VARIABLE

   tnode :TRI_STATE_NODE;

BEGIN

   tnode = TRI(in1, oe1);

   tnode = TRI(in2, oe2);

   tnode = TRI(in3, oe3);

   out1 = tnode;

END;

In tri_bus.tdf, multiple assignments to tnode tie the signals together. The TRI_STATE_NODE node type, rather than the ordinary NODE node type, is required to implement a tri-state bus: multiple assignments to nodes of type NODE tie the signals together by wired-AND or wired-OR functions; whereas multiple assignments to a TRI_STATE_NODE tie the signals to the same node. However, if only one variable is assigned to a TRI_STATE_NODE-type node, it is treated as an ordinary NODE instead.

See also:

Boolean Equation Rules

Declaring Nodes

Implementing Bidirectional Pins

Variable Section


Sequential Logic (AHDL)
Sequential Logic

Logic is sequential if outputs at a specified time are a function of the inputs at that time and at some or all preceding times. All sequential circuits must include one or more flipflops. Sequential logic can be implemented in AHDL with state machines, registers, or latches; LPM functions are also available. State machines are especially useful for implementing sequential logic. Other examples of sequential logic include counters and controllers.

Information on sequential logic is available in the following topics:

Declaring Registers

Declaring Registered Outputs

Creating Counters

See also:

Megafunctions/LPM

State Machines (AHDL)

Using Conditionally Generated Logic

Using Iteratively Generated Logic


Declaring Registers (AHDL)
Declaring Registers

Registers store data values and synchronize data with a Clock signal. You can declare, i.e., implement, an instance of a register with a Register Declaration in the Variable Section. (You can also implement registers with in-line references in the Logic Section.) AHDL offers several register primitives and also supports registered LPM functions.

Once you have declared a register, you can connect it to other logic in the TDF by using its ports. A port of an instance is used in the following format:

<instance name>.<port name>

The bur_reg.tdf file shown below uses a Register Declaration to create a byte register that latches values of the d inputs onto the q outputs on the rising edge of the Clock when the load input is high.

SUBDESIGN bur_reg

(

   clk, load, d[7..0] : INPUT;

   q[7..0]            : OUTPUT;

)

VARIABLE

   ff[7..0]           : DFFE;

BEGIN

   ff[].clk = clk;

   ff[].ena = load;

   ff[].d = d[];

   q[] = ff[].q;

END;

The registers are declared as Enable D flipflops (DFFE) in the Variable Section. The first Boolean equation in the Logic Section connects the bur_reg.tdf file’s Clock input, clk, to the Clock ports of the ff[7..0] flipflops. The second equation connects the load input to the Clock Enable ports. The third equation connects the file’s data inputs, d[7..0], to the data input ports of the ff[7..0] flipflops. The fourth equation connects the file’s outputs to the flipflop outputs. All four statements are evaluated concurrently.

You can also declare T, JK, and SR flipflops in the Variable Section, then use them in the Logic Section. For example, for T flipflops (TFF), you would change the Register Declaration to ff[7..0] : TFF; and change ff[].d to ff[].t in the third equation. Similarly, for Enable JK flipflops (JKFFE), you would change the Register Declaration to ff[7..0] : JKFFE; and replace the third equation with two equations that connect the ff[].j and ff[].k ports to other signals.

If you wish to load a register on a specific rising edge of the global Clock, Altera recommends that you use the Clock Enable input of one of the DFFE, TFFE, JKFFE, or SRFFE Enable-type flipflops to control when the register is loaded.

The lpm_reg.tdf file shown below uses an in-line reference to implement an instance of the lpm_dff function that has the same functionality as the bur_reg.tdf file.

INCLUDE "lpm_dff.inc";

SUBDESIGN lpm_reg

(

   clk, load, d[7..0] : INPUT;

   q[7..0]            : OUTPUT;

)

BEGIN

   q[] = lpm_dff (.clock=clk, .enable=load, .data[]=d[])

      WITH (LPM_WIDTH=8)

   RETURNS (.q[]);

END;

See also:

Declaring Nodes

Declaring Registered Outputs

Implementing a Hierarchical Project

Implementing Boolean Expressions & Equations

Ports


Declaring Registered Outputs (AHDL)
Declaring Registered Outputs

You can declare registered outputs of a TDF by declaring the output ports as flipflops in a Register Declaration in the Variable Section. The reg_out.tdf file shown below has the same functionality as bur_reg.tdf (shown in Declaring Registers), but has registered outputs.

SUBDESIGN reg_out

(

   clk, load, d[7..0] : INPUT;

   q[7..0]            : OUTPUT;

)

VARIABLE

   q[7..0]            : DFFE; % outputs also declared as registers %

BEGIN

   q[].clk = clk;

   q[].ena = load;

   q[] = d[];

END;

When you assign a value to a registered output in the Logic Section, that value drives the d inputs to the registers. The register’s output does not change until the rising edge of the Clock. To define the Clock input to the register, use <register name>.clk for the Clock input to the register in the Logic Section. You can implement a global Clock with the GLOBAL primitive or with the Automatic Global Clock option in the Global Project Logic Synthesis command (Assign menu).

In the sample file shown above, each Enable D flipflop (DFFE) declared in the Variable Section feeds an output with the same name, so you can refer to the q outputs of the declared flipflops without using the q port of the flipflops.

In a top-level TDF, output ports are synonymous with output pins. When you declare the same name for an output port and a register, any logic option assignments on that name are applied to the pin rather than the register. These identical names can prevent you from assigning a register-specific logic option such as I/O Cell Register. Therefore, if you wish to use a register-specific logic option, you must name the registers and ports differently. (However, you may be able to implement the desired functionality in a different way. For example, you can use the Automatic I/O Cell Registers option in the Global Project Logic Synthesis dialog box to automatically implement registers in I/O cells, regardless of whether you have declared the same name for output ports and registers.)

See also:

Declaring Registers

Implementing a Hierarchical Project


Creating Counters (AHDL)
Creating Counters

Counters use sequential logic to count Clock pulses. Some counters can count forward and backward, and can be loaded with data and cleared to zero. Counters can be defined with D flipflops (DFF and DFFE) and If Then Statements or with the lpm_counter function.

The ahdlcnt.tdf file shown below implements a 16-bit loadable up counter that can be cleared to zero.

SUBDESIGN ahdlcnt

(

   clk, load, ena, clr, d[15..0] : INPUT;

   q[15..0]                      : OUTPUT;

)

VARIABLE

   count[15..0]                  : DFF;

BEGIN

   count[].clk = clk;

   count[].clrn = !clr;

   IF load THEN

      count[].d = d[];

   ELSIF ena THEN

      count[].d = count[].q + 1;

   ELSE

      count[].d = count[].q;

   END IF;

   q[] = count[];

END;

In this file, 16 D flipflops are declared in the Variable Section and assigned the names count0 through count15. The If Then Statement determines the value that is loaded into the flipflops on the rising Clock edge (e.g., if load is driven by VCC, the flipflops are assigned the value of d[]).

The lpm_cnt.tdf file shown below uses the lpm_counter function to implement the same functionality as ahdlcnt.tdf:

INCLUDE "lpm_counter.inc";

SUBDESIGN lpm_cnt

(

   clk, load, ena, clr, d[15..0] : INPUT;

   q[15..0]                      : OUTPUT;

)

VARIABLE

   my_cntr: lpm_counter WITH (LPM_WIDTH=16);

BEGIN

   my_cntr.clock  = clk;

   my_cntr.aload  = load;

   my_cntr.cnt_en = ena;

   my_cntr.aclr   = clr;

   my_cntr.data[] = d[];

   q[] = my_cntr.q[];

END;

See also:

Declaring Registers

Implementing Conditional Logic


State Machines (AHDL)

State machines, like truth tables and Boolean equations, are easily implemented in AHDL. The language is structured so that you can either assign state bits and state values yourself, or allow the MAX+PLUS II Compiler to do the work for you.

The Compiler uses advanced proprietary heuristic algorithms to make automatic state assignments that minimize the logic resources required to implement the state machine.

You simply need to draw a state diagram and construct a next-state table. The Compiler then performs the following functions automatically:

Assigns bits, selecting either a T or D flipflop (TFF or DFF) for each bit

Assigns state values

Applies sophisticated logic synthesis techniques to derive the excitation equations

To specify a state machine in AHDL, you must include the following items in the TDF:

State Machine Declaration (Variable Section)

Boolean control equations (Logic Section)

State transitions in Truth Table Statements or Case Statements (Logic Section)

You can also import and export AHDL state machines between TDFs and other design files by specifying an input or output signal as a machine port in the Subdesign Section.

The following topics provide information on creating state machines:

Implementing State Machines

Setting Clock, Reset & Enable Signals

Assigning State Machine Bits & Values

State Machines with Synchronous Outputs

State Machines with Asynchronous Outputs

Recovering from Illegal States

See also:

Importing & Exporting State Machines

Ports


Implementing State Machines (AHDL)
Implementing State Machines

You can create a state machine by declaring the name of the state machine, its states, and, optionally, the state machine bits in a State Machine Declaration in the Variable Section.

The simple.tdf file shown below has the same functionality as a D flipflop (DFF).

SUBDESIGN simple

(

   clk, reset, d : INPUT;

   q             : OUTPUT;

)

VARIABLE

   ss: MACHINE WITH STATES (s0, s1);

BEGIN

   ss.clk = clk;

   ss.reset = reset;

   CASE ss IS

      WHEN s0 =>

         q = GND;

         IF d THEN

            ss = s1;

         END IF;

      WHEN s1 =>

         q = VCC;

         IF !d THEN

            ss = s0;

         END IF;

   END CASE;

END;

In simple.tdf, a state machine with the name ss is declared in a State Machine Declaration in the Variable Section. The states of the machine are defined as s0 and s1, and no state bits are declared.

State machine transitions define the conditions under which the state machine changes to a new state. You must conditionally assign the states within a single behavioral construct to specify state machine transitions. Case or Truth Table Statements are recommended for this purpose. For example, in simple.tdf, the transitions out of each state are defined in the WHEN clauses of the Case Statement.

You can also define an output value for a state with an If Then or Case Statement. In Case Statements, these assignments are made in WHEN clauses. For example, in simple.tdf, output q is assigned to GND when state machine ss is in state s0, and to VCC when the machine is in state s1.

Output values can also be defined in truth tables, as described in Assigning State Machine Bits & Values.

See also:

Implementing Conditional Logic

Importing & Exporting State Machines

Recovering from Illegal States

Setting Clock, Reset & Enable Signals

State Machines with Asynchronous Outputs

State Machines with Synchronous Outputs


Setting Clock, Reset & Enable Signals (AHDL)
Setting Clock, Reset & Enable Signals

Clock, Reset, and Clock Enable signals control the flipflops of the state register in the state machine. These signals are specified with Boolean control equations in the Logic Section.

In the file simple.tdf shown below, the state machine Clock is driven by the input clk. The state machine’s asynchronous Reset signal is driven by reset, which is active high. In this design file, the declaration of the ena input in the Subdesign Section and the Boolean equation ss.ena = ena in the Logic Section connect the Clock Enable signal.

SUBDESIGN simple

(

   clk, reset, ena, d : INPUT;

   q                  : OUTPUT;

)

VARIABLE

   ss: MACHINE WITH STATES (s0, s1);

BEGIN

   ss.clk = clk;

   ss.reset = reset;

   ss.ena = ena;

   CASE ss IS

      WHEN s0 =>

         q = GND;

         IF d THEN

            ss = s1;

         END IF;

      WHEN s1 =>

         q = VCC;

         IF !d THEN

            ss = s0;

         END IF;

   END CASE;

END;

See also:

Assigning State Machine Bits & Values

Implementing Boolean Expressions & Equations

Ports

Recovering from Illegal States

State Machines with Asynchronous Outputs

State Machines with Synchronous Outputs


Assigning State Machine Bits & Values (AHDL)
Assigning State Machine Bits & Values

A state bit is an output of a flipflop used by a state machine to store one bit of the value of the state machine. In most cases, you should allow the MAX+PLUS II Compiler to assign state bits and values to minimize the logic resources required: the Logic Synthesizer automatically minimizes the number of state bits needed, optimizing both device utilization and performance.

However, some state machines may operate faster with state values that use more than the minimum number of state bits. In addition, you may want explicit state bits to be the outputs of a state machine. To control these cases, you can declare state machine bits and values in the State Machine Declaration.

The Global Project Logic Synthesis  command (Assign menu) includes a One-Hot State Machine Encoding option that automatically implements one-hot encoding for a project. In addition, the MAX+PLUS II Compiler automatically implements one-hot state machine encoding for FLEX 8000 and FLEX 10K devices, regardless of whether the One-Hot State Machine Encoding option is turned on or off. If you explicitly assign state bits in addition to using automatic one-hot encoding, your project’s logic may be implemented inefficiently.

The stepper.tdf file shown below implements a stepper motor controller.

SUBDESIGN stepper

(

   clk, reset   : INPUT;

   ccw, cw      : INPUT;

   phase[3..0]  : OUTPUT;

)

VARIABLE

   ss: MACHINE OF BITS (phase[3..0])

      WITH STATES  (

         s0 = B"0001",

         s1 = B"0010",

         s2 = B"0100",

         s3 = B"1000");

BEGIN

   ss.clk   = clk;

   ss.reset = reset;

   TABLE

      ss,   ccw,   cw   =>   ss;

      s0,   1,      x   =>   s3;

      s0,   x,      1   =>   s1;

      s1,   1,      x   =>   s0;

      s1,   x,      1   =>   s2;

      s2,   1,      x   =>   s1;

      s2,   x,      1   =>   s3;

      s3,   1,      x   =>   s2;

      s3,   x,      1   =>   s0;

   END TABLE;

END;

In this example, the phase[3..0] outputs declared in the Subdesign Section are also declared as bits of the state machine ss in the State Machine Declaration. Note that ccw and cw must never both be equal to 1 in the same table. AHDL assumes that only one condition in a truth table is true at a time; therefore, overlapping bit patterns may cause unpredictable results. Refer to Truth Table Statement Rules for more information.

See also:

Assigning State Machine Bits & Values

Implementing State Machines

Recovering from Illegal States

Setting Clock, Reset & Enable Signals

State Machines with Asynchronous Outputs

State Machines with Synchronous Outputs


State Machines with Synchronous Outputs (AHDL)
State Machines with Synchronous Outputs

If the outputs of a state machine depend only on the machine’s state, you can specify the state machine outputs in the WITH STATES clause of the State Machine Declaration. These state value assignments make state machine entry less prone to error, and in some cases, the logic may use fewer logic cells.

The moore1.tdf file shown below implements a four-state Moore state machine.

SUBDESIGN moore1

(

   clk   : INPUT;

   reset : INPUT;

   y     : INPUT;

   z     : OUTPUT;

)

VARIABLE

                %   current   current %

                %   state     output  %

   ss: MACHINE OF BITS (z)

       WITH STATES (s0    =   0,

                    s1    =   1,

                    s2    =   1,

                    s3    =   0);

BEGIN

   ss.clk   = clk;

   ss.reset = reset;

   TABLE

   %  current  current     next  %

   %  state    input       state %

      ss,      y      =>   ss;

      s0,      0      =>   s0;

      s0,      1      =>   s2;

      s1,      0      =>   s0;

      s1,      1      =>   s2;

      s2,      0      =>   s2;

      s2,      1      =>   s3;

      s3,      0      =>   s3;

      s3,      1      =>   s1;

   END TABLE;

END;

This example defines the states of the state machine with a State Machine Declaration. The state transitions are defined in a next-state table, which is implemented with a Truth Table Statement. In this example, machine ss has four states but only one state bit (z). The MAX+PLUS II Compiler automatically adds another bit and makes appropriate assignments to this synthetic variable to produce a four-state machine. This state machine requires at least two bits.

When state values are used as outputs, as in moore1.tdf, the project may use fewer logic cells, but the logic cells may also require more logic to drive their flipflop inputs. The Compiler’s Logic Synthesizer module may not be able to fully minimize the state machine in these cases.

Another way to design state machines with synchronous outputs is to omit state value assignments and to explicitly declare output flipflops. The file moore2.tdf, shown below, illustrates this alternative method.

SUBDESIGN moore2

(

   clk   : INPUT;

   reset : INPUT;

   y     : INPUT;

   z     : OUTPUT;

)

VARIABLE

   ss: MACHINE WITH STATES (s0, s1, s2, s3);

   zd: NODE;

BEGIN

   ss.clk   = clk;

   ss.reset = reset;

   z = DFF(zd, clk, VCC, VCC);

   TABLE

   %  current  current     next     next   %

   %  state    input       state    output %

      ss,      y      =>   ss,      zd;

      s0,      0      =>   s0,      0;

      s0,      1      =>   s2,      1;

      s1,      0      =>   s0,      0;

      s1,      1      =>   s2,      1;

      s2,      0      =>   s2,      1;

      s2,      1      =>   s3,      0;

      s3,      0      =>   s3,      0;

      s3,      1      =>   s1,      1;

   END TABLE;

END;

Instead of specifying the output with state value assignments in the State Machine Declaration, this example includes a "next output" column after the "next state" column in the Truth Table Statement. This method uses a D flipflop (DFF)--called with an in-line reference--to synchronize the outputs with the Clock.

See also:

Assigning State Machine Bits & Values

Creating Decoders

Declaring Registers

Implementing State Machines

Recovering from Illegal States

Setting Clock, Reset & Enable Signals

State Machines with Asynchronous Outputs


State Machines with Asynchronous Outputs (AHDL)
State Machines with Asynchronous Outputs

AHDL supports the implementation of state machines with asynchronous outputs. The outputs of these types of state machines can change whenever the inputs change, regardless of Clock transitions.

The mealy.tdf file shown below implements a four-state Mealy state machine with asynchronous outputs.

SUBDESIGN mealy

(

   clk   : INPUT;

   reset : INPUT;

   y     : INPUT;

   z     : OUTPUT;

)

VARIABLE

   ss: MACHINE WITH STATES (s0, s1, s2, s3);

BEGIN

   ss.clk = clk;

   ss.reset = reset;

   TABLE

   %  current  current     current  next  %

   %  state    input       output   state %

      ss,      y       =>  z,       ss;

      s0,      0       =>  0,       s0;

      s0,      1       =>  1,       s1;

      s1,      0       =>  1,       s1;

      s1,      1       =>  0,       s2;

      s2,      0       =>  0,       s2;

      s2,      1       =>  1,       s3;

      s3,      0       =>  0,       s3;

      s3,      1       =>  1,       s0;

   END TABLE;

END;

See also:

Assigning State Machine Bits & Values

Creating Decoders

Implementing State Machines

Recovering from Illegal States

Setting Clock, Reset & Enable Signals

State Machines with Synchronous Outputs


Recovering from Illegal States (AHDL)
Recovering From Illegal States

Logic generated for a state machine by the MAX+PLUS II Compiler will behave as you specified in the TDF. However, state machine designs that explicitly declare state bits and which also do not use one-hot encoding often allow state bit values that are not assigned to valid states. These unassigned state bit values are called illegal states. A design that enters an illegal state--for example, as a result of setup or hold time violations--can cause erroneous outputs. Although Altera recommends that state machine inputs meet all setup and hold time requirements, you can make a state machine recover from an illegal state by forcing the illegal state to a known state with a Case Statement.

The Global Project Logic Synthesis  command (Assign menu) includes a One-Hot State Machine Encoding option that automatically implements one-hot encoding--which automatically assigns all state bits to valid states--for a project. In addition, the MAX+PLUS II Compiler automatically implements one-hot state machine encoding for FLEX 8000 and FLEX 10K devices, regardless of whether the One-Hot State Machine Encoding option is turned on or off. If you explicitly assign state bits in addition to using automatic one-hot encoding, your project’s logic may be implemented inefficiently.

To recover from illegal states, you must name all illegal states in a state machine. The WHEN OTHERS clause in the Case Statement, which forces each transition from an illegal state to a known state, applies only to states that have been declared but are not mentioned in a WHEN clause. The WHEN OTHERS clause can force the required transitions only if all illegal states are defined in the State Machine Declaration.

For an n-bit state machine, 2^n possible states exist. If you declare n bits in a state machine, you should continue to add dummy state names until the number of states reaches a power of 2. The recover.tdf file shown below contains a state machine that can recover from illegal states.

SUBDESIGN recover

(

   clk : INPUT;

   go  : INPUT;

   ok  : OUTPUT;

)

VARIABLE

   sequence : MACHINE

            OF BITS (q[2..0])

            WITH STATES (

               idle,

               one,

               two,

               three,

               four,

               illegal1,

               illegal2,

               illegal3);

BEGIN

   sequence.clk = clk;

   CASE sequence IS

      WHEN idle =>

         IF go THEN

            sequence = one;

         END IF;

      WHEN one =>

         sequence = two;

      WHEN two =>

         sequence = three;

      WHEN three =>

         sequence = four;

      WHEN OTHERS =>

         sequence = idle;

   END CASE;

   ok = (sequence == four);

END;

This example contains 3 bits: q2, q1, and q0. Therefore, 2^3 states, i.e., 8 states, exist. Since only 5 of the states are declared, 3 dummy state names were added, creating a total of 8 states.

See also:

Assigning State Machine Bits & Values

Implementing State Machines

Implementing Conditional Logic

Setting Clock, Reset & Enable Signals

State Machines with Asynchronous Outputs

State Machines with Synchronous Outputs


Implementing a Hierarchical Project (AHDL)
Implementing a Hierarchical Project

AHDL TDFs can be mixed with other design files in a project hierarchy. Lower-level files in a project hierarchy can either be Altera-provided or user-defined megafunctions or macrofunctions.

Information on implementing a hierarchical project is available in the following topics:

Using Altera MAX+PLUS II Megafunctions & Macrofunctions

Using Custom Megafunctions & Macrofunctions

Importing & Exporting State Machines

See also:

Renaming a Megafunction or Macrofunction in the Current Project


Using Altera-Provided Unparameterized Functions (AHDL)
Using Altera-Provided Unparameterized Functions

MAX+PLUS II includes libraries of primitives and old-style macrofunctions that are not inherently parameterized; in addition, some megafunctions are not inherently parameterized. All MAX+PLUS II logic functions can be used to create hierarchical logic designs. Mega- and macrofunctions are automatically installed in subdirectories of the \maxplus2\max2lib directory created during installation; primitive logic is built into AHDL.

There are two ways to use (i.e., insert an instance of) an unparameterized function in AHDL:

Declare a variable for the function, i.e., an instance name, in an Instance Declaration in the Variable Section, and use ports of the instance of the function in the Logic Section.

Use an in-line logic function reference in the Logic Section of the TDF.

The inputs and outputs of mega- and macrofunctions must be declared with a Function Prototype Statement. (Function Prototypes are not required for primitives.) MAX+PLUS II provides Include Files that contain Function Prototypes for all MAX+PLUS II mega- and macrofunctions in the \maxplus2\max2lib\mega_lpm and \maxplus2\max2inc directories, respectively. With an Include Statement, you can import the contents of an Include File into a TDF to declare the Function Prototype of a MAX+PLUS II mega- or macrofunction.

The macro1.tdf file shown below shows a 4-bit counter connected to a 4-bit-binary-to-16-line decoder. Instances of these functions are created with Instance Declarations in the Variable Section:

INCLUDE "4count";

INCLUDE "16dmux";

SUBDESIGN macro1

(

   clk        : INPUT;

   out[15..0] : OUTPUT;

)

VARIABLE

   counter : 4count;

   decoder : 16dmux;

BEGIN

   counter.clk = clk;

   counter.dnup = GND;

   decoder.(d,c,b,a) = counter.(qd,qc,qb,qa);

   out[15..0] = decoder.q[15..0];

END;

This file uses Include Statements to import Function Prototypes for two Altera-provided macrofunctions: 4count and 16dmux. In the Variable Section, the variable counter is declared as an instance of the 4count function, and the variable decoder is declared as an instance of the 16dmux function. The input ports of both functions, which are in the format <instance name>.<port name>, are defined on the left side of the Boolean equations in the Logic Section; the output ports are defined on the right.

The macro2.tdf file shown below has the same functionality as macro1.tdf, but creates instances of the two functions with in-line references and the nodes q[3..0]:

INCLUDE "4count";

INCLUDE "16dmux";

SUBDESIGN macro2

(

   clk         : INPUT;

   out[15..0]  : OUTPUT;

)

VARIABLE

   q[3..0]     : NODE;

BEGIN

   (q[3..0], ) = 4count (clk, , , , , GND, , , , );

% equivalent in-line ref. with named port association  %

%  (q[3..0], ) = 4count (.clk=clk, .dnup=GND);         %

% equivalent in-line ref. with named port association  %

% and RETURNS clause specifying which outputs are used %

%  q[3..0] = 4count (.clk=clk, .dnup=GND)              %

%                RETURNS (qd, qc, qb, qa);             %

   out[15..0]  = 16dmux (.(d, c, b, a)=q[3..0]);

% equivalent in-line ref. with positional port association %

% out[15..0]  = 16dmux (q[3..0]);                          %

END;

The Function Prototypes for the two macrofunctions, which are stored in the Include Files 4count.inc and 16dmux.inc, are shown below:

FUNCTION 4count (clk, clrn, setn, ldn, cin, dnup, d, c, b, a)

   RETURNS (qd, qc, qb, qa, cout);

FUNCTION 16dmux (d, c, b, a)

   RETURNS (q[15..0]);

The in-line references for 4count and 16dmux appear in the first and second Boolean equations in the Logic Section, respectively. The in-line reference for 4count uses positional port association, whereas the in-line reference for 16dmux uses named port association. The input ports of both macrofunctions are defined on the right side of the in-line references; the output ports are defined on the left.

Comments show the equivalent in-line references for different styles of port association. In an in-line reference, ports on the right-hand side of the equals symbol (=) can be listed with either positional or named port association; ports on the left-hand side of the equals symbol always use positional port association. When positional port association is used, the order of ports is important because there is a one-to-one correspondence between the order of the ports in the Function Prototype and the ports defined in the Logic Section. In the in-line reference for 4count, commas are used as placeholders for ports that are not explicitly connected.

A RETURNS clause, which is based on the RETURNS clause in the Function Prototype, is optional in an in-line reference. The RETURNS clause can be used to list the subset of the function’s outputs that is used in the instance. In macro2.tdf, the second comment that shows an alternative in-line reference for 4count omits the cout output of 4count from the RETURNS clause; therefore, only the q[3..0] outputs are listed in the in-line reference and a comma placeholder is not required for cout.

Primitives and old-style macrofunctions always have default values for unconnected inputs. In contrast, megafunctions do not necessarily have default values for unconnected inputs.

See also:

Ports

Renaming a Megafunction or Macrofunction in the Current Project

Using Altera-Provided Parameterized Functions

Using Custom Megafunctions & Macrofunctions


Using Altera-Provided Parameterized Functions (AHDL)
Using Altera-Provided Parameterized Functions

MAX+PLUS II includes inherently parameterized megafunctions, including LPM functions. For example, parameters are used to specify the width of a port or whether a block of RAM should be implemented as synchronous or asynchronous memory. Parameterized functions can contain other subdesigns, which may be parameterized or unparameterized. Parameters can also be used on some old-style macrofunctions that are not inherently parameterized. (Primitives cannot be parameterized.) All MAX+PLUS II logic functions can be used to create hierarchical logic designs. Mega- and macrofunctions are automatically installed in subdirectories of the \maxplus2\max2lib directory created during installation; primitive logic is built into AHDL.

Parameterized functions are instantiated with an in-line logic function reference or an Instance Declaration in the same way as unparameterized functions, as described in Using Altera-Provided Unparameterized Functions, with a few additional steps:

The logic function instance must include a WITH clause, which is based on the WITH clause in the Function Prototype, that lists the parameters used by the instance. You can use the WITH clause to optionally assign parameter values on an instance; however, for all required parameters in a function, a parameter value must be supplied somewhere within the project. If the instance itself does not include some or all of the values for required parameters, the Compiler searches for them in parameter value search order.

Since parameterized megafunctions do not necessarily have default values for unconnected inputs, you must ensure that all required ports are connected. In contrast, primitives and old-style macrofunctions always have default values for unconnected inputs.

The inputs, outputs, and parameters of the function are declared with a Function Prototype Statement. MAX+PLUS II provides Include Files that contain Function Prototypes for all MAX+PLUS II mega- and macrofunctions in the \maxplus2\max2lib\mega_lpm and \maxplus2\max2inc directories, respectively. With an Include Statement, you can import the contents of an Include File into a TDF to declare the Function Prototype of a MAX+PLUS II mega- or macrofunction.

The lpm_add1.tdf file shown below implements an 8-bit adder with an in-line logic function reference to the parameterized lpm_add_sub megafunction:

INCLUDE "lpm_add_sub.inc";

SUBDESIGN lpm_add1

(

   a[8..1], b[8..1] : INPUT;

   c[8..1]          : OUTPUT;

   carry_out        : OUTPUT;

)

BEGIN

% Megafunction instance with positional port association %

   (c[], carry_out, ) = lpm_add_sub(GND, a[], b[], GND)

                           WITH (LPM_WIDTH=8,

                                 LPM_REPRESENTATION="unsigned");

% Equivalent instance with named port association %

   (c[], carry_out, ) = lpm_add_sub(.dataa[]=a[], .datab[]=b[],

                              .cin=GND, .add_sub=GND)

                           WITH (LPM_WIDTH=8,

                                 LPM_REPRESENTATION="unsigned");

END;

The Function Prototype for lpm_add_sub, which is stored in the Include File lpm_add_sub.inc, is shown below:

FUNCTION lpm_add_sub(cin, dataa[LPM_WIDTH-1..0], datab[LPM_WIDTH-1..0],

      add_sub)

   WITH (LPM_WIDTH, LPM_REPRESENTATION, LPM_DIRECTION, ADDERTYPE,

      ONE_INPUT_IS_CONSTANT)

   RETURNS (result[LPM_WIDTH-1..0], cout, overflow);

Only the LPM_WIDTH parameter is required, and the instance of the lpm_add_sub function in lpm_add1.tdf specifies parameter values only for the LPM_WIDTH and LPM_REPRESENTATION parameters.

The lpm_add2.tdf file shown below is identical to lpm_add1.tdf, but implements the 8-bit adder with an Instance Declaration:

INCLUDE "lpm_add_sub.inc";

SUBDESIGN lpm_add2

(

   a[8..1], b[8..1] : INPUT;

   c[8..1]          : OUTPUT;

   carry_out        : OUTPUT;

)

VARIABLE

   8bitadder : lpm_add_sub WITH (LPM_WIDTH=8,

                  LPM_REPRESENTATION="unsigned");

BEGIN

   8bitadder.cin = GND

   8bitadder.dataa[] = a[]

   8bitadder.datab[] = b[]

   8bitadder.add_sub = GND

   c[] = 8bitadder.result[]

   carry_out = 8bitadder.cout

END;

See also:

Ports

Renaming a Megafunction or Macrofunction in the Current Project

Using Custom Megafunctions & Macrofunctions


Using Custom Megafunctions & Macrofunctions (AHDL)
Using Custom Megafunctions & Macrofunctions

You can easily create and use custom megafunctions or macrofunctions in AHDL TDFs.

Once you have defined the logic for a custom function in a design file, a few steps are required to use the function in other TDFs or other types of design files.

To prepare a custom AHDL-based mega- or macrofunction for use in other design files:

1.	Compile and optionally simulate the design file to ensure that it functions correctly.

2.	If you plan to use the function in multiple projects, you should designate the directory that contains the design file as a user library with User Libraries (Options menu) or save a copy of the file to an existing user library directory. Otherwise, save a copy of the file to the directory containing the project that will use the custom function.

3.	With the file open in a Text Editor window, create an Include File and a symbol that represent the current file:

a.	Choose Create Default Include File (File menu) to create an Include File that can be used in a higher-level TDF. With an Include Statement, you can import the contents of an Include File into a TDF to declare the Function Prototype of a custom mega- or macrofunction.

b.	Choose Create Default Symbol (File menu) to create a symbol that can be used in a GDF.

Once you have prepared a function for use in other design files, you can create a new TDF and insert an instance of the function with an Instance Declaration or an in-line reference. You can use custom functions in exactly the same way as Altera-provided functions. See Using Altera-Provided Unparameterized Functions and Using Altera-Provided Parameterized Functions for more information.

See also:

Compiling a Project

Creating a Default Include File

Creating the Default Symbol for a File

Importing & Exporting State Machines

Renaming a Megafunction or Macrofunction in the Current Project

Specifying a User Library


Importing & Exporting State Machines (AHDL)
Importing & Exporting State Machines

You can import and export state machines between TDFs and other design files by specifying an input or output port as MACHINE INPUT or MACHINE OUTPUT in the Subdesign Section. The Function Prototype that represents the file containing the state machine must indicate which inputs and outputs are state machines by prefixing the signal names with the keyword MACHINE.

MACHINE INPUT and MACHINE OUTPUT port types cannot be used in a top-level design file. Although top-level files with these port types do not compile fully, you can use Project Save & Check (File menu) to check their syntax and Create Default Include File (File menu) to create an Include File that represents the current file.

You can rename a state machine with a temporary name by entering a Machine Alias Declaration in the Variable Section. You can use a machine alias in the file where the state machine is created or in a file that uses a MACHINE INPUT port to import a state machine. You can then use this name instead of the original state machine name.

The ss_def.tdf file shown below defines and exports the state machine ss with the MACHINE OUTPUT port ss_out.

SUBDESIGN ss_def

(

   clk, reset, count : INPUT;

   ss_out            : MACHINE OUTPUT;

)

VARIABLE

   ss: MACHINE WITH STATES (s1, s2, s3, s4, s5);

BEGIN

   ss_out = ss;

   CASE ss IS

      WHEN s1=>

         IF count THEN ss = s2; ELSE ss = s1; END IF;

      WHEN s2=>

         IF count THEN ss = s3; ELSE ss = s2; END IF;

      WHEN s3=>

         IF count THEN ss = s4; ELSE ss = s3; END IF;

      WHEN s4=>

         IF count THEN ss = s5; ELSE ss = s4; END IF;

      WHEN s5=>

         IF count THEN ss = s1; ELSE ss = s5; END IF;

   END CASE;

   ss.(clk, reset) = (clk, reset);

END;

The ss_use.tdf file shown below imports a state machine with the MACHINE INPUT port ss_in.

SUBDESIGN ss_use

(

   ss_in : MACHINE INPUT;

   out   : OUTPUT;

)

BEGIN

   out = (ss_in == s2) OR (ss_in == s4);

END;

The top1.tdf file shown below uses in-line references to insert instances of the functions ss_def and ss_use. The Function Prototypes for ss_def and ss_use include MACHINE keywords that indicate which inputs and outputs are state machines.

FUNCTION ss_def (clk, reset, count) RETURNS (MACHINE ss_out);

FUNCTION ss_use (MACHINE ss_in) RETURNS (out);

SUBDESIGN top1

(

sys_clk, /reset, hold : INPUT;

sync_out              : OUTPUT;

)

VARIABLE

ss_ref: MACHINE;  % Machine Alias Declaration %

BEGIN

ss_ref = ss_def(sys_clk, !/reset, !hold);

sync_out = ss_use(ss_ref);

END;

An external state machine can also be implemented in a top-level TDF with an Instance Declaration in the Variable Section. The top2.tdf file shown below has the same functionality as top1.tdf, but uses Instance Declarations instead of in-line references to instantiate the functions.

FUNCTION ss_def (clk, reset, count) RETURNS (MACHINE ss_out);

FUNCTION ss_use (MACHINE ss_in) RETURNS (out);

SUBDESIGN top2

(

sys_clk, /reset, hold : INPUT;

sync_out              : OUTPUT;

)

VARIABLE

sm_macro : ss_def;

sync     : ss_use;

BEGIN

   sm_macro.(clk, reset, count) = (sys_clk, !/reset, !hold);

   sync.ss_in = sm_macro.ss_out;

   sync_out = sync.out;

END;

See also:

State Machines (AHDL)

Using Altera-Provided Parameterized Functions

Using Altera-Provided Unparameterized Functions

Using Custom Megafunctions & Macrofunctions


Implementing LCELL & SOFT Primitives (AHDL)
Implementing LCELL & SOFT Primitives

You can limit the extent of logic synthesis by changing NODE variables into SOFT and LCELL primitives. NODE variables and LCELL primitives provide the greatest control over logic synthesis. SOFT primitives provide less control over logic synthesis.

NODE variables, which are declared with a Node Declaration in the Variable Section, place very few restrictions on logic synthesis. During synthesis, the Logic Synthesizer replaces each instance of a NODE variable with the logic that the variable represents. It then minimizes the logic to fit into a single logic cell. This method usually yields the greatest speed, but may result in logic that is too complex or hard to fit.

SOFT buffers provide more control over resource usage than NODE variables. The Logic Synthesizer chooses when to replace instances of SOFT primitives with LCELL primitives. SOFT buffers may help eliminate logic that is too complex and make the project easier to fit, but may increase logic cell utilization and reduce speed performance.

LCELL primitives provide the most control. The Logic Synthesizer minimizes all logic that drives an LCELL primitive so that the logic fits into a single logic cell. LCELL primitives are always implemented in a logic cell, and they are never removed from the project even if they are fed by a single input. If the project is minimized so that an LCELL primitive is fed by a single input, you can use a SOFT primitive instead of an LCELL primitive so that the SOFT primitive is removed during logic synthesis.

MAX+PLUS II provides several logic options that automatically insert or remove SOFT and LCELL buffers at appropriate locations in the project. See Assigning a Logic Option for more information.

The following illustration shows two versions of a TDF: one is implemented with NODE variables and one with SOFT primitives. In nodevar, the variable odd_parity is declared as a NODE, then assigned the value of the Boolean expression d0 $ d1 $ ... $ d8. In softbuf, the Compiler will replace some of the SOFT primitives with LCELL primitives during processing to improve device utilization.

TDF with NODE Variables:	TDF with SOFT Primitives:

SUBDESIGN nodevar	SUBDESIGN softbuf

(	(

)	)

VARIABLE	VARIABLE

odd_parity : NODE;	odd_parity : NODE;

BEGIN	BEGIN

odd_parity = d0 $ d1 $ d2	odd_parity = SOFT(d0 $ d1 $ d2)

           $ d3 $ d4 $ d5	$ SOFT(d3 $ d4 $ d5)

        $ d6 $ d7 $ d8;	$ SOFT(d6 $ d7 $ d8);

END;	END;

See also:

Declaring Nodes

Guiding the Partitioner

Implementing a Hierarchical Project

Implementing Boolean Expressions & Equations


Implementing RAM & ROM (AHDL)
Implementing RAM & ROM

MAX+PLUS II (and AHDL) provide several LPM functions and other megafunctions that allow you to implement RAM and ROM in MAX+PLUS II devices. The generic, scalable nature of each of these functions ensures that you can use them to implement any supported type of RAM or ROM in MAX+PLUS II.

Altera does not recommend creating custom logic functions to implement memory. You should use Altera-provided functions in all cases where you wish to implement RAM or ROM.

The following megafunctions can be used to implement RAM and ROM in MAX+PLUS II:

Name:	Description:

LPM_RAM_DQ	Synchronous or asynchronous memory with separate input and output ports

LPM_RAM_IO	Synchronous or asynchronous memory with a single I/O port

LPM_ROM	Synchronous or asynchronous read-only memory

CSDPRAM	Synchronous or asynchronous read-only memory

CSFIFO	Cycle-shared first-in first-out (FIFO) buffer

In these LPM functions, parameters are used to determine the input and output data widths; the number of data words stored in memory; whether data inputs, address/control inputs, and outputs are registered or unregistered; whether an initial memory content file is to be included for a RAM block; and so on.

See also:

Megafunctions/LPM


Naming a Boolean Operator or Comparator (AHDL)
Naming a Boolean Operator or Comparator

You can name Boolean operators and comparators in AHDL files to make it easy to enter resource assignments and to interpret the Equations Section of the project’s Report File.

The boole3.tdf file shown below is identical to the boole1.tdf file (shown in Implementing Boolean Expressions & Equations), but uses named operators. The operator name is separated from the operator by a colon (:); the name can contain up to 32 name chararacters.

SUBDESIGN boole3

(

   a0, a1, b  : INPUT;

   out1, out2 : OUTPUT;

)

BEGIN

   out1 = a1 tiger:& !a0;

   out2 = out1 panther:# b;

END;

The following Report File excerpts show the difference between boole3.rpt and boole1.rpt for the first of the two equations:

-- boole3.rpt equations:

-- Node name is 'out1' from file "boole3.tdf" line 7, column 2

-- Equation name is 'out1', location is LC3_A1, type is output

out1 = tiger~0;

-- Node name is 'tiger~0' from file "boole3.tdf" line 7, column 18

-- Equation name is 'tiger~0', location is LC2_A1, type is buried

tiger~0 = LCELL( _EQ002);

  _EQ002 = !a0 &  a1;

-- boole1.rpt equations:

-- Node name is 'out1' from file "boole1.tdf" line 7, column 2

-- Equation name is 'out1', location is LC3_A1, type is output

out1 = _LC2_A1;

-- Node name is ':33' from file "boole1.tdf" line 7, column 12

-- Equation name is '_LC2_A1', type is buried

LC2_A1 = LCELL( _EQ001);

  _EQ001 = !a0 &  a1;

Depending on the logic of the equation, a named operator can produce multiple node names; however, all names are based on the operator name and are thus easily recognizable in the Report File. In boole3.rpt, a single node, tiger~0, is generated for the first equation. In boole1.tdf, the Compiler assigns the net ID :33 to the same node.

After you have compiled a project, you can use the named operator-based node names shown in the Report File to enter resource assignments for future compilations, even if the project logic changes. The names of logic cells created from named operators remain constant if you change unrelated logic (e.g., other equations) in the file. For example, you can enter an assignment on the node tiger~0. In contrast, if operators are unnamed, only net ID numbers are available, and these numbers are randomly reassigned with each compilation.

See also:

Assigning a Clique

Assigning a Pin, Location, or Chip

Assigning an Individual Logic Option or Synthesis Style

Assigning Individual Timing Requirements

Comparators

Implementing Boolean Expressions & Equations

Logical Operators


Using Iteratively Generated Logic (AHDL)
Using Iteratively Generated Logic

When you wish to use multiple blocks of logic that are very similar, you can use the For Generate Statement to iteratively generate logic based on a numeric range delimited by arithmetic expressions.

The iter_add.tdf file shown below shows an example of iterative logic generation:

CONSTANT NUM_OF_ADDERS = 8;

SUBDESIGN iter_add

(

   a[NUM_OF_ADDERS..1], b[NUM_OF_ADDERS..1], cin : INPUT;

   c[NUM_OF_ADDERS..1], cout                     : OUTPUT;

)

VARIABLE

   sum[NUM_OF_ADDERS..1], carryout[(NUM_OF_ADDERS+1)..1] : NODE;

BEGIN

   carryout[1] = cin;

   FOR i IN 1 TO NUM_OF_ADDERS GENERATE

      sum[i] = a[i] $ b[i] $ carryout[i];   % Full Adder %

      carryout[i+1] = a[i] & b[i] # carryout[i] & (a[i] $ b[i]);

   END GENERATE;

   cout = carryout[NUM_OF_ADDERS+1];

   c[] = sum[];

END;

In iter_add.tdf, the For Generate Statement is used to instantiate full adders that each perform one bit of the NUM_OF_ADDERS-bit (i.e., 8-bit) addition. The carryout of each bit is generated along with each full adder.

The If Generate Statement is especially useful with For Generate Statements that handle special cases differently, for example, the the first and last stages of a multi-stage multiplier. See Using Conditionally Generated Logic for more information.


Using Conditionally Generated Logic (AHDL)
Using Conditionally Generated Logic

You can generate logic conditionally with If Generate Statements, if, for example, you wish to implement different behavior based on the value of an arithmetic expressions. An If Generate Statement lists a series of behavioral statements that are activated after the positive evaluation of one or more arithmetic expressions.

The condlog1.tdf file shown below uses an If Generate Statement to implement different behavior for the output_b output on the basis of the current device family:

PARAMETERS (DEVICE_FAMILY);

SUBDESIGN condlog1

(

   input_a : INPUT;

   output_b : OUTPUT;

)

BEGIN

   IF DEVICE_FAMILY == "FLEX8K" GENERATE

      output_b = input_a;

   ELSE GENERATE

      output_b = LCELL(input_a);

   END GENERATE;

END;

The If Generate Statement is especially useful with For Generate Statements that handle special cases differently, for example, the first and last stages of a multi-stage multiplier. See Using Iteratively Generated Logic for more information on For Generate Statements.

MAX+PLUS II includes the predefined parameter DEVICE_FAMILY, as shown in the example above, and the predefined evaluated function USED, which can be used in arithmetic expressions. The DEVICE_FAMILY parameter can be used to test the current device family for the project, which is specified with Device (Assign menu). The USED evaluated function can be used to test whether an optional port has been used in the current instance. USED takes the port name as input and returns a value of FALSE if the port is not used.

You can find numerous additional examples of If Generate Statements in the TDFs that implement LPM functions in MAX+PLUS II. These TDFs are located in the mega_lpm subdirectory of the max2lib directory.


Using the Assert Statement (AHDL)
Using the Assert Statement

You can use the Assert Statement to test the validity of any arbitrary expression that uses parameters, numbers, evaluated functions, or the used or unused status of a port. You might, for example, use the Assert Statement to determine whether the value of an optional parameter falls within a range determined by the value of a second parameter.

When you use an Assert Statement with conditions, you list the acceptable values for the assertion conditions. If a value is unacceptable, the assertion is activated and a message is issued. If you use an Assert Statement without conditions, the assertion is always activated.

The Compiler evaluates each assertion condition only once, after the Compiler Netlist Extractor module has resolved all parameter values. An assertion cannot depend on the value of a signal that is implemented in the device. For example, if an Assert Statement is placed after an If Then Statement of the form IF a = VCC THEN c = d, the assertion condition cannot depend on the value of a.

The condlog2.tdf file shown below has the same functionality as condlog1.tdf (shown in Using Conditionally Generated Logic), but uses Assert Statements in the Logic Section to report which logic was generated by the If Generate Statement:

PARAMETERS (DEVICE_FAMILY);

SUBDESIGN condlog2

(

   input_a : INPUT;

   output_b : OUTPUT;

)

BEGIN

   IF DEVICE_FAMILY == "FLEX8000" GENERATE

      output_b = input_a;

      -- Assertion is always activated if there is no condition

      ASSERT

         REPORT "Compiling for FLEX8000 family"

         SEVERITY INFO;

   ELSE GENERATE

      output_b = LCELL(input_a);

      -- Assertion is activated if current family is not FLEX10K

      -- or FLEX 8000. Severity defaults to ERROR

      ASSERT (DEVICE_FAMILY == "FLEX10K")

         REPORT "Compiling for % family", DEVICE_FAMILY;

   END GENERATE;

END;

You can find numerous additional examples of Assert Statements in the TDFs that implement LPM functions in MAX+PLUS II. These TDFs are located in the mega_lpm subdirectory of the max2lib directory.


**********************  BEGINNING OF NON-TRANSLATED TEXT *********************************

Messages from other files documented here

ss2e_comment_end_missing

Messages in ml_msgs.msg that are documented elsewhere:

fml_cant_write_gdf	glmess

fml_cant_read_parser_table	glmess

eml_bad_based_number	comess

eml_expected_but_found	comess

eml_expected_filename	comess

eml_expeced_gdf_indent_char	comess

eml_expected_quote	comess

eml_expected_semicolon	comess

eml_illegal_option_val	glmess

eml_unknown_option	glmess

*****************************  END OF NON-TRANSLATED TEXT *********************************


BIDIR pin <name> cannot be assigned more than one value

CAUSE	A bidirectional pin (BIDIR) has been assigned multiple values, which are logically ORed during compilation. A bidirectional pin cannot be driven by logic.

ACTION:	Assign the values to the input of a TRI buffer, and drive the BIDIR primitive with the TRI buffer.

See also:

Implementing Bidirectional Pins (AHDL)

MAX+PLUS II Messages

Message Format


Binary number B"1" was expanded differently before MAX+PLUS II version 5.0

CAUSE:	The binary number B"1" expanded to B"000...01" when compiled with pre-version 5.0 MAX+PLUS II, but in version 5.0 and higher, B"1" expands to B"111...1".

ACTION:	Be aware that projects with these binary numbers that were created with pre-version 5.0 MAX+PLUS II will behave differently. Change B"1" into 1 to retain the pre-version 5.0 behavior. Change B"1" into VCC to use the version 5.0 behavior and avoid this warning during future compilations.

See also:

MAX+PLUS II Messages

Message Format


Can't divide an expression by zero
Cant divide an expression by zero

CAUSE:	The divisor in an arithmetic expression in your AHDL TDF is defined as zero or as another arithmetic expression that reduces to zero.

ACTION:	Make sure the divisor, or the arithmetic expression that defines the divisor, does not equal zero.

See also:

MAX+PLUS II Messages

Message Format


Chip <name> already declared

CAUSE	When MAX+PLUS II attempted to convert the resource and device assignments in your project to the ACF format, it found the same chip name in two or more Device Specifications in a TDF. All chips in a project must have unique names.

ACTION:	To successfully convert the TDF assignments into the ACF format, you must ensure that all chips have unique names before choosing Convert Obsolete Assignment Format. You should use the Assign menu commands, the Floorplan Editor, and/or the ACF to enter all assignments for new projects.

See also:

Changes to AHDL Support in MAX+PLUS II Version 5.0

Converting an Obsolete Assignment Format

MAX+PLUS II Messages

Message Format


Constant <name> may not be assigned a value

CAUSE:	You assigned a value to a symbolic name that is defined as a constant.

ACTION:	Constants must remain constant. Remove any assignments to constants in your Logic Section.

See also:

Constant Statement (AHDL)

MAX+PLUS II Messages

Message Format

Using Constants (AHDL)


Constant too large

CAUSE:	You used a decimal number larger than 4,294,967,295 as a constant.

ACTION:	Ensure that all decimal numbers in your project are no larger than 4,294,967,295. If necessary, express the number in binary or hexadecimal notation since these numbers may be of arbitrary width.

See also:

MAX+PLUS II Messages

Message Format

Using Constants (AHDL)

Using Numbers (AHDL)


Constant truncated

CAUSE:	You assigned a number to a group of lesser width. The number of significant bits needed to represent the number you specified was greater than the size of the group to which the number was assigned, so the number was truncated to match the size of the group.

ACTION:	No action is required. If you do not want the number to be truncated, make sure it is not larger than the group to which it is assigned.

See also:

Defining Groups (AHDL)

MAX+PLUS II Messages

Message Format

Using Numbers (AHDL)


Defaults Statement must be first in Logic Section

CAUSE:	You entered a Defaults Statement in the wrong location. A Defaults Statement must be entered immediately after the BEGIN keyword in the Logic Section.

ACTION:	Move the Defaults Statement to the beginning of the Logic Section.

See also:

MAX+PLUS II Messages

Message Format

Using Default Values for Variables (AHDL)


Design name <name> must be the same as the filename <filename>

CAUSE:	When MAX+PLUS II attempted to convert the resource and device assignments in your project to the ACF format, it found that the name of the design specified in the Design Section is different from the name of the TDF.

ACTION:	To successfully convert the TDF information into the ACF format, you must ensure that both the design name and filename are the same before choosing Convert Obsolete Assignment Format. You should use the Assign menu commands, the Floorplan Editor, and/or the ACF to enter all assignments for new projects.

See also:

Changes to AHDL Support in MAX+PLUS II Version 5.0

Converting an Obsolete Assignment Format

MAX+PLUS II Messages

Message Format

Quoted & Unquoted Names (AHDL)


Don't care value <text> detected in comparison
Dont care value <text> detected in comparison

CAUSE	You used a constant with dont care (X) values as an operand in a comparison. The comparison will be performed as if those values were not part of the comparison, and unexpected carries and borrows may occur.

ACTION:	Use only fully defined values, i.e., values with no dont care bits, in comparisons.

See also:

MAX+PLUS II Messages

Message Format


Expected <text> but found <text>

CAUSE:	MAX+PLUS II expected but could not find a state name, node, or constant in an AHDL TDF. You may have entered a symbolic name that is not legal at this location in the TDF.

ACTION:	Check the TDF for errors. If the error is in a state machine assignment, you have assigned a constant instead of a state name to the state machine in the Logic Section. If the error is in an If Statement, the statements expression is a group instead of a node. If the error is in a Defaults Statement, you have assigned a non-constant expression to a node. If the error is in a Truth Table Statement, you have included a non-constant expression in the table body.

See also:

Implementing Conditional Logic (AHDL)

MAX+PLUS II Messages

Message Format

State Machines (AHDL)

State Machine Declaration (AHDL)

Using Default Values for Variables (AHDL)


Expression must be a machine variable, machine input, or machine output

CAUSE:	You compared a state to an expression other than an AHDL state machine variable, machine input, or machine output. States may only be compared to these variables.

ACTION:	Edit the expression.

See also:

Assigning State Machine Bits & Values (AHDL)

MAX+PLUS II Messages

Message Format


Expression passed to LOG2 is negative or zero

CAUSE:	The LOG operation in an arithmetic expression defined in your AHDL TDF cannot be resolved because the argument of LOG2 is a negative number. It is illegal to take the LOG2 of a negative number.

ACTION:	Change the argument of the LOG operation in the arithmetic expression to be non-negative.

See also:

MAX+PLUS II Messages

Message Format


Expressions to left of period (.) may be macrofunction or primitive variables only

CAUSE:	An expression on the left side of an equation is not a macrofunction or primitive. This message can occur if you enter a port name that contains more than one period (.). For example, the expression (A.q, B.q) is correct, but the expression (A.q, B.q).q is not.

ACTION:	Edit the expression.

See also:

MAX+PLUS II Messages

Message Format


End of comment character (%) is missing -- rest of file is treated as a comment

CAUSE:	You left out the closing percent symbol (%) for a comment, so all text up to the end of the file has been treated as a comment.

ACTION:	Insert a percent symbol at the end of the comment.

See also:

MAX+PLUS II Messages

Message Format


File contains multiple <text>

CAUSE:	You used more than one Subdesign Section or Title Statement in a TDF.

ACTION:	Remove all but one of the specified sections or statements.

See also:

MAX+PLUS II Messages

Message Format


Group <name> is missing brackets [ ]

CAUSE:	You left out the index brackets ([ ]) when you used a decimal group name in the Logic Section of a TDF.

ACTION:	Append the index brackets to the group name.

See also:

Defining Groups (AHDL)

Group Syntax (AHDL)

MAX+PLUS II Messages

Message Format


Group range expression cannot be negative

CAUSE:	You have used an arithmetic expression that defines a negative group range in your AHDL TDF. Group range expressions must be greater than or equal to zero.

ACTION:	Redefine the group range to be greater than or equal to zero.

See also:

MAX+PLUS II Messages

Message Format


Group <name> was redeclared with a different range

CAUSE:	You have redeclared a group in the Variable Section of a TDF using a different range than was used in a previous declaration of the same group in the Subdesign Section.

ACTION:	Change one of the declarations so that the group ranges are the same.

See also:

Defining Groups (AHDL)

Group Ranges & Subranges (AHDL)

MAX+PLUS II Messages

Message Format


Group LSB will be <name>, overrides BIT0 = MSB in Options Statement

CAUSE:	You listed the numbers in the range of a group declaration in descending order but specified Bit0 = MSB in an Options Statement of a TDF. The smallest number in the range will determine the LSB of the group.

ACTION:	Change the order of the numbers in the range. To use a descending range, remove the BIT0 option from the Options Statement or change it to Bit0 = ANY.

See also:

Defining Groups (AHDL)

Group Ranges & Subranges (AHDL)

MAX+PLUS II Messages

Message Format


Group MSB will be <name>, overrides BIT0 = LSB in Options Statement
Group MSB will be <name>, overrides default order of bits or BIT0 = LSB in Options Statement

CAUSE:	You listed the numbers in the range of a group declaration in ascending order but specified Bit0 = LSB in an Options Statement of a TDF, or did not specify the BIT0 option at all. The smallest number in the range will determine the MSB of the group.

ACTION:	Change the order of the numbers in the range. To use an ascending range, change the BIT0 option in the Options Statement to Bit0 = MSB or Bit0 = ANY.

See also:

Defining Groups (AHDL)

Group Ranges & Subranges (AHDL)

MAX+PLUS II Messages

Message Format


Group range <name><range> differs from declaration <name><range>

CAUSE:	You used a group range in an order different from that of the range you declared.

ACTION:	Ensure that the range you specify in the Logic Section of a TDF is the one you want. Otherwise, change the group range to correspond to the range declared in the Variable Section or Subdesign Section.

See also:

Defining Groups (AHDL)

Group Ranges & Subranges (AHDL)

MAX+PLUS II Messages

Message Format


Group range of stub <name> must be specified when using comma placeholders to left of period (.)
Group range of <name> must be specified when using comma placeholders to left of period (.)

CAUSE:	You did not specify a group range within brackets ([ ]) when you used a comma as a placeholder in a group of ports (before the period). For example, (m1, ).d[ ] is illegal. A group range is needed either before or after the period.

ACTION:	Enter a group range on either before or after the period.

See also:

Group Ranges & Subranges (AHDL)

MAX+PLUS II Messages

Message Format


Group range too large: <name><range>

CAUSE:	You declared a decimal group name with a range of numbers, one of which is greater than 32767.

ACTION:	Change the group declaration so that the highest number in the group range is 32767.

See also:

Defining Groups (AHDL)

Group Ranges & Subranges

MAX+PLUS II Messages

Message Format


Groups may not be assigned to nodes

CAUSE:	You assigned a group to a single node in a Boolean equation.

ACTION:	A group cannot be assigned to a single node--there is no room for the group members. Change the equation. If the left and right sides of an equation have groups of different sizes, the number of bits in the group on the left must be evenly divisible by the number of bits in the group on the right.

See also:

Boolean Equation Rules (AHDL)

Defining Groups (AHDL)

Group Ranges & Subranges (AHDL)

MAX+PLUS II Messages

Message Format


Groups must be of equal size, but one has <number> members and the other has <number>

CAUSE:	You used two groups of unequal size in an operation. This problem may occur if the width of a constant group on the right-hand side of an equation is larger than the group on the left-hand side of the equation, or if the width of a constant group in the body of a Truth Table Statement is different from the width of the corresponding variable in the header.

ACTION:	Ensure that the group sizes match. Decrease the value of a constant so that its binary representation has a width less than or equal to the width of the group used on the left-hand side of an equation (if the constant is binary, the sizes of the two groups must be equal). If necessary, use commas as placeholders, or add a zero to the beginning of the shorter group to fill the missing bits to the left with zeros, e.g., a[7..0] = (0, b[3..0]).

See also:

Boolean Equation Rules (AHDL)

Defining Groups (AHDL)

MAX+PLUS II Messages

Message Format


IF keyword that is paired with substituted text <text> of previous message is at line <number>

CAUSE:	The previous message reported that an END keyword was found where the END IF keywords were expected, and that the Compiler substituted the END IF keywords for the END keyword. This message reports the location of the IF keyword that is paired with the END IF keywords mentioned in the previous message.

ACTION:	Check the ELSE clause of the If Statement specified in this message if an unexpected end of file message is reported during subsequent processing. Be sure to not use the ELSE IF keywords where the ELSIF keyword is needed.

See also:

Defining Groups (AHDL)

MAX+PLUS II Messages

Message Format


Ignored all options except BIT0 in Options Statement -- other options are not supported

CAUSE:	You tried to compile a project containing an Options Statement with an option other than the BIT0 option. In MAX+PLUS II version 5.0 and higher, the BIT0 option is the only option supported in the Options Statement.

ACTION:	Use the Assign menu commands, the Floorplan Editor, and/or the ACF to enter all assignments for projects created with MAX+PLUS II version 5.0 and higher.

See also:

ACF Format

Changes to AHDL Support in MAX+PLUS II Version 5.0

Converting an Obsolete Assignment Format

MAX+PLUS II Messages

Message Format


Ignored Design Section -- it is not supported

CAUSE:	You tried to compile a project containing a Design Section. In MAX+PLUS II version 5.0 and higher, Design Sections are obsolete and are not supported.

ACTION:	Use the Assign menu commands, the Floorplan Editor, and/or the ACF to enter all assignments for projects created with MAX+PLUS II version 5.0 and higher.

See also:

ACF Format

Changes to AHDL Support in MAX+PLUS II Version 5.0

Converting an Obsolete Assignment Format

MAX+PLUS II Messages

Message Format


Ignored TDF <text> -- it contains no design information

CAUSE:	The specified TDF does not contain design logic, so the MAX+PLUS II Compiler has ignored it. This message can occur in MAX+PLUS II version 5.0 and higher if your project includes a TDF created with an earlier version of MAX+PLUS II that contained only resource and/or device assignments. MAX+PLUS II version 5.0 and higher automatically converts these assignments into the ACF format and comments out the old assignment information in the TDF.

ACTION:	Delete the TDF after verifying that it contains no useful design information.

See also:

ACF Format

Changes to AHDL Support in MAX+PLUS II Version 5.0

Converting an Obsolete Assignment Format

MAX+PLUS II Messages

Message Format


Illegal based number format: <text>

CAUSE:	You used a character other than B, O, Q, X, or H as a radix prefix or you omitted the digits of the number (e.g., B"").

ACTION:	Use the B, O, Q, X, or H prefixes for binary, octal, and hexadecimal numbers. Use no prefix for decimal numbers. Be sure not to omit the digits between quotes.

See also:

MAX+PLUS II Messages

Message Format

Numbers in AHDL

Using Numbers (AHDL)


Illegal digit <character> in numeric constant: <number>

CAUSE:	You used an illegal digit in a binary, octal, or hexadecimal number.

ACTION:	Change the digit to a legal one for the number. See Numbers in AHDL for a list of legal digits for each numbering system.

See also:

MAX+PLUS II Messages

Message Format

Using Numbers (AHDL)


Illegal don't care value <text> in add operation
 Illegal dont care value <text> in add operation

CAUSE	You used a constant with dont care (X) values as an operand in an add operation. Add operations will not work if any of the constants in the operation contain dont care values.

ACTION:	Use only fully defined values, i.e., values with no dont care bits, in add operations.

See also:

MAX+PLUS II Messages

Message Format


Illegal filename <text> in Include Statement

CAUSE:	You specified an illegal filename in the Include Statement of an AHDL TDF.

ACTION:	Edit the file to specify a legal Include File name. See Include Statement & Include File Rules for more information about filenames.

See also:

MAX+PLUS II Messages

Message Format


Illegal use of state machine variable <name>

CAUSE:	You used an AHDL state machine variable in a group operation or in an expression or equation where it was not assigned or compared to the value of a state.

ACTION:	State machine variables may only be used in assignments to or comparisons of state values. Ensure that you do not use state machine variables in any other way, and that you declare all states of the machine in the State Machine Declaration.

See also:

MAX+PLUS II Messages

Message Format

State Machines (AHDL)


Include Files may not be nested

CAUSE:	You used an Include Statement to include an Include File in the current file, but this Include File has an Include Statement that in turn includes another file.

ACTION:	Ensure that you do not have nested Include Statements. You can avoid this problem by placing only Function Prototypes and Constant Statements within Include Files.

See also:

MAX+PLUS II Messages

Message Format


Input pin <name> may not be assigned a value

CAUSE:	You used an input pin on the left side of an equation in a TDF, assigning it a value.

ACTION:	Ensure that all input pins are used as values on the right side of an equation.

See also:

Boolean Equations (AHDL)

Implementing Boolean Expressions & Equations (AHDL)

MAX+PLUS II Messages

Message Format

Ports (AHDL)


Input port <instance name>.<port name> may not be used as a value

CAUSE:	You used an input port as a value on the right side of an equation.

ACTION:	Ensure that all input ports, if used, are assigned values on the left sides of equations.

See also:

Boolean Equations (AHDL)

Implementing Boolean Expressions & Equations (AHDL)

MAX+PLUS II Messages

Message Format


Include File contains information other than Constant and Function Prototype Statements

CAUSE:	An Include File contains information other than Constant and Function Prototype Statements, which are the only types of information that are permitted in an Include File.

ACTION:	Move all information other than Constant and Function Prototype Statements to the TDF that includes the Include File.

See also:

MAX+PLUS II Messages

Message Format


Left side of equation may not contain <text>

CAUSE:	You used an illegal value on the left side of a Boolean equation of a TDF, i.e., something other than a symbolic name, group, or the NOT (!) operator.

ACTION:	Ensure that the left side of the equation contains only symbolic names, groups, or NOT (!) operators.

See also:

Boolean Equations (AHDL)

Implementing Boolean Expressions & Equations (AHDL)

Logical Operators

MAX+PLUS II Messages

Message Format


Logic option assignments are not allowed in Pin Connection Statements

CAUSE:	When MAX+PLUS II attempted to convert the resource and device assignments in your project to the ACF format, it found a logic option assigned to a node in the Pin Connection Statement of a TDF.

ACTION:	To successfully convert the TDF assignments into the ACF format, you must remove the logic option assignment from the Pin Connection Statement or move it to an Options Statement or a Resource Assignment Statement before choosing Convert Obsolete Assignment Format. You should use the Assign menu commands, the Floorplan Editor, and/or the ACF to enter all assignments for new projects.

See also:

Changes to AHDL Support in MAX+PLUS II Version 5.0

Converting an Obsolete Assignment Format

MAX+PLUS II Messages

Message Format


Machine node <name> may only be assigned to a machine

CAUSE:	A state machine port or state machine alias in a TDF has been assigned to something other than a MACHINE OUTPUT declared in the Subdesign Section, a MACHINE INPUT port of a macrofunction instance in the Variable Section, or a state machine alias.

ACTION:	Connect the machine node to a MACHINE OUTPUT declared in the Subdesign Section, a MACHINE INPUT port of a macrofunction instance in the Variable Section, or a state machine alias.

See also:

Machine Alias Declaration

MAX+PLUS II Messages

Message Format

State Machines (AHDL)


Macrofunction instance <text> requires and output port
Macrofunction instance <text> requires an output port

Output ports: <text>

CAUSE:	A Boolean expression in your project contains a macrofunction instance name that does not have an output port name appended to it.

ACTION:	Append a period (.) plus a port name to the macrofunction instance name. Use one of the port names specified in this message.

See also:

MAX+PLUS II Messages

Message Format


Mismatched table -- heading has more/less items than table row(s)

CAUSE:	The number of comma-separated items in a row of a TDF Truth Table Statement row is not equal to the number of comma-separated items in the heading (the first row).

ACTION:	Change the table so that each row has the same number of items. Use parentheses consistently.

See also:

MAX+PLUS II Messages

Message Format


Multiple assignments to machine node <name>

CAUSE:	A state machine MACHINE INPUT, a node, or a port of a macrofunction has been connected to more than one state machine. Only one such connection is allowed.

ACTION:	Only one of the assignments is meaningful; remove all others.

See also:

MAX+PLUS II Messages

Message Format

Ports (AHDL)

State Machines (AHDL)

State Machine Declaration (AHDL)


Nesting too deep

CAUSE:	You have nested too many Boolean expressions, Boolean equations, If Statements, and/or Case Statements in a TDF, causing logic that is too complex.

ACTION:	Remove one or more of the nested levels to simplify your project.

See also:

MAX+PLUS II Messages

Message Format


No Function Prototype for <macrofunction>

CAUSE:	You declared a variable of type <macrofunction> or used an in-line macrofunction reference in a TDF without including a Function Prototype of the macrofunction.

ACTION:	Ensure that you have a Function Prototype of each macrofunction you use. You can also use an Include Statement to include a Function Prototype that is in an Include File.

See also:

Creating & Using Custom Macrofunctions (AHDL)

MAX+PLUS II Messages

Message Format

Using Altera MAX+PLUS II Macrofunctions (AHDL)


Nodes may not be used <text>

CAUSE:	You used a single node as an arithmetic operand or in an arithmetic comparison in a TDF.

ACTION:	Use only groups with arithmetic operators and in arithmetic comparisons.

See also:

MAX+PLUS II Messages

Message Format


Number of bits in group on left side of equation must be evenly divisible by the number of bits on right
Number of bits in group on left side of equation must be evenly divisible by the number of bits in the group on the right, but one has <number> bits and the other has <number>

CAUSE:	A Boolean equation in your AHDL TDF includes a group on each side of the operator. If the left and right sides of an equation have groups of different sizes, the number of bits in the group on the left must be evenly divisible by the number of bits in the group on the right.

ACTION:	Make sure the number of bits in the group on the left is evenly divisible by the number of bits in the group on the right. If necessary, you can break up the group.

See also:

Boolean Equations (AHDL)

MAX+PLUS II Messages

Message Format


Numbers may not be assigned to nodes

CAUSE:	You assigned a number to a single node in a Boolean equation in a TDF. Numbers are always interpreted as groups, and groups may not be assigned to nodes.

ACTION:	Use VCC and GND instead of 0 and 1.

See also:

Implementing Boolean Expressions & Equations (AHDL)

MAX+PLUS II Messages

Message Format


Only INPUT and BIDIR ports may have default values

CAUSE:	You assigned a default value to an output port in the Logic Section of a TDF. Unlike input and bidirectional ports, output ports may not be assigned default values.

ACTION:	Remove the default value assignment.

See also:

MAX+PLUS II Messages

Message Format


Options Statements are not allowed in Pin Connection Statements

CAUSE:	When MAX+PLUS II attempted to convert the resource and device assignments in your project to the ACF format, it found an Options Statement included in a Pin Connection Statement of a TDF.

ACTION:	Remove the Options Statement from the Pin Connection Statement before choosing Convert Obsolete Assignment Format to successfully convert the TDF assignments into the ACF format. The Options Statement in pre-version 5.0 releases of MAX+PLUS II can be placed only within a Device Specification, between Device Specifications, or outside of other TDF sections. Use the Assign menu commands, the Floorplan Editor, and/or the ACF to enter all assignments for new projects.

See also:

Changes to AHDL Support in MAX+PLUS II Version 5.0

Converting an Obsolete Assignment Format

MAX+PLUS II Messages

Message Format


OUTPUT port <instance name>.<port name> may not be used as a value
Output port <instance name>.<port name> may not be assigned a value

CAUSE:	You used a macrofunction output port name on the left side of an equation, assigning it a value.

ACTION:	Ensure that all macrofunction output ports are used as values on the right sides of equations.

See also:

Boolean Equations (AHDL)

MAX+PLUS II Messages

Message Format


Pin and logic cell assignments are not allowed in <text>

CAUSE:	When MAX+PLUS II attempted to convert the resource and device assignments in your project to the ACF format, it found a node had been assigned to a pin or logic cell in a Clique Assignment Statement or a Pin Connection Statement of a TDF.

ACTION:	To successfully convert the TDF assignments into the ACF format, you must delete the pin or logic cell assignment or move it from the specified statement to a Resource Assignment Statement before choosing Convert Obsolete Assignment Format. You should use the Assign menu commands, the Floorplan Editor, and/or the ACF to enter all assignments for new projects.

See also:

Changes to AHDL Support in MAX+PLUS II Version 5.0

Converting an Obsolete Assignment Format

MAX+PLUS II Messages

Message Format


Port <name> is declared as an <text> when it should be an <text> for <name> primitive
Port <name> declared as an <text> when it should be an <text> for <name> primitive

CAUSE:	You redefined a primitive in a TDF, but declared an output port of the primitive as an input in the Function Prototype, i.e., you listed an output port after the FUNCTION keyword, or an input port after the RETURNS keyword.

ACTION:	Although you may redefine the order of signals in primitives, you must declare the outputs as outputs and the inputs as inputs. Make the necessary changes in the Function Prototype for the primitive.

See also:

MAX+PLUS II Messages

Message Format


Port <name> is declared more than once in Function Prototype <name>

CAUSE:	You used a symbolic name more than once for a port within a Function Prototype.

ACTION:	Change one of the port names. All symbolic names must be unique.

See also:

MAX+PLUS II Messages

Message Format


Port count for instance of <macrofunction> (<number>) does not agree with Function Prototype port count (<number>)

CAUSE:	You did not include the correct number of input and output port names in an equation with an in-line reference in a TDF.

ACTION:	In equations that contain in-line references, variables must have a one-to-one correspondence to the input and output ports of the Function Prototype. The variables in such equations must match the number and positions of the input and output ports of the Function Prototype, or commas must be used to hold the places of missing variables.

See also:

MAX+PLUS II Messages

Message Format


Right side of equation may not contain <text>

CAUSE:	You used an illegal value on the right side of a Boolean equation expression in a TDF.

ACTION:	Make sure the right side of the equation contains only values allowed in Boolean Expressions.

See also:

Implementing Boolean Expressions & Equations

MAX+PLUS II Messages

Message Format

Reserved AHDL Keywords


Rounded non-integer result of LOG2 up to next whole number

CAUSE:	The LOG operation in an arithmetic expression defined in your AHDL TDF does not result in an integer. Since there is a remainder, MAX+PLUS II will round the result to the next highest integer.

ACTION:	If you wish to avoid this warning message in the future, modify the arithmetic expression to make the LOG operation result in an integer.

See also:

MAX+PLUS II Messages

Message Format


Size of WHEN group different from CASE group

CAUSE:	The number of bits in the WHEN group is different from the number of bits in the CASE group of a TDF Case Statement. These groups are compared, so they must be the same size.

ACTION:	Make sure that these two groups are equal.

See also:

Implementing Conditional Logic (AHDL)

MAX+PLUS II Messages

Message Format


State <name> of state machine <name> has no transitions

CAUSE:	You did not provide any transitions out of the specified state in the specified state machine.

ACTION:	If you do not wish to leave the state machine in the specified state, you should assign a different state to the state machine variable. If you do wish to leave the state machine in the specified state, no action is required. You can avoid this warning message in the future by adding a transition that always returns to the same state. You may also wish to add a comment to the file to indicate that the machine should remain in the specified state indefinitely.

See also:

MAX+PLUS II Messages

Message Format

Specifying State Transitions (AHDL)

State Machine Declaration (AHDL)


State bit <name> of state machine <name> may not be assigned a value

CAUSE:	You assigned a value to one or more state bits in a TDF State Machine Declaration. Only states may be assigned values, not bits.

ACTION:	Change the State Machine Declaration.

See also:

Assigning State Machine Bits & Values (AHDL)

MAX+PLUS II Messages

Message Format


State machine Case Statements may not have groups in their WHEN clauses

CAUSE:	You used a list of states enclosed in parentheses in the WHEN clause of a state machine Case Statement. A list of states is not a group, and parentheses are used only to delimit groups.

ACTION:	Remove the parentheses.

See also:

MAX+PLUS II Messages

Message Format

State Machines (AHDL)


State value <value> has more significant bits than declared state bits

CAUSE:	The numerical value assigned to a state in the State Machine Declaration of a TDF has more significant bits than declared state bits. You may have entered a binary string in the wrong radix (e.g., you may have entered 110 or H "110" instead of B"110").

ACTION:	Check your TDF for errors. If you would like to get rid of the warning, you may have to declare dummy state bits so that the number of declared state bits is greater than or equal to the number of significant bits in the numerical value.

See also:

MAX+PLUS II Messages

Message Format

State Machines (AHDL)


States of input state machines may not be assigned a value

CAUSE:	You have assigned a value to a state name. State names are constants.

ACTION:	To make a state transition, assign a state name to the name of the state machine.

See also:

MAX+PLUS II Messages

Message Format

Specifying State Transitions (AHDL)


Subdesign already specified in another design file

CAUSE:	The Compiler found a design file that contains a behavioral description and has the same name as a TDF, which also contains a behavioral description (in the Subdesign and Logic Sections). This logic duplication is not allowed. This message may occur if you change to use a different type of design file to contain part of your projects logic.

ACTION:	Check the Hierarchy Display window. If the leftmost file icon for a filename shows a different type of design file than you planned to use, change the file type with Change File Type. Otherwise, remove the sections from the TDF or change the name of the TDF.

See also:

Changing the File Type

MAX+PLUS II Messages

Message Format


Subdesign name <name> must be the same as the filename <filename>

CAUSE:	The name of a TDF subdesign and the name of the file in which it resides are different.

ACTION:	The TDF name and the subdesign name must be the same. Make sure the subdesign name declared in the Subdesign Section is both a legal subdesign name and legal filename.

See also:

MAX+PLUS II Messages

Message Format

Quoted & Unquoted Names (AHDL)


Subdesign and Logic Sections missing from design file

CAUSE:	You tried to compile a TDF that does not contain Subdesign and Logic Sections.

ACTION:	Make sure that a Subdesign Section and Logic Section are in the file. You should not place them in an Include File.

See also:

MAX+PLUS II Messages

Message Format


Substituted <text> with <text>
Substituted <text> for <text>

CAUSE:	The Compiler determined that the second <text> in a TDF was erroneous, so it substituted the first <text>. This message may occur if you entered a keyword incorrectly. For example, you may have typed ELSEIF or ELSE IF instead of ELSIF. The first <text> shows the correct form of the keyword.

ACTION:	Although the Compiler substitutes the correct keyword internally, you should enter the correction in your TDF.

See also:

AHDL Syntax

MAX+PLUS II Messages

Message Format


Symbolic name <name> already declared [<text>]

CAUSE:	You declared the same symbolic name in a TDF more than once, or used a reserved keyword for a symbolic name.

ACTION:	Make sure each symbolic name is unique and make sure all symbolic names are not reserved keywords.

See also:

MAX+PLUS II Messages

Message Format

Quoted & Unquoted Names (AHDL)

AHDL Reserved Keywords


Symbolic name <name> does not have ports

CAUSE:	You used a symbolic name that had a port name appended to it in a TDF, but the name was not declared as a variable of type <primitive> or <macrofunction>, or as a state machine variable. Only these variables have ports.

ACTION:	Change the symbolic name to one of these variable types or remove the period and port name from the symbolic name.

See also:

MAX+PLUS II Messages

Message Format


Symbolic name <name> is not a port of <name>

[Input ports: <names>]

[Output ports: <names>]

CAUSE:	You used a symbolic name in a TDF as a port of a primitive, macrofunction, or state machine, but the port does not exist. You may have used an incorrect pinstub name.

ACTION:	Change the name of the port to one in the lists of input and output ports that accompany this message.

See also:

MAX+PLUS II Messages

Message Format


Symbolic name <name> is not a state of state machine <name>

CAUSE:	You used a symbolic name in a TDF as a state name, but did not declare it.

ACTION:	Add the name to the State Machine Declaration or change the name to a state you have declared.

See also:

MAX+PLUS II Messages

Message Format

State Machines (AHDL)


Symbolic name <name> was declared as a Function Prototype, not a variable

CAUSE:	You used the name of a macrofunction in the project as a variable in the Logic Section of a TDF.

ACTION:	Change the symbolic name. Remember to declare variables of type <macrofunction> in your Variable Section for each instance of a macrofunction, or use in-line references. Do not use the macrofunction name as a variable.

See also:

Implementing a Hierarchical Project (AHDL)

MAX+PLUS II Messages

Message Format


Symbolic name <name> was declared but never used

CAUSE:	You declared a variable or input pin but never used it in the Logic Section of a TDF.

ACTION:	Either use the variable or input somewhere in your project or remove it from the Subdesign or Variable Section.

See also:

MAX+PLUS II Messages

Message Format


Symbolic name <name> was not <text>

CAUSE:	The <text> of this message indicates that you used a symbolic name in the Logic Section that you did not declare or define, or used a variable as a group that you had already declared as a single node.

ACTION:	If the message refers to an undeclared or undefined symbolic name, make sure that all symbolic names are declared or defined before being used. If the message refers to a group, change the declaration to make the symbolic name a group rather than a node, or change the group in the Logic Section to a node.

See also:

MAX+PLUS II Messages

Message Format


Truncated result of division with non-zero remainder

CAUSE:	The division in an arithmetic expression defined in your AHDL TDF does not result in an integer. MAX+PLUS II will truncate the remainder.

ACTION:	If you wish to avoid this warning message in the future, modify the arithmetic expression to make the division result in an integer.

See also:

MAX+PLUS II Messages

Message Format


AHDL Elements
Elements

Reserved Keywords

Reserved Identifiers

Symbols

Quoted & Unquoted Names

Groups

Group Ranges & Subranges

Numbers in AHDL

Arithmetic Expressions

Boolean Expressions

Logical Operators

Expressions Using NOT

Expressions Using AND, NAND, OR, NOR, XOR, and XNOR

Arithmetic Operators in Boolean Expressions

Comparators

Boolean Operator & Comparator Priorities

Primitives

Primitive/Port Interconnections

Primitive Interconnections

Macrofunctions

Megafunctions (???link)

Ports


Reserved Keywords (AHDL)
Reserved Keywords

Reserved keywords are used for beginnings, endings, and transitions of AHDL statements and for the predefined constant values GND and VCC.

Reserved keywords differ from reserved identifiers in that keywords can be used as symbolic names when they are enclosed in single quotation marks ('), whereas reserved identifiers cannot. Both reserved keywords and reserved identifiers can be used freely in comments.

Altera recommends that you enter all keywords in capital letters for easy readability. See AHDL & VHDL Style Guide for more information.

To obtain context-sensitive help on an AHDL keyword, make sure the TDF is saved with the extension .tdf. While the file is open in a Text Editor window, you can press Shift+F1 and click Button 1 on the keyword, or choose the context-sensitive help button in the toolbar ( [image]).

The following list shows all AHDL reserved keywords:

AND	FUNCTION	OUTPUT

ASSERT	GENERATE	PARAMETERS

BEGIN	GND	REPORT

BIDIR	HELP_ID	RETURNS

BITS	IF	SEGMENTS

BURIED	INCLUDE	SEVERITY

CASE	INPUT	STATES

CLIQUE	IS	SUBDESIGN

CONNECTED_PINS	LOG2	TABLE

CONSTANT	MACHINE	THEN

DEFAULTS	MOD	TITLE

DEFINE	NAND	TO

DESIGN	NODE	TRI_STATE_NODE

DEVICE	NOR	VARIABLE

DIV	NOT	VCC

ELSE	OF	WHEN

ELSIF	OPTIONS	WITH

END	OR	XNOR

FOR	OTHERS	XOR

See also:

Getting Context-Sensitive Help for AHDL Operators, Comparators, Keywords & Identifiers

Symbols


Reserved Identifiers (AHDL)
Reserved Identifiers

Reserved identifiers are names that are reserved for special use within AHDL, and may not be defined by the user.

Reserved identifiers differ from reserved keywords in that keywords can be used as symbolic names when they are enclosed in single quotation marks ('), whereas reserved identifiers cannot. Both reserved keywords and reserved identifiers can be used freely in comments.

To obtain context-sensitive help on an AHDL identifier, make sure the TDF is saved with the extension .tdf. While the file is open in a Text Editor window, you can press Shift+F1 and click Button 1 on the identifier, or choose the context-sensitive help button in the toolbar ( [image]).

The following list shows all AHDL reserved identifiers.

CARRY	JKFFE	SRFFE

CASCADE	JKFF	SRFF

CEIL	LATCH	TFFE

DFFE	LCELL  	TFF

DFF	MCELL	TRI

EXP	MEMORY	WIRE

FLOOR	OPENDRN	X

GLOBAL  	SOFT

See also:

Getting Context-Sensitive Help for AHDL Operators, Comparators, Keywords & Identifiers

Symbols


Symbols (AHDL)
Symbols

he symbols listed below have predefined meanings in AHDL. This list includes symbols that are used as operators and comparators in Boolean expressions and as operators in arithmetic expressions.

Symbol:	Function:

_	(underscore)	User-defined identifiers used as legal characters in symbolic names.

-	(dash)

--	(two dashes)	Starts a VHDL-style comment, which extends to the end of the line. (Go to Comments & Documentation for more information.)

%	(percent)	Encloses AHDL-style comments. (Go to Comments & Documentation for more information.)

( )	(left & right parentheses)	Enclose and define sequential group names.

Enclose pin names in Subdesign Sections and Function Prototype Statements.

Optionally enclose inputs and outputs of truth tables in Truth Table Statements.

Enclose bitsand states of State Machine Declarations.

Enclose highest priority operations in Boolean and arithmetic expressions.

Enclose parameter definitions in Parameters Statements and parameter names in Function Prototype Statements and in-line references

Optionally enclose the condition in an Assert Statement.

Enclose the arguments of evaluated functions in Define Statements.

[ ]	(left & right brackets)	Enclose the  range of a single-  or dual-range group name.

'...' 	(single quotation marks)	Enclose quoted symbolic names.

"..."	(double quotation marks)	Enclose strings in Title Statements, Parameters Statements, and Assert Statements.

Enclose a filename in Include Statements.

Enclose digits in non-decimal numbers.

.	(period)	Separates symbolic names of logic function variables from port names.

Separates extensions from filenames.

..	(ellipsis)	Separates MSB from LSB in ranges.

;	(semicolon)	Ends AHDL statements and sections.

,	(comma)	Separates members of sequential groups and lists.

:	(colon)	Separates symbolic names from types in declarations.

=	(equals)	Assigns default GND and VCC values to inputs in a Subdesign Section.

Assigns settings to options in an Options Statement.

Assigns a default value to a parameter in a Parameters Statement  or an in-line reference .

Assigns values to state machine states.

Assigns values in Boolean equations.

Connects a signal to a port in an in-line reference that uses named port association.

=>	(arrow)	Separates inputs from outputs in Truth Table Statements.

Separates WHEN clauses from Boolean expressions in Case Statements.

+	(plus)	addition operator

-	(minus)	subtraction operator

== 	(two equal signs)	numeric or string equality operator

! 	(exclamation point)	NOT operator

!=	(exclamation equals)	not equal to operator

>	(greater than)	greater than comparator

>=	(greater than equals)	greater than or equal to comparator

<	(less than)	less than comparator

<=	(less than equals)	less than or equal to comparator

&	(ampersand)	AND operator

!&	(exclamation ampersand)	NAND operator

$	(dollar sign)	XOR operator

!$	(exclamation dollar)	XNOR operator

#	(pound sign)	OR operator

!#	(exclamation pound)	NOR operator

?	(question mark)	ternary operator

See also:

Arithmetic Expressions

Arithmetic Operators in Boolean Expressions

Boolean Equations

Comparators

Logical Operators

Reserved Identifiers

Reserved Keywords


Quoted & Unquoted Names (AHDL)
Quoted & Unquoted Names

Three types of names exist in AHDL:

Symbolic names are user-defined identifiers in AHDL. They are used to name the following parts of a TDF:

-	Internal and external nodes and groups

-	Constants

-	State machine variables, state bits, and state names

-	Instances

-	Parameters

-	Memory segments

-	Evaluated functions

-	Named operators

Subdesign names are user-defined names for lower-level design files. The subdesign name must be the same as the TDF filename.

Port names are symbolic names that identify the input or output of a logic function.

Compiler-generated names that contain the tilde (~) character may appear in the Fit File for a project. If you back-annotate the Fit File assignments, these names will then appear in the project’s ACF. The tilde character is reserved for Compiler-generated names only; you cannot use it in your own pin, node, and group (bus) names.

Two notations are available for subdesign, symbolic, and port names: quoted and unquoted. Quoted names are enclosed in single quotation marks ('); unquoted names are not.

When you create a default symbol for a TDF that includes quoted port names, the quotes are not included in the pinstub names shown in the symbol.

Subdesign, symbolic, and port names have the following characteristics:

Legal	Unquoted	Quoted	Unquoted	Quoted	Unquoted	Quoted

Name	Subdesign	Subdesign	Symbolic	Symbolic	Port	Port

Characters   Note (1)	Name	Name	Name	Name	Name	Name

A-Z

a-z

0-9

Underscore (_)

Slash (/)	No	No

Dash (-)	No	No	No

Digits only (0-9)	No

Keyword	No	No	No

Identifier	No	No	No	No

Max. Characters	32	32	32	32	32	32

Examples: Unquoted symbolic names

Examples: Quoted Symbolic Names

See also:

Reserved Keywords

Reserved Identifiers


Note 1
The delimiters of ranges in single-range and double-range group names can also include the operators described in Arithmetic Expressions.


Unquoted Symbolic Name Examples
Legal unquoted symbolic names:

a     /a1

Illegal unquoted symbolic names:

-foo     node    55


Quoted Symbolic Name Examples
Legal quoted symbolic names:

'-bar'    'table'    '1221'

Illegal quoted symbolic names:

'bowling4$'    'a_name_with_more_than_32_characters'

'has a space'


Groups (AHDL)
Groups

Symbolic names and ports of the same type may be declared and used as groups in Boolean expressions and equations.

A group, which can include up to 256 members (or "bits"), is treated as a collection of nodes and acted upon as a single unit.

Groups in the Logic Section or Variable Section of a TDF can consist of nodes. Single nodes and the constants GND and VCC may be duplicated to form groups in Boolean expressions and equations.

Groups can be declared with the following three notations:

1.	A single-range group name consists of a symbolic name or port name followed by a single range of numbers enclosed in brackets, e.g., a[4..1]. The symbolic or port name, together with the longest number in the range, can contain up to 32 name characters. Example

Once a group has been defined, [] is a shorthand way of specifying the entire range. Example

A single number can be used in place of a range, e.g., a[5]. However, this notation signifies a single symbolic name, not a group, and is equivalent to the name a5.

2.	A dual-range group name consists of a symbolic name or port name followed by two ranges enclosed in brackets, e.g., d[6..0][2..0]. The symbolic or port name, together with the longest number in each range, can contain up to 32 name characters. Example

The dual-range group notation is useful for specifying groups of buses and for designs with two-dimensional topologies. Once a group has been defined, [][] is a shorthand way of specifying both ranges. Example

An individual node within the group can be referenced as name[y][z] or namey_z, where y and z are numbers in the group ranges.

3.	A sequential group name consists of a list of symbolic names, ports, or numbers, separated by commas and enclosed in parentheses, e.g., (a, b, c). Single- and dual-range group names can be listed within the parentheses. Example

This notation is useful for specifying port names. Example

The following two sets of examples show two groups specified with different notations:

b[5..0]

(b5, b4, b3, b2, b1, b0)

b[]

b[log2(256)..1+2-1]

b[2^8..3 mod 1]

b[2*8..8 div 2]

Compiler-generated names that contain the tilde (~) character may appear in the Fit File for a project. If you back-annotate the Fit File assignments, these names will then appear in the project’s ACF. The tilde character is reserved for Compiler-generated names only; you cannot use it in your own pin, node, and group (bus) names.

See also:

Boolean Equations

Boolean Expressions

Defining Groups

Group Ranges & Subranges

Logic Section

Quoted & Unquoted Names


Example:Group 1
a[4..1] can also be denoted by a[].

b[6..0][3..2] can also be denoted by b[][].


Example:Group 2
(a, b, c[5..1]) is a legal group.


Example:Group 3
The input ports of variable reg of type DFF can be written as reg.(d, clk, clrn, prn).


Example Group 5
[2*2..2-1] is a legal range.

The group range in the name q[MAX..0] is legal if the constant MAX has been defined previously in a Constant Statement.


Example Group 4
a[4..1]	is a group with members a4, a3, a2, and a1.

d[B"10"..B"00"]	is a group with members d2, d1, and d0.

b[2*2..2-1]	is a group with members b4, b3, b2, and b1. The group range delimiters are defined with arithmetic expressions.

q[MAX..0]	is a legal group if the constant MAX has been previously defined in a Constant Statement.

c[MIN(a,b)..0]	is a legal group if the evaluated function MIN has been previously defined in a Define Statement.


Example Group DR
The dual-range group a[4..2][3..1] is equivalent to the following groups:

(a4_[3..1], a3_[3..1], a2_[3..1])

(a4_3, a4_2, a4_1, a3_3, a3_2, a3_1, a2_3, a2_2, a2_1, a1_3, a1_2, a1_1)


Group Ranges & Subranges (AHDL)
Group Ranges & Subranges

Ranges of single-  or dual-range group names can consist of numbers or arithmetic expressions that are separated by two periods (..) and enclosed in brackets []. Example

Regardless of whether a range delimiter is a number or an arithmetic expression, the Compiler resolves and interprets the delimiters as decimal values (integers).

Subranges include a subset of the nodes specified in a declared group, and can be specified in a number of ways. Commas can be used as placeholders only in groups on the left side of a Boolean equation or in an in-line reference. Example

Ranges are normally listed in descending order. To list ranges in ascending order or in both ascending and descending order, you must specify the BIT0 option with the Options Statement to prevent the Compiler from issuing warning messages. In dual-range group names, the BIT0 option affects both of the ranges.

See also:

Defining Groups

Groups

Numbers in AHDL

Using Constants


Example:Group 5
If you declare the group c[5..1], you can use the following subranges of this group:

c[3..1]

c[4..2]

c4

c[5]

(c2, , c4)

In the subrange (c2, , c4), a comma is used to hold the place of an unassigned group member.


Arithmetic Expressions (AHDL)
Arithmetic Expressions

Arithmetic expressions can be used to define evaluated functions in Define Statements, constants in Constant Statements, and as the delimiters of group ranges. Example

The arithmetic operators and comparators used in these expressions perform basic arithmetic and comparison operations on the numbers used in the expression. The following arithmetic operators and comparators are used in AHDL arithmetic expressions:

Operator/	Example:	Description:	Priority:

Comparator:

+ (unary)	+1	positive	1

- (unary)	-1	negative	1

!	!a	NOT	1

^	a ^ 2	exponent	1

MOD	4 MOD 2	modulus	2

DIV	4 DIV 2	division	2

*	a * 2	multiplication	2

LOG2	LOG2(4-3)	logarithm base2	2

+	1+1	addition	3

-	1-1	subtraction	3

== (numeric)	5 == 5	numeric equality	4

== (string)	"a" = "b" 	string equality	4

!=	5 != 4	not equal to	4

>	5 > 4	greater than	4

>=	5 >= 5	greater than or equal to	4

<	a < b+2	less than	4

<=	a <= b+2	less than or equal to	4

&	a & b	AND	5

AND	a AND b

!&	1 !& 0	NAND (AND inverter)	5

NAND	1 NAND 0

$	1 $ 1	XOR (exclusive OR)	6

XOR	1 XOR 1

!$	1 !$ 1	XNOR (exclusive NOR)	6

XNOR	1 XNOR 1

#	a # b	OR	7

OR	a OR b

!#	a !# b	NOR (OR inverter)	7

NOR	a NOR b

?	(5<4) ? 3:4	ternary	8

The unary plus (+) and minus (-) are prefix operators. The + operator does not affect its operand, but you may use it for documentation purposes (i.e., to indicate a positive number).

The predefined evaluated functions CEIL and FLOOR can also be used in arithmetic expressions. The ceiling (CEIL) of a real number is the smallest integer that is at least that real number; the floor (FLOOR) is the largest integer that is at most that real number. Although these operation apply to all arithmetic expressions, they are meaningful only for LOG2 and DIV operations in which the result can be a real number. The ceiling or floor is obtained by enclosing the expression in parentheses and prepending CEIL or FLOOR to it. Example

The following rules apply to all arithmetic expressions:

Arithmetic expressions must resolve to non-negative numbers.

When the result of LOG2 is not an integer, the result is automatically rounded up to the next integer. Example

The arithmetic operators that are supported in arithmetic expressions are a superset of the arithmetic operators supported in Boolean expressions, which are described in Arithmetic Operators in Boolean Expressions.

See also:

Numbers in AHDL


Example: Group6
Range defined with an arithmetic expression:

SUBDESIGN foo

(

a[4..2+1-3+8] : INPUT;

)

Constant defined with an arithmetic expression:

CONSTANT foo = 1 + 2 DIV 3 + LOG2(256);

Evaluated function defined with an arithmetic expression:

DEFINE MIN(a,b) = ((a < b) ? a : b);


Example: Ceiling/Floor
Ceiling of a real number:

CEIL(LOG2(255)) = 8

Floor of a real number:

FLOOR(LOG2(255)) = 7


Example: Group7
LOG2(257) = 9


Numbers (AHDL)
Numbers in AHDL

You can use decimal, binary, octal, and hexadecimal numbers in any combination in AHDL. The syntax for each radix (numbering system) is shown below.

Radix:	Values:

Decimal	<series of digits 0 to 9>

Binary	B"<series of 0’s, 1’s, X’s>"

(where X = "don’t care")

Octal	O"<series of digits 0 to 7>" or

Q"<series of digits 0 to 7>"

Hexadecimal	X"<series from 0 to 9, A to F>" or

H"<series from 0 to 9, A to F>"

The following examples show valid AHDL numbers:

B"0110X1X10"

Q"4671223"

H"123AECF"

The following rules apply to AHDL numbers:

The MAX+PLUS II Compiler always interprets numbers in Boolean Expressions as groups of binary digits; numbers in group ranges are interpreted as decimal values.

Numbers cannot be assigned to single nodes in Boolean equations. Use VCC and GND instead.

See also:

Boolean Equations

Boolean Expressions

Using Numbers


Boolean Expressions (AHDL)
Boolean Expressions

Boolean expressions consist of operands that are separated by logical and arithmetic operators and comparators, and are optionally grouped within parentheses. Expressions are used in Boolean equations as well as in other statements such as Case and If Then Statements.

A Boolean expression may be one of the following:

An operand

Examples:   a, b[5..1], 7, VCC

An in-line logic function reference

A prefix operator (! or -) applied to a Boolean expression

Example:   !c

Two Boolean expressions separated by a binary (non-prefix) operator

Example:   d1 $ d3

A Boolean expression enclosed in parentheses

Example:   (!foo & bar)

The result of every Boolean expression has the same width as its operands.

You can name Boolean operators and comparators in AHDL files to make it easy to enter resource assignments and to interpret the Equations Section of the Report File. For more information, go to Naming a Boolean Operator or Comparator.

See also:

Arithmetic Operators in Boolean Expressions

Boolean Operator & Comparator Priorities

Boolean Equation Rules

Boolean Equations Description

Comparators

Defining Groups

Function Prototype Statement

Implementing Boolean Expressions & Equations

In-Line Logic Function Reference

Logical Operators


Logical Operators (AHDL)
Logical Operators

The following logical operators can be used in Boolean expressions:

Operator:	Example:	Description:

!	!tob	one’s complement (prefix inverter)

NOT	NOT tob

&	bread & butter	AND

AND	bread AND butter

!&	a[3..1] !& b[5..3]	AND inverter

NAND	a[3..1] NAND b[5..3]

#	trick # treat	OR

OR	trick OR treat

!#	c[8..5] !# d[7..4]	OR inverter

NOR	c[8..5] NOR d[7..4]

$	foo $ bar	exclusive OR

XOR	foo XOR bar

!$	x2 !$ x4	exclusive NOR

XNOR	x2 XNOR x4

Each operator represents a two-input logic gate, except the NOT (!) operator, which is a prefix inverter on a single node. You can use either the name or the symbol to represent a logical operator.

Expressions that use these operators are interpreted differently, depending on whether the operands are single nodes, groups, or numbers. Also, expressions with the NOT operator are interpreted differently from those with other logical operators.

You can name Boolean operators and comparators in AHDL files to make it easy to enter resource assignments and to interpret the Equations Section of the Report File (.rpt). For more information, go to Naming a Boolean Operator or Comparator.

If you turn on the Use LPM for AHDL Operators logic option, the Compiler replaces AND operators in Boolean expressions with the lpm_add_sub function.

See also:

Arithmetic Operators in Boolean Expressions

Assigning an Individual Logic Option or Synthesis Style

Boolean Equation Syntax

Boolean Equations Description

Boolean Expressions Using AND, NAND, OR, NOR, XOR, and XNOR

Boolean Expressions Using NOT

Comparators

Implementing Boolean Expressions & Equations

Naming a Boolean Operator or Comparator

Numbers in AHDL


Boolean Expressions Using NOT (AHDL)
Boolean Expressions Using NOT

The NOT operator is a prefix inverter. The behavior of the NOT operator depends on the operand that it affects.

Three operand types can be used with the NOT operator:

If the operand is a single node, GND, or VCC, a single inversion operation is performed. Example

If the operand is a group of nodes, every member of the group passes through an inverter. Example

If the operand is a number, it is treated as a binary number with as many bits as the group context in which it is used, and every bit is inverted. Example

See also:

Boolean Expressions Using AND, NAND, OR, NOR, XOR, and XNOR

Implementing Boolean Expressions & Equations

Logical Operators

Naming a Boolean Operator or Comparator


Example:Operands 1
!a means that the signal a passes through an inverter


Example:Operands 2
The group !a[4..1] is interpreted as (!a4, !a3, !a2, !a1).


Example:Operands 3
!9 in a four-member group context is interpreted as !B"1001", which is the same as B"0110".


Boolean Expressions Using AND, NAND, OR, NOR, XOR, and XNOR (AHDL)
Boolean Expressions Using AND, NAND, OR, NOR, XOR, and XNOR

Five operand combinations exist with the binary (non-prefix) operators. Each of these combinations is interpreted differently:

If both operands are single nodes or the constants GND or VCC, the operator performs the logical operation on the two elements. Example

If both operands are groups of nodes, the operator acts upon the corresponding nodes of each group, producing a bitwise set of operations between the groups. The groups must be the same size. Example

If one operand is a single node, GND, or VCC, and the other operand is a group of nodes, the single node or constant is duplicated to form a group of the same size as the other operand. The expression is then treated as a group operation. Example

If both operands are numbers, the shorter number is sign-extended to match the size of the other number. The expression is then treated as a group operation. Example

If one operand is a number and the other is a node or group of nodes, the number is truncated or sign-extended to match the size of the group. If any significant bits are truncated, an error message is generated. The expression is then treated as a group operation. Example

An expression that uses VCC as an operand is interpreted differently from an expression that uses 1 as an operand. Example

See also:

Boolean Expressions Using NOT

Implementing Boolean Expressions & Equations

Logical Operators

Naming a Boolean Operator or Comparator


Example:Operands 4
(a & b)


Example:Operands 5
(a, b, c) # (d, e, f) is interpreted as (a # d, b # e, c # f)


Example:Operands 6
a & b[4..1] is interpreted as (a & b4, a & b3, a & b2, a & b1)


Example:Operands 7
In the expression (3 # 8), the 3 and 8 are converted to the binary numbers B"0011" and B"1000", respectively. The expression then becomes B"1011".


Example:Operands 8
In the expression (a, b, c) & 1, the 1 is converted to B"001" and the expression becomes (a, b, c) & (0, 0, 1). The expression is then interpreted as (a & 0, b & 0, c & 1).


Example:Operands 9
In the first equation, the number 1 is sign-extended to match the size of the group. In the second equation, the node VCC is duplicated to form a group of the same size. Each equation is then treated as a group operation.

(a, b, c) & 1   = (0, 0, c)

(a, b, c) & VCC = (a, b, c)


Arithmetic Operators in Boolean Expressions (AHDL)
Arithmetic Operators in Boolean Expressions

Arithmetic operators are used to perform arithmetic addition and subtraction operations on groups and numbers in AHDL Boolean expressions. The following arithmetic operators are used in Boolean expressions:

Operator:	Example:	Description:

+ (unary)	+1	positive

- (unary)	-a[4..1]	negative

+	count[7..0] + delta[7..0]	addition

-	rightmost_x[] - leftmost_x[]	subtraction

The unary plus (+) and minus (-) are prefix operators. The + operator does not affect its operand, but you may use it for documentation purposes (i.e., to indicate a positive number). The - operator interprets its operand as a binary representation of a number if it is not already a number. It then performs a two’s complement unary-minus operation on the operand.

The following rules apply to the other arithmetic operators:

Operations are performed between two operands, which must be groups of nodes or numbers.

If both operands are groups of nodes, the groups must be the same size.

If both operands are numbers, the shorter number is sign-extended to match the size of the other operand.

If one operand is a number and the other is a group of nodes, the number is truncated or sign-extended to match the size of the group. If any significant bits are truncated, the MAX+PLUS II Compiler generates an error message.

1.	When you add two groups together on the right side of a Boolean equation with the + operator, you can place a 0 on the left of each group to sign-extend the width of the group. This method provides an extra bit of information to the group on the left side of the equation that can be used as a carry-out signal. Example

2.	You can name Boolean operators and comparators in AHDL files to make it easy to enter resource assignments and to interpret the Equations Section of the Report File. For more information, go to Naming a Boolean Operator or Comparator.

3.	The arithmetic operators that are supported in Boolean expressions are a subset of the arithmetic operators supported in arithmetic expressions.

See also:

Boolean Operator & Comparator Priorities

Boolean Equation Syntax

Boolean Equations Description

Boolean Expressions

Comparators

Implementing Boolean Expressions & Equations

Logical Operators

Numbers in AHDL


Example:Operands 1
In the following example, the groups count[7..0] and delta[7..0] are sign-extended with zeros to provide information to the cout carry-out signal:

(cout, answer[7..0]) = (0, count[7..0]) + (0, delta[7..0])


Comparators (AHDL)
Comparators

Two types of comparators are used to compare single nodes or groups: logical and arithmetic. The following comparators can be used in Boolean expressions.

Comparator:	Example:	Description:

==	(logical)	addr[19..4] == B"B800"	equal to

!=	(logical)	b1 != b3	not equal to

< 	(arithmetic)	fame[] < power[]	less than

<=	(arithmetic)	money[] <= power[]	less than or equal to

>	(arithmetic)	love[] > money[]	greater than

>=	(arithmetic)	delta[] >= 0	greater than or equal to

Logical comparators can compare single nodes, groups of nodes, and numbers without "don’t care" (X) values. If groups of nodes or numbers are compared, the groups must be the same size. The MAX+PLUS II Compiler performs a bitwise comparison on the groups, returning VCC when the comparison is true and GND when the comparison is false.

Arithmetic comparators may only compare groups of nodes and numbers, and the groups must be the same size. The Compiler performs an unsigned magnitude comparison on the groups; that is, each group is interpreted as a positive binary number and compared to the other group.

If you turn on the Use LPM for AHDL Operators logic option (???link???), the Compiler replaces comparators in Boolean expressions with the lpm_compare function.

See also:

Arithmetic Expressions

Arithmetic Operators in Boolean Expressions

Assigning an Individual Logic Option or Synthesis Style

Boolean Equation Syntax

Boolean Equations Description

Boolean Operator & Comparator Priorities

Groups

Implementing Boolean Expressions & Equations

Logical Operators

Numbers in AHDL


Boolean Operator & Comparator Priorities (AHDL)
Boolean Operator & Comparator Priorities

Operands separated by logical and arithmetic operators and comparators are evaluated according to the priority rules listed below (priority 1 is the highest priority). Operations of equal priority are evaluated from left to right. Parentheses () may change the order of evaluation.

Priority:	Operator/Comparator:

1	- 	(negative)

1	! 	(NOT)

2	+ 	(addition)

2	- 	(subtraction)

3	== 	(equal to)

3	!= 	(not equal to)

3	< 	(less than)

3	<= 	(less than or equal to)

3	> 	(greater than)

3	>= 	(greater than or equal to)

4	& 	(AND)

4	!& 	(NAND)

5	$ 	(XOR)

5	!$ 	(XNOR)

6	# 	(OR)

6	!# 	(NOR)

The arithmetic operators that are supported in Boolean expressions are a subset of the arithmetic operators supported in arithmetic expressions.

See also:

Arithmetic Operators in Boolean Expressions

Boolean Equation Syntax

Boolean Equations Description

Boolean Expressions

Comparators

Implementing Boolean Expressions & Equations

Logical Operators


Ports (AHDL)
Ports

A port is an input or output of a logic function. A port can appear in two locations:

A port that is an input or output of the current file is declared in the Subdesign Section.

A port that is an input or output of an instance of a primitive or lower-level design file is used in the Logic Section.

Ports of the Current File

A port that is an input or output of the current file is declared in the following format within the Subdesign Section:

<port name>: <port type> [ = <default port value> ]

The following port types are available:

INPUT	MACHINE INPUT

OUTPUT	MACHINE OUTPUT

BIDIR

When a TDF is the top-level file in a hierarchy, the port name is synonymous with a pin name. The optional default port value, which is either VCC or GND, can be specified for INPUT and BIDIR port types. This default value is used only if the port is left unconnected when an instance of the TDF is used in a higher-level design file.

In the following example, the input, output, and bidirectional ports of the file are declared in the Subdesign Section:

SUBDESIGN top

(

foo, bar, clk1, clk2, c[4..0][6..0]	: INPUT = VCC;

% VCC is default port value %

a0, a1, a2, a3, a4	: OUTPUT;

b[7..0]	: BIDIR;

)

You can import and export state machines between TDFs and other design files by specifying an input or output port as MACHINE INPUT or MACHINE OUTPUT in the Subdesign Section. The Function Prototype that represents the file must indicate which ports are state machines. MACHINE INPUT and MACHINE OUTPUT ports can only be used in lower-level files in a project hierarchy.

Ports of Instances

A port that is an input or output of an instance of a logic function is connected in the Logic Section. To connect a logic function to other portions of a TDF, you insert an instance of the function with an in-line reference or Instance Declaration or declare a state machine with a State Machine Declaration, and then use ports of the function in the Logic Section.

If you use an in-line reference with positional port association to create an instance of a logic function, the order of the ports, not the names, is important. The order of ports is defined in the Function Prototype for the function.

If you use an Instance Declaration or an in-line reference with named port association to create an instance of a logic function, the names of the ports, not their order, are important.

In the following example, an instance of a D flipflop is declared as the variable reg in the Variable Section, then used in the Logic Section:

VARIABLE

reg : DFF;

BEGIN

reg.clk = clk

reg.d   = d

out     = reg.q

END;

Port names are used in the following format in the Logic Section:

<instance name>.<port name>

The <instance name> is a user-defined name for a function. The <port name> is identical to the port name that is declared as an input or output of the file in the Subdesign Section of a lower-level TDF, or to a pin name in another type of design file. This <port name> is synonymous with the pinstub name for the symbol that represents an instance of the design file in a GDF.

All Altera-provided logic functions have predefined port (pinstub) names, which are shown in the Function Prototype. Commonly used primitive port names are shown in the following table:

Port Name:	Definition:

.q	Output of a flipflop or latch

.d	Data input to a D flipflop or latch

.t	Toggle input to a T flipflop

.j	J input to a JK flipflop

.k	K input to a JK flipflop

.s	Set input to an SR flipflop

.r	Reset input to an SR flipflop

.clk	Clock input to a flipflop

.ena	Clock Enable input to a flipflop, Latch Enable input to a latch, or Enable input to a state machine

.prn	Active-low Preset input to a flipflop

.clrn	Active-low Clear input to a flipflop

.reset	Active-high Reset input to a state machine

.oe	Output Enable input to a TRI primitive

.in	Primary input to TRI, OPNDRN,  SOFT, GLOBAL, and LCELL primitives

.out	Output of TRI, OPNDRN, SOFT, GLOBAL, and LCELL primitives

See also:

Machine Alias Declaration

Port Syntax

Quoted & Unquoted Names

Subdesign Section


Select the Appropriate Operator Category

Choose one of the following topics for information on the usage of the + or - operator:

Arithmetic Operators in Boolean Expressions

Arithmetic Expressions

Choose one of the following topics for information on the usage of the !, &, !&, $, !$, #, !#, or ? operators.

Logical Operators

Arithmetic Expressions


AHDL Design Structure
Design Structure

Title Statement

Include Statement

Include Statement & Include File Rules

Constant Statement

Define Statement

Parameters Statement

Function Prototype Statement

Options Statement

Assert Statement

Subdesign Section

Variable Section

Instance Declaration

Node Declaration

Register Declaration

State Machine Declaration

Machine Alias Declaration

Logic Section

Defaults Statement

Defaults Statement Rules

Assert Statement

Boolean Equations

Boolean Equation Rules

Boolean Control Equations

Case Statement

For Generate Statement

If Generate Statement

If Then Statement

In-Line Logic Function Reference

Truth Table Statement

Truth Table Statement Rules

See also:

Obsolete AHDL Statements

Recommended File Structure


Title Statement Description (AHDL)
Title Statement

The Title Statement allows you to provide documentary comments for the Report File generated by the Compiler. The following example shows a Title Statement:

TITLE "Display Controller";

The Title Statement has the following characteristics:

A Title Statement begins with the keyword TITLE, followed by a text string enclosed in double quotation marks ("). The statement ends with a semicolon (;).

If a Title Statement is included in a TDF, the title appears at the top of the Report File. In the example shown above, the title Display Controller appears in the Report File.

Title Statements must conform to the following rules:

The string can contain a maximum of 255 characters and may not contain end-of-line or end-of-file characters. To include quotation marks in the title, use two quotation marks. For example:

TITLE """EPM5130"" Display Controller";

The Title Statement can only be used once in a TDF.

The Title Statement must be placed outside of all other AHDL sections.

See also:

Inserting an AHDL Template

Recommended File Structure

Title Statement Syntax


Parameters Statement Description (AHDL)
Parameters Statement

The Parameters Statement allows you to declare one or more parameters that control the implementation of a parameterized megafunction or macrofunction. The following example shows a Parameters Statement:

PARAMETERS

(

   FILENAME = "myfile.mif", -- optional default value follows "=" sign

   WIDTH,

   AD_WIDTH = 8,

   NUMWORDS = 2^AD_WIDTH

);

The Parameters Statement has the following characteristics:

A Parameters Statement begins with the keyword PARAMETERS, followed by a list of one or more parameters and optional default values, enclosed in parentheses ().

Parameters in the parameter list are separated by commas (,); parameter names are separated from optional default values by an equals symbol (=). In the example shown above, only the WIDTH parameter does not have a default value.

Parameter names can be user-defined symbolic names or predefined Altera parameters.

Parameter values can consist of text strings enclosed in double quotation marks ("), which are evaluated as strings. When parameter values are unquoted, the Compiler attempts to treat them as arithmetic expressions; failing that, they are treated as strings.

The statement ends with a semicolon (;).

Once a parameter has been defined, you can use it throughout the TDF.

Parameter Statements must conform to the following rules:

A parameter can only be used after it is declared.

Each parameter name must be unique.

The parameter name cannot contain spaces. Use underscores to separate words and improve readability.

The Parameters Statement can be used any number of times in a TDF.

The Parameters Statement must be placed outside of all other AHDL sections.

Parameters used in the definition of other parameters must already be defined.

Circular references are not allowed. Example

When MAX+PLUS II compiles a project, the Compiler searches for parameter values in parameter value search order.

See also:

Constant Statement

Using Altera-Provided Parameterized Functions

Parameters Statement Syntax

Recommended File Structure


Sample circular reference for parameters
Circular reference:

PARAMETERS

(

   FOO = BAR;

   BAR = FOO;

);


Include Statement Description (AHDL)
Include Statement

The Include Statement allows you to import text from an Include File into the current file. The following example shows an Include Statement:

INCLUDE "const.inc";

The Include Statement has the following characteristics:

The Include Statement begins with the keyword INCLUDE, followed by the name of the file to be included, enclosed in double quotation marks (").

If you do not specify a filename extension, the Compiler assumes the extension .inc.

The statement ends with a semicolon (;).

When the Compiler processes the project, the text from the Include File is substituted for the Include Statement. In the example shown above, the file const.inc is substituted for the text INCLUDE "const.inc";.

Be sure to refer to Include Statement & Include File Rules for additional information on using Include Files and Include Statements.

Include Statements are often used to include Function Prototypes for a lower-level design file in a TDF. To use a megafunction or macrofunction, you must first define its logic in a design file. You must then use a Function Prototype Statement to specify the ports of the function. Alternatively, you can use Include Statements to include Function Prototypes that are saved in Include Files. You can then insert an instance of the logic function with an Instance Declaration or an in-line reference.

You can automatically generate an Include File that contains a Function Prototype for a design file with Create Default Include File (File menu).

When you compile a file, the Compiler searches your computer’s directories for Include Files in the following order:

1.	The project directory.

2.	Any user libraries specified with User Libraries.

3.	The \maxplus2\max2lib\mega_lpm and \maxplus2\max2inc directories created during installation.

If you change a TDF that includes an Include File, you can use Project Save & Check (File menu) or fully recompile the project to update the view of the project’s hierarchy tree that is displayed in the Hierarchy Display window.

See also:

Creating & Using Custom Macrofunctions

Creating a Default Include File

Include Statement Syntax

Inserting an AHDL Template

Macrofunctions

Recommended File Structure

Using Altera MAX+PLUS II Unparameterized Macrofunctions


Include Statement & Include File Rules (AHDL)
Include Statement & Include File Rules

Include Statements must conform to the following rules:

The filename specified in the Include Statement cannot contain a path name.

In the workstation environment, filenames are case-sensitive. In MAX+PLUS II documentation, filenames may be listed in upper- or lowercase letters. However, the case of the filename in an Include Statement must match the case of the Include File name. Altera-provided macrofunction and megafunction Include Files list function names with lowercase letters.

An Include Statement must be placed outside of all other AHDL sections.

An Include Statement can appear any number of times in a TDF.

Include Files must conform to the following rules:

Names of Include Files must have the extension .inc.

Include Files should contain only Function Prototype, Define, Parameters, or Constant Statements.

Include Files cannot contain Subdesign Sections.

Include Files cannot be nested.

See also:

Creating & Using Custom Macrofunctions

Creating a Default Include File

Include Statement Syntax

Recommended File Structure

Using Altera MAX+PLUS II Unparameterized Macrofunctions


Constant Statement Description (AHDL)
Constant Statement

The Constant Statement allows you to substitute a meaningful symbolic name for a number or an arithmetic expression. The symbolic name simply represents that number. The following examples show Constant Statements:

CONSTANT UPPER_LIMIT = 130;

CONSTANT BAR = 1 + 2 DIV 3 + LOG2(256);

CONSTANT FOO = 1;

CONSTANT FOO_PLUS_ONE = FOO + 1;

The Constant Statement has the following characteristics:

The Constant Statement begins with the keyword CONSTANT, followed by a symbolic name, an equals symbol (=), and a number (including a radix, if necessary) or an arithmetic expression.

The statement ends with a semicolon (;).

Once a constant is declared, you can use it to represent the number throughout the TDF. In the example shown above, you can use UPPER_LIMIT in the Logic Section to represent the decimal number 130.

Constants can be declared as arithmetic expressions. These arithmetic expressions can include previously defined constants.

The Compiler evaluates arithmetic expressions in Constant Statements and reduces them to numerical values. No logic is generated for these expressions.

Constant Statements must conform to the following rules:

A constant can only be used after it is declared.

Each constant name must be unique.

The constant name cannot contain spaces. Use underscores to separate words and improve readability.

The Constant Statement can be used any number of times in a TDF.

The Constant Statement must be placed outside of all other AHDL sections.

Constants used in the definition of other constants must already be defined.

Circular references are not allowed. Example

See also:

Arithmetic Expressions

Constant Statement Syntax

Define Statement

Inserting an AHDL Template

Numbers in AHDL

Recommended File Structure

Using Constants

Using Default Values for Variables

Using Numbers


Sample circular reference for constants
Circular reference:

CONSTANT FOO = BAR;

CONSTANT BAR = FOO;


Define Statement Description (AHDL)
Define Statement

The Define Statement allows you to define an evaluated function, which is a mathematical function that returns a value that is based on optional arguments.

The following example defines the evaluated function MAX, which ensures that the Subdesign Section declares at least one port.

DEFINE MAX(a,b) = (a > b) ? a : b;

SUBDESIGN

(

   dataA[MAX(WIDTH,0)..0]: INPUT;

   dataB[MAX(WIDTH,0)..0]: OUTPUT;

)

BEGIN

   dataB[] = dataA[];

END;

The Define Statement has the following characteristics:

The Define Statement begins with the keyword DEFINE, followed by a symbolic name and a list of one or more arguments enclosed in parentheses ().

Arguments in the argument list are separated by commas (,). An equals symbol (=) separates the argument list from an arithmetic expression.

If no arguments are listed, an evaluated function behaves as a constant.

The statement ends with a semicolon (;).

Once an evaluated function has been defined, you can use it throughout the TDF.

Evaluated functions can be defined in terms of previously defined evaluated functions. Example

The Compiler evaluates arithmetic expressions in Define Statements and reduces them to numerical values. No logic is generated for these expressions.

Define Statements must conform to the following rules:

An evaluated function can only be used after it has been defined.

Each evaluated function must be unique.

The evaluated function name cannot contain spaces. Use underscores to separate words and improve readability.

The Define Statement can be used any number of times in a TDF.

The Define Statement must be placed outside of all other AHDL sections.

See also:

Using Macros (???title???link)


Sample evaluated function definition
Evaluated Function

DEFINE MIN_ARRAY_BOUND(x) = MAX(0, x) + 1;


Function Prototype Statement Description (AHDL)
Function Prototype Statement

Function Prototype Statements have the same function as symbols in schematic design files. Both provide a shorthand description of a logic function, listing its name and its input, output, and bidirectional ports. Machine ports can also be used for functions that import or export state machines.

However, megafunction and macrofunction input port default values are not automatically assigned as they are in MAX+PLUS II Graphic Editor files; you must assign them explicitly in the Subdesign Section of a TDF. You can also assign a default value for bidirectional ports in the Subdesign Section. However, output ports cannot be assigned a default value.

When you wish to implement an instance of a mega- or macrofunction, you must ensure that its logic is defined in its own design file. You then use a Function Prototype Statement to specify the ports of the function, and implement an instance of the function with an in-line reference or an Instance Declaration.

To implement an instance of a primitive, you also use an in-line reference or an Instance Declaration. However, in contrast to mega- and macrofunctions, primitive logic is predefined, so you do not need to define the primitive logic in a separate design file. In addition, you do not need to use a Function Prototype Statement unless you wish to change the order of the primitive inputs. Example

The following examples show Function Prototype Statements. The first is for a parameterized function; the second is for an unparameterized function:

FUNCTION lpm_add_sub (cin, dataa[LPM_WIDTH-1..0], datab[LPM_WIDTH-1..0],

   add_sub,

   WITH (LPM_WIDTH, LPM_REPRESENTATION, LPM_DIRECTION, ADDERTYPE,

      ONE_INPUT_IS_CONSTANT)

   RETURNS (result[LPM_WIDTH-1..0], cout, overflow);

FUNCTION compare (a[3..0], b[3..0])

RETURNS (less, equal, greater);

The Function Prototype Statement has the following characteristics:

The keyword FUNCTION is followed by the name of the function. In the example shown above, the function names are lpm_add_sub and compare.

A list of input ports to the function follows the name. In the first example shown above, the input ports are cin, dataa[LPM_WIDTH-1..0], and datab[LPM_WIDTH-1..0]; in the second, they are a3, a2, a1, a0, b3, b2, b1, and b0.

In a parameterized function, the keyword WITH and a parameter name list follow the input port list. The list is enclosed in parentheses (); the individual parameter names are separated by commas (,).

The keyword RETURNS is followed by a list of output and bidirectional ports of the function. In the first example shown above, the output ports are result,[LPM_WIDTH-1..0], cout, and overflow; in the second, they are less, equal, and greater.

Both the input and output lists are enclosed in parentheses; the individual port names are separated by commas.

When you import or export a state machine, the Function Prototype for the file must use a machine port (MACHINE keyword) to indicate which inputs and outputs are state machines. For example:

FUNCTION ss_def (clock, reset, count)

   RETURNS (MACHINE ss_out);

The Function Prototype Statement ends with a semicolon (;).

A Function Prototype Statement must be placed outside of the Subdesign Section in a TDF, and it must be placed before the logic function is instantiated in an in-line reference or Instance Declaration.

As an alternative to using a Function Prototype Statement in a file, you can use an Include Statement to call an Include File that contains a Function Prototype Statement. MAX+PLUS II also provides the Create Default Include File command (File menu), which automatically creates an Include File containing a Function Prototype for any design file.

Function Prototypes for all MAX+PLUS II megafunctions and macrofunctions are stored in Include Files in the \maxplus2\max2lib\mega_lpm and \maxplus2\max2inc directories, respectively On-line help for all megafunctions, macrofunctions, and primitives shows the Function Prototype for each Altera-provided function.

See also:

Creating a Default Include File

Function Prototype Statement Syntax

Implementing Bidirectional Pins

Importing & Exporting State Machines

In-Line Logic Function Reference

Inserting an AHDL Template

Ports

Recommended File Structure

Using Altera-Provided Parameterized Functions

Using Altera-Provided Unparameterized Functions

Using Custom Megafunctions & Macrofunctions


Example: Function Prototype 1
The following example shows the default Function Prototype for a JKFF primitive:

FUNCTION JKFF (j, k, clk, clrn, prn)

RETURNS (q);

The following example shows a modified Function Prototype for a JKFF primitive:

FUNCTION JKFF (k, j, clk, clrn, prn)

RETURNS (q);


Example: Function Prototype 2
The following example shows a Function Prototype for the ss_def function:

FUNCTION ss_def (clock, reset, count)

RETURNS (MACHINE ss_out);


Options Statement Description (AHDL)
Options Statement

The Options Statement sets the BIT0 option to specify whether the lowest numbered bit of a group will be the MSB the LSB or either, depending on its location.

The Options Statement begins with the keyword OPTIONS, followed by the BIT0 option and setting. The Options Statement ends with a semicolon (;).

The following example shows an Options Statement:

OPTIONS BIT0 = MSB;

In this example, the lowest numbered bit of a group is specified as the MSB. The other settings available are LSB and ANY.

An Options Statement at the beginning of a TDF sets the default bit-ordering for the entire file. If the file is a top-level TDF, the Options Statement applies to the entire project. If the file is lower in the project hierarchy, the Options Statement specifies the bit-ordering only for that file.

See also:

Inserting an AHDL Template

Obsolete AHDL Statements

Options Statement Syntax

Recommended File Structure


Obsolete AHDL Statements

In versions of MAX+PLUS II earlier than 5.0, you could enter resource and device assignments using the AHDL Options Statement and the AHDL Design Section. Starting with version 5.0, you must enter resource and device assignments only with Assign menu commands or in an Assignment & Configuration File. The functions of the Design Section and many of the functions of the Options Statement in earlier versions of MAX+PLUS II are no longer supported in AHDL. The AHDL Design Section is no longer supported, and the Options Statement now includes only the BIT0 option.

The following statements are no longer available or have changed in AHDL:

Obsolete AHDL Statement:	Equivalent Assign Menu Command/Dialog Box:

Clique Assignment Statement	Clique

Device Specification	Device

Auto Device Selection

Individual Device Options

Global Project Device Options

Options Statement	Logic Options

Individual Logic Options

Advanced Options

Global Project Logic Synthesis

Pin Connection Statement	Connected Pins

Resource Assignment Statement	Pin/Location/Chip

When you open a project with MAX+PLUS II version 5.0, MAX+PLUS II automatically converts assignments in pre-version 5.0 TDFs to the current format in the file <project name>.acf. If MAX+PLUS II is unable to convert the TDF assignments, a message is displayed. After you correct the TDF, you can then choose Convert Obsolete Assignment Format to convert the corrected files.

See also:

Converting an Obsolete Assignment Format

Inserting an AHDL Template

Recommended File Structure


Subdesign Section Description (AHDL)
Subdesign Section

The Subdesign Section declares the input, output, and bidirectional ports of the TDF.

The following example shows a Subdesign Section:

SUBDESIGN top

(

foo, bar, clk1, clk2	: INPUT = VCC;

a0, a1, a2, a3, a4	: OUTPUT;

b[7..0]	: BIDIR;

)

The Subdesign Section has the following characteristics:

The keyword SUBDESIGN is followed by the subdesign name. The subdesign name must be the same as the TDF filename. In this example, the subdesign name is top.

The list of signals is enclosed in parentheses.

Signal names are represented by symbolic names such as foo, and are assigned a port type such as INPUT.

Signal names are separated by commas (,), are followed by a colon (:) and a port type, and end with a semicolon (;).

The port type may be INPUT, OUTPUT, BIDIR, MACHINE INPUT, or MACHINE OUTPUT. In the example shown above, the foo, bar, clk1, and clk2 signals are inputs and a0, a1, a2, a3, and a4 are outputs. The bus b[7..0] is bidirectional.

The MACHINE INPUT and MACHINE OUTPUT keywords are used to import and export state machines between TDFs and other design files. However, MACHINE INPUT and MACHINE OUTPUT port types cannot be used in a top-level TDF.

You can optionally assign a default value of GND or VCC after the port type (otherwise, no default value is assumed). In the example shown above, VCC is the default value for the input signals unless they are assigned in a higher-level file (assignments in a higher-level file take precedence).

In a top-level design file, INPUT, OUTPUT, and BIDIR port types represent actual device pins. In a lower-level design file, all port types are the inputs and outputs of the file, but not of the project itself.

See also:

Importing & Exporting State Machines

Inserting an AHDL Template

Recommended File Structure

Subdesign Section Syntax


Variable Section Description (AHDL)
Variable Section

The optional Variable Section is used to declare and/or generate any variables used in the Logic Section. AHDL variables are similar to variables in a high-level programming language; they are used to define buried (internal) logic.

The following example shows a Variable Section:

VARIABLE

a, b, c	: NODE;

temp 	: halfadd;

ts_node	: TRI_STATE_NODE;

IF DEVICE_FAMILY == "FLEX8000" GENERATE

8kadder	: flex_adder;

d,e	: NODE;

ELSE GENERATE

7kadder	: pterm_adder;

f,g	: NODE;

END GENERATE;

The Variable Section has the following subsections:

If Generate Statement

Instance Declaration

Node Declaration

Register Declaration

State Machine Declaration

Machine Alias Declaration

The Variable Section has the following characteristics:

The keyword VARIABLE begins the Variable Section.

In all subsections except the If Generate Statement, user-defined, symbolic variable names are separated from each other by commas (,) and from the variable type by a colon (:). The variable type can be NODE, TRI_STATE_NODE, <primitive>, <megafunction>, <macrofunction>, or <state machine declaration>. In the example shown above, the internal variables are a, b, and c of type NODE; temp, an instance of the macrofunction halfadd; and ts_node, an instance of type TRI_STATE_NODE.

In all subsections except the If Generate Statement, each entry in the list of variables ends with a semicolon (;).

If Generate Statements that are used as subsections of the Variable Section have the format described in If Generate Statement.

Compiler-generated names that contain the tilde (~) character may appear in the Fit File for a project. If you back-annotate the Fit File assignments, these names will then appear in the project’s ACF. The tilde character is reserved for Compiler-generated names only; you cannot use it in your own pin, node, and group (bus) names.

See also:

Inserting an AHDL Template

Recommended File Structure

Variable Section Syntax


Instance Declaration Description (AHDL)
Instance Declaration

Each individual usage, or instance, of a particular logic function can be declared as a variable with an Instance Declaration in the Variable Section. After it is declared, you can use the input and output ports of each logic function as ports in the Logic Section.

When you wish to implement an instance of a megafunction or macrofunction, you must ensure that its logic is defined in its own design file. You then use a Function Prototype Statement to specify the ports and parameters of the function, and implement an instance of the function with an in-line reference or an Instance Declaration.

To implement an instance of a primitive, you also use an in-line reference or an Instance Declaration. However, in contrast to mega- and macrofunctions, primitive logic is predefined, so you do not need to define the primitive logic in a separate design file. In most cases, a Function Prototype Statement is not needed. See Function Prototype Statement for more information.

To use an Instance Declaration, you declare a variable of type <primitive>, <megafunction>, or <macrofunction> in the Variable Section. For a parameterized mega- or macrofunction, the declaration includes a list of the parameters used by the instance and optional default parameter values. Once you declare the variable, you can use ports of the instance of the function in the following format:

<instance name>.<port name>

For example, if you wish to incorporate the compare and adder functions (taken from the example in Function Prototype Statement) into your current TDF, make the following Instance Declarations in the Variable Section:

VARIABLE

comp  : compare;

adder : lpm_add_sub WITH (LPM_WIDTH = 8)

The variables comp and adder are instances of the functions compare and lpm_add_sub, which have the following inputs and outputs:

a[3..0], b[3..0] 	: INPUT;	-- inputs to compare

less, equal, greater : OUTPUT;	-- outputs of compare

a[8..1], b[8..1]	: INPUT; 	-- inputs of adder

sum[8..1]	: OUTPUT;	-- outputs of adder

You can therefore use the following ports of comp and adder in the current Logic Section:

comp.a[], comp.b[], comp.less, comp.equal, comp.greater

adder.dataa[], adder.datab[], adder.result[]

These ports can be used in any behavioral statement in the same way as nodes.

Since all primitives have only one output, you can use the name of a primitive without a port name (e.g., without .q or .out) on the right side of an equation if you want to use its output. Similarly, for all primitives that have a single primary input (i.e., all primitives except JKFF, JKFFE, SRFF, and SRFFE), you can use the name of a primitive without a port name (e.g., without .d, .t, or .in) on the left side of an equation to connect the primitive to its primary input. See Register Declaration for more information.

When MAX+PLUS II compiles a Project, the Compiler searches for parameter values for each instance of a mega- or macrofunction in parameter value search order.

See also:

Creating & Using Custom Macrofunctions

Creating & Using Parameterized Macrofunctions (???title???link)

Creating a Default Include File

If Generate Statement

Implementing LCELL & SOFT primitives

Inserting an AHDL Template

Macrofunctions

Megafunctions (???link???)

Node Declaration

Ports

Primitives

Recommended File Structure

Using Altera MAX+PLUS II Unparameterized Macrofunctions

Variable Section Syntax


Node Declaration Description (AHDL)
Node Declaration

AHDL supports two types of nodes: NODE and TRI_STATE_NODE.

Both types are all-purpose variable types used to store signals that have not been declared in the Subdesign Section or elsewhere in the Variable Section. Therefore, a variable of either type can be used on the left or the right side of an equation.

Both NODE and TRI_STATE_NODE are similar to the INPUT, OUTPUT, and BIDIR port types of the Subdesign Section, in that they represent a single wire that propagates signals.

Compiler-generated names that contain the tilde (~) character may appear in the Fit File for a project. If you back-annotate the Fit File assignments, these names will then appear in the project’s ACF. The tilde character is reserved for Compiler-generated names only; you cannot use it in your own pin, node, and group (bus) names.

The following example shows a Node Declaration:

SUBDESIGN node_ex

(

a, oe	: INPUT;

b	   : OUTPUT;

c	   : BIDIR;

)

VARIABLE

b : NODE;

t : TRI_STATE_NODE;

BEGIN

b = a;

out = b	% therefore out = a %

t = TRI(a, oe);

t = c;	% t is bus of c and tri_stated a %

END;

NODE and TRI_STATE_NODE differ in that multiple assignments to them yield different results:

Multiple assignments to nodes of type NODE tie the signals together by wired-AND or wired-OR functions. The default values for variables declared in Defaults Statements determine the behavior: a VCC default produces a wired-AND function; a GND default produces a wired-OR function.

Multiple assignments to a TRI_STATE_NODE tie the signals to the same node.

If only one variable is assigned to a TRI_STATE_NODE, it is treated as NODE.

The following primitives and signals can feed TRI_STATE_NODE nodes:

TRI primitives

INPUT ports from a design file at a higher hierarchical level

OUTPUT and BIDIR ports from a design file at a lower hierarchical level

BIDIR ports of the current file

Other nodes declared as TRI_STATE_NODE types in the current file

See also:

Declaring Nodes

If Generate Statement

Inserting an AHDL Template

Instance Declaration

Recommended File Structure

Register Declaration

State Machine Declaration

Variable Section Syntax

Implementing Tri-State Buses (AHDL)


Register Declaration Description (AHDL)
Register Declaration

The Variable Section is used to declare registers, including D, T, JK, and SR flipflops (DFF, DFFE, TFF, TFFE, JKFF, JKFFE, SRFF and SRFFE) and latches (LATCH). The following example shows a Register Declaration:

VARIABLE

ff : TFF;

The name of this instance of a T flipflop is ff. After making this declaration, you can use the input and output ports of the instance of ff in the format <instance name>.<port name>:

ff.t

ff.clk

ff.clrn

ff.prn

ff.q

Since all primitives have only one output, you can use the name of an instance of a primitive without appending a port name (e.g., without .q or .out) on the right side of an equation if you want to use its output. Similarly, for all primitives that have a single primary input, i.e., all primitives except JKFF, JKFFE, SRFF, and SRFFE, you can use the name of an instance of a primitive without a port name (e.g., without .d, .t, or .in) on the left side of an equation to connect the primitive to its primary input.

For example, the DFF Function Prototype is FUNCTION DFF(d, clk, clrn, prn) RETURNS (q);. In the following TDF excerpt, a = b; is equivalent to a.d = b.q;:

VARIABLE

a, b : DFF;

BEGIN

a = b;

END;

See also:

Declaring Registers

If Generate Statement

Inserting an AHDL Template

Instance Declaration

Node Declaration

Primitives

Recommended File Structure

State Machine Declaration

Variable Section Syntax


State Machine Declaration Description (AHDL)
State Machine Declaration

You create a state machine by declaring the name of the state machine, its states, and, optionally, its bits in the Variable Section.

The following example shows a State Machine Declaration:

VARIABLE

ss :	MACHINE

OF BITS (q1, q2, q3)

WITH STATES (

s1 = B"000",

s2 = B"010",

s3 = B"111");

The state machine name is ss. The state bits q1, q2, and q3 are outputs of registers for this machine. The states of this state machine are s1, s2, and s3, each of which is assigned a numerical state value for the state bits q1, q2, and q3.

A State Machine Declaration has the following characteristics:

The state machine name is a symbolic name. In the example shown above, the state machine name is ss.

The state machine name is followed by a colon (:) and the keyword MACHINE.

The State Machine Declaration must include a list of states, and can include a list of state bit names.

Optional state bits are specified with the keywords OF BITS, followed by a comma-separated list of symbolic names; the list must be enclosed in parentheses (). The example shown above specifies the state bits q1, q2, and q3.

States are specified by the keywords WITH STATES, followed by a comma-separated list of symbolic names; the list must also be enclosed in parentheses. The example shown above specifies the states s1, s2, and s3.

The first state listed in the WITH STATES clause is the Reset state for the state machine.

The state names may be optionally assigned to a value with an equals symbol (=) followed by a numerical value. In the example shown above, s1 is assigned to B"000", s2 is assigned to B"010", and s3 is assigned to B"111".

You can use a Machine Alias Declaration to assign an alternate name to a state machine that is declared in the current file or imported from another file.

A semicolon (;) ends a State Machine Declaration.

Each state of a state machine is represented by a unique pattern of high and low flipflop output signals. The state bits are the flipflops required by the machine to store the states. The number of states has the following relationship to the number of state bits in a state machine:

<number of states> <= 2^<number of state bits>

See also:

Assigning State Machine Bits & Values

If Generate Statement

Inserting an AHDL Template

Numbers in AHDL

Recommended File Structure

Recovering from Illegal States

State Machines (AHDL)

Variable Section Syntax


Machine Alias Declaration Description (AHDL)
Machine Alias Declaration

You can rename a state machine with a temporary name using a Machine Alias Declaration in the Variable Section. You can use a machine alias in the file where the state machine is created, or in a file that uses a MACHINE INPUT port to import a state machine. You can then use this name instead of the original state machine name. For example:

FUNCTION ss_def (clock, reset, count)

RETURNS (MACHINE ss_out);

VARIABLE

ss : MACHINE;

BEGIN

ss = ss_def (sys_clk, reset, !hold);

IF ss == s0 THEN

ELSIF ss == s1 THEN

END;

A Machine Alias Declaration has the following characteristics:

The machine alias is a symbolic name. It is followed by a colon (:) and the keyword MACHINE. In the example shown above, ss is the machine alias.

You can import and export state machines between TDFs and other design files by specifying an input or output port as MACHINE INPUT or MACHINE OUTPUT in the Subdesign Section.

When you import or export a state machine, the Function Prototype that represents the file must indicate which inputs and outputs are state machines. In the example shown above, ss_out is the state machine name.

A semicolon (;) ends a Machine Alias Declaration.

MACHINE INPUT and MACHINE OUTPUT port types cannot be used in a top-level TDF.

See also:

Importing & Exporting State Machines

Inserting an AHDL Template

Ports

Recommended File Structure

State Machines (AHDL)

Variable Section Syntax


Logic Section Description (AHDL)
Logic Section

The Logic Section specifies the logical operations of the TDF. This section is required. One or more of the following statements or constructs may be used in this section:

Boolean Equations

Boolean Control Equations

Case Statement

Defaults Statement

If Then Statement

If Generate Statement

For Generate Statement

Assert Statement

Truth Table Statement

The BEGIN and END keywords enclose the Logic Section. A semicolon (;) follows the END keyword and terminates this section. The Defaults Statement must be the first statement in the section.

AHDL is a concurrent language. The Compiler evaluates all behavior specified in the Logic Section of a TDF at the same time rather than sequentially. Equations that assign multiple values to the same AHDL node or variable are logically ORed. See Defaults Statement Rules for more information.

See also:

Logic Section Syntax

Inserting an AHDL Template

Recommended File Structure


If Generate Statement Description (AHDL)
If Generate Statement

The If Generate Statement lists a series of behavioral statements that are activated after the positive evaluation of an arithmetic expressions.

The following example shows an If Generate Statement:

IF DEVICE_FAMILY == "FLEX8K" GENERATE

c[] = 8kadder(a[], b[], cin);

ELSE GENERATE

c[] = otheradder(a[], b[], cin);

END GENERATE;

The If Generate Statement has the following characteristics:

The keywords IF and GENERATE enclose the arithmetic expression to be evaluated and are followed by one or more behavioral statements, each of which ends with a semicolon (;). These statements are activated if the expression is true.

The keywords ELSE GENERATE are followed by one or more behavioral statements, each of which ends with a semicolon. These statements are activated if the arithmetic expression is false.

The keywords END GENERATE and a semicolon (;) end the If Generate Statement.

The If Generate Statement can be used in the Logic Section or in the Variable Section.

1. 	Unlike If Then Statements, which can evaluate only Boolean expressions, If Generate Statements can evaluate the superset of arithmetic expressions. The essential difference between an If Then Statement and an If Generate Statement is that the former is evaluated in hardware (silicon), whereas the latter is evaluated when the design is compiled.

2. 	The If Generate Statement is especially useful with For Generate Statements that handle special cases differently, for example, the LSB of a multi-stage multiplier. It can also be used to test parameter values, as shown in the example above.

See also:

If Generate Statement Syntax

Implementing Conditional Logic

Inserting an AHDL Template

Recommended File Structure (AHDL)


For Generate Statement Description (AHDL)
For Generate Statement

The For Generate Statement lists a series of behavioral statements to be repeated.

The following example shows an iterative For Generate Statement:

CONSTANT NUM_OF_ADDERS = 8;

SUBDESIGN 4gentst

(

a[NUM_OF_ADDERS..1], b[NUM_OF_ADDERS..1], cin : INPUT;

c[NUM_OF_ADDERS..1], cout	 : OUTPUT;

)

VARIABLE

carry_out[(NUM_OF_ADDERS+1)..1] : NODE;

BEGIN

carry_out[1] = cin;

FOR i IN 1 TO NUM_OF_ADDERS GENERATE

c[i] = a[i] $ b[i] $ carry_out[i];	% Full Adder %

carry_out[i+1] = a[i] & b[i] # carry_out[i] & (a[i] $ b[i]);

END GENERATE;

cout = carry_out[NUM_OF_ADDERS+1];

END;

The For Generate Statement has the following characteristics:

The keywords FOR and GENERATE enclose the following items:

1. 	A temporary variable name, which consists of a symbolic name that is used only within the context of the For Generate Statement, i.e., the variable ceases to exist after the Compiler processes the statement. In the example shown above, the variable is i.

2. 	The word IN, which is followed by a range delimited by two arithmetic expressions. The arithmetic expressions are separated by the TO keyword. In the example shown above, the arithmetic expressions are 1 and NUM_OF_ADDERS. The range endpoints can consist of expressions containing only constants and parameters; variables are not required.

The GENERATE keyword is followed by one or more logic statements, each of which ends with a semicolon (;).

The keywords END GENERATE and a semicolon (;) end the For Generate Statement.

See also:

Arithmetic Expressions

For Generate Statement Syntax

Implementing Conditional Logic

Inserting an AHDL Template

Recommended File Structure (AHDL)


Assert Statement Description (AHDL)
Assert Statement

The Assert Statement allows you to test the validity of any arbitrary expression that uses parameters, numbers, evaluated functions, or the used or unused status of a port.

The following example shows an Assert Statement:

ASSERT (WIDTH > 0)

REPORT 	"Width (%) must be a positive integer" WIDTH

SEVERITY	ERROR

HELP_ID	INTVALUE;	-- for internal Altera use only

The Assert Statement has the following characteristics:

The keyword ASSERT is followed by an arithmetic expression that is optionally enclosed in parentheses (). When the expression is false, the assertion is activated and the message string following the REPORT keyword is displayed in the Message Processor. If you do not specify a condition, the assertion is always activated.

The REPORT keyword is followed by a message string and optional message variables. The message string is enclosed in double quotation marks ("), and can include % characters that are substituted with the values of optional message variables. If no REPORT keyword is used, an assertion that is activated displays a generic message of the following format in the Message Processor:

<severity>: Line <line number>, File <filename>: Assertion failed

Optional message variables consist of one or more parameters, evaluated functions, or arithmetic expressions. Multiple message variables are separated by commas (,). The values of the message variables are substituted, in order, for the % characters in the quoted message string. In the example shown above, the value of WIDTH is substituted for the % in the quoted message string.

The optional SEVERITY keyword is followed by a severity level of ERROR, WARNING, or INFO. If no severity is specified, it defaults to ERROR.

The HELP_ID keyword and help string are used in some Altera-provided logic functions and are reserved for internal Altera use.

The statement ends with a semicolon (;).

The Assert Statement can be used within the Variable Section and Logic Section or outside of any other AHDL section.

See also:

Using the Assert Statement (???link)


Boolean Equations Description (AHDL)
Boolean Equations

Boolean equations are used in the Logic Section of your AHDL TDF to represent the connection of nodes, the flow of inputs into and the flow of outputs from input and output pins, primitives, macrofunctions, and state machines.

Boolean equations must follow the rules described in Boolean Equation Rules.

The following example shows a complex Boolean equation:

a[] = ((c[] & -B"001101") + e[6..1]) # (p, q, r, s, t, v);

The left side of the equation can be a symbolic, port, or group name. You can use the NOT (!) operator to invert any item on the left. The right side of the equation consists of a Boolean expression, which is evaluated as described in Boolean Equation Priorities.

The equals symbol (=) is used in Boolean equations to indicate that the result of the Boolean expression on the right side is the source of the symbolic node or group on the left side. The single equals symbol differs from the double equals symbol (==), which is used as a comparator.

In the example shown above, the Boolean expression on the right is evaluated according to Boolean equation priority rules:

1.	The binary number B"001101" is negated and becomes B"110011". The unary minus (-) has first priority.

2.	B"110011" is anded (&) with the group c[]. This expression has second priority because it is enclosed in parentheses.

3.	The result of the group expression in step 2 is added to the group e[6..1].

4.	The result of the expression in step 3 is ORed (#) with the group (p, q, r, s, t, v). This expression has last priority.

The final result is assigned to the group a[].

For the sample equation shown above to be legal, the number of bits in the group on the left side of the equation must be evenly divisible by the number of bits in the group on the right side of the equation. The bits on the left side of the equation are mapped to the right side of the equation in order. Example

See also:

Boolean Equation Syntax

Boolean Expressions

Implementing Boolean Expressions & Equations

Inserting an AHDL Template

Recommended File Structure


Boolean Equation Rules (AHDL)
Boolean Equation Rules

The following rules apply to Boolean equations:

Multiple assignments to a variable are logically ORed (#), except when the default for the variable is VCC.

If the number of nodes on the left side of the Boolean equation equals the number of nodes on the right, a one-to-one correspondence exists.

If a single node, GND, or VCC on the right side of an equation is assigned to a group, the node or constant is duplicated to match the size of the group. Example

If both the left and right sides of the equation are groups of the same size, each member on the right is assigned to the member on the left that corresponds in position. Example

When you add two groups together on the right side of a Boolean equation with the + operator, you can place a 0 on the left of each group to sign-extend the width of the group. This method provides an extra bit of information to the group on the left side of the equation that can be used as a carry-out signal. Example

If the left and right sides of an equation have groups of different sizes, the number of bits in the group on the left must be evenly divisible by the number of bits in the group on the right. The bits on the left side of the equation are mapped to the right side of the equation, in order. Example

A group of nodes or numbers cannot be assigned to a single node.

If a number on the right side of an equation is assigned to a group, the number is truncated or sign-extended to match the size of the group. If any significant bits are truncated, the Compiler issues an error message. Each member on the right is assigned to the member on the left with the corresponding position. Example

Commas can be used to hold the places of unassigned group members in a Boolean equation. Example

A semicolon (;) ends each equation.

See also:

Boolean Equation Priorities

Boolean Equation Syntax

Boolean Equations

Boolean Expressions

Defaults Statement

Implementing Boolean Expressions & Equations

Recommended File Structure


Example:Boolean 1
(a, b) = e; is the same as a = e; b = e;


Example: Boolean 2
(a, b) = (c, d); is the same as a = c; b = d;


Example:Boolean Group Multiple
The following equation is legal:

a[4..1] = b[2..1]

In this equation, the bits are mapped as follows:

a4 = b2

a3 = b1

a2 = b2

a1 = b1


Example:Boolean 3
(a, b) = 1; is the same as a = 0; b = 1;


Example:Boolean 4
The following example shows commas that hold the places of two members of the group (a, b, c, d):

(a, , c, ) = B"1011";

In this example, both a and c are assigned the value 1.


Boolean Control Equations Description (AHDL)
Boolean Control Equations

Control equations are Boolean equations used in the Logic Section to set up the state machine Clock, Reset, and Clock Enable signals.

The following examples show Boolean control equations:

ss.clk = clk1;

ss.reset = a & b;

ss.ena = clk1ena;

Boolean control equations have the following characteristics:

You can define the Clock, Reset, and Clock Enable inputs of each state machine in the format <state machine name>.<port name>. In the example above, these inputs are defined for the state machine ss.

You can use the state machine name declared in the State Machine Declaration as the state machine name in the control equations.

The Clock signal <state machine name>.clk must always be assigned a value.

If the start state of the state machine has been assigned a non-zero value, then the Reset signal <state machine name>.reset assignment is required; otherwise, it is optional.

Assigning the Clock Enable signal <state machine name>.ena to a value is always optional.

A semicolon (;) ends each equation.

See also:

Boolean Control Equation Syntax

Recommended File Structure

Setting Clock & Reset Signals

State Machines (AHDL)


Case Statement Description (AHDL)
Case Statement

The Case Statement lists the alternatives that may be activated depending on the value of the variable, group, or expression following the CASE keyword.

The following example shows a Case Statement:

CASE f[].q IS

WHEN H"00" =>

addr[] = 0;

s = a & b;

WHEN H"01" =>

count[].d = count[].q + 1;

WHEN H"02", H"03", H"04" =>

f[3..0].d = addr[4..1];

WHEN OTHERS =>

f[].d = f[].q;

END CASE;

The Case Statement has the following characteristics:

The keywords CASE and IS enclose a Boolean expression, group, or state machine (in the example shown above, f[].q).

The Case Statement is terminated by the keywords END CASE and a semicolon (;).

One or more unique alternatives are listed in the WHEN clauses in the body of the Case Statement. Each WHEN clause begins with the keyword WHEN.

In each alternative WHEN clause, one or more comma-separated constant values are followed by an arrow symbol (=>). In this example, the H"02", H"03", and H"04" constant values are listed in a single WHEN clause; the H"00" and H"01" constant values are listed in separate WHEN clauses.

If the Boolean expression following the CASE keyword evaluates to a specific alternative, all the behavioral statements following the arrow are activated. In the example shown above, if f[].q evaluates to H"01", the Boolean equation count[].d = count[].q + 1 is activated.

When no other alternative is true, the keywords WHEN OTHERS define the default alternative. In the example shown above, if f[].q does not equal H"00", H"01", or H"CF", the Boolean equation f[].d = f[].q is activated.

If the Case Statement is used to define the transitions of a state machine, the keywords WHEN OTHERS cannot be used to recover from illegal states of an n-bit state machine unless the state machine contains exactly 2^n states.

Each behavioral statement ends with a semicolon (;).

See also:

Case Statement Syntax

Implementing Conditional Logic

Inserting an AHDL Template

Recommended File Structure

Recovering from Illegal States


Defaults Statement Description (AHDL)
Defaults Statement

The Defaults Statement allows you to specify default values for variables used in Truth Table, If Then, and Case Statements. Since active-high signals automatically default to GND, Defaults Statements are required only for active-low signals.

1.	You should not confuse default values for variables with default values for ports that are assigned in the Subdesign Section.

2.	Defaults Statements must follow the rules described in Defaults Statement Rules.

The following example shows a Defaults Statement:

BEGIN

DEFAULTS

a = VCC;

END DEFAULTS;

IF y & z THEN

a = GND;	% a is active low %

END IF;

END;

The Defaults Statement has the following characteristics:

It is enclosed by the keywords DEFAULTS and END DEFAULTS and ends with a semicolon (;).

The body of the Defaults Statement consists of one or more Boolean equations that assign constant values to variables. In the example shown above, the Defaults Statement assigns the default value VCC to the variable a.

Each equation ends with a semicolon (;).

The Defaults Statement is activated if a variable that follows it is undefined for certain conditions. In the example shown above, the variable a is undefined when y or z is a logical low, so the equation (a = VCC) in the Defaults Statement is activated.

A Defaults Statement cannot be used to set a default value of X (don’t care) to a variable.

See also:

Defaults Statement Syntax

Recommended File Structure

Using Default Values for Variables


Defaults Statement Rules (AHDL)
Defaults Statement Rules

The following rules apply to Defaults Statements:

Only one Defaults Statement is allowed in the Logic Section, and it must be the first statement after the BEGIN keyword.

If a single variable is assigned a value more than once in a Defaults Statement, all assignments but the last are ignored.

A Defaults Statement cannot be used to set a default value of X (don’t care) to a variable.

Multiple assignments to a variable outside of a Defaults Statement are logically ORed, except when the default for the variable is VCC. Example

Active-low variables that are assigned more than once should be given a default value of VCC. Example

See also:

Defaults Statement Syntax

Inserting an AHDL Template

Recommended File Structure

Using Default Values for Variables


Example:Defaults 1
The following TDF excerpt illustrates the default values for two variables: a with default value GND, and bn with default value VCC:

BEGIN

DEFAULTS

a = GND;

bn = VCC;

END DEFAULTS;

IF c1 THEN

a = a1;

bn = b1n;

END IF;

IF c2 THEN

a = a2;

bn = b2n;

END IF;

END;

This example is equivalent to:

a = c1 & a1 # c2 & a2;

bn = (!c1 # b1n) & (!c2 # b2n);


Example: Defaults 2
In the following example, reg[].clrn is given a default value of VCC:

SUBDESIGN 5bcount

(

d[5..1]	: INPUT;

clk	: INPUT;

clr	: INPUT;
sys_reset	: INPUT;

enable	: INPUT;

load	: INPUT;

q[5..1]	: OUTPUT;

)

VARIABLE

reg[5..1] 	: DFF;

BEGIN

DEFAULTS

reg[].clrn = VCC;

END DEFAULTS;

reg[].clk = clk;

q[]       = reg[];

IF sys_reset # clr THEN

reg[].clrn = GND;

END IF;

!reg[].prn  = (load & d[]) & !clr;

!reg[].clrn = load & !d[];

reg[] = reg[] + (0, enable);

END;


If Then Statement Description (AHDL)
If Then Statement

The If Then Statement lists a series of behavioral statements to be activated after the positive evaluation of one or more Boolean expressions.

The following example shows an If Statement:

IF a[] == b[] THEN

c[8..1] = H "77";

addr[3..1] = f[3..1].q;

f[].d = addr[] + 1;

ELSIF g3 $ g4 THEN

f[].d = addr[];

ELSE

d = VCC;

END IF;

The If Then Statement has the following characteristics:

The keywords IF and THEN enclose the Boolean expression to be evaluated and are followed by one or more behavioral statements, each of which ends with a semicolon (;).

The keywords ELSIF and THEN enclose any additional Boolean expressions to be evaluated, and are also followed by one or more behavioral statements. These optional statements can be repeated.

The behavioral statement(s) following the keyword THEN are activated for the first expression that evaluates to true.

The keyword ELSE followed by one or more behavioral statements is similar to the WHEN OTHERS default alternative of the Case Statement. If none of the previously evaluated Boolean equations is true, then the behavioral statement(s) following ELSE are activated. In the example shown above, if neither expression evaluates to true, the equation d = VCC is activated. The ELSE clause is also optional.

Expressions following IF and ELSIF keywords (in the example shown above, a[] == b[] and g3 $ g4) are evaluated concurrently.

An If Then Statement may generate logic that is too complex for the MAX+PLUS II Compiler. If an If Then Statement contains complex expressions, then the inversion of each expression is likely to be even more complex. Example

The keywords END IF and a semicolon (;) end the If Then Statement.

Unlike If Then Statements, which can evaluate only Boolean expressions, If Generate Statements can evaluate the superset of arithmetic expressions. The essential difference between an If Then Statement and an If Generate Statement is that the former is evaluated in hardware (silicon), whereas the latter is evaluated when the design is compiled.

See also:

Boolean Equations

If Then Statement Syntax

If Then Statement vs. Case Statement

Implementing Conditional Logic

Inserting an AHDL Template

Recommended File Structure


Example: Complex If Statement
If Statement:	Compiler Interpretation:

If a and b are complex expressions, then the inversion of each expression is likely to be even more complex.

IF a THEN	IF a THEN

c = d;	c = d;

END IF;

ELSIF b THEN	IF !a & b THEN

c = e;	c = e;

END IF;

ELSE 	IF !a & !b THEN

c = f;	c = f;

END IF;	END IF;


In-Line Logic Function Reference Description (AHDL)
In-Line Logic Function Reference

An in-line logic function reference is a Boolean equation that implements a logic function. It is a shorthand method for implementing a logic function that uses only one line of the Logic Section and does not require a Variable Declaration.

When you wish to implement an instance of a megafunction or macrofunction, you must ensure that its logic is defined in its own design file. You then use a Function Prototype Statement of the function, and implement an instance of the function with an in-line reference or an Instance Declaration.

To implement an instance of a primitive, you also use an in-line reference or an Instance Declaration. However, in contrast to mega- and macrofunctions, primitive logic is predefined, so you do not need to define the primitive logic in a separate design file. In most cases, a Function Prototype Statement is not needed. See Function Prototype Statement for more information.

The following examples show the Function Prototypes for the compare and lpm_add_sub functions. The compare function has input ports a[3..0] and b[3..0] and output ports less, equal, and greater; the lpm_add_sub function has the input ports

FUNCTION compare (a[3..0], b[3..0])

RETURNS (less, equal, greater);

FUNCTION LPM_ADD_SUB (cin, dataa[LPM_WIDTH-1..0], datab[LPM_WIDTH-1..0],

   add_sub)

WITH (LPM_WIDTH, LPM_REPRESENTATION)

RETURNS (result[LPM_WIDTH-1..0], cout, overflow);

The in-line logic function references for the compare and lpm_add_sub functions appear on the right side of the equations below:

(clockwise, , counterclockwise) = compare(position[], target[]);

sum[] = lpm_add_sub (.datab[] = b[], .dataa[] = a[])

   WITH (LPM_WIDTH = 8)

   RETURNS (.result[]);

The in-line reference for a logic function has the following characteristics:

The function name on the right side of the equals symbol (=) is followed by a signal list enclosed in parentheses (), containing symbolic names, decimal numbers, or groups, separated by commas (,). These items correspond to the input ports of the function or primitive.

In the signal list, port names can be given through positional port association or named port association:

-	In the compare example shown above, the a[3..0] and b[3..0] inputs of compare are connected to the variables named position[] and target[], respectively, through positional port association. When you use positional port association, you can use commas as placeholders for outputs that are not connected to a variable. In compare, the equal output is not connected to any variable, so an extra comma is needed to hold its place in the group on the left side of the equation.

-	In the lpm_add_sub example shown above, the .datab[] and .dataa[] inputs of lpm_add_sub are connected to the variables b[] and a[], respectively, through named port association. Port names are connected to variables with an equals symbol (=).

1.	Port names must have the format .<port name> on both the left and right sides of in-line references that use named port association.

2.	Named port association is supported only on the right side of an in-line reference. The left side of an in-line reference is always connected to variables by positional port association.

In a parameterized function, the keyword WITH and parameter name list follows the input port list. The list is enclosed in parentheses; parameter names are separated by commas. Only the parameters used by the instance are declared; optional parameter values are separated from parameter names by an equals symbol. In the lpm_add_sub example shown above, the LPM_WIDTH parameter is assigned a value of 8. If no parameter values are assigned in the in-line reference, the Compiler searches for them in parameter value search order.

On the left side of the in-line reference, the outputs of the function are connected to variables. In the compare example shown above, the function’s less and greater outputs are connected to the variables clockwise and counterclockwise, respectively, through positional port association. Similarly, in the lpm_add_sub example, the function’s sum[] outputs are connected through positional port association.

The values of the variables, which are determined elsewhere in the Logic Section, feed the associated inputs and outputs. In the example compare shown above, the values of position[] and target[] feed the inputs of compare. The values of output ports less and greater feed clockwise and counterclockwise, respectively. These variables may be used in other operations in the Logic Section.

See also:

Boolean Equations

Creating & Using Custom Macrofunctions

Creating a Default Include File

Importing & Exporting State Machines

In-Line Macrofunction or Primitive Reference Syntax

Inserting an AHDL Template

Recommended File Structure

Using Altera MAX+PLUS II Unparameterized Macrofunctions

Creating & Using Parameterized Macrofunctions (AHDL) (??? title ??? link)


Truth Table Statement Description (AHDL)
Truth Table Statement

The Truth Table Statement is used to specify combinatorial logic or state machine behavior. In an AHDL truth table, each entry in the table contains a combination of input values that will produce specified output values. These output values can be used as feedback to specify state transitions and outputs of state machines.

Truth tables must follow the rules described in Truth Table Statement Rules.

The following example shows a Truth Table Statement:

TABLE

a0,	f[4..1].q	=>	f[4..1].d,	control;

0,	B"0000"	=>	B"0001",	1;

0,	B"0100"	=>	B"0010",	0;

1,	B"0XXX"	=>	B"0100",	0;

X,	B"1111"	=>	B"0101",	1;

END TABLE;

The Truth Table Statement has the following characteristics:

The truth table heading consists of the keyword TABLE, followed by a comma-separated list of table inputs, an arrow symbol (=>), and a comma-separated list of table outputs. The heading ends with a semicolon (;).

Truth table inputs are Boolean expressions; truth table outputs are variables. In the example shown above, the input signals are a0 and f[4..1].q; the output signals are f[4..1].d and control.

The body of the table consists of one or more entries, each spanning one or more lines and ending with a semicolon.

An entry consists of a comma-separated list of inputs and a comma-separated list of numerical outputs. The inputs and outputs are separated by =>.

Each signal has a one-to-one correspondence with the values in each entry. Thus, the first entry in the example shown above signifies that when a0 has the value 0 and f[4..1].q has the value B"0000", then f[4..1].d will have the value B"0001", and control will have the value 1.

Input and output values can be numbers, predefined constants VCC or GND, symbolic constants (i.e., symbolic names used as constants), or groups of numbers or constants. Input values can also be X (don’t care).

Input and output values correspond to the inputs and outputs of the table heading.

The keywords END TABLE, followed by a semicolon (;), end the truth table.

See also:

Assigning State Machine Bits & Values

Creating Decoders

Inserting an AHDL Template

Recommended File Structure

State Machines with Asynchronous Outputs

State Machines with Synchronous Outputs

Truth Table Statement Rules

Truth Table Statement Syntax


Truth Table Statement Rules (AHDL)
Truth Table Statement Rules

The following rules apply to the Truth Table Statement:

The names in the table heading can be either single nodes or groups.

Every conceivable combination of input values need not be listed. You can use an X (don’t care) to indicate that the output does not depend on the input corresponding to the position of the X. The following example specifies that if a0 is high and f4 is low, the value of the other inputs is not important. Therefore, you can specify the common portion of the input pattern (in this example, 0), then use X characters for the rest of the input pattern (in this example, XXX).

TABLE

a0,	f[4..1].q	=>	f[4..1].d,	control;

0,	B"0000"	=>	B"0001",	1;

0,	B"0100"	=>	B"0010",	0;

1,	B"0XXX"	=>	B"0100",	0;

X,	B"1111"	=>	B"0101",	1;

END TABLE;

The number of comma-separated items in a truth table row must equal the number of comma-separated items in the truth table heading.

The Defaults Statement assigns output values in cases when the actual inputs do not match the input values of the table.

When you use X (don’t care) characters to specify a bit pattern, you must ensure that the pattern cannot assume the value of another bit pattern in the truth table. AHDL assumes that only one condition in a truth table is true at a time; therefore, overlapping bit patterns may cause unpredictable results.

See also:

Assigning State Machine Bits & Values

Creating Decoders

Default Constant Values

Recommended File Structure

State Machines with Asynchronous Outputs

State Machines with Synchronous Outputs

Truth Table Statement Syntax


-----BEGINNING OF NON-TRANSLATED TEXT-----

The following messages in an_msgs.msg are documented elsewhere:

fan_nofile	documented in glmess

ean_pargen_syntax_error	in comess.

fan_pargen_syntax_error	in comess

fan_pargen_fatal_error	documented in comess

EAN_NODE_MISSING_SOURCE	comess

The term "primitive" is deliberately NOT glossarized in this file because the definition is specific to MAX+PLUS II and does not apply to ADFs. Also, links are not present for names of primitives.

-----END OF NON-TRANSLATED TEXT-----


Can’t tie output to <text>

CAUSE:	While reading the Network Section of an Altera Design File, the Compiler encountered a primitive statement that is illegally tied to GND or VCC rather than being connected to logic.

ACTION:	Check the Network Section for primitive statement syntax errors.

See also:

MAX+PLUS II Messages

Message Format


Can’t tie primitive outputs together (node: <name>)

CAUSE:	The Compiler encountered a node in an Altera Design File that is used on the left-hand side of more than one primitive statement.

ACTION:	A node name can be used on the left-hand side of only one primitive statement.

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MAX+PLUS II Messages

Message Format


Duplicate input or output pin name: <name>

CAUSE:	The specified pin name was assigned to more than one input or output pin in an Altera Design File.

ACTION:	Ensure that each pin name is used only once in the Inputs Section. All names in the Outputs Section must also be unique.

 	A bidirectional pin must be declared once in both the Inputs and Outputs sections.

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MAX+PLUS II Messages

Message Format


Ignored buried assignment for <node name>

CAUSE:	You made a pin assignment to a buried node in an Altera Design File. MAX+PLUS II does not support pin assignments on buried nodes in ADFs.

ACTION:	Remove the pin assignment from the ADF and enter the assignment with Pin/Location/Chip (Assign menu).

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MAX+PLUS II Messages

Message Format


Illegal node name character in <node name>

CAUSE:	A node name in an Altera Design File contains a character that is not permitted by MAX+PLUS II software.

ACTION:	Ensure that all node names contain eight or fewer name characters.

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MAX+PLUS II Messages

Message Format


Input/Output pin <name> has two statements in Network Section

CAUSE:	You specified the same input or output pin name in more than one statement in the Network Section of an Altera Design File.

ACTION:	Make sure each input or output pin is specified only once.

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MAX+PLUS II Messages

Message Format


Input pin <name> missing primitive in Network Section

CAUSE:	The specified pin name has been declared in the Inputs Section of an Altera Design File but not assigned to an input primitive (INP) in the Network Section.

ACTION:	Ensure that all pin names declared in the Inputs Sections have a corresponding INP statement in the Network Section of an ADF.

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MAX+PLUS II Messages

Message Format


Mismatched pin assignments for bidirectional pin: <name>

CAUSE:	You have assigned pin numbers in the Inputs Section and the Outputs Section of an Altera Design File that are different. When implementing dual I/O feedback on a bidirectional pin, both pin assignments must be the same.

ACTION:	Ensure that the pin is assigned to the same pin number in both sections.

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MAX+PLUS II Messages

Message Format


Node <name> converted to <node name> (same name as input pin)
Node <name> converted to <node name> [(same name as input pin)]

CAUSE:	In A+PLUS, an output pin can have the same name as a node within the project. In MAX+PLUS II, they must have different names. Therefore, the Compiler has changed a node name to be the same as an input pin name or generated a unique name for a node in an Altera Design File. (The output pin name is not changed.)

ACTION:	No action is required. (Use the new node name when simulating the project.)

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MAX+PLUS II Messages

Message Format


Too many characters in <node/pin> name <name>  (max. = 10)
Node [or pin] name <name> has too many characters (max. = 10)

CAUSE:	The specified node or pin name contains more than 10 characters, which is the maximum allowed for a node or pin name in an Altera Design File.

ACTION:	Change the name or shorten it.

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MAX+PLUS II Messages

Message Format


Output Enable input to <primitive name> is VCC ­ converted primitive to <primitive name>
Output Enable input to <primitive name> is VCC -- converted primitive to <primitive name>

CAUSE:	The Output Enable input to the specified COIF, ROIF, or TOIF primitive in an Altera Design File is set to VCC, so the Compiler has changed the primitive to the more architecture-efficient COCF, RORF, or TOTF primitive, respectively.

ACTION:	No action is required.

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MAX+PLUS II Messages

Message Format


Output pin <name> missing primitive in Network Section

CAUSE:	The specified output pin name has been declared in the Outputs Section of an Altera Design File but not assigned to a primitive in the Network Section.

ACTION:	Ensure that all pin names declared in the Outputs Section are also used in the Network Section of the ADF.

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MAX+PLUS II Messages

Message Format


Periods (.) in node names have been converted to underscores (_)

CAUSE:	Internal node names in A+PLUS contain periods (.). Since periods are not legal name characters in MAX+PLUS II design files, the Compiler has converted the periods in these names into underscores (_).

ACTION:	No action is required. Use the new node names when editing the symbol for the design file or simulating the project.

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Altera Design File (.adf)

MAX+PLUS II Messages

Message Format

State Machine File (.smf)


Pin name truncated to <name>

CAUSE:	An Altera Design File contained a pin name that the Compiler expanded to more than 31 characters, which is the maximum permitted when A+PLUS-generated ADFs are converted. This message may occur if pin names in your ADF contain characters that are permitted in A+PLUS but not in MAX+PLUS II; such characters are converted to ~#~, where # represents an integer.

ACTION:	Use pin names that contain only eight of the following characters A-Z, a-z, 0-9, and _ (underscore). Alternatively, you may use the truncated pin name during the remainder of compilation and simulation.

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MAX+PLUS II Messages

Message Format


Too many inputs to logic primitive

CAUSE:	You have entered more than 12 inputs to a logic primitive in an Altera Design File or State Machine File.

ACTION:	You may use any number between 2 and 12 inputs for AND, NAND, NOR, and OR primitives. NOT gates must have only 1 input; XOR and XNOR gates must have exactly 2 inputs.

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MAX+PLUS II Messages

Message Format


Too many/few inputs on right-hand side of primitive statement
Too many or few inputs on right-hand side of primitive statement

CAUSE:	You have entered too many/few of the input parameters required on the right-hand side of a primitive statement in an Altera Design File. This message may occur if you intended to use some default values but have too many/few of the commas that are required to delimit the fields.

ACTION:	Check the Network Section for errors.

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MAX+PLUS II Messages

Message Format


Too many/few signals on left-hand side of primitive statement
Too many or few signals on left-hand side of primitive statement

CAUSE:	You have entered more signal names on the left-hand side of a primitive statement in an Altera Design File than the primitive supports.

ACTION:	Check the Network Section for errors.

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MAX+PLUS II Messages

Message Format


Undeclared input or output pin name <name>

CAUSE:	The input (output) node associated with an INPUT (I/O) primitive in the Network Section of an Altera Design File was not declared in the Inputs (Outputs) Section of the file. This message may occur if you have forgotten to name the pin.)

ACTION:	Declare all input (output) pin names in the Inputs (Outputs) Section of the ADF.

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MAX+PLUS II Messages

Message Format